From nobody Sat May 18 06:50:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=ilande.co.uk Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1713556388283656.041672225921; Fri, 19 Apr 2024 12:53:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rxuHG-0004U5-Nb; Fri, 19 Apr 2024 15:52:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rxuHF-0004Tb-0e for qemu-devel@nongnu.org; Fri, 19 Apr 2024 15:52:05 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rxuHA-0004q4-Lp for qemu-devel@nongnu.org; Fri, 19 Apr 2024 15:52:04 -0400 Received: from [2a00:23c4:8bb4:4000:a36d:d178:601a:c356] (helo=localhost.localdomain) by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1rxuG3-00050p-7H; Fri, 19 Apr 2024 20:50:55 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ilande.co.uk; s=20220518; h=Subject:Content-Transfer-Encoding:MIME-Version: Message-Id:Date:To:From:Sender:Reply-To:Cc:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=ORrWk6OZBCnrD3OWSoi1f9pNjLtL8H1wx40T95LWl4Q=; b=1goBwYmGmEpxUAOzeAAyVaSUGS Hclesiz4r7Owp2ndb0RGXzA1cqUzIz6Xv7OvRmngvJhVGEMymV/Hw+xB/gCThGtHNzXkqyQO/O6R8 u9/8J7T5AnQsYScfip8dZYBqarPbyKZQhNUZkilENZ6IGHT3vf95/Tu2jUg2C1Yg9kFCY38RsV6qN m9IAS2DViTtdXWmI5ePPOTfrC1ABOjb+a7ppxzKazHtEz2+YIecw4xTVkmgwyrEayHSKa0rWGwIrp 93HxbZu3cTwfIdkfoiRXkaP+m/Bss3RYguwolwbjmjzzVbDkNATJPod7q2eU93WBfw6jzA4+g7q5r lxe3oJqZMIQw3qMYoOpYdt51Bmim9YG069Pq1RDYLkzJ/IayDkNMXgkPpjtxTt7aLUaG5eRYup9nQ ZlYLs7D250HFIA4LwKlY3gosea2scIi3zWIjPK95/KY1by//EGLjowc9VKPz1KSjSbinWNEDgDh0H KV5rr8aW2RhOQby4AJnrNwZc8C8owrrtA3lC/aCe6B9f1pmFWsHA20RY7VDWOoOlKAe49fU9jRumY 8qBN2+CJD+9/pAEXa9wFKyGG39I7faeulnxhz76BwRm0IzRMoD8rzW+MMgOhzUlVtZmhmcHqY2Oxa ARWvqs6qE1PlC//19Wb9eUIWVqr2ouYMd0MmF5qnE=; From: Mark Cave-Ayland To: pbonzini@redhat.com, richard.henderson@linaro.org, eduardo@habkost.net, qemu-devel@nongnu.org Date: Fri, 19 Apr 2024 20:51:47 +0100 Message-Id: <20240419195147.434894-1-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a00:23c4:8bb4:4000:a36d:d178:601a:c356 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH] target/i386/translate.c: always write 32-bits for SGDT and SIDT X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1713556390125100002 Content-Type: text/plain; charset="utf-8" The various Intel CPU manuals claim that SGDT and SIDT can write either 24-= bits or 32-bits depending upon the operand size, but this is incorrect. Not only= do the Intel CPU manuals give contradictory information between processor revisions, but this information doesn't even match real-life behaviour. In fact, tests on real hardware show that the CPU always writes 32-bits for= SGDT and SIDT, and this behaviour is required for at least OS/2 Warp and WFW 3.1= 1 with Win32s to function correctly. Remove the masking applied due to the operand= size for SGDT and SIDT so that the TCG behaviour matches the behaviour on real hardware. Signed-off-by: Mark Cave-Ayland Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2198 -- MCA: Whilst I don't have a copy of OS/2 Warp handy, I've confirmed that this patch fixes the issue in WFW 3.11 with Win32s. For more technical informati= on I highly recommend the excellent write-up at https://www.os2museum.com/wp/sgdtsidt-fiction-and-reality/. Reviewed-by: Richard Henderson --- target/i386/tcg/translate.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 76a42c679c..3026eb6774 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -5846,9 +5846,10 @@ static bool disas_insn(DisasContext *s, CPUState *cp= u) gen_op_st_v(s, MO_16, s->T0, s->A0); gen_add_A0_im(s, 2); tcg_gen_ld_tl(s->T0, tcg_env, offsetof(CPUX86State, gdt.base)); - if (dflag =3D=3D MO_16) { - tcg_gen_andi_tl(s->T0, s->T0, 0xffffff); - } + /* + * NB: Despite claims to the contrary in Intel CPU documentati= on, + * all 32-bits are written regardless of operand size. + */ gen_op_st_v(s, CODE64(s) + MO_32, s->T0, s->A0); break; =20 @@ -5901,9 +5902,10 @@ static bool disas_insn(DisasContext *s, CPUState *cp= u) gen_op_st_v(s, MO_16, s->T0, s->A0); gen_add_A0_im(s, 2); tcg_gen_ld_tl(s->T0, tcg_env, offsetof(CPUX86State, idt.base)); - if (dflag =3D=3D MO_16) { - tcg_gen_andi_tl(s->T0, s->T0, 0xffffff); - } + /* + * NB: Despite claims to the contrary in Intel CPU documentati= on, + * all 32-bits are written regardless of operand size. + */ gen_op_st_v(s, CODE64(s) + MO_32, s->T0, s->A0); break; =20 --=20 2.39.2