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bh=Bp3oHnePKhWq2QoakUNtEuAtVReIW674eSBPqyAvHNk=; b=UloekG+sRi9PDxnFsoeZVhAB8VoYf5p9qceL8TBfWEoWr2jFN6L0S4RES12Eu5w568zavt hcm7fEwfjQ5jvTGvP7nASfIYULPcDsouekZ8ux8mzTEkiZwOX8qrhghj6VjGb53fAJwwSb 5GLjdR6eKYFyli+rFzDOz7Sm2F84UF4= X-MC-Unique: tf9drnTdOyWWaLdCrnQfPw-1 From: Thomas Huth To: qemu-devel@nongnu.org, Artyom Tarasenko , Mark Cave-Ayland Cc: Eduardo Habkost , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Paolo Bonzini , Markus Armbruster Subject: [PATCH v2 1/4] target/sparc/cpu: Rename the CPU models with a "+" in their names Date: Fri, 19 Apr 2024 10:48:09 +0200 Message-ID: <20240419084812.504779-2-thuth@redhat.com> In-Reply-To: <20240419084812.504779-1-thuth@redhat.com> References: <20240419084812.504779-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.067, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1713516594256100001 Content-Type: text/plain; charset="utf-8" Commit b447378e12 ("qom/object: Limit type names to alphanumerical ...") cut down the amount of allowed characters for QOM types to a saner set. The "+" character was meant to be included in this set, so we had to add a hack there to still allow the legacy names of POWER and Sparc64 CPUs. However, instead of putting such a hack in the common QOM code, there is a much better place to do this: The sparc_cpu_class_by_name() function which is used to look up the names of all Sparc CPUs. Thus let's finally get rid of the "+" in the Sparc CPU names, and provide backward compatibility for the old names via some simple checks in the sparc_cpu_class_by_name() function. Reviewed-by: Mark Cave-Ayland Signed-off-by: Thomas Huth Reviewed-by: Richard Henderson --- qom/object.c | 8 -------- target/sparc/cpu.c | 14 ++++++++++++-- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/qom/object.c b/qom/object.c index d4a001cf41..759e194972 100644 --- a/qom/object.c +++ b/qom/object.c @@ -158,14 +158,6 @@ static bool type_name_is_valid(const char *name) "ABCDEFGHIJKLMNOPQRSTUVWXYZ" "0123456789-_."); =20 - /* Allow some legacy names with '+' in it for compatibility reasons */ - if (name[plen] =3D=3D '+') { - if (plen >=3D 17 && g_str_has_prefix(name, "Sun-UltraSparc-I")) { - /* Allow "Sun-UltraSparc-IV+" and "Sun-UltraSparc-IIIi+" */ - return true; - } - } - return plen =3D=3D slen; } =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index e820f50acf..774e234e09 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -314,7 +314,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Sun UltraSparc IV+", + .name =3D "Sun UltraSparc IV plus", .iu_version =3D ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -323,7 +323,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, }, { - .name =3D "Sun UltraSparc IIIi+", + .name =3D "Sun UltraSparc IIIi plus", .iu_version =3D ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_3, @@ -762,6 +762,16 @@ static ObjectClass *sparc_cpu_class_by_name(const char= *cpu_model) char *typename; =20 typename =3D sparc_cpu_type_name(cpu_model); + + /* Fix up legacy names with '+' in it */ + if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV+"))) { + g_free(typename); + typename =3D g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV-plus"= )); + } else if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-I= IIi+"))) { + g_free(typename); + typename =3D g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi-plu= s")); + } + oc =3D object_class_by_name(typename); g_free(typename); return oc; --=20 2.44.0 From nobody Sat May 18 06:50:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1713516753; cv=none; d=zohomail.com; s=zohoarc; b=E9glvLVGRVemndW6/65MLleJBRkGovfuSXUtbX1jZo7L2WJ0Nk/knR84dnzw6pxeMjj/pEbJbX3lufz6KqOCKN+sBqEZjo8EQXIMKBwq5TPPwU/uJWthXZr5abmaF4ot/L8Hde1RWqhSIdCEZl8GpAlJ7WI/TVcTwOq7sXyh57k= ARC-Message-Signature: i=1; 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Fri, 19 Apr 2024 08:48:20 +0000 (UTC) Received: from thuth-p1g4.redhat.com (unknown [10.39.194.170]) by smtp.corp.redhat.com (Postfix) with ESMTP id 922591121306; Fri, 19 Apr 2024 08:48:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1713516726; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LEurQWwIj1ae0zpFiHYFzGSS3+PXFjNqJBQ/9xpNOOI=; b=cN5agRlkrKrc1+rvocQ0YLKrgr7BpWfTYgbTQ1mTou46WpBDGSseAfBQhyvSusa1YUI4LY I1Ye4qqy3++5cDSiuYv7lPYHDQ0HGy25Jl8NiMCK43zX6GLhHfSl43Go8V4geQz+/CIQhm jHASWlqm8C6GYWiGKCBBQF9G5eQoT9A= X-MC-Unique: eiDEitBkMke1VTFcydvbtA-1 From: Thomas Huth To: qemu-devel@nongnu.org, Artyom Tarasenko , Mark Cave-Ayland Cc: Eduardo Habkost , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Paolo Bonzini , Markus Armbruster Subject: [PATCH v2 2/4] target/sparc/cpu: Avoid spaces by default in the CPU names Date: Fri, 19 Apr 2024 10:48:10 +0200 Message-ID: <20240419084812.504779-3-thuth@redhat.com> In-Reply-To: <20240419084812.504779-1-thuth@redhat.com> References: <20240419084812.504779-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.067, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1713516755029100003 Content-Type: text/plain; charset="utf-8" The output of "-cpu help" is currently rather confusing to the users: It might not be fully clear which part of the output defines the CPU names since the CPU names contain white spaces (which we later have to convert into dashes internally). At best it's at least a nuisance since the users might need to specify the CPU names with quoting on the command line if they are not aware of the fact that the CPU names could be written with dashes instead. So let's finally clean up this mess by using dashes instead of white spaces for the CPU names, like we're doing it internally later (and like we're doing it in most other targets of QEMU). Note that it is still possible to pass the CPU names with spaces to the "-cpu" option, since sparc_cpu_type_name() still translates those to "-". Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2141 Reviewed-by: Richard Henderson Reviewed-by: Mark Cave-Ayland Signed-off-by: Thomas Huth --- target/sparc/cpu.c | 56 +++++++++++++++++++++++----------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 774e234e09..593c8d6867 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -206,7 +206,7 @@ void cpu_sparc_set_id(CPUSPARCState *env, unsigned int = cpu) static const sparc_def_t sparc_defs[] =3D { #ifdef TARGET_SPARC64 { - .name =3D "Fujitsu Sparc64", + .name =3D "Fujitsu-Sparc64", .iu_version =3D ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -215,7 +215,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Fujitsu Sparc64 III", + .name =3D "Fujitsu-Sparc64-III", .iu_version =3D ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -224,7 +224,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Fujitsu Sparc64 IV", + .name =3D "Fujitsu-Sparc64-IV", .iu_version =3D ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -233,7 +233,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Fujitsu Sparc64 V", + .name =3D "Fujitsu-Sparc64-V", .iu_version =3D ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -242,7 +242,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI UltraSparc I", + .name =3D "TI-UltraSparc-I", .iu_version =3D ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -251,7 +251,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI UltraSparc II", + .name =3D "TI-UltraSparc-II", .iu_version =3D ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -260,7 +260,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI UltraSparc IIi", + .name =3D "TI-UltraSparc-IIi", .iu_version =3D ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -269,7 +269,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI UltraSparc IIe", + .name =3D "TI-UltraSparc-IIe", .iu_version =3D ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -278,7 +278,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Sun UltraSparc III", + .name =3D "Sun-UltraSparc-III", .iu_version =3D ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -287,7 +287,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Sun UltraSparc III Cu", + .name =3D "Sun-UltraSparc-III-Cu", .iu_version =3D ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_3, @@ -296,7 +296,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Sun UltraSparc IIIi", + .name =3D "Sun-UltraSparc-IIIi", .iu_version =3D ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -305,7 +305,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Sun UltraSparc IV", + .name =3D "Sun-UltraSparc-IV", .iu_version =3D ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_4, @@ -314,7 +314,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Sun UltraSparc IV plus", + .name =3D "Sun-UltraSparc-IV-plus", .iu_version =3D ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -323,7 +323,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, }, { - .name =3D "Sun UltraSparc IIIi plus", + .name =3D "Sun-UltraSparc-IIIi-plus", .iu_version =3D ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_3, @@ -332,7 +332,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Sun UltraSparc T1", + .name =3D "Sun-UltraSparc-T1", /* defined in sparc_ifu_fdp.v and ctu.h */ .iu_version =3D ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 2= 4)), .fpu_version =3D 0x00000000, @@ -343,7 +343,7 @@ static const sparc_def_t sparc_defs[] =3D { | CPU_FEATURE_GL, }, { - .name =3D "Sun UltraSparc T2", + .name =3D "Sun-UltraSparc-T2", /* defined in tlu_asi_ctl.v and n2_revid_cust.v */ .iu_version =3D ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 2= 4)), .fpu_version =3D 0x00000000, @@ -354,7 +354,7 @@ static const sparc_def_t sparc_defs[] =3D { | CPU_FEATURE_GL, }, { - .name =3D "NEC UltraSparc I", + .name =3D "NEC-UltraSparc-I", .iu_version =3D ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 2= 4)), .fpu_version =3D 0x00000000, .mmu_version =3D mmu_us_12, @@ -364,7 +364,7 @@ static const sparc_def_t sparc_defs[] =3D { }, #else { - .name =3D "Fujitsu MB86904", + .name =3D "Fujitsu-MB86904", .iu_version =3D 0x04 << 24, /* Impl 0, ver 4 */ .fpu_version =3D 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ .mmu_version =3D 0x04 << 24, /* Impl 0, ver 4 */ @@ -377,7 +377,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "Fujitsu MB86907", + .name =3D "Fujitsu-MB86907", .iu_version =3D 0x05 << 24, /* Impl 0, ver 5 */ .fpu_version =3D 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */ .mmu_version =3D 0x05 << 24, /* Impl 0, ver 5 */ @@ -390,7 +390,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI MicroSparc I", + .name =3D "TI-MicroSparc-I", .iu_version =3D 0x41000000, .fpu_version =3D 4 << FSR_VER_SHIFT, .mmu_version =3D 0x41000000, @@ -403,7 +403,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_FEATURE_MUL | CPU_FEATURE_DIV, }, { - .name =3D "TI MicroSparc II", + .name =3D "TI-MicroSparc-II", .iu_version =3D 0x42000000, .fpu_version =3D 4 << FSR_VER_SHIFT, .mmu_version =3D 0x02000000, @@ -416,7 +416,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI MicroSparc IIep", + .name =3D "TI-MicroSparc-IIep", .iu_version =3D 0x42000000, .fpu_version =3D 4 << FSR_VER_SHIFT, .mmu_version =3D 0x04000000, @@ -429,7 +429,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI SuperSparc 40", /* STP1020NPGA */ + .name =3D "TI-SuperSparc-40", /* STP1020NPGA */ .iu_version =3D 0x41000000, /* SuperSPARC 2.x */ .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x00000800, /* SuperSPARC 2.x, no MXCC */ @@ -442,7 +442,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI SuperSparc 50", /* STP1020PGA */ + .name =3D "TI-SuperSparc-50", /* STP1020PGA */ .iu_version =3D 0x40000000, /* SuperSPARC 3.x */ .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x01000800, /* SuperSPARC 3.x, no MXCC */ @@ -455,7 +455,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI SuperSparc 51", + .name =3D "TI-SuperSparc-51", .iu_version =3D 0x40000000, /* SuperSPARC 3.x */ .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x01000000, /* SuperSPARC 3.x, MXCC */ @@ -469,7 +469,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI SuperSparc 60", /* STP1020APGA */ + .name =3D "TI-SuperSparc-60", /* STP1020APGA */ .iu_version =3D 0x40000000, /* SuperSPARC 3.x */ .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x01000800, /* SuperSPARC 3.x, no MXCC */ @@ -482,7 +482,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI SuperSparc 61", + .name =3D "TI-SuperSparc-61", .iu_version =3D 0x44000000, /* SuperSPARC 3.x */ .fpu_version =3D 0 << FSR_VER_SHIFT, .mmu_version =3D 0x01000000, /* SuperSPARC 3.x, MXCC */ @@ -496,7 +496,7 @@ static const sparc_def_t sparc_defs[] =3D { .features =3D CPU_DEFAULT_FEATURES, }, { - .name =3D "TI SuperSparc II", + .name =3D "TI-SuperSparc-II", .iu_version =3D 0x40000000, /* SuperSPARC II 1.x */ .fpu_version =3D 0 << FSR_VER_SHIFT, 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<20240419084812.504779-4-thuth@redhat.com> In-Reply-To: <20240419084812.504779-1-thuth@redhat.com> References: <20240419084812.504779-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.067, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1713516568243100009 Content-Type: text/plain; charset="utf-8" Add some words about how to enable or disable boolean features, and remove the note about a Linux kernel being available on the QEMU website (they have been removed long ago already), and the note about NetBSD and OpenBSD still having issues (they should work fine nowadays). Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2141 Signed-off-by: Thomas Huth Reviewed-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- docs/system/target-sparc.rst | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/docs/system/target-sparc.rst b/docs/system/target-sparc.rst index 9ec8c90c14..54bd8b6ead 100644 --- a/docs/system/target-sparc.rst +++ b/docs/system/target-sparc.rst @@ -27,6 +27,11 @@ architecture machines: The emulation is somewhat complete. SMP up to 16 CPUs is supported, but Linux limits the number of usable CPUs to 4. =20 +The list of available CPUs can be viewed by starting QEMU with ``-cpu help= ``. +Optional boolean features can be added with a "+" in front of the feature = name, +or disabled with a "-" in front of the name, for example +``-cpu TI-SuperSparc-II,+float128``. + QEMU emulates the following sun4m peripherals: =20 - IOMMU @@ -55,8 +60,5 @@ OpenBIOS is a free (GPL v2) portable firmware implementat= ion. The goal is to implement a 100% IEEE 1275-1994 (referred to as Open Firmware) compliant firmware. =20 -A sample Linux 2.6 series kernel and ram disk image are available on the -QEMU web site. There are still issues with NetBSD and OpenBSD, but most -kernel versions work. Please note that currently older Solaris kernels -don't work probably due to interface issues between OpenBIOS and -Solaris. +Please note that currently older Solaris kernels don't work probably due +to interface issues between OpenBIOS and Solaris. --=20 2.44.0 From nobody Sat May 18 06:50:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1713516566; cv=none; d=zohomail.com; s=zohoarc; b=iXjKeMPdNTS8w7ACRg/ZjOAXDSyo5ponBP+QwJ3kTHynj/kIDqUcJqMoAwVrQy31R6CYzX/MEPTY1z+m+D69WxXjIkj3R4PuOU8HZS9Fu1xSCOuha+dxQ1XIdkKWLwQZwmy501YWetZ3S9slkAvGp9sTR7/Xj9UVL8cEULYyUc4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1713516566; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Fri, 19 Apr 2024 08:48:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1713516509; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2kHEYBckbAZWVsxVOv9Z20aD6o0POU9kFay7g0bMsXY=; b=EXSCnurc/4GYCaBYl8j96vtkiHbsRBRXkehGGdU5onfmSsxmsWxW0oOP9qo8yxcrs73uCY X9/1zovHEdZ+oMYS9ddF8Yd0vBpOv5qKpfvyWKpim7T3jAg5SVwKck2QAph7/p4znEn0FW gqV+hzDqRW+2Ks5pQONAbi9dRW2tHMQ= X-MC-Unique: k_ExXMzVMBSZH_x6cekDsw-1 From: Thomas Huth To: qemu-devel@nongnu.org, Artyom Tarasenko , Mark Cave-Ayland Cc: Eduardo Habkost , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Paolo Bonzini , Markus Armbruster Subject: [PATCH v2 4/4] docs/about: Deprecate the old "UltraSparc" CPU names that contain a "+" Date: Fri, 19 Apr 2024 10:48:12 +0200 Message-ID: <20240419084812.504779-5-thuth@redhat.com> In-Reply-To: <20240419084812.504779-1-thuth@redhat.com> References: <20240419084812.504779-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.067, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1713516568238100008 Content-Type: text/plain; charset="utf-8" For consistency we should drop the names with a "+" in it in the long run. Reviewed-by: Mark Cave-Ayland Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- docs/about/deprecated.rst | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 6b932961bc..70026c3c11 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -206,6 +206,15 @@ in the QEMU object model anymore. ``power5+``, ``power= 5+_v2.1``, an alias, but for consistency these will get removed in a future release, too. Use ``power5p_v2.1`` and ``power7p_v2.1`` instead. =20 +``Sun-UltraSparc-IIIi+`` and ``Sun-UltraSparc-IV+`` CPU names (since 9.1) +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +The character "+" in device (and thus also CPU) names is not allowed +in the QEMU object model anymore. ``Sun-UltraSparc-IIIi+`` and +``Sun-UltraSparc-IV+`` are currently still supported via a workaround, +but for consistency these will get removed in a future release, too. +Use ``Sun-UltraSparc-IIIi-plus`` and ``Sun-UltraSparc-IV-plus`` instead. + CRIS CPU architecture (since 9.0) ''''''''''''''''''''''''''''''''' =20 --=20 2.44.0