target/riscv: set (m|s)tval on

[PATCH for-9.1 v2 0/2] target/riscv: set (m|s)tval on

Daniel Henrique Barboza posted 2 patches 1 week, 6 days ago

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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20240416194132.1843699-1-dbarboza@ventanamicro.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/cpu_helper.c                      | 1 +
target/riscv/debug.c                           | 3 +++
target/riscv/insn_trans/trans_privileged.c.inc | 4 ++++
3 files changed, 8 insertions(+)

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[PATCH for-9.1 v2 0/2] target/riscv: set (m|s)tval on

Posted by Daniel Henrique Barboza 1 week, 6 days ago

Hi,

This is a re-send of the patch sent as a 9.0 bugfix in [1], now reframed
as a non-bug fix chabge,

A new patch (2) was added to handle a similar scenario with ebreak and tval.

Changes from v1:
- patch 1:
  - rewrite commit msg to make it clear that this is a non-bug
    fix change
- new patch (2):
  -  set mtval/stval during ebreak
- v1 link: https://lore.kernel.org/qemu-riscv/20240320093221.220854-1-dbarboza@ventanamicro.com/

Daniel Henrique Barboza (2):
  target/riscv/debug: set tval=pc in breakpoint exceptions
  trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint

 target/riscv/cpu_helper.c                      | 1 +
 target/riscv/debug.c                           | 3 +++
 target/riscv/insn_trans/trans_privileged.c.inc | 4 ++++
 3 files changed, 8 insertions(+)

-- 
2.44.0