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Mon, 15 Apr 2024 14:50:11 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pku.edu.cn; s=dkim; h=Received:From:To:Cc:Subject:Date: Message-ID:MIME-Version:Content-Transfer-Encoding; bh=J7nmHWbIgf Oam3kaQDyRbozkPA763qUZT/BorRoWyHY=; b=eC6r9kvD09qzANDGF9BPS0UjIg 09NmWw+bv7XOAgPOI6lJvxu+vm7DhcwZJUBBCVubSpret/Nh+NxpzT8gpBH0UzXd /p8fS50SK4H/YvQVRxYTVQRVsCtKAXfSOErjzTx1NWCo1+MrsRKuMgz2xkN84Uqv 69lpN9ph40KSuBA8I= From: Ruihan Li To: qemu-devel@nongnu.org Cc: Ruihan Li , Eduardo Habkost , Paolo Bonzini , Richard Henderson Subject: [PATCH v2] target/i386: Give IRQs a chance when resetting HF_INHIBIT_IRQ_MASK Date: Mon, 15 Apr 2024 14:45:21 +0800 Message-ID: <20240415064518.4951-4-lrh2000@pku.edu.cn> X-Mailer: git-send-email 2.44.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: 5oFpogCHK+EfzhxmpwhiAw--.11576S2 X-Coremail-Antispam: 1UD129KBjvJXoWxJw1UAr1kurWrZFy7CrWxJFb_yoW5WF1xpa 1xCwnFyr4kXF4UGa1xJa1DWFyYyF4rtr1j9Fn7tw4rK3yrKr9YqFn3KFW5KFW5WF4xuFyY vr10yFyj9F98XaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUB21xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s1l1IIY67AE w4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xvwVC0I7IYx2 IY67AKxVWDJVCq3wA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWxJr0_GcWl84ACjcxK6I8E 87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1lnxkEFVAIw20F6c xK64vIFxWle2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2Wl Yx0E2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbV WUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc7CjxVAaw2AF wI0_JF0_Jw1lc2xSY4AK67AK6r47MxAIw28IcxkI7VAKI48JMxAIw28IcVCjz48v1sIEY2 0_Kw1UJr1UMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2Iq xVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42 IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY 6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aV CY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfU8KZXUUUUU X-CM-SenderInfo: yssqiiarrvmko6sn3hxhgxhubq/1tbiAgEHBWYavlcgnwADso Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=159.65.134.6; envelope-from=lrh2000@pku.edu.cn; helo=zg8tmtu5ljy1ljeznc42.icoremail.net X-Spam_score_int: 17 X-Spam_score: 1.7 X-Spam_bar: + X-Spam_report: (1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_BL=0.01, RCVD_IN_MSPIKE_L5=2.5, RCVD_IN_VALIDITY_RPBL=1.31, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @pku.edu.cn) X-ZM-MESSAGEID: 1713163879040100001 Content-Type: text/plain; charset="utf-8" When emulated with QEMU, interrupts will never come in the following loop. However, if the NOP instruction is uncommented, interrupts will fire as normal. loop: cli call do_sti jmp loop do_sti: sti # nop ret This behavior is different from that of a real processor. For example, if KVM is enabled, interrupts will always fire regardless of whether the NOP instruction is commented or not. Also, the Intel Software Developer Manual states that after the STI instruction is executed, the interrupt inhibit should end as soon as the next instruction (e.g., the RET instruction if the NOP instruction is commented) is executed. This problem is caused because the previous code may choose not to end the TB even if the HF_INHIBIT_IRQ_MASK has just been reset (e.g., in the case where the STI instruction is immediately followed by the RET instruction), so that IRQs may not have a change to trigger. This commit fixes the problem by always terminating the current TB to give IRQs a chance to trigger when HF_INHIBIT_IRQ_MASK is reset. Reviewed-by: Richard Henderson Signed-off-by: Ruihan Li --- The same problem was discovered two years ago, see [StackOverflow][so]. [so]: https://stackoverflow.com/questions/68135305/executing-ret-after-sti= -doesnt-start-interrupts Changes since v1: - Fix a typo: "RET is followed by STI" -> "STI is followed by RET" Link to v1: - https://lore.kernel.org/qemu-devel/20231210190147.129734-2-lrh2000@pku.e= du.cn/ target/i386/tcg/translate.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 76a42c6..3f0fbdf 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2798,13 +2798,19 @@ static void gen_bnd_jmp(DisasContext *s) static void do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr) { + bool inhibit_reset; + gen_update_cc_op(s); =20 /* If several instructions disable interrupts, only the first does it.= */ if (inhibit && !(s->flags & HF_INHIBIT_IRQ_MASK)) { gen_set_hflag(s, HF_INHIBIT_IRQ_MASK); - } else { + inhibit_reset =3D false; + } else if (!inhibit && (s->flags & HF_INHIBIT_IRQ_MASK)) { gen_reset_hflag(s, HF_INHIBIT_IRQ_MASK); + inhibit_reset =3D true; + } else { + inhibit_reset =3D false; } =20 if (s->base.tb->flags & HF_RF_MASK) { @@ -2815,7 +2821,9 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool= recheck_tf, bool jr) tcg_gen_exit_tb(NULL, 0); } else if (s->flags & HF_TF_MASK) { gen_helper_single_step(tcg_env); - } else if (jr) { + } else if (jr && + /* give irqs a chance to happen */ + !inhibit_reset) { tcg_gen_lookup_and_goto_ptr(); } else { tcg_gen_exit_tb(NULL, 0); --=20 2.44.0