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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id v19-20020a17090abb9300b002a0544b81d6sm3564074pjr.35.2024.04.12.22.23.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Apr 2024 22:23:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712985818; x=1713590618; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HtyEz9ZqG6bUxigt3H0a/+KeCYzNX8VAHbBRr96gz24=; b=GQ65+x5VKwIDuurB3w7tNV+yQn5ws/8Q9EImJOLNLJu5uteHb34VtdKIgnppaTgtgN K/aePfNTysAbXy969wj0l8fts2CEgo0nBdw5LD/9d8ezbpH3mkPDwcKmFMiB3J9ZacpJ Xmo/tJ5JYbIkoSgswdWNSRhry/yFD4Eqqa2Fy/zAar5zbzbsTrYu8TYLzZLJ/A9mAV2a ZsW2gQ22YqMRXhUQXLPj4gvXAdFT4pdi0D67c1mtydvhLB0bKsr42DX6OMsLyWLmOktF T378Jx8Q85WSOwidtfvchm27mCUHA+ASyPDnbLlATrkH+54BgoStYdXadT7eGRMVUZ5z u2TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712985818; x=1713590618; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HtyEz9ZqG6bUxigt3H0a/+KeCYzNX8VAHbBRr96gz24=; b=fL9gzcQDtTTp7FtDEuEmJZGQh+uFA0QBTtdCgaFePAnt89it+Y2iVRD4g7b1ffqa3l NBBmWV/58rzHLGgdywP/OrFDgPmvL+463FKGHT2amkmG3EHzFoiixCh9Ih9CaQprtLW8 KLiEBXNXwOR80NCNCbqmG57RgdHlWnfF1O1RoR1Meft27eIh3trhTKWVMH/tggw6us5d 9WTqc4D28Q4spbCQEEBndcCweKJtE6FkrC6nRYLy9afu7QyQEexbhqOWi4LHVirF6Ml1 k6EnmcyZ1HHMD52SLp/dgv3QPofXc9h/EwiruPUDS/tHW7+5UU/PZZ3J4AXEvVnp8fu+ xMIw== X-Gm-Message-State: AOJu0Yw0lCIcRGb4se7YbPg5/EWHPHwm3Cb3WGXGQdGCHyODjDKStxsT 48cLCVwsmqG24z+cSB5SuMittLz28MSbbuof8IyprNETikOOujvtSb4qACT0CLEncCKsDynKEmU F X-Google-Smtp-Source: AGHT+IGJt/F5qCX8Yh+EjuxwDoKDKdD3PJ1JDURTAnRgj18sQilOYTd09i1mOcqK410DI6RCyxYRQA== X-Received: by 2002:a05:6358:690f:b0:186:3ae:e138 with SMTP id d15-20020a056358690f00b0018603aee138mr5060841rwh.25.1712985817107; Fri, 12 Apr 2024 22:23:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, philmd@linaro.org Subject: [PATCH 1/6] disas/cris: Untabify Date: Fri, 12 Apr 2024 22:23:28 -0700 Message-Id: <20240413052333.688151-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240413052333.688151-1-richard.henderson@linaro.org> References: <20240413052333.688151-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2a; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1712985932523100025 Content-Type: text/plain; charset="utf-8" Nothing but whitespace changes. Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias --- disas/cris.c | 2266 +++++++++++++++++++++++++------------------------- 1 file changed, 1133 insertions(+), 1133 deletions(-) diff --git a/disas/cris.c b/disas/cris.c index 409a224c5d..d62f9e3264 100644 --- a/disas/cris.c +++ b/disas/cris.c @@ -53,64 +53,64 @@ along with this program; if not, see . */ const struct cris_spec_reg cris_spec_regs[] =3D { - {"bz", 0, 1, cris_ver_v32p, NULL}, - {"p0", 0, 1, 0, NULL}, - {"vr", 1, 1, 0, NULL}, - {"p1", 1, 1, 0, NULL}, + {"bz", 0, 1, cris_ver_v32p, NULL}, + {"p0", 0, 1, 0, NULL}, + {"vr", 1, 1, 0, NULL}, + {"p1", 1, 1, 0, NULL}, {"pid", 2, 1, cris_ver_v32p, NULL}, - {"p2", 2, 1, cris_ver_v32p, NULL}, + {"p2", 2, 1, cris_ver_v32p, NULL}, {"p2", 2, 1, cris_ver_warning, NULL}, {"srs", 3, 1, cris_ver_v32p, NULL}, - {"p3", 3, 1, cris_ver_v32p, NULL}, + {"p3", 3, 1, cris_ver_v32p, NULL}, {"p3", 3, 1, cris_ver_warning, NULL}, - {"wz", 4, 2, cris_ver_v32p, NULL}, - {"p4", 4, 2, 0, NULL}, + {"wz", 4, 2, cris_ver_v32p, NULL}, + {"p4", 4, 2, 0, NULL}, {"ccr", 5, 2, cris_ver_v0_10, NULL}, - {"exs", 5, 4, cris_ver_v32p, NULL}, + {"exs", 5, 4, cris_ver_v32p, NULL}, {"p5", 5, 2, cris_ver_v0_10, NULL}, - {"p5", 5, 4, cris_ver_v32p, NULL}, - {"dcr0",6, 2, cris_ver_v0_3, NULL}, - {"eda", 6, 4, cris_ver_v32p, NULL}, - {"p6", 6, 2, cris_ver_v0_3, NULL}, - {"p6", 6, 4, cris_ver_v32p, NULL}, + {"p5", 5, 4, cris_ver_v32p, NULL}, + {"dcr0",6, 2, cris_ver_v0_3, NULL}, + {"eda", 6, 4, cris_ver_v32p, NULL}, + {"p6", 6, 2, cris_ver_v0_3, NULL}, + {"p6", 6, 4, cris_ver_v32p, NULL}, {"dcr1/mof", 7, 4, cris_ver_v10p, "Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes"}, {"dcr1/mof", 7, 2, cris_ver_v0_3, "Register `dcr1/mof' with ambiguous size specified. Guessing 2 bytes"}, - {"mof", 7, 4, cris_ver_v10p, NULL}, - {"dcr1",7, 2, cris_ver_v0_3, NULL}, - {"p7", 7, 4, cris_ver_v10p, NULL}, - {"p7", 7, 2, cris_ver_v0_3, NULL}, - {"dz", 8, 4, cris_ver_v32p, NULL}, - {"p8", 8, 4, 0, NULL}, + {"mof", 7, 4, cris_ver_v10p, NULL}, + {"dcr1",7, 2, cris_ver_v0_3, NULL}, + {"p7", 7, 4, cris_ver_v10p, NULL}, + {"p7", 7, 2, cris_ver_v0_3, NULL}, + {"dz", 8, 4, cris_ver_v32p, NULL}, + {"p8", 8, 4, 0, NULL}, {"ibr", 9, 4, cris_ver_v0_10, NULL}, - {"ebp", 9, 4, cris_ver_v32p, NULL}, - {"p9", 9, 4, 0, NULL}, + {"ebp", 9, 4, cris_ver_v32p, NULL}, + {"p9", 9, 4, 0, NULL}, {"irp", 10, 4, cris_ver_v0_10, NULL}, - {"erp", 10, 4, cris_ver_v32p, NULL}, - {"p10", 10, 4, 0, NULL}, - {"srp", 11, 4, 0, NULL}, - {"p11", 11, 4, 0, NULL}, + {"erp", 10, 4, cris_ver_v32p, NULL}, + {"p10", 10, 4, 0, NULL}, + {"srp", 11, 4, 0, NULL}, + {"p11", 11, 4, 0, NULL}, /* For disassembly use only. Accept at assembly with a warning. */ {"bar/dtp0", 12, 4, cris_ver_warning, "Ambiguous register `bar/dtp0' specified"}, - {"nrp", 12, 4, cris_ver_v32p, NULL}, + {"nrp", 12, 4, cris_ver_v32p, NULL}, {"bar", 12, 4, cris_ver_v8_10, NULL}, - {"dtp0",12, 4, cris_ver_v0_3, NULL}, - {"p12", 12, 4, 0, NULL}, + {"dtp0",12, 4, cris_ver_v0_3, NULL}, + {"p12", 12, 4, 0, NULL}, /* For disassembly use only. Accept at assembly with a warning. */ {"dccr/dtp1",13, 4, cris_ver_warning, "Ambiguous register `dccr/dtp1' specified"}, - {"ccs", 13, 4, cris_ver_v32p, NULL}, + {"ccs", 13, 4, cris_ver_v32p, NULL}, {"dccr",13, 4, cris_ver_v8_10, NULL}, - {"dtp1",13, 4, cris_ver_v0_3, NULL}, - {"p13", 13, 4, 0, NULL}, + {"dtp1",13, 4, cris_ver_v0_3, NULL}, + {"p13", 13, 4, 0, NULL}, {"brp", 14, 4, cris_ver_v3_10, NULL}, - {"usp", 14, 4, cris_ver_v32p, NULL}, - {"p14", 14, 4, cris_ver_v3p, NULL}, - {"usp", 15, 4, cris_ver_v10, NULL}, - {"spc", 15, 4, cris_ver_v32p, NULL}, - {"p15", 15, 4, cris_ver_v10p, NULL}, + {"usp", 14, 4, cris_ver_v32p, NULL}, + {"p14", 14, 4, cris_ver_v3p, NULL}, + {"usp", 15, 4, cris_ver_v10, NULL}, + {"spc", 15, 4, cris_ver_v32p, NULL}, + {"p15", 15, 4, cris_ver_v10p, NULL}, {NULL, 0, 0, cris_ver_version_all, NULL} }; =20 @@ -151,53 +151,53 @@ const struct cris_support_reg cris_support_regs[] =3D Operand-matching characters: [ ] , space Verbatim. - A The string "ACR" (case-insensitive). - B Not really an operand. It causes a "BDAP -size,SP" prefix to be - output for the PUSH alias-instructions and recognizes a push- - prefix at disassembly. This letter isn't recognized for v32. - Must be followed by a R or P letter. - ! Non-match pattern, will not match if there's a prefix insn. - b Non-matching operand, used for branches with 16-bit - displacement. Only recognized by the disassembler. - c 5-bit unsigned immediate in bits <4:0>. - C 4-bit unsigned immediate in bits <3:0>. + A The string "ACR" (case-insensitive). + B Not really an operand. It causes a "BDAP -size,SP" prefix to be + output for the PUSH alias-instructions and recognizes a push- + prefix at disassembly. This letter isn't recognized for v32. + Must be followed by a R or P letter. + ! Non-match pattern, will not match if there's a prefix insn. + b Non-matching operand, used for branches with 16-bit + displacement. Only recognized by the disassembler. + c 5-bit unsigned immediate in bits <4:0>. + C 4-bit unsigned immediate in bits <3:0>. d At assembly, optionally (as in put other cases before this one) - ".d" or ".D" at the start of the operands, followed by one space - character. At disassembly, nothing. - D General register in bits <15:12> and <3:0>. - f List of flags in bits <15:12> and <3:0>. - i 6-bit signed immediate in bits <5:0>. - I 6-bit unsigned immediate in bits <5:0>. - M Size modifier (B, W or D) for CLEAR instructions. - m Size modifier (B, W or D) in bits <5:4> + ".d" or ".D" at the start of the operands, followed by one space + character. At disassembly, nothing. + D General register in bits <15:12> and <3:0>. + f List of flags in bits <15:12> and <3:0>. + i 6-bit signed immediate in bits <5:0>. + I 6-bit unsigned immediate in bits <5:0>. + M Size modifier (B, W or D) for CLEAR instructions. + m Size modifier (B, W or D) in bits <5:4> N A 32-bit dword, like in the difference between s and y. This has no effect on bits in the opcode. Can also be expressed - as "[pc+]" in input. + as "[pc+]" in input. n As N, but PC-relative (to the start of the instruction). - o [-128..127] word offset in bits <7:1> and <0>. Used by 8-bit - branch instructions. - O [-128..127] offset in bits <7:0>. Also matches a comma and a - general register after the expression, in bits <15:12>. Used - only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode). - P Special register in bits <15:12>. - p Indicates that the insn is a prefix insn. Must be first - character. + o [-128..127] word offset in bits <7:1> and <0>. Used by 8-bit + branch instructions. + O [-128..127] offset in bits <7:0>. Also matches a comma and a + general register after the expression, in bits <15:12>. Used + only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode). + P Special register in bits <15:12>. + p Indicates that the insn is a prefix insn. Must be first + character. Q As O, but don't relax; force an 8-bit offset. - R General register in bits <15:12>. - r General register in bits <3:0>. - S Source operand in bit <10> and a prefix; a 3-operand prefix - without side-effect. - s Source operand in bits <10> and <3:0>, optionally with a - side-effect prefix, except [pc] (the name, not R15 as in ACR) - isn't allowed for v32 and higher. + R General register in bits <15:12>. + r General register in bits <3:0>. + S Source operand in bit <10> and a prefix; a 3-operand prefix + without side-effect. + s Source operand in bits <10> and <3:0>, optionally with a + side-effect prefix, except [pc] (the name, not R15 as in ACR) + isn't allowed for v32 and higher. T Support register in bits <15:12>. u 4-bit (PC-relative) unsigned immediate word offset in bits <3:0>. U Relaxes to either u or n, instruction is assumed LAPCQ or LAPC. - Not recognized at disassembly. - x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>. - y Like 's' but do not allow an integer at assembly. - Y The difference s-y; only an integer is allowed. - z Size modifier (B or W) in bit <4>. */ + Not recognized at disassembly. + x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4= >. + y Like 's' but do not allow an integer at assembly. + Y The difference s-y; only an integer is allowed. + z Size modifier (B or W) in bit <4>. */ =20 =20 /* Please note the order of the opcodes in this table is significant. @@ -216,150 +216,150 @@ const struct cris_support_reg cris_support_regs[] = =3D const struct cris_opcode cris_opcodes[] =3D { - {"abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0, + {"abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0, cris_abs_op}, =20 - {"add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0, + {"add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0, + {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE, + {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE, + {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_add_sub_cmp_and_or_op}, =20 - {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, + {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, cris_ver_v32p, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"addc", 0x0570, 0x0A80, "r,R", 0, SIZE_FIX_32, + {"addc", 0x0570, 0x0A80, "r,R", 0, SIZE_FIX_32, cris_ver_v32p, cris_not_implemented_op}, =20 - {"addc", 0x09A0, 0x0250, "s,R", 0, SIZE_FIX_32, + {"addc", 0x09A0, 0x0250, "s,R", 0, SIZE_FIX_32, cris_ver_v32p, cris_not_implemented_op}, =20 - {"addi", 0x0540, 0x0A80, "x,r,A", 0, SIZE_NONE, + {"addi", 0x0540, 0x0A80, "x,r,A", 0, SIZE_NONE, cris_ver_v32p, cris_addi_op}, =20 - {"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0, + {"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0, cris_addi_op}, =20 /* This collates after "addo", but we want to disassemble as "addoq", not "addo". */ - {"addoq", 0x0100, 0x0E00, "Q,A", 0, SIZE_NONE, + {"addoq", 0x0100, 0x0E00, "Q,A", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, =20 - {"addo", 0x0940, 0x0280, "m s,R,A", 0, SIZE_FIELD_SIGNED, + {"addo", 0x0940, 0x0280, "m s,R,A", 0, SIZE_FIELD_SIGNED, cris_ver_v32p, cris_not_implemented_op}, =20 /* This must be located after the insn above, lest we misinterpret "addo.b -1,r0,acr" as "addo .b-1,r0,acr". FIXME: Sounds like a parser bug. */ - {"addo", 0x0100, 0x0E00, "O,A", 0, SIZE_NONE, + {"addo", 0x0100, 0x0E00, "O,A", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, =20 - {"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0, + {"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0, cris_quick_mode_add_sub_op}, =20 - {"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0, + {"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, =20 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */ - {"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0, + {"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE, + {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE, + {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_add_sub_cmp_and_or_op}, =20 - {"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0, + {"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, =20 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ - {"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0, + {"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE, + {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE, + {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_add_sub_cmp_and_or_op}, =20 - {"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0, + {"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0, + {"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE, + {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE, + {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_add_sub_cmp_and_or_op}, =20 - {"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0, + {"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0, cris_quick_mode_and_cmp_move_or_op}, =20 - {"asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0, + {"asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0, cris_asr_op}, =20 - {"asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0, + {"asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0, cris_asrq_op}, =20 - {"ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0, + {"ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0, cris_ax_ei_setf_op}, =20 /* FIXME: Should use branch #defines. */ - {"b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0, + {"b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0, cris_sixteen_bit_offset_branch_op}, =20 {"ba", BA_QUICK_OPCODE, - 0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0, + 0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, =20 /* Needs to come after the usual "ba o", which might be relaxed to this one. */ {"ba", BA_DWORD_OPCODE, - 0xffff & (~BA_DWORD_OPCODE), "n", 0, SIZE_FIX_32, + 0xffff & (~BA_DWORD_OPCODE), "n", 0, SIZE_FIX_32, cris_ver_v32p, cris_none_reg_mode_jump_op}, =20 - {"bas", 0x0EBF, 0x0140, "n,P", 0, SIZE_FIX_32, + {"bas", 0x0EBF, 0x0140, "n,P", 0, SIZE_FIX_32, cris_ver_v32p, cris_none_reg_mode_jump_op}, =20 - {"basc", 0x0EFF, 0x0100, "n,P", 0, SIZE_FIX_32, + {"basc", 0x0EFF, 0x0100, "n,P", 0, SIZE_FIX_32, cris_ver_v32p, cris_none_reg_mode_jump_op}, =20 {"bcc", BRANCH_QUICK_OPCODE+CC_CC*0x1000, - 0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0, + 0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, =20 {"bcs", BRANCH_QUICK_OPCODE+CC_CS*0x1000, - 0x0f00+(0xF-CC_CS)*0x1000, "o", 1, SIZE_NONE, 0, + 0x0f00+(0xF-CC_CS)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, =20 {"bdap", @@ -368,13 +368,13 @@ cris_opcodes[] =3D cris_bdap_prefix}, =20 {"bdap", - BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE, + BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE, cris_ver_v0_10, cris_quick_mode_bdap_prefix}, =20 {"beq", BRANCH_QUICK_OPCODE+CC_EQ*0x1000, - 0x0f00+(0xF-CC_EQ)*0x1000, "o", 1, SIZE_NONE, 0, + 0x0f00+(0xF-CC_EQ)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, =20 /* This is deliberately put before "bext" to trump it, even though not @@ -382,396 +382,396 @@ cris_opcodes[] =3D for v0..v10. */ {"bwf", BRANCH_QUICK_OPCODE+CC_EXT*0x1000, - 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, + 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, cris_ver_v10, cris_eight_bit_offset_branch_op}, =20 {"bext", BRANCH_QUICK_OPCODE+CC_EXT*0x1000, - 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, + 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, cris_ver_v0_3, cris_eight_bit_offset_branch_op}, =20 {"bge", BRANCH_QUICK_OPCODE+CC_GE*0x1000, - 0x0f00+(0xF-CC_GE)*0x1000, "o", 1, SIZE_NONE, 0, + 0x0f00+(0xF-CC_GE)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, =20 {"bgt", BRANCH_QUICK_OPCODE+CC_GT*0x1000, - 0x0f00+(0xF-CC_GT)*0x1000, "o", 1, SIZE_NONE, 0, + 0x0f00+(0xF-CC_GT)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, =20 {"bhi", BRANCH_QUICK_OPCODE+CC_HI*0x1000, - 0x0f00+(0xF-CC_HI)*0x1000, "o", 1, SIZE_NONE, 0, + 0x0f00+(0xF-CC_HI)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, =20 {"bhs", BRANCH_QUICK_OPCODE+CC_HS*0x1000, - 0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0, + 0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, =20 - {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE, + {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE, cris_ver_v0_10, cris_biap_prefix}, =20 {"ble", BRANCH_QUICK_OPCODE+CC_LE*0x1000, - 0x0f00+(0xF-CC_LE)*0x1000, "o", 1, SIZE_NONE, 0, + 0x0f00+(0xF-CC_LE)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, =20 {"blo", BRANCH_QUICK_OPCODE+CC_LO*0x1000, - 0x0f00+(0xF-CC_LO)*0x1000, "o", 1, SIZE_NONE, 0, + 0x0f00+(0xF-CC_LO)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, =20 {"bls", BRANCH_QUICK_OPCODE+CC_LS*0x1000, - 0x0f00+(0xF-CC_LS)*0x1000, "o", 1, SIZE_NONE, 0, + 0x0f00+(0xF-CC_LS)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, =20 {"blt", BRANCH_QUICK_OPCODE+CC_LT*0x1000, - 0x0f00+(0xF-CC_LT)*0x1000, "o", 1, SIZE_NONE, 0, + 0x0f00+(0xF-CC_LT)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, =20 {"bmi", BRANCH_QUICK_OPCODE+CC_MI*0x1000, - 0x0f00+(0xF-CC_MI)*0x1000, "o", 1, SIZE_NONE, 0, + 0x0f00+(0xF-CC_MI)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, =20 - {"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32, + {"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32, cris_ver_sim_v0_10, cris_not_implemented_op}, =20 - {"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE, + {"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE, cris_ver_sim_v0_10, cris_not_implemented_op}, =20 - {"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE, + {"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE, cris_ver_sim_v0_10, cris_not_implemented_op}, =20 {"bne", BRANCH_QUICK_OPCODE+CC_NE*0x1000, - 0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0, + 0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, =20 - {"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0, + {"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0, cris_two_operand_bound_op}, /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ - {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD, + {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD, cris_ver_v0_10, cris_two_operand_bound_op}, /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ - {"bound", 0x0dcf, 0x0200, "m Y,R", 0, SIZE_FIELD, 0, + {"bound", 0x0dcf, 0x0200, "m Y,R", 0, SIZE_FIELD, 0, cris_two_operand_bound_op}, - {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE, + {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_two_operand_bound_op}, - {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE, + {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_bound_op}, =20 {"bpl", BRANCH_QUICK_OPCODE+CC_PL*0x1000, - 0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0, + 0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, =20 - {"break", 0xe930, 0x16c0, "C", 0, SIZE_NONE, + {"break", 0xe930, 0x16c0, "C", 0, SIZE_NONE, cris_ver_v3p, cris_break_op}, =20 {"bsb", BRANCH_QUICK_OPCODE+CC_EXT*0x1000, - 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, + 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE, cris_ver_v32p, cris_eight_bit_offset_branch_op}, =20 - {"bsr", 0xBEBF, 0x4140, "n", 0, SIZE_FIX_32, + {"bsr", 0xBEBF, 0x4140, "n", 0, SIZE_FIX_32, cris_ver_v32p, cris_none_reg_mode_jump_op}, =20 - {"bsrc", 0xBEFF, 0x4100, "n", 0, SIZE_FIX_32, + {"bsrc", 0xBEFF, 0x4100, "n", 0, SIZE_FIX_32, cris_ver_v32p, cris_none_reg_mode_jump_op}, =20 - {"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32, + {"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32, cris_ver_warning, cris_not_implemented_op}, =20 - {"bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE, + {"bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE, cris_ver_warning, cris_not_implemented_op}, =20 - {"bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE, + {"bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE, cris_ver_warning, cris_not_implemented_op}, =20 - {"btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0, + {"btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0, cris_btst_nop_op}, - {"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0, + {"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0, cris_btst_nop_op}, =20 {"bvc", BRANCH_QUICK_OPCODE+CC_VC*0x1000, - 0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0, + 0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, =20 {"bvs", BRANCH_QUICK_OPCODE+CC_VS*0x1000, - 0x0f00+(0xF-CC_VS)*0x1000, "o", 1, SIZE_NONE, 0, + 0x0f00+(0xF-CC_VS)*0x1000, "o", 1, SIZE_NONE, 0, cris_eight_bit_offset_branch_op}, =20 - {"clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0, + {"clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0, cris_reg_mode_clear_op}, =20 - {"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0, + {"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0, cris_none_reg_mode_clear_test_op}, =20 - {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE, + {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_clear_test_op}, =20 - {"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0, + {"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0, cris_clearf_di_op}, =20 - {"cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0, + {"cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0, + {"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE, + {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0, + {"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0, cris_quick_mode_and_cmp_move_or_op}, =20 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */ - {"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0, + {"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE, + {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ - {"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0, + {"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE, + {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0, + {"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0, cris_clearf_di_op}, =20 - {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32, + {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32, cris_ver_v0_10, cris_dip_prefix}, =20 - {"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0, + {"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0, cris_not_implemented_op}, =20 - {"dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0, + {"dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0, cris_dstep_logshift_mstep_neg_not_op}, =20 - {"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0, + {"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0, cris_ax_ei_setf_op}, =20 - {"fidxd", 0x0ab0, 0xf540, "[r]", 0, SIZE_NONE, + {"fidxd", 0x0ab0, 0xf540, "[r]", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, =20 - {"fidxi", 0x0d30, 0xF2C0, "[r]", 0, SIZE_NONE, + {"fidxi", 0x0d30, 0xF2C0, "[r]", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, =20 - {"ftagd", 0x1AB0, 0xE540, "[r]", 0, SIZE_NONE, + {"ftagd", 0x1AB0, 0xE540, "[r]", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, =20 - {"ftagi", 0x1D30, 0xE2C0, "[r]", 0, SIZE_NONE, + {"ftagi", 0x1D30, 0xE2C0, "[r]", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, =20 - {"halt", 0xF930, 0x06CF, "", 0, SIZE_NONE, + {"halt", 0xF930, 0x06CF, "", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, =20 - {"jas", 0x09B0, 0x0640, "r,P", 0, SIZE_NONE, + {"jas", 0x09B0, 0x0640, "r,P", 0, SIZE_NONE, cris_ver_v32p, cris_reg_mode_jump_op}, =20 - {"jas", 0x0DBF, 0x0240, "N,P", 0, SIZE_FIX_32, + {"jas", 0x0DBF, 0x0240, "N,P", 0, SIZE_FIX_32, cris_ver_v32p, cris_reg_mode_jump_op}, =20 - {"jasc", 0x0B30, 0x04C0, "r,P", 0, SIZE_NONE, + {"jasc", 0x0B30, 0x04C0, "r,P", 0, SIZE_NONE, cris_ver_v32p, cris_reg_mode_jump_op}, =20 - {"jasc", 0x0F3F, 0x00C0, "N,P", 0, SIZE_FIX_32, + {"jasc", 0x0F3F, 0x00C0, "N,P", 0, SIZE_FIX_32, cris_ver_v32p, cris_reg_mode_jump_op}, =20 - {"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE, + {"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE, cris_ver_v8_10, cris_reg_mode_jump_op}, =20 - {"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32, + {"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32, cris_ver_v8_10, cris_none_reg_mode_jump_op}, =20 - {"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE, + {"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE, cris_ver_v8_10, cris_none_reg_mode_jump_op}, =20 - {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE, + {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE, cris_ver_v8_10, cris_reg_mode_jump_op}, =20 - {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32, + {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32, cris_ver_v8_10, cris_none_reg_mode_jump_op}, =20 - {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE, + {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE, cris_ver_v8_10, cris_none_reg_mode_jump_op}, =20 - {"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE, + {"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE, cris_ver_v8_10, cris_reg_mode_jump_op}, =20 - {"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32, + {"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32, cris_ver_v8_10, cris_none_reg_mode_jump_op}, =20 - {"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE, + {"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE, cris_ver_v8_10, cris_none_reg_mode_jump_op}, =20 - {"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0, + {"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0, cris_reg_mode_jump_op}, =20 - {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32, + {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32, cris_ver_v0_10, cris_none_reg_mode_jump_op}, =20 - {"jsr", 0xBDBF, 0x4240, "N", 0, SIZE_FIX_32, + {"jsr", 0xBDBF, 0x4240, "N", 0, SIZE_FIX_32, cris_ver_v32p, cris_none_reg_mode_jump_op}, =20 - {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE, + {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_jump_op}, =20 - {"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE, + {"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE, cris_ver_v8_10, cris_reg_mode_jump_op}, =20 - {"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32, + {"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32, cris_ver_v8_10, cris_none_reg_mode_jump_op}, =20 - {"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE, + {"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE, cris_ver_v8_10, cris_none_reg_mode_jump_op}, =20 - {"jsrc", 0xBB30, 0x44C0, "r", 0, SIZE_NONE, + {"jsrc", 0xBB30, 0x44C0, "r", 0, SIZE_NONE, cris_ver_v32p, cris_reg_mode_jump_op}, =20 - {"jsrc", 0xBF3F, 0x40C0, "N", 0, SIZE_FIX_32, + {"jsrc", 0xBF3F, 0x40C0, "N", 0, SIZE_FIX_32, cris_ver_v32p, cris_reg_mode_jump_op}, =20 - {"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0, + {"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0, cris_reg_mode_jump_op}, =20 {"jump", - JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32, + JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32, cris_ver_v0_10, cris_none_reg_mode_jump_op}, =20 {"jump", - JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE, + JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_jump_op}, =20 - {"jump", 0x09F0, 0x060F, "P", 0, SIZE_NONE, + {"jump", 0x09F0, 0x060F, "P", 0, SIZE_NONE, cris_ver_v32p, cris_none_reg_mode_jump_op}, =20 {"jump", JUMP_PC_INCR_OPCODE_V32, - (0xffff & ~JUMP_PC_INCR_OPCODE_V32), "N", 0, SIZE_FIX_32, + (0xffff & ~JUMP_PC_INCR_OPCODE_V32), "N", 0, SIZE_FIX_32, cris_ver_v32p, cris_none_reg_mode_jump_op}, =20 - {"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32, + {"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32, cris_ver_v10, cris_none_reg_mode_jump_op}, =20 - {"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE, + {"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE, cris_ver_v10, cris_none_reg_mode_jump_op}, =20 - {"lapc", 0x0970, 0x0680, "U,R", 0, SIZE_NONE, + {"lapc", 0x0970, 0x0680, "U,R", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, =20 - {"lapc", 0x0D7F, 0x0280, "dn,R", 0, SIZE_FIX_32, + {"lapc", 0x0D7F, 0x0280, "dn,R", 0, SIZE_FIX_32, cris_ver_v32p, cris_not_implemented_op}, =20 - {"lapcq", 0x0970, 0x0680, "u,R", 0, SIZE_NONE, + {"lapcq", 0x0970, 0x0680, "u,R", 0, SIZE_NONE, cris_ver_v32p, cris_addi_op}, =20 - {"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0, + {"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0, cris_dstep_logshift_mstep_neg_not_op}, =20 - {"lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0, + {"lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0, cris_dstep_logshift_mstep_neg_not_op}, =20 - {"lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0, + {"lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0, cris_dstep_logshift_mstep_neg_not_op}, =20 - {"lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0, + {"lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0, cris_dstep_logshift_mstep_neg_not_op}, =20 - {"lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE, + {"lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE, cris_ver_v3p, cris_not_implemented_op}, =20 - {"mcp", 0x07f0, 0x0800, "P,r", 0, SIZE_NONE, + {"mcp", 0x07f0, 0x0800, "P,r", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, =20 - {"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0, + {"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0, + {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE, + {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0, + {"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0, cris_move_to_preg_op}, =20 - {"move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0, + {"move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0, cris_reg_mode_move_from_preg_op}, =20 - {"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0, + {"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE, + {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 @@ -780,80 +780,80 @@ cris_opcodes[] =3D "s,P", 0, SIZE_SPEC_REG, 0, cris_move_to_preg_op}, =20 - {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE, + {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE, cris_ver_v0_10, cris_move_to_preg_op}, =20 - {"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0, + {"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0, cris_none_reg_mode_move_from_preg_op}, =20 - {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE, + {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_move_from_preg_op}, =20 - {"move", 0x0B70, 0x0480, "r,T", 0, SIZE_NONE, + {"move", 0x0B70, 0x0480, "r,T", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, =20 - {"move", 0x0F70, 0x0080, "T,r", 0, SIZE_NONE, + {"move", 0x0F70, 0x0080, "T,r", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, =20 - {"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0, + {"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0, cris_move_reg_to_mem_movem_op}, =20 - {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE, + {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE, cris_ver_v0_10, cris_move_reg_to_mem_movem_op}, =20 - {"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0, + {"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0, cris_move_mem_to_reg_movem_op}, =20 - {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE, + {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_move_mem_to_reg_movem_op}, =20 - {"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0, + {"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0, cris_quick_mode_and_cmp_move_or_op}, =20 - {"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0, + {"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, =20 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */ - {"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0, + {"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE, + {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0, + {"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, =20 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ - {"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0, + {"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE, + {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE, + {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE, cris_ver_v0_10, cris_dstep_logshift_mstep_neg_not_op}, =20 - {"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE, + {"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE, cris_ver_v10p, cris_muls_op}, =20 - {"mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE, + {"mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE, cris_ver_v10p, cris_mulu_op}, =20 - {"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0, + {"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0, cris_dstep_logshift_mstep_neg_not_op}, =20 - {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE, + {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE, cris_ver_v0_10, cris_btst_nop_op}, =20 @@ -861,124 +861,124 @@ cris_opcodes[] =3D cris_ver_v32p, cris_btst_nop_op}, =20 - {"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0, + {"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0, cris_dstep_logshift_mstep_neg_not_op}, =20 - {"or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0, + {"or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0, + {"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE, + {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE, + {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_add_sub_cmp_and_or_op}, =20 - {"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0, + {"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0, cris_quick_mode_and_cmp_move_or_op}, =20 - {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE, + {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE, + {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_move_from_preg_op}, =20 - {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE, + {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE, + {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE, cris_ver_v0_10, cris_move_to_preg_op}, =20 - {"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE, + {"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE, cris_ver_v10, cris_not_implemented_op}, =20 - {"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE, + {"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE, cris_ver_v10, cris_not_implemented_op}, =20 - {"rfe", 0x2930, 0xD6CF, "", 0, SIZE_NONE, + {"rfe", 0x2930, 0xD6CF, "", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, =20 - {"rfg", 0x4930, 0xB6CF, "", 0, SIZE_NONE, + {"rfg", 0x4930, 0xB6CF, "", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, =20 - {"rfn", 0x5930, 0xA6CF, "", 0, SIZE_NONE, + {"rfn", 0x5930, 0xA6CF, "", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, =20 - {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE, + {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE, cris_ver_v0_10, cris_reg_mode_move_from_preg_op}, =20 - {"ret", 0xB9F0, 0x460F, "", 1, SIZE_NONE, + {"ret", 0xB9F0, 0x460F, "", 1, SIZE_NONE, cris_ver_v32p, cris_reg_mode_move_from_preg_op}, =20 - {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE, + {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE, cris_ver_v0_10, cris_reg_mode_move_from_preg_op}, =20 - {"rete", 0xA9F0, 0x560F, "", 1, SIZE_NONE, + {"rete", 0xA9F0, 0x560F, "", 1, SIZE_NONE, cris_ver_v32p, cris_reg_mode_move_from_preg_op}, =20 - {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE, + {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE, cris_ver_v0_10, cris_reg_mode_move_from_preg_op}, =20 - {"retn", 0xC9F0, 0x360F, "", 1, SIZE_NONE, + {"retn", 0xC9F0, 0x360F, "", 1, SIZE_NONE, cris_ver_v32p, cris_reg_mode_move_from_preg_op}, =20 - {"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE, + {"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE, cris_ver_v10, cris_not_implemented_op}, =20 - {"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE, + {"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE, cris_ver_v10, cris_not_implemented_op}, =20 {"sa", 0x0530+CC_A*0x1000, - 0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0, + 0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, =20 {"ssb", 0x0530+CC_EXT*0x1000, - 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, + 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, cris_ver_v32p, cris_scc_op}, =20 {"scc", 0x0530+CC_CC*0x1000, - 0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0, + 0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, =20 {"scs", 0x0530+CC_CS*0x1000, - 0x0AC0+(0xf-CC_CS)*0x1000, "r", 0, SIZE_NONE, 0, + 0x0AC0+(0xf-CC_CS)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, =20 {"seq", 0x0530+CC_EQ*0x1000, - 0x0AC0+(0xf-CC_EQ)*0x1000, "r", 0, SIZE_NONE, 0, + 0x0AC0+(0xf-CC_EQ)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, =20 - {"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0, + {"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0, cris_ax_ei_setf_op}, =20 - {"sfe", 0x3930, 0xC6CF, "", 0, SIZE_NONE, + {"sfe", 0x3930, 0xC6CF, "", 0, SIZE_NONE, cris_ver_v32p, cris_not_implemented_op}, =20 @@ -986,203 +986,203 @@ cris_opcodes[] =3D disassembly. */ {"swf", 0x0530+CC_EXT*0x1000, - 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, + 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, cris_ver_v10, cris_scc_op}, =20 {"sext", 0x0530+CC_EXT*0x1000, - 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, + 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE, cris_ver_v0_3, cris_scc_op}, =20 {"sge", 0x0530+CC_GE*0x1000, - 0x0AC0+(0xf-CC_GE)*0x1000, "r", 0, SIZE_NONE, 0, + 0x0AC0+(0xf-CC_GE)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, =20 {"sgt", 0x0530+CC_GT*0x1000, - 0x0AC0+(0xf-CC_GT)*0x1000, "r", 0, SIZE_NONE, 0, + 0x0AC0+(0xf-CC_GT)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, =20 {"shi", 0x0530+CC_HI*0x1000, - 0x0AC0+(0xf-CC_HI)*0x1000, "r", 0, SIZE_NONE, 0, + 0x0AC0+(0xf-CC_HI)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, =20 {"shs", 0x0530+CC_HS*0x1000, - 0x0AC0+(0xf-CC_HS)*0x1000, "r", 0, SIZE_NONE, 0, + 0x0AC0+(0xf-CC_HS)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, =20 {"sle", 0x0530+CC_LE*0x1000, - 0x0AC0+(0xf-CC_LE)*0x1000, "r", 0, SIZE_NONE, 0, + 0x0AC0+(0xf-CC_LE)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, =20 {"slo", 0x0530+CC_LO*0x1000, - 0x0AC0+(0xf-CC_LO)*0x1000, "r", 0, SIZE_NONE, 0, + 0x0AC0+(0xf-CC_LO)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, =20 {"sls", 0x0530+CC_LS*0x1000, - 0x0AC0+(0xf-CC_LS)*0x1000, "r", 0, SIZE_NONE, 0, + 0x0AC0+(0xf-CC_LS)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, =20 {"slt", 0x0530+CC_LT*0x1000, - 0x0AC0+(0xf-CC_LT)*0x1000, "r", 0, SIZE_NONE, 0, + 0x0AC0+(0xf-CC_LT)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, =20 {"smi", 0x0530+CC_MI*0x1000, - 0x0AC0+(0xf-CC_MI)*0x1000, "r", 0, SIZE_NONE, 0, + 0x0AC0+(0xf-CC_MI)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, =20 {"sne", 0x0530+CC_NE*0x1000, - 0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0, + 0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, =20 {"spl", 0x0530+CC_PL*0x1000, - 0x0AC0+(0xf-CC_PL)*0x1000, "r", 0, SIZE_NONE, 0, + 0x0AC0+(0xf-CC_PL)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, =20 - {"sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0, + {"sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0, + {"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE, + {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE, + {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_add_sub_cmp_and_or_op}, =20 - {"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0, + {"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0, cris_quick_mode_add_sub_op}, =20 - {"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0, + {"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, =20 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */ - {"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0, + {"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE, + {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE, + {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_add_sub_cmp_and_or_op}, =20 - {"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0, + {"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0, cris_reg_mode_add_sub_cmp_and_or_move_op}, =20 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */ - {"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0, + {"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE, + {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_add_sub_cmp_and_or_move_op}, =20 - {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE, + {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE, cris_ver_v0_10, cris_three_operand_add_sub_cmp_and_or_op}, =20 {"svc", 0x0530+CC_VC*0x1000, - 0x0AC0+(0xf-CC_VC)*0x1000, "r", 0, SIZE_NONE, 0, + 0x0AC0+(0xf-CC_VC)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, =20 {"svs", 0x0530+CC_VS*0x1000, - 0x0AC0+(0xf-CC_VS)*0x1000, "r", 0, SIZE_NONE, 0, + 0x0AC0+(0xf-CC_VS)*0x1000, "r", 0, SIZE_NONE, 0, cris_scc_op}, =20 /* The insn "swapn" is the same as "not" and will be disassembled as such, but the swap* family of mnmonics are generally v8-and-higher only, so count it in. */ - {"swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE, + {"swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, =20 - {"swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE, + {"swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, =20 - {"swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE, + {"swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, =20 - {"swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE, + {"swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, =20 - {"swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE, + {"swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, =20 - {"swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE, + {"swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, =20 - {"swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE, + {"swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, =20 - {"swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE, + {"swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, =20 - {"swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE, + {"swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, =20 - {"swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE, + {"swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, =20 - {"swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE, + {"swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, =20 - {"swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE, + {"swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, =20 - {"swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE, + {"swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, =20 - {"swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE, + {"swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, =20 - {"swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE, + {"swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE, cris_ver_v8p, cris_not_implemented_op}, =20 - {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE, + {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE, cris_ver_v0_10, cris_reg_mode_test_op}, =20 - {"test", 0x0b80, 0xf040, "m y", 0, SIZE_FIELD, 0, + {"test", 0x0b80, 0xf040, "m y", 0, SIZE_FIELD, 0, cris_none_reg_mode_clear_test_op}, =20 - {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE, + {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE, cris_ver_v0_10, cris_none_reg_mode_clear_test_op}, =20 - {"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0, + {"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0, cris_xor_op}, =20 {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op} @@ -1296,8 +1296,8 @@ static int cris_constraint =20 static void cris_parse_disassembler_options (struct cris_disasm_data *disdata, - char *disassembler_options, - enum cris_disass_family distype) + char *disassembler_options, + enum cris_disass_family distype) { /* Default true. */ disdata->trace_case @@ -1315,25 +1315,25 @@ spec_reg_info (unsigned int sreg, enum cris_disass_= family distype) for (i =3D 0; cris_spec_regs[i].name !=3D NULL; i++) { if (cris_spec_regs[i].number =3D=3D sreg) - { - if (distype =3D=3D cris_dis_v32) - switch (cris_spec_regs[i].applicable_version) - { - case cris_ver_warning: - case cris_ver_version_all: - case cris_ver_v3p: - case cris_ver_v8p: - case cris_ver_v10p: - case cris_ver_v32p: - /* No ambiguous sizes or register names with CRISv32. */ - if (cris_spec_regs[i].warning =3D=3D NULL) - return &cris_spec_regs[i]; - default: - ; - } - else if (cris_spec_regs[i].applicable_version !=3D cris_ver_v32p) - return &cris_spec_regs[i]; - } + { + if (distype =3D=3D cris_dis_v32) + switch (cris_spec_regs[i].applicable_version) + { + case cris_ver_warning: + case cris_ver_version_all: + case cris_ver_v3p: + case cris_ver_v8p: + case cris_ver_v10p: + case cris_ver_v32p: + /* No ambiguous sizes or register names with CRISv32. */ + if (cris_spec_regs[i].warning =3D=3D NULL) + return &cris_spec_regs[i]; + default: + ; + } + else if (cris_spec_regs[i].applicable_version !=3D cris_ver_v32p) + return &cris_spec_regs[i]; + } } =20 return NULL; @@ -1356,8 +1356,8 @@ number_of_bits (unsigned int val) =20 static const struct cris_opcode * get_opcode_entry (unsigned int insn, - unsigned int prefix_insn, - struct cris_disasm_data *disdata) + unsigned int prefix_insn, + struct cris_disasm_data *disdata) { /* For non-prefixed insns, we keep a table of pointers, indexed by the insn code. Each entry is initialized when found to be NULL. */ @@ -1393,47 +1393,47 @@ get_opcode_entry (unsigned int insn, if (prefix_insn !=3D NO_CRIS_PREFIX) { const struct cris_opcode *popcodep - =3D (opc_table[prefix_insn] !=3D NULL - ? opc_table[prefix_insn] - : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata)); + =3D (opc_table[prefix_insn] !=3D NULL + ? opc_table[prefix_insn] + : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata)); =20 if (popcodep =3D=3D NULL) - return NULL; + return NULL; =20 if (popcodep->match =3D=3D BDAP_QUICK_OPCODE) - { - /* Since some offsets are recognized with "push" macros, we - have to have different tables for them. */ - int offset =3D (prefix_insn & 255); + { + /* Since some offsets are recognized with "push" macros, we + have to have different tables for them. */ + int offset =3D (prefix_insn & 255); =20 - if (offset > 127) - offset -=3D 256; + if (offset > 127) + offset -=3D 256; =20 - switch (offset) - { - case -4: - prefix_opc_table =3D bdapq_m4_prefixes; - break; + switch (offset) + { + case -4: + prefix_opc_table =3D bdapq_m4_prefixes; + break; =20 - case -2: - prefix_opc_table =3D bdapq_m2_prefixes; - break; + case -2: + prefix_opc_table =3D bdapq_m2_prefixes; + break; =20 - case -1: - prefix_opc_table =3D bdapq_m1_prefixes; - break; + case -1: + prefix_opc_table =3D bdapq_m1_prefixes; + break; =20 - default: - prefix_opc_table =3D rest_prefixes; - break; - } - } + default: + prefix_opc_table =3D rest_prefixes; + break; + } + } else if (popcodep->match =3D=3D DIP_OPCODE) - /* We don't allow postincrement when the prefix is DIP, so use a - different table for DIP. */ - prefix_opc_table =3D dip_prefixes; + /* We don't allow postincrement when the prefix is DIP, so use a + different table for DIP. */ + prefix_opc_table =3D dip_prefixes; else - prefix_opc_table =3D rest_prefixes; + prefix_opc_table =3D rest_prefixes; } =20 if (prefix_insn !=3D NO_CRIS_PREFIX @@ -1447,104 +1447,104 @@ get_opcode_entry (unsigned int insn, int max_level_of_match =3D -1; =20 for (opcodep =3D cris_opcodes; - opcodep->name !=3D NULL; - opcodep++) - { - int level_of_match; + opcodep->name !=3D NULL; + opcodep++) + { + int level_of_match; =20 - if (disdata->distype =3D=3D cris_dis_v32) - { - switch (opcodep->applicable_version) - { - case cris_ver_version_all: - break; + if (disdata->distype =3D=3D cris_dis_v32) + { + switch (opcodep->applicable_version) + { + case cris_ver_version_all: + break; =20 - case cris_ver_v0_3: - case cris_ver_v0_10: - case cris_ver_v3_10: - case cris_ver_sim_v0_10: - case cris_ver_v8_10: - case cris_ver_v10: - case cris_ver_warning: - continue; + case cris_ver_v0_3: + case cris_ver_v0_10: + case cris_ver_v3_10: + case cris_ver_sim_v0_10: + case cris_ver_v8_10: + case cris_ver_v10: + case cris_ver_warning: + continue; =20 - case cris_ver_v3p: - case cris_ver_v8p: - case cris_ver_v10p: - case cris_ver_v32p: - break; + case cris_ver_v3p: + case cris_ver_v8p: + case cris_ver_v10p: + case cris_ver_v32p: + break; =20 - case cris_ver_v8: - abort (); - default: - abort (); - } - } - else - { - switch (opcodep->applicable_version) - { - case cris_ver_version_all: - case cris_ver_v0_3: - case cris_ver_v3p: - case cris_ver_v0_10: - case cris_ver_v8p: - case cris_ver_v8_10: - case cris_ver_v10: - case cris_ver_sim_v0_10: - case cris_ver_v10p: - case cris_ver_warning: - break; + case cris_ver_v8: + abort (); + default: + abort (); + } + } + else + { + switch (opcodep->applicable_version) + { + case cris_ver_version_all: + case cris_ver_v0_3: + case cris_ver_v3p: + case cris_ver_v0_10: + case cris_ver_v8p: + case cris_ver_v8_10: + case cris_ver_v10: + case cris_ver_sim_v0_10: + case cris_ver_v10p: + case cris_ver_warning: + break; =20 - case cris_ver_v32p: - continue; + case cris_ver_v32p: + continue; =20 - case cris_ver_v8: - abort (); - default: - abort (); - } - } + case cris_ver_v8: + abort (); + default: + abort (); + } + } =20 - /* We give a double lead for bits matching the template in - cris_opcodes. Not even, because then "move p8,r10" would - be given 2 bits lead over "clear.d r10". When there's a - tie, the first entry in the table wins. This is - deliberate, to avoid a more complicated recognition - formula. */ - if ((opcodep->match & insn) =3D=3D opcodep->match - && (opcodep->lose & insn) =3D=3D 0 - && ((level_of_match - =3D cris_constraint (opcodep->args, - insn, - prefix_insn, - disdata)) - >=3D 0) - && ((level_of_match - +=3D 2 * number_of_bits (opcodep->match - | opcodep->lose)) - > max_level_of_match)) - { - max_matchedp =3D opcodep; - max_level_of_match =3D level_of_match; + /* We give a double lead for bits matching the template in + cris_opcodes. Not even, because then "move p8,r10" would + be given 2 bits lead over "clear.d r10". When there's a + tie, the first entry in the table wins. This is + deliberate, to avoid a more complicated recognition + formula. */ + if ((opcodep->match & insn) =3D=3D opcodep->match + && (opcodep->lose & insn) =3D=3D 0 + && ((level_of_match + =3D cris_constraint (opcodep->args, + insn, + prefix_insn, + disdata)) + >=3D 0) + && ((level_of_match + +=3D 2 * number_of_bits (opcodep->match + | opcodep->lose)) + > max_level_of_match)) + { + max_matchedp =3D opcodep; + max_level_of_match =3D level_of_match; =20 - /* If there was a full match, never mind looking - further. */ - if (level_of_match >=3D 2 * 16) - break; - } - } + /* If there was a full match, never mind looking + further. */ + if (level_of_match >=3D 2 * 16) + break; + } + } /* Fill in the new entry. =20 - If there are changes to the opcode-table involving prefixes, and - disassembly then does not work correctly, try removing the - else-clause below that fills in the prefix-table. If that - helps, you need to change the prefix_opc_table setting above, or - something related. */ + If there are changes to the opcode-table involving prefixes, and + disassembly then does not work correctly, try removing the + else-clause below that fills in the prefix-table. If that + helps, you need to change the prefix_opc_table setting above, or + something related. */ if (prefix_insn =3D=3D NO_CRIS_PREFIX) - opc_table[insn] =3D max_matchedp; + opc_table[insn] =3D max_matchedp; else - prefix_opc_table[insn] =3D max_matchedp; + prefix_opc_table[insn] =3D max_matchedp; } =20 return max_matchedp; @@ -1556,9 +1556,9 @@ get_opcode_entry (unsigned int insn, =20 static int cris_constraint (const char *cs, - unsigned int insn, - unsigned int prefix_insn, - struct cris_disasm_data *disdata) + unsigned int insn, + unsigned int prefix_insn, + struct cris_disasm_data *disdata) { int retval =3D 0; int tmp; @@ -1569,136 +1569,136 @@ cris_constraint (const char *cs, switch (*s) { case '!': - /* Do not recognize "pop" if there's a prefix and then only for + /* Do not recognize "pop" if there's a prefix and then only for v0..v10. */ - if (prefix_insn !=3D NO_CRIS_PREFIX - || disdata->distype !=3D cris_dis_v0_v10) - return -1; - break; + if (prefix_insn !=3D NO_CRIS_PREFIX + || disdata->distype !=3D cris_dis_v0_v10) + return -1; + break; =20 case 'U': - /* Not recognized at disassembly. */ - return -1; + /* Not recognized at disassembly. */ + return -1; =20 case 'M': - /* Size modifier for "clear", i.e. special register 0, 4 or 8. - Check that it is one of them. Only special register 12 could - be mismatched, but checking for matches is more logical than - checking for mismatches when there are only a few cases. */ - tmp =3D ((insn >> 12) & 0xf); - if (tmp !=3D 0 && tmp !=3D 4 && tmp !=3D 8) - return -1; - break; + /* Size modifier for "clear", i.e. special register 0, 4 or 8. + Check that it is one of them. Only special register 12 could + be mismatched, but checking for matches is more logical than + checking for mismatches when there are only a few cases. */ + tmp =3D ((insn >> 12) & 0xf); + if (tmp !=3D 0 && tmp !=3D 4 && tmp !=3D 8) + return -1; + break; =20 case 'm': - if ((insn & 0x30) =3D=3D 0x30) - return -1; - break; + if ((insn & 0x30) =3D=3D 0x30) + return -1; + break; =20 case 'S': - /* A prefix operand without side-effect. */ - if (prefix_insn !=3D NO_CRIS_PREFIX && (insn & 0x400) =3D=3D 0) - { - prefix_ok =3D 1; - break; - } - else - return -1; + /* A prefix operand without side-effect. */ + if (prefix_insn !=3D NO_CRIS_PREFIX && (insn & 0x400) =3D=3D 0) + { + prefix_ok =3D 1; + break; + } + else + return -1; =20 case 's': case 'y': case 'Y': - /* If this is a prefixed insn with postincrement (side-effect), - the prefix must not be DIP. */ - if (prefix_insn !=3D NO_CRIS_PREFIX) - { - if (insn & 0x400) - { - const struct cris_opcode *prefix_opcodep - =3D get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata); + /* If this is a prefixed insn with postincrement (side-effect), + the prefix must not be DIP. */ + if (prefix_insn !=3D NO_CRIS_PREFIX) + { + if (insn & 0x400) + { + const struct cris_opcode *prefix_opcodep + =3D get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disda= ta); =20 - if (prefix_opcodep->match =3D=3D DIP_OPCODE) - return -1; - } + if (prefix_opcodep->match =3D=3D DIP_OPCODE) + return -1; + } =20 - prefix_ok =3D 1; - } - break; + prefix_ok =3D 1; + } + break; =20 case 'B': - /* If we don't fall through, then the prefix is ok. */ - prefix_ok =3D 1; + /* If we don't fall through, then the prefix is ok. */ + prefix_ok =3D 1; =20 - /* A "push" prefix. Check for valid "push" size. - In case of special register, it may be !=3D 4. */ - if (prefix_insn !=3D NO_CRIS_PREFIX) - { - /* Match the prefix insn to BDAPQ. */ - const struct cris_opcode *prefix_opcodep - =3D get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata); + /* A "push" prefix. Check for valid "push" size. + In case of special register, it may be !=3D 4. */ + if (prefix_insn !=3D NO_CRIS_PREFIX) + { + /* Match the prefix insn to BDAPQ. */ + const struct cris_opcode *prefix_opcodep + =3D get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata); =20 - if (prefix_opcodep->match =3D=3D BDAP_QUICK_OPCODE) - { - int pushsize =3D (prefix_insn & 255); + if (prefix_opcodep->match =3D=3D BDAP_QUICK_OPCODE) + { + int pushsize =3D (prefix_insn & 255); =20 - if (pushsize > 127) - pushsize -=3D 256; + if (pushsize > 127) + pushsize -=3D 256; =20 - if (s[1] =3D=3D 'P') - { - unsigned int spec_reg =3D (insn >> 12) & 15; - const struct cris_spec_reg *sregp - =3D spec_reg_info (spec_reg, disdata->distype); + if (s[1] =3D=3D 'P') + { + unsigned int spec_reg =3D (insn >> 12) & 15; + const struct cris_spec_reg *sregp + =3D spec_reg_info (spec_reg, disdata->distype); =20 - /* For a special-register, the "prefix size" must - match the size of the register. */ - if (sregp && sregp->reg_size =3D=3D (unsigned int) -pushsize) - break; - } - else if (s[1] =3D=3D 'R') - { - if ((insn & 0x30) =3D=3D 0x20 && pushsize =3D=3D -4) - break; - } - /* FIXME: Should abort here; next constraint letter - *must* be 'P' or 'R'. */ - } - } - return -1; + /* For a special-register, the "prefix size" must + match the size of the register. */ + if (sregp && sregp->reg_size =3D=3D (unsigned int) -pu= shsize) + break; + } + else if (s[1] =3D=3D 'R') + { + if ((insn & 0x30) =3D=3D 0x20 && pushsize =3D=3D -4) + break; + } + /* FIXME: Should abort here; next constraint letter + *must* be 'P' or 'R'. */ + } + } + return -1; =20 case 'D': - retval =3D (((insn >> 12) & 15) =3D=3D (insn & 15)); - if (!retval) - return -1; - else - retval +=3D 4; - break; + retval =3D (((insn >> 12) & 15) =3D=3D (insn & 15)); + if (!retval) + return -1; + else + retval +=3D 4; + break; =20 case 'P': - { - const struct cris_spec_reg *sregp - =3D spec_reg_info ((insn >> 12) & 15, disdata->distype); + { + const struct cris_spec_reg *sregp + =3D spec_reg_info ((insn >> 12) & 15, disdata->distype); =20 - /* Since we match four bits, we will give a value of 4-1 =3D 3 - in a match. If there is a corresponding exact match of a - special register in another pattern, it will get a value of - 4, which will be higher. This should be correct in that an - exact pattern would match better than a general pattern. + /* Since we match four bits, we will give a value of 4-1 =3D 3 + in a match. If there is a corresponding exact match of a + special register in another pattern, it will get a value of + 4, which will be higher. This should be correct in that an + exact pattern would match better than a general pattern. =20 - Note that there is a reason for not returning zero; the - pattern for "clear" is partly matched in the bit-pattern - (the two lower bits must be zero), while the bit-pattern - for a move from a special register is matched in the - register constraint. */ + Note that there is a reason for not returning zero; the + pattern for "clear" is partly matched in the bit-pattern + (the two lower bits must be zero), while the bit-pattern + for a move from a special register is matched in the + register constraint. */ =20 - if (sregp !=3D NULL) - { - retval +=3D 3; - break; - } - else - return -1; - } + if (sregp !=3D NULL) + { + retval +=3D 3; + break; + } + else + return -1; + } } =20 if (prefix_insn !=3D NO_CRIS_PREFIX && ! prefix_ok) @@ -1711,8 +1711,8 @@ cris_constraint (const char *cs, =20 static char * format_hex (unsigned long number, - char *outbuffer, - struct cris_disasm_data *disdata) + char *outbuffer, + struct cris_disasm_data *disdata) { /* Truncate negative numbers on >32-bit hosts. */ number &=3D 0xffffffff; @@ -1743,9 +1743,9 @@ format_dec (long number, char *outbuffer, size_t outs= ize, int signedp) =20 static char * format_reg (struct cris_disasm_data *disdata, - int regno, - char *outbuffer_start, - bfd_boolean with_reg_prefix) + int regno, + char *outbuffer_start, + bfd_boolean with_reg_prefix) { char *outbuffer =3D outbuffer_start; =20 @@ -1757,9 +1757,9 @@ format_reg (struct cris_disasm_data *disdata, case 15: /* For v32, there is no context in which we output PC. */ if (disdata->distype =3D=3D cris_dis_v32) - strcpy (outbuffer, "acr"); + strcpy (outbuffer, "acr"); else - strcpy (outbuffer, "pc"); + strcpy (outbuffer, "pc"); break; =20 case 14: @@ -1778,8 +1778,8 @@ format_reg (struct cris_disasm_data *disdata, =20 static char * format_sup_reg (unsigned int regno, - char *outbuffer_start, - bfd_boolean with_reg_prefix) + char *outbuffer_start, + bfd_boolean with_reg_prefix) { char *outbuffer =3D outbuffer_start; int i; @@ -1790,8 +1790,8 @@ format_sup_reg (unsigned int regno, for (i =3D 0; cris_support_regs[i].name !=3D NULL; i++) if (cris_support_regs[i].number =3D=3D regno) { - sprintf (outbuffer, "%s", cris_support_regs[i].name); - return outbuffer_start + strlen (outbuffer_start); + sprintf (outbuffer, "%s", cris_support_regs[i].name); + return outbuffer_start + strlen (outbuffer_start); } =20 /* There's supposed to be register names covering all numbers, though @@ -1804,9 +1804,9 @@ format_sup_reg (unsigned int regno, =20 static unsigned bytes_to_skip (unsigned int insn, - const struct cris_opcode *matchedp, - enum cris_disass_family distype, - const struct cris_opcode *prefix_matchedp) + const struct cris_opcode *matchedp, + enum cris_disass_family distype, + const struct cris_opcode *prefix_matchedp) { /* Each insn is a word plus "immediate" operands. */ unsigned to_skip =3D 2; @@ -1815,33 +1815,33 @@ bytes_to_skip (unsigned int insn, =20 for (s =3D template; *s; s++) if ((*s =3D=3D 's' || *s =3D=3D 'N' || *s =3D=3D 'Y') - && (insn & 0x400) && (insn & 15) =3D=3D 15 - && prefix_matchedp =3D=3D NULL) + && (insn & 0x400) && (insn & 15) =3D=3D 15 + && prefix_matchedp =3D=3D NULL) { - /* Immediate via [pc+], so we have to check the size of the - operand. */ - int mode_size =3D 1 << ((insn >> 4) & (*template =3D=3D 'z' ? 1 : 3)); + /* Immediate via [pc+], so we have to check the size of the + operand. */ + int mode_size =3D 1 << ((insn >> 4) & (*template =3D=3D 'z' ? 1 : = 3)); =20 - if (matchedp->imm_oprnd_size =3D=3D SIZE_FIX_32) - to_skip +=3D 4; - else if (matchedp->imm_oprnd_size =3D=3D SIZE_SPEC_REG) - { - const struct cris_spec_reg *sregp - =3D spec_reg_info ((insn >> 12) & 15, distype); + if (matchedp->imm_oprnd_size =3D=3D SIZE_FIX_32) + to_skip +=3D 4; + else if (matchedp->imm_oprnd_size =3D=3D SIZE_SPEC_REG) + { + const struct cris_spec_reg *sregp + =3D spec_reg_info ((insn >> 12) & 15, distype); =20 - /* FIXME: Improve error handling; should have been caught - earlier. */ - if (sregp =3D=3D NULL) - return 2; + /* FIXME: Improve error handling; should have been caught + earlier. */ + if (sregp =3D=3D NULL) + return 2; =20 - /* PC is incremented by two, not one, for a byte. Except on - CRISv32, where constants are always DWORD-size for - special registers. */ - to_skip +=3D - distype =3D=3D cris_dis_v32 ? 4 : (sregp->reg_size + 1) & ~1; - } - else - to_skip +=3D (mode_size + 1) & ~1; + /* PC is incremented by two, not one, for a byte. Except on + CRISv32, where constants are always DWORD-size for + special registers. */ + to_skip +=3D + distype =3D=3D cris_dis_v32 ? 4 : (sregp->reg_size + 1) & ~1; + } + else + to_skip +=3D (mode_size + 1) & ~1; } else if (*s =3D=3D 'n') to_skip +=3D 4; @@ -1888,17 +1888,17 @@ print_flags (struct cris_disasm_data *disdata, unsi= gned int insn, char *cp) =20 static void print_with_operands (const struct cris_opcode *opcodep, - unsigned int insn, - unsigned char *buffer, - bfd_vma addr, - disassemble_info *info, - /* If a prefix insn was before this insn (and is supposed - to be output as an address), here is a description of - it. */ - const struct cris_opcode *prefix_opcodep, - unsigned int prefix_insn, - unsigned char *prefix_buffer, - bfd_boolean with_reg_prefix) + unsigned int insn, + unsigned char *buffer, + bfd_vma addr, + disassemble_info *info, + /* If a prefix insn was before this insn (and is supp= osed + to be output as an address), here is a description= of + it. */ + const struct cris_opcode *prefix_opcodep, + unsigned int prefix_insn, + unsigned char *prefix_buffer, + bfd_boolean with_reg_prefix) { /* Get a buffer of somewhat reasonable size where we store intermediate parts of the insn. */ @@ -1926,9 +1926,9 @@ print_with_operands (const struct cris_opcode *opcode= p, =20 /* Get the size-letter. */ *tp++ =3D *s =3D=3D 'M' - ? (insn & 0x8000 ? 'd' - : insn & 0x4000 ? 'w' : 'b') - : mode_char[(insn >> 4) & (*s =3D=3D 'z' ? 1 : 3)]; + ? (insn & 0x8000 ? 'd' + : insn & 0x4000 ? 'w' : 'b') + : mode_char[(insn >> 4) & (*s =3D=3D 'z' ? 1 : 3)]; =20 /* Ignore the size and the space character that follows. */ s +=3D 2; @@ -1944,11 +1944,11 @@ print_with_operands (const struct cris_opcode *opco= dep, if (opcodep->name[0] =3D=3D 'j') { if (CONST_STRNEQ (opcodep->name, "jsr")) - /* It's "jsr" or "jsrc". */ - info->insn_type =3D dis_jsr; + /* It's "jsr" or "jsrc". */ + info->insn_type =3D dis_jsr; else - /* Any other jump-type insn is considered a branch. */ - info->insn_type =3D dis_branch; + /* Any other jump-type insn is considered a branch. */ + info->insn_type =3D dis_branch; } =20 /* We might know some more fields right now. */ @@ -1960,475 +1960,475 @@ print_with_operands (const struct cris_opcode *op= codep, switch (*s) { case 'T': - tp =3D format_sup_reg ((insn >> 12) & 15, tp, with_reg_prefix); - break; + tp =3D format_sup_reg ((insn >> 12) & 15, tp, with_reg_prefix); + break; =20 case 'A': - if (with_reg_prefix) - *tp++ =3D REGISTER_PREFIX_CHAR; - *tp++ =3D 'a'; - *tp++ =3D 'c'; - *tp++ =3D 'r'; - break; + if (with_reg_prefix) + *tp++ =3D REGISTER_PREFIX_CHAR; + *tp++ =3D 'a'; + *tp++ =3D 'c'; + *tp++ =3D 'r'; + break; =20 case '[': case ']': case ',': - *tp++ =3D *s; - break; + *tp++ =3D *s; + break; =20 case '!': - /* Ignore at this point; used at earlier stages to avoid - recognition if there's a prefix at something that in other - ways looks like a "pop". */ - break; + /* Ignore at this point; used at earlier stages to avoid + recognition if there's a prefix at something that in other + ways looks like a "pop". */ + break; =20 case 'd': - /* Ignore. This is an optional ".d " on the large one of - relaxable insns. */ - break; + /* Ignore. This is an optional ".d " on the large one of + relaxable insns. */ + break; =20 case 'B': - /* This was the prefix that made this a "push". We've already - handled it by recognizing it, so signal that the prefix is - handled by setting it to NULL. */ - prefix_opcodep =3D NULL; - break; + /* This was the prefix that made this a "push". We've already + handled it by recognizing it, so signal that the prefix is + handled by setting it to NULL. */ + prefix_opcodep =3D NULL; + break; =20 case 'D': case 'r': - tp =3D format_reg (disdata, insn & 15, tp, with_reg_prefix); - break; + tp =3D format_reg (disdata, insn & 15, tp, with_reg_prefix); + break; =20 case 'R': - tp =3D format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix); - break; + tp =3D format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix= ); + break; =20 case 'n': - { - /* Like N but pc-relative to the start of the insn. */ - uint32_t number - =3D (buffer[2] + buffer[3] * 256 + buffer[4] * 65536 - + buffer[5] * 0x1000000 + addr); + { + /* Like N but pc-relative to the start of the insn. */ + uint32_t number + =3D (buffer[2] + buffer[3] * 256 + buffer[4] * 65536 + + buffer[5] * 0x1000000 + addr); =20 - /* Finish off and output previous formatted bytes. */ - *tp =3D 0; - if (temp[0]) - (*info->fprintf_func) (info->stream, "%s", temp); - tp =3D temp; + /* Finish off and output previous formatted bytes. */ + *tp =3D 0; + if (temp[0]) + (*info->fprintf_func) (info->stream, "%s", temp); + tp =3D temp; =20 - (*info->print_address_func) ((bfd_vma) number, info); - } - break; + (*info->print_address_func) ((bfd_vma) number, info); + } + break; =20 case 'u': - { - /* Like n but the offset is bits <3:0> in the instruction. */ - unsigned long number =3D (buffer[0] & 0xf) * 2 + addr; + { + /* Like n but the offset is bits <3:0> in the instruction. */ + unsigned long number =3D (buffer[0] & 0xf) * 2 + addr; =20 - /* Finish off and output previous formatted bytes. */ - *tp =3D 0; - if (temp[0]) - (*info->fprintf_func) (info->stream, "%s", temp); - tp =3D temp; + /* Finish off and output previous formatted bytes. */ + *tp =3D 0; + if (temp[0]) + (*info->fprintf_func) (info->stream, "%s", temp); + tp =3D temp; =20 - (*info->print_address_func) ((bfd_vma) number, info); - } - break; + (*info->print_address_func) ((bfd_vma) number, info); + } + break; =20 case 'N': case 'y': case 'Y': case 'S': case 's': - /* Any "normal" memory operand. */ - if ((insn & 0x400) && (insn & 15) =3D=3D 15 && prefix_opcodep =3D=3D NULL) - { - /* We're looking at [pc+], i.e. we need to output an immediate - number, where the size can depend on different things. */ - int32_t number; - int signedp - =3D ((*cs =3D=3D 'z' && (insn & 0x20)) - || opcodep->match =3D=3D BDAP_QUICK_OPCODE); - int nbytes; + /* Any "normal" memory operand. */ + if ((insn & 0x400) && (insn & 15) =3D=3D 15 && prefix_opcodep =3D= =3D NULL) + { + /* We're looking at [pc+], i.e. we need to output an immediate + number, where the size can depend on different things. */ + int32_t number; + int signedp + =3D ((*cs =3D=3D 'z' && (insn & 0x20)) + || opcodep->match =3D=3D BDAP_QUICK_OPCODE); + int nbytes; =20 - if (opcodep->imm_oprnd_size =3D=3D SIZE_FIX_32) - nbytes =3D 4; - else if (opcodep->imm_oprnd_size =3D=3D SIZE_SPEC_REG) - { - const struct cris_spec_reg *sregp - =3D spec_reg_info ((insn >> 12) & 15, disdata->distype); + if (opcodep->imm_oprnd_size =3D=3D SIZE_FIX_32) + nbytes =3D 4; + else if (opcodep->imm_oprnd_size =3D=3D SIZE_SPEC_REG) + { + const struct cris_spec_reg *sregp + =3D spec_reg_info ((insn >> 12) & 15, disdata->distype); =20 - /* A NULL return should have been as a non-match earlier, - so catch it as an internal error in the error-case - below. */ - if (sregp =3D=3D NULL) - /* Whatever non-valid size. */ - nbytes =3D 42; - else - /* PC is always incremented by a multiple of two. - For CRISv32, immediates are always 4 bytes for - special registers. */ - nbytes =3D disdata->distype =3D=3D cris_dis_v32 - ? 4 : (sregp->reg_size + 1) & ~1; - } - else - { - int mode_size =3D 1 << ((insn >> 4) & (*cs =3D=3D 'z' ? 1 : 3)); + /* A NULL return should have been as a non-match earlier, + so catch it as an internal error in the error-case + below. */ + if (sregp =3D=3D NULL) + /* Whatever non-valid size. */ + nbytes =3D 42; + else + /* PC is always incremented by a multiple of two. + For CRISv32, immediates are always 4 bytes for + special registers. */ + nbytes =3D disdata->distype =3D=3D cris_dis_v32 + ? 4 : (sregp->reg_size + 1) & ~1; + } + else + { + int mode_size =3D 1 << ((insn >> 4) & (*cs =3D=3D 'z' ? 1 = : 3)); =20 - if (mode_size =3D=3D 1) - nbytes =3D 2; - else - nbytes =3D mode_size; - } + if (mode_size =3D=3D 1) + nbytes =3D 2; + else + nbytes =3D mode_size; + } =20 - switch (nbytes) - { - case 1: - number =3D buffer[2]; - if (signedp && number > 127) - number -=3D 256; - break; + switch (nbytes) + { + case 1: + number =3D buffer[2]; + if (signedp && number > 127) + number -=3D 256; + break; =20 - case 2: - number =3D buffer[2] + buffer[3] * 256; - if (signedp && number > 32767) - number -=3D 65536; - break; + case 2: + number =3D buffer[2] + buffer[3] * 256; + if (signedp && number > 32767) + number -=3D 65536; + break; =20 - case 4: - number - =3D buffer[2] + buffer[3] * 256 + buffer[4] * 65536 - + buffer[5] * 0x1000000; - break; + case 4: + number + =3D buffer[2] + buffer[3] * 256 + buffer[4] * 65536 + + buffer[5] * 0x1000000; + break; =20 - default: - strcpy (tp, "bug"); - tp +=3D 3; - number =3D 42; - } + default: + strcpy (tp, "bug"); + tp +=3D 3; + number =3D 42; + } =20 - if ((*cs =3D=3D 'z' && (insn & 0x20)) - || (opcodep->match =3D=3D BDAP_QUICK_OPCODE - && (nbytes <=3D 2 || buffer[1 + nbytes] =3D=3D 0))) - tp =3D FORMAT_DEC (number, tp, signedp); - else - { - unsigned int highbyte =3D (number >> 24) & 0xff; + if ((*cs =3D=3D 'z' && (insn & 0x20)) + || (opcodep->match =3D=3D BDAP_QUICK_OPCODE + && (nbytes <=3D 2 || buffer[1 + nbytes] =3D=3D 0))) + tp =3D FORMAT_DEC (number, tp, signedp); + else + { + unsigned int highbyte =3D (number >> 24) & 0xff; =20 - /* Either output this as an address or as a number. If it's - a dword with the same high-byte as the address of the - insn, assume it's an address, and also if it's a non-zero - non-0xff high-byte. If this is a jsr or a jump, then - it's definitely an address. */ - if (nbytes =3D=3D 4 - && (highbyte =3D=3D ((addr >> 24) & 0xff) - || (highbyte !=3D 0 && highbyte !=3D 0xff) - || info->insn_type =3D=3D dis_branch - || info->insn_type =3D=3D dis_jsr)) - { - /* Finish off and output previous formatted bytes. */ - *tp =3D 0; - tp =3D temp; - if (temp[0]) - (*info->fprintf_func) (info->stream, "%s", temp); + /* Either output this as an address or as a number. If it= 's + a dword with the same high-byte as the address of the + insn, assume it's an address, and also if it's a non-ze= ro + non-0xff high-byte. If this is a jsr or a jump, then + it's definitely an address. */ + if (nbytes =3D=3D 4 + && (highbyte =3D=3D ((addr >> 24) & 0xff) + || (highbyte !=3D 0 && highbyte !=3D 0xff) + || info->insn_type =3D=3D dis_branch + || info->insn_type =3D=3D dis_jsr)) + { + /* Finish off and output previous formatted bytes. */ + *tp =3D 0; + tp =3D temp; + if (temp[0]) + (*info->fprintf_func) (info->stream, "%s", temp); =20 - (*info->print_address_func) ((bfd_vma) number, info); + (*info->print_address_func) ((bfd_vma) number, info); =20 - info->target =3D number; - } - else - tp =3D format_hex (number, tp, disdata); - } - } - else - { - /* Not an immediate number. Then this is a (possibly - prefixed) memory operand. */ - if (info->insn_type !=3D dis_nonbranch) - { - int mode_size - =3D 1 << ((insn >> 4) - & (opcodep->args[0] =3D=3D 'z' ? 1 : 3)); - int size; - info->insn_type =3D dis_dref; - info->flags |=3D CRIS_DIS_FLAG_MEMREF; + info->target =3D number; + } + else + tp =3D format_hex (number, tp, disdata); + } + } + else + { + /* Not an immediate number. Then this is a (possibly + prefixed) memory operand. */ + if (info->insn_type !=3D dis_nonbranch) + { + int mode_size + =3D 1 << ((insn >> 4) + & (opcodep->args[0] =3D=3D 'z' ? 1 : 3)); + int size; + info->insn_type =3D dis_dref; + info->flags |=3D CRIS_DIS_FLAG_MEMREF; =20 - if (opcodep->imm_oprnd_size =3D=3D SIZE_FIX_32) - size =3D 4; - else if (opcodep->imm_oprnd_size =3D=3D SIZE_SPEC_REG) - { - const struct cris_spec_reg *sregp - =3D spec_reg_info ((insn >> 12) & 15, disdata->distype); + if (opcodep->imm_oprnd_size =3D=3D SIZE_FIX_32) + size =3D 4; + else if (opcodep->imm_oprnd_size =3D=3D SIZE_SPEC_REG) + { + const struct cris_spec_reg *sregp + =3D spec_reg_info ((insn >> 12) & 15, disdata->disty= pe); =20 - /* FIXME: Improve error handling; should have been caught - earlier. */ - if (sregp =3D=3D NULL) - size =3D 4; - else - size =3D sregp->reg_size; - } - else - size =3D mode_size; + /* FIXME: Improve error handling; should have been cau= ght + earlier. */ + if (sregp =3D=3D NULL) + size =3D 4; + else + size =3D sregp->reg_size; + } + else + size =3D mode_size; =20 - info->data_size =3D size; - } + info->data_size =3D size; + } =20 - *tp++ =3D '['; + *tp++ =3D '['; =20 - if (prefix_opcodep - /* We don't match dip with a postincremented field - as a side-effect address mode. */ - && ((insn & 0x400) =3D=3D 0 - || prefix_opcodep->match !=3D DIP_OPCODE)) - { - if (insn & 0x400) - { - tp =3D format_reg (disdata, insn & 15, tp, with_reg_prefix); - *tp++ =3D '=3D'; - } + if (prefix_opcodep + /* We don't match dip with a postincremented field + as a side-effect address mode. */ + && ((insn & 0x400) =3D=3D 0 + || prefix_opcodep->match !=3D DIP_OPCODE)) + { + if (insn & 0x400) + { + tp =3D format_reg (disdata, insn & 15, tp, with_reg_pr= efix); + *tp++ =3D '=3D'; + } =20 =20 - /* We mainly ignore the prefix format string when the - address-mode syntax is output. */ - switch (prefix_opcodep->match) - { - case DIP_OPCODE: - /* It's [r], [r+] or [pc+]. */ - if ((prefix_insn & 0x400) && (prefix_insn & 15) =3D=3D 15) - { - /* It's [pc+]. This cannot possibly be anything - but an address. */ - uint32_t number - =3D prefix_buffer[2] + prefix_buffer[3] * 256 - + prefix_buffer[4] * 65536 - + prefix_buffer[5] * 0x1000000; + /* We mainly ignore the prefix format string when the + address-mode syntax is output. */ + switch (prefix_opcodep->match) + { + case DIP_OPCODE: + /* It's [r], [r+] or [pc+]. */ + if ((prefix_insn & 0x400) && (prefix_insn & 15) =3D=3D= 15) + { + /* It's [pc+]. This cannot possibly be anything + but an address. */ + uint32_t number + =3D prefix_buffer[2] + prefix_buffer[3] * 256 + + prefix_buffer[4] * 65536 + + prefix_buffer[5] * 0x1000000; =20 - info->target =3D (bfd_vma) number; + info->target =3D (bfd_vma) number; =20 - /* Finish off and output previous formatted - data. */ - *tp =3D 0; - tp =3D temp; - if (temp[0]) - (*info->fprintf_func) (info->stream, "%s", temp); + /* Finish off and output previous formatted + data. */ + *tp =3D 0; + tp =3D temp; + if (temp[0]) + (*info->fprintf_func) (info->stream, "%s", temp); =20 - (*info->print_address_func) ((bfd_vma) number, info); - } - else - { - /* For a memref in an address, we use target2. - In this case, target is zero. */ - info->flags - |=3D (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG - | CRIS_DIS_FLAG_MEM_TARGET2_MEM); + (*info->print_address_func) ((bfd_vma) number, inf= o); + } + else + { + /* For a memref in an address, we use target2. + In this case, target is zero. */ + info->flags + |=3D (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG + | CRIS_DIS_FLAG_MEM_TARGET2_MEM); =20 - info->target2 =3D prefix_insn & 15; + info->target2 =3D prefix_insn & 15; =20 - *tp++ =3D '['; - tp =3D format_reg (disdata, prefix_insn & 15, tp, - with_reg_prefix); - if (prefix_insn & 0x400) - *tp++ =3D '+'; - *tp++ =3D ']'; - } - break; + *tp++ =3D '['; + tp =3D format_reg (disdata, prefix_insn & 15, tp, + with_reg_prefix); + if (prefix_insn & 0x400) + *tp++ =3D '+'; + *tp++ =3D ']'; + } + break; =20 - case BDAP_QUICK_OPCODE: - { - int number; + case BDAP_QUICK_OPCODE: + { + int number; =20 - number =3D prefix_buffer[0]; - if (number > 127) - number -=3D 256; + number =3D prefix_buffer[0]; + if (number > 127) + number -=3D 256; =20 - /* Output "reg+num" or, if num < 0, "reg-num". */ - tp =3D format_reg (disdata, (prefix_insn >> 12) & 15, tp, - with_reg_prefix); - if (number >=3D 0) - *tp++ =3D '+'; - tp =3D FORMAT_DEC (number, tp, 1); + /* Output "reg+num" or, if num < 0, "reg-num". */ + tp =3D format_reg (disdata, (prefix_insn >> 12) & 15= , tp, + with_reg_prefix); + if (number >=3D 0) + *tp++ =3D '+'; + tp =3D FORMAT_DEC (number, tp, 1); =20 - info->flags |=3D CRIS_DIS_FLAG_MEM_TARGET_IS_REG; - info->target =3D (prefix_insn >> 12) & 15; - info->target2 =3D (bfd_vma) number; - break; - } + info->flags |=3D CRIS_DIS_FLAG_MEM_TARGET_IS_REG; + info->target =3D (prefix_insn >> 12) & 15; + info->target2 =3D (bfd_vma) number; + break; + } =20 - case BIAP_OPCODE: - /* Output "r+R.m". */ - tp =3D format_reg (disdata, prefix_insn & 15, tp, - with_reg_prefix); - *tp++ =3D '+'; - tp =3D format_reg (disdata, (prefix_insn >> 12) & 15, tp, - with_reg_prefix); - *tp++ =3D '.'; - *tp++ =3D mode_char[(prefix_insn >> 4) & 3]; + case BIAP_OPCODE: + /* Output "r+R.m". */ + tp =3D format_reg (disdata, prefix_insn & 15, tp, + with_reg_prefix); + *tp++ =3D '+'; + tp =3D format_reg (disdata, (prefix_insn >> 12) & 15, = tp, + with_reg_prefix); + *tp++ =3D '.'; + *tp++ =3D mode_char[(prefix_insn >> 4) & 3]; =20 - info->flags - |=3D (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG - | CRIS_DIS_FLAG_MEM_TARGET_IS_REG + info->flags + |=3D (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG + | CRIS_DIS_FLAG_MEM_TARGET_IS_REG =20 - | ((prefix_insn & 0x8000) - ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4 - : ((prefix_insn & 0x8000) - ? CRIS_DIS_FLAG_MEM_TARGET2_MULT2 : 0))); + | ((prefix_insn & 0x8000) + ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4 + : ((prefix_insn & 0x8000) + ? CRIS_DIS_FLAG_MEM_TARGET2_MULT2 : 0))); =20 - /* Is it the casejump? It's a "adds.w [pc+r%d.w],pc". */ - if (insn =3D=3D 0xf83f && (prefix_insn & ~0xf000) =3D=3D 0x55f) - /* Then start interpreting data as offsets. */ - case_offset_counter =3D no_of_case_offsets; - break; + /* Is it the casejump? It's a "adds.w [pc+r%d.w],pc".= */ + if (insn =3D=3D 0xf83f && (prefix_insn & ~0xf000) =3D= =3D 0x55f) + /* Then start interpreting data as offsets. */ + case_offset_counter =3D no_of_case_offsets; + break; =20 - case BDAP_INDIR_OPCODE: - /* Output "r+s.m", or, if "s" is [pc+], "r+s" or - "r-s". */ - tp =3D format_reg (disdata, (prefix_insn >> 12) & 15, tp, - with_reg_prefix); + case BDAP_INDIR_OPCODE: + /* Output "r+s.m", or, if "s" is [pc+], "r+s" or + "r-s". */ + tp =3D format_reg (disdata, (prefix_insn >> 12) & 15, = tp, + with_reg_prefix); =20 - if ((prefix_insn & 0x400) && (prefix_insn & 15) =3D=3D 15) - { - int32_t number; - unsigned int nbytes; + if ((prefix_insn & 0x400) && (prefix_insn & 15) =3D=3D= 15) + { + int32_t number; + unsigned int nbytes; =20 - /* It's a value. Get its size. */ - int mode_size =3D 1 << ((prefix_insn >> 4) & 3); + /* It's a value. Get its size. */ + int mode_size =3D 1 << ((prefix_insn >> 4) & 3); =20 - if (mode_size =3D=3D 1) - nbytes =3D 2; - else - nbytes =3D mode_size; + if (mode_size =3D=3D 1) + nbytes =3D 2; + else + nbytes =3D mode_size; =20 - switch (nbytes) - { - case 1: - number =3D prefix_buffer[2]; - if (number > 127) - number -=3D 256; - break; + switch (nbytes) + { + case 1: + number =3D prefix_buffer[2]; + if (number > 127) + number -=3D 256; + break; =20 - case 2: - number =3D prefix_buffer[2] + prefix_buffer[3] * 256; - if (number > 32767) - number -=3D 65536; - break; + case 2: + number =3D prefix_buffer[2] + prefix_buffer[3]= * 256; + if (number > 32767) + number -=3D 65536; + break; =20 - case 4: - number - =3D prefix_buffer[2] + prefix_buffer[3] * 256 - + prefix_buffer[4] * 65536 - + prefix_buffer[5] * 0x1000000; - break; + case 4: + number + =3D prefix_buffer[2] + prefix_buffer[3] * 256 + + prefix_buffer[4] * 65536 + + prefix_buffer[5] * 0x1000000; + break; =20 - default: - strcpy (tp, "bug"); - tp +=3D 3; - number =3D 42; - } + default: + strcpy (tp, "bug"); + tp +=3D 3; + number =3D 42; + } =20 - info->flags |=3D CRIS_DIS_FLAG_MEM_TARGET_IS_REG; - info->target2 =3D (bfd_vma) number; + info->flags |=3D CRIS_DIS_FLAG_MEM_TARGET_IS_REG; + info->target2 =3D (bfd_vma) number; =20 - /* If the size is dword, then assume it's an - address. */ - if (nbytes =3D=3D 4) - { - /* Finish off and output previous formatted - bytes. */ - *tp++ =3D '+'; - *tp =3D 0; - tp =3D temp; - (*info->fprintf_func) (info->stream, "%s", temp); + /* If the size is dword, then assume it's an + address. */ + if (nbytes =3D=3D 4) + { + /* Finish off and output previous formatted + bytes. */ + *tp++ =3D '+'; + *tp =3D 0; + tp =3D temp; + (*info->fprintf_func) (info->stream, "%s", tem= p); =20 - (*info->print_address_func) ((bfd_vma) number, info); - } - else - { - if (number >=3D 0) - *tp++ =3D '+'; - tp =3D FORMAT_DEC (number, tp, 1); - } - } - else - { - /* Output "r+[R].m" or "r+[R+].m". */ - *tp++ =3D '+'; - *tp++ =3D '['; - tp =3D format_reg (disdata, prefix_insn & 15, tp, - with_reg_prefix); - if (prefix_insn & 0x400) - *tp++ =3D '+'; - *tp++ =3D ']'; - *tp++ =3D '.'; - *tp++ =3D mode_char[(prefix_insn >> 4) & 3]; + (*info->print_address_func) ((bfd_vma) number,= info); + } + else + { + if (number >=3D 0) + *tp++ =3D '+'; + tp =3D FORMAT_DEC (number, tp, 1); + } + } + else + { + /* Output "r+[R].m" or "r+[R+].m". */ + *tp++ =3D '+'; + *tp++ =3D '['; + tp =3D format_reg (disdata, prefix_insn & 15, tp, + with_reg_prefix); + if (prefix_insn & 0x400) + *tp++ =3D '+'; + *tp++ =3D ']'; + *tp++ =3D '.'; + *tp++ =3D mode_char[(prefix_insn >> 4) & 3]; =20 - info->flags - |=3D (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG - | CRIS_DIS_FLAG_MEM_TARGET2_MEM - | CRIS_DIS_FLAG_MEM_TARGET_IS_REG + info->flags + |=3D (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG + | CRIS_DIS_FLAG_MEM_TARGET2_MEM + | CRIS_DIS_FLAG_MEM_TARGET_IS_REG =20 - | (((prefix_insn >> 4) =3D=3D 2) - ? 0 - : (((prefix_insn >> 4) & 3) =3D=3D 1 - ? CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD - : CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE))); - } - break; + | (((prefix_insn >> 4) =3D=3D 2) + ? 0 + : (((prefix_insn >> 4) & 3) =3D=3D 1 + ? CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD + : CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE))= ); + } + break; =20 - default: - (*info->fprintf_func) (info->stream, "?prefix-bug"); - } + default: + (*info->fprintf_func) (info->stream, "?prefix-bug"); + } =20 - /* To mark that the prefix is used, reset it. */ - prefix_opcodep =3D NULL; - } - else - { - tp =3D format_reg (disdata, insn & 15, tp, with_reg_prefix); + /* To mark that the prefix is used, reset it. */ + prefix_opcodep =3D NULL; + } + else + { + tp =3D format_reg (disdata, insn & 15, tp, with_reg_prefix= ); =20 - info->flags |=3D CRIS_DIS_FLAG_MEM_TARGET_IS_REG; - info->target =3D insn & 15; + info->flags |=3D CRIS_DIS_FLAG_MEM_TARGET_IS_REG; + info->target =3D insn & 15; =20 - if (insn & 0x400) - *tp++ =3D '+'; - } - *tp++ =3D ']'; - } - break; + if (insn & 0x400) + *tp++ =3D '+'; + } + *tp++ =3D ']'; + } + break; =20 case 'x': - tp =3D format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix); - *tp++ =3D '.'; - *tp++ =3D mode_char[(insn >> 4) & 3]; - break; + tp =3D format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix= ); + *tp++ =3D '.'; + *tp++ =3D mode_char[(insn >> 4) & 3]; + break; =20 case 'I': - tp =3D FORMAT_DEC (insn & 63, tp, 0); - break; + tp =3D FORMAT_DEC (insn & 63, tp, 0); + break; =20 case 'b': - { - int where =3D buffer[2] + buffer[3] * 256; + { + int where =3D buffer[2] + buffer[3] * 256; =20 - if (where > 32767) - where -=3D 65536; + if (where > 32767) + where -=3D 65536; =20 - where +=3D addr + ((disdata->distype =3D=3D cris_dis_v32) ? 0 : 4); + where +=3D addr + ((disdata->distype =3D=3D cris_dis_v32) ? 0 : = 4); =20 - if (insn =3D=3D BA_PC_INCR_OPCODE) - info->insn_type =3D dis_branch; - else - info->insn_type =3D dis_condbranch; + if (insn =3D=3D BA_PC_INCR_OPCODE) + info->insn_type =3D dis_branch; + else + info->insn_type =3D dis_condbranch; =20 - info->target =3D (bfd_vma) where; + info->target =3D (bfd_vma) where; =20 - *tp =3D 0; - tp =3D temp; - (*info->fprintf_func) (info->stream, "%s%s ", - temp, cris_cc_strings[insn >> 12]); + *tp =3D 0; + tp =3D temp; + (*info->fprintf_func) (info->stream, "%s%s ", + temp, cris_cc_strings[insn >> 12]); =20 - (*info->print_address_func) ((bfd_vma) where, info); - } + (*info->print_address_func) ((bfd_vma) where, info); + } break; =20 case 'c': @@ -2441,37 +2441,37 @@ print_with_operands (const struct cris_opcode *opco= dep, =20 case 'o': { - long offset =3D insn & 0xfe; - bfd_vma target; + long offset =3D insn & 0xfe; + bfd_vma target; =20 - if (insn & 1) - offset |=3D ~0xff; + if (insn & 1) + offset |=3D ~0xff; =20 - if (opcodep->match =3D=3D BA_QUICK_OPCODE) - info->insn_type =3D dis_branch; - else - info->insn_type =3D dis_condbranch; + if (opcodep->match =3D=3D BA_QUICK_OPCODE) + info->insn_type =3D dis_branch; + else + info->insn_type =3D dis_condbranch; =20 - target =3D addr + ((disdata->distype =3D=3D cris_dis_v32) ? 0 : 2) + offs= et; - info->target =3D target; - *tp =3D 0; - tp =3D temp; - (*info->fprintf_func) (info->stream, "%s", temp); - (*info->print_address_func) (target, info); + target =3D addr + ((disdata->distype =3D=3D cris_dis_v32) ? 0 : 2)= + offset; + info->target =3D target; + *tp =3D 0; + tp =3D temp; + (*info->fprintf_func) (info->stream, "%s", temp); + (*info->print_address_func) (target, info); } break; =20 case 'Q': case 'O': { - long number =3D buffer[0]; + long number =3D buffer[0]; =20 - if (number > 127) - number =3D number - 256; + if (number > 127) + number =3D number - 256; =20 - tp =3D FORMAT_DEC (number, tp, 1); - *tp++ =3D ','; - tp =3D format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix); + tp =3D FORMAT_DEC (number, tp, 1); + *tp++ =3D ','; + tp =3D format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix= ); } break; =20 @@ -2485,19 +2485,19 @@ print_with_operands (const struct cris_opcode *opco= dep, =20 case 'P': { - const struct cris_spec_reg *sregp - =3D spec_reg_info ((insn >> 12) & 15, disdata->distype); + const struct cris_spec_reg *sregp + =3D spec_reg_info ((insn >> 12) & 15, disdata->distype); =20 - if (sregp =3D=3D NULL || sregp->name =3D=3D NULL) - /* Should have been caught as a non-match earlier. */ - *tp++ =3D '?'; - else - { - if (with_reg_prefix) - *tp++ =3D REGISTER_PREFIX_CHAR; - strcpy (tp, sregp->name); - tp +=3D strlen (tp); - } + if (sregp =3D=3D NULL || sregp->name =3D=3D NULL) + /* Should have been caught as a non-match earlier. */ + *tp++ =3D '?'; + else + { + if (with_reg_prefix) + *tp++ =3D REGISTER_PREFIX_CHAR; + strcpy (tp, sregp->name); + tp +=3D strlen (tp); + } } break; =20 @@ -2511,7 +2511,7 @@ print_with_operands (const struct cris_opcode *opcode= p, =20 if (prefix_opcodep) (*info->fprintf_func) (info->stream, " (OOPS unused prefix \"%s: %s\")= ", - prefix_opcodep->name, prefix_opcodep->args); + prefix_opcodep->name, prefix_opcodep->args); =20 (*info->fprintf_func) (info->stream, "%s", temp); =20 @@ -2521,23 +2521,23 @@ print_with_operands (const struct cris_opcode *opco= dep, if (TRACE_CASE && case_offset_counter =3D=3D 0) { if (CONST_STRNEQ (opcodep->name, "sub")) - case_offset =3D last_immediate; + case_offset =3D last_immediate; =20 /* It could also be an "add", if there are negative case-values. */ else if (CONST_STRNEQ (opcodep->name, "add")) - /* The first case is the negated operand to the add. */ - case_offset =3D -last_immediate; + /* The first case is the negated operand to the add. */ + case_offset =3D -last_immediate; =20 /* A bound insn will tell us the number of cases. */ else if (CONST_STRNEQ (opcodep->name, "bound")) - no_of_case_offsets =3D last_immediate + 1; + no_of_case_offsets =3D last_immediate + 1; =20 /* A jump or jsr or branch breaks the chain of insns for a - case-table, so assume default first-case again. */ + case-table, so assume default first-case again. */ else if (info->insn_type =3D=3D dis_jsr - || info->insn_type =3D=3D dis_branch - || info->insn_type =3D=3D dis_condbranch) - case_offset =3D 0; + || info->insn_type =3D=3D dis_branch + || info->insn_type =3D=3D dis_condbranch) + case_offset =3D 0; } } =20 @@ -2548,8 +2548,8 @@ print_with_operands (const struct cris_opcode *opcode= p, =20 static int print_insn_cris_generic (bfd_vma memaddr, - disassemble_info *info, - bfd_boolean with_reg_prefix) + disassemble_info *info, + bfd_boolean with_reg_prefix) { int nbytes; unsigned int insn; @@ -2575,7 +2575,7 @@ print_insn_cris_generic (bfd_vma memaddr, nbytes =3D info->buffer_length ? info->buffer_length : MAX_BYTES_PER_CRIS_INSN; nbytes =3D MIN(nbytes, MAX_BYTES_PER_CRIS_INSN); - status =3D (*info->read_memory_func) (memaddr, buffer, nbytes, info); =20 + status =3D (*info->read_memory_func) (memaddr, buffer, nbytes, info); =20 /* If we did not get all we asked for, then clear the rest. Hopefully this makes a reproducible result in case of errors. */ @@ -2603,101 +2603,101 @@ print_insn_cris_generic (bfd_vma memaddr, =20 /* If we're in a case-table, don't disassemble the offsets. */ if (TRACE_CASE && case_offset_counter !=3D 0) - { - info->insn_type =3D dis_noninsn; - advance +=3D 2; + { + info->insn_type =3D dis_noninsn; + advance +=3D 2; =20 - /* If to print data as offsets, then shortcut here. */ - (*info->fprintf_func) (info->stream, "case %ld%s: -> ", - case_offset + no_of_case_offsets - - case_offset_counter, - case_offset_counter =3D=3D 1 ? "/default" : - ""); + /* If to print data as offsets, then shortcut here. */ + (*info->fprintf_func) (info->stream, "case %ld%s: -> ", + case_offset + no_of_case_offsets + - case_offset_counter, + case_offset_counter =3D=3D 1 ? "/default"= : + ""); =20 - (*info->print_address_func) ((bfd_vma) - ((short) (insn) - + (long) (addr - - (no_of_case_offsets - - case_offset_counter) - * 2)), info); - case_offset_counter--; + (*info->print_address_func) ((bfd_vma) + ((short) (insn) + + (long) (addr + - (no_of_case_offsets + - case_offset_counter) + * 2)), info); + case_offset_counter--; =20 - /* The default case start (without a "sub" or "add") must be - zero. */ - if (case_offset_counter =3D=3D 0) - case_offset =3D 0; - } + /* The default case start (without a "sub" or "add") must be + zero. */ + if (case_offset_counter =3D=3D 0) + case_offset =3D 0; + } else if (insn =3D=3D 0) - { - /* We're often called to disassemble zeroes. While this is a - valid "bcc .+2" insn, it is also useless enough and enough - of a nuiscance that we will just output "bcc .+2" for it - and signal it as a noninsn. */ - (*info->fprintf_func) (info->stream, - disdata->distype =3D=3D cris_dis_v32 - ? "bcc ." : "bcc .+2"); - info->insn_type =3D dis_noninsn; - advance +=3D 2; - } + { + /* We're often called to disassemble zeroes. While this is a + valid "bcc .+2" insn, it is also useless enough and enough + of a nuiscance that we will just output "bcc .+2" for it + and signal it as a noninsn. */ + (*info->fprintf_func) (info->stream, + disdata->distype =3D=3D cris_dis_v32 + ? "bcc ." : "bcc .+2"); + info->insn_type =3D dis_noninsn; + advance +=3D 2; + } else - { - const struct cris_opcode *prefix_opcodep =3D NULL; - unsigned char *prefix_buffer =3D bufp; - unsigned int prefix_insn =3D insn; - int prefix_size =3D 0; + { + const struct cris_opcode *prefix_opcodep =3D NULL; + unsigned char *prefix_buffer =3D bufp; + unsigned int prefix_insn =3D insn; + int prefix_size =3D 0; =20 - matchedp =3D get_opcode_entry (insn, NO_CRIS_PREFIX, disdata); + matchedp =3D get_opcode_entry (insn, NO_CRIS_PREFIX, disdata); =20 - /* Check if we're supposed to write out prefixes as address - modes and if this was a prefix. */ - if (matchedp !=3D NULL && PARSE_PREFIX && matchedp->args[0] =3D=3D 'p') - { - /* If it's a prefix, put it into the prefix vars and get the - main insn. */ - prefix_size =3D bytes_to_skip (prefix_insn, matchedp, - disdata->distype, NULL); - prefix_opcodep =3D matchedp; + /* Check if we're supposed to write out prefixes as address + modes and if this was a prefix. */ + if (matchedp !=3D NULL && PARSE_PREFIX && matchedp->args[0] =3D= =3D 'p') + { + /* If it's a prefix, put it into the prefix vars and get the + main insn. */ + prefix_size =3D bytes_to_skip (prefix_insn, matchedp, + disdata->distype, NULL); + prefix_opcodep =3D matchedp; =20 - insn =3D bufp[prefix_size] + bufp[prefix_size + 1] * 256; - matchedp =3D get_opcode_entry (insn, prefix_insn, disdata); + insn =3D bufp[prefix_size] + bufp[prefix_size + 1] * 256; + matchedp =3D get_opcode_entry (insn, prefix_insn, disdata); =20 - if (matchedp !=3D NULL) - { - addr +=3D prefix_size; - bufp +=3D prefix_size; - advance +=3D prefix_size; - } - else - { - /* The "main" insn wasn't valid, at least not when - prefixed. Put back things enough to output the - prefix insn only, as a normal insn. */ - matchedp =3D prefix_opcodep; - insn =3D prefix_insn; - prefix_opcodep =3D NULL; - } - } + if (matchedp !=3D NULL) + { + addr +=3D prefix_size; + bufp +=3D prefix_size; + advance +=3D prefix_size; + } + else + { + /* The "main" insn wasn't valid, at least not when + prefixed. Put back things enough to output the + prefix insn only, as a normal insn. */ + matchedp =3D prefix_opcodep; + insn =3D prefix_insn; + prefix_opcodep =3D NULL; + } + } =20 - if (matchedp =3D=3D NULL) - { - (*info->fprintf_func) (info->stream, "??0x%x", insn); - advance +=3D 2; + if (matchedp =3D=3D NULL) + { + (*info->fprintf_func) (info->stream, "??0x%x", insn); + advance +=3D 2; =20 - info->insn_type =3D dis_noninsn; - } - else - { - advance - +=3D bytes_to_skip (insn, matchedp, disdata->distype, - prefix_opcodep); + info->insn_type =3D dis_noninsn; + } + else + { + advance + +=3D bytes_to_skip (insn, matchedp, disdata->distype, + prefix_opcodep); =20 - /* The info_type and assorted fields will be set according - to the operands. */ - print_with_operands (matchedp, insn, bufp, addr, info, - prefix_opcodep, prefix_insn, - prefix_buffer, with_reg_prefix); - } - } + /* The info_type and assorted fields will be set according + to the operands. */ + print_with_operands (matchedp, insn, bufp, addr, info, + prefix_opcodep, prefix_insn, + prefix_buffer, with_reg_prefix); + } + } } else info->insn_type =3D dis_noninsn; @@ -2733,24 +2733,24 @@ print_insn_cris_generic (bfd_vma memaddr, /* Disassemble, prefixing register names with `$'. CRIS v0..v10. */ static int print_insn_cris_with_register_prefix (bfd_vma vma, - disassemble_info *info) + disassemble_info *info) { struct cris_disasm_data disdata; info->private_data =3D &disdata; cris_parse_disassembler_options (&disdata, info->disassembler_options, - cris_dis_v0_v10); + cris_dis_v0_v10); return print_insn_cris_generic (vma, info, true); } /* Disassemble, prefixing register names with `$'. CRIS v32. */ =20 static int print_insn_crisv32_with_register_prefix (bfd_vma vma, - disassemble_info *info) + disassemble_info *info) { struct cris_disasm_data disdata; info->private_data =3D &disdata; cris_parse_disassembler_options (&disdata, info->disassembler_options, - cris_dis_v32); + cris_dis_v32); return print_insn_cris_generic (vma, info, true); } =20 @@ -2760,12 +2760,12 @@ print_insn_crisv32_with_register_prefix (bfd_vma vm= a, =20 static int print_insn_crisv10_v32_with_register_prefix (bfd_vma vma, - disassemble_info *info) + disassemble_info *info) { struct cris_disasm_data disdata; info->private_data =3D &disdata; cris_parse_disassembler_options (&disdata, info->disassembler_options, - cris_dis_common_v10_v32); + cris_dis_common_v10_v32); return print_insn_cris_generic (vma, info, true); } =20 @@ -2773,12 +2773,12 @@ print_insn_crisv10_v32_with_register_prefix (bfd_vm= a vma, =20 static int print_insn_cris_without_register_prefix (bfd_vma vma, - disassemble_info *info) + disassemble_info *info) { struct cris_disasm_data disdata; info->private_data =3D &disdata; cris_parse_disassembler_options (&disdata, info->disassembler_options, - cris_dis_v0_v10); + cris_dis_v0_v10); return print_insn_cris_generic (vma, info, false); } =20 @@ -2786,12 +2786,12 @@ print_insn_cris_without_register_prefix (bfd_vma vm= a, =20 static int print_insn_crisv32_without_register_prefix (bfd_vma vma, - disassemble_info *info) + disassemble_info *info) { struct cris_disasm_data disdata; info->private_data =3D &disdata; cris_parse_disassembler_options (&disdata, info->disassembler_options, - cris_dis_v32); + cris_dis_v32); return print_insn_cris_generic (vma, info, false); } =20 @@ -2800,26 +2800,26 @@ print_insn_crisv32_without_register_prefix (bfd_vma= vma, =20 static int print_insn_crisv10_v32_without_register_prefix (bfd_vma vma, - disassemble_info *info) + disassemble_info *info) { struct cris_disasm_data disdata; info->private_data =3D &disdata; cris_parse_disassembler_options (&disdata, info->disassembler_options, - cris_dis_common_v10_v32); + cris_dis_common_v10_v32); return print_insn_cris_generic (vma, info, false); } #endif =20 int print_insn_crisv10 (bfd_vma vma, - disassemble_info *info) + disassemble_info *info) { return print_insn_cris_with_register_prefix(vma, info); } =20 int print_insn_crisv32 (bfd_vma vma, - disassemble_info *info) + disassemble_info *info) { return print_insn_crisv32_with_register_prefix(vma, info); } @@ -2841,12 +2841,12 @@ cris_get_disassembler (bfd *abfd) if (bfd_get_symbol_leading_char (abfd) =3D=3D 0) { if (bfd_get_mach (abfd) =3D=3D bfd_mach_cris_v32) - return print_insn_crisv32_with_register_prefix; + return print_insn_crisv32_with_register_prefix; if (bfd_get_mach (abfd) =3D=3D bfd_mach_cris_v10_v32) - return print_insn_crisv10_v32_with_register_prefix; + return print_insn_crisv10_v32_with_register_prefix; =20 /* We default to v10. This may be specifically specified in the - bfd mach, but is also the default setting. */ + bfd mach, but is also the default setting. */ return print_insn_cris_with_register_prefix; } =20 --=20 2.34.1 From nobody Thu May 16 09:54:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1712985931; cv=none; d=zohomail.com; s=zohoarc; b=XO3dTQCA6UWIOZpa2LTExN5CrbHKuG0JZImblcXKUUuJSzgF3uRWVRb/7I+ChJTfK1fTfaZiv9sPazUiXN7C66IBs3b4IhDD+7LHISZNLI2ZIi5UKbWVxFYZY1fkKe7ifg91XrkI7Kf3HTvXBBYwTpQncIpMQj+RVjnFiVkHBm8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1712985931; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WeAW3psO2a4Q9h7sQeQJixxfk9X81dmTMFMwdx2gcGw=; b=AYCD9R+hsUPaOoiXqlyk0B3F5BEaj3/CHcExCVw9HDrN1IQlpe0yx7OmmS+skmtDMiF0XcUPYpEZxbCe3CGxNRvNxhB28DV47lElsWwt4N16uRYGHtJie35grZhh9y86F4/04t5FGAWuYmfRGqqhGt+AuUcqDDfexrLQxXbJ25w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1712985931125583.6412358932085; Fri, 12 Apr 2024 22:25:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rvVra-0001sd-Mq; Sat, 13 Apr 2024 01:23:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rvVrZ-0001sF-8p for qemu-devel@nongnu.org; Sat, 13 Apr 2024 01:23:41 -0400 Received: from mail-oo1-xc2f.google.com ([2607:f8b0:4864:20::c2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rvVrX-0001co-BB for qemu-devel@nongnu.org; Sat, 13 Apr 2024 01:23:40 -0400 Received: by mail-oo1-xc2f.google.com with SMTP id 006d021491bc7-5aa1bf6cb40so947148eaf.1 for ; Fri, 12 Apr 2024 22:23:38 -0700 (PDT) Received: from stoup.. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id v19-20020a17090abb9300b002a0544b81d6sm3564074pjr.35.2024.04.12.22.23.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Apr 2024 22:23:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712985818; x=1713590618; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WeAW3psO2a4Q9h7sQeQJixxfk9X81dmTMFMwdx2gcGw=; b=zfaZ/kBTLeex2K2c4ktcVBbA/r6HdFpyQrpOnxWtoUrH1pG/8RVZwmlmLwD6FyL+gz oYYgrAu+0/5/A5WBrMjukpZ9Wv/mK65pqEn1lTuULNFg+Wqyyhei8MtM8yYYWbyvkQzq hsgd4CQXYk8HvD2/muYgECEBtP7+O8TarK8pEPV6JmO0p37I8ZL0ukHenKoTrJAgpWAe gnGUV0ef/39aS9kiPjx7gdTA5TaBsHwEWdwGBhzLw1CQ/zqee5m4uKMYgGMJSw2mAe+L 2B46cWuz2KHYkxImLAkMAKpCKPWGtDs5JjXbEaBYx7K6KmfrDe50GwibIEAjJIdYxp8G a0Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712985818; x=1713590618; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WeAW3psO2a4Q9h7sQeQJixxfk9X81dmTMFMwdx2gcGw=; b=PV1dxWX99MIlS1BGO33UCDSgtjpDWxJLEz3BluSw8bMxR3J5TZPKCX9oyXiQRELEYg BqJJjPOruiiXfONq+mLQmvrZRM5xKzi1fISnFrc3WdgECkRkRv5XkfcLBLklp+uyOt3h GNWtbbbP+K61hnJBmwN/CHWMR4/R2vHh7/WFqgpu4dtwo1yjXouWKRMFZHOgDpxJFwgc SGQnXEL1emftS2OXndJnjeqOdRX6KsymjbdLDZyzyd5SJrT0ybHe0rEOD2wfdFRHAtc7 oQi5yWMhPDS6/KDKetyWbdHQzLpnW6Vw8fqxaQ1VZ563yPYfU7rTPueTveDVw0n/m09c me4A== X-Gm-Message-State: AOJu0Yw+t05E+QTAvUAOHFGJjuZHHjL70Mq5D62Wios5iw1cBKRxkggm ySxYKC/thQWvR/ToxiVTQxllTtdWXNiKEl5bY5d3cYfW4ThpHFCSZGvfApFxS+BmFNHJQqmFKNe Q X-Google-Smtp-Source: AGHT+IEODxDNWy0TZn5Nfs0denrfv4djfpsZ1L/BaRBURW2aRTHgYLudnrTtuh8XYFN1goGlFSC0sQ== X-Received: by 2002:a05:6359:4246:b0:183:ddb0:eb03 with SMTP id ko6-20020a056359424600b00183ddb0eb03mr6777500rwb.21.1712985818096; Fri, 12 Apr 2024 22:23:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, philmd@linaro.org Subject: [PATCH 2/6] disas/cris: Remove TRACE_CASE and related code Date: Fri, 12 Apr 2024 22:23:29 -0700 Message-Id: <20240413052333.688151-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240413052333.688151-1-richard.henderson@linaro.org> References: <20240413052333.688151-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1712985932400100015 Content-Type: text/plain; charset="utf-8" The disassembler_options variable is never set within QEMU, so this code is never enabled. Remove it all. Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias --- disas/cris.c | 114 ++------------------------------------------------- 1 file changed, 3 insertions(+), 111 deletions(-) diff --git a/disas/cris.c b/disas/cris.c index d62f9e3264..1cc8752104 100644 --- a/disas/cris.c +++ b/disas/cris.c @@ -1236,58 +1236,17 @@ cris_cc_strings[] =3D /* Sometimes we prefix all registers with this character. */ #define REGISTER_PREFIX_CHAR '$' =20 -/* Whether or not to trace the following sequence: - sub* X,r%d - bound* Y,r%d - adds.w [pc+r%d.w],pc - - This is the assembly form of a switch-statement in C. - The "sub is optional. If there is none, then X will be zero. - X is the value of the first case, - Y is the number of cases (including default). - - This results in case offsets printed on the form: - case N: -> case_address - where N is an estimation on the corresponding 'case' operand in C, - and case_address is where execution of that case continues after the - sequence presented above. - - The old style of output was to print the offsets as instructions, - which made it hard to follow "case"-constructs in the disassembly, - and caused a lot of annoying warnings about undefined instructions. - - FIXME: Make this optional later. */ -#ifndef TRACE_CASE -#define TRACE_CASE (disdata->trace_case) -#endif - enum cris_disass_family { cris_dis_v0_v10, cris_dis_common_v10_v32, cris_dis_v32 }; =20 /* Stored in the disasm_info->private_data member. */ struct cris_disasm_data { - /* Whether to print something less confusing if we find something - matching a switch-construct. */ - bfd_boolean trace_case; - /* Whether this code is flagged as crisv32. FIXME: Should be an enum that includes "compatible". */ enum cris_disass_family distype; }; =20 -/* Value of first element in switch. */ -static long case_offset =3D 0; - -/* How many more case-offsets to print. */ -static long case_offset_counter =3D 0; - -/* Number of case offsets. */ -static long no_of_case_offsets =3D 0; - -/* Candidate for next case_offset. */ -static long last_immediate =3D 0; - static int cris_constraint (const char *, unsigned, unsigned, struct cris_disasm_data *); =20 @@ -1299,11 +1258,6 @@ cris_parse_disassembler_options (struct cris_disasm_= data *disdata, char *disassembler_options, enum cris_disass_family distype) { - /* Default true. */ - disdata->trace_case - =3D (disassembler_options =3D=3D NULL - || (strcmp (disassembler_options, "nocase") !=3D 0)); - disdata->distype =3D distype; } =20 @@ -1711,18 +1665,13 @@ cris_constraint (const char *cs, =20 static char * format_hex (unsigned long number, - char *outbuffer, - struct cris_disasm_data *disdata) + char *outbuffer) { /* Truncate negative numbers on >32-bit hosts. */ number &=3D 0xffffffff; =20 sprintf (outbuffer, "0x%lx", number); =20 - /* Save this value for the "case" support. */ - if (TRACE_CASE) - last_immediate =3D number; - return outbuffer + strlen (outbuffer); } =20 @@ -1733,7 +1682,6 @@ format_hex (unsigned long number, static char * format_dec (long number, char *outbuffer, size_t outsize, int signedp) { - last_immediate =3D number; snprintf (outbuffer, outsize, signedp ? "%ld" : "%lu", number); =20 return outbuffer + strlen (outbuffer); @@ -2138,7 +2086,7 @@ print_with_operands (const struct cris_opcode *opcode= p, info->target =3D number; } else - tp =3D format_hex (number, tp, disdata); + tp =3D format_hex (number, tp); } } else @@ -2273,11 +2221,6 @@ print_with_operands (const struct cris_opcode *opcod= ep, ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4 : ((prefix_insn & 0x8000) ? CRIS_DIS_FLAG_MEM_TARGET2_MULT2 : 0))); - - /* Is it the casejump? It's a "adds.w [pc+r%d.w],pc".= */ - if (insn =3D=3D 0xf83f && (prefix_insn & ~0xf000) =3D= =3D 0x55f) - /* Then start interpreting data as offsets. */ - case_offset_counter =3D no_of_case_offsets; break; =20 case BDAP_INDIR_OPCODE: @@ -2514,31 +2457,6 @@ print_with_operands (const struct cris_opcode *opcod= ep, prefix_opcodep->name, prefix_opcodep->args); =20 (*info->fprintf_func) (info->stream, "%s", temp); - - /* Get info for matching case-tables, if we don't have any active. - We assume that the last constant seen is used; either in the insn - itself or in a "move.d const,rN, sub.d rN,rM"-like sequence. */ - if (TRACE_CASE && case_offset_counter =3D=3D 0) - { - if (CONST_STRNEQ (opcodep->name, "sub")) - case_offset =3D last_immediate; - - /* It could also be an "add", if there are negative case-values. */ - else if (CONST_STRNEQ (opcodep->name, "add")) - /* The first case is the negated operand to the add. */ - case_offset =3D -last_immediate; - - /* A bound insn will tell us the number of cases. */ - else if (CONST_STRNEQ (opcodep->name, "bound")) - no_of_case_offsets =3D last_immediate + 1; - - /* A jump or jsr or branch breaks the chain of insns for a - case-table, so assume default first-case again. */ - else if (info->insn_type =3D=3D dis_jsr - || info->insn_type =3D=3D dis_branch - || info->insn_type =3D=3D dis_condbranch) - case_offset =3D 0; - } } =20 =20 @@ -2601,33 +2519,7 @@ print_insn_cris_generic (bfd_vma memaddr, =20 insn =3D bufp[0] + bufp[1] * 256; =20 - /* If we're in a case-table, don't disassemble the offsets. */ - if (TRACE_CASE && case_offset_counter !=3D 0) - { - info->insn_type =3D dis_noninsn; - advance +=3D 2; - - /* If to print data as offsets, then shortcut here. */ - (*info->fprintf_func) (info->stream, "case %ld%s: -> ", - case_offset + no_of_case_offsets - - case_offset_counter, - case_offset_counter =3D=3D 1 ? "/default"= : - ""); - - (*info->print_address_func) ((bfd_vma) - ((short) (insn) - + (long) (addr - - (no_of_case_offsets - - case_offset_counter) - * 2)), info); - case_offset_counter--; - - /* The default case start (without a "sub" or "add") must be - zero. */ - if (case_offset_counter =3D=3D 0) - case_offset =3D 0; - } - else if (insn =3D=3D 0) + if (insn =3D=3D 0) { /* We're often called to disassemble zeroes. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id v19-20020a17090abb9300b002a0544b81d6sm3564074pjr.35.2024.04.12.22.23.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Apr 2024 22:23:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712985819; x=1713590619; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nGlcb0FOsVrtW/loWoknwOL1pthHdADUVw02ahp2qOs=; b=eTxDeJKHK5jWg78ggzI05M8cZUleNlmYKPZbnzABr/wg6DQnb+Vke7uz/QsN2kJ0TC iQy9MtDiDf418EcWnvYwvOrYzFqavT4xkFSngc4k+tQBm6k2h8KTVW/2yE4l9UB3P2L3 thgJiW2jjogV8i2kKwApWyiowcXaB9oGOuVlUfWsGkF4iqojcf/JMUxHC6I7zGCu3yRH iYtitqCS1gPKEzCatRFaoiaXNyrxwBJntgL+Xju+GdS9ph5kRYYc8HKQnGI37rYJXiqV gQROfFiohT8WheePZLRJvFt0VDeUuosha4V0UWX2g5Ig1eHAdyjtAFkHK6T+Nv//4JDy 3aHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712985819; x=1713590619; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nGlcb0FOsVrtW/loWoknwOL1pthHdADUVw02ahp2qOs=; b=rJniLkQTeeOGS/2gatNTWVRDr2BnffZyshHZJCA8VStNOfYuDGevGz5+bT6TWwQlJ/ ApIVuWHPN6x6eYSmX3f+LTQc2aM2UbAot6nwiQiA9jz2AvbO9k6ywzpaGWpfQXk0KxaO skMUNJLC/faaTVq5RxqZwCnu4U8HhsuidWDdkJ7K2bJihlH2Ouy8mzUUQjGKJYuf3R7X bGHxj2M1SYbe8xe8u+CJHKEhzqoPXa51JGeibZy+KTZUbYUCA7nWHQ6EBIraL7hBOpNv iC30HrlH6L0zx8jpzXpZJUi+ngHrpx01FdQZyPLcnav33WO4rfJL3K+t4FpCZd4e9CH9 06Qg== X-Gm-Message-State: AOJu0YwimAIk7gteuw37S51bvjsHj+U1mgbI3aCmHIrqfoy5hEPKrI/q /psna19wQJx5VVcSBlUoiIva+7reohj4GrYUTTx9cMiXzYwo9u9DqTen8uEHIqWi89S0izgOM7X X X-Google-Smtp-Source: AGHT+IGsDrY2kGlKQi/BstwiTxQ/4+GN6O/ac97MDFf62SHf2vzU6HzFsCB/2F/sfojegCIPWopl5Q== X-Received: by 2002:a05:6358:7c13:b0:181:6575:1b22 with SMTP id p19-20020a0563587c1300b0018165751b22mr4657754rwf.6.1712985819025; Fri, 12 Apr 2024 22:23:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, philmd@linaro.org Subject: [PATCH 3/6] disas/cris: Drop with_reg_prefix Date: Fri, 12 Apr 2024 22:23:30 -0700 Message-Id: <20240413052333.688151-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240413052333.688151-1-richard.henderson@linaro.org> References: <20240413052333.688151-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c32; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1712985932426100020 Content-Type: text/plain; charset="utf-8" The *_without_reg_prefix functions are all commented out. Remove them, remove all 'with_reg_prefix' parameters, and remove all of the conditions that test them. Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias --- disas/cris.c | 188 +++++++++------------------------------------------ 1 file changed, 32 insertions(+), 156 deletions(-) diff --git a/disas/cris.c b/disas/cris.c index 1cc8752104..27f71a8257 100644 --- a/disas/cris.c +++ b/disas/cris.c @@ -1692,13 +1692,11 @@ format_dec (long number, char *outbuffer, size_t ou= tsize, int signedp) static char * format_reg (struct cris_disasm_data *disdata, int regno, - char *outbuffer_start, - bfd_boolean with_reg_prefix) + char *outbuffer_start) { char *outbuffer =3D outbuffer_start; =20 - if (with_reg_prefix) - *outbuffer++ =3D REGISTER_PREFIX_CHAR; + *outbuffer++ =3D REGISTER_PREFIX_CHAR; =20 switch (regno) { @@ -1726,14 +1724,12 @@ format_reg (struct cris_disasm_data *disdata, =20 static char * format_sup_reg (unsigned int regno, - char *outbuffer_start, - bfd_boolean with_reg_prefix) + char *outbuffer_start) { char *outbuffer =3D outbuffer_start; int i; =20 - if (with_reg_prefix) - *outbuffer++ =3D REGISTER_PREFIX_CHAR; + *outbuffer++ =3D REGISTER_PREFIX_CHAR; =20 for (i =3D 0; cris_support_regs[i].name !=3D NULL; i++) if (cris_support_regs[i].number =3D=3D regno) @@ -1845,8 +1841,7 @@ print_with_operands (const struct cris_opcode *opcode= p, it. */ const struct cris_opcode *prefix_opcodep, unsigned int prefix_insn, - unsigned char *prefix_buffer, - bfd_boolean with_reg_prefix) + unsigned char *prefix_buffer) { /* Get a buffer of somewhat reasonable size where we store intermediate parts of the insn. */ @@ -1908,12 +1903,11 @@ print_with_operands (const struct cris_opcode *opco= dep, switch (*s) { case 'T': - tp =3D format_sup_reg ((insn >> 12) & 15, tp, with_reg_prefix); + tp =3D format_sup_reg ((insn >> 12) & 15, tp); break; =20 case 'A': - if (with_reg_prefix) - *tp++ =3D REGISTER_PREFIX_CHAR; + *tp++ =3D REGISTER_PREFIX_CHAR; *tp++ =3D 'a'; *tp++ =3D 'c'; *tp++ =3D 'r'; @@ -1945,11 +1939,11 @@ print_with_operands (const struct cris_opcode *opco= dep, =20 case 'D': case 'r': - tp =3D format_reg (disdata, insn & 15, tp, with_reg_prefix); + tp =3D format_reg (disdata, insn & 15, tp); break; =20 case 'R': - tp =3D format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix= ); + tp =3D format_reg (disdata, (insn >> 12) & 15, tp); break; =20 case 'n': @@ -2132,7 +2126,7 @@ print_with_operands (const struct cris_opcode *opcode= p, { if (insn & 0x400) { - tp =3D format_reg (disdata, insn & 15, tp, with_reg_pr= efix); + tp =3D format_reg (disdata, insn & 15, tp); *tp++ =3D '=3D'; } =20 @@ -2174,8 +2168,7 @@ print_with_operands (const struct cris_opcode *opcode= p, info->target2 =3D prefix_insn & 15; =20 *tp++ =3D '['; - tp =3D format_reg (disdata, prefix_insn & 15, tp, - with_reg_prefix); + tp =3D format_reg (disdata, prefix_insn & 15, tp); if (prefix_insn & 0x400) *tp++ =3D '+'; *tp++ =3D ']'; @@ -2191,8 +2184,7 @@ print_with_operands (const struct cris_opcode *opcode= p, number -=3D 256; =20 /* Output "reg+num" or, if num < 0, "reg-num". */ - tp =3D format_reg (disdata, (prefix_insn >> 12) & 15= , tp, - with_reg_prefix); + tp =3D format_reg (disdata, (prefix_insn >> 12) & 15= , tp); if (number >=3D 0) *tp++ =3D '+'; tp =3D FORMAT_DEC (number, tp, 1); @@ -2205,11 +2197,9 @@ print_with_operands (const struct cris_opcode *opcod= ep, =20 case BIAP_OPCODE: /* Output "r+R.m". */ - tp =3D format_reg (disdata, prefix_insn & 15, tp, - with_reg_prefix); + tp =3D format_reg (disdata, prefix_insn & 15, tp); *tp++ =3D '+'; - tp =3D format_reg (disdata, (prefix_insn >> 12) & 15, = tp, - with_reg_prefix); + tp =3D format_reg (disdata, (prefix_insn >> 12) & 15, = tp); *tp++ =3D '.'; *tp++ =3D mode_char[(prefix_insn >> 4) & 3]; =20 @@ -2226,8 +2216,7 @@ print_with_operands (const struct cris_opcode *opcode= p, case BDAP_INDIR_OPCODE: /* Output "r+s.m", or, if "s" is [pc+], "r+s" or "r-s". */ - tp =3D format_reg (disdata, (prefix_insn >> 12) & 15, = tp, - with_reg_prefix); + tp =3D format_reg (disdata, (prefix_insn >> 12) & 15, = tp); =20 if ((prefix_insn & 0x400) && (prefix_insn & 15) =3D=3D= 15) { @@ -2297,8 +2286,7 @@ print_with_operands (const struct cris_opcode *opcode= p, /* Output "r+[R].m" or "r+[R+].m". */ *tp++ =3D '+'; *tp++ =3D '['; - tp =3D format_reg (disdata, prefix_insn & 15, tp, - with_reg_prefix); + tp =3D format_reg (disdata, prefix_insn & 15, tp); if (prefix_insn & 0x400) *tp++ =3D '+'; *tp++ =3D ']'; @@ -2327,7 +2315,7 @@ print_with_operands (const struct cris_opcode *opcode= p, } else { - tp =3D format_reg (disdata, insn & 15, tp, with_reg_prefix= ); + tp =3D format_reg (disdata, insn & 15, tp); =20 info->flags |=3D CRIS_DIS_FLAG_MEM_TARGET_IS_REG; info->target =3D insn & 15; @@ -2340,7 +2328,7 @@ print_with_operands (const struct cris_opcode *opcode= p, break; =20 case 'x': - tp =3D format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix= ); + tp =3D format_reg (disdata, (insn >> 12) & 15, tp); *tp++ =3D '.'; *tp++ =3D mode_char[(insn >> 4) & 3]; break; @@ -2414,7 +2402,7 @@ print_with_operands (const struct cris_opcode *opcode= p, =20 tp =3D FORMAT_DEC (number, tp, 1); *tp++ =3D ','; - tp =3D format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix= ); + tp =3D format_reg (disdata, (insn >> 12) & 15, tp); } break; =20 @@ -2436,8 +2424,7 @@ print_with_operands (const struct cris_opcode *opcode= p, *tp++ =3D '?'; else { - if (with_reg_prefix) - *tp++ =3D REGISTER_PREFIX_CHAR; + *tp++ =3D REGISTER_PREFIX_CHAR; strcpy (tp, sregp->name); tp +=3D strlen (tp); } @@ -2466,8 +2453,7 @@ print_with_operands (const struct cris_opcode *opcode= p, =20 static int print_insn_cris_generic (bfd_vma memaddr, - disassemble_info *info, - bfd_boolean with_reg_prefix) + disassemble_info *info) { int nbytes; unsigned int insn; @@ -2587,7 +2573,7 @@ print_insn_cris_generic (bfd_vma memaddr, to the operands. */ print_with_operands (matchedp, insn, bufp, addr, info, prefix_opcodep, prefix_insn, - prefix_buffer, with_reg_prefix); + prefix_buffer); } } } @@ -2622,134 +2608,24 @@ print_insn_cris_generic (bfd_vma memaddr, return advance; } =20 -/* Disassemble, prefixing register names with `$'. CRIS v0..v10. */ -static int -print_insn_cris_with_register_prefix (bfd_vma vma, - disassemble_info *info) -{ - struct cris_disasm_data disdata; - info->private_data =3D &disdata; - cris_parse_disassembler_options (&disdata, info->disassembler_options, - cris_dis_v0_v10); - return print_insn_cris_generic (vma, info, true); -} -/* Disassemble, prefixing register names with `$'. CRIS v32. */ - -static int -print_insn_crisv32_with_register_prefix (bfd_vma vma, - disassemble_info *info) -{ - struct cris_disasm_data disdata; - info->private_data =3D &disdata; - cris_parse_disassembler_options (&disdata, info->disassembler_options, - cris_dis_v32); - return print_insn_cris_generic (vma, info, true); -} - -#if 0 -/* Disassemble, prefixing register names with `$'. - Common v10 and v32 subset. */ - -static int -print_insn_crisv10_v32_with_register_prefix (bfd_vma vma, - disassemble_info *info) -{ - struct cris_disasm_data disdata; - info->private_data =3D &disdata; - cris_parse_disassembler_options (&disdata, info->disassembler_options, - cris_dis_common_v10_v32); - return print_insn_cris_generic (vma, info, true); -} - -/* Disassemble, no prefixes on register names. CRIS v0..v10. */ - -static int -print_insn_cris_without_register_prefix (bfd_vma vma, - disassemble_info *info) -{ - struct cris_disasm_data disdata; - info->private_data =3D &disdata; - cris_parse_disassembler_options (&disdata, info->disassembler_options, - cris_dis_v0_v10); - return print_insn_cris_generic (vma, info, false); -} - -/* Disassemble, no prefixes on register names. CRIS v32. */ - -static int -print_insn_crisv32_without_register_prefix (bfd_vma vma, - disassemble_info *info) -{ - struct cris_disasm_data disdata; - info->private_data =3D &disdata; - cris_parse_disassembler_options (&disdata, info->disassembler_options, - cris_dis_v32); - return print_insn_cris_generic (vma, info, false); -} - -/* Disassemble, no prefixes on register names. - Common v10 and v32 subset. */ - -static int -print_insn_crisv10_v32_without_register_prefix (bfd_vma vma, - disassemble_info *info) -{ - struct cris_disasm_data disdata; - info->private_data =3D &disdata; - cris_parse_disassembler_options (&disdata, info->disassembler_options, - cris_dis_common_v10_v32); - return print_insn_cris_generic (vma, info, false); -} -#endif - int print_insn_crisv10 (bfd_vma vma, disassemble_info *info) { - return print_insn_cris_with_register_prefix(vma, info); + struct cris_disasm_data disdata; + info->private_data =3D &disdata; + cris_parse_disassembler_options (&disdata, info->disassembler_options, + cris_dis_v0_v10); + return print_insn_cris_generic (vma, info); } =20 int print_insn_crisv32 (bfd_vma vma, disassemble_info *info) { - return print_insn_crisv32_with_register_prefix(vma, info); + struct cris_disasm_data disdata; + info->private_data =3D &disdata; + cris_parse_disassembler_options (&disdata, info->disassembler_options, + cris_dis_v32); + return print_insn_cris_generic (vma, info); } - -/* Return a disassembler-function that prints registers with a `$' prefix, - or one that prints registers without a prefix. - FIXME: We should improve the solution to avoid the multitude of - functions seen above. */ -#if 0 -disassembler_ftype -cris_get_disassembler (bfd *abfd) -{ - /* If there's no bfd in sight, we return what is valid as input in all - contexts if fed back to the assembler: disassembly *with* register - prefix. Unfortunately this will be totally wrong for v32. */ - if (abfd =3D=3D NULL) - return print_insn_cris_with_register_prefix; - - if (bfd_get_symbol_leading_char (abfd) =3D=3D 0) - { - if (bfd_get_mach (abfd) =3D=3D bfd_mach_cris_v32) - return print_insn_crisv32_with_register_prefix; - if (bfd_get_mach (abfd) =3D=3D bfd_mach_cris_v10_v32) - return print_insn_crisv10_v32_with_register_prefix; - - /* We default to v10. This may be specifically specified in the - bfd mach, but is also the default setting. */ - return print_insn_cris_with_register_prefix; - } - - if (bfd_get_mach (abfd) =3D=3D bfd_mach_cris_v32) - return print_insn_crisv32_without_register_prefix; - if (bfd_get_mach (abfd) =3D=3D bfd_mach_cris_v10_v32) - return print_insn_crisv10_v32_without_register_prefix; - return print_insn_cris_without_register_prefix; -} -#endif -/* Local variables: - eval: (c-set-style "gnu") - indent-tabs-mode: t - End: */ --=20 2.34.1 From nobody Thu May 16 09:54:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1712985931; cv=none; d=zohomail.com; s=zohoarc; b=jte6R/L7FRMOfwmi3hYMfeeKMl8KZqf193wFKrqpuxbUrwMnjdSJCF/hImLGDkrCD0YoBmS7zqiuuS85a2KARVdNkOHcJsWbORngSATZByxgMB4XpJywhV3YEbLlNI5SdtjJMX8DC1i3/WbScs0vBNIU0f81qg8zfbcRyNoIWYI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1712985931; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xHXdGb2Ykd1dojWJmRnTDjJcr6qyUR/mTTLDcFT9woA=; b=SMLy6GvOLX4PLKLDxOiMrbxPovIPAUM7h0QlAK4G9bFC5rcqqJH1W13u4Ge7n6GnanMw0CRATqlxFcklRjlzsJjYOCDAyFJzaHsDDnWuZDty3Ul/aJYjjD2IIpnV+j8Ll4sEtq9t+HW8rsM43VJi4zTEPM345gZ0L9pIZw7C0qc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1712985931160459.30117407601745; Fri, 12 Apr 2024 22:25:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rvVre-0001u0-Ti; Sat, 13 Apr 2024 01:23:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rvVrc-0001tF-O0 for qemu-devel@nongnu.org; Sat, 13 Apr 2024 01:23:44 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rvVrZ-0001dJ-Oy for qemu-devel@nongnu.org; Sat, 13 Apr 2024 01:23:44 -0400 Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-29e0229d6b5so1221372a91.3 for ; Fri, 12 Apr 2024 22:23:41 -0700 (PDT) Received: from stoup.. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id v19-20020a17090abb9300b002a0544b81d6sm3564074pjr.35.2024.04.12.22.23.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Apr 2024 22:23:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712985820; x=1713590620; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xHXdGb2Ykd1dojWJmRnTDjJcr6qyUR/mTTLDcFT9woA=; b=PxT3eqVVdogAFSg8rpgi3tzyDcTomyOOSk5h/GiehWNZaD0JpAHI9VJVEhS58c8xb9 oEFAEL/aBCalkJVazdUdNpH/XPtxpzuVccp/aT7BfnTpVxH9lxaQ+qNcwZFo8LQIXI2e xGICXDLvDvWQYv/VFSabKRkxOCAKP1gdVf3RA+S4WAFoIfN0z9U+qvg/H3z76cvWt5to mLcfP9RoNlpfD/ku7fJssQ8qNfAeIbpxRcetIHq2MXKhQCDWd790zSPyZVn2x2nh19xB jvPXmZK4rjzsTEcWRX8n7Is9XzEwYJTeswGUImc4JOSP4bWV+9PQUyv474caqDyOmMs6 TJhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712985820; x=1713590620; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xHXdGb2Ykd1dojWJmRnTDjJcr6qyUR/mTTLDcFT9woA=; b=JefcyCtcc/yjI8vCDorji4bTJe0mdcywu3Iza2fk6D2j/d3GaejrlI5sIl1gSqy/LL TeD+6Lq+ecA3ltQL4oQM4doeFwypbz6BjagqocULgDtgq+vwUntfqoxj9KabfH9cLEuN wVFMjrP3mkuVeLaxCyN7BJxqasjzG1/my1+R1MyWe8J481aF/ldBHzWTYGOpfDpaKOBf z5dBjwHnUwy2aRQdEayUCRUNan1/qnYMP57XDf2eBH5ZYaqv2fLInq8jldIkEQZdV9o7 QzxqitmdSM1KN1DJKJohGuts80e7Kj+RRDLMvj0j96nFLk07wD0UlD+gTNEhWuoFf6Mk ZzKQ== X-Gm-Message-State: AOJu0Yxd2w7ZVrFUrQO7kklJrWoYIYpiR1evKVK8lpsCEEWRs+67i4HF dOJqXxqPeyjfJu2uuATqVb9/W6HgVbD7oTFdn4sCmGEGxOjscFOTNcW9zn1xf7607YjEjymAJoJ n X-Google-Smtp-Source: AGHT+IEdBAA66AmgZVcjoP+lHDG4J9y+OxJcae/3VsemMM+MXTEmTNiIQ9cClVWNhlDqniVCjdMlZw== X-Received: by 2002:a17:90a:db0a:b0:29b:c9ac:c563 with SMTP id g10-20020a17090adb0a00b0029bc9acc563mr3911941pjv.19.1712985819985; Fri, 12 Apr 2024 22:23:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, philmd@linaro.org Subject: [PATCH 4/6] disas/cris: Use GString in print_with_operands and subroutines Date: Fri, 12 Apr 2024 22:23:31 -0700 Message-Id: <20240413052333.688151-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240413052333.688151-1-richard.henderson@linaro.org> References: <20240413052333.688151-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1712985932425100019 Content-Type: text/plain; charset="utf-8" sprintf() is deprecated on Darwin since macOS 13.0 / XCode 14.1. Use GString in the core of the disassembler instead of buffering the string locally. Instead of info->print_address_func, use format_hex for addresses. Printing a hex number is what print_address_func does, and using format_hex properly truncates the 32-bit bit address. E.g. -0x00080988: move.d 0xfffffffffeda49ff,$r4 +0x00080988: move.d 0xfeda49ff,$r4 Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias --- disas/cris.c | 288 +++++++++++++++++---------------------------------- 1 file changed, 96 insertions(+), 192 deletions(-) diff --git a/disas/cris.c b/disas/cris.c index 27f71a8257..692cd4d163 100644 --- a/disas/cris.c +++ b/disas/cris.c @@ -1663,85 +1663,74 @@ cris_constraint (const char *cs, =20 /* Format number as hex with a leading "0x" into outbuffer. */ =20 -static char * -format_hex (unsigned long number, - char *outbuffer) +static void +format_hex(unsigned long number, GString *str) { /* Truncate negative numbers on >32-bit hosts. */ number &=3D 0xffffffff; =20 - sprintf (outbuffer, "0x%lx", number); - - return outbuffer + strlen (outbuffer); + g_string_append_printf(str, "0x%lx", number); } =20 /* Format number as decimal into outbuffer. Parameter signedp says whether the number should be formatted as signed (!=3D 0) or unsigned (=3D=3D 0). */ =20 -static char * -format_dec (long number, char *outbuffer, size_t outsize, int signedp) +static void +format_dec(long number, GString *str, int signedp) { - snprintf (outbuffer, outsize, signedp ? "%ld" : "%lu", number); - - return outbuffer + strlen (outbuffer); + if (signedp) + g_string_append_printf(str, "%ld", number); + else + g_string_append_printf(str, "%lu", number); } =20 /* Format the name of the general register regno into outbuffer. */ =20 -static char * -format_reg (struct cris_disasm_data *disdata, - int regno, - char *outbuffer_start) +static void +format_reg(struct cris_disasm_data *disdata, int regno, GString *str) { - char *outbuffer =3D outbuffer_start; - - *outbuffer++ =3D REGISTER_PREFIX_CHAR; + g_string_append_c(str, REGISTER_PREFIX_CHAR); =20 switch (regno) { case 15: /* For v32, there is no context in which we output PC. */ if (disdata->distype =3D=3D cris_dis_v32) - strcpy (outbuffer, "acr"); + g_string_append(str, "acr"); else - strcpy (outbuffer, "pc"); + g_string_append(str, "pc"); break; =20 case 14: - strcpy (outbuffer, "sp"); + g_string_append(str, "sp"); break; =20 default: - sprintf (outbuffer, "r%d", regno); + g_string_append_printf(str, "r%d", regno); break; } - - return outbuffer_start + strlen (outbuffer_start); } =20 /* Format the name of a support register into outbuffer. */ =20 -static char * -format_sup_reg (unsigned int regno, - char *outbuffer_start) +static void +format_sup_reg(unsigned int regno, GString *str) { - char *outbuffer =3D outbuffer_start; int i; =20 - *outbuffer++ =3D REGISTER_PREFIX_CHAR; + g_string_append_c(str, REGISTER_PREFIX_CHAR); =20 for (i =3D 0; cris_support_regs[i].name !=3D NULL; i++) if (cris_support_regs[i].number =3D=3D regno) { - sprintf (outbuffer, "%s", cris_support_regs[i].name); - return outbuffer_start + strlen (outbuffer_start); + g_string_append(str, cris_support_regs[i].name); + return; } =20 /* There's supposed to be register names covering all numbers, though some may be generic names. */ - sprintf (outbuffer, "format_sup_reg-BUG"); - return outbuffer_start + strlen (outbuffer_start); + g_string_append(str, "format_sup_reg-BUG"); } =20 /* Return the length of an instruction. */ @@ -1797,8 +1786,8 @@ bytes_to_skip (unsigned int insn, =20 /* Print condition code flags. */ =20 -static char * -print_flags (struct cris_disasm_data *disdata, unsigned int insn, char *cp) +static void +print_flags(struct cris_disasm_data *disdata, unsigned int insn, GString *= str) { /* Use the v8 (Etrax 100) flag definitions for disassembly. The differences with v0 (Etrax 1..4) vs. Svinto are: @@ -1815,17 +1804,9 @@ print_flags (struct cris_disasm_data *disdata, unsig= ned int insn, char *cp) =20 for (i =3D 0; i < 8; i++) if (flagbits & (1 << i)) - *cp++ =3D fnames[i]; - - return cp; + g_string_append_c(str, fnames[i]); } =20 -#define FORMAT_DEC(number, tp, signedp) \ - format_dec (number, tp, ({ \ - assert(tp >=3D temp && tp <=3D temp + sizeof(temp)); \ - temp + sizeof(temp) - tp; \ - }), signedp) - /* Print out an insn with its operands, and update the info->insn_type fields. The prefix_opcodep and the rest hold a prefix insn that is supposed to be output as an address mode. */ @@ -1843,19 +1824,13 @@ print_with_operands (const struct cris_opcode *opco= dep, unsigned int prefix_insn, unsigned char *prefix_buffer) { - /* Get a buffer of somewhat reasonable size where we store - intermediate parts of the insn. */ - char temp[sizeof (".d [$r13=3D$r12-2147483648],$r10") * 2]; - char *tp =3D temp; + g_autoptr(GString) str =3D g_string_new(opcodep->name); static const char mode_char[] =3D "bwd?"; const char *s; const char *cs; struct cris_disasm_data *disdata =3D (struct cris_disasm_data *) info->private_data; =20 - /* Print out the name first thing we do. */ - (*info->fprintf_func) (info->stream, "%s", opcodep->name); - cs =3D opcodep->args; s =3D cs; =20 @@ -1865,13 +1840,13 @@ print_with_operands (const struct cris_opcode *opco= dep, =20 if (*s =3D=3D 'm' || *s =3D=3D 'M' || *s =3D=3D 'z') { - *tp++ =3D '.'; + g_string_append_c(str, '.'); =20 /* Get the size-letter. */ - *tp++ =3D *s =3D=3D 'M' - ? (insn & 0x8000 ? 'd' - : insn & 0x4000 ? 'w' : 'b') - : mode_char[(insn >> 4) & (*s =3D=3D 'z' ? 1 : 3)]; + if (*s =3D=3D 'M') + g_string_append_c(str, insn & 0x8000 ? 'd' : insn & 0x4000 ? 'w' := 'b'); + else + g_string_append_c(str, mode_char[(insn >> 4) & (*s =3D=3D 'z' ? 1 = : 3)]); =20 /* Ignore the size and the space character that follows. */ s +=3D 2; @@ -1880,7 +1855,7 @@ print_with_operands (const struct cris_opcode *opcode= p, /* Add a space if this isn't a long-branch, because for those will add the condition part of the name later. */ if (opcodep->match !=3D (BRANCH_PC_LOW + BRANCH_INCR_HIGH * 256)) - *tp++ =3D ' '; + g_string_append_c(str, ' '); =20 /* Fill in the insn-type if deducible from the name (and there's no better way). */ @@ -1903,20 +1878,18 @@ print_with_operands (const struct cris_opcode *opco= dep, switch (*s) { case 'T': - tp =3D format_sup_reg ((insn >> 12) & 15, tp); + format_sup_reg((insn >> 12) & 15, str); break; =20 case 'A': - *tp++ =3D REGISTER_PREFIX_CHAR; - *tp++ =3D 'a'; - *tp++ =3D 'c'; - *tp++ =3D 'r'; + g_string_append_c(str, REGISTER_PREFIX_CHAR); + g_string_append(str, "acr"); break; =20 case '[': case ']': case ',': - *tp++ =3D *s; + g_string_append_c(str, *s); break; =20 case '!': @@ -1939,11 +1912,11 @@ print_with_operands (const struct cris_opcode *opco= dep, =20 case 'D': case 'r': - tp =3D format_reg (disdata, insn & 15, tp); + format_reg(disdata, insn & 15, str); break; =20 case 'R': - tp =3D format_reg (disdata, (insn >> 12) & 15, tp); + format_reg(disdata, (insn >> 12) & 15, str); break; =20 case 'n': @@ -1953,13 +1926,7 @@ print_with_operands (const struct cris_opcode *opcod= ep, =3D (buffer[2] + buffer[3] * 256 + buffer[4] * 65536 + buffer[5] * 0x1000000 + addr); =20 - /* Finish off and output previous formatted bytes. */ - *tp =3D 0; - if (temp[0]) - (*info->fprintf_func) (info->stream, "%s", temp); - tp =3D temp; - - (*info->print_address_func) ((bfd_vma) number, info); + format_hex(number, str); } break; =20 @@ -1968,13 +1935,7 @@ print_with_operands (const struct cris_opcode *opcod= ep, /* Like n but the offset is bits <3:0> in the instruction. */ unsigned long number =3D (buffer[0] & 0xf) * 2 + addr; =20 - /* Finish off and output previous formatted bytes. */ - *tp =3D 0; - if (temp[0]) - (*info->fprintf_func) (info->stream, "%s", temp); - tp =3D temp; - - (*info->print_address_func) ((bfd_vma) number, info); + format_hex(number, str); } break; =20 @@ -2045,43 +2006,16 @@ print_with_operands (const struct cris_opcode *opco= dep, break; =20 default: - strcpy (tp, "bug"); - tp +=3D 3; + g_string_append(str, "bug"); number =3D 42; } =20 if ((*cs =3D=3D 'z' && (insn & 0x20)) || (opcodep->match =3D=3D BDAP_QUICK_OPCODE && (nbytes <=3D 2 || buffer[1 + nbytes] =3D=3D 0))) - tp =3D FORMAT_DEC (number, tp, signedp); + format_dec(number, str, signedp); else - { - unsigned int highbyte =3D (number >> 24) & 0xff; - - /* Either output this as an address or as a number. If it= 's - a dword with the same high-byte as the address of the - insn, assume it's an address, and also if it's a non-ze= ro - non-0xff high-byte. If this is a jsr or a jump, then - it's definitely an address. */ - if (nbytes =3D=3D 4 - && (highbyte =3D=3D ((addr >> 24) & 0xff) - || (highbyte !=3D 0 && highbyte !=3D 0xff) - || info->insn_type =3D=3D dis_branch - || info->insn_type =3D=3D dis_jsr)) - { - /* Finish off and output previous formatted bytes. */ - *tp =3D 0; - tp =3D temp; - if (temp[0]) - (*info->fprintf_func) (info->stream, "%s", temp); - - (*info->print_address_func) ((bfd_vma) number, info); - - info->target =3D number; - } - else - tp =3D format_hex (number, tp); - } + format_hex(number, str); } else { @@ -2116,7 +2050,7 @@ print_with_operands (const struct cris_opcode *opcode= p, info->data_size =3D size; } =20 - *tp++ =3D '['; + g_string_append_c(str, '['); =20 if (prefix_opcodep /* We don't match dip with a postincremented field @@ -2126,8 +2060,8 @@ print_with_operands (const struct cris_opcode *opcode= p, { if (insn & 0x400) { - tp =3D format_reg (disdata, insn & 15, tp); - *tp++ =3D '=3D'; + format_reg(disdata, insn & 15, str); + g_string_append_c(str, '=3D'); } =20 =20 @@ -2146,16 +2080,7 @@ print_with_operands (const struct cris_opcode *opcod= ep, + prefix_buffer[4] * 65536 + prefix_buffer[5] * 0x1000000; =20 - info->target =3D (bfd_vma) number; - - /* Finish off and output previous formatted - data. */ - *tp =3D 0; - tp =3D temp; - if (temp[0]) - (*info->fprintf_func) (info->stream, "%s", temp); - - (*info->print_address_func) ((bfd_vma) number, inf= o); + format_hex(number, str); } else { @@ -2167,11 +2092,11 @@ print_with_operands (const struct cris_opcode *opco= dep, =20 info->target2 =3D prefix_insn & 15; =20 - *tp++ =3D '['; - tp =3D format_reg (disdata, prefix_insn & 15, tp); + g_string_append_c(str, '['); + format_reg(disdata, prefix_insn & 15, str); if (prefix_insn & 0x400) - *tp++ =3D '+'; - *tp++ =3D ']'; + g_string_append_c(str, '+'); + g_string_append_c(str, ']'); } break; =20 @@ -2184,10 +2109,10 @@ print_with_operands (const struct cris_opcode *opco= dep, number -=3D 256; =20 /* Output "reg+num" or, if num < 0, "reg-num". */ - tp =3D format_reg (disdata, (prefix_insn >> 12) & 15= , tp); + format_reg(disdata, (prefix_insn >> 12) & 15, str); if (number >=3D 0) - *tp++ =3D '+'; - tp =3D FORMAT_DEC (number, tp, 1); + g_string_append_c(str, '+'); + format_dec(number, str, 1); =20 info->flags |=3D CRIS_DIS_FLAG_MEM_TARGET_IS_REG; info->target =3D (prefix_insn >> 12) & 15; @@ -2197,16 +2122,15 @@ print_with_operands (const struct cris_opcode *opco= dep, =20 case BIAP_OPCODE: /* Output "r+R.m". */ - tp =3D format_reg (disdata, prefix_insn & 15, tp); - *tp++ =3D '+'; - tp =3D format_reg (disdata, (prefix_insn >> 12) & 15, = tp); - *tp++ =3D '.'; - *tp++ =3D mode_char[(prefix_insn >> 4) & 3]; + format_reg(disdata, prefix_insn & 15, str); + g_string_append_c(str, '+'); + format_reg(disdata, (prefix_insn >> 12) & 15, str); + g_string_append_c(str, '.'); + g_string_append_c(str, mode_char[(prefix_insn >> 4) & = 3]); =20 info->flags |=3D (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG | CRIS_DIS_FLAG_MEM_TARGET_IS_REG - | ((prefix_insn & 0x8000) ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4 : ((prefix_insn & 0x8000) @@ -2214,9 +2138,8 @@ print_with_operands (const struct cris_opcode *opcode= p, break; =20 case BDAP_INDIR_OPCODE: - /* Output "r+s.m", or, if "s" is [pc+], "r+s" or - "r-s". */ - tp =3D format_reg (disdata, (prefix_insn >> 12) & 15, = tp); + /* Output "r+s.m", or, if "s" is [pc+], "r+s" or "r-s"= . */ + format_reg(disdata, (prefix_insn >> 12) & 15, str); =20 if ((prefix_insn & 0x400) && (prefix_insn & 15) =3D=3D= 15) { @@ -2253,8 +2176,7 @@ print_with_operands (const struct cris_opcode *opcode= p, break; =20 default: - strcpy (tp, "bug"); - tp +=3D 3; + g_string_append(str, "bug"); number =3D 42; } =20 @@ -2265,39 +2187,32 @@ print_with_operands (const struct cris_opcode *opco= dep, address. */ if (nbytes =3D=3D 4) { - /* Finish off and output previous formatted - bytes. */ - *tp++ =3D '+'; - *tp =3D 0; - tp =3D temp; - (*info->fprintf_func) (info->stream, "%s", tem= p); - - (*info->print_address_func) ((bfd_vma) number,= info); + g_string_append_c(str, '+'); + format_hex(number, str); } else { if (number >=3D 0) - *tp++ =3D '+'; - tp =3D FORMAT_DEC (number, tp, 1); + g_string_append_c(str, '+'); + format_dec(number, str, 1); } } else { /* Output "r+[R].m" or "r+[R+].m". */ - *tp++ =3D '+'; - *tp++ =3D '['; - tp =3D format_reg (disdata, prefix_insn & 15, tp); + g_string_append_c(str, '+'); + g_string_append_c(str, '['); + format_reg(disdata, prefix_insn & 15, str); if (prefix_insn & 0x400) - *tp++ =3D '+'; - *tp++ =3D ']'; - *tp++ =3D '.'; - *tp++ =3D mode_char[(prefix_insn >> 4) & 3]; + g_string_append_c(str, '+'); + g_string_append_c(str, ']'); + g_string_append_c(str, '.'); + g_string_append_c(str, mode_char[(prefix_insn >> 4= ) & 3]); =20 info->flags |=3D (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG | CRIS_DIS_FLAG_MEM_TARGET2_MEM | CRIS_DIS_FLAG_MEM_TARGET_IS_REG - | (((prefix_insn >> 4) =3D=3D 2) ? 0 : (((prefix_insn >> 4) & 3) =3D=3D 1 @@ -2315,26 +2230,26 @@ print_with_operands (const struct cris_opcode *opco= dep, } else { - tp =3D format_reg (disdata, insn & 15, tp); + format_reg(disdata, insn & 15, str); =20 info->flags |=3D CRIS_DIS_FLAG_MEM_TARGET_IS_REG; info->target =3D insn & 15; =20 if (insn & 0x400) - *tp++ =3D '+'; + g_string_append_c(str, '+'); } - *tp++ =3D ']'; + g_string_append_c(str, ']'); } break; =20 case 'x': - tp =3D format_reg (disdata, (insn >> 12) & 15, tp); - *tp++ =3D '.'; - *tp++ =3D mode_char[(insn >> 4) & 3]; + format_reg(disdata, (insn >> 12) & 15, str); + g_string_append_c(str, '.'); + g_string_append_c(str, mode_char[(insn >> 4) & 3]); break; =20 case 'I': - tp =3D FORMAT_DEC (insn & 63, tp, 0); + format_dec(insn & 63, str, 0); break; =20 case 'b': @@ -2353,21 +2268,17 @@ print_with_operands (const struct cris_opcode *opco= dep, =20 info->target =3D (bfd_vma) where; =20 - *tp =3D 0; - tp =3D temp; - (*info->fprintf_func) (info->stream, "%s%s ", - temp, cris_cc_strings[insn >> 12]); - - (*info->print_address_func) ((bfd_vma) where, info); + g_string_append(str, cris_cc_strings[insn >> 12]); + format_hex(where, str); } break; =20 case 'c': - tp =3D FORMAT_DEC (insn & 31, tp, 0); + format_dec(insn & 31, str, 0); break; =20 case 'C': - tp =3D FORMAT_DEC (insn & 15, tp, 0); + format_dec(insn & 15, str, 0); break; =20 case 'o': @@ -2385,10 +2296,7 @@ print_with_operands (const struct cris_opcode *opcod= ep, =20 target =3D addr + ((disdata->distype =3D=3D cris_dis_v32) ? 0 : 2)= + offset; info->target =3D target; - *tp =3D 0; - tp =3D temp; - (*info->fprintf_func) (info->stream, "%s", temp); - (*info->print_address_func) (target, info); + format_hex(target, str); } break; =20 @@ -2400,18 +2308,18 @@ print_with_operands (const struct cris_opcode *opco= dep, if (number > 127) number =3D number - 256; =20 - tp =3D FORMAT_DEC (number, tp, 1); - *tp++ =3D ','; - tp =3D format_reg (disdata, (insn >> 12) & 15, tp); + format_dec(number, str, 1); + g_string_append_c(str, ','); + format_reg(disdata, (insn >> 12) & 15, str); } break; =20 case 'f': - tp =3D print_flags (disdata, insn, tp); + print_flags(disdata, insn, str); break; =20 case 'i': - tp =3D FORMAT_DEC ((insn & 32) ? (insn & 31) | ~31L : insn & 31, tp,= 1); + format_dec((insn & 32) ? (insn & 31) | ~31L : insn & 31, str, 1); break; =20 case 'P': @@ -2421,29 +2329,25 @@ print_with_operands (const struct cris_opcode *opco= dep, =20 if (sregp =3D=3D NULL || sregp->name =3D=3D NULL) /* Should have been caught as a non-match earlier. */ - *tp++ =3D '?'; + g_string_append_c(str, '?'); else { - *tp++ =3D REGISTER_PREFIX_CHAR; - strcpy (tp, sregp->name); - tp +=3D strlen (tp); + g_string_append_c(str, REGISTER_PREFIX_CHAR); + g_string_append(str, sregp->name); } } break; =20 default: - strcpy (tp, "???"); - tp +=3D 3; + g_string_append(str, "???"); } } =20 - *tp =3D 0; - if (prefix_opcodep) - (*info->fprintf_func) (info->stream, " (OOPS unused prefix \"%s: %s\")= ", + (*info->fprintf_func) (info->stream, "(OOPS unused prefix \"%s: %s\") = ", prefix_opcodep->name, prefix_opcodep->args); =20 - (*info->fprintf_func) (info->stream, "%s", temp); + (*info->fprintf_func) (info->stream, "%s", str->str); } =20 =20 --=20 2.34.1 From nobody Thu May 16 09:54:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1712985931; cv=none; d=zohomail.com; s=zohoarc; b=CU9ZfOqlqqHLxQsIko4JSMDWvwOTZYt9fH+NzukBbCMY79Gj+QXyPj9SGubdQzL5iH1BuXS52irrSgttmpXowVDzbMxJFTZlhKZYaedCXggLevl1wDfLFRmawbm3HKCq4xtxOWQcMoFtGGC91Is5n2Nd5taECZaeHSSCjdgMmZk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1712985931; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=pF9Q6sT8QWcjaBZdy/z96I4yqBVj9yrUa4QsuaKPwaQ=; b=RPxX2hkbCfedX7ZJKtQRhMnBUuT24poeDIgZ0C5LkVag+yTXEmMkapCuwj/qxlcyeufQHQEXkLZKckPig/x9ays52lXsS706WrntFgytas8sXQIpxKzsSpaRPc55Fn+zBfUVm76EbTWysoxG4Bgmn0PDkFQH36wmi8ox0TUlFaY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1712985931356386.2650290884998; Fri, 12 Apr 2024 22:25:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rvVre-0001tz-Rk; Sat, 13 Apr 2024 01:23:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rvVrd-0001tb-As for qemu-devel@nongnu.org; Sat, 13 Apr 2024 01:23:45 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rvVra-0001dT-DB for qemu-devel@nongnu.org; Sat, 13 Apr 2024 01:23:45 -0400 Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-2a526803fccso904135a91.1 for ; Fri, 12 Apr 2024 22:23:42 -0700 (PDT) Received: from stoup.. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id v19-20020a17090abb9300b002a0544b81d6sm3564074pjr.35.2024.04.12.22.23.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Apr 2024 22:23:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712985821; x=1713590621; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pF9Q6sT8QWcjaBZdy/z96I4yqBVj9yrUa4QsuaKPwaQ=; b=QPo3Khdj1My1L00CDFnB45MqqE0xgVk3NvX09InE+z9LkqmTsv6HvoEbVrQOPB4KHO SFvNU5TAB7RcE9/1WSsroyqfqxOsAuSEy6mTOrxzUIBpFmON18tL+ni5XdLXldIID5bA WgEvTlzZRVKfouKw+aicU30MgMOtbLFgwBuo69fGKyqRCL3N9CGRUPRs90W6WyrimtYI 8xtj4YfCJ0Pd0v8mihQ4Qzf8ZzEYYWk1spm3bbd0K0od85gp/9NZSLyOFHOe/bMK1e+Z 2I+ftX1fzJC9g6+8Z54s1doflodMgjgug5f5f0c5TgqdfsoDojDg/apCVsYCAb6fOy96 YrEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712985821; x=1713590621; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pF9Q6sT8QWcjaBZdy/z96I4yqBVj9yrUa4QsuaKPwaQ=; b=RL76l4QpFM9OXCeht7oYlAoqiZZJ2LOQoXXpHHg7AscZ6qHeJqnvsP1PK8hROdjbj7 a7ldGbKploYjm3Vj2PnHeY2XRI9JYw0PENtGbThV0viQaVl3yBec6DgXEP5XeYA6RtUr P2mf2gF3OTvrqyzQygxO6BPEAv0gCRKM61FROSqf+ZjP+eyEEyGgan2zEKr4jqOKxuEy t239U9NF/Q6PJi5HRb5lSZ3vBXlBdzx/EqC5+qa8zJl4gZb/ltNbjSX2/q6Lp2HiIUlI O37Q7aY3xG/vUFMLld0kxlPOmH1JIDPAfbMI6+WlaBSKIdKd8pX0IS7MF2GR7abnwSvk yfQA== X-Gm-Message-State: AOJu0YxpH+d3M1oUf1GGEkg4O08tJkLvRxxZBp/i+0G0GCMabPBzWSrc xcfZgc0g64mJZNSEonJpB4kJ5s2BYaWVIB4Of0NwRYlW0Jq+OVVRQF57UqSHXty75/iWAN5/WT6 4 X-Google-Smtp-Source: AGHT+IGe8yiK9Wol7Ag8uXF3OOWu4DfxzeZBV900Fclb9ozPEx1Z1EHR2puPMDBwLJLjCXhtH3UN1Q== X-Received: by 2002:a17:90b:46c8:b0:2a2:50ef:ece2 with SMTP id jx8-20020a17090b46c800b002a250efece2mr4154763pjb.17.1712985821014; Fri, 12 Apr 2024 22:23:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, philmd@linaro.org Subject: [PATCH 5/6] disas/cris: Remove struct cris_disasm_data Date: Fri, 12 Apr 2024 22:23:32 -0700 Message-Id: <20240413052333.688151-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240413052333.688151-1-richard.henderson@linaro.org> References: <20240413052333.688151-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1712985932422100018 Content-Type: text/plain; charset="utf-8" As the structure contains one element, pass the element around instead of the structure. Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias --- disas/cris.c | 187 +++++++++++++++++++++------------------------------ 1 file changed, 76 insertions(+), 111 deletions(-) diff --git a/disas/cris.c b/disas/cris.c index 692cd4d163..71c292188a 100644 --- a/disas/cris.c +++ b/disas/cris.c @@ -1239,30 +1239,11 @@ cris_cc_strings[] =3D enum cris_disass_family { cris_dis_v0_v10, cris_dis_common_v10_v32, cris_dis_v32 }; =20 -/* Stored in the disasm_info->private_data member. */ -struct cris_disasm_data -{ - /* Whether this code is flagged as crisv32. FIXME: Should be an enum - that includes "compatible". */ - enum cris_disass_family distype; -}; - -static int cris_constraint - (const char *, unsigned, unsigned, struct cris_disasm_data *); - -/* Parse disassembler options and store state in info. FIXME: For the - time being, we abuse static variables. */ - -static void -cris_parse_disassembler_options (struct cris_disasm_data *disdata, - char *disassembler_options, - enum cris_disass_family distype) -{ - disdata->distype =3D distype; -} +static int cris_constraint(const char *, unsigned, unsigned, + enum cris_disass_family); =20 static const struct cris_spec_reg * -spec_reg_info (unsigned int sreg, enum cris_disass_family distype) +spec_reg_info(unsigned int sreg, enum cris_disass_family distype) { int i; =20 @@ -1309,9 +1290,9 @@ number_of_bits (unsigned int val) /* Get an entry in the opcode-table. */ =20 static const struct cris_opcode * -get_opcode_entry (unsigned int insn, - unsigned int prefix_insn, - struct cris_disasm_data *disdata) +get_opcode_entry(unsigned int insn, + unsigned int prefix_insn, + enum cris_disass_family distype) { /* For non-prefixed insns, we keep a table of pointers, indexed by the insn code. Each entry is initialized when found to be NULL. */ @@ -1349,7 +1330,7 @@ get_opcode_entry (unsigned int insn, const struct cris_opcode *popcodep =3D (opc_table[prefix_insn] !=3D NULL ? opc_table[prefix_insn] - : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata)); + : get_opcode_entry(prefix_insn, NO_CRIS_PREFIX, distype)); =20 if (popcodep =3D=3D NULL) return NULL; @@ -1406,7 +1387,7 @@ get_opcode_entry (unsigned int insn, { int level_of_match; =20 - if (disdata->distype =3D=3D cris_dis_v32) + if (distype =3D=3D cris_dis_v32) { switch (opcodep->applicable_version) { @@ -1469,10 +1450,8 @@ get_opcode_entry (unsigned int insn, if ((opcodep->match & insn) =3D=3D opcodep->match && (opcodep->lose & insn) =3D=3D 0 && ((level_of_match - =3D cris_constraint (opcodep->args, - insn, - prefix_insn, - disdata)) + =3D cris_constraint(opcodep->args, insn, + prefix_insn, distype)) >=3D 0) && ((level_of_match +=3D 2 * number_of_bits (opcodep->match @@ -1509,10 +1488,10 @@ get_opcode_entry (unsigned int insn, indicating the confidence in the match (higher is better). */ =20 static int -cris_constraint (const char *cs, - unsigned int insn, - unsigned int prefix_insn, - struct cris_disasm_data *disdata) +cris_constraint(const char *cs, + unsigned int insn, + unsigned int prefix_insn, + enum cris_disass_family distype) { int retval =3D 0; int tmp; @@ -1526,7 +1505,7 @@ cris_constraint (const char *cs, /* Do not recognize "pop" if there's a prefix and then only for v0..v10. */ if (prefix_insn !=3D NO_CRIS_PREFIX - || disdata->distype !=3D cris_dis_v0_v10) + || distype !=3D cris_dis_v0_v10) return -1; break; =20 @@ -1569,7 +1548,7 @@ cris_constraint (const char *cs, if (insn & 0x400) { const struct cris_opcode *prefix_opcodep - =3D get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disda= ta); + =3D get_opcode_entry(prefix_insn, NO_CRIS_PREFIX, distyp= e); =20 if (prefix_opcodep->match =3D=3D DIP_OPCODE) return -1; @@ -1589,7 +1568,7 @@ cris_constraint (const char *cs, { /* Match the prefix insn to BDAPQ. */ const struct cris_opcode *prefix_opcodep - =3D get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata); + =3D get_opcode_entry(prefix_insn, NO_CRIS_PREFIX, distype); =20 if (prefix_opcodep->match =3D=3D BDAP_QUICK_OPCODE) { @@ -1602,7 +1581,7 @@ cris_constraint (const char *cs, { unsigned int spec_reg =3D (insn >> 12) & 15; const struct cris_spec_reg *sregp - =3D spec_reg_info (spec_reg, disdata->distype); + =3D spec_reg_info(spec_reg, distype); =20 /* For a special-register, the "prefix size" must match the size of the register. */ @@ -1631,7 +1610,7 @@ cris_constraint (const char *cs, case 'P': { const struct cris_spec_reg *sregp - =3D spec_reg_info ((insn >> 12) & 15, disdata->distype); + =3D spec_reg_info((insn >> 12) & 15, distype); =20 /* Since we match four bits, we will give a value of 4-1 =3D 3 in a match. If there is a corresponding exact match of a @@ -1688,7 +1667,7 @@ format_dec(long number, GString *str, int signedp) /* Format the name of the general register regno into outbuffer. */ =20 static void -format_reg(struct cris_disasm_data *disdata, int regno, GString *str) +format_reg(enum cris_disass_family distype, int regno, GString *str) { g_string_append_c(str, REGISTER_PREFIX_CHAR); =20 @@ -1696,7 +1675,7 @@ format_reg(struct cris_disasm_data *disdata, int regn= o, GString *str) { case 15: /* For v32, there is no context in which we output PC. */ - if (disdata->distype =3D=3D cris_dis_v32) + if (distype =3D=3D cris_dis_v32) g_string_append(str, "acr"); else g_string_append(str, "pc"); @@ -1736,10 +1715,10 @@ format_sup_reg(unsigned int regno, GString *str) /* Return the length of an instruction. */ =20 static unsigned -bytes_to_skip (unsigned int insn, - const struct cris_opcode *matchedp, - enum cris_disass_family distype, - const struct cris_opcode *prefix_matchedp) +bytes_to_skip(unsigned int insn, + const struct cris_opcode *matchedp, + enum cris_disass_family distype, + const struct cris_opcode *prefix_matchedp) { /* Each insn is a word plus "immediate" operands. */ unsigned to_skip =3D 2; @@ -1760,7 +1739,7 @@ bytes_to_skip (unsigned int insn, else if (matchedp->imm_oprnd_size =3D=3D SIZE_SPEC_REG) { const struct cris_spec_reg *sregp - =3D spec_reg_info ((insn >> 12) & 15, distype); + =3D spec_reg_info((insn >> 12) & 15, distype); =20 /* FIXME: Improve error handling; should have been caught earlier. */ @@ -1787,7 +1766,7 @@ bytes_to_skip (unsigned int insn, /* Print condition code flags. */ =20 static void -print_flags(struct cris_disasm_data *disdata, unsigned int insn, GString *= str) +print_flags(enum cris_disass_family distype, unsigned int insn, GString *s= tr) { /* Use the v8 (Etrax 100) flag definitions for disassembly. The differences with v0 (Etrax 1..4) vs. Svinto are: @@ -1796,8 +1775,7 @@ print_flags(struct cris_disasm_data *disdata, unsigne= d int insn, GString *str) FIXME: Emit v0..v3 flag names somehow. */ static const char v8_fnames[] =3D "cvznxibm"; static const char v32_fnames[] =3D "cvznxiup"; - const char *fnames - =3D disdata->distype =3D=3D cris_dis_v32 ? v32_fnames : v8_fnames; + const char *fnames =3D distype =3D=3D cris_dis_v32 ? v32_fnames : v8_fna= mes; =20 unsigned char flagbits =3D (((insn >> 8) & 0xf0) | (insn & 15)); int i; @@ -1812,24 +1790,25 @@ print_flags(struct cris_disasm_data *disdata, unsig= ned int insn, GString *str) supposed to be output as an address mode. */ =20 static void -print_with_operands (const struct cris_opcode *opcodep, - unsigned int insn, - unsigned char *buffer, - bfd_vma addr, - disassemble_info *info, - /* If a prefix insn was before this insn (and is supp= osed - to be output as an address), here is a description= of - it. */ - const struct cris_opcode *prefix_opcodep, - unsigned int prefix_insn, - unsigned char *prefix_buffer) +print_with_operands(const struct cris_opcode *opcodep, + unsigned int insn, + unsigned char *buffer, + bfd_vma addr, + disassemble_info *info, + /* + * If a prefix insn was before this insn + * (and is supposed to be output as an address), + * here is a description of it. + */ + const struct cris_opcode *prefix_opcodep, + unsigned int prefix_insn, + unsigned char *prefix_buffer, + enum cris_disass_family distype) { g_autoptr(GString) str =3D g_string_new(opcodep->name); static const char mode_char[] =3D "bwd?"; const char *s; const char *cs; - struct cris_disasm_data *disdata - =3D (struct cris_disasm_data *) info->private_data; =20 cs =3D opcodep->args; s =3D cs; @@ -1912,11 +1891,11 @@ print_with_operands (const struct cris_opcode *opco= dep, =20 case 'D': case 'r': - format_reg(disdata, insn & 15, str); + format_reg(distype, insn & 15, str); break; =20 case 'R': - format_reg(disdata, (insn >> 12) & 15, str); + format_reg(distype, (insn >> 12) & 15, str); break; =20 case 'n': @@ -1960,7 +1939,7 @@ print_with_operands (const struct cris_opcode *opcode= p, else if (opcodep->imm_oprnd_size =3D=3D SIZE_SPEC_REG) { const struct cris_spec_reg *sregp - =3D spec_reg_info ((insn >> 12) & 15, disdata->distype); + =3D spec_reg_info((insn >> 12) & 15, distype); =20 /* A NULL return should have been as a non-match earlier, so catch it as an internal error in the error-case @@ -1972,7 +1951,7 @@ print_with_operands (const struct cris_opcode *opcode= p, /* PC is always incremented by a multiple of two. For CRISv32, immediates are always 4 bytes for special registers. */ - nbytes =3D disdata->distype =3D=3D cris_dis_v32 + nbytes =3D distype =3D=3D cris_dis_v32 ? 4 : (sregp->reg_size + 1) & ~1; } else @@ -2035,7 +2014,7 @@ print_with_operands (const struct cris_opcode *opcode= p, else if (opcodep->imm_oprnd_size =3D=3D SIZE_SPEC_REG) { const struct cris_spec_reg *sregp - =3D spec_reg_info ((insn >> 12) & 15, disdata->disty= pe); + =3D spec_reg_info((insn >> 12) & 15, distype); =20 /* FIXME: Improve error handling; should have been cau= ght earlier. */ @@ -2060,7 +2039,7 @@ print_with_operands (const struct cris_opcode *opcode= p, { if (insn & 0x400) { - format_reg(disdata, insn & 15, str); + format_reg(distype, insn & 15, str); g_string_append_c(str, '=3D'); } =20 @@ -2093,7 +2072,7 @@ print_with_operands (const struct cris_opcode *opcode= p, info->target2 =3D prefix_insn & 15; =20 g_string_append_c(str, '['); - format_reg(disdata, prefix_insn & 15, str); + format_reg(distype, prefix_insn & 15, str); if (prefix_insn & 0x400) g_string_append_c(str, '+'); g_string_append_c(str, ']'); @@ -2109,7 +2088,7 @@ print_with_operands (const struct cris_opcode *opcode= p, number -=3D 256; =20 /* Output "reg+num" or, if num < 0, "reg-num". */ - format_reg(disdata, (prefix_insn >> 12) & 15, str); + format_reg(distype, (prefix_insn >> 12) & 15, str); if (number >=3D 0) g_string_append_c(str, '+'); format_dec(number, str, 1); @@ -2122,9 +2101,9 @@ print_with_operands (const struct cris_opcode *opcode= p, =20 case BIAP_OPCODE: /* Output "r+R.m". */ - format_reg(disdata, prefix_insn & 15, str); + format_reg(distype, prefix_insn & 15, str); g_string_append_c(str, '+'); - format_reg(disdata, (prefix_insn >> 12) & 15, str); + format_reg(distype, (prefix_insn >> 12) & 15, str); g_string_append_c(str, '.'); g_string_append_c(str, mode_char[(prefix_insn >> 4) & = 3]); =20 @@ -2139,7 +2118,7 @@ print_with_operands (const struct cris_opcode *opcode= p, =20 case BDAP_INDIR_OPCODE: /* Output "r+s.m", or, if "s" is [pc+], "r+s" or "r-s"= . */ - format_reg(disdata, (prefix_insn >> 12) & 15, str); + format_reg(distype, (prefix_insn >> 12) & 15, str); =20 if ((prefix_insn & 0x400) && (prefix_insn & 15) =3D=3D= 15) { @@ -2202,7 +2181,7 @@ print_with_operands (const struct cris_opcode *opcode= p, /* Output "r+[R].m" or "r+[R+].m". */ g_string_append_c(str, '+'); g_string_append_c(str, '['); - format_reg(disdata, prefix_insn & 15, str); + format_reg(distype, prefix_insn & 15, str); if (prefix_insn & 0x400) g_string_append_c(str, '+'); g_string_append_c(str, ']'); @@ -2230,7 +2209,7 @@ print_with_operands (const struct cris_opcode *opcode= p, } else { - format_reg(disdata, insn & 15, str); + format_reg(distype, insn & 15, str); =20 info->flags |=3D CRIS_DIS_FLAG_MEM_TARGET_IS_REG; info->target =3D insn & 15; @@ -2243,7 +2222,7 @@ print_with_operands (const struct cris_opcode *opcode= p, break; =20 case 'x': - format_reg(disdata, (insn >> 12) & 15, str); + format_reg(distype, (insn >> 12) & 15, str); g_string_append_c(str, '.'); g_string_append_c(str, mode_char[(insn >> 4) & 3]); break; @@ -2259,7 +2238,7 @@ print_with_operands (const struct cris_opcode *opcode= p, if (where > 32767) where -=3D 65536; =20 - where +=3D addr + ((disdata->distype =3D=3D cris_dis_v32) ? 0 : = 4); + where +=3D addr + ((distype =3D=3D cris_dis_v32) ? 0 : 4); =20 if (insn =3D=3D BA_PC_INCR_OPCODE) info->insn_type =3D dis_branch; @@ -2294,7 +2273,7 @@ print_with_operands (const struct cris_opcode *opcode= p, else info->insn_type =3D dis_condbranch; =20 - target =3D addr + ((disdata->distype =3D=3D cris_dis_v32) ? 0 : 2)= + offset; + target =3D addr + (distype =3D=3D cris_dis_v32 ? 0 : 2) + offset; info->target =3D target; format_hex(target, str); } @@ -2310,12 +2289,12 @@ print_with_operands (const struct cris_opcode *opco= dep, =20 format_dec(number, str, 1); g_string_append_c(str, ','); - format_reg(disdata, (insn >> 12) & 15, str); + format_reg(distype, (insn >> 12) & 15, str); } break; =20 case 'f': - print_flags(disdata, insn, str); + print_flags(distype, insn, str); break; =20 case 'i': @@ -2325,7 +2304,7 @@ print_with_operands (const struct cris_opcode *opcode= p, case 'P': { const struct cris_spec_reg *sregp - =3D spec_reg_info ((insn >> 12) & 15, disdata->distype); + =3D spec_reg_info((insn >> 12) & 15, distype); =20 if (sregp =3D=3D NULL || sregp->name =3D=3D NULL) /* Should have been caught as a non-match earlier. */ @@ -2356,15 +2335,14 @@ print_with_operands (const struct cris_opcode *opco= dep, WITH_REG_PREFIX. */ =20 static int -print_insn_cris_generic (bfd_vma memaddr, - disassemble_info *info) +print_insn_cris_generic(bfd_vma memaddr, + disassemble_info *info, + enum cris_disass_family distype) { int nbytes; unsigned int insn; const struct cris_opcode *matchedp; int advance =3D 0; - struct cris_disasm_data *disdata - =3D (struct cris_disasm_data *) info->private_data; =20 /* No instruction will be disassembled as longer than this number of bytes; stacked prefixes will not be expanded. */ @@ -2416,7 +2394,7 @@ print_insn_cris_generic (bfd_vma memaddr, of a nuiscance that we will just output "bcc .+2" for it and signal it as a noninsn. */ (*info->fprintf_func) (info->stream, - disdata->distype =3D=3D cris_dis_v32 + distype =3D=3D cris_dis_v32 ? "bcc ." : "bcc .+2"); info->insn_type =3D dis_noninsn; advance +=3D 2; @@ -2428,7 +2406,7 @@ print_insn_cris_generic (bfd_vma memaddr, unsigned int prefix_insn =3D insn; int prefix_size =3D 0; =20 - matchedp =3D get_opcode_entry (insn, NO_CRIS_PREFIX, disdata); + matchedp =3D get_opcode_entry(insn, NO_CRIS_PREFIX, distype); =20 /* Check if we're supposed to write out prefixes as address modes and if this was a prefix. */ @@ -2436,12 +2414,11 @@ print_insn_cris_generic (bfd_vma memaddr, { /* If it's a prefix, put it into the prefix vars and get the main insn. */ - prefix_size =3D bytes_to_skip (prefix_insn, matchedp, - disdata->distype, NULL); + prefix_size =3D bytes_to_skip(prefix_insn, matchedp, distype= , NULL); prefix_opcodep =3D matchedp; =20 insn =3D bufp[prefix_size] + bufp[prefix_size + 1] * 256; - matchedp =3D get_opcode_entry (insn, prefix_insn, disdata); + matchedp =3D get_opcode_entry(insn, prefix_insn, distype); =20 if (matchedp !=3D NULL) { @@ -2469,15 +2446,13 @@ print_insn_cris_generic (bfd_vma memaddr, } else { - advance - +=3D bytes_to_skip (insn, matchedp, disdata->distype, - prefix_opcodep); + advance +=3D bytes_to_skip(insn, matchedp, distype, prefix_o= pcodep); =20 /* The info_type and assorted fields will be set according to the operands. */ - print_with_operands (matchedp, insn, bufp, addr, info, - prefix_opcodep, prefix_insn, - prefix_buffer); + print_with_operands(matchedp, insn, bufp, addr, info, + prefix_opcodep, prefix_insn, + prefix_buffer, distype); } } } @@ -2513,23 +2488,13 @@ print_insn_cris_generic (bfd_vma memaddr, } =20 int -print_insn_crisv10 (bfd_vma vma, - disassemble_info *info) +print_insn_crisv10(bfd_vma vma, disassemble_info *info) { - struct cris_disasm_data disdata; - info->private_data =3D &disdata; - cris_parse_disassembler_options (&disdata, info->disassembler_options, - cris_dis_v0_v10); - return print_insn_cris_generic (vma, info); + return print_insn_cris_generic(vma, info, cris_dis_v0_v10); } =20 int -print_insn_crisv32 (bfd_vma vma, - disassemble_info *info) +print_insn_crisv32(bfd_vma vma, disassemble_info *info) { - struct cris_disasm_data disdata; - info->private_data =3D &disdata; - cris_parse_disassembler_options (&disdata, info->disassembler_options, - cris_dis_v32); - return print_insn_cris_generic (vma, info); + return print_insn_cris_generic(vma, info, cris_dis_v32); } --=20 2.34.1 From nobody Thu May 16 09:54:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1712985930; cv=none; d=zohomail.com; s=zohoarc; b=kFEm4nsGLmxHlDO8U6e82/USId5FsfpWDUSHOea36nTkKGzgENtOxDQ+vs/AI9tT+tn6jVKRNg2bS6gLV86MWypf8PFbi/OzdhKNTsPk7LnklvRdsMWB4wxjGj406Xl+V4cxv9DPiEzg4t0Bv5uHtAzyg723UZx5ArlewxSLpU4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1712985930; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1i3GYPODdGEunG05Dn7518COsozxbeHPzw45fI5pR1c=; b=ntWeS25DAjJ7I2KFfoP911E+ySTtaRvq3pAMqYdXFgZD+Rj11j2FbsmnErbwM9b27bP9lIfzmVxVXuCugEANP6skerB+gTTw/0h/O+P3XkBUM/20H42iZUJoLvSKsrVSyqJtj/7EUGessu/KmmtZrEnK1vqs6gIc0XbozqNdAx8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 171298593090319.735627185441444; Fri, 12 Apr 2024 22:25:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rvVrf-0001u5-H9; Sat, 13 Apr 2024 01:23:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rvVrd-0001ta-8i for qemu-devel@nongnu.org; Sat, 13 Apr 2024 01:23:45 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rvVrb-0001da-HA for qemu-devel@nongnu.org; Sat, 13 Apr 2024 01:23:44 -0400 Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1e2bbc2048eso13204925ad.3 for ; Fri, 12 Apr 2024 22:23:42 -0700 (PDT) Received: from stoup.. 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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id v19-20020a17090abb9300b002a0544b81d6sm3564074pjr.35.2024.04.12.22.23.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Apr 2024 22:23:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712985822; x=1713590622; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1i3GYPODdGEunG05Dn7518COsozxbeHPzw45fI5pR1c=; b=VNApF3/hWFHop3H4G2rHERoXM7b22zAN6+1OnAOZSUQ0vRmBA/EKJ0FYfQmd39EmXK WPlU4MeOg1m16VCrA/TiWrfjLVzdcwj01kPA8rkSI9CaVId1ISjHHXh9JRIxz7pUCEA7 +tGhoIjSEwRZitRXpcFyWjjqQTwrD+19UdfMTrGq5eQdDUZxSj2BBdoyGAPuMgad21Qt M6RQRDltUMtZXWDJtxpPVeCKiNH9jBN3USdPMdqkFXY0Pk4tcIaKvdaDU9zkZmWzdn44 Pzb2ngOXNYJdJfu3a8KrfFeZmBZV8LEMFoIlk7r9yjB0dti4Pcm8lEVByyqWl9AAz35O 5hcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712985822; x=1713590622; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1i3GYPODdGEunG05Dn7518COsozxbeHPzw45fI5pR1c=; b=vbgVlLd5RhgKcWYsRt3gzrsSewWTqO55QRN2PomGmbeekU/8YCgJ/hWLOqXwr4HNTn OBiOZl19lwVIWD+44r0Dyw5tvWiH/t4uwtMQzelZB4zGSRSZsj41eDqRaEfBhMzUWpkz NDPz7vDoIP9R4HRhAO8r32PYqfJtlSc71hy9tFbMwrxqsVnHFjRsQIj/v3c51VLJ1Hn1 HeSSlxvdddF0B0n+Rs7ucYf9UPougIpUKh0gQ8w2fkwGeTmwiuEpmne+37eAcJHfWGr1 IsMSyeFn9eVOcoCsJ+h4/XyloJ8U2J+842rGaUMZyDan6J6JDivKPbNYHjep0+7jvbL1 b9ng== X-Gm-Message-State: AOJu0YwU6cOBZW6XuRenl5JyNdPo/QB4a8UfK3ialSqw9EHnm8aje1BA YQMyv6EtRgLna7fW6EoU7Tz9kRTkNMrscCkZwBHwXVeetRXds5l3cUPSvg7/FijkAQHD2ixTpHB t X-Google-Smtp-Source: AGHT+IGC78uYqxyTgow5ZpgGrA5vO4+oDzbQp5d/T/Jvjdm81AEEDXml1BmiZpixiFFJAaQVnWnXDg== X-Received: by 2002:a05:6a20:5648:b0:1a7:47ff:5f3e with SMTP id is8-20020a056a20564800b001a747ff5f3emr4370168pzc.9.1712985821960; Fri, 12 Apr 2024 22:23:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, philmd@linaro.org Subject: [PATCH 6/6] disas/cris: Improve output of register names Date: Fri, 12 Apr 2024 22:23:33 -0700 Message-Id: <20240413052333.688151-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240413052333.688151-1-richard.henderson@linaro.org> References: <20240413052333.688151-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1712985932385100014 Content-Type: text/plain; charset="utf-8" Add REGISTER_PREFIX as a string literal that may be concatenated with other string literals. Use a table of the 16 register names instead of using g_string_append_printf. Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias --- disas/cris.c | 45 +++++++++++++++++++++++++-------------------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/disas/cris.c b/disas/cris.c index 71c292188a..01ea63c428 100644 --- a/disas/cris.c +++ b/disas/cris.c @@ -1234,6 +1234,7 @@ cris_cc_strings[] =3D #endif =20 /* Sometimes we prefix all registers with this character. */ +#define REGISTER_PREFIX "$" #define REGISTER_PREFIX_CHAR '$' =20 enum cris_disass_family @@ -1669,26 +1670,31 @@ format_dec(long number, GString *str, int signedp) static void format_reg(enum cris_disass_family distype, int regno, GString *str) { - g_string_append_c(str, REGISTER_PREFIX_CHAR); + static const char reg_names[16][5] =3D { + REGISTER_PREFIX "r0", + REGISTER_PREFIX "r1", + REGISTER_PREFIX "r2", + REGISTER_PREFIX "r3", + REGISTER_PREFIX "r4", + REGISTER_PREFIX "r5", + REGISTER_PREFIX "r6", + REGISTER_PREFIX "r7", + REGISTER_PREFIX "r8", + REGISTER_PREFIX "r9", + REGISTER_PREFIX "r10", + REGISTER_PREFIX "r11", + REGISTER_PREFIX "r12", + REGISTER_PREFIX "r13", + REGISTER_PREFIX "sp", + REGISTER_PREFIX "pc", + }; + const char *name =3D reg_names[regno]; =20 - switch (regno) - { - case 15: - /* For v32, there is no context in which we output PC. */ - if (distype =3D=3D cris_dis_v32) - g_string_append(str, "acr"); - else - g_string_append(str, "pc"); - break; + /* For v32, there is no context in which we output PC. */ + if (regno =3D=3D 15 && distype =3D=3D cris_dis_v32) + name =3D REGISTER_PREFIX "acr"; =20 - case 14: - g_string_append(str, "sp"); - break; - - default: - g_string_append_printf(str, "r%d", regno); - break; - } + g_string_append(str, name); } =20 /* Format the name of a support register into outbuffer. */ @@ -1861,8 +1867,7 @@ print_with_operands(const struct cris_opcode *opcodep, break; =20 case 'A': - g_string_append_c(str, REGISTER_PREFIX_CHAR); - g_string_append(str, "acr"); + g_string_append(str, REGISTER_PREFIX "acr"); break; =20 case '[': --=20 2.34.1