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b=PPrqORmVLQSfvyDINnVHP/qc0O/WzYWjCCAbA/4Kb9uyqOOCwtjX40uqkgp+x31+V3XU ht0RSVRQ0i4ro0bCJN9mJ7jEjSKyZ/ec5PBNKRHMQLQ3KfR1APZRHGEcWiDNKxU17MRh iPtTe5+U05C+A47jDFHFX6DANNBxzSyVxJoVE6/UjM4KDl5yS8ZXfG04Y5JZDxN7OWre hfhQA96yQUMaf0PeOQJVxKSgIyibqQf4ZYguPmSm7xDvXUvOMfZ6h2blClGpg6VofXZB qsyutxmyiwiV3W01LraLwtxQHN92NBNY0B58aXOySr7neyZOeISd414Huxe0IUVCj527 3Q== From: Glenn Miles To: qemu-ppc@nongnu.org Cc: Glenn Miles , qemu-devel@nongnu.org, Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nicholas Piggin , David Gibson , Peter Maydell Subject: [PATCH v4 1/4] target/ppc: Add new hflags to support BHRB Date: Thu, 28 Mar 2024 14:23:53 -0500 Message-Id: <20240328192356.2144086-2-milesg@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.8 In-Reply-To: <20240328192356.2144086-1-milesg@linux.vnet.ibm.com> References: <20240328192356.2144086-1-milesg@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: jDtcGsQ_HrMMEzevIowlzgEnEgWaGoSi X-Proofpoint-ORIG-GUID: _1BArnR6kyC07JhEe76u3FgNHUN6sj18 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-28_17,2024-03-28_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 malwarescore=0 suspectscore=0 spamscore=0 mlxlogscore=999 bulkscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2403210000 definitions=main-2403280136 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.156.1; envelope-from=milesg@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1711653933730100003 Content-Type: text/plain; charset="utf-8" This commit is preparatory to the addition of Branch History Rolling Buffer (BHRB) functionality, which is being provided today starting with the P8 processor. BHRB uses several SPR register fields to control whether or not a branch instruction's address (and sometimes target address) should be recorded. Checking each of these fields with each branch instruction using jitted code would lead to a significant decrease in performance. Therefore, it was decided that BHRB configuration bits that are not expected to change frequently should have their state summarized in an hflag so that the amount of checking done by jitted code can be reduced. This commit contains the changes for summarizing the state of the following register fields in the HFLAGS_BHRB_ENABLE hflag: MMCR0[FCP] - Determines if BHRB recording is frozen in the problem state MMCR0[FCPC] - A modifier for MMCR0[FCP] MMCRA[BHRBRD] - Disables all BHRB recording for a thread Signed-off-by: Glenn Miles Reviewed-by: Nicholas Piggin --- Changes from v3: - Rebased on latest master branch - Fixed compile errors from non ppc64-softmmu targets target/ppc/cpu.h | 5 +++++ target/ppc/cpu_init.c | 4 ++-- target/ppc/helper.h | 1 + target/ppc/helper_regs.c | 37 ++++++++++++++++++++++++++++++++ target/ppc/machine.c | 2 +- target/ppc/power8-pmu-regs.c.inc | 5 +++++ target/ppc/power8-pmu.c | 15 +++++++++---- target/ppc/power8-pmu.h | 4 ++-- target/ppc/spr_common.h | 1 + target/ppc/translate.c | 2 ++ 10 files changed, 67 insertions(+), 9 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 67e6b2effd..3f6b93ca8f 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -535,6 +535,8 @@ FIELD(MSR, LE, MSR_LE, 1) #define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */ #define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */ #define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */ +#define MMCR0_FCP PPC_BIT(34) /* Freeze Counters/BHRB if PR=3D1= */ +#define MMCR0_FCPC PPC_BIT(51) /* Condition for FCP bit */ /* MMCR0 userspace r/w mask */ #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE) /* MMCR2 userspace r/w mask */ @@ -547,6 +549,8 @@ FIELD(MSR, LE, MSR_LE, 1) #define MMCR2_UREG_MASK (MMCR2_FC1P0 | MMCR2_FC2P0 | MMCR2_FC3P0 | \ MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0) =20 +#define MMCRA_BHRBRD PPC_BIT(26) /* BHRB Recording Disable */ + #define MMCR1_EVT_SIZE 8 /* extract64() does a right shift before extracting */ #define MMCR1_PMC1SEL_START 32 @@ -799,6 +803,7 @@ enum { HFLAGS_PMCJCE =3D 17, /* MMCR0 PMCjCE bit */ HFLAGS_PMC_OTHER =3D 18, /* PMC other than PMC5-6 is enabled */ HFLAGS_INSN_CNT =3D 19, /* PMU instruction count enabled */ + HFLAGS_BHRB_ENABLE =3D 20, /* Summary flag for enabling BHRB */ HFLAGS_VSX =3D 23, /* MSR_VSX if cpu has VSX */ HFLAGS_VR =3D 25, /* MSR_VR if cpu has VRE */ =20 diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 7e65f08147..4e65335669 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5152,7 +5152,7 @@ static void register_book3s_pmu_sup_sprs(CPUPPCState = *env) KVM_REG_PPC_MMCR1, 0x00000000); spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_MMCRA, KVM_REG_PPC_MMCRA, 0x00000000); spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", SPR_NOACCESS, SPR_NOACCESS, @@ -7194,7 +7194,7 @@ static void ppc_cpu_reset_hold(Object *obj) if (env->mmu_model !=3D POWERPC_MMU_REAL) { ppc_tlb_invalidate_all(env); } - pmu_mmcr01_updated(env); + pmu_mmcr01a_updated(env); } =20 /* clean any pending stop state */ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 86f97ee1e7..3df360efe9 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -30,6 +30,7 @@ DEF_HELPER_2(store_dawr0, void, env, tl) DEF_HELPER_2(store_dawrx0, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) DEF_HELPER_2(store_mmcr1, void, env, tl) +DEF_HELPER_2(store_mmcrA, void, env, tl) DEF_HELPER_3(store_pmc, void, env, i32, i64) DEF_HELPER_2(read_pmc, tl, env, i32) DEF_HELPER_2(insns_inc, void, env, i32) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 25258986e3..07a07ae720 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -47,6 +47,39 @@ void hreg_swap_gpr_tgpr(CPUPPCState *env) env->tgpr[3] =3D tmp; } =20 +#if defined(TARGET_PPC64) +static bool hreg_check_bhrb_enable(CPUPPCState *env) +{ + bool pr =3D !!(env->msr & (1 << MSR_PR)); + target_long mmcr0; + bool fcp; + bool hv; + + /* ISA 3.1 adds the PMCRA[BRHBRD] and problem state checks */ + if ((env->insns_flags2 & PPC2_ISA310) && + ((env->spr[SPR_POWER_MMCRA] & MMCRA_BHRBRD) || !pr)) { + return false; + } + + /* Check for BHRB "frozen" conditions */ + mmcr0 =3D env->spr[SPR_POWER_MMCR0]; + fcp =3D !!(mmcr0 & MMCR0_FCP); + if (mmcr0 & MMCR0_FCPC) { + hv =3D !!(env->msr & (1ull << MSR_HV)); + if (fcp) { + if (hv && pr) { + return false; + } + } else if (!hv && pr) { + return false; + } + } else if (fcp && pr) { + return false; + } + return true; +} +#endif + static uint32_t hreg_compute_pmu_hflags_value(CPUPPCState *env) { uint32_t hflags =3D 0; @@ -61,6 +94,9 @@ static uint32_t hreg_compute_pmu_hflags_value(CPUPPCState= *env) if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE) { hflags |=3D 1 << HFLAGS_PMCJCE; } + if (hreg_check_bhrb_enable(env)) { + hflags |=3D 1 << HFLAGS_BHRB_ENABLE; + } =20 #ifndef CONFIG_USER_ONLY if (env->pmc_ins_cnt) { @@ -85,6 +121,7 @@ static uint32_t hreg_compute_pmu_hflags_mask(CPUPPCState= *env) hflags_mask |=3D 1 << HFLAGS_PMCJCE; hflags_mask |=3D 1 << HFLAGS_INSN_CNT; hflags_mask |=3D 1 << HFLAGS_PMC_OTHER; + hflags_mask |=3D 1 << HFLAGS_BHRB_ENABLE; #endif return hflags_mask; } diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 203fe28e01..6b6c31d903 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -333,7 +333,7 @@ static int cpu_post_load(void *opaque, int version_id) * triggered types (including HDEC) would need to carry more state. */ cpu_ppc_store_decr(env, env->spr[SPR_DECR]); - pmu_mmcr01_updated(env); + pmu_mmcr01a_updated(env); } =20 return 0; diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.= c.inc index 4956a8b350..652cf20704 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -175,6 +175,11 @@ void spr_write_MMCR2_ureg(DisasContext *ctx, int sprn,= int gprn) gen_store_spr(SPR_POWER_MMCR2, masked_gprn); } =20 +void spr_write_MMCRA(DisasContext *ctx, int sprn, int gprn) +{ + gen_helper_store_mmcrA(tcg_env, cpu_gpr[gprn]); +} + void spr_read_PMC(DisasContext *ctx, int gprn, int sprn) { TCGv_i32 t_sprn =3D tcg_constant_i32(sprn); diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index cbc5889d91..6f5d4e1256 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -82,7 +82,7 @@ static void pmu_update_summaries(CPUPPCState *env) env->pmc_cyc_cnt =3D cyc_cnt; } =20 -void pmu_mmcr01_updated(CPUPPCState *env) +void pmu_mmcr01a_updated(CPUPPCState *env) { PowerPCCPU *cpu =3D env_archcpu(env); =20 @@ -260,7 +260,7 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong = value) =20 env->spr[SPR_POWER_MMCR0] =3D value; =20 - pmu_mmcr01_updated(env); + pmu_mmcr01a_updated(env); =20 /* Update cycle overflow timers with the current MMCR0 state */ pmu_update_overflow_timers(env); @@ -272,7 +272,14 @@ void helper_store_mmcr1(CPUPPCState *env, uint64_t val= ue) =20 env->spr[SPR_POWER_MMCR1] =3D value; =20 - pmu_mmcr01_updated(env); + pmu_mmcr01a_updated(env); +} + +void helper_store_mmcrA(CPUPPCState *env, uint64_t value) +{ + env->spr[SPR_POWER_MMCRA] =3D value; + + pmu_mmcr01a_updated(env); } =20 target_ulong helper_read_pmc(CPUPPCState *env, uint32_t sprn) @@ -301,7 +308,7 @@ static void perfm_alert(PowerPCCPU *cpu) env->spr[SPR_POWER_MMCR0] |=3D MMCR0_FC; =20 /* Changing MMCR0_FC requires summaries and hflags update */ - pmu_mmcr01_updated(env); + pmu_mmcr01a_updated(env); =20 /* * Delete all pending timers if we need to freeze diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h index 775e640053..87fa8c9334 100644 --- a/target/ppc/power8-pmu.h +++ b/target/ppc/power8-pmu.h @@ -18,10 +18,10 @@ #define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL =20 void cpu_ppc_pmu_init(CPUPPCState *env); -void pmu_mmcr01_updated(CPUPPCState *env); +void pmu_mmcr01a_updated(CPUPPCState *env); #else static inline void cpu_ppc_pmu_init(CPUPPCState *env) { } -static inline void pmu_mmcr01_updated(CPUPPCState *env) { } +static inline void pmu_mmcr01a_updated(CPUPPCState *env) { } #endif =20 #endif diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h index 8a9d6cd994..eb2561f593 100644 --- a/target/ppc/spr_common.h +++ b/target/ppc/spr_common.h @@ -85,6 +85,7 @@ void spr_write_generic32(DisasContext *ctx, int sprn, int= gprn); void spr_core_write_generic(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn); void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn); +void spr_write_MMCRA(DisasContext *ctx, int sprn, int gprn); void spr_write_PMC(DisasContext *ctx, int sprn, int gprn); void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn); void spr_read_xer(DisasContext *ctx, int gprn, int sprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 93ffec787c..26bcc720b3 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -194,6 +194,7 @@ struct DisasContext { bool mmcr0_pmcjce; bool pmc_other; bool pmu_insn_cnt; + bool bhrb_enable; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; uint32_t flags; @@ -7258,6 +7259,7 @@ static void ppc_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->mmcr0_pmcjce =3D (hflags >> HFLAGS_PMCJCE) & 1; ctx->pmc_other =3D (hflags >> HFLAGS_PMC_OTHER) & 1; ctx->pmu_insn_cnt =3D (hflags >> HFLAGS_INSN_CNT) & 1; + ctx->bhrb_enable =3D (hflags >> HFLAGS_BHRB_ENABLE) & 1; =20 ctx->singlestep_enabled =3D 0; if ((hflags >> HFLAGS_SE) & 1) { --=20 2.31.8 From nobody Wed May 15 21:16:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.vnet.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1711653994; cv=none; d=zohomail.com; s=zohoarc; b=N89DeA1olh3rap0OxmtRQMU3w2Myu4GqgPbiis96eeVPln0RMODKg+v/rTpaT17f1THt73TFYas3GKlIgboCggd+zRxK4Ck3E56ACrd8yKY5N9ScTE1edaVpHZz0q0sDCTDRT35r1yMojePjBxRz6STbcimFDSRRG7GdoNDX6qY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1711653994; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Thu, 28 Mar 2024 19:24:32 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=P6sUhRPi5NyJq7ZGPqNsjaJv9uG5+7x3koE1N+CaZYw=; b=TYMntIdxz10UEloV+iwWn0nYxCPX81wZSu5d0bHKp1wVi3pp+eVqiT2rkagjJYcVqzhX jXc5Pa9J04h8LbZ9eFyuEyGVtvhGZFOjzEc5B1w7b3inc5D4bQLPqgei2W1nm9tjKvfG ZvIKqVpFgq90AaDmaPTtTrRUoXCsQjzlAkRGRsHrncWqi7fgM3tbIR2Jr8KFXNnBV91F EQSKaWGfU5r4WYT55A/TidP7drHJzhOBgP6hn2TJTE1BqTMovaE0Xl9wsSrzXtv0sT3J ZMWnuEKfe24ouNFa8qrPBZS8oNbMXKJry0h6iUr+Eu5vxiA4oZs5x/iFdU3wmyt5o6nU Cw== From: Glenn Miles To: qemu-ppc@nongnu.org Cc: Glenn Miles , qemu-devel@nongnu.org, Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nicholas Piggin , David Gibson , Peter Maydell Subject: [PATCH v4 2/4] target/ppc: Add recording of taken branches to BHRB Date: Thu, 28 Mar 2024 14:23:54 -0500 Message-Id: <20240328192356.2144086-3-milesg@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.8 In-Reply-To: <20240328192356.2144086-1-milesg@linux.vnet.ibm.com> References: <20240328192356.2144086-1-milesg@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: CwMgaMqSonAJF7lPs9xMnjmRzFz-KX1V X-Proofpoint-GUID: xNFU8EghLRN9wvTddVUpyl4OKdsRflza X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-28_17,2024-03-28_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 clxscore=1015 bulkscore=0 adultscore=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=902 impostorscore=0 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2403210000 definitions=main-2403280136 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.156.1; envelope-from=milesg@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1711653995929100002 Content-Type: text/plain; charset="utf-8" This commit continues adding support for the Branch History Rolling Buffer (BHRB) as is provided starting with the P8 processor and continuing with its successors. This commit is limited to the recording and filtering of taken branches. The following changes were made: - Enabled functionality on P10 processors only due to performance impact seen with P8 and P9 where it is not disabled for non problem state branches. - Added a BHRB buffer for storing branch instruction and target addresses for taken branches - Renamed gen_update_cfar to gen_update_branch_history and added a 'target' parameter to hold the branch target address and 'inst_type' parameter to use for filtering - Added TCG code to gen_update_branch_history that stores data to the BHRB and updates the BHRB offset. - Added BHRB resource initialization and reset functions Signed-off-by: Glenn Miles Reviewed-by: Nicholas Piggin --- Changes from v3: - Rebased on latest master branch - Fixed compile errors for non ppc64-softmmu targets - Fixed compile errors from compiling on 32 bit hosts target/ppc/cpu.h | 17 +++++ target/ppc/cpu_init.c | 37 +++++++++- target/ppc/power8-pmu.c | 33 +++++++++ target/ppc/power8-pmu.h | 7 ++ target/ppc/translate.c | 98 ++++++++++++++++++++++++-- target/ppc/translate/branch-impl.c.inc | 2 +- 6 files changed, 186 insertions(+), 8 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 3f6b93ca8f..7a62a82d03 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -550,6 +550,8 @@ FIELD(MSR, LE, MSR_LE, 1) MMCR2_FC4P0 | MMCR2_FC5P0 | MMCR2_FC6P0) =20 #define MMCRA_BHRBRD PPC_BIT(26) /* BHRB Recording Disable */ +#define MMCRA_IFM_MASK PPC_BITMASK(32, 33) /* BHRB Instruction Filtering = */ +#define MMCRA_IFM_SHIFT PPC_BIT_NR(33) =20 #define MMCR1_EVT_SIZE 8 /* extract64() does a right shift before extracting */ @@ -776,6 +778,8 @@ enum { POWERPC_FLAG_SMT =3D 0x00400000, /* Using "LPAR per core" mode (as opposed to per-thread) = */ POWERPC_FLAG_SMT_1LPAR =3D 0x00800000, + /* Has BHRB */ + POWERPC_FLAG_BHRB =3D 0x01000000, }; =20 /* @@ -1217,6 +1221,9 @@ struct pnv_tod_tbst { #define PPC_CPU_OPCODES_LEN 0x40 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20 =20 +#define BHRB_MAX_NUM_ENTRIES_LOG2 (5) +#define BHRB_MAX_NUM_ENTRIES (1 << BHRB_MAX_NUM_ENTRIES_LOG2) + struct CPUArchState { /* Most commonly used resources during translated code execution first= */ target_ulong gpr[32]; /* general purpose registers */ @@ -1313,6 +1320,16 @@ struct CPUArchState { int dcache_line_size; int icache_line_size; =20 +#ifdef TARGET_PPC64 + /* Branch History Rolling Buffer (BHRB) resources */ + target_ulong bhrb_num_entries; + intptr_t bhrb_base; + target_ulong bhrb_filter; + target_ulong bhrb_offset; + target_ulong bhrb_offset_mask; + uint64_t bhrb[BHRB_MAX_NUM_ENTRIES]; +#endif + /* These resources are used during exception processing */ /* CPU model definition */ target_ulong msr_mask; diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 4e65335669..907cdde5a8 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6142,6 +6142,28 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) pcc->l1_icache_size =3D 0x8000; } =20 +static void bhrb_init_state(CPUPPCState *env, target_long num_entries_log2) +{ + if (env->flags & POWERPC_FLAG_BHRB) { + if (num_entries_log2 > BHRB_MAX_NUM_ENTRIES_LOG2) { + num_entries_log2 =3D BHRB_MAX_NUM_ENTRIES_LOG2; + } + env->bhrb_num_entries =3D 1 << num_entries_log2; + env->bhrb_base =3D (intptr_t)&env->bhrb[0]; + env->bhrb_offset_mask =3D (env->bhrb_num_entries * sizeof(uint64_t= )) - 1; + } +} + +static void bhrb_reset_state(CPUPPCState *env) +{ + if (env->flags & POWERPC_FLAG_BHRB) { + env->bhrb_offset =3D 0; + env->bhrb_filter =3D 0; + memset(env->bhrb, 0, sizeof(env->bhrb)); + } +} + +#define POWER8_BHRB_ENTRIES_LOG2 5 static void init_proc_POWER8(CPUPPCState *env) { /* Common Registers */ @@ -6183,6 +6205,8 @@ static void init_proc_POWER8(CPUPPCState *env) env->dcache_line_size =3D 128; env->icache_line_size =3D 128; =20 + bhrb_init_state(env, POWER8_BHRB_ENTRIES_LOG2); + /* Allocate hardware IRQ controller */ init_excp_POWER8(env); ppcPOWER7_irq_init(env_archcpu(env)); @@ -6307,6 +6331,7 @@ static struct ppc_radix_page_info POWER9_radix_page_i= nfo =3D { }; #endif /* CONFIG_USER_ONLY */ =20 +#define POWER9_BHRB_ENTRIES_LOG2 5 static void init_proc_POWER9(CPUPPCState *env) { /* Common Registers */ @@ -6357,6 +6382,8 @@ static void init_proc_POWER9(CPUPPCState *env) env->dcache_line_size =3D 128; env->icache_line_size =3D 128; =20 + bhrb_init_state(env, POWER9_BHRB_ENTRIES_LOG2); + /* Allocate hardware IRQ controller */ init_excp_POWER9(env); ppcPOWER9_irq_init(env_archcpu(env)); @@ -6497,6 +6524,7 @@ static struct ppc_radix_page_info POWER10_radix_page_= info =3D { }; #endif /* !CONFIG_USER_ONLY */ =20 +#define POWER10_BHRB_ENTRIES_LOG2 5 static void init_proc_POWER10(CPUPPCState *env) { /* Common Registers */ @@ -6546,6 +6574,8 @@ static void init_proc_POWER10(CPUPPCState *env) env->dcache_line_size =3D 128; env->icache_line_size =3D 128; =20 + bhrb_init_state(env, POWER10_BHRB_ENTRIES_LOG2); + /* Allocate hardware IRQ controller */ init_excp_POWER10(env); ppcPOWER9_irq_init(env_archcpu(env)); @@ -6650,7 +6680,8 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) pcc->flags =3D POWERPC_FLAG_VRE | POWERPC_FLAG_SE | POWERPC_FLAG_BE | POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | - POWERPC_FLAG_VSX | POWERPC_FLAG_SCV; + POWERPC_FLAG_VSX | POWERPC_FLAG_SCV | + POWERPC_FLAG_BHRB; pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; } @@ -7220,6 +7251,10 @@ static void ppc_cpu_reset_hold(Object *obj) } env->spr[i] =3D spr->default_value; } + +#if defined(TARGET_PPC64) + bhrb_reset_state(env); +#endif } =20 #ifndef CONFIG_USER_ONLY diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 6f5d4e1256..db9ee8e96b 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -82,6 +82,37 @@ static void pmu_update_summaries(CPUPPCState *env) env->pmc_cyc_cnt =3D cyc_cnt; } =20 +static void hreg_bhrb_filter_update(CPUPPCState *env) +{ + target_long ifm; + + if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE)) { + /* disable recording to BHRB */ + env->bhrb_filter =3D BHRB_TYPE_NORECORD; + return; + } + + ifm =3D (env->spr[SPR_POWER_MMCRA] & MMCRA_IFM_MASK) >> MMCRA_IFM_SHIF= T; + switch (ifm) { + case 0: + /* record all branches */ + env->bhrb_filter =3D -1; + break; + case 1: + /* only record calls (LK =3D 1) */ + env->bhrb_filter =3D BHRB_TYPE_CALL; + break; + case 2: + /* only record indirect branches */ + env->bhrb_filter =3D BHRB_TYPE_INDIRECT; + break; + case 3: + /* only record conditional branches */ + env->bhrb_filter =3D BHRB_TYPE_COND; + break; + } +} + void pmu_mmcr01a_updated(CPUPPCState *env) { PowerPCCPU *cpu =3D env_archcpu(env); @@ -95,6 +126,8 @@ void pmu_mmcr01a_updated(CPUPPCState *env) ppc_set_irq(cpu, PPC_INTERRUPT_PERFM, 0); } =20 + hreg_bhrb_filter_update(env); + /* * Should this update overflow timers (if mmcr0 is updated) so they * get set in cpu_post_load? diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h index 87fa8c9334..3f79cfc45b 100644 --- a/target/ppc/power8-pmu.h +++ b/target/ppc/power8-pmu.h @@ -13,6 +13,13 @@ #ifndef POWER8_PMU_H #define POWER8_PMU_H =20 +#define BHRB_TYPE_NORECORD 0x00 +#define BHRB_TYPE_CALL 0x01 +#define BHRB_TYPE_INDIRECT 0x02 +#define BHRB_TYPE_COND 0x04 +#define BHRB_TYPE_OTHER 0x08 +#define BHRB_TYPE_XL_FORM 0x10 + #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) =20 #define PMC_COUNTER_NEGATIVE_VAL 0x80000000UL diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 26bcc720b3..5de82abf7d 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -181,6 +181,7 @@ struct DisasContext { #if defined(TARGET_PPC64) bool sf_mode; bool has_cfar; + bool has_bhrb; #endif bool fpu_enabled; bool altivec_enabled; @@ -4072,14 +4073,86 @@ static void gen_rvwinkle(DisasContext *ctx) gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); #endif /* defined(CONFIG_USER_ONLY) */ } + +static inline TCGv gen_write_bhrb(TCGv_ptr base, TCGv offset, TCGv mask, + TCGv value) +{ + TCGv_ptr tmp =3D tcg_temp_new_ptr(); + + /* add base and offset to get address of bhrb entry */ + tcg_gen_add_ptr(tmp, base, (TCGv_ptr)offset); + + /* store value into bhrb at bhrb_offset */ + tcg_gen_st_i64(value, tmp, 0); + + /* add 8 to current bhrb_offset */ + tcg_gen_addi_tl(offset, offset, 8); + + /* apply offset mask */ + tcg_gen_and_tl(offset, offset, mask); + + return offset; +} #endif /* #if defined(TARGET_PPC64) */ =20 -static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) +static inline void gen_update_branch_history(DisasContext *ctx, + target_ulong nip, + TCGv target, + target_long inst_type) { #if defined(TARGET_PPC64) + TCGv_ptr base; + TCGv tmp; + TCGv offset; + TCGv mask; + TCGLabel *no_update; + if (ctx->has_cfar) { tcg_gen_movi_tl(cpu_cfar, nip); } + + if (!ctx->has_bhrb || + !ctx->bhrb_enable || + inst_type =3D=3D BHRB_TYPE_NORECORD) { + return; + } + + tmp =3D tcg_temp_new(); + no_update =3D gen_new_label(); + + /* check for bhrb filtering */ + tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPUPPCState, bhrb_filter)); + tcg_gen_andi_tl(tmp, tmp, inst_type); + tcg_gen_brcondi_tl(TCG_COND_EQ, tmp, 0, no_update); + + base =3D tcg_temp_new_ptr(); + offset =3D tcg_temp_new(); + mask =3D tcg_temp_new(); + + /* load bhrb base address */ + tcg_gen_ld_ptr(base, tcg_env, offsetof(CPUPPCState, bhrb_base)); + + /* load current bhrb_offset */ + tcg_gen_ld_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset)); + + /* load a BHRB offset mask */ + tcg_gen_ld_tl(mask, tcg_env, offsetof(CPUPPCState, bhrb_offset_mask)); + + offset =3D gen_write_bhrb(base, offset, mask, tcg_constant_i64(nip)); + + /* Also record the target address for XL-Form branches */ + if (inst_type & BHRB_TYPE_XL_FORM) { + + /* Set the 'T' bit for target entries */ + tcg_gen_ori_tl(tmp, target, 0x2); + + offset =3D gen_write_bhrb(base, offset, mask, tmp); + } + + /* save updated bhrb_offset for next time */ + tcg_gen_st_tl(offset, tcg_env, offsetof(CPUPPCState, bhrb_offset)); + + gen_set_label(no_update); #endif } =20 @@ -4209,8 +4282,10 @@ static void gen_b(DisasContext *ctx) } if (LK(ctx->opcode)) { gen_setlr(ctx, ctx->base.pc_next); + gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_CALL); + } else { + gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_OTHER); } - gen_update_cfar(ctx, ctx->cia); gen_goto_tb(ctx, 0, target); ctx->base.is_jmp =3D DISAS_NORETURN; } @@ -4225,6 +4300,7 @@ static void gen_bcond(DisasContext *ctx, int type) uint32_t bo =3D BO(ctx->opcode); TCGLabel *l1; TCGv target; + target_long bhrb_type =3D BHRB_TYPE_OTHER; =20 if (type =3D=3D BCOND_LR || type =3D=3D BCOND_CTR || type =3D=3D BCOND= _TAR) { target =3D tcg_temp_new(); @@ -4235,11 +4311,16 @@ static void gen_bcond(DisasContext *ctx, int type) } else { tcg_gen_mov_tl(target, cpu_lr); } + if (!LK(ctx->opcode)) { + bhrb_type |=3D BHRB_TYPE_INDIRECT; + } + bhrb_type |=3D BHRB_TYPE_XL_FORM; } else { target =3D NULL; } if (LK(ctx->opcode)) { gen_setlr(ctx, ctx->base.pc_next); + bhrb_type |=3D BHRB_TYPE_CALL; } l1 =3D gen_new_label(); if ((bo & 0x4) =3D=3D 0) { @@ -4290,6 +4371,7 @@ static void gen_bcond(DisasContext *ctx, int type) tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); } } + bhrb_type |=3D BHRB_TYPE_COND; } if ((bo & 0x10) =3D=3D 0) { /* Test CR */ @@ -4304,8 +4386,11 @@ static void gen_bcond(DisasContext *ctx, int type) tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); } + bhrb_type |=3D BHRB_TYPE_COND; } - gen_update_cfar(ctx, ctx->cia); + + gen_update_branch_history(ctx, ctx->cia, target, bhrb_type); + if (type =3D=3D BCOND_IM) { target_ulong li =3D (target_long)((int16_t)(BD(ctx->opcode))); if (likely(AA(ctx->opcode) =3D=3D 0)) { @@ -4421,7 +4506,7 @@ static void gen_rfi(DisasContext *ctx) /* Restore CPU state */ CHK_SV(ctx); translator_io_start(&ctx->base); - gen_update_cfar(ctx, ctx->cia); + gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); gen_helper_rfi(tcg_env); ctx->base.is_jmp =3D DISAS_EXIT; #endif @@ -4436,7 +4521,7 @@ static void gen_rfid(DisasContext *ctx) /* Restore CPU state */ CHK_SV(ctx); translator_io_start(&ctx->base); - gen_update_cfar(ctx, ctx->cia); + gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); gen_helper_rfid(tcg_env); ctx->base.is_jmp =3D DISAS_EXIT; #endif @@ -4451,7 +4536,7 @@ static void gen_rfscv(DisasContext *ctx) /* Restore CPU state */ CHK_SV(ctx); translator_io_start(&ctx->base); - gen_update_cfar(ctx, ctx->cia); + gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); gen_helper_rfscv(tcg_env); ctx->base.is_jmp =3D DISAS_EXIT; #endif @@ -7243,6 +7328,7 @@ static void ppc_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) #if defined(TARGET_PPC64) ctx->sf_mode =3D (hflags >> HFLAGS_64) & 1; ctx->has_cfar =3D !!(env->flags & POWERPC_FLAG_CFAR); + ctx->has_bhrb =3D !!(env->flags & POWERPC_FLAG_BHRB); #endif ctx->lazy_tlb_flush =3D env->mmu_model =3D=3D POWERPC_MMU_32B || env->mmu_model & POWERPC_MMU_64; diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/= branch-impl.c.inc index fb0fcf30cc..9ade0c659a 100644 --- a/target/ppc/translate/branch-impl.c.inc +++ b/target/ppc/translate/branch-impl.c.inc @@ -17,7 +17,7 @@ static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) REQUIRE_INSNS_FLAGS2(ctx, ISA207S); =20 translator_io_start(&ctx->base); - gen_update_cfar(ctx, ctx->cia); + gen_update_branch_history(ctx, ctx->cia, NULL, BHRB_TYPE_NORECORD); gen_helper_rfebb(tcg_env, cpu_gpr[arg->s]); =20 ctx->base.is_jmp =3D DISAS_CHAIN; --=20 2.31.8 From nobody Wed May 15 21:16:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.vnet.ibm.com ARC-Seal: i=1; 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Thu, 28 Mar 2024 19:24:38 GMT Received: from smtpav04.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2527558045; Thu, 28 Mar 2024 19:24:36 +0000 (GMT) Received: from smtpav04.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9A04A58056; Thu, 28 Mar 2024 19:24:35 +0000 (GMT) Received: from mamboa4.aus.stglabs.ibm.com (unknown [9.3.84.87]) by smtpav04.wdc07v.mail.ibm.com (Postfix) with ESMTP; Thu, 28 Mar 2024 19:24:35 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=RIb9jPTRKPhhYur4GjRbwz1VZFP+CXDe02Qi3AUij3Q=; b=L6MurnF+3EACV47gyZLfYeodw0SNVwbd2cQI7RTV45ez3wmOCee9GIaSv4E1ohMdkrEh sF68vyia0BsdW5XBYeX2iHS3w24kc2h94/MEz2Js2ig44sbLsoBVM7PHES/By1MmB7jy LwQzxrXc2K1C2t1oO0hPso+db76AOn+jbLpjqrYVuERbPCjnyL4Lo1EElf/RWS29wQs7 7BqqYGdGwRcUnA2Oyjr7i5uYAbpmUuDi4eya+Wy/9VusxO1GnSUq9jviYnAR98mqd8VT W4D8ElFTAM7QXv9yBoM3oZWmB6H4XiKrvaKDgIZAjKPI4H9lkeBle/+krp85hKJiB+TD Rw== From: Glenn Miles To: qemu-ppc@nongnu.org Cc: Glenn Miles , qemu-devel@nongnu.org, Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nicholas Piggin , David Gibson , Peter Maydell Subject: [PATCH v4 3/4] target/ppc: Add clrbhrb and mfbhrbe instructions Date: Thu, 28 Mar 2024 14:23:55 -0500 Message-Id: <20240328192356.2144086-4-milesg@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.8 In-Reply-To: <20240328192356.2144086-1-milesg@linux.vnet.ibm.com> References: <20240328192356.2144086-1-milesg@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: tK8WMj3Y6vRbKcYpyYmgP3yp2NXMA6oh X-Proofpoint-GUID: -OkRbrWPz45uD4ZOSJDjJezZyniRhdO6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-28_17,2024-03-28_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 impostorscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 bulkscore=0 mlxscore=0 mlxlogscore=673 adultscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2403210000 definitions=main-2403280136 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.158.5; envelope-from=milesg@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1711653967824100002 Content-Type: text/plain; charset="utf-8" Add support for the clrbhrb and mfbhrbe instructions. Since neither instruction is believed to be critical to performance, both instructions were implemented using helper functions. Access to both instructions is controlled by bits in the HFSCR (for privileged state) and MMCR0 (for problem state). A new function, helper_mmcr0_facility_check, was added for checking MMCR0[BHRBA] and raising a facility_unavailable exception if required. NOTE: For P8 and P9, due to a performance issue, branch history will not be kept, but the instructions will be allowed to execute as normal with the exception that the mfbhrbe instruction will always return a zero value. Signed-off-by: Glenn Miles Reviewed-by: Nicholas Piggin --- Changes from v3: - Rebased on latest master branch - Fixed compile errors for non ppc64-softmmu targets target/ppc/cpu.h | 2 ++ target/ppc/helper.h | 7 ++++ target/ppc/insn32.decode | 8 +++++ target/ppc/misc_helper.c | 50 ++++++++++++++++++++++++++++ target/ppc/translate.c | 2 ++ target/ppc/translate/bhrb-impl.c.inc | 43 ++++++++++++++++++++++++ 6 files changed, 112 insertions(+) create mode 100644 target/ppc/translate/bhrb-impl.c.inc diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 7a62a82d03..76e896fdda 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -537,6 +537,7 @@ FIELD(MSR, LE, MSR_LE, 1) #define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */ #define MMCR0_FCP PPC_BIT(34) /* Freeze Counters/BHRB if PR=3D1= */ #define MMCR0_FCPC PPC_BIT(51) /* Condition for FCP bit */ +#define MMCR0_BHRBA_NR PPC_BIT_NR(42) /* BHRB Available */ /* MMCR0 userspace r/w mask */ #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE) /* MMCR2 userspace r/w mask */ @@ -636,6 +637,7 @@ FIELD(MSR, LE, MSR_LE, 1) =20 /* HFSCR bits */ #define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */ +#define HFSCR_BHRB PPC_BIT(59) /* BHRB Instructions */ #define HFSCR_IC_MSGP 0xA =20 #define DBCR0_ICMP (1 << 27) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 3df360efe9..8cdb322ed6 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -820,3 +820,10 @@ DEF_HELPER_4(DSCLIQ, void, env, fprp, fprp, i32) =20 DEF_HELPER_1(tbegin, void, env) DEF_HELPER_FLAGS_1(fixup_thrm, TCG_CALL_NO_RWG, void, env) + +#if !defined(CONFIG_USER_ONLY) +#if defined(TARGET_PPC64) +DEF_HELPER_1(clrbhrb, void, env) +DEF_HELPER_FLAGS_2(mfbhrbe, TCG_CALL_NO_WG, i64, env, i32) +#endif +#endif diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index eada59f59f..a343621cdd 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -998,3 +998,11 @@ MSGSND 011111 ----- ----- ..... 0011001110 - = @X_rb MSGCLRP 011111 ----- ----- ..... 0010101110 - @X_rb MSGSNDP 011111 ----- ----- ..... 0010001110 - @X_rb MSGSYNC 011111 ----- ----- ----- 1101110110 - + +# Branch History Rolling Buffer (BHRB) Instructions + +&XFX_bhrbe rt bhrbe +@XFX_bhrbe ...... rt:5 bhrbe:10 .......... - &XFX_bhrbe + +MFBHRBE 011111 ..... ..... ..... 0100101110 - @XFX_bhrbe +CLRBHRB 011111 ----- ----- ----- 0110101110 - diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 58e808dc96..6f419c9346 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -150,6 +150,17 @@ void helper_msr_facility_check(CPUPPCState *env, uint3= 2_t bit, =20 #if !defined(CONFIG_USER_ONLY) =20 +#ifdef TARGET_PPC64 +static void helper_mmcr0_facility_check(CPUPPCState *env, uint32_t bit, + uint32_t sprn, uint32_t cause) +{ + if (FIELD_EX64(env->msr, MSR, PR) && + !(env->spr[SPR_POWER_MMCR0] & (1ULL << bit))) { + raise_fu_exception(env, bit, sprn, cause, GETPC()); + } +} +#endif + void helper_store_sdr1(CPUPPCState *env, target_ulong val) { if (env->spr[SPR_SDR1] !=3D val) { @@ -363,3 +374,42 @@ void helper_fixup_thrm(CPUPPCState *env) env->spr[i] =3D v; } } + +#if !defined(CONFIG_USER_ONLY) +#if defined(TARGET_PPC64) +void helper_clrbhrb(CPUPPCState *env) +{ + helper_hfscr_facility_check(env, HFSCR_BHRB, "clrbhrb", FSCR_IC_BHRB); + + helper_mmcr0_facility_check(env, MMCR0_BHRBA_NR, 0, FSCR_IC_BHRB); + + if (env->flags & POWERPC_FLAG_BHRB) { + memset(env->bhrb, 0, sizeof(env->bhrb)); + } +} + +uint64_t helper_mfbhrbe(CPUPPCState *env, uint32_t bhrbe) +{ + unsigned int index; + + helper_hfscr_facility_check(env, HFSCR_BHRB, "mfbhrbe", FSCR_IC_BHRB); + + helper_mmcr0_facility_check(env, MMCR0_BHRBA_NR, 0, FSCR_IC_BHRB); + + if (!(env->flags & POWERPC_FLAG_BHRB) || + (bhrbe >=3D env->bhrb_num_entries) || + (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE)) { + return 0; + } + + /* + * Note: bhrb_offset is the byte offset for writing the + * next entry (over the oldest entry), which is why we + * must offset bhrbe by 1 to get to the 0th entry. + */ + index =3D ((env->bhrb_offset / sizeof(uint64_t)) - (bhrbe + 1)) % + env->bhrb_num_entries; + return env->bhrb[index]; +} +#endif +#endif diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5de82abf7d..42446f7d05 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6450,6 +6450,8 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d= , arg_PLS_D *a) =20 #include "translate/storage-ctrl-impl.c.inc" =20 +#include "translate/bhrb-impl.c.inc" + /* Handles lfdp */ static void gen_dform39(DisasContext *ctx) { diff --git a/target/ppc/translate/bhrb-impl.c.inc b/target/ppc/translate/bh= rb-impl.c.inc new file mode 100644 index 0000000000..3a19bc4555 --- /dev/null +++ b/target/ppc/translate/bhrb-impl.c.inc @@ -0,0 +1,43 @@ +/* + * Power ISA Decode For BHRB Instructions + * + * Copyright IBM Corp. 2023 + * + * Authors: + * Glenn Miles + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + +static bool trans_MFBHRBE(DisasContext *ctx, arg_XFX_bhrbe *arg) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + TCGv_i32 bhrbe =3D tcg_constant_i32(arg->bhrbe); + gen_helper_mfbhrbe(cpu_gpr[arg->rt], tcg_env, bhrbe); + return true; +} + +static bool trans_CLRBHRB(DisasContext *ctx, arg_CLRBHRB *arg) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + gen_helper_clrbhrb(tcg_env); + return true; +} + +#else + +static bool trans_MFBHRBE(DisasContext *ctx, arg_XFX_bhrbe *arg) +{ + gen_invalid(ctx); + return true; +} + +static bool trans_CLRBHRB(DisasContext *ctx, arg_CLRBHRB *arg) +{ + gen_invalid(ctx); + return true; +} +#endif --=20 2.31.8 From nobody Wed May 15 21:16:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.vnet.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1711653968; cv=none; d=zohomail.com; s=zohoarc; b=Dp4AMGo84/WbA8a/vPkw5rrOI72gcXWo+sRpJ1MVfX8J9M5hGsVIodVyDIniMU67MYDHvslokGl1WUrFzljA58kVt9MOIS7dLu3mcDHJ0Vfkx2hChc08qD1qGii1NB8Jp0wnh34fCNoplMYvhjYHt5VX2fbQpJw7Fv4XmDcXuck= ARC-Message-Signature: i=1; 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Thu, 28 Mar 2024 19:24:40 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=Ef4PM3TipPS+SQ3Q87k5uq0UbPfTnh5ekJ5DvOAxajs=; b=MmmQyA51aotLPADs8Fp6AtfIDl61VniBQxIAwBekenPDmwthB6gmvaquwhdCbxhbaRpM /tWH2QD+DY+BZhUU536xCThFwq12onODIVqb1A9UW5lwT3aINTFhfo2VinwJJmfcfiYS Ky3KLnHE8Dna6y6OO7rCMTzwVQok++iUIZDIYnLTqbjbRq7x4W8h3BzofTEugKePG/qR 3kVwaQ+gVUnDPXnfFV5cnCbZEkTkVqimD9TRxyFRjovxma6QIBCIgUv4SQMq3ZJvzNSP SNUMCdJ/Eq9YoGOU9hkzNK+lspTZEbrvMBHasR9jSP5Ptv1QoRA1vw/GprLOw4YNwJTe rQ== From: Glenn Miles To: qemu-ppc@nongnu.org Cc: Glenn Miles , qemu-devel@nongnu.org, Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Nicholas Piggin , David Gibson , Peter Maydell Subject: [PATCH v4 4/4] target/ppc: Add migration support for BHRB Date: Thu, 28 Mar 2024 14:23:56 -0500 Message-Id: <20240328192356.2144086-5-milesg@linux.vnet.ibm.com> X-Mailer: git-send-email 2.31.8 In-Reply-To: <20240328192356.2144086-1-milesg@linux.vnet.ibm.com> References: <20240328192356.2144086-1-milesg@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: PSPE5cTU25lEDQVT7lRUN95oMWdLL8vH X-Proofpoint-ORIG-GUID: aBMxUDC4mqcivTj-JKsFCVbuSeYAm4dK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-28_17,2024-03-28_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 malwarescore=0 suspectscore=0 adultscore=0 impostorscore=0 phishscore=0 spamscore=0 mlxlogscore=822 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2403210000 definitions=main-2403280136 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.158.5; envelope-from=milesg@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1711653969873100006 Content-Type: text/plain; charset="utf-8" Adds migration support for Branch History Rolling Buffer (BHRB) internal state. Signed-off-by: Glenn Miles Reviewed-by: Nicholas Piggin --- Changes from v3: - Rebased onto latest master branch target/ppc/machine.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 6b6c31d903..731dd8df35 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -711,6 +711,26 @@ static const VMStateDescription vmstate_reservation = =3D { } }; =20 +#ifdef TARGET_PPC64 +static bool bhrb_needed(void *opaque) +{ + PowerPCCPU *cpu =3D opaque; + return (cpu->env.flags & POWERPC_FLAG_BHRB) !=3D 0; +} + +static const VMStateDescription vmstate_bhrb =3D { + .name =3D "cpu/bhrb", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D bhrb_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL(env.bhrb_offset, PowerPCCPU), + VMSTATE_UINT64_ARRAY(env.bhrb, PowerPCCPU, BHRB_MAX_NUM_ENTRIES), + VMSTATE_END_OF_LIST() + } +}; +#endif + const VMStateDescription vmstate_ppc_cpu =3D { .name =3D "cpu", .version_id =3D 5, @@ -756,6 +776,7 @@ const VMStateDescription vmstate_ppc_cpu =3D { #ifdef TARGET_PPC64 &vmstate_tm, &vmstate_slb, + &vmstate_bhrb, #endif /* TARGET_PPC64 */ &vmstate_tlb6xx, &vmstate_tlbemb, --=20 2.31.8