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Mon, 25 Mar 2024 07:14:27 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF0mCWCepaQf/otmERs1RkCJybbSbsc8J5ZI89tKCvpXxEY37PNvkkGCLBoFTEDgmbsQJUdmQ== X-Received: by 2002:a2e:938e:0:b0:2d4:94eb:e9fe with SMTP id g14-20020a2e938e000000b002d494ebe9femr5750118ljh.21.1711376066931; Mon, 25 Mar 2024 07:14:26 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Gerd Hoffmann , Xiaoyao Li , Cornelia Huck , Thomas Huth , Harsh Prateek Bora , Gavin Shan Subject: [PATCH for-9.1 v5 1/3] hw: Add compat machines for 9.1 Date: Mon, 25 Mar 2024 15:14:20 +0100 Message-ID: <20240325141422.1380087-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240325141422.1380087-1-pbonzini@redhat.com> References: <20240325141422.1380087-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.065, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1711376152486100003 Content-Type: text/plain; charset="utf-8" Add 9.1 machine types for arm/i440fx/m68k/q35/s390x/spapr. Cc: Cornelia Huck Cc: Thomas Huth Cc: Harsh Prateek Bora Cc: Gavin Shan Signed-off-by: Paolo Bonzini Acked-by: Thomas Huth Reviewed-by: Cornelia Huck Reviewed-by: Harsh Prateek Bora Reviewed-by: Zhao Liu --- include/hw/boards.h | 3 +++ include/hw/i386/pc.h | 3 +++ hw/arm/virt.c | 11 +++++++++-- hw/core/machine.c | 3 +++ hw/i386/pc.c | 3 +++ hw/i386/pc_piix.c | 17 ++++++++++++++--- hw/i386/pc_q35.c | 14 ++++++++++++-- hw/m68k/virt.c | 11 +++++++++-- hw/ppc/spapr.c | 17 ++++++++++++++--- hw/s390x/s390-virtio-ccw.c | 14 +++++++++++++- 10 files changed, 83 insertions(+), 13 deletions(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index 8b8f6d5c00d..50e0cf4278e 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -425,6 +425,9 @@ struct MachineState { } \ type_init(machine_initfn##_register_types) =20 +extern GlobalProperty hw_compat_9_0[]; +extern const size_t hw_compat_9_0_len; + extern GlobalProperty hw_compat_8_2[]; extern const size_t hw_compat_8_2_len; =20 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 27a68071d77..349f79df086 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -198,6 +198,9 @@ void pc_system_parse_ovmf_flash(uint8_t *flash_ptr, siz= e_t flash_size); /* sgx.c */ void pc_machine_init_sgx_epc(PCMachineState *pcms); =20 +extern GlobalProperty pc_compat_9_0[]; +extern const size_t pc_compat_9_0_len; + extern GlobalProperty pc_compat_8_2[]; extern const size_t pc_compat_8_2_len; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a9a913aeadb..c9119ef3847 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3223,10 +3223,17 @@ static void machvirt_machine_init(void) } type_init(machvirt_machine_init); =20 -static void virt_machine_9_0_options(MachineClass *mc) +static void virt_machine_9_1_options(MachineClass *mc) { } -DEFINE_VIRT_MACHINE_AS_LATEST(9, 0) +DEFINE_VIRT_MACHINE_AS_LATEST(9, 1) + +static void virt_machine_9_0_options(MachineClass *mc) +{ + virt_machine_9_1_options(mc); + compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len); +} +DEFINE_VIRT_MACHINE(9, 0) =20 static void virt_machine_8_2_options(MachineClass *mc) { diff --git a/hw/core/machine.c b/hw/core/machine.c index 37ede0e7d4f..a92bec23147 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -33,6 +33,9 @@ #include "hw/virtio/virtio-iommu.h" #include "audio/audio.h" =20 +GlobalProperty hw_compat_9_0[] =3D {}; +const size_t hw_compat_9_0_len =3D G_N_ELEMENTS(hw_compat_9_0); + GlobalProperty hw_compat_8_2[] =3D { { "migration", "zero-page-detection", "legacy"}, { TYPE_VIRTIO_IOMMU_PCI, "granule", "4k" }, diff --git a/hw/i386/pc.c b/hw/i386/pc.c index e80f02bef41..461fcaa1b48 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -78,6 +78,9 @@ { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }= ,\ { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, =20 +GlobalProperty pc_compat_9_0[] =3D {}; +const size_t pc_compat_9_0_len =3D G_N_ELEMENTS(pc_compat_9_0); + GlobalProperty pc_compat_8_2[] =3D {}; const size_t pc_compat_8_2_len =3D G_N_ELEMENTS(pc_compat_8_2); =20 diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 18ba0766092..8850c49c66a 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -513,13 +513,26 @@ static void pc_i440fx_machine_options(MachineClass *m) "Use a different south bridge than PI= IX3"); } =20 -static void pc_i440fx_9_0_machine_options(MachineClass *m) +static void pc_i440fx_9_1_machine_options(MachineClass *m) { pc_i440fx_machine_options(m); m->alias =3D "pc"; m->is_default =3D true; } =20 +DEFINE_I440FX_MACHINE(v9_1, "pc-i440fx-9.1", NULL, + pc_i440fx_9_1_machine_options); + +static void pc_i440fx_9_0_machine_options(MachineClass *m) +{ + pc_i440fx_9_1_machine_options(m); + m->alias =3D NULL; + m->is_default =3D false; + + compat_props_add(m->compat_props, hw_compat_9_0, hw_compat_9_0_len); + compat_props_add(m->compat_props, pc_compat_9_0, pc_compat_9_0_len); +} + DEFINE_I440FX_MACHINE(v9_0, "pc-i440fx-9.0", NULL, pc_i440fx_9_0_machine_options); =20 @@ -528,8 +541,6 @@ static void pc_i440fx_8_2_machine_options(MachineClass = *m) PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); =20 pc_i440fx_9_0_machine_options(m); - m->alias =3D NULL; - m->is_default =3D false; =20 compat_props_add(m->compat_props, hw_compat_8_2, hw_compat_8_2_len); compat_props_add(m->compat_props, pc_compat_8_2, pc_compat_8_2_len); diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index c7bc8a2041f..6e1180d4b60 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -365,12 +365,23 @@ static void pc_q35_machine_options(MachineClass *m) pc_q35_compat_defaults, pc_q35_compat_defaults_len); } =20 -static void pc_q35_9_0_machine_options(MachineClass *m) +static void pc_q35_9_1_machine_options(MachineClass *m) { pc_q35_machine_options(m); m->alias =3D "q35"; } =20 +DEFINE_Q35_MACHINE(v9_1, "pc-q35-9.1", NULL, + pc_q35_9_1_machine_options); + +static void pc_q35_9_0_machine_options(MachineClass *m) +{ + pc_q35_9_1_machine_options(m); + m->alias =3D NULL; + compat_props_add(m->compat_props, hw_compat_9_0, hw_compat_9_0_len); + compat_props_add(m->compat_props, pc_compat_9_0, pc_compat_9_0_len); +} + DEFINE_Q35_MACHINE(v9_0, "pc-q35-9.0", NULL, pc_q35_9_0_machine_options); =20 @@ -378,7 +389,6 @@ static void pc_q35_8_2_machine_options(MachineClass *m) { PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); pc_q35_9_0_machine_options(m); - m->alias =3D NULL; m->max_cpus =3D 1024; compat_props_add(m->compat_props, hw_compat_8_2, hw_compat_8_2_len); compat_props_add(m->compat_props, pc_compat_8_2, pc_compat_8_2_len); diff --git a/hw/m68k/virt.c b/hw/m68k/virt.c index b8e5e102e6b..09bc9bdfefb 100644 --- a/hw/m68k/virt.c +++ b/hw/m68k/virt.c @@ -357,10 +357,17 @@ type_init(virt_machine_register_types) } \ type_init(machvirt_machine_##major##_##minor##_init); =20 -static void virt_machine_9_0_options(MachineClass *mc) +static void virt_machine_9_1_options(MachineClass *mc) { } -DEFINE_VIRT_MACHINE(9, 0, true) +DEFINE_VIRT_MACHINE(9, 1, true) + +static void virt_machine_9_0_options(MachineClass *mc) +{ + virt_machine_9_1_options(mc); + compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len); +} +DEFINE_VIRT_MACHINE(9, 0, false) =20 static void virt_machine_8_2_options(MachineClass *mc) { diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index c417f9dd523..ab0cf496d61 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4805,14 +4805,25 @@ static void spapr_machine_latest_class_options(Mach= ineClass *mc) type_init(spapr_machine_register_##suffix) =20 /* - * pseries-9.0 + * pseries-9.1 */ -static void spapr_machine_9_0_class_options(MachineClass *mc) +static void spapr_machine_9_1_class_options(MachineClass *mc) { /* Defaults for the latest behaviour inherited from the base class */ } =20 -DEFINE_SPAPR_MACHINE(9_0, "9.0", true); +DEFINE_SPAPR_MACHINE(9_1, "9.1", true); + +/* + * pseries-9.0 + */ +static void spapr_machine_9_0_class_options(MachineClass *mc) +{ + spapr_machine_9_1_class_options(mc); + compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len); +} + +DEFINE_SPAPR_MACHINE(9_0, "9.0", false); =20 /* * pseries-8.2 diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index b1dcb3857f0..67e8b0b05e8 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -859,14 +859,26 @@ bool css_migration_enabled(void) } = \ type_init(ccw_machine_register_##suffix) =20 +static void ccw_machine_9_1_instance_options(MachineState *machine) +{ +} + +static void ccw_machine_9_1_class_options(MachineClass *mc) +{ +} +DEFINE_CCW_MACHINE(9_0, "9.1", true); + static void ccw_machine_9_0_instance_options(MachineState *machine) { + ccw_machine_9_1_instance_options(machine); } =20 static void ccw_machine_9_0_class_options(MachineClass *mc) { + ccw_machine_9_1_class_options(machine); + compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len); 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Mon, 25 Mar 2024 07:14:29 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE1K2Gy9c3Ze3o23ubwmlygWg1Un6OMU1GF8QMuOlSaADdGdpJXZ6ru6SUO2X4wzbXJanzSYw== X-Received: by 2002:a19:9108:0:b0:515:8550:58c9 with SMTP id t8-20020a199108000000b00515855058c9mr5632558lfd.63.1711376068956; Mon, 25 Mar 2024 07:14:28 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Gerd Hoffmann , Xiaoyao Li Subject: [PATCH for-9.1 v5 2/3] target/i386: add guest-phys-bits cpu property Date: Mon, 25 Mar 2024 15:14:21 +0100 Message-ID: <20240325141422.1380087-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240325141422.1380087-1-pbonzini@redhat.com> References: <20240325141422.1380087-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.065, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1711376230720100001 Content-Type: text/plain; charset="utf-8" From: Gerd Hoffmann Allows to set guest-phys-bits (cpuid leaf 80000008, eax[23:16]) via -cpu $model,guest-phys-bits=3D$nr. Signed-off-by: Gerd Hoffmann Message-ID: <20240318155336.156197-3-kraxel@redhat.com> Signed-off-by: Paolo Bonzini Reviewed-by: Xiaoyao Li Reviewed-by: Zhao Liu --- v4->v5: - move here all non-KVM parts - add compat property and support for special value "-1" (accelerator defines value) target/i386/cpu.h | 1 + hw/i386/pc.c | 4 +++- target/i386/cpu.c | 22 ++++++++++++++++++++++ 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6b057380791..83e47358451 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2026,6 +2026,7 @@ struct ArchCPU { =20 /* Number of physical address bits supported */ uint32_t phys_bits; + uint32_t guest_phys_bits; =20 /* in order to simplify APIC support, we leave this pointer to the user */ diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 461fcaa1b48..9c4b3969cc8 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -78,7 +78,9 @@ { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }= ,\ { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, =20 -GlobalProperty pc_compat_9_0[] =3D {}; +GlobalProperty pc_compat_9_0[] =3D { + { TYPE_X86_CPU, "guest-phys-bits", "0" }, +}; const size_t pc_compat_9_0_len =3D G_N_ELEMENTS(pc_compat_9_0); =20 GlobalProperty pc_compat_8_2[] =3D {}; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 33760a2ee16..eef3d08473e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6570,6 +6570,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { /* 64 bit processor */ *eax |=3D (cpu_x86_virtual_addr_width(env) << 8); + *eax |=3D (cpu->guest_phys_bits << 16); } *ebx =3D env->features[FEAT_8000_0008_EBX]; if (cs->nr_cores * cs->nr_threads > 1) { @@ -7329,6 +7330,14 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) goto out; } =20 + if (cpu->guest_phys_bits =3D=3D -1) { + /* + * If it was not set by the user, or by the accelerator via + * cpu_exec_realizefn, clear. + */ + cpu->guest_phys_bits =3D 0; + } + if (cpu->ucode_rev =3D=3D 0) { /* * The default is the same as KVM's. Note that this check @@ -7379,6 +7388,14 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) if (cpu->phys_bits =3D=3D 0) { cpu->phys_bits =3D TCG_PHYS_ADDR_BITS; } + if (cpu->guest_phys_bits && + (cpu->guest_phys_bits > cpu->phys_bits || + cpu->guest_phys_bits < 32)) { + error_setg(errp, "guest-phys-bits should be between 32 and %u " + " (but is %u)", + cpu->phys_bits, cpu->guest_phys_bits); + return; + } } else { /* For 32 bit systems don't use the user set value, but keep * phys_bits consistent with what we tell the guest. @@ -7387,6 +7404,10 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) error_setg(errp, "phys-bits is not user-configurable in 32 bit= "); return; } + if (cpu->guest_phys_bits !=3D 0) { + error_setg(errp, "guest-phys-bits is not user-configurable in = 32 bit"); + return; + } =20 if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { cpu->phys_bits =3D 36; @@ -7887,6 +7908,7 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), + DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, -1), DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit= , 0), DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), --=20 2.44.0 From nobody Fri May 17 08:25:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 25 Mar 2024 07:14:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG3UFOtJKt83FgFLS3Tys3E7nFkpGNeVHrBg8PhI2qOF+H6pvDdGUn5mi/CqA4p1eEYnsAtmQ== X-Received: by 2002:a17:906:7d51:b0:a45:f352:73b0 with SMTP id l17-20020a1709067d5100b00a45f35273b0mr5240550ejp.65.1711376071947; Mon, 25 Mar 2024 07:14:31 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Gerd Hoffmann , Xiaoyao Li Subject: [PATCH for-9.1 v5 3/3] kvm: add support for guest physical bits Date: Mon, 25 Mar 2024 15:14:22 +0100 Message-ID: <20240325141422.1380087-4-pbonzini@redhat.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240325141422.1380087-1-pbonzini@redhat.com> References: <20240325141422.1380087-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.065, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1711376232818100007 Content-Type: text/plain; charset="utf-8" From: Gerd Hoffmann Query kvm for supported guest physical address bits, in cpuid function 80000008, eax[23:16]. Usually this is identical to host physical address bits. With NPT or EPT being used this might be restricted to 48 (max 4-level paging address space size) even if the host cpu supports more physical address bits. When set pass this to the guest, using cpuid too. Guest firmware can use this to figure how big the usable guest physical address space is, so PCI bar mapping are actually reachable. Signed-off-by: Gerd Hoffmann Reviewed-by: Xiaoyao Li Message-ID: <20240318155336.156197-2-kraxel@redhat.com> Signed-off-by: Paolo Bonzini Reviewed-by: Zhao Liu --- v4->v5: - only call new function if cpu->guest_phys_bits =3D=3D -1 - guard more precisely the upper bound of cpu->guest_phys_bits target/i386/kvm/kvm-cpu.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index 9c791b7b052..e6b7a46743b 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -18,10 +18,32 @@ #include "kvm_i386.h" #include "hw/core/accel-cpu.h" =20 +static void kvm_set_guest_phys_bits(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + uint32_t eax, guest_phys_bits; + + eax =3D kvm_arch_get_supported_cpuid(cs->kvm_state, 0x80000008, 0, R_E= AX); + guest_phys_bits =3D (eax >> 16) & 0xff; + if (!guest_phys_bits) { + return; + } + cpu->guest_phys_bits =3D guest_phys_bits; + if (cpu->guest_phys_bits > cpu->phys_bits) { + cpu->guest_phys_bits =3D cpu->phys_bits; + } + + if (cpu->host_phys_bits && cpu->host_phys_bits_limit && + cpu->guest_phys_bits > cpu->host_phys_bits_limit) { + cpu->guest_phys_bits =3D cpu->host_phys_bits_limit; + } +} + static bool kvm_cpu_realizefn(CPUState *cs, Error **errp) { X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; + bool ret; =20 /* * The realize order is important, since x86_cpu_realize() checks if @@ -50,7 +72,17 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp) MSR_IA32_UCODE_REV); } } - return host_cpu_realizefn(cs, errp); + ret =3D host_cpu_realizefn(cs, errp); + if (!ret) { + return ret; + } + + if ((env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) && + cpu->guest_phys_bits =3D=3D -1) { + kvm_set_guest_phys_bits(cs); + } + + return true; } =20 static bool lmce_supported(void) --=20 2.44.0