From nobody Sun May 12 04:04:21 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1710408200; cv=none; d=zohomail.com; s=zohoarc; b=S80iN8+R5Naypik72iUvRMNpwiVVfvB2yn7qs51+0WyGRsZZqc/i1G4gofXT93nW5A+zKYlZsYhwhecAgRVyuGxgMNVqdluRWi8AS/5RezCLLKN2SOvzZhwKtujsy5eIaYlhLiyRJQNxpW/kZxxtQNmMz1XOmXumYPiWrgYL4WY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1710408200; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8AVRS8kdGDxvhZ7lJ3E08rqjLlrzW7JeEhjy+paRXxQ=; b=TUpumCuk75w2I87R+hslehroAWRndGI8qxvLdNLpqZ4StIuOrUlLNd5RcR3tXyO7QABKXUJxbNUYi26zP0burI/I2MSbegUJOjzfckIm9D/Gvn95TUQ8uaLmu5n8W5eoxGVSomW7wNaBXNoZ69xXUo9YHiERAf+Obs5MPo6fuOw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1710408200610920.7415908268215; Thu, 14 Mar 2024 02:23:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rkhIG-0003ms-L5; Thu, 14 Mar 2024 05:22:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rkhI9-0003kJ-UZ; Thu, 14 Mar 2024 05:22:26 -0400 Received: from out30-118.freemail.mail.aliyun.com ([115.124.30.118]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rkhI6-0007kf-Kv; Thu, 14 Mar 2024 05:22:25 -0400 Received: from localhost.localdomain(mailfrom:eric.huang@linux.alibaba.com fp:SMTPD_---0W2S0TRv_1710408129) by smtp.aliyun-inc.com; Thu, 14 Mar 2024 17:22:10 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1710408132; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=8AVRS8kdGDxvhZ7lJ3E08rqjLlrzW7JeEhjy+paRXxQ=; b=I/RFnLuvEeG8tVAUAYNaqSvhm8G4TmZCK9pl38a4Y05pA7clPOOCl1Te+HwaPJbp2vLvpsgvIUWyqj6HMbhiK1eSlhS9am6fv12wAJBYyZjmSzU7pxmL90OoclGFMX8rlmBhK/LKRVBkzOrCA1PgipJy3X4vp+HCM4SxG+iNT5o= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R481e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046056; MF=eric.huang@linux.alibaba.com; NM=1; PH=DS; RN=11; SR=0; TI=SMTPD_---0W2S0TRv_1710408129; From: Huang Tao To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bin.meng@windriver.com, alistair.francis@wdc.com, palmer@dabbelt.com, Huang Tao , Christoph Muellner , Richard Henderson Subject: [PATCH v4] target/riscv: Implement dynamic establishment of custom decoder Date: Thu, 14 Mar 2024 17:21:58 +0800 Message-ID: <20240314092158.65866-1-eric.huang@linux.alibaba.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.118; envelope-from=eric.huang@linux.alibaba.com; helo=out30-118.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1710408202486100003 Content-Type: text/plain; charset="utf-8" In this patch, we modify the decoder to be a freely composable data structure instead of a hardcoded one. It can be dynamically builded up according to the extensions. This approach has several benefits: 1. Provides support for heterogeneous cpu architectures. As we add decoder = in RISCVCPU, each cpu can have their own decoder, and the decoders can be different due to cpu's features. 2. Improve the decoding efficiency. We run the guard_func to see if the dec= oder can be added to the dynamic_decoder when building up the decoder. Theref= ore, there is no need to run the guard_func when decoding each instruction. I= t can improve the decoding efficiency 3. For vendor or dynamic cpus, it allows them to customize their own decoder functions to improve decoding efficiency, especially when vendor-defined instruction sets increase. Because of dynamic building up, it can skip t= he other decoder guard functions when decoding. 4. Pre patch for allowing adding a vendor decoder before decode_insn32() wi= th minimal overhead for users that don't need this particular vendor decoder. Signed-off-by: Huang Tao Suggested-by: Christoph Muellner Co-authored-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- Changes in v4: - fix typo - rename function - add 'if tcg_enable()' - move function to tcg-cpu.c and declarations to tcg-cpu.h Changes in v3: - use GPtrArray to save decode function poionter list. --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 15 +++++++++++++++ target/riscv/tcg/tcg-cpu.h | 15 +++++++++++++++ target/riscv/translate.c | 31 +++++++++++++++---------------- 5 files changed, 47 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c160b9216b..17070b82a7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1132,6 +1132,7 @@ void riscv_cpu_finalize_features(RISCVCPU *cpu, Error= **errp) error_propagate(errp, local_err); return; } + riscv_tcg_cpu_finalize_dynamic_decoder(cpu); } else if (kvm_enabled()) { riscv_kvm_cpu_finalize_features(cpu, &local_err); if (local_err !=3D NULL) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3b1a02b944..48e67410e1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -457,6 +457,7 @@ struct ArchCPU { uint32_t pmu_avail_ctrs; /* Mapping of events to counters */ GHashTable *pmu_event_ctr_map; + const GPtrArray *decoders; }; =20 /** diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ab6db817db..c9ab92ea2f 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -853,6 +853,21 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Er= ror **errp) } } =20 +void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu) +{ + GPtrArray *dynamic_decoders; + dynamic_decoders =3D g_ptr_array_sized_new(decoder_table_size); + for (size_t i =3D 0; i < decoder_table_size; ++i) { + if (decoder_table[i].guard_func && + decoder_table[i].guard_func(&cpu->cfg)) { + g_ptr_array_add(dynamic_decoders, + (gpointer)decoder_table[i].riscv_cpu_decode_fn= ); + } + } + + cpu->decoders =3D dynamic_decoders; +} + bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) { return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) =3D=3D NU= LL; diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h index f7b32417f8..ce94253fe4 100644 --- a/target/riscv/tcg/tcg-cpu.h +++ b/target/riscv/tcg/tcg-cpu.h @@ -26,4 +26,19 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Er= ror **errp); void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp); bool riscv_cpu_tcg_compatible(RISCVCPU *cpu); =20 +struct DisasContext; +struct RISCVCPUConfig; +typedef struct RISCVDecoder { + bool (*guard_func)(const struct RISCVCPUConfig *); + bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t); +} RISCVDecoder; + +typedef bool (*riscv_cpu_decode_fn)(struct DisasContext *, uint32_t); + +extern const size_t decoder_table_size; + +extern const RISCVDecoder decoder_table[]; + +void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu); + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ea5d52b2ef..bce16d5054 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -37,6 +37,8 @@ #include "exec/helper-info.c.inc" #undef HELPER_H =20 +#include "tcg/tcg-cpu.h" + /* global register indices */ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ @@ -117,6 +119,7 @@ typedef struct DisasContext { bool frm_valid; /* TCG of the current insn_start */ TCGOp *insn_start; + const GPtrArray *decoders; } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -1120,21 +1123,16 @@ static inline int insn_len(uint16_t first_word) return (first_word & 3) =3D=3D 3 ? 4 : 2; } =20 +const RISCVDecoder decoder_table[] =3D { + { always_true_p, decode_insn32 }, + { has_xthead_p, decode_xthead}, + { has_XVentanaCondOps_p, decode_XVentanaCodeOps}, +}; + +const size_t decoder_table_size =3D ARRAY_SIZE(decoder_table); + static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opc= ode) { - /* - * A table with predicate (i.e., guard) functions and decoder functions - * that are tested in-order until a decoder matches onto the opcode. - */ - static const struct { - bool (*guard_func)(const RISCVCPUConfig *); - bool (*decode_func)(DisasContext *, uint32_t); - } decoders[] =3D { - { always_true_p, decode_insn32 }, - { has_xthead_p, decode_xthead }, - { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, - }; - ctx->virt_inst_excp =3D false; ctx->cur_insn_len =3D insn_len(opcode); /* Check for compressed insn */ @@ -1155,9 +1153,9 @@ static void decode_opc(CPURISCVState *env, DisasConte= xt *ctx, uint16_t opcode) ctx->base.pc_next + 2)); ctx->opcode =3D opcode32; =20 - for (size_t i =3D 0; i < ARRAY_SIZE(decoders); ++i) { - if (decoders[i].guard_func(ctx->cfg_ptr) && - decoders[i].decode_func(ctx, opcode32)) { + for (guint i =3D 0; i < ctx->decoders->len; ++i) { + riscv_cpu_decode_fn func =3D g_ptr_array_index(ctx->decoders, = i); + if (func(ctx, opcode32)) { return; } } @@ -1202,6 +1200,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; + ctx->decoders =3D cpu->decoders; } =20 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) --=20 2.41.0