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Tue, 12 Mar 2024 23:10:16 -0700 (PDT) From: Himanshu Chauhan To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v4 1/3] target/riscv: Enable mcontrol6 triggers only when sdtrig is selected Date: Wed, 13 Mar 2024 11:39:29 +0530 Message-Id: <20240313060931.242161-2-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240313060931.242161-1-hchauhan@ventanamicro.com> References: <20240313060931.242161-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=hchauhan@ventanamicro.com; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1710310334814100002 Content-Type: text/plain; charset="utf-8" The mcontrol6 triggers are not defined in debug specification v0.13 These triggers are defined in sdtrig ISA extension. This patch: * Adds ext_sdtrig capability which is used to select mcontrol6 triggers * Keeps the debug property. All triggers that are defined in v0.13 are exposed. Signed-off-by: Himanshu Chauhan --- target/riscv/cpu.c | 4 +- target/riscv/cpu_cfg.h | 1 + target/riscv/csr.c | 2 +- target/riscv/debug.c | 92 +++++++++++++++++++++++++----------------- target/riscv/machine.c | 2 +- 5 files changed, 60 insertions(+), 41 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c160b9216b..2602aae9f5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1008,7 +1008,7 @@ static void riscv_cpu_reset_hold(Object *obj) set_default_nan_mode(1, &env->fp_status); =20 #ifndef CONFIG_USER_ONLY - if (cpu->cfg.debug) { + if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) { riscv_trigger_reset_hold(env); } =20 @@ -1168,7 +1168,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) riscv_cpu_register_gdb_regs_for_features(cs); =20 #ifndef CONFIG_USER_ONLY - if (cpu->cfg.debug) { + if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) { riscv_trigger_realize(&cpu->env); } #endif diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2040b90da0..0c57e1acd4 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -114,6 +114,7 @@ struct RISCVCPUConfig { bool ext_zvfbfwma; bool ext_zvfh; bool ext_zvfhmin; + bool ext_sdtrig; bool ext_smaia; bool ext_ssaia; bool ext_sscofpmf; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 726096444f..26623d3640 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -546,7 +546,7 @@ static RISCVException have_mseccfg(CPURISCVState *env, = int csrno) =20 static RISCVException debug(CPURISCVState *env, int csrno) { - if (riscv_cpu_cfg(env)->debug) { + if (riscv_cpu_cfg(env)->debug || riscv_cpu_cfg(env)->ext_sdtrig) { return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/debug.c b/target/riscv/debug.c index e30d99cc2f..c6a92ba0f7 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -100,13 +100,16 @@ static trigger_action_t get_trigger_action(CPURISCVSt= ate *env, target_ulong tdata1 =3D env->tdata1[trigger_index]; int trigger_type =3D get_trigger_type(env, trigger_index); trigger_action_t action =3D DBG_ACTION_NONE; + const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); =20 switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: action =3D (tdata1 & TYPE2_ACTION) >> 12; break; case TRIGGER_TYPE_AD_MATCH6: - action =3D (tdata1 & TYPE6_ACTION) >> 12; + /* Only sdtrig ISA extension supports type 6 match */ + if (cfg->ext_sdtrig) + action =3D (tdata1 & TYPE6_ACTION) >> 12; break; case TRIGGER_TYPE_INST_CNT: case TRIGGER_TYPE_INT: @@ -727,7 +730,12 @@ void tdata_csr_write(CPURISCVState *env, int tdata_ind= ex, target_ulong val) type2_reg_write(env, env->trigger_cur, tdata_index, val); break; case TRIGGER_TYPE_AD_MATCH6: - type6_reg_write(env, env->trigger_cur, tdata_index, val); + if (riscv_cpu_cfg(env)->ext_sdtrig) { + type6_reg_write(env, env->trigger_cur, tdata_index, val); + } else { + qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", + trigger_type); + } break; case TRIGGER_TYPE_INST_CNT: itrigger_reg_write(env, env->trigger_cur, tdata_index, val); @@ -750,9 +758,15 @@ void tdata_csr_write(CPURISCVState *env, int tdata_ind= ex, target_ulong val) =20 target_ulong tinfo_csr_read(CPURISCVState *env) { - /* assume all triggers support the same types of triggers */ - return BIT(TRIGGER_TYPE_AD_MATCH) | - BIT(TRIGGER_TYPE_AD_MATCH6); + target_ulong ts =3D 0; + + ts =3D BIT(TRIGGER_TYPE_AD_MATCH); + + /* sdtrig ISA extension supports type 6 match */ + if (riscv_cpu_cfg(env)->ext_sdtrig) + ts |=3D BIT(TRIGGER_TYPE_AD_MATCH6); + + return ts; } =20 void riscv_cpu_debug_excp_handler(CPUState *cs) @@ -803,19 +817,21 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) } break; case TRIGGER_TYPE_AD_MATCH6: - ctrl =3D env->tdata1[i]; - pc =3D env->tdata2[i]; - - if ((ctrl & TYPE6_EXEC) && (bp->pc =3D=3D pc)) { - if (env->virt_enabled) { - /* check VU/VS bit against current privilege level= */ - if ((ctrl >> 23) & BIT(env->priv)) { - return true; - } - } else { - /* check U/S/M bit against current privilege level= */ - if ((ctrl >> 3) & BIT(env->priv)) { - return true; + if (cpu->cfg.ext_sdtrig) { + ctrl =3D env->tdata1[i]; + pc =3D env->tdata2[i]; + + if ((ctrl & TYPE6_EXEC) && (bp->pc =3D=3D pc)) { + if (env->virt_enabled) { + /* check VU/VS bit against current privilege l= evel */ + if ((ctrl >> 23) & BIT(env->priv)) { + return true; + } + } else { + /* check U/S/M bit against current privilege l= evel */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } } } } @@ -869,27 +885,29 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, C= PUWatchpoint *wp) } break; case TRIGGER_TYPE_AD_MATCH6: - ctrl =3D env->tdata1[i]; - addr =3D env->tdata2[i]; - flags =3D 0; + if (cpu->cfg.ext_sdtrig) { + ctrl =3D env->tdata1[i]; + addr =3D env->tdata2[i]; + flags =3D 0; =20 - if (ctrl & TYPE6_LOAD) { - flags |=3D BP_MEM_READ; - } - if (ctrl & TYPE6_STORE) { - flags |=3D BP_MEM_WRITE; - } + if (ctrl & TYPE6_LOAD) { + flags |=3D BP_MEM_READ; + } + if (ctrl & TYPE6_STORE) { + flags |=3D BP_MEM_WRITE; + } =20 - if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { - if (env->virt_enabled) { - /* check VU/VS bit against current privilege level */ - if ((ctrl >> 23) & BIT(env->priv)) { - return true; - } - } else { - /* check U/S/M bit against current privilege level */ - if ((ctrl >> 3) & BIT(env->priv)) { - return true; + if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { + if (env->virt_enabled) { + /* check VU/VS bit against current privilege level= */ + if ((ctrl >> 23) & BIT(env->priv)) { + return true; + } + } else { + /* check U/S/M bit against current privilege level= */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } } } } diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 76f2150f78..1cb8656191 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -230,7 +230,7 @@ static bool debug_needed(void *opaque) { RISCVCPU *cpu =3D opaque; =20 - return cpu->cfg.debug; + return (cpu->cfg.debug || cpu->cfg.ext_sdtrig); } =20 static int debug_post_load(void *opaque, int version_id) --=20 2.34.1 From nobody Thu May 9 08:15:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1710310260; cv=none; d=zohomail.com; s=zohoarc; b=HmOZZ8Oqu8wzufTAZPgoKMe4PxHotc0nRI8Dv9/NjZNIgQmACOBpVBPn6Jqk7GeZlHiZNjLateRrU10j0XnS/RrPjkTBAAsXPwU17nf2Iz7WSbLyVUmXlAxSuXDiJ4HkOZRaMTSjn8NbT/SMZ4IyfcrRBYh/+t3dnYGvhSX3ZDk= ARC-Message-Signature: i=1; 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AJvYcCXLtF1/8vYW6GRN3SRis4ZDfYHbwmQaQypkNqFD+3woq14g+05Dz3BNqdapcvyFxsHGtwzsOF5fJeqLqxEX5v22PBT9/r8= X-Gm-Message-State: AOJu0Yy5k7U7sIBMOeQ271Ra2TG1ataWbCfID+FLs/8l4h5FhN2e7gby 2Qqj0Hyv++oMHvjZp0NCZsuNTegKtPBrcWbhTHPttwDweiLA6IyaW+8SEWaZmM8aejADEaveD3M L X-Google-Smtp-Source: AGHT+IGtJFfCuPj4EK5G/SINU6FLz3LBPeObe2Wl+GqYTiLAuH5R8N6maKWj8eWPachbnAdY/PfVRg== X-Received: by 2002:a17:902:c10c:b0:1dc:82bc:c072 with SMTP id 12-20020a170902c10c00b001dc82bcc072mr12684563pli.1.1710310218338; Tue, 12 Mar 2024 23:10:18 -0700 (PDT) From: Himanshu Chauhan To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v4 2/3] target/riscv: Expose sdtrig ISA extension Date: Wed, 13 Mar 2024 11:39:30 +0530 Message-Id: <20240313060931.242161-3-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240313060931.242161-1-hchauhan@ventanamicro.com> References: <20240313060931.242161-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=hchauhan@ventanamicro.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1710310262594100003 Content-Type: text/plain; charset="utf-8" This patch adds "sdtrig" in the ISA string when sdtrig extension is enabled. The sdtrig extension may or may not be implemented in a system. Therefore, = the -cpu rv64,sdtrig=3D option can be used to dynamically turn sdtrig extension on or off. Since, the sdtrig ISA extension is a superset of debug specification, disab= le the debug property when sdtrig is enabled. A warning is printed when this is done. By default, the sdtrig extension is disabled and debug property enabled as = usual. Signed-off-by: Himanshu Chauhan --- target/riscv/cpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2602aae9f5..ab057a0926 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -175,6 +175,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), @@ -1008,6 +1009,12 @@ static void riscv_cpu_reset_hold(Object *obj) set_default_nan_mode(1, &env->fp_status); =20 #ifndef CONFIG_USER_ONLY + if (cpu->cfg.debug && cpu->cfg.ext_sdtrig) { + warn_report("Disabling debug property since sdtrig ISA extension " + "is enabled"); + cpu->cfg.debug =3D 0; + } + if (cpu->cfg.debug || cpu->cfg.ext_sdtrig) { riscv_trigger_reset_hold(env); } @@ -1480,6 +1487,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false), MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), =20 + MULTI_EXT_CFG_BOOL("sdtrig", ext_sdtrig, false), MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), --=20 2.34.1 From nobody Thu May 9 08:15:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1710310333; cv=none; d=zohomail.com; s=zohoarc; b=AI6fAgV+fv49ISYl+R21PX2vHCDSPH2c/Hs2BPe4mrGK22WOUhQKYM6JKmV1lFDLdiHmHFPqo+46uoGMkmGzWdWsHydcRZQ5P9O6kLdt6tFRooRA7oyK90oAmOX9LPRy259oCQeSj4OrVihxIi9cLNXSeKH4rvB4yOQ47TVFCpY= ARC-Message-Signature: i=1; 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AJvYcCU8y9OR1iMKm9XLvWyU7ccQtico410d2TlaljmH07n4VjoDVKSbj2lVZ0hIpqIdMfVGltpzCxQeBdMp9aZn3FwgIfcjJFM= X-Gm-Message-State: AOJu0YyaU/vYXPyjWqMrXKMHcB2LRtc6EqWrDYPwWpIgqK7WMKCQ62IX OnDp4YzB5SjVBp2XciEV3O7QawkjfufJKRDG4Rw+MPpB3mer2Y/G0D0HgsXPlKo= X-Google-Smtp-Source: AGHT+IHip3y4zqqJRj41qLIwWeZ8MuB5IVmlZCLDAvyP/3xR6jazyXhLhFblBobsdr5I3xSOKdialQ== X-Received: by 2002:a17:902:e843:b0:1dd:b883:3398 with SMTP id t3-20020a170902e84300b001ddb8833398mr3826257plg.4.1710310219966; Tue, 12 Mar 2024 23:10:19 -0700 (PDT) From: Himanshu Chauhan To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v4 3/3] target/riscv: Enable sdtrig for Ventana's Veyron CPUs Date: Wed, 13 Mar 2024 11:39:31 +0530 Message-Id: <20240313060931.242161-4-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240313060931.242161-1-hchauhan@ventanamicro.com> References: <20240313060931.242161-1-hchauhan@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=hchauhan@ventanamicro.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1710310334811100001 Content-Type: text/plain; charset="utf-8" Ventana's Veyron CPUs support sdtrig ISA extension. By default, enable the sdtrig extension and disable the debug property for these CPUs. Signed-off-by: Himanshu Chauhan --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ab057a0926..9ddebe468b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -568,7 +568,9 @@ static void rv64_veyron_v1_cpu_init(Object *obj) cpu->cfg.ext_zicbom =3D true; cpu->cfg.cbom_blocksize =3D 64; cpu->cfg.cboz_blocksize =3D 64; + cpu->cfg.debug=3Dfalse; cpu->cfg.ext_zicboz =3D true; + cpu->cfg.ext_sdtrig =3D true; cpu->cfg.ext_smaia =3D true; cpu->cfg.ext_ssaia =3D true; cpu->cfg.ext_sscofpmf =3D true; --=20 2.34.1