[v2] target/riscv: Support mxstatus CSR for thead-c906

[PATCH v2 0/2] target/riscv: Support mxstatus CSR for thead-c906

LIU Zhiwei posted 2 patches 3 months ago

Diff against v1
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Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20240204054228.651-1-zhiwei._5Fliu@linux.alibaba.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/cpu.c         |  9 ++++++
target/riscv/cpu.h         |  9 ++++++
target/riscv/cpu_bits.h    |  6 ++++
target/riscv/cpu_cfg.h     |  4 ++-
target/riscv/cpu_helper.c  | 25 ++++++++-------
target/riscv/meson.build   |  1 +
target/riscv/tcg/tcg-cpu.c | 25 ++++++++++++++-
target/riscv/tcg/tcg-cpu.h |  1 +
target/riscv/xthead_csr.c  | 65 ++++++++++++++++++++++++++++++++++++++
9 files changed, 132 insertions(+), 13 deletions(-)
create mode 100644 target/riscv/xthead_csr.c

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[PATCH v2 0/2] target/riscv: Support mxstatus CSR for thead-c906

Posted by LIU Zhiwei 3 months ago

This patch set fix the regression on kernel pointed by Björn Töpel in
https://www.mail-archive.com/qemu-devel@nongnu.org/msg1018232.html.

We first add a framework for vendor CSRs in patch 1. After that we add
one thead-c906 CSR mxstatus, which is used for mmu extension xtheadmaee.

thead-c906 uses some flags in pte [60-63] bits. It has history reasons that
SVPBMT didn't exist when thead-c906 came to wotrld. We named this feature as
xtheadmaee[1]. this feature is controlled by an custom CSR named mxstatus,
whose maee field encodes whether enable the pte [60-63] bits.

[1]:https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadmaee.adoc

LIU Zhiwei (2):
  target/riscv: Register vendors CSR
  target/riscv: Support xtheadmaee for thead-c906

 target/riscv/cpu.c         |  9 ++++++
 target/riscv/cpu.h         |  9 ++++++
 target/riscv/cpu_bits.h    |  6 ++++
 target/riscv/cpu_cfg.h     |  4 ++-
 target/riscv/cpu_helper.c  | 25 ++++++++-------
 target/riscv/meson.build   |  1 +
 target/riscv/tcg/tcg-cpu.c | 25 ++++++++++++++-
 target/riscv/tcg/tcg-cpu.h |  1 +
 target/riscv/xthead_csr.c  | 65 ++++++++++++++++++++++++++++++++++++++
 9 files changed, 132 insertions(+), 13 deletions(-)
 create mode 100644 target/riscv/xthead_csr.c

-- 
2.25.1