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Sat, 03 Feb 2024 02:11:18 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCVzENxv70mH8N3klnj30nfK9W6gQT4X2HdV3CxrWY5aDfTkY9637cQRkfwZT0pHtpqBQI6xGAQg1OvndYpp4sNV54s5BMvUNizal3U9ViMH+YYwm3X99dWxiQiGTWnthJQ1Ci1LKukx8Un74s/N6mE1Z7lfJz3u0wPpgPpD6L6YQynLox6iDuEJKPuKGM+bBODfqRQ0aZMrC7GUfVx9+lr0jiB7XmL0o2WNxcEZLKlNtqt5F7wLUQErxJScCaFEK2uUKmauJTM+d459EXGn9W3xJ3qrerSFbNHaPrZOvHmdp1XCatnuVcW/ZTbYiOJPOUbvZOoYURwwP99jzf5ey6bVCUm6mGXJD6Vg77jTUncM/L9CvjN7ULl+ZNF98UqMnmC7Jf8Ek1MU+yb/QPqIPUgKaCv1QV3glwyxiCql1614UuTzVbSO+v4t1eKj40h64aQTBclQaa1/P6stj6fR From: Akihiko Odaki Date: Sat, 03 Feb 2024 19:11:08 +0900 Subject: [PATCH v11 1/3] target/riscv: Remove misa_mxl validation MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240203-riscv-v11-1-a23f4848a628@daynix.com> References: <20240203-riscv-v11-0-a23f4848a628@daynix.com> In-Reply-To: <20240203-riscv-v11-0-a23f4848a628@daynix.com> To: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , =?utf-8?q?Alex_Benn=C3=A9e?= , Mikhail Tyutin , Aleksandr Anenkov , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Fabiano Rosas , Andrew Jones Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::632; envelope-from=akihiko.odaki@daynix.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1706955171171100001 It is initialized with a simple assignment and there is little room for error. In fact, the validation is even more complex. Signed-off-by: Akihiko Odaki Acked-by: LIU Zhiwei Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index da437975b429..94dca7e446eb 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -268,7 +268,7 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState = *env, Error **errp) } } =20 -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); CPUClass *cc =3D CPU_CLASS(mcc); @@ -288,11 +288,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu,= Error **errp) default: g_assert_not_reached(); } - - if (env->misa_mxl_max !=3D env->misa_mxl) { - error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); - return; - } } =20 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, @@ -908,7 +903,6 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) { RISCVCPU *cpu =3D RISCV_CPU(cs); - Error *local_err =3D NULL; =20 if (!riscv_cpu_tcg_compatible(cpu)) { g_autofree char *name =3D riscv_cpu_get_name(cpu); @@ -917,14 +911,11 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error= **errp) return false; } =20 - riscv_cpu_validate_misa_mxl(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return false; - } + riscv_cpu_validate_misa_mxl(cpu); =20 #ifndef CONFIG_USER_ONLY CPURISCVState *env =3D &cpu->env; + Error *local_err =3D NULL; =20 CPU(cs)->tcg_cflags |=3D CF_PCREL; =20 --=20 2.43.0 From nobody Fri May 10 02:43:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1706955154; cv=none; d=zohomail.com; s=zohoarc; b=UkYYWhY0PhEFNZgUzKbOc7/uIli/2XJ6GZGZxZKifHuIdjPpu8l3yncDzJwoyTBVxZH2SGDkfq+M1RwH7W1sUOzJGiHa2NI4VyVcpoIFLv7wSwcJhpUlY7w5k1DkbxIaj2MU+MrOc4dgMaH4Ek1Ors4r+XCLG22w7PrK6FD7Tog= ARC-Message-Signature: i=1; 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Sat, 03 Feb 2024 02:11:23 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCU/66o723I4E1PchhOIUJaTnh5s1I0b24syxmEPxLzK5lCZmEtwTdzBqoJxwfFpIQScIm5xgCDLH6iLTv0L0ZXwlU0/J9AEDw719NNtjzIJnznyDdWZQNzxYkMdFFyxuf6VCwyhxSDIyZ7cIISXl4atE1px2of9RJLTCnT7YZVXWuYw3tkPxqIZiBvoGGjq4vsA0P536RcIVpWqi0rcgMA/Dabq1+OBCP3tN8FpmB294DfaDXjsqNCjRKQzSnhndmKc8PQFmG84/z4DP35Yfh3wR9PZoNWdx5CI4XlXrAfH/lioh0Z/C4d6Qj7VK9O8l9deK9iaA+fpxOaQfeV458EnxvhY1G7MMF5HBE3Q+oLyQRGVBo3H++bzbBWcapGDl+e+Y6K/eeHDLrdvJtGuJpjjvhaVL8PYh5E5dK0bDG6KYMDqv5E6l7AkvhKByCLBcjuTfyeDQezzZDnOtfq1 From: Akihiko Odaki Date: Sat, 03 Feb 2024 19:11:09 +0900 Subject: [PATCH v11 2/3] target/riscv: Move misa_mxl_max to class MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240203-riscv-v11-2-a23f4848a628@daynix.com> References: <20240203-riscv-v11-0-a23f4848a628@daynix.com> In-Reply-To: <20240203-riscv-v11-0-a23f4848a628@daynix.com> To: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , =?utf-8?q?Alex_Benn=C3=A9e?= , Mikhail Tyutin , Aleksandr Anenkov , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Fabiano Rosas , Andrew Jones Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::132; envelope-from=akihiko.odaki@daynix.com; helo=mail-il1-x132.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1706955155344100002 misa_mxl_max is common for all instances of a RISC-V CPU class so they are better put into class. Signed-off-by: Akihiko Odaki Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 4 +- hw/riscv/boot.c | 3 +- target/riscv/cpu.c | 160 ++++++++++++++++++++++++-----------------= ---- target/riscv/gdbstub.c | 12 ++-- target/riscv/kvm/kvm-cpu.c | 10 +-- target/riscv/machine.c | 7 +- target/riscv/tcg/tcg-cpu.c | 12 ++-- target/riscv/translate.c | 3 +- 8 files changed, 112 insertions(+), 99 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 51381877273e..5c9577f1be7b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -189,7 +189,6 @@ struct CPUArchState { =20 /* RISCVMXL, but uint32_t for vmstate migration */ uint32_t misa_mxl; /* current mxl */ - uint32_t misa_mxl_max; /* max mxl for this cpu */ uint32_t misa_ext; /* current extensions */ uint32_t misa_ext_mask; /* max ext for this cpu */ uint32_t xl; /* current xlen */ @@ -471,6 +470,7 @@ struct RISCVCPUClass { =20 DeviceRealize parent_realize; ResettablePhases parent_phases; + uint32_t misa_mxl_max; /* max mxl for this cpu */ }; =20 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) @@ -783,7 +783,7 @@ enum riscv_pmu_event_idx { /* used by tcg/tcg-cpu.c*/ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); -void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); +void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext); bool riscv_cpu_is_vendor(Object *cpu_obj); =20 typedef struct RISCVCPUMultiExtConfig { diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 0ffca05189f0..12f9792245a4 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -36,7 +36,8 @@ =20 bool riscv_is_32bit(RISCVHartArrayState *harts) { - return harts->harts[0].env.misa_mxl_max =3D=3D MXL_RV32; + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(&harts->harts[0]); + return mcc->misa_mxl_max =3D=3D MXL_RV32; } =20 /* diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 88e8cc868144..c9d09d175510 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -301,9 +301,8 @@ const char *riscv_cpu_get_trap_name(target_ulong cause,= bool async) } } =20 -void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) +void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext) { - env->misa_mxl_max =3D env->misa_mxl =3D mxl; env->misa_ext_mask =3D env->misa_ext =3D ext; } =20 @@ -416,11 +415,7 @@ static void riscv_any_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; -#if defined(TARGET_RISCV32) - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | = RVU); -#elif defined(TARGET_RISCV64) - riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | = RVU); -#endif + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVU); =20 #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), @@ -441,19 +436,17 @@ static void riscv_max_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - RISCVMXL mlx =3D MXL_RV64; =20 cpu->cfg.mmu =3D true; cpu->cfg.pmp =3D true; =20 -#ifdef TARGET_RISCV32 - mlx =3D MXL_RV32; -#endif - riscv_cpu_set_misa(env, mlx, 0); env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), mlx =3D=3D MXL_RV32 ? - VM_1_10_SV32 : VM_1_10_SV57); +#ifdef TARGET_RISCV32 + set_satp_mode_max_supported(cpu, VM_1_10_SV32); +#else + set_satp_mode_max_supported(cpu, VM_1_10_SV57); +#endif #endif } =20 @@ -466,8 +459,6 @@ static void rv64_base_cpu_init(Object *obj) cpu->cfg.mmu =3D true; cpu->cfg.pmp =3D true; =20 - /* We set this in the realise function */ - riscv_cpu_set_misa(env, MXL_RV64, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -479,8 +470,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - riscv_cpu_set_misa(env, MXL_RV64, - RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | = RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); @@ -498,7 +488,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -515,7 +505,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); + riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_11_0; =20 cpu->cfg.ext_zfa =3D true; @@ -546,7 +536,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); + riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH); env->priv_ver =3D PRIV_VERSION_1_12_0; =20 /* Enable ISA extensions */ @@ -596,8 +586,6 @@ static void rv128_base_cpu_init(Object *obj) cpu->cfg.mmu =3D true; cpu->cfg.pmp =3D true; =20 - /* We set this in the realise function */ - riscv_cpu_set_misa(env, MXL_RV128, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -608,7 +596,7 @@ static void rv128_base_cpu_init(Object *obj) static void rv64i_bare_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; - riscv_cpu_set_misa(env, MXL_RV64, RVI); + riscv_cpu_set_misa_ext(env, RVI); =20 /* Remove the defaults from the parent class */ RISCV_CPU(obj)->cfg.ext_zicntr =3D false; @@ -635,8 +623,6 @@ static void rv32_base_cpu_init(Object *obj) cpu->cfg.mmu =3D true; cpu->cfg.pmp =3D true; =20 - /* We set this in the realise function */ - riscv_cpu_set_misa(env, MXL_RV32, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -648,8 +634,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - riscv_cpu_set_misa(env, MXL_RV32, - RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | = RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); @@ -667,7 +652,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -684,7 +669,7 @@ static void rv32_ibex_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -701,7 +686,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); + riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -921,7 +906,7 @@ static void riscv_cpu_reset_hold(Object *obj) mcc->parent_phases.hold(obj); } #ifndef CONFIG_USER_ONLY - env->misa_mxl =3D env->misa_mxl_max; + env->misa_mxl =3D mcc->misa_mxl_max; env->priv =3D PRV_M; env->mstatus &=3D ~(MSTATUS_MIE | MSTATUS_MPRV); if (env->misa_mxl > MXL_RV32) { @@ -1298,7 +1283,11 @@ static void riscv_cpu_post_init(Object *obj) =20 static void riscv_cpu_init(Object *obj) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(obj); RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + + env->misa_mxl =3D mcc->misa_mxl_max; =20 #ifndef CONFIG_USER_ONLY qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, @@ -2276,7 +2265,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops =3D= { }; #endif =20 -static void riscv_cpu_class_init(ObjectClass *c, void *data) +static void riscv_cpu_common_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); CPUClass *cc =3D CPU_CLASS(c); @@ -2309,6 +2298,13 @@ static void riscv_cpu_class_init(ObjectClass *c, voi= d *data) device_class_set_props(dc, riscv_cpu_properties); } =20 +static void riscv_cpu_class_init(ObjectClass *c, void *data) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); + + mcc->misa_mxl_max =3D (uint32_t)(uintptr_t)data; +} + static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) { @@ -2345,39 +2341,49 @@ char *riscv_isa_string(RISCVCPU *cpu) return isa_str; } =20 -#define DEFINE_CPU(type_name, initfn) \ - { \ - .name =3D type_name, \ - .parent =3D TYPE_RISCV_CPU, \ - .instance_init =3D initfn \ +#define DEFINE_CPU(type_name, misa_mxl_max, initfn) \ + { \ + .name =3D (type_name), \ + .parent =3D TYPE_RISCV_CPU, \ + .instance_init =3D (initfn), \ + .class_init =3D riscv_cpu_class_init, \ + .class_data =3D (void *)(misa_mxl_max) \ } =20 -#define DEFINE_DYNAMIC_CPU(type_name, initfn) \ - { \ - .name =3D type_name, \ - .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ - .instance_init =3D initfn \ +#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \ + { \ + .name =3D (type_name), \ + .parent =3D TYPE_RISCV_DYNAMIC_CPU, \ + .instance_init =3D (initfn), \ + .class_init =3D riscv_cpu_class_init, \ + .class_data =3D (void *)(misa_mxl_max) \ } =20 -#define DEFINE_VENDOR_CPU(type_name, initfn) \ - { \ - .name =3D type_name, \ - .parent =3D TYPE_RISCV_VENDOR_CPU, \ - .instance_init =3D initfn \ +#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \ + { \ + .name =3D (type_name), \ + .parent =3D TYPE_RISCV_VENDOR_CPU, \ + .instance_init =3D (initfn), \ + .class_init =3D riscv_cpu_class_init, \ + .class_data =3D (void *)(misa_mxl_max) \ } =20 -#define DEFINE_BARE_CPU(type_name, initfn) \ - { \ - .name =3D type_name, \ - .parent =3D TYPE_RISCV_BARE_CPU, \ - .instance_init =3D initfn \ +#define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \ + { \ + .name =3D (type_name), \ + .parent =3D TYPE_RISCV_BARE_CPU, \ + .instance_init =3D (initfn), \ + .class_init =3D riscv_cpu_class_init, \ + .class_data =3D (void *)(misa_mxl_max) \ } =20 -#define DEFINE_PROFILE_CPU(type_name, initfn) \ - { \ - .name =3D type_name, \ - .parent =3D TYPE_RISCV_BARE_CPU, \ - .instance_init =3D initfn \ +#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \ + { \ + .name =3D (type_name), \ + .parent =3D TYPE_RISCV_BARE_CPU, \ + .instance_init =3D (initfn), \ + .class_init =3D riscv_cpu_class_init, \ + .class_data =3D (void *)(misa_mxl_max) \ } =20 static const TypeInfo riscv_cpu_type_infos[] =3D { @@ -2390,7 +2396,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .instance_post_init =3D riscv_cpu_post_init, .abstract =3D true, .class_size =3D sizeof(RISCVCPUClass), - .class_init =3D riscv_cpu_class_init, + .class_init =3D riscv_cpu_common_class_init, }, { .name =3D TYPE_RISCV_DYNAMIC_CPU, @@ -2407,25 +2413,27 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .parent =3D TYPE_RISCV_CPU, .abstract =3D true, }, - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), #if defined(TARGET_RISCV32) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_in= it), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV32, riscv_any_cpu_= init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_= init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32, rv32_base_cpu_= init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_= init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_= cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_no= mmu_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_= cpu_init), #elif defined(TARGET_RISCV64) - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init= ), - DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), - DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, rva22u64_profile_cpu_init), - DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, rva22s64_profile_cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV64, riscv_any_cpu_= init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_= init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_= init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_= cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_= cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_= cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c90= 6_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1= _cpu_init), + DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu= _init), + DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu= _init), + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profi= le_cpu_init), + DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profi= le_cpu_init), #endif }; =20 diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 5ab0abda19a9..0ae0c47df13e 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -49,6 +49,7 @@ static const struct TypeSize vec_lanes[] =3D { =20 int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; target_ulong tmp; @@ -61,7 +62,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray = *mem_buf, int n) return 0; } =20 - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { case MXL_RV32: return gdb_get_reg32(mem_buf, tmp); case MXL_RV64: @@ -75,12 +76,13 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArra= y *mem_buf, int n) =20 int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; int length =3D 0; target_ulong tmp; =20 - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { case MXL_RV32: tmp =3D (int32_t)ldl_p(mem_buf); length =3D 4; @@ -214,11 +216,12 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, u= int8_t *mem_buf, int n) =20 static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; GString *s =3D g_string_new(NULL); riscv_csr_predicate_fn predicate; - int bitsize =3D 16 << env->misa_mxl_max; + int bitsize =3D 16 << mcc->misa_mxl_max; int i; =20 #if !defined(CONFIG_USER_ONLY) @@ -310,6 +313,7 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs, i= nt base_reg) =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; if (env->misa_ext & RVD) { @@ -326,7 +330,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) ricsv_gen_dynamic_vector_xml(cs, base_reg= ), "riscv-vector.xml", 0); } - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { case MXL_RV32: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index a7881de7f9eb..422e4f121c63 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1769,14 +1769,14 @@ static void kvm_cpu_accel_register_types(void) } type_init(kvm_cpu_accel_register_types); =20 -static void riscv_host_cpu_init(Object *obj) +static void riscv_host_cpu_class_init(ObjectClass *c, void *data) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); =20 #if defined(TARGET_RISCV32) - env->misa_mxl_max =3D env->misa_mxl =3D MXL_RV32; + mcc->misa_mxl_max =3D MXL_RV32; #elif defined(TARGET_RISCV64) - env->misa_mxl_max =3D env->misa_mxl =3D MXL_RV64; + mcc->misa_mxl_max =3D MXL_RV64; #endif } =20 @@ -1784,7 +1784,7 @@ static const TypeInfo riscv_kvm_cpu_type_infos[] =3D { { .name =3D TYPE_RISCV_CPU_HOST, .parent =3D TYPE_RISCV_CPU, - .instance_init =3D riscv_host_cpu_init, + .class_init =3D riscv_host_cpu_class_init, } }; =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 72fe2374dc2a..81cf22894e0e 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -178,10 +178,9 @@ static const VMStateDescription vmstate_pointermasking= =3D { =20 static bool rv128_needed(void *opaque) { - RISCVCPU *cpu =3D opaque; - CPURISCVState *env =3D &cpu->env; + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(opaque); =20 - return env->misa_mxl_max =3D=3D MXL_RV128; + return mcc->misa_mxl_max =3D=3D MXL_RV128; } =20 static const VMStateDescription vmstate_rv128 =3D { @@ -372,7 +371,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINTTL(env.vext_ver, RISCVCPU), VMSTATE_UINT32(env.misa_mxl, RISCVCPU), VMSTATE_UINT32(env.misa_ext, RISCVCPU), - VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU), + VMSTATE_UNUSED(4), VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU), VMSTATE_UINTTL(env.priv, RISCVCPU), VMSTATE_BOOL(env.virt_enabled, RISCVCPU), diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 94dca7e446eb..067f1493fea7 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -272,10 +272,9 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); CPUClass *cc =3D CPU_CLASS(mcc); - CPURISCVState *env =3D &cpu->env; =20 /* Validate that MISA_MXL is set properly. */ - switch (env->misa_mxl_max) { + switch (mcc->misa_mxl_max) { #ifdef TARGET_RISCV64 case MXL_RV64: case MXL_RV128: @@ -426,6 +425,7 @@ static void riscv_cpu_validate_b(RISCVCPU *cpu) */ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; =20 @@ -592,7 +592,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); - if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max =3D=3D MXL_RV32) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } } @@ -600,7 +600,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { + if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max =3D=3D MXL_RV32) { cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); } if (riscv_has_ext(env, RVD)) { @@ -608,7 +608,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp) } } =20 - if (env->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { + if (mcc->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { error_setg(errp, "Zcf extension is only relevant to RV32"); return; } @@ -1307,7 +1307,7 @@ static void riscv_init_max_cpu_extensions(Object *obj) const RISCVCPUMultiExtConfig *prop; =20 /* Enable RVG, RVJ and RVV that are disabled by default */ - riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV= ); + riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV); =20 for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { isa_ext_update_enabled(cpu, prop->offset, true); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 071fbad7ef43..20dbc737d775 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1168,6 +1168,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPURISCVState *env =3D cpu_env(cs); + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); uint32_t tb_flags =3D ctx->base.tb->flags; =20 @@ -1189,7 +1190,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->cfg_vta_all_1s =3D cpu->cfg.rvv_ta_all_1s; ctx->vstart_eq_zero =3D FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); - ctx->misa_mxl_max =3D env->misa_mxl_max; + ctx->misa_mxl_max =3D mcc->misa_mxl_max; ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl =3D FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs =3D cs; --=20 2.43.0 From nobody Fri May 10 02:43:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1706955154; cv=none; d=zohomail.com; s=zohoarc; b=ln2uKLznVGjePdKCDHmKpapsoQAGjeCjp0eqizWr4dv2K/OJoiO/a8U2TFzE9wIrxCt/B/XSUNytFy/4/H9EIdDjbImNvbrdCHIK+VT4jD+tZz2IvrD1Zlhm98AqvJUdLmJ7r0WZ2JHHITNr/OeF3T0nIfatt8JFwDtxk8ec/LY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706955154; 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AJvYcCUhQsx5HwPyyzYbLf43+RduaXcHaEb+Ud7+X7CDugvD+ZEkgyUBe/ZLhmWjuAT1s84KKPNyBSC4dcZBrQxhDGSxggnKL8e0BVxOcO6QU3Vdftml/VeFeMVJdqU8KSiQBHBrsUuSFTrrre75zxT+Ep/XnhB7ztpBj47I+tlKRxi4UR66tzq9znWQChquhcesCr5qNKyBUEnT/wSFKSglyxiBtkHAHuLurIVu6ZkdPEn9A459vwYOrB1tiyk8fK18pGvCIN+7D76xEU7cUj/4fWHFEsuCEpjr6dfdehCxMcUXsYYJ/ycepzfzZDOXvt/mHEHA5muPHSFcHptJXA01rRDVcDxVMP5tOd27jFU3QEGiId8nh3RWmoQImuV/39tMIfZVPkZ/jB19KilCrxirA6wUcgMjT2myUkJTxVBB/0akc66l3HpkSKvaEa5/Q0kgLiP1TKdpIugv7/WwTY2q From: Akihiko Odaki Date: Sat, 03 Feb 2024 19:11:10 +0900 Subject: [PATCH v11 3/3] target/riscv: Validate misa_mxl_max only once MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240203-riscv-v11-3-a23f4848a628@daynix.com> References: <20240203-riscv-v11-0-a23f4848a628@daynix.com> In-Reply-To: <20240203-riscv-v11-0-a23f4848a628@daynix.com> To: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , =?utf-8?q?Alex_Benn=C3=A9e?= , Mikhail Tyutin , Aleksandr Anenkov , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Fabiano Rosas , Andrew Jones Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Akihiko Odaki X-Mailer: b4 0.12.3 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::c2b; envelope-from=akihiko.odaki@daynix.com; helo=mail-oo1-xc2b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1706955155338100001 misa_mxl_max is now a class member and initialized only once for each class. This also moves the initialization of gdb_core_xml_file which will be referenced before realization in the future. Signed-off-by: Akihiko Odaki Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 21 +++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 23 ----------------------- 2 files changed, 21 insertions(+), 23 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c9d09d175510..12a69efe89c4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1344,6 +1344,26 @@ static const MISAExtInfo misa_ext_info_arr[] =3D { MISA_EXT_INFO(RVB, "x-b", "Bit manipulation (Zba_Zbb_Zbs)") }; =20 +static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc) +{ + CPUClass *cc =3D CPU_CLASS(mcc); + + /* Validate that MISA_MXL is set properly. */ + switch (mcc->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + case MXL_RV128: + cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; + break; +#endif + case MXL_RV32: + cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; + break; + default: + g_assert_not_reached(); + } +} + static int riscv_validate_misa_info_idx(uint32_t bit) { int idx; @@ -2303,6 +2323,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) RISCVCPUClass *mcc =3D RISCV_CPU_CLASS(c); =20 mcc->misa_mxl_max =3D (uint32_t)(uintptr_t)data; + riscv_cpu_validate_misa_mxl(mcc); } =20 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 067f1493fea7..e5a60c2e8b60 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -268,27 +268,6 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState= *env, Error **errp) } } =20 -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu) -{ - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); - CPUClass *cc =3D CPU_CLASS(mcc); - - /* Validate that MISA_MXL is set properly. */ - switch (mcc->misa_mxl_max) { -#ifdef TARGET_RISCV64 - case MXL_RV64: - case MXL_RV128: - cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; - break; -#endif - case MXL_RV32: - cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; - break; - default: - g_assert_not_reached(); - } -} - static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, Error **errp) { @@ -911,8 +890,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error *= *errp) return false; } =20 - riscv_cpu_validate_misa_mxl(cpu); - #ifndef CONFIG_USER_ONLY CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; --=20 2.43.0