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[73.169.12.54]) by smtp.gmail.com with ESMTPSA id q3-20020a92c003000000b00361b6a1e6aasm3152089ild.87.2024.02.01.02.33.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 02:33:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1706783623; x=1707388423; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fFcNQALLp828WUobDdICu7UURWQLSRkGcGCql/AlsZ8=; b=P7dq2QVnG8mNlOJdbdTfdI3UUWuPhbZnMw27ngKLPidsHe33qpOJ6dBOe2kLbA3O2H 2/fOFrWRG6JGfoHSYW4sasHHY2pC424UghC2r713nwhikRnA8ibxsaYGjAN3uGOsNo+w h4s3qIldN7uIfmap5aHPqu5tod95xJvTho2Z2KIX7VZytnAHUrAWV2pUrqE8tlr5RhyP uCsZ7lKm5CXasYdasuERHPnDR0fmctvX6/1NSPS32OHpLoFoxAjLSCVeuAdT2VHxUViD srtQR2OoD8w5+1GPZnPq1Wcsmz78aJEbFmOG1/cYT0M8QcQi/IP3V5C/U8t2GbdKFzop 1CjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706783623; x=1707388423; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fFcNQALLp828WUobDdICu7UURWQLSRkGcGCql/AlsZ8=; b=RMVuOMRZ1HTJU6AkuQDZU2azrimr9FQ5IFu2aLlpCXMoVsRdVLqDqx6+7XE80MCrZ5 U3aJE+upncbu1+hGOqwCG+iexjOQuj6pdb7rWc+/0qhpWYzKOuNwxm5ljfd4rNr68kEA W6c/nddstHoE7UgYWwN3qgh3s3Q2EIMaeaVyNI0+VQbMtCS59s9IbGEvchaN8GZqEamS PCoYjN+ARVb3y2aylpWPjYnCz6l78M2i9KnF7HgP8JKO7IiHASpy9bpjqy0xVancyNiJ HgwSk2rXmIjCaoA8QnP5y14c2Yx4vAFWhmQDQK9LMxS+V2qa1HUKZwTIsN6MlgafEhhp PO9A== X-Gm-Message-State: AOJu0YyV+R1yntZpwDQHW6OW8NjePj4WEcColqJtz6WysNUyaCuYNvee ePssEw75pH0Zme0K8GwXVPg/3Ytiot531yluzX5Z9UaboRM1JCfdEQ8ob+pGC8E= X-Google-Smtp-Source: AGHT+IHbwNqUD3hP0AqE9UAktNEGUrE7p7Fw0jgqVnYZo4ZgjzuQ8jDrwN4VkXWyooPXKk+SUkoKqg== X-Received: by 2002:a92:d64a:0:b0:363:a47b:7b95 with SMTP id x10-20020a92d64a000000b00363a47b7b95mr736543ilp.5.1706783623226; Thu, 01 Feb 2024 02:33:43 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCXTFnJK3VOmWhpyJ3LIjVfKIPEz9eYLrkgkclaxsLzr+Xo5QpmnKYjLbuXQpGiuYViJkmxfPAZZYsYElePHYKylftCqN121+XXzcwZeJ2ojFxV4sVeQtzWe3AAqLBx0FWxn5DqUhMXq/vwlq49y60cLKykyWfHJ7RcAC5ZqXTJiEiEKK4a3eaQuOoe2OuEZXsqUyRJymaDXEcuLfJdpQrG1KRy1pixng5z0T5f4hSZXI3g0f34llbkNtJvsG2tm4qINowAgGY/0Snxrqob30XdLONXBDEQwtX3ilOc6 From: Taylor Simpson To: qemu-devel@nongnu.org Cc: bcain@quicinc.com, quic_mathbern@quicinc.com, sidneym@quicinc.com, quic_mliebel@quicinc.com, richard.henderson@linaro.org, philmd@linaro.org, ale@rev.ng, anjo@rev.ng, ltaylorsimpson@gmail.com Subject: [PATCH v2 1/3] Hexagon (target/hexagon) Analyze reads before writes Date: Thu, 1 Feb 2024 03:33:38 -0700 Message-Id: <20240201103340.119081-2-ltaylorsimpson@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240201103340.119081-1-ltaylorsimpson@gmail.com> References: <20240201103340.119081-1-ltaylorsimpson@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::131; envelope-from=ltaylorsimpson@gmail.com; helo=mail-il1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1706783674228100003 We divide gen_analyze_funcs.py into 3 phases Declare the operands Analyze the register reads Analyze the register writes We also create special versions of ctx_log_*_read for new operands Check that the operand is written before the read This is a precursor to improving the analysis for short-circuiting the packet semantics in a subsequent commit Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain --- target/hexagon/translate.h | 26 +++++++++++- target/hexagon/README | 9 +++-- target/hexagon/gen_analyze_funcs.py | 34 ++++++++++------ target/hexagon/hex_common.py | 63 +++++++++++++++-------------- 4 files changed, 83 insertions(+), 49 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 4dd59c6726..f06d71fc53 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Res= erved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -75,6 +75,8 @@ typedef struct DisasContext { TCGv dczero_addr; } DisasContext; =20 +bool is_gather_store_insn(DisasContext *ctx); + static inline void ctx_log_pred_write(DisasContext *ctx, int pnum) { if (!test_bit(pnum, ctx->pregs_written)) { @@ -89,6 +91,12 @@ static inline void ctx_log_pred_read(DisasContext *ctx, = int pnum) set_bit(pnum, ctx->pregs_read); } =20 +static inline void ctx_log_pred_read_new(DisasContext *ctx, int pnum) +{ + g_assert(test_bit(pnum, ctx->pregs_written)); + set_bit(pnum, ctx->pregs_read); +} + static inline void ctx_log_reg_write(DisasContext *ctx, int rnum, bool is_predicated) { @@ -120,6 +128,12 @@ static inline void ctx_log_reg_read(DisasContext *ctx,= int rnum) set_bit(rnum, ctx->regs_read); } =20 +static inline void ctx_log_reg_read_new(DisasContext *ctx, int rnum) +{ + g_assert(test_bit(rnum, ctx->regs_written)); + set_bit(rnum, ctx->regs_read); +} + static inline void ctx_log_reg_read_pair(DisasContext *ctx, int rnum) { ctx_log_reg_read(ctx, rnum); @@ -171,6 +185,15 @@ static inline void ctx_log_vreg_read(DisasContext *ctx= , int rnum) set_bit(rnum, ctx->vregs_read); } =20 +static inline void ctx_log_vreg_read_new(DisasContext *ctx, int rnum) +{ + g_assert(is_gather_store_insn(ctx) || + test_bit(rnum, ctx->vregs_updated) || + test_bit(rnum, ctx->vregs_select) || + test_bit(rnum, ctx->vregs_updated_tmp)); + set_bit(rnum, ctx->vregs_read); +} + static inline void ctx_log_vreg_read_pair(DisasContext *ctx, int rnum) { ctx_log_vreg_read(ctx, rnum ^ 0); @@ -205,7 +228,6 @@ extern TCGv hex_vstore_addr[VSTORES_MAX]; extern TCGv hex_vstore_size[VSTORES_MAX]; extern TCGv hex_vstore_pending[VSTORES_MAX]; =20 -bool is_gather_store_insn(DisasContext *ctx); void process_store(DisasContext *ctx, int slot_num); =20 FIELD(PROBE_PKT_SCALAR_STORE_S0, MMU_IDX, 0, 2) diff --git a/target/hexagon/README b/target/hexagon/README index 746ebec378..c1d8c8d0ab 100644 --- a/target/hexagon/README +++ b/target/hexagon/README @@ -183,10 +183,11 @@ when the override is present. } =20 We also generate an analyze_ function for each instruction. Currentl= y, -these functions record the writes to registers by calling ctx_log_*. Duri= ng -gen_start_packet, we invoke the analyze_ function for each instructio= n in -the packet, and we mark the implicit writes. After the analysis is perfor= med, -we initialize the result register for each of the predicated assignments. +these functions record the reads and writes to registers by calling ctx_lo= g_*. +During gen_start_packet, we invoke the analyze_ function for each ins= truction in +the packet, and we mark the implicit writes. The analysis determines if t= he packet +semantics can be short-circuited. If not, we initialize the result regist= er for each +of the predicated assignments. =20 In addition to instruction semantics, we use a generator to create the dec= ode tree. This generation is a four step process. diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analy= ze_funcs.py index a9af666cef..890e6a3a95 100755 --- a/target/hexagon/gen_analyze_funcs.py +++ b/target/hexagon/gen_analyze_funcs.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 =20 ## -## Copyright(c) 2022-2023 Qualcomm Innovation Center, Inc. All Rights Res= erved. +## Copyright(c) 2022-2024 Qualcomm Innovation Center, Inc. All Rights Res= erved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -44,15 +44,25 @@ def gen_analyze_func(f, tag, regs, imms): =20 f.write(" Insn *insn G_GNUC_UNUSED =3D ctx->insn;\n") =20 - i =3D 0 - ## Analyze all the registers - for regtype, regid in regs: - reg =3D hex_common.get_register(tag, regtype, regid) + ## Declare all the registers + for regno, register in enumerate(regs): + reg_type, reg_id =3D register + reg =3D hex_common.get_register(tag, reg_type, reg_id) + reg.decl_reg_num(f, regno) + + ## Analyze the register reads + for regno, register in enumerate(regs): + reg_type, reg_id =3D register + reg =3D hex_common.get_register(tag, reg_type, reg_id) + if reg.is_read(): + reg.analyze_read(f, regno) + + ## Analyze the register writes + for regno, register in enumerate(regs): + reg_type, reg_id =3D register + reg =3D hex_common.get_register(tag, reg_type, reg_id) if reg.is_written(): - reg.analyze_write(f, tag, i) - else: - reg.analyze_read(f, i) - i +=3D 1 + reg.analyze_write(f, tag, regno) =20 has_generated_helper =3D not hex_common.skip_qemu_helper( tag @@ -89,13 +99,13 @@ def main(): tagimms =3D hex_common.get_tagimms() =20 with open(sys.argv[-1], "w") as f: - f.write("#ifndef HEXAGON_TCG_FUNCS_H\n") - f.write("#define HEXAGON_TCG_FUNCS_H\n\n") + f.write("#ifndef HEXAGON_ANALYZE_FUNCS_C_INC\n") + f.write("#define HEXAGON_ANALYZE_FUNCS_C_INC\n\n") =20 for tag in hex_common.tags: gen_analyze_func(f, tag, tagregs[tag], tagimms[tag]) =20 - f.write("#endif /* HEXAGON_TCG_FUNCS_H */\n") + f.write("#endif /* HEXAGON_ANALYZE_FUNCS_C_INC */\n") =20 =20 if __name__ =3D=3D "__main__": diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 195620c7ec..33801e4bd7 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 =20 ## -## Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Res= erved. +## Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Res= erved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -425,7 +425,6 @@ def log_write(self, f, tag): gen_log_reg_write(ctx, {self.reg_num}, {self.reg_tcg()}); """)) def analyze_write(self, f, tag, regno): - self.decl_reg_num(f, regno) predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ ctx_log_reg_write(ctx, {self.reg_num}, {predicated}); @@ -438,7 +437,6 @@ def decl_tcg(self, f, tag, regno): TCGv {self.reg_tcg()} =3D hex_gpr[{self.reg_num}]; """)) def analyze_read(self, f, regno): - self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ ctx_log_reg_read(ctx, {self.reg_num}); """)) @@ -449,9 +447,8 @@ def decl_tcg(self, f, tag, regno): TCGv {self.reg_tcg()} =3D get_result_gpr(ctx, insn->regno[{reg= no}]); """)) def analyze_read(self, f, regno): - self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ - ctx_log_reg_read(ctx, {self.reg_num}); + ctx_log_reg_read_new(ctx, {self.reg_num}); """)) =20 class GprReadWrite(Register, Single, ReadWrite): @@ -471,8 +468,11 @@ def log_write(self, f, tag): f.write(code_fmt(f"""\ gen_log_reg_write(ctx, {self.reg_num}, {self.reg_tcg()}); """)) + def analyze_read(self, f, regno): + f.write(code_fmt(f"""\ + ctx_log_reg_read(ctx, {self.reg_num}); + """)) def analyze_write(self, f, tag, regno): - self.decl_reg_num(f, regno) predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ ctx_log_reg_write(ctx, {self.reg_num}, {predicated}); @@ -493,7 +493,6 @@ def log_write(self, f, tag): gen_write_ctrl_reg(ctx, {self.reg_num}, {self.reg_tcg()}); """)) def analyze_write(self, f, tag, regno): - self.decl_reg_num(f, regno) predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ ctx_log_reg_write(ctx, {self.reg_num}, {predicated}); @@ -511,7 +510,6 @@ def decl_tcg(self, f, tag, regno): gen_read_ctrl_reg(ctx, {self.reg_num}, {self.reg_tcg()}); """)) def analyze_read(self, f, regno): - self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ ctx_log_reg_read(ctx, {self.reg_num}); """)) @@ -532,7 +530,6 @@ def idef_arg(self, declared): declared.append(self.reg_tcg()) declared.append("CS") def analyze_read(self, f, regno): - self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ ctx_log_reg_read(ctx, {self.reg_num}); """)) @@ -548,7 +545,6 @@ def log_write(self, f, tag): gen_log_pred_write(ctx, {self.reg_num}, {self.reg_tcg()}); """)) def analyze_write(self, f, tag, regno): - self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ ctx_log_pred_write(ctx, {self.reg_num}); """)) @@ -560,7 +556,6 @@ def decl_tcg(self, f, tag, regno): TCGv {self.reg_tcg()} =3D hex_pred[{self.reg_num}]; """)) def analyze_read(self, f, regno): - self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ ctx_log_pred_read(ctx, {self.reg_num}); """)) @@ -571,9 +566,8 @@ def decl_tcg(self, f, tag, regno): TCGv {self.reg_tcg()} =3D get_result_pred(ctx, insn->regno[{re= gno}]); """)) def analyze_read(self, f, regno): - self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ - ctx_log_pred_read(ctx, {self.reg_num}); + ctx_log_pred_read_new(ctx, {self.reg_num}); """)) =20 class PredReadWrite(Register, Single, ReadWrite): @@ -587,8 +581,11 @@ def log_write(self, f, tag): f.write(code_fmt(f"""\ gen_log_pred_write(ctx, {self.reg_num}, {self.reg_tcg()}); """)) + def analyze_read(self, f, regno): + f.write(code_fmt(f"""\ + ctx_log_pred_read(ctx, {self.reg_num}); + """)) def analyze_write(self, f, tag, regno): - self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ ctx_log_pred_write(ctx, {self.reg_num}); """)) @@ -605,7 +602,6 @@ def log_write(self, f, tag): gen_log_reg_write_pair(ctx, {self.reg_num}, {self.reg_tcg()}); """)) def analyze_write(self, f, tag, regno): - self.decl_reg_num(f, regno) predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ ctx_log_reg_write_pair(ctx, {self.reg_num}, {predicated}); @@ -621,7 +617,6 @@ def decl_tcg(self, f, tag, regno): hex_gpr[{self.reg_num} + 1]); """)) def analyze_read(self, f, regno): - self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ ctx_log_reg_read_pair(ctx, {self.reg_num}); """)) @@ -640,8 +635,11 @@ def log_write(self, f, tag): f.write(code_fmt(f"""\ gen_log_reg_write_pair(ctx, {self.reg_num}, {self.reg_tcg()}); """)) + def analyze_read(self, f, regno): + f.write(code_fmt(f"""\ + ctx_log_reg_read_pair(ctx, {self.reg_num}); + """)) def analyze_write(self, f, tag, regno): - self.decl_reg_num(f, regno) predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ ctx_log_reg_write_pair(ctx, {self.reg_num}, {predicated}); @@ -663,7 +661,6 @@ def log_write(self, f, tag): gen_write_ctrl_reg_pair(ctx, {self.reg_num}, {self.reg_tcg()}); """)) def analyze_write(self, f, tag, regno): - self.decl_reg_num(f, regno) predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ ctx_log_reg_write_pair(ctx, {self.reg_num}, {predicated}); @@ -681,7 +678,6 @@ def decl_tcg(self, f, tag, regno): gen_read_ctrl_reg_pair(ctx, {self.reg_num}, {self.reg_tcg()}); """)) def analyze_read(self, f, regno): - self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ ctx_log_reg_read_pair(ctx, {self.reg_num}); """)) @@ -705,7 +701,6 @@ def helper_hvx_desc(self, f): /* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()})= */ """)) def analyze_write(self, f, tag, regno): - self.decl_reg_num(f, regno) newv =3D hvx_newv(tag) predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ @@ -728,7 +723,6 @@ def helper_hvx_desc(self, f): /* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()})= */ """)) def analyze_read(self, f, regno): - self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ ctx_log_vreg_read(ctx, {self.reg_num}); """)) @@ -746,9 +740,8 @@ def helper_hvx_desc(self, f): /* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()})= */ """)) def analyze_read(self, f, regno): - self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ - ctx_log_vreg_read(ctx, {self.reg_num}); + ctx_log_vreg_read_new(ctx, {self.reg_num}); """)) =20 class VRegReadWrite(Register, Hvx, ReadWrite): @@ -772,8 +765,11 @@ def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()})= */ """)) + def analyze_read(self, f, regno): + f.write(code_fmt(f"""\ + ctx_log_vreg_read(ctx, {self.reg_num}); + """)) def analyze_write(self, f, tag, regno): - self.decl_reg_num(f, regno) newv =3D hvx_newv(tag) predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ @@ -803,8 +799,11 @@ def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMVector *)({self.helper_arg_name()})= */ """)) + def analyze_read(self, f, regno): + f.write(code_fmt(f"""\ + ctx_log_vreg_read(ctx, {self.reg_num}); + """)) def analyze_write(self, f, tag, regno): - self.decl_reg_num(f, regno) newv =3D hvx_newv(tag) predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ @@ -830,7 +829,6 @@ def helper_hvx_desc(self, f): /* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg_name= ()}) */ """)) def analyze_write(self, f, tag, regno): - self.decl_reg_num(f, regno) newv =3D hvx_newv(tag) predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ @@ -860,7 +858,6 @@ def helper_hvx_desc(self, f): /* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg_name= ()}) */ """)) def analyze_read(self, f, regno): - self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ ctx_log_vreg_read_pair(ctx, {self.reg_num}); """)) @@ -892,8 +889,11 @@ def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMVectorPair *)({self.helper_arg_name= ()}) */ """)) + def analyze_read(self, f, regno): + f.write(code_fmt(f"""\ + ctx_log_vreg_read_pair(ctx, {self.reg_num}); + """)) def analyze_write(self, f, tag, regno): - self.decl_reg_num(f, regno) newv =3D hvx_newv(tag) predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ @@ -919,7 +919,6 @@ def helper_hvx_desc(self, f): /* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */ """)) def analyze_write(self, f, tag, regno): - self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ ctx_log_qreg_write(ctx, {self.reg_num}); """)) @@ -941,7 +940,6 @@ def helper_hvx_desc(self, f): /* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */ """)) def analyze_read(self, f, regno): - self.decl_reg_num(f, regno) f.write(code_fmt(f"""\ ctx_log_qreg_read(ctx, {self.reg_num}); """)) @@ -967,8 +965,11 @@ def helper_hvx_desc(self, f): f.write(code_fmt(f"""\ /* {self.reg_tcg()} is *(MMQReg *)({self.helper_arg_name()}) */ """)) + def analyze_read(self, f, regno): + f.write(code_fmt(f"""\ + ctx_log_qreg_read(ctx, {self.reg_num}); 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AJvYcCX5+bUQRIXkMBKz0l8WDQ3AL3Eg3ffNZEDQuJnV9KbICWotZoRr8fVZq1N8oi34Mx0t0DZUYiJeQ4tOliqYCQAXp1EgfRJ+HvFsD677W5OPL2wMSQaL1qocgj8kewYAfbUohk2pMFcVLIJAPApamQYPZvGVTQtrn4njcd6L6CtVt6dh4mjiqle9K7PPURydzkrcAUGHsmWiIE4eXHzREPytm/d2PwlUA85owEbJ1Ua83+lvparUiJwX6xk/ihcQRusryMl6EU3NqA8x+4DRVmwN79Ib5mXF1W2ecwZm From: Taylor Simpson To: qemu-devel@nongnu.org Cc: bcain@quicinc.com, quic_mathbern@quicinc.com, sidneym@quicinc.com, quic_mliebel@quicinc.com, richard.henderson@linaro.org, philmd@linaro.org, ale@rev.ng, anjo@rev.ng, ltaylorsimpson@gmail.com Subject: [PATCH v2 2/3] Hexagon (target/hexagon) Enable more short-circuit packets (scalar core) Date: Thu, 1 Feb 2024 03:33:39 -0700 Message-Id: <20240201103340.119081-3-ltaylorsimpson@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240201103340.119081-1-ltaylorsimpson@gmail.com> References: <20240201103340.119081-1-ltaylorsimpson@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::12d; envelope-from=ltaylorsimpson@gmail.com; helo=mail-il1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1706783686227100003 Look for read-after-write instead of overlap of reads and writes Here is an example with overalp but no read-after-write: 0x000200fc: 0x38103876 { R0 =3D add(R0,R1); R6 =3D add(R6,R7) } BEFORE: ---- 00000000000200fc mov_i32 loc2,$0x0 mov_i32 loc2,r0 add_i32 loc3,loc2,r1 mov_i32 loc2,loc3 mov_i32 loc4,$0x0 mov_i32 loc4,r6 add_i32 loc5,loc4,r7 mov_i32 loc4,loc5 mov_i32 r0,loc2 mov_i32 r6,loc4 AFTER: ---- 00000000000200fc add_i32 loc2,r0,r1 mov_i32 r0,loc2 add_i32 loc3,r6,r7 mov_i32 r6,loc3 We can also short-circuit packets with .new values by reading from the real destination instead of the temporary. 0x00020100: 0x78005ff3 { R19 =3D #0xff 0x00020104: 0x2002e204 if (cmp.eq(N19.new,R2)) jump:t PC+8 } BEFORE: ---- 0000000000020100 mov_i32 pc,$0x20108 mov_i32 loc8,$0x0 mov_i32 loc8,$0xff setcond_i32 loc10,loc8,r2,eq mov_i32 loc6,loc10 mov_i32 r19,loc8 add_i32 pkt_cnt,pkt_cnt,$0x2 add_i32 insn_cnt,insn_cnt,$0x4 brcond_i32 loc6,$0x0,eq,$L1 goto_tb $0x0 mov_i32 pc,$0x20108 exit_tb $0x7fbb54000040 set_label $L1 goto_tb $0x1 exit_tb $0x7fbb54000041 set_label $L0 exit_tb $0x7fbb54000043 AFTER: ---- 0000000000020100 mov_i32 pc,$0x20108 mov_i32 r19,$0xff setcond_i32 loc7,r19,r2,eq mov_i32 loc4,loc7 add_i32 pkt_cnt,pkt_cnt,$0x2 add_i32 insn_cnt,insn_cnt,$0x4 brcond_i32 loc4,$0x0,eq,$L1 goto_tb $0x0 mov_i32 pc,$0x20108 exit_tb $0x7f9764000040 set_label $L1 goto_tb $0x1 exit_tb $0x7f9764000041 set_label $L0 exit_tb $0x7f9764000043 Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain --- target/hexagon/translate.h | 13 +++++++------ target/hexagon/translate.c | 21 ++++----------------- 2 files changed, 11 insertions(+), 23 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index f06d71fc53..d5e7f49ad8 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -38,12 +38,10 @@ typedef struct DisasContext { int reg_log[REG_WRITES_MAX]; int reg_log_idx; DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS); - DECLARE_BITMAP(regs_read, TOTAL_PER_THREAD_REGS); DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS); int preg_log[PRED_WRITES_MAX]; int preg_log_idx; DECLARE_BITMAP(pregs_written, NUM_PREGS); - DECLARE_BITMAP(pregs_read, NUM_PREGS); uint8_t store_width[STORES_MAX]; bool s1_store_processed; int future_vregs_idx; @@ -68,6 +66,7 @@ typedef struct DisasContext { bool is_tight_loop; bool short_circuit; bool has_hvx_helper; + bool read_after_write; TCGv new_value[TOTAL_PER_THREAD_REGS]; TCGv new_pred_value[NUM_PREGS]; TCGv pred_written; @@ -88,13 +87,14 @@ static inline void ctx_log_pred_write(DisasContext *ctx= , int pnum) =20 static inline void ctx_log_pred_read(DisasContext *ctx, int pnum) { - set_bit(pnum, ctx->pregs_read); + if (test_bit(pnum, ctx->pregs_written)) { + ctx->read_after_write =3D true; + } } =20 static inline void ctx_log_pred_read_new(DisasContext *ctx, int pnum) { g_assert(test_bit(pnum, ctx->pregs_written)); - set_bit(pnum, ctx->pregs_read); } =20 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum, @@ -125,13 +125,14 @@ static inline void ctx_log_reg_write_pair(DisasContex= t *ctx, int rnum, =20 static inline void ctx_log_reg_read(DisasContext *ctx, int rnum) { - set_bit(rnum, ctx->regs_read); + if (test_bit(rnum, ctx->regs_written)) { + ctx->read_after_write =3D true; + } } =20 static inline void ctx_log_reg_read_new(DisasContext *ctx, int rnum) { g_assert(test_bit(rnum, ctx->regs_written)); - set_bit(rnum, ctx->regs_read); } =20 static inline void ctx_log_reg_read_pair(DisasContext *ctx, int rnum) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 95579ae243..751ca71790 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * Copyright(c) 2019-2024 Qualcomm Innovation Center, Inc. All Rights Res= erved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -394,20 +394,8 @@ static bool need_commit(DisasContext *ctx) } } =20 - /* Check for overlap between register reads and writes */ - for (int i =3D 0; i < ctx->reg_log_idx; i++) { - int rnum =3D ctx->reg_log[i]; - if (test_bit(rnum, ctx->regs_read)) { - return true; - } - } - - /* Check for overlap between predicate reads and writes */ - for (int i =3D 0; i < ctx->preg_log_idx; i++) { - int pnum =3D ctx->preg_log[i]; - if (test_bit(pnum, ctx->pregs_read)) { - return true; - } + if (ctx->read_after_write) { + return true; } =20 /* Check for overlap between HVX reads and writes */ @@ -466,6 +454,7 @@ static void analyze_packet(DisasContext *ctx) { Packet *pkt =3D ctx->pkt; ctx->has_hvx_helper =3D false; + ctx->read_after_write =3D false; for (int i =3D 0; i < pkt->num_insns; i++) { Insn *insn =3D &pkt->insn[i]; ctx->insn =3D insn; @@ -490,11 +479,9 @@ static void gen_start_packet(DisasContext *ctx) ctx->next_PC =3D next_PC; ctx->reg_log_idx =3D 0; bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS); - bitmap_zero(ctx->regs_read, TOTAL_PER_THREAD_REGS); bitmap_zero(ctx->predicated_regs, TOTAL_PER_THREAD_REGS); ctx->preg_log_idx =3D 0; bitmap_zero(ctx->pregs_written, NUM_PREGS); - bitmap_zero(ctx->pregs_read, NUM_PREGS); ctx->future_vregs_idx =3D 0; ctx->tmp_vregs_idx =3D 0; ctx->vreg_log_idx =3D 0; --=20 2.34.1 From nobody Mon May 20 19:51:39 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1706783660; cv=none; d=zohomail.com; s=zohoarc; b=ikCjjmS7xoSDWWUGur95HJfhZD8mJJulSa2V8ysDw4oTMAY5exqKBBXI5EBX0MxfORdwEsGar83ebvj4exZgXwLOmrrMRIQRonrgjq5hOuUr3XH3eywjzngLB0YSD0ITdtbe/5SBUItnq5Roj8xmThxLopxEjrBgfCGzH7BNCuk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1706783660; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qjpON3cPks6DBAlROmi6sm64J8dDNhFlT1cYucf3+UQ=; b=AnyJjO14KIQxJ5OOzqOx5vRCKoVtgIZLBr2isCIzZBqFPkPgjxZCudmPajT4kvPkECvHwZ19LS4t3KMKTZo63emup/G47Vsfh9b3pYNAgJOto72VtLSVBROIKesR3Rpb8Mc/xuNOnxLhFO921Tk5T6uaSXL+BeDQqDz265S/ImM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1706783660636967.7950462055957; Thu, 1 Feb 2024 02:34:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rVUOG-0003io-QJ; Thu, 01 Feb 2024 05:33:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rVUOF-0003iX-RE for qemu-devel@nongnu.org; Thu, 01 Feb 2024 05:33:51 -0500 Received: from mail-il1-x12f.google.com ([2607:f8b0:4864:20::12f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rVUOD-0004qx-Ie for qemu-devel@nongnu.org; Thu, 01 Feb 2024 05:33:51 -0500 Received: by mail-il1-x12f.google.com with SMTP id e9e14a558f8ab-3637b935e80so2470745ab.3 for ; Thu, 01 Feb 2024 02:33:49 -0800 (PST) Received: from taylor-ubuntu.hsd1.co.comcast.net (c-73-169-12-54.hsd1.co.comcast.net. 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Signed-off-by: Taylor Simpson Reviewed-by: Brian Cain --- target/hexagon/translate.h | 88 +++++++++++++++++++++++------ target/hexagon/translate.c | 58 ++----------------- target/hexagon/gen_analyze_funcs.py | 19 ++++--- target/hexagon/hex_common.py | 45 ++++++++++----- 4 files changed, 115 insertions(+), 95 deletions(-) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index d5e7f49ad8..00cc2bcd63 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -50,23 +50,27 @@ typedef struct DisasContext { int tmp_vregs_num[VECTOR_TEMPS_MAX]; int vreg_log[NUM_VREGS]; int vreg_log_idx; + DECLARE_BITMAP(vregs_written, NUM_VREGS); + DECLARE_BITMAP(insn_vregs_written, NUM_VREGS); DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS); DECLARE_BITMAP(vregs_updated, NUM_VREGS); DECLARE_BITMAP(vregs_select, NUM_VREGS); DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS); DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS); - DECLARE_BITMAP(vregs_read, NUM_VREGS); + DECLARE_BITMAP(insn_vregs_read, NUM_VREGS); int qreg_log[NUM_QREGS]; int qreg_log_idx; - DECLARE_BITMAP(qregs_read, NUM_QREGS); + DECLARE_BITMAP(qregs_written, NUM_QREGS); + DECLARE_BITMAP(insn_qregs_written, NUM_QREGS); + DECLARE_BITMAP(insn_qregs_read, NUM_QREGS); bool pre_commit; bool need_commit; TCGCond branch_cond; target_ulong branch_dest; bool is_tight_loop; bool short_circuit; - bool has_hvx_helper; bool read_after_write; + bool has_hvx_overlap; TCGv new_value[TOTAL_PER_THREAD_REGS]; TCGv new_pred_value[NUM_PREGS]; TCGv pred_written; @@ -146,10 +150,25 @@ intptr_t ctx_future_vreg_off(DisasContext *ctx, int r= egnum, intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, int num, bool alloc_ok); =20 +static inline void ctx_start_hvx_insn(DisasContext *ctx) +{ + bitmap_zero(ctx->insn_vregs_written, NUM_VREGS); + bitmap_zero(ctx->insn_vregs_read, NUM_VREGS); + bitmap_zero(ctx->insn_qregs_written, NUM_QREGS); + bitmap_zero(ctx->insn_qregs_read, NUM_QREGS); +} + static inline void ctx_log_vreg_write(DisasContext *ctx, int rnum, VRegWriteType type, - bool is_predicated) + bool is_predicated, bool has_helper) { + if (has_helper) { + set_bit(rnum, ctx->insn_vregs_written); + if (test_bit(rnum, ctx->insn_vregs_read)) { + ctx->has_hvx_overlap =3D true; + } + } + set_bit(rnum, ctx->vregs_written); if (type !=3D EXT_TMP) { if (!test_bit(rnum, ctx->vregs_updated)) { ctx->vreg_log[ctx->vreg_log_idx] =3D rnum; @@ -175,42 +194,77 @@ static inline void ctx_log_vreg_write(DisasContext *c= tx, =20 static inline void ctx_log_vreg_write_pair(DisasContext *ctx, int rnum, VRegWriteType type, - bool is_predicated) + bool is_predicated, bool has_he= lper) { - ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated); - ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated); + ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated, has_helper); + ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated, has_helper); } =20 -static inline void ctx_log_vreg_read(DisasContext *ctx, int rnum) +static inline void ctx_log_vreg_read(DisasContext *ctx, int rnum, + bool has_helper) { - set_bit(rnum, ctx->vregs_read); + if (has_helper) { + set_bit(rnum, ctx->insn_vregs_read); + if (test_bit(rnum, ctx->insn_vregs_written)) { + ctx->has_hvx_overlap =3D true; + } + } + if (test_bit(rnum, ctx->vregs_written)) { + ctx->read_after_write =3D true; + } } =20 -static inline void ctx_log_vreg_read_new(DisasContext *ctx, int rnum) +static inline void ctx_log_vreg_read_new(DisasContext *ctx, int rnum, + bool has_helper) { g_assert(is_gather_store_insn(ctx) || test_bit(rnum, ctx->vregs_updated) || test_bit(rnum, ctx->vregs_select) || test_bit(rnum, ctx->vregs_updated_tmp)); - set_bit(rnum, ctx->vregs_read); + if (has_helper) { + set_bit(rnum, ctx->insn_vregs_read); + if (test_bit(rnum, ctx->insn_vregs_written)) { + ctx->has_hvx_overlap =3D true; + } + } + if (is_gather_store_insn(ctx)) { + ctx->read_after_write =3D true; + } } =20 -static inline void ctx_log_vreg_read_pair(DisasContext *ctx, int rnum) +static inline void ctx_log_vreg_read_pair(DisasContext *ctx, int rnum, + bool has_helper) { - ctx_log_vreg_read(ctx, rnum ^ 0); - ctx_log_vreg_read(ctx, rnum ^ 1); + ctx_log_vreg_read(ctx, rnum ^ 0, has_helper); + ctx_log_vreg_read(ctx, rnum ^ 1, has_helper); } =20 static inline void ctx_log_qreg_write(DisasContext *ctx, - int rnum) + int rnum, bool has_helper) { + if (has_helper) { + set_bit(rnum, ctx->insn_qregs_written); + if (test_bit(rnum, ctx->insn_qregs_read)) { + ctx->has_hvx_overlap =3D true; + } + } + set_bit(rnum, ctx->qregs_written); ctx->qreg_log[ctx->qreg_log_idx] =3D rnum; ctx->qreg_log_idx++; } =20 -static inline void ctx_log_qreg_read(DisasContext *ctx, int qnum) +static inline void ctx_log_qreg_read(DisasContext *ctx, + int qnum, bool has_helper) { - set_bit(qnum, ctx->qregs_read); + if (has_helper) { + set_bit(qnum, ctx->insn_qregs_read); + if (test_bit(qnum, ctx->insn_qregs_written)) { + ctx->has_hvx_overlap =3D true; + } + } + if (test_bit(qnum, ctx->qregs_written)) { + ctx->read_after_write =3D true; + } } =20 extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 751ca71790..ed4b4acd1d 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -378,60 +378,10 @@ static bool need_commit(DisasContext *ctx) return true; } =20 - if (pkt->num_insns =3D=3D 1) { - if (pkt->pkt_has_hvx) { - /* - * The HVX instructions with generated helpers use - * pass-by-reference, so they need the read/write overlap - * check below. - * The HVX instructions with overrides are OK. - */ - if (!ctx->has_hvx_helper) { - return false; - } - } else { - return false; - } - } - - if (ctx->read_after_write) { + if (ctx->read_after_write || ctx->has_hvx_overlap) { return true; } =20 - /* Check for overlap between HVX reads and writes */ - for (int i =3D 0; i < ctx->vreg_log_idx; i++) { - int vnum =3D ctx->vreg_log[i]; - if (test_bit(vnum, ctx->vregs_read)) { - return true; - } - } - if (!bitmap_empty(ctx->vregs_updated_tmp, NUM_VREGS)) { - int i =3D find_first_bit(ctx->vregs_updated_tmp, NUM_VREGS); - while (i < NUM_VREGS) { - if (test_bit(i, ctx->vregs_read)) { - return true; - } - i =3D find_next_bit(ctx->vregs_updated_tmp, NUM_VREGS, i + 1); - } - } - if (!bitmap_empty(ctx->vregs_select, NUM_VREGS)) { - int i =3D find_first_bit(ctx->vregs_select, NUM_VREGS); - while (i < NUM_VREGS) { - if (test_bit(i, ctx->vregs_read)) { - return true; - } - i =3D find_next_bit(ctx->vregs_select, NUM_VREGS, i + 1); - } - } - - /* Check for overlap between HVX predicate reads and writes */ - for (int i =3D 0; i < ctx->qreg_log_idx; i++) { - int qnum =3D ctx->qreg_log[i]; - if (test_bit(qnum, ctx->qregs_read)) { - return true; - } - } - return false; } =20 @@ -453,8 +403,8 @@ static void mark_implicit_pred_reads(DisasContext *ctx) static void analyze_packet(DisasContext *ctx) { Packet *pkt =3D ctx->pkt; - ctx->has_hvx_helper =3D false; ctx->read_after_write =3D false; + ctx->has_hvx_overlap =3D false; for (int i =3D 0; i < pkt->num_insns; i++) { Insn *insn =3D &pkt->insn[i]; ctx->insn =3D insn; @@ -485,13 +435,13 @@ static void gen_start_packet(DisasContext *ctx) ctx->future_vregs_idx =3D 0; ctx->tmp_vregs_idx =3D 0; ctx->vreg_log_idx =3D 0; + bitmap_zero(ctx->vregs_written, NUM_VREGS); bitmap_zero(ctx->vregs_updated_tmp, NUM_VREGS); bitmap_zero(ctx->vregs_updated, NUM_VREGS); bitmap_zero(ctx->vregs_select, NUM_VREGS); bitmap_zero(ctx->predicated_future_vregs, NUM_VREGS); bitmap_zero(ctx->predicated_tmp_vregs, NUM_VREGS); - bitmap_zero(ctx->vregs_read, NUM_VREGS); - bitmap_zero(ctx->qregs_read, NUM_QREGS); + bitmap_zero(ctx->qregs_written, NUM_QREGS); ctx->qreg_log_idx =3D 0; for (i =3D 0; i < STORES_MAX; i++) { ctx->store_width[i] =3D 0; diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analy= ze_funcs.py index 890e6a3a95..81e1d9cfa3 100755 --- a/target/hexagon/gen_analyze_funcs.py +++ b/target/hexagon/gen_analyze_funcs.py @@ -43,6 +43,16 @@ def gen_analyze_func(f, tag, regs, imms): f.write("{\n") =20 f.write(" Insn *insn G_GNUC_UNUSED =3D ctx->insn;\n") + if (hex_common.is_hvx_insn(tag)): + if hex_common.has_hvx_helper(tag): + f.write( + " const bool G_GNUC_UNUSED insn_has_hvx_helper =3D true= ;\n" + ) + f.write(" ctx_start_hvx_insn(ctx);\n") + else: + f.write( + " const bool G_GNUC_UNUSED insn_has_hvx_helper =3D fals= e;\n" + ) =20 ## Declare all the registers for regno, register in enumerate(regs): @@ -64,15 +74,6 @@ def gen_analyze_func(f, tag, regs, imms): if reg.is_written(): reg.analyze_write(f, tag, regno) =20 - has_generated_helper =3D not hex_common.skip_qemu_helper( - tag - ) and not hex_common.is_idef_parser_enabled(tag) - - ## Mark HVX instructions with generated helpers - if (has_generated_helper and - "A_CVI" in hex_common.attribdict[tag]): - f.write(" ctx->has_hvx_helper =3D true;\n") - f.write("}\n\n") =20 =20 diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 33801e4bd7..9e7f613e3c 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -241,6 +241,16 @@ def is_idef_parser_enabled(tag): return tag in idef_parser_enabled =20 =20 +def is_hvx_insn(tag): + return "A_CVI" in attribdict[tag] + + +def has_hvx_helper(tag): + return (is_hvx_insn(tag) and + not skip_qemu_helper(tag) and + not is_idef_parser_enabled(tag)) + + def imm_name(immlett): return f"{immlett}iV" =20 @@ -704,7 +714,8 @@ def analyze_write(self, f, tag, regno): newv =3D hvx_newv(tag) predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ - ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated}); + ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated}, + insn_has_hvx_helper); """)) =20 class VRegSource(Register, Hvx, OldSource): @@ -724,7 +735,7 @@ def helper_hvx_desc(self, f): """)) def analyze_read(self, f, regno): f.write(code_fmt(f"""\ - ctx_log_vreg_read(ctx, {self.reg_num}); + ctx_log_vreg_read(ctx, {self.reg_num}, insn_has_hvx_helper); """)) =20 class VRegNewSource(Register, Hvx, NewSource): @@ -741,7 +752,7 @@ def helper_hvx_desc(self, f): """)) def analyze_read(self, f, regno): f.write(code_fmt(f"""\ - ctx_log_vreg_read_new(ctx, {self.reg_num}); + ctx_log_vreg_read_new(ctx, {self.reg_num}, insn_has_hvx_helper= ); """)) =20 class VRegReadWrite(Register, Hvx, ReadWrite): @@ -767,13 +778,14 @@ def helper_hvx_desc(self, f): """)) def analyze_read(self, f, regno): f.write(code_fmt(f"""\ - ctx_log_vreg_read(ctx, {self.reg_num}); + ctx_log_vreg_read(ctx, {self.reg_num}, insn_has_hvx_helper); """)) def analyze_write(self, f, tag, regno): newv =3D hvx_newv(tag) predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ - ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated}); + ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated}, + insn_has_hvx_helper); """)) =20 class VRegTmp(Register, Hvx, ReadWrite): @@ -801,13 +813,14 @@ def helper_hvx_desc(self, f): """)) def analyze_read(self, f, regno): f.write(code_fmt(f"""\ - ctx_log_vreg_read(ctx, {self.reg_num}); + ctx_log_vreg_read(ctx, {self.reg_num}, insn_has_hvx_helper); """)) def analyze_write(self, f, tag, regno): newv =3D hvx_newv(tag) predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ - ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated}); + ctx_log_vreg_write(ctx, {self.reg_num}, {newv}, {predicated}, + insn_has_hvx_helper); """)) =20 class VRegPairDest(Register, Hvx, Dest): @@ -832,7 +845,8 @@ def analyze_write(self, f, tag, regno): newv =3D hvx_newv(tag) predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ - ctx_log_vreg_write_pair(ctx, {self.reg_num}, {newv}, {predicat= ed}); + ctx_log_vreg_write_pair(ctx, {self.reg_num}, {newv}, {predicat= ed}, + insn_has_hvx_helper); """)) =20 class VRegPairSource(Register, Hvx, OldSource): @@ -859,7 +873,7 @@ def helper_hvx_desc(self, f): """)) def analyze_read(self, f, regno): f.write(code_fmt(f"""\ - ctx_log_vreg_read_pair(ctx, {self.reg_num}); + ctx_log_vreg_read_pair(ctx, {self.reg_num}, insn_has_hvx_helpe= r); """)) =20 class VRegPairReadWrite(Register, Hvx, ReadWrite): @@ -891,13 +905,14 @@ def helper_hvx_desc(self, f): """)) def analyze_read(self, f, regno): f.write(code_fmt(f"""\ - ctx_log_vreg_read_pair(ctx, {self.reg_num}); + ctx_log_vreg_read_pair(ctx, {self.reg_num}, insn_has_hvx_helpe= r); """)) def analyze_write(self, f, tag, regno): newv =3D hvx_newv(tag) predicated =3D "true" if is_predicated(tag) else "false" f.write(code_fmt(f"""\ - ctx_log_vreg_write_pair(ctx, {self.reg_num}, {newv}, {predicat= ed}); + ctx_log_vreg_write_pair(ctx, {self.reg_num}, {newv}, {predicat= ed}, + insn_has_hvx_helper); """)) =20 class QRegDest(Register, Hvx, Dest): @@ -920,7 +935,7 @@ def helper_hvx_desc(self, f): """)) def analyze_write(self, f, tag, regno): f.write(code_fmt(f"""\ - ctx_log_qreg_write(ctx, {self.reg_num}); + ctx_log_qreg_write(ctx, {self.reg_num}, insn_has_hvx_helper); """)) =20 class QRegSource(Register, Hvx, OldSource): @@ -941,7 +956,7 @@ def helper_hvx_desc(self, f): """)) def analyze_read(self, f, regno): f.write(code_fmt(f"""\ - ctx_log_qreg_read(ctx, {self.reg_num}); + ctx_log_qreg_read(ctx, {self.reg_num}, insn_has_hvx_helper); """)) =20 class QRegReadWrite(Register, Hvx, ReadWrite): @@ -967,11 +982,11 @@ def helper_hvx_desc(self, f): """)) def analyze_read(self, f, regno): f.write(code_fmt(f"""\ - ctx_log_qreg_read(ctx, {self.reg_num}); + ctx_log_qreg_read(ctx, {self.reg_num}, insn_has_hvx_helper); """)) def analyze_write(self, f, tag, regno): f.write(code_fmt(f"""\ - ctx_log_qreg_write(ctx, {self.reg_num}); + ctx_log_qreg_write(ctx, {self.reg_num}, insn_has_hvx_helper); """)) =20 def init_registers(): --=20 2.34.1