Currently the available PMU counters start at HPM3 and run through to
the number specified by the "pmu-num" property. There is no
requirement in the specification that the available counters be
continously numbered. This series add suppport for specifying a
discountinuous range of counters though a "pmu-mask" property.
v3:
* Use env_archcpu() in csr.c
* Re-added check to enforce deprectated "num-pmu" below limit
* Check that standard counters are not included in mask
* Remove use of MAKE_32BIT_MASK()
v2:
* Use cfg.pmu_mask wherever cfg.pmu_num was used previously
* Deprecate pmu_num property (warning, comment & updated documentation)
* Override default pmu_mask value iff pmu_num changed from default
Rob Bradford (6):
target/riscv: Propagate error from PMU setup
target/riscv: Don't assume PMU counters are continuous
target/riscv: Use existing PMU counter mask in FDT generation
target/riscv: Add "pmu-mask" property to replace "pmu-num"
docs/about/deprecated: Document RISC-V "pmu-num" deprecation
target/riscv: Use MAKE_64BIT_MASK instead of custom macro
docs/about/deprecated.rst | 10 ++++++++++
hw/riscv/virt.c | 2 +-
target/riscv/cpu.c | 13 ++++++++++---
target/riscv/cpu_cfg.h | 3 ++-
target/riscv/csr.c | 5 +++--
target/riscv/machine.c | 2 +-
target/riscv/pmu.c | 41 ++++++++++++++++++++++-----------------
target/riscv/pmu.h | 5 +++--
8 files changed, 53 insertions(+), 28 deletions(-)
--
2.41.0