hw/cxl/cxl-component-utils.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
void cxl_component_register_block_init(Object *obj,
CXLComponentState *cxl_cstate,
const char *type)
{
ComponentRegisters *cregs = &cxl_cstate->crb;
...
memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs,
".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE);
Obviously, opaque should be pointer to ComponentRegisters.
Fortunately, cregs is the first member of cxl_state, so their values are
the same.
Fixes: 9e58f52d3f8 ("hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)")
Signed-off-by: Li Zhijian <lizhijian@fujitsu.com>
---
hw/cxl/cxl-component-utils.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index f3bbf0fd131..f27a9d3cf60 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -64,8 +64,7 @@ hwaddr cxl_decode_ig(int ig)
static uint64_t cxl_cache_mem_read_reg(void *opaque, hwaddr offset,
unsigned size)
{
- CXLComponentState *cxl_cstate = opaque;
- ComponentRegisters *cregs = &cxl_cstate->crb;
+ ComponentRegisters *cregs = opaque;
if (size == 8) {
qemu_log_mask(LOG_UNIMP,
@@ -113,8 +112,7 @@ static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset,
static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
- CXLComponentState *cxl_cstate = opaque;
- ComponentRegisters *cregs = &cxl_cstate->crb;
+ ComponentRegisters *cregs = opaque;
uint32_t mask;
if (size == 8) {
--
2.41.0
On 13/10/23 03:55, Li Zhijian wrote: > void cxl_component_register_block_init(Object *obj, > CXLComponentState *cxl_cstate, > const char *type) > { > ComponentRegisters *cregs = &cxl_cstate->crb; > ... > memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs, > ".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE); > > Obviously, opaque should be pointer to ComponentRegisters. > Fortunately, cregs is the first member of cxl_state, so their values are > the same. > > Fixes: 9e58f52d3f8 ("hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)") > Signed-off-by: Li Zhijian <lizhijian@fujitsu.com> > --- > hw/cxl/cxl-component-utils.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
On 13/10/2023 16:52, Philippe Mathieu-Daudé wrote: > On 13/10/23 03:55, Li Zhijian wrote: >> void cxl_component_register_block_init(Object *obj, >> CXLComponentState *cxl_cstate, >> const char *type) >> { >> ComponentRegisters *cregs = &cxl_cstate->crb; >> ... >> memory_region_init_io(&cregs->cache_mem, obj, &cache_mem_ops, cregs, >> ".cache_mem", CXL2_COMPONENT_CM_REGION_SIZE); >> >> Obviously, opaque should be pointer to ComponentRegisters. >> Fortunately, cregs is the first member of cxl_state, so their values are >> the same. >> >> Fixes: 9e58f52d3f8 ("hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)") >> Signed-off-by: Li Zhijian <lizhijian@fujitsu.com> >> --- >> hw/cxl/cxl-component-utils.c | 6 ++---- >> 1 file changed, 2 insertions(+), 4 deletions(-) > > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Philippe, thanks for you quickly review, I just post V2 which change the source side type to CXLComponentState because the read/write require it. Please take another look. >
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