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[81.111.69.236]) by smtp.gmail.com with ESMTPSA id c16-20020a5d4f10000000b00324ae863ac1sm15583141wru.35.2023.10.11.06.45.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 06:45:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697031904; x=1697636704; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x2kQfCvmCVx9gJVDCvtHZckhf9GohCiTELJzFx8TozM=; b=wv3A7/0t/zI0qhAo6iRk55TYVW7iEQ/wZzohLb4E9a5SaYuvAijTJJFWxT6LSz7HYV 9s5PGYDaDfGm4gDZ7C9a1XHcKYF0j9WaAqd5M1b8cHOX36v8r9RGOmFvQ6fDj+iWlm/z zJv1YsLMJQWi5LxWzPkWmMWAAaz8ELpghRESTYorBS6BoVRxbRSz6NVhSRuy3CDE6JjU 895hzRjMIFTnhqbmX2ZKoKUH8HHwdh9/6vc0ocuEP5AkM25scPD5u98CYUfe/woaq0MV mffSUGuBmkUqnRgzKZDEHDEdjjO8Z//WZAAoLXKOcI6r4XfXQPWo7y6pacUUCkCYRIXi Y4Xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697031904; x=1697636704; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x2kQfCvmCVx9gJVDCvtHZckhf9GohCiTELJzFx8TozM=; b=jka0/BoSo/r2r42JXyMLbvXlthqpP3jFQ/KGNgaCQXiVDYX5rdNI/5WasxG5rgpJ+o IMVmVNx80GiOS9BNpzt1BF5NyNAsq+3IhUkt2A63MhF5kpkGzb8Pq2VgClewVAO/y6f0 0sirpxI0hSF3am2/c5xrDyvaD+jiDRq2Y8UC6gc88NgYewOBDjH/9Geeu0FprbKN1b8Z EESVscNKyEqckQbQxoIYt+ECFs/jHso+YlyGqEpiIGa5Xrn9XAoYIuCiR8trfbaD0gjY 0Hk+VIYvF3QwcGC1JHmp7F+2wXbthLQNuZg+X/Ra23/WtLJDZF/5FbZ1WfsxSFGn75f6 tpbQ== X-Gm-Message-State: AOJu0YyGKx7iBdajQkx4407xCT1S4oNWnKrntUMHiHUo+He8HuVMVA5J xi4UqK+SJLe+v+Iz7N5vVCXU7w== X-Google-Smtp-Source: AGHT+IFdUSJr2yGGGp1PpNiLVLqDVlcvV7aDT6wiAEe/721z/ch3ODyp5ecPiPj1lIxePB2bIIsZNQ== X-Received: by 2002:a05:6000:1f87:b0:32d:24c7:a268 with SMTP id bw7-20020a0560001f8700b0032d24c7a268mr5162731wrb.4.1697031904295; Wed, 11 Oct 2023 06:45:04 -0700 (PDT) From: Rajnesh Kanwal To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, rkanwal@rivosinc.com Subject: [PATCH v3 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie. Date: Wed, 11 Oct 2023 14:44:45 +0100 Message-Id: <20231011134450.117629-2-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231011134450.117629-1-rkanwal@rivosinc.com> References: <20231011134450.117629-1-rkanwal@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=rkanwal@rivosinc.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1697031970620100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 85a31dc420..0241c77719 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1524,7 +1524,7 @@ static RISCVException rmw_mie64(CPURISCVState *env, i= nt csrno, env->mie =3D (env->mie & ~mask) | (new_val & mask); =20 if (!riscv_has_ext(env, RVH)) { - env->mie &=3D ~((uint64_t)MIP_SGEIP); + env->mie &=3D ~((uint64_t)HS_MODE_INTERRUPTS); } =20 return RISCV_EXCP_NONE; --=20 2.34.1 From nobody Wed May 29 05:03:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1697032023; cv=none; d=zohomail.com; s=zohoarc; b=mwTXMtET2e0hojx288+e0GUuljn7b1E7wVa/gAemJ7sVd5htWUVFI50pDOeCvTWhrBaIVG4jy8km8fjEDftpXAs3eARzatnI16hO/j0rXHkiPmIKU70ZAfQ9V2Rq+NfGBikOkmVx6OXvEHygTXIz+Zkme+469/Wk9XQl2pwG1d0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697032023; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Fb2+LvO1+deM50mzL+oyBsOTtdeQSiHaKqKpKzvLC4g=; b=AnGK08BhQA7pDIpQ6PTaiBFFcBxpxpU3Q0R6rPTCJmz7QdorO6rhFU1GDR+GuSurokeUYO672PkdHtg0I4XOO2cNnShhTV0Xj5pE0MdPR4ud1eaV9DXooI9RbPMi6noVd5FS3bVWUrZ9BUaEwKBivxGV+5/VbFF9kGL5ELQ66ko= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169703202367738.87862072867381; Wed, 11 Oct 2023 06:47:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qqZXz-000505-Ig; Wed, 11 Oct 2023 09:46:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qqZWk-0003tn-E3 for qemu-devel@nongnu.org; Wed, 11 Oct 2023 09:45:31 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qqZWN-0001Ul-B4 for qemu-devel@nongnu.org; Wed, 11 Oct 2023 09:45:30 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-32caaa1c493so1626609f8f.3 for ; Wed, 11 Oct 2023 06:45:06 -0700 (PDT) Received: from rkanwal-XPS-15-9520.ba.rivosinc.com (cpc91760-watf12-2-0-cust235.15-2.cable.virginm.net. [81.111.69.236]) by smtp.gmail.com with ESMTPSA id c16-20020a5d4f10000000b00324ae863ac1sm15583141wru.35.2023.10.11.06.45.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 06:45:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697031905; x=1697636705; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Fb2+LvO1+deM50mzL+oyBsOTtdeQSiHaKqKpKzvLC4g=; b=Vd21BnWRdXAAXErB23TmzB5raArfdlqPAFaYOtim5JdBc4XL/7v+q2xpsGhaz2/15V W5ed91wgLDmmWRcvqTv4r0LYKE7oIMZh+D/vWry2uCOboZlqZRZ1+MnmyR3OpVNgrZFo JEe25kTRUsBhBalyQUWGDbwNDiIfQ4WnNvQ2KrkfjJo+i156D6Rl0PJgzlFStBubl8H+ hQXwxFnYZS//e2lpk5Wx2d7EVIuPxwDB+Dvr3h0DOQjmCPbn9UPDZ0pMw4BdmozrpBPP EMbDnRVMv7PbO2ZieYUS+7X2VkaiqfQJnKExCgFRvIF600d8NYM5djP9Kpepz9go+eqT OzzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697031905; x=1697636705; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Fb2+LvO1+deM50mzL+oyBsOTtdeQSiHaKqKpKzvLC4g=; b=aiS9aJ3gLQQwDMx9U6CYHNEv2lIEBjKe720zxKkbR0OSVNcVPV45kZ4m1uZ8qo/JUS HHX8fuZAL5rOhZ6KIX3yH521sEYQd61m1ugRj7dUDaJWn0BBpav5/mHF8/10QvXHy8/1 ymLDl0i4xk/1sMYQOc4udXHd70qSAltPHMB7nXWTkcPJjraveptqMg5Cj4WzA8m8SEls jAmH4XLoog+3q+gbwS3y8DHcYwWKwSQTtEmfq3bZV8q+xXvy1Dia0HuzocVCXcz504tW DKF/nFudGLohIq2Uu+dL3WmtiINqgbSqc6YIw4Rs7V1Xoe3cRxyEsk9sssrYv3y2zh4D D0Ww== X-Gm-Message-State: AOJu0YypoS9793abJLBqqTZ7TY/dqLwT2bPO+bL/FKSEnomPYIRGVv3P oEmKX9j5WAxbsRpfBIyPSK/1JQ== X-Google-Smtp-Source: AGHT+IH9R86mBtDtpLGy9m6BXuA2VmcEXRTR81RVQwhbXVy8e6zjuxLISPaUVW8g0AWZWCgvbmAyDw== X-Received: by 2002:a5d:6a08:0:b0:320:896:5ea8 with SMTP id m8-20020a5d6a08000000b0032008965ea8mr17997566wru.19.1697031905347; Wed, 11 Oct 2023 06:45:05 -0700 (PDT) From: Rajnesh Kanwal To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, rkanwal@rivosinc.com Subject: [PATCH v3 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST. Date: Wed, 11 Oct 2023 14:44:46 +0100 Message-Id: <20231011134450.117629-3-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231011134450.117629-1-rkanwal@rivosinc.com> References: <20231011134450.117629-1-rkanwal@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=rkanwal@rivosinc.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1697032024152100001 Content-Type: text/plain; charset="utf-8" RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that async flag check is performed before invoking semihosting logic. Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3a02079290..8ffb31b607 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1606,15 +1606,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong htval =3D 0; target_ulong mtval2 =3D 0; =20 - if (cause =3D=3D RISCV_EXCP_SEMIHOST) { - do_common_semihosting(cs); - env->pc +=3D 4; - return; - } - if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { + case RISCV_EXCP_SEMIHOST: + do_common_semihosting(cs); + env->pc +=3D 4; + return; case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: case RISCV_EXCP_LOAD_ADDR_MIS: --=20 2.34.1 From nobody Wed May 29 05:03:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1697032017; cv=none; d=zohomail.com; s=zohoarc; b=JWt/uKTj68MfkQL0duMiaM5p3Eb+Wp4idbu5t5cIR8HWsRnr3YVYRzKRqm0PDC1SQT53XVbRgYTquBAxVm29GHvLjlYSNb/uhvXBB+U5Zk+N1vRe1zl9kw3VoOwvHIP5d7+G2Oj7SQHP8kpRjaRSY/UElgtYgp570lCgGtAB5Xc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697032017; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PR/k1jk+L5GVDsO5EvG9L65Srx4ejFSRYd/PckSLUK8=; b=gOjSa8RmdK764+C/3OaSS+w6sKEIetkDZtFqcAwgP+NOaRBLtmNZInx7jInmcMEbSN7CVfJakYuWOdU8dgIe4S4BKGJvig1CHUY0IHnZcBT74kNPYpU9PSR4C6Qp/d79y0NB11BGMtK3hCai1TVfrniWNcF6EeW8sD9WG8y5VBo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697032017905485.1315980706527; Wed, 11 Oct 2023 06:46:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qqZWj-0003tK-5I; Wed, 11 Oct 2023 09:45:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qqZWa-0003qw-RX for qemu-devel@nongnu.org; Wed, 11 Oct 2023 09:45:20 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qqZWN-0001Vs-Ss for qemu-devel@nongnu.org; Wed, 11 Oct 2023 09:45:20 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-323ef9a8b59so6489079f8f.3 for ; Wed, 11 Oct 2023 06:45:07 -0700 (PDT) Received: from rkanwal-XPS-15-9520.ba.rivosinc.com (cpc91760-watf12-2-0-cust235.15-2.cable.virginm.net. [81.111.69.236]) by smtp.gmail.com with ESMTPSA id c16-20020a5d4f10000000b00324ae863ac1sm15583141wru.35.2023.10.11.06.45.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 06:45:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697031906; x=1697636706; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PR/k1jk+L5GVDsO5EvG9L65Srx4ejFSRYd/PckSLUK8=; b=ahA6FWYauRayOgm7zywz9j6ePjrA+NLE5d8cKi7/+2Da9QH5oKees7zJIwoeBPo/RZ 4pXDsQyzp/H4wgRn+GAM7vzS+qDpJR2mTf+5wCTH0I0zBMP05kFO/OY+SusgamZD64nP IYkbiaQgMdyRVCAgkhronlPMiweaQOtN8ONQ3S9T7JjnMGW0KrMJcuAhJ6T7S+GAjg21 ZMtL1/NTy7RZoWbT03fLYL0MniKYVRCkvMy5+PtghhzPqKLtcFMO5hqm9uJnm8czGlyf 3ZhmYdgcwH1MCZHhRxiUjam/pxmWdlIxWYqvEKiEaQvZnHIM4pScwL3I2kpa2FuLSUHv maFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697031906; x=1697636706; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PR/k1jk+L5GVDsO5EvG9L65Srx4ejFSRYd/PckSLUK8=; b=q9RsJvwUR4k2Bi4Ap3bcI+5QsyZN4rjTlU+erMwBhbO1H1PEJ5+sfxDB+i4xv0ebCp 5Cb3PIFiz6GjLqhTTazZDnHnkgXL01fnerW1qYH6YPdz3CsfhChFlUmqAznujQ5c/7h3 QqhlkxgTXLEIJz0YQ+XTN0WEA+x9i7q2ds7Hh2mn8d1ZVKRYXv7clf/i+6yf25/XxS6F QfAhhF6nj3po/lr8ZwpqB1WnJwOiBcl0T1ZtkNHxCqWpQ8l7SufqrQSkqc9PpQwg7p9R XjeDM1R5wCZd37z6YKSctvutqXwXUvQlov3l/39oOh+RfsL36qMqjwFGgRon1ql6tXfP S4Wg== X-Gm-Message-State: AOJu0Yyd3Ekhg/Go2y/eSihZgCACRNCYD6L8njeDc4jrYvt2AADggkzw nvZ9qzIQ3pflJ7UpgrVm24DOfg== X-Google-Smtp-Source: AGHT+IGS5jQXR+UdTa6GNv0WcjqmEiAwxnL2mbU4brez2BKgIg5B3dJo8e+5h6Gc9TDu/vwyD0lkbQ== X-Received: by 2002:a5d:4d06:0:b0:320:824:e3df with SMTP id z6-20020a5d4d06000000b003200824e3dfmr17929446wrt.35.1697031906376; Wed, 11 Oct 2023 06:45:06 -0700 (PDT) From: Rajnesh Kanwal To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, rkanwal@rivosinc.com Subject: [PATCH v3 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled Date: Wed, 11 Oct 2023 14:44:47 +0100 Message-Id: <20231011134450.117629-4-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231011134450.117629-1-rkanwal@rivosinc.com> References: <20231011134450.117629-1-rkanwal@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=rkanwal@rivosinc.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1697032018231100004 Content-Type: text/plain; charset="utf-8" With H-Ext supported, VS bits are all hardwired to one in MIDELEG denoting always delegated interrupts. This is being done in rmw_mideleg but given mideleg is used in other places when routing interrupts this change initializes it in riscv_cpu_realize to be on the safe side. Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac2b94b6a6..0e7620d1ad 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1492,7 +1492,12 @@ static void riscv_cpu_realize_tcg(DeviceState *dev, = Error **errp) cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, riscv_pmu_timer_cb, cpu); } - } + } + + /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ + if (riscv_has_ext(env, RVH)) { + env->mideleg =3D MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; + } #endif } =20 --=20 2.34.1 From nobody Wed May 29 05:03:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1697031997; cv=none; d=zohomail.com; s=zohoarc; b=PgWmT7bnNxsaQDvgNhefCtsWlNbqfIEaMhLgKN3oQmOi/2OW4PLCdfLD5YPzDGJZ7ENN+c7XdfUDpcDw6jui8j/AS7k+bQsr6Cgc+o6CK24LY18XmJrnLdOG+Xa9oi8WwqNxJ6dMSzO0uOA0/avGli/d8JlNq9SafjNtVqZ3f8k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697031997; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=QgjYiWrRAnOVB1lMpMitgXOQmvnNlVuniYuwRkkmmR0=; b=CKCyh91FrsYXSvJ5ptu2nuXkTggt3qZFcVkz08795Bmb3PEiDDK5pGskQPIfWGZGWmkFz1XLrqs62B5F14DPcL775zyZPEpAfqChynlIysY6J8WALbGFkqMkAwrJmjL/yJf+iyS5jd+67o2t3BPsBSn52DIVp9JBSIMMT1IWa1s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697031997263755.7679223348879; Wed, 11 Oct 2023 06:46:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qqZXc-0004Eo-Cb; Wed, 11 Oct 2023 09:46:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qqZWc-0003rd-Ry for qemu-devel@nongnu.org; Wed, 11 Oct 2023 09:45:23 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qqZWP-0001W3-K4 for qemu-devel@nongnu.org; Wed, 11 Oct 2023 09:45:22 -0400 Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-31c5cac3ae2so6209196f8f.3 for ; Wed, 11 Oct 2023 06:45:09 -0700 (PDT) Received: from rkanwal-XPS-15-9520.ba.rivosinc.com (cpc91760-watf12-2-0-cust235.15-2.cable.virginm.net. [81.111.69.236]) by smtp.gmail.com with ESMTPSA id c16-20020a5d4f10000000b00324ae863ac1sm15583141wru.35.2023.10.11.06.45.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 06:45:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697031907; x=1697636707; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QgjYiWrRAnOVB1lMpMitgXOQmvnNlVuniYuwRkkmmR0=; b=pIaKtiUD7yPkXdc3NiSNGTWRaZHDX+mx8YqvJt5e4PPMSCg1FBGd68/dRxJz6LxNfh 4FHMNJ1KEajtfMdjVgO6apafqv0QiHa6XtarHra5a+VsmVXgnJlpurCqT3kgp514FZIg rYN+4d4IOt8YMhLMwIXwG5i4Pwlk3JjI+cipelQzKjFbB6jA1eCIJzCJ3RgrDQPuY/5S FqpwNFIw7U+mzda1iisSJQvd4ApPhPmfj2lXAkoUWNG/scFL3ie+ykO/sphof2SjiENx MxL2JG/ngpbNOoAVjlJSslPjGJ2smajHi6xxLAjptTSVOPdcf8Haow79f2IDlc9tGMqU /BkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697031907; x=1697636707; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QgjYiWrRAnOVB1lMpMitgXOQmvnNlVuniYuwRkkmmR0=; b=hCryHk8v58azqDl/zIBA5kS1Vii2FKf0UKNZeBjq4wzf79LD096tU9MY/TSExwaTXj Zgux86BdyDQr5XifnKPrFztcTAzKdbaiCQcCC8DCyE2bqnBtPa1DlDKdpQb5OjCcmLQr BC8ORlTnEzucnvswA5VzSRwcZ+TwrE0OvTvPFZ8rRwJvPh5wy59b2EZdivGg7+N8wdtK ML0iwTCpu5LJQjzmo7qqiYpeJe+UWtCK36KQt2aKfqIYM9jfHOkRnJTcvHhWoFH6epD6 3OASPfa5Z1orYQ0hEWFinEptxtKBZMFsV/r0MZ8GAPV+50xcu/ixM5qzv4TkeMpoIiAU dH3A== X-Gm-Message-State: AOJu0YxENvDRrnrcIIIRA9zgP2+JjjXJ26IXL75kd4JgRivG1T/SKyPz q2MQkZJY+y7nxqYhSk6Tk5D94g== X-Google-Smtp-Source: AGHT+IErv32X2+DeHfFm0P+f3XW9YdrseUACH3rElgboZNsA39qLSxwmky5St8ea4wgrS5udKfcjVg== X-Received: by 2002:a5d:4c50:0:b0:31c:8880:5d0f with SMTP id n16-20020a5d4c50000000b0031c88805d0fmr17824917wrt.11.1697031907317; Wed, 11 Oct 2023 06:45:07 -0700 (PDT) From: Rajnesh Kanwal To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, rkanwal@rivosinc.com Subject: [PATCH v3 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip. Date: Wed, 11 Oct 2023 14:44:48 +0100 Message-Id: <20231011134450.117629-5-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231011134450.117629-1-rkanwal@rivosinc.com> References: <20231011134450.117629-1-rkanwal@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=rkanwal@rivosinc.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1697031998118100003 Content-Type: text/plain; charset="utf-8" This is to allow virtual interrupts to be inserted into S and VS modes. Given virtual interrupts will be maintained in separate mvip and hvip CSRs, riscv_cpu_update_mip will no longer be in the path and interrupts need to be triggered for these cases from rmw_hvip64 and rmw_mvip64 functions. Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 25 ++++++++++++++++++------- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ef9cf21c0c..7092aeb7f0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -460,6 +460,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t value); +void riscv_cpu_interrupt(CPURISCVState *env); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), void *arg); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8ffb31b607..a182336cd2 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -621,11 +621,12 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_= t interrupts) } } =20 -uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, - uint64_t value) +void riscv_cpu_interrupt(CPURISCVState *env) { + uint64_t gein, vsgein =3D 0, vstip =3D 0; CPUState *cs =3D env_cpu(env); - uint64_t gein, vsgein =3D 0, vstip =3D 0, old =3D env->mip; + + QEMU_IOTHREAD_LOCK_GUARD(); =20 if (env->virt_enabled) { gein =3D get_field(env->hstatus, HSTATUS_VGEIN); @@ -634,15 +635,25 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uin= t64_t mask, =20 vstip =3D env->vstime_irq ? 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Date: Wed, 11 Oct 2023 14:44:49 +0100 Message-Id: <20231011134450.117629-6-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231011134450.117629-1-rkanwal@rivosinc.com> References: <20231011134450.117629-1-rkanwal@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=rkanwal@rivosinc.com; helo=mail-wr1-x444.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1697032004196100001 Content-Type: text/plain; charset="utf-8" This change adds support for inserting virtual interrupts from M-mode into S-mode using mvien and mvip csrs. IRQ filtering is a use case of this change, i-e M-mode can stop delegating an interrupt to S-mode and instead enable it in MIE and receive those interrupts in M-mode and then selectively inject the interrupt using mvien and mvip. Also, the spec doesn't mandate the interrupt to be actually supported in hardware. Which allows M-mode to assert virtual interrupts to S-mode that have no connection to any real interrupt events. This is defined as part of the AIA specification [0], "5.3 Interrupt filtering and virtual interrupts for supervisor level". [0]: https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-int= errupts-1.0-RC4.pdf Signed-off-by: Rajnesh Kanwal Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 3 +- target/riscv/cpu.h | 8 ++ target/riscv/cpu_bits.h | 6 + target/riscv/cpu_helper.c | 26 +++- target/riscv/csr.c | 279 ++++++++++++++++++++++++++++++++++---- target/riscv/machine.c | 3 + 6 files changed, 289 insertions(+), 36 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0e7620d1ad..96f2c38334 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -825,7 +825,8 @@ static bool riscv_cpu_has_work(CPUState *cs) * Definition of the WFI instruction requires it to ignore the privile= ge * mode and delegation registers, but respect individual enables */ - return riscv_cpu_all_pending(env) !=3D 0; + return riscv_cpu_all_pending(env) !=3D 0 || + riscv_cpu_sirq_pending(env) !=3D RISCV_EXCP_NONE; #else return true; #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7092aeb7f0..6dc4271c94 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -198,6 +198,12 @@ struct CPUArchState { uint64_t mie; uint64_t mideleg; =20 + /* + * When mideleg[i]=3D0 and mvien[i]=3D1, sie[i] is no more + * alias of mie[i] and needs to be maintained separatly. + */ + uint64_t sie; + target_ulong satp; /* since: priv-1.10.0 */ target_ulong stval; target_ulong medeleg; @@ -218,6 +224,8 @@ struct CPUArchState { /* AIA CSRs */ target_ulong miselect; target_ulong siselect; + uint64_t mvien; + uint64_t mvip; =20 /* Hypervisor CSRs */ target_ulong hstatus; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 3d6ffaabc7..ebd7917d49 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -735,6 +735,12 @@ typedef enum RISCVException { #define MIE_SSIE (1 << IRQ_S_SOFT) #define MIE_USIE (1 << IRQ_U_SOFT) =20 +/* Machine constants */ +#define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) +#define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP)) +#define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) +#define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) + /* General PointerMasking CSR bits */ #define PM_ENABLE 0x00000001ULL #define PM_CURRENT 0x00000002ULL diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index a182336cd2..4a27c4fa5e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -377,6 +377,10 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, return best_irq; } =20 +/* + * Doesn't report interrupts inserted using mvip from M-mode firmware. Tho= se + * are returned in riscv_cpu_sirq_pending(). + */ uint64_t riscv_cpu_all_pending(CPURISCVState *env) { uint32_t gein =3D get_field(env->hstatus, HSTATUS_VGEIN); @@ -399,9 +403,10 @@ int riscv_cpu_sirq_pending(CPURISCVState *env) { uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); + uint64_t irqs_f =3D env->mvip & env->mvien & ~env->mideleg & env->sie; =20 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, - irqs, env->siprio); + irqs | irqs_f, env->siprio); } =20 int riscv_cpu_vsirq_pending(CPURISCVState *env) @@ -415,8 +420,8 @@ int riscv_cpu_vsirq_pending(CPURISCVState *env) =20 static int riscv_cpu_local_irq_pending(CPURISCVState *env) { + uint64_t irqs, pending, mie, hsie, vsie, irqs_f; int virq; - uint64_t irqs, pending, mie, hsie, vsie; =20 /* Determine interrupt enable state of all privilege modes */ if (env->virt_enabled) { @@ -442,8 +447,11 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *= env) irqs, env->miprio); } =20 + /* Check for virtual S-mode interrupts. */ + irqs_f =3D env->mvip & (env->mvien & ~env->mideleg) & env->sie; + /* Check HS-mode interrupts */ - irqs =3D pending & env->mideleg & ~env->hideleg & -hsie; + irqs =3D ((pending & env->mideleg & ~env->hideleg) | irqs_f) & -hsie; if (irqs) { return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, irqs, env->siprio); @@ -623,7 +631,7 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t = interrupts) =20 void riscv_cpu_interrupt(CPURISCVState *env) { - uint64_t gein, vsgein =3D 0, vstip =3D 0; + uint64_t gein, vsgein =3D 0, vstip =3D 0, irqf =3D 0; CPUState *cs =3D env_cpu(env); =20 QEMU_IOTHREAD_LOCK_GUARD(); @@ -631,11 +639,13 @@ void riscv_cpu_interrupt(CPURISCVState *env) if (env->virt_enabled) { gein =3D get_field(env->hstatus, HSTATUS_VGEIN); vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; + } else { + irqf =3D env->mvien & env->mvip & env->sie; } =20 vstip =3D env->vstime_irq ? MIP_VSTIP : 0; =20 - if (env->mip | vsgein | vstip) { + if (env->mip | vsgein | vstip | irqf) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); @@ -1612,6 +1622,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool async =3D !!(cs->exception_index & RISCV_EXCP_INT_FLAG); target_ulong cause =3D cs->exception_index & RISCV_EXCP_INT_MASK; uint64_t deleg =3D async ? env->mideleg : env->medeleg; + bool s_injected =3D env->mvip & (1 << cause) & env->mvien && + !(env->mip & (1 << cause)); target_ulong tval =3D 0; target_ulong tinst =3D 0; target_ulong htval =3D 0; @@ -1700,8 +1712,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) __func__, env->mhartid, async, cause, env->pc, tval, riscv_cpu_get_trap_name(cause, async)); =20 - if (env->priv <=3D PRV_S && - cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { + if (env->priv <=3D PRV_S && cause < 64 && + (((deleg >> cause) & 1) || s_injected)) { /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0241c77719..82801b7db0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1116,21 +1116,16 @@ static RISCVException write_stimecmph(CPURISCVState= *env, int csrno, return RISCV_EXCP_NONE; } =20 -/* Machine constants */ - -#define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) -#define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP | \ - MIP_LCOFIP)) -#define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) -#define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) - #define VSTOPI_NUM_SRCS 5 =20 -static const uint64_t delegable_ints =3D S_MODE_INTERRUPTS | - VS_MODE_INTERRUPTS; -static const uint64_t vs_delegable_ints =3D VS_MODE_INTERRUPTS; +#define LOCAL_INTERRUPTS (~0x1FFF) + +static const uint64_t delegable_ints =3D + S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP; +static const uint64_t vs_delegable_ints =3D + (VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & ~MIP_LCOFIP; static const uint64_t all_ints =3D M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | - HS_MODE_INTERRUPTS; + HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ @@ -1161,12 +1156,30 @@ static const target_ulong vs_delegable_excps =3D DE= LEGABLE_EXCPS & static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI= E | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; -static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP | - SIP_LCOFIP; + +/* + * Spec allows for bits 13:63 to be either read-only or writable. + * So far we have interrupt LCOFIP in that region which is writable. + * + * Also, spec allows to inject virtual interrupts in this region even + * without any hardware interrupts for that interrupt number. + * + * For now interrupt in 13:63 region are all kept writable. 13 being + * LCOFIP and 14:63 being virtual only. Change this in future if we + * introduce more interrupts that are not writable. + */ + +/* Bit STIP can be an alias of mip.STIP that's why it's writable in mvip. = */ +static const target_ulong mvip_writable_mask =3D MIP_SSIP | MIP_STIP | MIP= _SEIP | + LOCAL_INTERRUPTS; +static const target_ulong mvien_writable_mask =3D MIP_SSIP | MIP_SEIP | + LOCAL_INTERRUPTS; + +static const target_ulong sip_writable_mask =3D SIP_SSIP | LOCAL_INTERRUPT= S; static const target_ulong hip_writable_mask =3D MIP_VSSIP; static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | - MIP_VSEIP; -static const target_ulong vsip_writable_mask =3D MIP_VSSIP; + MIP_VSEIP | LOCAL_INTERRUPTS; +static const target_ulong vsip_writable_mask =3D MIP_VSSIP | LOCAL_INTERRU= PTS; =20 const bool valid_vm_1_10_32[16] =3D { [VM_1_10_MBARE] =3D true, @@ -1561,6 +1574,52 @@ static RISCVException rmw_mieh(CPURISCVState *env, i= nt csrno, return ret; } =20 +static RISCVException rmw_mvien64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask) +{ + uint64_t mask =3D wr_mask & mvien_writable_mask; + + if (ret_val) { + *ret_val =3D env->mvien; + } + + env->mvien =3D (env->mvien & ~mask) | (new_val & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException rmw_mvien(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_mvien64(env, csrno, &rval, new_val, wr_mask); + if (ret_val) { + *ret_val =3D rval; + } + + return ret; +} + +static RISCVException rmw_mvienh(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_mvien64(env, csrno, &rval, + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); + if (ret_val) { + *ret_val =3D rval >> 32; + } + + return ret; +} + static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val) { int irq; @@ -1702,6 +1761,11 @@ static int rmw_xireg(CPURISCVState *env, int csrno, = target_ulong *val, priv =3D PRV_M; break; case CSR_SIREG: + if (env->priv =3D=3D PRV_S && env->mvien & MIP_SEIP && + env->siselect >=3D ISELECT_IMSIC_EIDELIVERY && + env->siselect <=3D ISELECT_IMSIC_EIE63) { + goto done; + } iprio =3D env->siprio; isel =3D env->siselect; priv =3D PRV_S; @@ -1768,6 +1832,9 @@ static int rmw_xtopei(CPURISCVState *env, int csrno, = target_ulong *val, priv =3D PRV_M; break; case CSR_STOPEI: + if (env->mvien & MIP_SEIP && env->priv =3D=3D PRV_S) { + goto done; + } priv =3D PRV_S; break; case CSR_VSTOPEI: @@ -2359,6 +2426,143 @@ static RISCVException rmw_miph(CPURISCVState *env, = int csrno, return ret; } =20 +/* + * The function is written for two use-cases: + * 1- To access mvip csr as is for m-mode access. + * 2- To access sip as a combination of mip and mvip for s-mode. + * + * Both report bits 1, 5, 9 and 13:63 but with the exception of + * STIP being read-only zero in case of mvip when sstc extension + * is present. + * Also, sip needs to be read-only zero when both mideleg[i] and + * mvien[i] are zero but mvip needs to be an alias of mip. + */ +static RISCVException rmw_mvip64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask) +{ + RISCVCPU *cpu =3D env_archcpu(env); + target_ulong ret_mip =3D 0; + RISCVException ret; + uint64_t old_mvip; + + /* + * mideleg[i] mvien[i] + * 0 0 No delegation. mvip[i] is alias of mip[i]. + * 0 1 mvip[i] becomes source of interrupt, mip bypas= sed. + * 1 X mip[i] is source of interrupt and mvip[i] alia= ses + * mip[i]. + * + * So alias condition would be for bits: + * ((S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & (mideleg | ~mvien)) | + * (!sstc & MIP_STIP) + * + * Non-alias condition will be for bits: + * (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & (~mideleg & mvien) + * + * alias_mask denotes the bits that come from mip nalias_mask denotes= bits + * that come from hvip. + */ + uint64_t alias_mask =3D ((S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & + (env->mideleg | ~env->mvien)) | MIP_STIP; + uint64_t nalias_mask =3D (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & + (~env->mideleg & env->mvien); + uint64_t wr_mask_mvip; + uint64_t wr_mask_mip; + + /* + * mideleg[i] mvien[i] + * 0 0 sip[i] read-only zero. + * 0 1 sip[i] alias of mvip[i]. + * 1 X sip[i] alias of mip[i]. + * + * Both alias and non-alias mask remain same for sip except for bits + * which are zero in both mideleg and mvien. + */ + if (csrno =3D=3D CSR_SIP) { + /* Remove bits that are zero in both mideleg and mvien. */ + alias_mask &=3D (env->mideleg | env->mvien); + nalias_mask &=3D (env->mideleg | env->mvien); + } + + /* + * If sstc is present, mvip.STIP is not an alias of mip.STIP so clear + * that our in mip returned value. + */ + if (cpu->cfg.ext_sstc && (env->priv =3D=3D PRV_M) && + get_field(env->menvcfg, MENVCFG_STCE)) { + alias_mask &=3D ~MIP_STIP; + } + + wr_mask_mip =3D wr_mask & alias_mask & mvip_writable_mask; + wr_mask_mvip =3D wr_mask & nalias_mask & mvip_writable_mask; + + /* + * For bits set in alias_mask, mvip needs to be alias of mip, so forwa= rd + * this to rmw_mip. + */ + ret =3D rmw_mip(env, CSR_MIP, &ret_mip, new_val, wr_mask_mip); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + old_mvip =3D env->mvip; + + /* + * Write to mvip. Update only non-alias bits. Alias bits were updated + * in mip in rmw_mip above. + */ + if (wr_mask_mvip) { + env->mvip =3D (env->mvip & ~wr_mask_mvip) | (new_val & wr_mask_mvi= p); + + /* + * Given mvip is separate source from mip, we need to trigger inte= rrupt + * from here separately. Normally this happen from riscv_cpu_updat= e_mip. + */ + riscv_cpu_interrupt(env); + } + + if (ret_val) { + ret_mip &=3D alias_mask; + old_mvip &=3D nalias_mask; + + *ret_val =3D old_mvip | ret_mip; + } + + return RISCV_EXCP_NONE; +} + +static RISCVException rmw_mvip(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_mvip64(env, csrno, &rval, new_val, wr_mask); + if (ret_val) { + *ret_val =3D rval; + } + + return ret; +} + +static RISCVException rmw_mviph(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_mvip64(env, csrno, &rval, + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); + if (ret_val) { + *ret_val =3D rval >> 32; + } + + return ret; +} + /* Supervisor Trap Setup */ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, Int128 *val) @@ -2453,20 +2657,37 @@ static RISCVException rmw_sie64(CPURISCVState *env,= int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { + uint64_t nalias_mask =3D (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & + (~env->mideleg & env->mvien); + uint64_t alias_mask =3D (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & env->= mideleg; + uint64_t sie_mask =3D wr_mask & nalias_mask; RISCVException ret; - uint64_t mask =3D env->mideleg & S_MODE_INTERRUPTS; =20 + /* + * mideleg[i] mvien[i] + * 0 0 sie[i] read-only zero. + * 0 1 sie[i] is a separate writable bit. + * 1 X sie[i] alias of mie[i]. + * + * Both alias and non-alias mask remain same for sip except for bits + * which are zero in both mideleg and mvien. + */ if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } ret =3D rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask); + if (ret_val) { + *ret_val &=3D alias_mask; + } } else { - ret =3D rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask); - } + ret =3D rmw_mie64(env, csrno, ret_val, new_val, wr_mask & alias_ma= sk); + if (ret_val) { + *ret_val &=3D alias_mask; + *ret_val |=3D env->sie & nalias_mask; + } =20 - if (ret_val) { - *ret_val &=3D mask; + env->sie =3D (env->sie & ~sie_mask) | (new_val & sie_mask); } =20 return ret; @@ -2664,7 +2885,7 @@ static RISCVException rmw_sip64(CPURISCVState *env, i= nt csrno, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; - uint64_t mask =3D env->mideleg & sip_writable_mask; + uint64_t mask =3D (env->mideleg | env->mvien) & sip_writable_mask; =20 if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { @@ -2672,11 +2893,12 @@ static RISCVException rmw_sip64(CPURISCVState *env,= int csrno, } ret =3D rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask); } else { - ret =3D rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask); + ret =3D rmw_mvip64(env, csrno, ret_val, new_val, wr_mask & mask); } =20 if (ret_val) { - *ret_val &=3D env->mideleg & S_MODE_INTERRUPTS; + *ret_val &=3D (env->mideleg | env->mvien) & + (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS); } =20 return ret; @@ -2841,6 +3063,7 @@ static int read_vstopi(CPURISCVState *env, int csrno,= target_ulong *val) =20 *val =3D (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT; *val |=3D iprio; + return RISCV_EXCP_NONE; } =20 @@ -4164,14 +4387,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MTOPI] =3D { "mtopi", aia_any, read_mtopi }, =20 /* Virtual Interrupts for Supervisor Level (AIA) */ - [CSR_MVIEN] =3D { "mvien", aia_any, read_zero, write_ignore }, - [CSR_MVIP] =3D { "mvip", aia_any, read_zero, write_ignore }, + [CSR_MVIEN] =3D { "mvien", aia_any, NULL, NULL, rmw_mvien }, + [CSR_MVIP] =3D { "mvip", aia_any, NULL, NULL, rmw_mvip }, =20 /* Machine-Level High-Half CSRs (AIA) */ [CSR_MIDELEGH] =3D { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, [CSR_MIEH] =3D { "mieh", aia_any32, NULL, NULL, rmw_mieh }, - [CSR_MVIENH] =3D { "mvienh", aia_any32, read_zero, write_ignore }, - [CSR_MVIPH] =3D { "mviph", aia_any32, read_zero, write_ignore }, + [CSR_MVIENH] =3D { "mvienh", aia_any32, NULL, NULL, rmw_mvienh }, + [CSR_MVIPH] =3D { "mviph", aia_any32, NULL, NULL, rmw_mviph }, [CSR_MIPH] =3D { "miph", aia_any32, NULL, NULL, rmw_miph }, =20 /* Execution environment configuration */ diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c7c862cdd3..3175587b0d 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -379,6 +379,9 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT64(env.mip, RISCVCPU), VMSTATE_UINT64(env.miclaim, RISCVCPU), VMSTATE_UINT64(env.mie, RISCVCPU), + VMSTATE_UINT64(env.mvien, RISCVCPU), + VMSTATE_UINT64(env.mvip, RISCVCPU), + VMSTATE_UINT64(env.sie, RISCVCPU), VMSTATE_UINT64(env.mideleg, RISCVCPU), VMSTATE_UINTTL(env.satp, RISCVCPU), VMSTATE_UINTTL(env.stval, RISCVCPU), --=20 2.34.1 From nobody Wed May 29 05:03:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Date: Wed, 11 Oct 2023 14:44:50 +0100 Message-Id: <20231011134450.117629-7-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231011134450.117629-1-rkanwal@rivosinc.com> References: <20231011134450.117629-1-rkanwal@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=rkanwal@rivosinc.com; helo=mail-wr1-x441.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1697032016154100001 Content-Type: text/plain; charset="utf-8" This change adds support for inserting virtual interrupts from HS-mode into VS-mode using hvien and hvip csrs. This also allows for IRQ filtering from HS-mode. Also, the spec doesn't mandate the interrupt to be actually supported in hardware. Which allows HS-mode to assert virtual interrupts to VS-mode that have no connection to any real interrupt events. This is defined as part of the AIA specification [0], "6.3.2 Virtual interrupts for VS level". [0]: https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-int= errupts-1.0-RC4.pdf Signed-off-by: Rajnesh Kanwal Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 3 +- target/riscv/cpu.h | 14 +++ target/riscv/cpu_helper.c | 48 +++++++--- target/riscv/csr.c | 196 ++++++++++++++++++++++++++++++++++---- target/riscv/machine.c | 3 + 5 files changed, 234 insertions(+), 30 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 96f2c38334..841ba38cf8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -826,7 +826,8 @@ static bool riscv_cpu_has_work(CPUState *cs) * mode and delegation registers, but respect individual enables */ return riscv_cpu_all_pending(env) !=3D 0 || - riscv_cpu_sirq_pending(env) !=3D RISCV_EXCP_NONE; + riscv_cpu_sirq_pending(env) !=3D RISCV_EXCP_NONE || + riscv_cpu_vsirq_pending(env) !=3D RISCV_EXCP_NONE; #else return true; #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6dc4271c94..4195d01617 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -204,6 +204,12 @@ struct CPUArchState { */ uint64_t sie; =20 + /* + * When hideleg[i]=3D0 and hvien[i]=3D1, vsie[i] is no more + * alias of sie[i] (mie[i]) and needs to be maintained separatly. + */ + uint64_t vsie; + target_ulong satp; /* since: priv-1.10.0 */ target_ulong stval; target_ulong medeleg; @@ -238,6 +244,14 @@ struct CPUArchState { target_ulong hgeie; target_ulong hgeip; uint64_t htimedelta; + uint64_t hvien; + + /* + * Bits VSSIP, VSTIP and VSEIP in hvip are maintained in mip. Other bi= ts + * from 0:12 are reserved. Bits 13:63 are not aliased and must be sepa= rately + * maintain in hvip. + */ + uint64_t hvip; =20 /* Hypervisor controlled virtual interrupt priorities */ target_ulong hvictl; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4a27c4fa5e..0594c8b1ae 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -378,8 +378,9 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, } =20 /* - * Doesn't report interrupts inserted using mvip from M-mode firmware. Tho= se - * are returned in riscv_cpu_sirq_pending(). + * Doesn't report interrupts inserted using mvip from M-mode firmware or + * using hvip bits 13:63 from HS-mode. Those are returned in + * riscv_cpu_sirq_pending() and riscv_cpu_vsirq_pending(). */ uint64_t riscv_cpu_all_pending(CPURISCVState *env) { @@ -411,16 +412,23 @@ int riscv_cpu_sirq_pending(CPURISCVState *env) =20 int riscv_cpu_vsirq_pending(CPURISCVState *env) { - uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); + uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & env->hid= eleg; + uint64_t irqs_f_vs =3D env->hvip & env->hvien & ~env->hideleg & env->v= sie; + uint64_t vsbits; + + /* Bring VS-level bits to correct position */ + vsbits =3D irqs & VS_MODE_INTERRUPTS; + irqs &=3D ~VS_MODE_INTERRUPTS; + irqs |=3D vsbits >> 1; =20 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, - irqs >> 1, env->hviprio); + (irqs | irqs_f_vs), env->hviprio); } =20 static int riscv_cpu_local_irq_pending(CPURISCVState *env) { - uint64_t irqs, pending, mie, hsie, vsie, irqs_f; + uint64_t irqs, pending, mie, hsie, vsie, irqs_f, irqs_f_vs; + uint64_t vsbits, irq_delegated; int virq; =20 /* Determine interrupt enable state of all privilege modes */ @@ -457,12 +465,26 @@ static int riscv_cpu_local_irq_pending(CPURISCVState = *env) irqs, env->siprio); } =20 + /* Check for virtual VS-mode interrupts. */ + irqs_f_vs =3D env->hvip & env->hvien & ~env->hideleg & env->vsie; + /* Check VS-mode interrupts */ - irqs =3D pending & env->mideleg & env->hideleg & -vsie; + irq_delegated =3D pending & env->mideleg & env->hideleg; + + /* Bring VS-level bits to correct position */ + vsbits =3D irq_delegated & VS_MODE_INTERRUPTS; + irq_delegated &=3D ~VS_MODE_INTERRUPTS; + irq_delegated |=3D vsbits >> 1; + + irqs =3D (irq_delegated | irqs_f_vs) & -vsie; if (irqs) { virq =3D riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, - irqs >> 1, env->hviprio); - return (virq <=3D 0) ? virq : virq + 1; + irqs, env->hviprio); + if (virq <=3D 0 || (virq > 12 && virq <=3D 63)) { + return virq; + } else { + return virq + 1; + } } =20 /* Indicate no pending interrupt */ @@ -639,6 +661,7 @@ void riscv_cpu_interrupt(CPURISCVState *env) if (env->virt_enabled) { gein =3D get_field(env->hstatus, HSTATUS_VGEIN); vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; + irqf =3D env->hvien & env->hvip & env->vsie; } else { irqf =3D env->mvien & env->mvip & env->sie; } @@ -1624,6 +1647,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) uint64_t deleg =3D async ? env->mideleg : env->medeleg; bool s_injected =3D env->mvip & (1 << cause) & env->mvien && !(env->mip & (1 << cause)); + bool vs_injected =3D env->hvip & (1 << cause) & env->hvien && + !(env->mip & (1 << cause)); target_ulong tval =3D 0; target_ulong tinst =3D 0; target_ulong htval =3D 0; @@ -1713,12 +1738,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_get_trap_name(cause, async)); =20 if (env->priv <=3D PRV_S && cause < 64 && - (((deleg >> cause) & 1) || s_injected)) { + (((deleg >> cause) & 1) || s_injected || vs_injected)) { /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; =20 - if (env->virt_enabled && ((hdeleg >> cause) & 1)) { + if (env->virt_enabled && + (((hdeleg >> cause) & 1) || vs_injected)) { /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode inte= rrupt diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 82801b7db0..ba5b596edd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -29,6 +29,7 @@ #include "qemu/guest-random.h" #include "qapi/error.h" =20 + /* CSR function table public API */ void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) { @@ -1179,6 +1180,8 @@ static const target_ulong sip_writable_mask =3D SIP_S= SIP | LOCAL_INTERRUPTS; static const target_ulong hip_writable_mask =3D MIP_VSSIP; static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | LOCAL_INTERRUPTS; +static const target_ulong hvien_writable_mask =3D LOCAL_INTERRUPTS; + static const target_ulong vsip_writable_mask =3D MIP_VSSIP | LOCAL_INTERRU= PTS; =20 const bool valid_vm_1_10_32[16] =3D { @@ -2607,16 +2610,36 @@ static RISCVException rmw_vsie64(CPURISCVState *env= , int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { + uint64_t alias_mask =3D (LOCAL_INTERRUPTS | VS_MODE_INTERRUPTS) & + env->hideleg; + uint64_t nalias_mask =3D LOCAL_INTERRUPTS & (~env->hideleg & env->hvie= n); + uint64_t rval, rval_vs, vsbits; + uint64_t wr_mask_vsie; + uint64_t wr_mask_mie; RISCVException ret; - uint64_t rval, mask =3D env->hideleg & VS_MODE_INTERRUPTS; =20 /* Bring VS-level bits to correct position */ - new_val =3D (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; - wr_mask =3D (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; + vsbits =3D new_val & (VS_MODE_INTERRUPTS >> 1); + new_val &=3D ~(VS_MODE_INTERRUPTS >> 1); + new_val |=3D vsbits << 1; + + vsbits =3D wr_mask & (VS_MODE_INTERRUPTS >> 1); + wr_mask &=3D ~(VS_MODE_INTERRUPTS >> 1); + wr_mask |=3D vsbits << 1; + + wr_mask_mie =3D wr_mask & alias_mask; + wr_mask_vsie =3D wr_mask & nalias_mask; + + ret =3D rmw_mie64(env, csrno, &rval, new_val, wr_mask_mie); + + rval_vs =3D env->vsie & nalias_mask; + env->vsie =3D (env->vsie & ~wr_mask_vsie) | (new_val & wr_mask_vsie); =20 - ret =3D rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask); if (ret_val) { - *ret_val =3D (rval & mask) >> 1; + rval &=3D alias_mask; + vsbits =3D rval & VS_MODE_INTERRUPTS; + rval &=3D ~VS_MODE_INTERRUPTS; + *ret_val =3D rval | (vsbits >> 1) | rval_vs; } =20 return ret; @@ -2829,21 +2852,36 @@ static RISCVException write_stval(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException rmw_hvip64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask); + static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; uint64_t rval, mask =3D env->hideleg & VS_MODE_INTERRUPTS; + uint64_t vsbits; =20 - /* Bring VS-level bits to correct position */ - new_val =3D (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; - wr_mask =3D (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; + /* Add virtualized bits into vsip mask. */ + mask |=3D env->hvien & ~env->hideleg; =20 - ret =3D rmw_mip64(env, csrno, &rval, new_val, - wr_mask & mask & vsip_writable_mask); + /* Bring VS-level bits to correct position */ + vsbits =3D new_val & (VS_MODE_INTERRUPTS >> 1); + new_val &=3D ~(VS_MODE_INTERRUPTS >> 1); + new_val |=3D vsbits << 1; + vsbits =3D wr_mask & (VS_MODE_INTERRUPTS >> 1); + wr_mask &=3D ~(VS_MODE_INTERRUPTS >> 1); + wr_mask |=3D vsbits << 1; + + ret =3D rmw_hvip64(env, csrno, &rval, new_val, + wr_mask & mask & vsip_writable_mask); if (ret_val) { - *ret_val =3D (rval & mask) >> 1; + rval &=3D mask; + vsbits =3D rval & VS_MODE_INTERRUPTS; + rval &=3D ~VS_MODE_INTERRUPTS; + *ret_val =3D rval | (vsbits >> 1); } =20 return ret; @@ -3135,6 +3173,52 @@ static RISCVException write_hedeleg(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException rmw_hvien64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask) +{ + uint64_t mask =3D wr_mask & hvien_writable_mask; + + if (ret_val) { + *ret_val =3D env->hvien; + } + + env->hvien =3D (env->hvien & ~mask) | (new_val & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException rmw_hvien(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_hvien64(env, csrno, &rval, new_val, wr_mask); + if (ret_val) { + *ret_val =3D rval; + } + + return ret; +} + +static RISCVException rmw_hvienh(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_m= ask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_hvien64(env, csrno, &rval, + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); + if (ret_val) { + *ret_val =3D rval >> 32; + } + + return ret; +} + static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) @@ -3180,16 +3264,94 @@ static RISCVException rmw_hidelegh(CPURISCVState *e= nv, int csrno, return ret; } =20 +/* + * The function is written for two use-cases: + * 1- To access hvip csr as is for HS-mode access. + * 2- To access vsip as a combination of hvip, and mip for vs-mode. + * + * Both report bits 2, 6, 10 and 13:63. + * vsip needs to be read-only zero when both hideleg[i] and + * hvien[i] are zero. + */ static RISCVException rmw_hvip64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; + uint64_t old_hvip; + uint64_t ret_mip; + + /* + * For bits 10, 6 and 2, vsip[i] is an alias of hip[i]. These bits are + * present in hip, hvip and mip. Where mip[i] is alias of hip[i] and h= vip[i] + * is OR'ed in hip[i] to inject virtual interrupts from hypervisor. Th= ese + * bits are actually being maintained in mip so we read them from ther= e. + * This way we have a single source of truth and allows for easier + * implementation. + * + * For bits 13:63 we have: + * + * hideleg[i] hvien[i] + * 0 0 No delegation. vsip[i] readonly zero. + * 0 1 vsip[i] is alias of hvip[i], sip bypassed. + * 1 X vsip[i] is alias of sip[i], hvip bypassed. + * + * alias_mask denotes the bits that come from sip (mip here given we + * maintain all bits there). nalias_mask denotes bits that come from + * hvip. + */ + uint64_t alias_mask =3D (env->hideleg | ~env->hvien) | VS_MODE_INTERRU= PTS; + uint64_t nalias_mask =3D (~env->hideleg & env->hvien); + uint64_t wr_mask_hvip; + uint64_t wr_mask_mip; + + /* + * Both alias and non-alias mask remain same for vsip except: + * 1- For VS* bits if they are zero in hideleg. + * 2- For 13:63 bits if they are zero in both hideleg and hvien. + */ + if (csrno =3D=3D CSR_VSIP) { + /* zero-out VS* bits that are not delegated to VS mode. */ + alias_mask &=3D (env->hideleg | ~VS_MODE_INTERRUPTS); + + /* + * zero-out 13:63 bits that are zero in both hideleg and hvien. + * nalias_mask mask can not contain any VS* bits so only second + * condition applies on it. + */ + nalias_mask &=3D (env->hideleg | env->hvien); + alias_mask &=3D (env->hideleg | env->hvien); + } + + wr_mask_hvip =3D wr_mask & nalias_mask & hvip_writable_mask; + wr_mask_mip =3D wr_mask & alias_mask & hvip_writable_mask; + + /* Aliased bits, bits 10, 6, 2 need to come from mip. */ + ret =3D rmw_mip64(env, csrno, &ret_mip, new_val, wr_mask_mip); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + old_hvip =3D env->hvip; + + if (wr_mask_hvip) { + env->hvip =3D (env->hvip & ~wr_mask_hvip) | (new_val & wr_mask_hvi= p); + + /* + * Given hvip is separate source from mip, we need to trigger inte= rrupt + * from here separately. Normally this happen from riscv_cpu_updat= e_mip. + */ + riscv_cpu_interrupt(env); + } =20 - ret =3D rmw_mip64(env, csrno, ret_val, new_val, - wr_mask & hvip_writable_mask); if (ret_val) { - *ret_val &=3D VS_MODE_INTERRUPTS; + /* Only take VS* bits from mip. */ + ret_mip &=3D alias_mask; + + /* Take in non-delegated 13:63 bits from hvip. */ + old_hvip &=3D nalias_mask; + + *ret_val =3D ret_mip | old_hvip; } =20 return ret; @@ -4568,14 +4730,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, =20 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) = */ - [CSR_HVIEN] =3D { "hvien", aia_hmode, read_zero, write_ign= ore }, + [CSR_HVIEN] =3D { "hvien", aia_hmode, NULL, NULL, rmw_hvie= n }, [CSR_HVICTL] =3D { "hvictl", aia_hmode, read_hvictl, write_hvictl = }, [CSR_HVIPRIO1] =3D { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 = }, [CSR_HVIPRIO2] =3D { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 = }, - /* * VS-Level Window to Indirectly Accessed Registers (H-extension with = AIA) */ @@ -4590,8 +4751,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ [CSR_HIDELEGH] =3D { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh = }, - [CSR_HVIENH] =3D { "hvienh", aia_hmode32, read_zero, - write_ignore = }, + [CSR_HVIENH] =3D { "hvienh", aia_hmode32, NULL, NULL, rmw_hv= ienh }, [CSR_HVIPH] =3D { "hviph", aia_hmode32, NULL, NULL, rmw_hv= iph }, [CSR_HVIPRIO1H] =3D { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h = }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 3175587b0d..97e79d333f 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -92,6 +92,8 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINTTL(env.hgatp, RISCVCPU), VMSTATE_UINTTL(env.hgeie, RISCVCPU), VMSTATE_UINTTL(env.hgeip, RISCVCPU), + VMSTATE_UINT64(env.hvien, RISCVCPU), + VMSTATE_UINT64(env.hvip, RISCVCPU), VMSTATE_UINT64(env.htimedelta, RISCVCPU), VMSTATE_UINT64(env.vstimecmp, RISCVCPU), =20 @@ -106,6 +108,7 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINTTL(env.vstval, RISCVCPU), VMSTATE_UINTTL(env.vsatp, RISCVCPU), VMSTATE_UINTTL(env.vsiselect, RISCVCPU), + VMSTATE_UINT64(env.vsie, RISCVCPU), =20 VMSTATE_UINTTL(env.mtval2, RISCVCPU), VMSTATE_UINTTL(env.mtinst, RISCVCPU), --=20 2.34.1