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[85.226.240.245]) by smtp.gmail.com with ESMTPSA id q2-20020ac25102000000b00500a4679148sm235154lfb.20.2023.10.05.03.04.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Oct 2023 03:04:44 -0700 (PDT) Received: by flawful.org (Postfix, from userid 112) id 4FC80B825; Thu, 5 Oct 2023 12:04:43 +0200 (CEST) Received: from x1-carbon.lan (OpenWrt.lan [192.168.1.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by flawful.org (Postfix) with ESMTPSA id F2D213EEC; Thu, 5 Oct 2023 12:04:24 +0200 (CEST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696500284; x=1697105084; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dkim-signature:dkim-signature:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fzxhQFr0lyOZPYfoaCWcAHMkrVCkPctHzsLj+f/d9PM=; b=iDnCoceFUBcdAEl35UHmQNVs3+g7N76dueX2Px8j8d67YXnEJYU886blRKr9ZZJqlg Sy9qyUS+emjWltuffG8p+4W47HrHz43o3F4jkKLlhCwXioF1moEN1dwdHVG8+C2zdLiy 3zkAs25NSorjnupnJQzj4B+91A0fyUSxSxk3X+bLahu8DRTFRR2DEXOcj+Wd3MpAwJ7N oIkZx8tilJVBgaQ1+nN6DAlQxoTjl9mKbbGGstJrNCa6OtHBHv1Rp5ON5ZYHRs6S5V46 HXAlYQx7hRqCY/kTbxq4v/wcKfjuK4Tie/rcRoVieJyvF93GF0fREFzumTqisddwMWqU X4fg== X-Gm-Message-State: AOJu0Yy+65zerYMj+44Z939EDFzZRvoqQgp21vwvdhdPCWhU+v+vfEK5 I9oWxJjfqNYKELnkc9fCPHadSShn6uWquw== X-Google-Smtp-Source: AGHT+IGSDflnGP0nomMkmeFz4iisfFN/0q6qnKVLObd81ffqPObRvNU+0Otv5inOZT6d8glsSa3aBg== X-Received: by 2002:a05:6512:10c9:b0:504:3807:22a4 with SMTP id k9-20020a05651210c900b00504380722a4mr5280238lfg.23.1696500284464; Thu, 05 Oct 2023 03:04:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1696500283; bh=rILs7CcOSgKih8VobjLFN3rA4GjJ2f5YTx7ZWKAgRQU=; h=From:To:Cc:Subject:Date:From; b=QVG7DufkJJHol8mlGXm7ovi2PLu1uEa4I/DS5jLwJxQPGjUnSvU6O/vuH7r9ToQ4N GcwKBjSSOTFVXPX8xakXJjWq6wGSNLyPQynvkiVtiRbqLGTVHB9wKMau5eZr4fseXe AmwO7pBEsYMVyVTRDoQKSieg19U0+4akOSIm4MhQ= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=flawful.org; s=mail; t=1696500265; bh=rILs7CcOSgKih8VobjLFN3rA4GjJ2f5YTx7ZWKAgRQU=; h=From:To:Cc:Subject:Date:From; b=KbjQx1bW4zcEvW49+fGQhRPpbYKLrSvoMU/tZZatJ6ictpXKGTgcRVq5M5fOA6pnb k/IoMVGZffqBocb0Ssbu2xWD1um3d7j0wDeqnSRwBb0JuvkvGXN0Kctq1MyfNCbyZ4 RbrhNtK2jOucSDkACD/KLZ9K2wpRmLM3lI6CHrc4= From: Niklas Cassel To: John Snow Cc: qemu-block@nongnu.org, qemu-devel@nongnu.org, Damien Le Moal , Marcin Juszkiewicz , Michael Tokarev , Niklas Cassel Subject: [PATCH v2] hw/ide/ahci: fix legacy software reset Date: Thu, 5 Oct 2023 12:04:07 +0200 Message-ID: <20231005100407.1136484-1-nks@flawful.org> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12f; envelope-from=nks.gnu@gmail.com; helo=mail-lf1-x12f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @flawful.org) (identity @flawful.org) X-ZM-MESSAGEID: 1696500360404100002 Content-Type: text/plain; charset="utf-8" From: Niklas Cassel Legacy software contains a standard mechanism for generating a reset to a Serial ATA device - setting the SRST (software reset) bit in the Device Control register. Serial ATA has a more robust mechanism called COMRESET, also referred to as port reset. A port reset is the preferred mechanism for error recovery and should be used in place of software reset. Commit e2a5d9b3d9c3 ("hw/ide/ahci: simplify and document PxCI handling") improved the handling of PxCI, such that PxCI gets cleared after handling a non-NCQ, or NCQ command (instead of incorrectly clearing PxCI after receiving an arbitrary FIS). However, simply clearing PxCI after a non-NCQ, or NCQ command, is not enough, we also need to clear PxCI when receiving a SRST in the Device Control register. This fixes an issue for FreeBSD where the device would fail to reset. The problem was not noticed in Linux, because Linux uses a COMRESET instead of a legacy software reset by default. Fixes: e2a5d9b3d9c3 ("hw/ide/ahci: simplify and document PxCI handling") Reported-by: Marcin Juszkiewicz Signed-off-by: Niklas Cassel --- Changes since v1: write the D2H FIS before clearing PxCI. hw/ide/ahci.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index babdd7b458..7269dabbdb 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1254,10 +1254,26 @@ static void handle_reg_h2d_fis(AHCIState *s, int po= rt, case STATE_RUN: if (cmd_fis[15] & ATA_SRST) { s->dev[port].port_state =3D STATE_RESET; + /* + * When setting SRST in the first H2D FIS in the reset seq= uence, + * the device does not send a D2H FIS. Host software thus = has to + * set the "Clear Busy upon R_OK" bit such that PxCI (and = BUSY) + * gets cleared. See AHCI 1.3.1, section 10.4.1 Software R= eset. + */ + if (opts & AHCI_CMD_CLR_BUSY) { + ahci_clear_cmd_issue(ad, slot); + } } break; case STATE_RESET: if (!(cmd_fis[15] & ATA_SRST)) { + /* + * When clearing SRST in the second H2D FIS in the reset + * sequence, the device will send a D2H FIS. See SATA 3.5a= Gold, + * section 11.4 Software reset protocol. + */ + ahci_clear_cmd_issue(ad, slot); + ahci_write_fis_d2h(ad, false); ahci_reset_port(s, port); } break; --=20 2.41.0