[v1] Support discontinuous PMU counters

[PATCH 0/3] Support discontinuous PMU counters

Rob Bradford posted 3 patches 7 months ago

Diff against v2 v3 v4 v5
Download series mbox

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git fetch https://github.com/patchew-project/qemu tags/patchew/20231003125107.34859-1-rbradford@rivosinc.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liweiwei@iscas.ac.cn>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

There is a newer version of this series

target/riscv/cpu.c     |  9 ++++++++-
target/riscv/cpu_cfg.h |  1 +
target/riscv/csr.c     |  5 +++--
target/riscv/pmu.c     | 32 +++++++++++++++++++++-----------
target/riscv/pmu.h     |  3 ++-
5 files changed, 35 insertions(+), 15 deletions(-)

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[PATCH 0/3] Support discontinuous PMU counters

Posted by Rob Bradford 7 months ago

Currently the available PMU counters start at HPM3 and run through to
the number specified by the "pmu-num" property. There is no
requirement in the specification that the available counters be
continously numbered. This series add suppport for specifying a
discountinuous range of counters though a "pmu-mask" property.

Rob Bradford (3):
  target/riscv: Propagate error from PMU setup
  target/riscv: Support discontinuous PMU counters
  target/riscv: Don't assume PMU counters are continuous

 target/riscv/cpu.c     |  9 ++++++++-
 target/riscv/cpu_cfg.h |  1 +
 target/riscv/csr.c     |  5 +++--
 target/riscv/pmu.c     | 32 +++++++++++++++++++++-----------
 target/riscv/pmu.h     |  3 ++-
 5 files changed, 35 insertions(+), 15 deletions(-)

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2.41.0