There are a bunch of RISC-V files that are currently not covered
by the "get_maintainers.pl" script. Add them to the right sections
in MAINTAINERS to fix this problem.
Signed-off-by: Thomas Huth <thuth@redhat.com>
---
MAINTAINERS | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 355b1960ce..1313257180 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -317,8 +317,11 @@ R: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
L: qemu-riscv@nongnu.org
S: Supported
+F: configs/targets/riscv*
+F: docs/system/target-riscv.rst
F: target/riscv/
F: hw/riscv/
+F: hw/intc/riscv*
F: include/hw/riscv/
F: linux-user/host/riscv32/
F: linux-user/host/riscv64/
@@ -330,6 +333,7 @@ L: qemu-riscv@nongnu.org
S: Supported
F: target/riscv/insn_trans/trans_xthead.c.inc
F: target/riscv/xthead*.decode
+F: disas/riscv-xthead*
RISC-V XVentanaCondOps extension
M: Philipp Tomsich <philipp.tomsich@vrull.eu>
@@ -337,6 +341,7 @@ L: qemu-riscv@nongnu.org
S: Maintained
F: target/riscv/XVentanaCondOps.decode
F: target/riscv/insn_trans/trans_xventanacondops.c.inc
+F: disas/riscv-xventana*
RENESAS RX CPUs
R: Yoshinori Sato <ysato@users.sourceforge.jp>
@@ -1518,6 +1523,7 @@ Microchip PolarFire SoC Icicle Kit
M: Bin Meng <bin.meng@windriver.com>
L: qemu-riscv@nongnu.org
S: Supported
+F: docs/system/riscv/microchip-icicle-kit.rst
F: hw/riscv/microchip_pfsoc.c
F: hw/char/mchp_pfsoc_mmuart.c
F: hw/misc/mchp_pfsoc_dmc.c
@@ -1533,6 +1539,7 @@ Shakti C class SoC
M: Vijai Kumar K <vijai@behindbytes.com>
L: qemu-riscv@nongnu.org
S: Supported
+F: docs/system/riscv/shakti-c.rst
F: hw/riscv/shakti_c.c
F: hw/char/shakti_uart.c
F: include/hw/riscv/shakti_c.h
@@ -1544,6 +1551,7 @@ M: Bin Meng <bin.meng@windriver.com>
M: Palmer Dabbelt <palmer@dabbelt.com>
L: qemu-riscv@nongnu.org
S: Supported
+F: docs/system/riscv/sifive_u.rst
F: hw/*/*sifive*.c
F: include/hw/*/*sifive*.h
@@ -3543,7 +3551,7 @@ M: Alistair Francis <Alistair.Francis@wdc.com>
L: qemu-riscv@nongnu.org
S: Maintained
F: tcg/riscv/
-F: disas/riscv.c
+F: disas/riscv.[ch]
S390 TCG target
M: Richard Henderson <richard.henderson@linaro.org>
--
2.41.0
29.09.2023 15:37, Thomas Huth wrote: > There are a bunch of RISC-V files that are currently not covered > by the "get_maintainers.pl" script. Add them to the right sections > in MAINTAINERS to fix this problem. Applied to my trivial-patches tree, thanks! /mjt
On 2023/9/29 20:37, Thomas Huth wrote: > There are a bunch of RISC-V files that are currently not covered > by the "get_maintainers.pl" script. Add them to the right sections > in MAINTAINERS to fix this problem. > > Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Zhiwei > --- > MAINTAINERS | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 355b1960ce..1313257180 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -317,8 +317,11 @@ R: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> > L: qemu-riscv@nongnu.org > S: Supported > +F: configs/targets/riscv* > +F: docs/system/target-riscv.rst > F: target/riscv/ > F: hw/riscv/ > +F: hw/intc/riscv* > F: include/hw/riscv/ > F: linux-user/host/riscv32/ > F: linux-user/host/riscv64/ > @@ -330,6 +333,7 @@ L: qemu-riscv@nongnu.org > S: Supported > F: target/riscv/insn_trans/trans_xthead.c.inc > F: target/riscv/xthead*.decode > +F: disas/riscv-xthead* > > RISC-V XVentanaCondOps extension > M: Philipp Tomsich <philipp.tomsich@vrull.eu> > @@ -337,6 +341,7 @@ L: qemu-riscv@nongnu.org > S: Maintained > F: target/riscv/XVentanaCondOps.decode > F: target/riscv/insn_trans/trans_xventanacondops.c.inc > +F: disas/riscv-xventana* > > RENESAS RX CPUs > R: Yoshinori Sato <ysato@users.sourceforge.jp> > @@ -1518,6 +1523,7 @@ Microchip PolarFire SoC Icicle Kit > M: Bin Meng <bin.meng@windriver.com> > L: qemu-riscv@nongnu.org > S: Supported > +F: docs/system/riscv/microchip-icicle-kit.rst > F: hw/riscv/microchip_pfsoc.c > F: hw/char/mchp_pfsoc_mmuart.c > F: hw/misc/mchp_pfsoc_dmc.c > @@ -1533,6 +1539,7 @@ Shakti C class SoC > M: Vijai Kumar K <vijai@behindbytes.com> > L: qemu-riscv@nongnu.org > S: Supported > +F: docs/system/riscv/shakti-c.rst > F: hw/riscv/shakti_c.c > F: hw/char/shakti_uart.c > F: include/hw/riscv/shakti_c.h > @@ -1544,6 +1551,7 @@ M: Bin Meng <bin.meng@windriver.com> > M: Palmer Dabbelt <palmer@dabbelt.com> > L: qemu-riscv@nongnu.org > S: Supported > +F: docs/system/riscv/sifive_u.rst > F: hw/*/*sifive*.c > F: include/hw/*/*sifive*.h > > @@ -3543,7 +3551,7 @@ M: Alistair Francis <Alistair.Francis@wdc.com> > L: qemu-riscv@nongnu.org > S: Maintained > F: tcg/riscv/ > -F: disas/riscv.c > +F: disas/riscv.[ch] > > S390 TCG target > M: Richard Henderson <richard.henderson@linaro.org>
On Fri, 29 Sept 2023 at 14:37, Thomas Huth <thuth@redhat.com> wrote: > > There are a bunch of RISC-V files that are currently not covered > by the "get_maintainers.pl" script. Add them to the right sections > in MAINTAINERS to fix this problem. > > Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
On 9/29/23 09:37, Thomas Huth wrote: > There are a bunch of RISC-V files that are currently not covered > by the "get_maintainers.pl" script. Add them to the right sections > in MAINTAINERS to fix this problem. > > Signed-off-by: Thomas Huth <thuth@redhat.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > MAINTAINERS | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 355b1960ce..1313257180 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -317,8 +317,11 @@ R: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> > L: qemu-riscv@nongnu.org > S: Supported > +F: configs/targets/riscv* > +F: docs/system/target-riscv.rst > F: target/riscv/ > F: hw/riscv/ > +F: hw/intc/riscv* > F: include/hw/riscv/ > F: linux-user/host/riscv32/ > F: linux-user/host/riscv64/ > @@ -330,6 +333,7 @@ L: qemu-riscv@nongnu.org > S: Supported > F: target/riscv/insn_trans/trans_xthead.c.inc > F: target/riscv/xthead*.decode > +F: disas/riscv-xthead* > > RISC-V XVentanaCondOps extension > M: Philipp Tomsich <philipp.tomsich@vrull.eu> > @@ -337,6 +341,7 @@ L: qemu-riscv@nongnu.org > S: Maintained > F: target/riscv/XVentanaCondOps.decode > F: target/riscv/insn_trans/trans_xventanacondops.c.inc > +F: disas/riscv-xventana* > > RENESAS RX CPUs > R: Yoshinori Sato <ysato@users.sourceforge.jp> > @@ -1518,6 +1523,7 @@ Microchip PolarFire SoC Icicle Kit > M: Bin Meng <bin.meng@windriver.com> > L: qemu-riscv@nongnu.org > S: Supported > +F: docs/system/riscv/microchip-icicle-kit.rst > F: hw/riscv/microchip_pfsoc.c > F: hw/char/mchp_pfsoc_mmuart.c > F: hw/misc/mchp_pfsoc_dmc.c > @@ -1533,6 +1539,7 @@ Shakti C class SoC > M: Vijai Kumar K <vijai@behindbytes.com> > L: qemu-riscv@nongnu.org > S: Supported > +F: docs/system/riscv/shakti-c.rst > F: hw/riscv/shakti_c.c > F: hw/char/shakti_uart.c > F: include/hw/riscv/shakti_c.h > @@ -1544,6 +1551,7 @@ M: Bin Meng <bin.meng@windriver.com> > M: Palmer Dabbelt <palmer@dabbelt.com> > L: qemu-riscv@nongnu.org > S: Supported > +F: docs/system/riscv/sifive_u.rst > F: hw/*/*sifive*.c > F: include/hw/*/*sifive*.h > > @@ -3543,7 +3551,7 @@ M: Alistair Francis <Alistair.Francis@wdc.com> > L: qemu-riscv@nongnu.org > S: Maintained > F: tcg/riscv/ > -F: disas/riscv.c > +F: disas/riscv.[ch] > > S390 TCG target > M: Richard Henderson <richard.henderson@linaro.org>
On Fri, Sep 29, 2023 at 2:37 PM Thomas Huth <thuth@redhat.com> wrote: > > There are a bunch of RISC-V files that are currently not covered > by the "get_maintainers.pl" script. Add them to the right sections > in MAINTAINERS to fix this problem. > > Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Christoph Müllner <christoph.muellner@vrull.eu> Thanks! > > --- > MAINTAINERS | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 355b1960ce..1313257180 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -317,8 +317,11 @@ R: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > R: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> > L: qemu-riscv@nongnu.org > S: Supported > +F: configs/targets/riscv* > +F: docs/system/target-riscv.rst > F: target/riscv/ > F: hw/riscv/ > +F: hw/intc/riscv* > F: include/hw/riscv/ > F: linux-user/host/riscv32/ > F: linux-user/host/riscv64/ > @@ -330,6 +333,7 @@ L: qemu-riscv@nongnu.org > S: Supported > F: target/riscv/insn_trans/trans_xthead.c.inc > F: target/riscv/xthead*.decode > +F: disas/riscv-xthead* > > RISC-V XVentanaCondOps extension > M: Philipp Tomsich <philipp.tomsich@vrull.eu> > @@ -337,6 +341,7 @@ L: qemu-riscv@nongnu.org > S: Maintained > F: target/riscv/XVentanaCondOps.decode > F: target/riscv/insn_trans/trans_xventanacondops.c.inc > +F: disas/riscv-xventana* > > RENESAS RX CPUs > R: Yoshinori Sato <ysato@users.sourceforge.jp> > @@ -1518,6 +1523,7 @@ Microchip PolarFire SoC Icicle Kit > M: Bin Meng <bin.meng@windriver.com> > L: qemu-riscv@nongnu.org > S: Supported > +F: docs/system/riscv/microchip-icicle-kit.rst > F: hw/riscv/microchip_pfsoc.c > F: hw/char/mchp_pfsoc_mmuart.c > F: hw/misc/mchp_pfsoc_dmc.c > @@ -1533,6 +1539,7 @@ Shakti C class SoC > M: Vijai Kumar K <vijai@behindbytes.com> > L: qemu-riscv@nongnu.org > S: Supported > +F: docs/system/riscv/shakti-c.rst > F: hw/riscv/shakti_c.c > F: hw/char/shakti_uart.c > F: include/hw/riscv/shakti_c.h > @@ -1544,6 +1551,7 @@ M: Bin Meng <bin.meng@windriver.com> > M: Palmer Dabbelt <palmer@dabbelt.com> > L: qemu-riscv@nongnu.org > S: Supported > +F: docs/system/riscv/sifive_u.rst > F: hw/*/*sifive*.c > F: include/hw/*/*sifive*.h > > @@ -3543,7 +3551,7 @@ M: Alistair Francis <Alistair.Francis@wdc.com> > L: qemu-riscv@nongnu.org > S: Maintained > F: tcg/riscv/ > -F: disas/riscv.c > +F: disas/riscv.[ch] > > S390 TCG target > M: Richard Henderson <richard.henderson@linaro.org> > -- > 2.41.0 >
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