From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695664716; cv=none; d=zohomail.com; s=zohoarc; b=guKJOQ/NauV3FO9OsJTTCpowgPhweaDgsvNrygfeDFca2gjVqyiqZREgKaRiPzgijtLiIO7GnF3CPzypebVf5UmsaqD3XM2J9TDoIwrP5QUramb2gM4NB8hkxnTAwlA29rDgudHS0Orr9vuA5rnxuD52/51quK2Ymj00vJ+kJjs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695664716; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=efnC/xB6Eo4AfTGFoE688TAzm2MA5EbrVOErI/CML58=; b=jvykfYEh2PX9kyZ3JvJ30t9NbuurmBowrsIaI5oIrK8mlS827wcZL+HAPGPDaZuF2CqN4foChvRKB6oZYBI0K9AeWH6LPrr1gH/gYDq+RLZrBX/NRUUZgewAlQHE1CQ5J7owIwWczcED6dgdu7dPn/9QF0ayDBkkaIgcGzhhPKg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695664716173332.8693226503617; Mon, 25 Sep 2023 10:58:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qkppj-0000YH-Ci; Mon, 25 Sep 2023 13:57:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkppi-0000Y2-8K for qemu-devel@nongnu.org; Mon, 25 Sep 2023 13:57:22 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qkppg-00029w-B8 for qemu-devel@nongnu.org; Mon, 25 Sep 2023 13:57:22 -0400 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-578d78ffdbcso4029798a12.2 for ; Mon, 25 Sep 2023 10:57:19 -0700 (PDT) Received: from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.57.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:57:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664639; x=1696269439; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=efnC/xB6Eo4AfTGFoE688TAzm2MA5EbrVOErI/CML58=; b=cK/MmU+acuRRaY1emCkuhr0qqwtV0fv8JNadHgckBvKgsFepGTTj7Wurrrg8s3YVCK J2ETmJn53jX/Rd4+xIlB+GJGybv2sciy6iT7LrCXDRbYqiqJ2+viTZsFGoZZOjXxzYFC QAAlwgN13CaGEiv2BsQWYjJkvp4+Yi2O7vI/c75foynoPuMJj/BV+ITLI7qg55e729pq aqG0/gIk66xwEA9TRPsfI0HF6LzRiUBfMMhRL0fDI+xV7HLgFfD2MWoiBnoQjXytE5L6 gAXFV1cWOOiv1dnTxGq2g5V51OcNBuxXeWUBOCvONL9X6I3KyzxmsKu4tWBgxH/QeD6h Lmxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664639; x=1696269439; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=efnC/xB6Eo4AfTGFoE688TAzm2MA5EbrVOErI/CML58=; b=NTjltbCAa1PdAbr+vXvK2s6StXHmvhqo8qCXPIf2fvBaaVZEfXmszA9ecbbYi7Hty0 eLCG1Q4EfZKusH1ngSDXBn9gcnwXcMYkgnND7oM9BQxOHeLr8jqt4zzKmOoJPrPc+rO6 WfU7BL2Nk2jb8V6I+8ZM23GcMiG8I4x80vsZkMK3nNbuBn/2RkS8GekmV/FTeOq6kL0S 0F/tXqpQEWFBjNVEVmAYInedGt1t5NQFe1LIVsqDCJx6sHQzYBwgyljrjZ606ykbHtxF by3WDpt36yfM+IDGzJhiTvEL/Z+Hm6iTj3nwj5ZTqpyScB3j+NUI7wZXaFQKFvHIRudh GanQ== X-Gm-Message-State: AOJu0Yyzv7aLYzb/E+kfTqZcBu90OsOkX5dKaWAAqBrwnv6yoWr6RxX1 X21U+0ZaNB94i6y3pS1FRG64hEJyJyR203J5fAY= X-Google-Smtp-Source: AGHT+IGT4ph7eP0udB366CTv2SS19OgjY0hCXiJhH0IWXnrENeb2i20LAz3QTBMwLhJYm1tBG9DdHw== X-Received: by 2002:a17:90b:1b51:b0:26d:49c8:78aa with SMTP id nv17-20020a17090b1b5100b0026d49c878aamr5499113pjb.32.1695664638684; Mon, 25 Sep 2023 10:57:18 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v4 01/19] target/riscv: introduce TCG AccelCPUClass Date: Mon, 25 Sep 2023 14:56:51 -0300 Message-ID: <20230925175709.35696-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664716809100001 Content-Type: text/plain; charset="utf-8" target/riscv/cpu.c needs to handle all possible accelerators (TCG and KVM at this moment) during both init() and realize() time. This forces us to resort to a lot of "if tcg" and "if kvm" throughout the code, which isn't wrong, but can get cluttered over time. Splitting acceleration specific code from cpu.c to its own file will help to declutter the existing code and it will also make it easier to support KVM/TCG only builds in the future. We'll start by adding a new subdir called 'tcg' and a new file called 'tcg-cpu.c'. This file will be used to introduce a new accelerator class for TCG acceleration in RISC-V, allowing us to center all TCG exclusive code in its file instead of using 'cpu.c' for everything. This design is inpired by the work Claudio Fontana did in x86 a few years ago in commit f5cc5a5c1 ("i386: split cpu accelerators from cpu.c, using AccelCPUClass"). To avoid moving too much code at once we'll start by adding the new file and TCG AccelCPUClass declaration. The 'class_init' from the accel class will init 'tcg_ops', relieving the common riscv_cpu_class_init() from doing it. 'riscv_tcg_ops' is being exported from 'cpu.c' for now to avoid having to deal with moving code and files around right now. We'll focus on decoupling the realize() logic first. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +--- target/riscv/cpu.h | 4 +++ target/riscv/meson.build | 2 ++ target/riscv/tcg/meson.build | 2 ++ target/riscv/tcg/tcg-cpu.c | 58 ++++++++++++++++++++++++++++++++++++ 5 files changed, 67 insertions(+), 4 deletions(-) create mode 100644 target/riscv/tcg/meson.build create mode 100644 target/riscv/tcg/tcg-cpu.c diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2644638b11..e72c49c881 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2288,9 +2288,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops =3D= { }; #endif =20 -#include "hw/core/tcg-cpu-ops.h" - -static const struct TCGCPUOps riscv_tcg_ops =3D { +const struct TCGCPUOps riscv_tcg_ops =3D { .initialize =3D riscv_translate_init, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, .restore_state_to_opc =3D riscv_restore_state_to_opc, @@ -2449,7 +2447,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; - cc->tcg_ops =3D &riscv_tcg_ops; =20 object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, cpu_set_mvendorid, NULL, NULL); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7d6cfb07ea..16a2dfa8c7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -707,6 +707,10 @@ enum riscv_pmu_event_idx { RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS =3D 0x10021, }; =20 +/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */ +#include "hw/core/tcg-cpu-ops.h" +extern const struct TCGCPUOps riscv_tcg_ops; + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; =20 diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 660078bda1..f0486183fa 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -38,5 +38,7 @@ riscv_system_ss.add(files( 'riscv-qmp-cmds.c', )) =20 +subdir('tcg') + target_arch +=3D {'riscv': riscv_ss} target_softmmu_arch +=3D {'riscv': riscv_system_ss} diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build new file mode 100644 index 0000000000..061df3d74a --- /dev/null +++ b/target/riscv/tcg/meson.build @@ -0,0 +1,2 @@ +riscv_ss.add(when: 'CONFIG_TCG', if_true: files( + 'tcg-cpu.c')) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c new file mode 100644 index 0000000000..795a8f06b2 --- /dev/null +++ b/target/riscv/tcg/tcg-cpu.c @@ -0,0 +1,58 @@ +/* + * riscv TCG cpu class initialization + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2017-2018 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "qemu/accel.h" +#include "hw/core/accel-cpu.h" + +static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) +{ + /* + * All cpus use the same set of operations. + * riscv_tcg_ops is being imported from cpu.c for now. + */ + cc->tcg_ops =3D &riscv_tcg_ops; +} + +static void tcg_cpu_class_init(CPUClass *cc) +{ + cc->init_accel_cpu =3D tcg_cpu_init_ops; +} + +static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_class_init =3D tcg_cpu_class_init; +} + +static const TypeInfo tcg_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("tcg"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D tcg_cpu_accel_class_init, + .abstract =3D true, +}; + +static void tcg_cpu_accel_register_types(void) +{ + type_register_static(&tcg_cpu_accel_type_info); +} +type_init(tcg_cpu_accel_register_types); --=20 2.41.0 From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695664734; cv=none; d=zohomail.com; s=zohoarc; b=Y844/+gFXntLNicoGegNd18XOWVHYCXZcB72+zOeRzK4xv02zfWp/u5KQQdGZtDEoudGSGOETC7ub/X9xs8bEz2pCqkEHPAhjvtL3xpze/vjTOkfNmhotclFRFWsF3lOhP4gmWrc7y2Ei114LjAeWivyocssa7JLd5bcK9C2i5Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695664734; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vvYfHSfqGjzJzjhxgz67b1ioP9Sb4vSPyH/KcYL/z1w=; b=Rrg0B1VHlyDa83aLSXWz+Sg/2qi3lNRINTCWxwetsOcF5k3K3l+PmN/UHg9SBd+E94NKLvBCFKIkx1xxXIyNy2lExI+OE8teUzl7QKedEowFWqSmK4TQzEGtybFvWgRbfFao08fcrkkhlwlDFZgs8J+YcYWIJmtpaWV8gnuA1DA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695664734469518.1618241648083; Mon, 25 Sep 2023 10:58:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qkppm-0000ZP-En; Mon, 25 Sep 2023 13:57:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkppl-0000Yu-EW for qemu-devel@nongnu.org; Mon, 25 Sep 2023 13:57:25 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qkppj-0002AG-Bv for qemu-devel@nongnu.org; Mon, 25 Sep 2023 13:57:25 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1c3f97f2239so62327675ad.0 for ; Mon, 25 Sep 2023 10:57:22 -0700 (PDT) Received: from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.57.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:57:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664642; x=1696269442; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vvYfHSfqGjzJzjhxgz67b1ioP9Sb4vSPyH/KcYL/z1w=; b=cMmDwQTzcmlYT/7N/38Zk9ImfcbJQG6kB4Kf5JqpF5N1gAAD3DI3yA8l3Gm8ii7UH1 vBlx8nzKE1sXOPhfOpPMjS+VAw1NZQLF5ekg+WB4Zb8cp1nNbtxbqoVWoLFtNkNP8OHh wsUqku3fD2uk3Q+Cu6gq/QCtvK+uzz2JM7AAoK2ZsYjJJ2nW1LHHPjNDCUmdekDGLvgB Ds2ynXl3slWvGvi66R/swCkmHi+ar4gCsS3Lxqw7xucWU7UERbgeE0OdssbFpZ4zDU88 HXefesNmqcROzD7I7SGC4rL+clRk5ul0F2fRdBCLy3EOazHhpMjaakzdCyCJFrHIqT6M T/Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664642; x=1696269442; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vvYfHSfqGjzJzjhxgz67b1ioP9Sb4vSPyH/KcYL/z1w=; b=a3x48B9B3zrrz5VjD1TjbcoJwHa5rfeu7dstnVybGHX+Bwt2guoo36Iig9MMdYiG6M DlQMqvW5agun9ak/H78nxLSh5KtAOeXzhmixHFjoEbxZLMh52UNPMFCBMCw5sav/meEI sHfZ/o0xGUH64y5dh/Hq9v/VYGyBZ2nomgZxBmxX3I60H0ISKTQu4QAJfLNU8RR49Nv5 aIncrIJ2kQpaH+qdby1hcY8Q8izwWEt8ztseEWAKw+RNnItVoaYGGO/sFMuvAgbGN4TI BYWaFjk0aS1MKfOJFa/sOWRAFbZ6j4keLItyZ+O97OfBnsX6k6I/GyqDKW9kilmscfDo VS5A== X-Gm-Message-State: AOJu0YzEG7KW9nHIvbRw+pE7nG2SmFZ0dMNYMA3Yd9BcTJ23EEPUZQb4 ZRDCtSdCMnPzO5h/GJLhXfzlfOzvyDDfNC3aPX4= X-Google-Smtp-Source: AGHT+IHIkbqVGfWdHdE1gZ4HHr8HSre88z+m9EBEUs0mUeyckAIsza9XHDf7eGTNtstii1XOSIPxnA== X-Received: by 2002:a17:90b:3588:b0:274:6cc9:ec69 with SMTP id mm8-20020a17090b358800b002746cc9ec69mr6057606pjb.49.1695664641688; Mon, 25 Sep 2023 10:57:21 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v4 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn() Date: Mon, 25 Sep 2023 14:56:52 -0300 Message-ID: <20230925175709.35696-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664736016100001 Content-Type: text/plain; charset="utf-8" riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different realize() path during the common riscv_cpu_realize(), making it a good choice to start moving TCG exclusive code to tcg-cpu.c. Rename it to tcg_cpu_realizefn() and assign it as a implementation of accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar approach with KVM in the near future. riscv_cpu_validate_set_extensions() is too big and with too many dependencies to be moved in this same patch. We'll do that next. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 128 ----------------------------------- target/riscv/tcg/tcg-cpu.c | 133 +++++++++++++++++++++++++++++++++++++ 2 files changed, 133 insertions(+), 128 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e72c49c881..030629294f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -23,9 +23,7 @@ #include "qemu/log.h" #include "cpu.h" #include "cpu_vendorid.h" -#include "pmu.h" #include "internals.h" -#include "time_helper.h" #include "exec/exec-all.h" #include "qapi/error.h" #include "qapi/visitor.h" @@ -1064,29 +1062,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env,= RISCVCPUConfig *cfg, } } =20 -static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) -{ - CPURISCVState *env =3D &cpu->env; - int priv_version =3D -1; - - if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { - priv_version =3D PRIV_VERSION_1_12_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { - priv_version =3D PRIV_VERSION_1_11_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { - priv_version =3D PRIV_VERSION_1_10_0; - } else { - error_setg(errp, - "Unsupported privilege spec version '%s'", - cpu->cfg.priv_spec); - return; - } - - env->priv_ver =3D priv_version; - } -} - static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) { CPURISCVState *env =3D &cpu->env; @@ -1111,33 +1086,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RIS= CVCPU *cpu) } } =20 -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) -{ - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); - CPUClass *cc =3D CPU_CLASS(mcc); - CPURISCVState *env =3D &cpu->env; - - /* Validate that MISA_MXL is set properly. */ - switch (env->misa_mxl_max) { -#ifdef TARGET_RISCV64 - case MXL_RV64: - case MXL_RV128: - cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; - break; -#endif - case MXL_RV32: - cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; - break; - default: - g_assert_not_reached(); - } - - if (env->misa_mxl_max !=3D env->misa_mxl) { - error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); - return; - } -} - /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -1511,74 +1459,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cp= u, Error **errp) #endif } =20 -static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) -{ - if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { - error_setg(errp, "H extension requires priv spec 1.12.0"); - return; - } -} - -static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) -{ - RISCVCPU *cpu =3D RISCV_CPU(dev); - CPURISCVState *env =3D &cpu->env; - Error *local_err =3D NULL; - - if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) { - error_setg(errp, "'host' CPU is not compatible with TCG accelerati= on"); - return; - } - - riscv_cpu_validate_misa_mxl(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - - riscv_cpu_validate_priv_spec(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - - riscv_cpu_validate_misa_priv(env, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - - if (cpu->cfg.epmp && !cpu->cfg.pmp) { - /* - * Enhanced PMP should only be available - * on harts with PMP support - */ - error_setg(errp, "Invalid configuration: EPMP requires PMP support= "); - return; - } - - riscv_cpu_validate_set_extensions(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - -#ifndef CONFIG_USER_ONLY - CPU(dev)->tcg_cflags |=3D CF_PCREL; - - if (cpu->cfg.ext_sstc) { - riscv_timer_init(cpu); - } - - if (cpu->cfg.pmu_num) { - if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpm= f) { - cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, - riscv_pmu_timer_cb, cpu); - } - } -#endif -} - static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -1597,14 +1477,6 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 - if (tcg_enabled()) { - riscv_cpu_realize_tcg(dev, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - } - riscv_cpu_finalize_features(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 795a8f06b2..5904cf7354 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -18,10 +18,142 @@ */ =20 #include "qemu/osdep.h" +#include "exec/exec-all.h" #include "cpu.h" +#include "pmu.h" +#include "time_helper.h" +#include "qapi/error.h" #include "qemu/accel.h" #include "hw/core/accel-cpu.h" =20 + +static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) +{ + if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { + error_setg(errp, "H extension requires priv spec 1.12.0"); + return; + } +} + +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); + CPUClass *cc =3D CPU_CLASS(mcc); + CPURISCVState *env =3D &cpu->env; + + /* Validate that MISA_MXL is set properly. */ + switch (env->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + case MXL_RV128: + cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; + break; +#endif + case MXL_RV32: + cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; + break; + default: + g_assert_not_reached(); + } + + if (env->misa_mxl_max !=3D env->misa_mxl) { + error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); + return; + } +} + +static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + int priv_version =3D -1; + + if (cpu->cfg.priv_spec) { + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { + priv_version =3D PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { + priv_version =3D PRIV_VERSION_1_11_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { + priv_version =3D PRIV_VERSION_1_10_0; + } else { + error_setg(errp, + "Unsupported privilege spec version '%s'", + cpu->cfg.priv_spec); + return; + } + + env->priv_ver =3D priv_version; + } +} + +/* + * We'll get here via the following path: + * + * riscv_cpu_realize() + * -> cpu_exec_realizefn() + * -> tcg_cpu_realizefn() (via accel_cpu_realizefn()) + */ +static bool tcg_cpu_realizefn(CPUState *cs, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + Error *local_err =3D NULL; + + if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { + error_setg(errp, "'host' CPU is not compatible with TCG accelerati= on"); + return false; + } + + riscv_cpu_validate_misa_mxl(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return false; + } + + riscv_cpu_validate_priv_spec(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return false; + } + + riscv_cpu_validate_misa_priv(env, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return false; + } + + if (cpu->cfg.epmp && !cpu->cfg.pmp) { + /* + * Enhanced PMP should only be available + * on harts with PMP support + */ + error_setg(errp, "Invalid configuration: EPMP requires PMP support= "); + return false; + } + + riscv_cpu_validate_set_extensions(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return false; + } + +#ifndef CONFIG_USER_ONLY + CPU(cs)->tcg_cflags |=3D CF_PCREL; + + if (cpu->cfg.ext_sstc) { + riscv_timer_init(cpu); + } + + if (cpu->cfg.pmu_num) { + if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpm= f) { + cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + riscv_pmu_timer_cb, cpu); + } + } +#endif + + return true; +} + static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) { /* @@ -41,6 +173,7 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, vo= id *data) AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); =20 acc->cpu_class_init =3D tcg_cpu_class_init; + acc->cpu_realizefn =3D tcg_cpu_realizefn; } =20 static const TypeInfo tcg_cpu_accel_type_info =3D { --=20 2.41.0 From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.57.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:57:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664645; x=1696269445; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kVrvtyYjxAqD1QhO+2lqCz4dBLw0mw428mjf5hanvQ8=; b=hrFGdtbtG7bDSU+0P3pocRdRcYNYub/pJuQ1bB/F91SlTWT3865s72M4fUEAPQ1yng Br1F+ZUwDp+qlvqdBmNDOTEtui5251Hykf7AS7qy+/LjxtjP9EtuSZzzH2smZhgTC3aq HHqSvqJXUj+DAKgWl7DzrVDpZwq+B5mKrYaUEecFKdN8akTeoeSxhhHo77CLSCoEeiFA L2LfpVnXnEfStJJIekdlYxvq2+PrnQh9nHWN2Na6i3ZT83ZS2iDAMKjFBx21CK9U+RzP Rhhh10IRKpuHQh85RIhogpdBqq1KMHeKBA8PChs7TZktGT6mbh4i5LN3/cEX9rA6Y1t6 972A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664645; x=1696269445; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kVrvtyYjxAqD1QhO+2lqCz4dBLw0mw428mjf5hanvQ8=; b=DTjxb+HDrBUarCHfJ/Ef03AyAvCNcobvtONbFGLFU9gXUxSfq1LgczPjtm/xhfRPSz h8ROiQdBJYnoITXZcXMpBMaI0EbUFfcFhmuvKqCNh4K0Q1gmHibiODc7kRxg366tF59h WqJEVnhZdZlC2jQFGnZWkqLXrPFc/Q7O3R0FVtnBbeMbvAnkGNbWKkp5dIZbgmyGORjr XwvHqIAhitiy8oWddPMkLnI1R8QHw8+1LxA+ChMcI5v7PQLS8PW8L6EBG8Ln9F7v0tKB UV3I9ymS2VhK0tK+GKzs+dVA1ILJNF15gJBPidWEXO6ERFTpbgeu4yqYg5Cw1zy6XdGZ g/vg== X-Gm-Message-State: AOJu0YyU/lULa9ylfFtF8WhDxfRZtXJfJgnWjSWOk7f3xRcz1DJgkxq3 INmBNdPR3c8/+0QWT7KkNbhJz2cqto23xq8l5qE= X-Google-Smtp-Source: AGHT+IEFO9dVvgXpe2qGZGHdkxVsbos9X30/mD2RAusyul6eIYx/M7Y7eCxXtqeUcUDUBvfzZOHRfA== X-Received: by 2002:a17:90a:540d:b0:26b:5461:8dd5 with SMTP id z13-20020a17090a540d00b0026b54618dd5mr4556926pjh.42.1695664644855; Mon, 25 Sep 2023 10:57:24 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v4 03/19] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c Date: Mon, 25 Sep 2023 14:56:53 -0300 Message-ID: <20230925175709.35696-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664750097100006 Content-Type: text/plain; charset="utf-8" This function is the core of the RISC-V validations for TCG CPUs, and it has a lot going on. Functions in cpu.c were made public to allow them to be used by the KVM accelerator class later on. 'cpu_cfg_ext_get_min_version()' is notably hard to move it to another file due to its dependency with isa_edata_arr[] array, thus make it public and use it as is for now. riscv_cpu_validate_set_extensions() is kept public because it's used by csr.c in write_misa(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 361 +------------------------------------ target/riscv/cpu.h | 8 +- target/riscv/csr.c | 1 + target/riscv/tcg/tcg-cpu.c | 357 ++++++++++++++++++++++++++++++++++++ target/riscv/tcg/tcg-cpu.h | 27 +++ 5 files changed, 397 insertions(+), 357 deletions(-) create mode 100644 target/riscv/tcg/tcg-cpu.h diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 030629294f..7215a29324 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -163,22 +163,21 @@ static const struct isa_ext_data isa_edata_arr[] =3D { /* Hash that stores user set extensions */ static GHashTable *multi_ext_user_opts; =20 -static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) +bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) { bool *ext_enabled =3D (void *)&cpu->cfg + ext_offset; =20 return *ext_enabled; } =20 -static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, - bool en) +void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en) { bool *ext_enabled =3D (void *)&cpu->cfg + ext_offset; =20 *ext_enabled =3D en; } =20 -static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) +int cpu_cfg_ext_get_min_version(uint32_t ext_offset) { int i; =20 @@ -193,38 +192,12 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_o= ffset) g_assert_not_reached(); } =20 -static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) +bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) { return g_hash_table_contains(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset)); } =20 -static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, - bool value) -{ - CPURISCVState *env =3D &cpu->env; - bool prev_val =3D isa_ext_is_enabled(cpu, ext_offset); - int min_version; - - if (prev_val =3D=3D value) { - return; - } - - if (cpu_cfg_ext_is_user_set(ext_offset)) { - return; - } - - if (value && env->priv_ver !=3D PRIV_VERSION_LATEST) { - /* Do not enable it if priv_ver is older than min_version */ - min_version =3D cpu_cfg_ext_get_min_version(ext_offset); - if (env->priv_ver < min_version) { - return; - } - } - - isa_ext_update_enabled(cpu, ext_offset, value); -} - const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -1023,46 +996,7 @@ static void riscv_cpu_disas_set_info(CPUState *s, dis= assemble_info *info) } } =20 -static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, - Error **errp) -{ - if (!is_power_of_2(cfg->vlen)) { - error_setg(errp, "Vector extension VLEN must be power of 2"); - return; - } - if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { - error_setg(errp, - "Vector extension implementation only supports VLEN " - "in the range [128, %d]", RV_VLEN_MAX); - return; - } - if (!is_power_of_2(cfg->elen)) { - error_setg(errp, "Vector extension ELEN must be power of 2"); - return; - } - if (cfg->elen > 64 || cfg->elen < 8) { - error_setg(errp, - "Vector extension implementation only supports ELEN " - "in the range [8, 64]"); - return; - } - if (cfg->vext_spec) { - if (!g_strcmp0(cfg->vext_spec, "v1.0")) { - env->vext_ver =3D VEXT_VERSION_1_00_0; - } else { - error_setg(errp, "Unsupported vector spec version '%s'", - cfg->vext_spec); - return; - } - } else if (env->vext_ver =3D=3D 0) { - qemu_log("vector version is not specified, " - "use the default value v1.0\n"); - - env->vext_ver =3D VEXT_VERSION_1_00_0; - } -} - -static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) +void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) { CPURISCVState *env =3D &cpu->env; int i; @@ -1086,291 +1020,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RI= SCVCPU *cpu) } } =20 -/* - * Check consistency between chosen extensions while setting - * cpu->cfg accordingly. - */ -void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) -{ - CPURISCVState *env =3D &cpu->env; - Error *local_err =3D NULL; - - /* Do some ISA extension error checking */ - if (riscv_has_ext(env, RVG) && - !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && - riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && - riscv_has_ext(env, RVD) && - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { - - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) && - !cpu->cfg.ext_icsr) { - error_setg(errp, "RVG requires Zicsr but user set Zicsr to fal= se"); - return; - } - - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) && - !cpu->cfg.ext_ifencei) { - error_setg(errp, "RVG requires Zifencei but user set " - "Zifencei to false"); - return; - } - - warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true); - - env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; - env->misa_ext_mask |=3D RVI | RVM | RVA | RVF | RVD; - } - - if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { - error_setg(errp, - "I and E extensions are incompatible"); - return; - } - - if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { - error_setg(errp, - "Either I or E extension must be set"); - return; - } - - if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { - error_setg(errp, - "Setting S extension without U extension is illegal"); - return; - } - - if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { - error_setg(errp, - "H depends on an I base integer ISA with 32 x registers= "); - return; - } - - if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { - error_setg(errp, "H extension implicitly requires S-mode"); - return; - } - - if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { - error_setg(errp, "F extension requires Zicsr"); - return; - } - - if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { - error_setg(errp, "Zawrs extension requires A extension"); - return; - } - - if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { - error_setg(errp, "Zfa extension requires F extension"); - return; - } - - if (cpu->cfg.ext_zfh) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true); - } - - if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { - error_setg(errp, "Zfh/Zfhmin extensions require F extension"); - return; - } - - if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { - error_setg(errp, "Zfbfmin extension depends on F extension"); - return; - } - - if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { - error_setg(errp, "D extension requires F extension"); - return; - } - - if (riscv_has_ext(env, RVV)) { - riscv_cpu_validate_v(env, &cpu->cfg, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - - /* The V vector extension depends on the Zve64d extension */ - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true); - } - - /* The Zve64d extension depends on the Zve64f extension */ - if (cpu->cfg.ext_zve64d) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); - } - - /* The Zve64f extension depends on the Zve32f extension */ - if (cpu->cfg.ext_zve64f) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); - } - - if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { - error_setg(errp, "Zve64d/V extensions require D extension"); - return; - } - - if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { - error_setg(errp, "Zve32f/Zve64f extensions require F extension"); - return; - } - - if (cpu->cfg.ext_zvfh) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true); - } - - if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { - error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension= "); - return; - } - - if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { - error_setg(errp, "Zvfh extensions requires Zfhmin extension"); - return; - } - - if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) { - error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension"= ); - return; - } - - if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { - error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); - return; - } - - if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { - error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension= "); - return; - } - - /* Set the ISA extensions, checks should have happened above */ - if (cpu->cfg.ext_zhinx) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - } - - if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfi= nx) { - error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); - return; - } - - if (cpu->cfg.ext_zfinx) { - if (!cpu->cfg.ext_icsr) { - error_setg(errp, "Zfinx extension requires Zicsr"); - return; - } - if (riscv_has_ext(env, RVF)) { - error_setg(errp, - "Zfinx cannot be supported together with F extensio= n"); - return; - } - } - - if (cpu->cfg.ext_zce) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); - if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); - } - } - - /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ - if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); - } - if (riscv_has_ext(env, RVD)) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); - } - } - - if (env->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { - error_setg(errp, "Zcf extension is only relevant to RV32"); - return; - } - - if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { - error_setg(errp, "Zcf extension requires F extension"); - return; - } - - if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { - error_setg(errp, "Zcd extension requires D extension"); - return; - } - - if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || - cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { - error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " - "extension"); - return; - } - - if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { - error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " - "Zcd extension"); - return; - } - - if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { - error_setg(errp, "Zcmt extension requires Zicsr extension"); - return; - } - - /* - * In principle Zve*x would also suffice here, were they supported - * in qemu - */ - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || - cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh)= && - !cpu->cfg.ext_zve32f) { - error_setg(errp, - "Vector crypto extensions require V or Zve* extensions"= ); - return; - } - - if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f= ) { - error_setg( - errp, - "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions= "); - return; - } - - if (cpu->cfg.ext_zk) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); - } - - if (cpu->cfg.ext_zkn) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); - } - - if (cpu->cfg.ext_zks) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); - } - - /* - * Disable isa extensions based on priv spec after we - * validated and set everything we need. - */ - riscv_cpu_disable_priv_spec_isa_exts(cpu); -} - #ifndef CONFIG_USER_ONLY static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 16a2dfa8c7..409d198635 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -445,7 +445,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); -void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); =20 #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index @@ -711,6 +710,13 @@ enum riscv_pmu_event_idx { #include "hw/core/tcg-cpu-ops.h" extern const struct TCGCPUOps riscv_tcg_ops; =20 +/* used by tcg/tcg-cpu.c*/ +void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); +bool cpu_cfg_ext_is_user_set(uint32_t ext_offset); +bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); +int cpu_cfg_ext_get_min_version(uint32_t ext_offset); +void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 85a31dc420..4b4ab56c40 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "qemu/timer.h" #include "cpu.h" +#include "tcg/tcg-cpu.h" #include "pmu.h" #include "time_helper.h" #include "exec/exec-all.h" diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 5904cf7354..47c89fd554 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -19,14 +19,43 @@ =20 #include "qemu/osdep.h" #include "exec/exec-all.h" +#include "tcg-cpu.h" #include "cpu.h" #include "pmu.h" #include "time_helper.h" #include "qapi/error.h" #include "qemu/accel.h" +#include "qemu/error-report.h" +#include "qemu/log.h" #include "hw/core/accel-cpu.h" =20 =20 +static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, + bool value) +{ + CPURISCVState *env =3D &cpu->env; + bool prev_val =3D isa_ext_is_enabled(cpu, ext_offset); + int min_version; + + if (prev_val =3D=3D value) { + return; + } + + if (cpu_cfg_ext_is_user_set(ext_offset)) { + return; + } + + if (value && env->priv_ver !=3D PRIV_VERSION_LATEST) { + /* Do not enable it if priv_ver is older than min_version */ + min_version =3D cpu_cfg_ext_get_min_version(ext_offset); + if (env->priv_ver < min_version) { + return; + } + } + + isa_ext_update_enabled(cpu, ext_offset, value); +} + static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) { if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { @@ -85,6 +114,334 @@ static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu= , Error **errp) } } =20 +static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, + Error **errp) +{ + if (!is_power_of_2(cfg->vlen)) { + error_setg(errp, "Vector extension VLEN must be power of 2"); + return; + } + + if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLEN " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + + if (!is_power_of_2(cfg->elen)) { + error_setg(errp, "Vector extension ELEN must be power of 2"); + return; + } + + if (cfg->elen > 64 || cfg->elen < 8) { + error_setg(errp, + "Vector extension implementation only supports ELEN " + "in the range [8, 64]"); + return; + } + + if (cfg->vext_spec) { + if (!g_strcmp0(cfg->vext_spec, "v1.0")) { + env->vext_ver =3D VEXT_VERSION_1_00_0; + } else { + error_setg(errp, "Unsupported vector spec version '%s'", + cfg->vext_spec); + return; + } + } else if (env->vext_ver =3D=3D 0) { + qemu_log("vector version is not specified, " + "use the default value v1.0\n"); + + env->vext_ver =3D VEXT_VERSION_1_00_0; + } +} + +/* + * Check consistency between chosen extensions while setting + * cpu->cfg accordingly. + */ +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + Error *local_err =3D NULL; + + /* Do some ISA extension error checking */ + if (riscv_has_ext(env, RVG) && + !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && + riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && + riscv_has_ext(env, RVD) && + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { + + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) && + !cpu->cfg.ext_icsr) { + error_setg(errp, "RVG requires Zicsr but user set Zicsr to fal= se"); + return; + } + + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) && + !cpu->cfg.ext_ifencei) { + error_setg(errp, "RVG requires Zifencei but user set " + "Zifencei to false"); + return; + } + + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true); + + env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; + env->misa_ext_mask |=3D RVI | RVM | RVA | RVF | RVD; + } + + if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { + error_setg(errp, + "I and E extensions are incompatible"); + return; + } + + if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { + error_setg(errp, + "Either I or E extension must be set"); + return; + } + + if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { + error_setg(errp, + "Setting S extension without U extension is illegal"); + return; + } + + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { + error_setg(errp, + "H depends on an I base integer ISA with 32 x registers= "); + return; + } + + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { + error_setg(errp, "H extension implicitly requires S-mode"); + return; + } + + if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { + error_setg(errp, "F extension requires Zicsr"); + return; + } + + if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { + error_setg(errp, "Zawrs extension requires A extension"); + return; + } + + if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { + error_setg(errp, "Zfa extension requires F extension"); + return; + } + + if (cpu->cfg.ext_zfh) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true); + } + + if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { + error_setg(errp, "Zfh/Zfhmin extensions require F extension"); + return; + } + + if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { + error_setg(errp, "Zfbfmin extension depends on F extension"); + return; + } + + if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { + error_setg(errp, "D extension requires F extension"); + return; + } + + if (riscv_has_ext(env, RVV)) { + riscv_cpu_validate_v(env, &cpu->cfg, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + + /* The V vector extension depends on the Zve64d extension */ + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true); + } + + /* The Zve64d extension depends on the Zve64f extension */ + if (cpu->cfg.ext_zve64d) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); + } + + /* The Zve64f extension depends on the Zve32f extension */ + if (cpu->cfg.ext_zve64f) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); + } + + if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { + error_setg(errp, "Zve64d/V extensions require D extension"); + return; + } + + if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { + error_setg(errp, "Zve32f/Zve64f extensions require F extension"); + return; + } + + if (cpu->cfg.ext_zvfh) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true); + } + + if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension= "); + return; + } + + if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { + error_setg(errp, "Zvfh extensions requires Zfhmin extension"); + return; + } + + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) { + error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension"= ); + return; + } + + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); + return; + } + + if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { + error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension= "); + return; + } + + /* Set the ISA extensions, checks should have happened above */ + if (cpu->cfg.ext_zhinx) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + } + + if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfi= nx) { + error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); + return; + } + + if (cpu->cfg.ext_zfinx) { + if (!cpu->cfg.ext_icsr) { + error_setg(errp, "Zfinx extension requires Zicsr"); + return; + } + if (riscv_has_ext(env, RVF)) { + error_setg(errp, + "Zfinx cannot be supported together with F extensio= n"); + return; + } + } + + if (cpu->cfg.ext_zce) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); + if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); + } + } + + /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ + if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); + } + if (riscv_has_ext(env, RVD)) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); + } + } + + if (env->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension is only relevant to RV32"); + return; + } + + if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension requires F extension"); + return; + } + + if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { + error_setg(errp, "Zcd extension requires D extension"); + return; + } + + if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || + cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { + error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " + "extension"); + return; + } + + if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { + error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " + "Zcd extension"); + return; + } + + if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { + error_setg(errp, "Zcmt extension requires Zicsr extension"); + return; + } + + /* + * In principle Zve*x would also suffice here, were they supported + * in qemu + */ + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || + cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh)= && + !cpu->cfg.ext_zve32f) { + error_setg(errp, + "Vector crypto extensions require V or Zve* extensions"= ); + return; + } + + if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f= ) { + error_setg( + errp, + "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions= "); + return; + } + + if (cpu->cfg.ext_zk) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); + } + + if (cpu->cfg.ext_zkn) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); + } + + if (cpu->cfg.ext_zks) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); + } + + /* + * Disable isa extensions based on priv spec after we + * validated and set everything we need. + */ + riscv_cpu_disable_priv_spec_isa_exts(cpu); +} + /* * We'll get here via the following path: * diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h new file mode 100644 index 0000000000..630184759d --- /dev/null +++ b/target/riscv/tcg/tcg-cpu.h @@ -0,0 +1,27 @@ +/* + * riscv TCG cpu class initialization + * + * Copyright (c) 2023 Ventana Micro Systems Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef RISCV_TCG_CPU_H +#define RISCV_TCG_CPU_H + +#include "cpu.h" + +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); + +#endif --=20 2.41.0 From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695664849; cv=none; d=zohomail.com; s=zohoarc; b=VBqKo2xzdt6jKHD3lx16Y7hKhgyBOR8amyvFIUxNYHfdisLrqmT9GNNJ6TBxFhQgKPzEFchnxwHic1Pzba6yedaCvyOvMgIWGrXKhltIUPesZ1AEZRYx3VWU2G83e/Mzf27wsYyG8HwCA+5t3/67MPhglNrkENJ5bTCzWUAKIfQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695664849; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6t/Hek37nvY/jYdRd1VfU2g8rvRGHXE1Y+hGG4OCR6w=; b=BlkKCLw9aLZyg4DAHg+zKVcjoHt/QQ9tg4d0WnAV/dSEvwtzeyfUzATTdIOkXP7jJFLD/r3X4Z259ObVM9BCwTz0FRRY1fjTmMoX1/p9NbiV33Qh4r3OynCjuBHrURV00w+Rz8WTaf3l2mcwn9A8UvdX66UndYth0Iampa2QqhY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695664848993122.07581880430507; Mon, 25 Sep 2023 11:00:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qkpps-0000bB-Ob; Mon, 25 Sep 2023 13:57:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkppr-0000aK-I0 for qemu-devel@nongnu.org; Mon, 25 Sep 2023 13:57:31 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qkppp-0002Ai-Mg for qemu-devel@nongnu.org; Mon, 25 Sep 2023 13:57:31 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-690f9c787baso5184271b3a.1 for ; Mon, 25 Sep 2023 10:57:29 -0700 (PDT) Received: from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.57.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:57:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664648; x=1696269448; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6t/Hek37nvY/jYdRd1VfU2g8rvRGHXE1Y+hGG4OCR6w=; b=XfDeeDtiKcQcOiyuvuhb0Z66JNnUo85GPqhZY9ScmTG0Ljy/nvg9ScyCc95EkVp3ct E59MbgnlAX1XLKqCE+Irja3icHbCSXObZJudgyDRjIWRlE77NcFLpKx+1V3YN5iV9fLK HxoLOMgXv7UElAifbL799qiCdkzBZZtqm/FMuwIvXdPVTQGuArKntJ/7yaaWdUQ2qNAU d3EFXIqLqofxZEOp9Klo/SXuSnWywxkyOfJWbxgOZPJY02IgV52hvzWnfr9EBNCL0Hau 8CRBz0+H9AUh2M4rPs1m7WCgSjLiAgN2sgI4zbGiVYi+Puhzx1g9tUN84odi0aehU2TC IwEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664648; x=1696269448; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6t/Hek37nvY/jYdRd1VfU2g8rvRGHXE1Y+hGG4OCR6w=; b=ReUoYaOio4k1BVof+pU/1UcX3A/iLsoqNJvvH4ezKniDYuQYbphYsMV8bFVe6rdZcB DfWPtx8BkjjT9NqnI1gFQz2ZuO1xG/S8TmwOqWW9eIbJ04/59cnko4uNm6FPUUWT6EdD gQEXn8KUJ7SFdluKEwrkeZwuTbmV6XglYbFctCQu37GHvHeHBIddRYs+eZPAoO71lkLp TzDpVEh/cAM6iLlUesymSZQYQ5MN/Svz0OfgASBLy4wGvS9mSfpqP1zoaUKLFzgmakFq AME6yz81rf+IuW46LOxFZYdaMOFvaJMy79yB2ZdXIzl2t1RAHNCLUGtJeYXiObqva5k/ znCQ== X-Gm-Message-State: AOJu0YzwAJlAhMrRLMs2TAeHz4uXhtvowW9PSZje4PdHVxpyhhp6S1A5 jLMyRCMx1syMRcXDHl9hjqIgdTQtaLsOiyUUFMk= X-Google-Smtp-Source: AGHT+IEiopeW2RR/srxuEjbR89rl4eFFXPL/mXhhgTdHD5cdaKuWudBAxWWJ3wam9kCj2JJQxrBWgw== X-Received: by 2002:a05:6a21:33a7:b0:159:beec:79d4 with SMTP id yy39-20020a056a2133a700b00159beec79d4mr6295621pzb.0.1695664648119; Mon, 25 Sep 2023 10:57:28 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Jones Subject: [PATCH v4 04/19] target/riscv: move riscv_tcg_ops to tcg-cpu.c Date: Mon, 25 Sep 2023 14:56:54 -0300 Message-ID: <20230925175709.35696-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664850447100011 Move the remaining of riscv_tcg_ops now that we have a working realize() implementation. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 58 ------------------------------------ target/riscv/cpu.h | 4 --- target/riscv/tcg/tcg-cpu.c | 60 +++++++++++++++++++++++++++++++++++++- 3 files changed, 59 insertions(+), 63 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7215a29324..9426b3b9d6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -838,24 +838,6 @@ static vaddr riscv_cpu_get_pc(CPUState *cs) return env->pc; } =20 -static void riscv_cpu_synchronize_from_tb(CPUState *cs, - const TranslationBlock *tb) -{ - if (!(tb_cflags(tb) & CF_PCREL)) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); - - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); - - if (xl =3D=3D MXL_RV32) { - env->pc =3D (int32_t) tb->pc; - } else { - env->pc =3D tb->pc; - } - } -} - static bool riscv_cpu_has_work(CPUState *cs) { #ifndef CONFIG_USER_ONLY @@ -871,29 +853,6 @@ static bool riscv_cpu_has_work(CPUState *cs) #endif } =20 -static void riscv_restore_state_to_opc(CPUState *cs, - const TranslationBlock *tb, - const uint64_t *data) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); - target_ulong pc; - - if (tb_cflags(tb) & CF_PCREL) { - pc =3D (env->pc & TARGET_PAGE_MASK) | data[0]; - } else { - pc =3D data[0]; - } - - if (xl =3D=3D MXL_RV32) { - env->pc =3D (int32_t)pc; - } else { - env->pc =3D pc; - } - env->bins =3D data[1]; -} - static void riscv_cpu_reset_hold(Object *obj) { #ifndef CONFIG_USER_ONLY @@ -1809,23 +1768,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -const struct TCGCPUOps riscv_tcg_ops =3D { - .initialize =3D riscv_translate_init, - .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, - .restore_state_to_opc =3D riscv_restore_state_to_opc, - -#ifndef CONFIG_USER_ONLY - .tlb_fill =3D riscv_cpu_tlb_fill, - .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, - .do_interrupt =3D riscv_cpu_do_interrupt, - .do_transaction_failed =3D riscv_cpu_do_transaction_failed, - .do_unaligned_access =3D riscv_cpu_do_unaligned_access, - .debug_excp_handler =3D riscv_cpu_debug_excp_handler, - .debug_check_breakpoint =3D riscv_cpu_debug_check_breakpoint, - .debug_check_watchpoint =3D riscv_cpu_debug_check_watchpoint, -#endif /* !CONFIG_USER_ONLY */ -}; - static bool riscv_cpu_is_dynamic(Object *cpu_obj) { return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 409d198635..b2e558f730 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -706,10 +706,6 @@ enum riscv_pmu_event_idx { RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS =3D 0x10021, }; =20 -/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */ -#include "hw/core/tcg-cpu-ops.h" -extern const struct TCGCPUOps riscv_tcg_ops; - /* used by tcg/tcg-cpu.c*/ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool cpu_cfg_ext_is_user_set(uint32_t ext_offset); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 47c89fd554..7d890823bd 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -28,7 +28,66 @@ #include "qemu/error-report.h" #include "qemu/log.h" #include "hw/core/accel-cpu.h" +#include "hw/core/tcg-cpu-ops.h" +#include "tcg/tcg.h" =20 +static void riscv_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) +{ + if (!(tb_cflags(tb) & CF_PCREL)) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); + + tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); + + if (xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t) tb->pc; + } else { + env->pc =3D tb->pc; + } + } +} + +static void riscv_restore_state_to_opc(CPUState *cs, + const TranslationBlock *tb, + const uint64_t *data) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); + target_ulong pc; + + if (tb_cflags(tb) & CF_PCREL) { + pc =3D (env->pc & TARGET_PAGE_MASK) | data[0]; + } else { + pc =3D data[0]; + } + + if (xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t)pc; + } else { + env->pc =3D pc; + } + env->bins =3D data[1]; +} + +static const struct TCGCPUOps riscv_tcg_ops =3D { + .initialize =3D riscv_translate_init, + .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, + .restore_state_to_opc =3D riscv_restore_state_to_opc, + +#ifndef CONFIG_USER_ONLY + .tlb_fill =3D riscv_cpu_tlb_fill, + .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, + .do_interrupt =3D riscv_cpu_do_interrupt, + .do_transaction_failed =3D riscv_cpu_do_transaction_failed, + .do_unaligned_access =3D riscv_cpu_do_unaligned_access, + .debug_excp_handler =3D riscv_cpu_debug_excp_handler, + .debug_check_breakpoint =3D riscv_cpu_debug_check_breakpoint, + .debug_check_watchpoint =3D riscv_cpu_debug_check_watchpoint, +#endif /* !CONFIG_USER_ONLY */ +}; =20 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) @@ -515,7 +574,6 @@ static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, = CPUClass *cc) { /* * All cpus use the same set of operations. - * riscv_tcg_ops is being imported from cpu.c for now. */ cc->tcg_ops =3D &riscv_tcg_ops; } --=20 2.41.0 From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695664847; cv=none; d=zohomail.com; s=zohoarc; b=D0FDqwpsJYQv3hoagqzfe6Vq9mmT4zyPl1zRZhj+n22WhPujwh1zbu0Mec349n2P4hdwIlDU8mr81Vqk+b32SKFX3SrVGm/kaSLDsgtGrmDhyDoRhfDj8mG52EzNS+VbDBaupO9FR0hSxukBLAVk1RlScE+Kuj8qWTXXU2hJi9A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695664847; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.57.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:57:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664651; x=1696269451; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VCxYR3NTkKbBCe79icU57Lpo0FuaiVGO/o6EjtNcge0=; b=Dr9zYjGuZSGU2KXLOmtB/tU1eOr9qcIICHi6odIxJBR+9/lSZHukvYf2aGMVkqWBbx De9U0pkgqMcZ+xizfwSNkqpBh9dVdvn6q/4zw0zIO+eos0K/PoAAWtdhnGS01Y9UTVcr YZvF+XgobWvaGTnirgn93P0zvWyIRnXC0/T76TU2R56D9VkkHcuEcbXo9Wqd4pR51Nos 946VH/gjOubtjNUn+KiTUnNbEyAntibLxWANPTz+Cyz2muNGeAvHBrW5scwQWnUMhSS8 VhPTx/A62/1bNpOFJ3KMl9jKT7JptDqC9YEWXQqApY7LHV30nq0yWWlEsW7Ez+GuzhDZ BQ+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664651; x=1696269451; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VCxYR3NTkKbBCe79icU57Lpo0FuaiVGO/o6EjtNcge0=; b=vxqrECDBvdf1dqI92x9o1EEFNPuVXrdmkYovWytyJ0GfPRnNx1CF/tIhExSjka7E5e l+JQ19JghJCcEV249PNWNJEmd9Vu9AQFZjYNVGVnuon90o0g1MTYuu+qbwN+TR1mkPON Jb7w46AKJgueexO9SxEiTZOJL0b5JS0VB4WPIKo/eQ5PfjGK+IBCd1N9/suuBCxYI2r6 Y9g23cpXH0Iyzdp8bpWPfK2V2J9GO/94s7uww1+5ukDMa2ICiN/5nf8D1/FbGwOxHz3e jfXrSM5o1bfcd1ZrULnxS0qEhm08egZgI7j0JhuUGw03/+AZocgrSY/whSGar7LHE1rp SUZg== X-Gm-Message-State: AOJu0YzsKHBJ8+8RfFn3IeiAVzxgTB3po5eDpThbVJuEWZdCaNptTZJB iYMpCwdANv5DeMmCJXK2XuCT4FrdCBegXjBGrBg= X-Google-Smtp-Source: AGHT+IE1LPj0kQTrXwlmEAvzb1RB0Tl4btUpYg7oLpEX0/WIIDFuM+NOYkFsdv2gFIyWKpQmWXJ7tQ== X-Received: by 2002:a17:90a:7786:b0:274:8041:94c with SMTP id v6-20020a17090a778600b002748041094cmr4736259pjk.13.1695664651138; Mon, 25 Sep 2023 10:57:31 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v4 05/19] target/riscv/cpu.c: add .instance_post_init() Date: Mon, 25 Sep 2023 14:56:55 -0300 Message-ID: <20230925175709.35696-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664848391100007 Content-Type: text/plain; charset="utf-8" All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU calls riscv_init_max_cpu_extensions(). Both can be moved to a common instance_post_init() callback, implemented in riscv_cpu_post_init(), called by all CPUs. The call order then becomes: riscv_cpu_init() -> cpu_init() of each CPU -> .instance_post_init() In the near future riscv_cpu_post_init() will call the init() function of the current accelerator, providing a hook for KVM and TCG accel classes to change the init() process of the CPU. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 43 ++++++++++++++++++++++++++++++++----------- 1 file changed, 32 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9426b3b9d6..848b58e7c4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -427,8 +427,6 @@ static void riscv_max_cpu_init(Object *obj) mlx =3D MXL_RV32; #endif set_misa(env, mlx, 0); - riscv_cpu_add_user_properties(obj); - riscv_init_max_cpu_extensions(obj); env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), mlx =3D=3D MXL_RV32 ? @@ -442,7 +440,6 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -566,7 +563,6 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -579,7 +575,6 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -666,7 +661,6 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - riscv_cpu_add_user_properties(obj); } #endif /* CONFIG_KVM */ =20 @@ -1215,6 +1209,37 @@ static void riscv_cpu_set_irq(void *opaque, int irq,= int level) } #endif /* CONFIG_USER_ONLY */ =20 +static bool riscv_cpu_is_dynamic(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; +} + +static bool riscv_cpu_has_max_extensions(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) !=3D NULL; +} + +static bool riscv_cpu_has_user_properties(Object *cpu_obj) +{ + if (kvm_enabled() && + object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) !=3D NULL) { + return true; + } + + return riscv_cpu_is_dynamic(cpu_obj); +} + +static void riscv_cpu_post_init(Object *obj) +{ + if (riscv_cpu_has_user_properties(obj)) { + riscv_cpu_add_user_properties(obj); + } + + if (riscv_cpu_has_max_extensions(obj)) { + riscv_init_max_cpu_extensions(obj); + } +} + static void riscv_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); @@ -1768,11 +1793,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -static bool riscv_cpu_is_dynamic(Object *cpu_obj) -{ - return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; -} - static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -2009,6 +2029,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .instance_size =3D sizeof(RISCVCPU), .instance_align =3D __alignof__(RISCVCPU), .instance_init =3D riscv_cpu_init, + .instance_post_init =3D riscv_cpu_post_init, .abstract =3D true, .class_size =3D sizeof(RISCVCPUClass), .class_init =3D riscv_cpu_class_init, --=20 2.41.0 From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.57.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:57:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664654; x=1696269454; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YIlNvKVe9OTA8egt3cf/svUMIvB2+X3kSHOpaS7W4Ek=; b=XKXEI1jc6N1hzE1Z+zh9EPwHn/+YkiH8vrTRqzmv2nBIdwOu0fX3YsK40LSCzmPBrn JE6ny6tgLSxbg0aInf2uThzCA+FHgtBiLyyrlSNVZV1ZdQxR9/gzHp8fqtQT/oBUIgcY /2/kzTJhpSeVBLr8SDB3IwSQhlLJtOfhzA9PrXlidUyIe90qIncF1wpDe7UL8r3yPTh0 S+rRl8UJ0pPJXuLUqbFToB7vWMXsKqQRRlACzAPN0k3TgDXLlsHApfnVvOIztce5BrIE FvGGTJRALyZ0S+IR6IxY9fsgLsoCqy0cJCHJEbz5EG+f3xdu1ktFcbWFfp13KqxJBi+N SL9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664654; x=1696269454; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YIlNvKVe9OTA8egt3cf/svUMIvB2+X3kSHOpaS7W4Ek=; b=X/mWOUk6RYMYN0pHVFqV2EPG186mAbesNHIkKl33zJD+QHJXBkCMrWp/4+JgC5vpaH nu6G7sZeeChmvgr7PSKLEUwgL7Gb0BvWnb0Q3dVWgGb/NH6mcf8QXPEGXz1nUWZlcSnk AjlCcf15+HxS4wHgshqPPUAtLdWp6VoD/XU/Cx5VZh17yO4JXwVd3JRAN3ofgzMQyL11 ymCWZXHPcS2hbYLXkiaNmEkYZSs05vYd2y1tz9Twkv2lujXZUb4K5IUOYRyOzHXxeJqT 2zdjh95d/abZ68c+YlCgDwMVGWQ8cEvZAW6XAGV9xiX11DeTF2GqZPTLa039OOySvdgN qaGg== X-Gm-Message-State: AOJu0Yzvoa3rdCc1TcQi3uCs7ZheFkWT3+gZ0uBMeZEM6GgL9e7a1kzv KACu+4ARWx/I19LUurslHaQNE6AEuVAZ6mPSemc= X-Google-Smtp-Source: AGHT+IFCx45lTshLhjQezFzfkqdu8K2pLDRu29JA/8ySPRDFvR6+wTjsz5fZrInb0uYM8UqGQC1Lqw== X-Received: by 2002:a17:90b:3a92:b0:273:cec7:23ee with SMTP id om18-20020a17090b3a9200b00273cec723eemr6533788pjb.37.1695664654368; Mon, 25 Sep 2023 10:57:34 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Jones Subject: [PATCH v4 06/19] target/riscv: move 'host' CPU declaration to kvm.c Date: Mon, 25 Sep 2023 14:56:56 -0300 Message-ID: <20230925175709.35696-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664826317100001 This CPU only exists if we're compiling with KVM so move it to the kvm specific file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 15 --------------- target/riscv/kvm.c | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 848b58e7c4..f8368ce274 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -652,18 +652,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) } #endif =20 -#if defined(CONFIG_KVM) -static void riscv_host_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; -#if defined(TARGET_RISCV32) - set_misa(env, MXL_RV32, 0); -#elif defined(TARGET_RISCV64) - set_misa(env, MXL_RV64, 0); -#endif -} -#endif /* CONFIG_KVM */ - static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; @@ -2041,9 +2029,6 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { }, DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), -#if defined(CONFIG_KVM) - DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), -#endif #if defined(TARGET_RISCV32) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 1e4e4456b3..31d2ede4b6 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -1271,3 +1271,24 @@ void kvm_riscv_aia_create(MachineState *machine, uin= t64_t group_shift, =20 kvm_msi_via_irqfd_allowed =3D kvm_irqfds_enabled(); } + +static void riscv_host_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + +#if defined(TARGET_RISCV32) + env->misa_mxl_max =3D env->misa_mxl =3D MXL_RV32; +#elif defined(TARGET_RISCV64) + env->misa_mxl_max =3D env->misa_mxl =3D MXL_RV64; +#endif +} + +static const TypeInfo riscv_kvm_cpu_type_infos[] =3D { + { + .name =3D TYPE_RISCV_CPU_HOST, + .parent =3D TYPE_RISCV_CPU, + .instance_init =3D riscv_host_cpu_init, + } +}; + +DEFINE_TYPES(riscv_kvm_cpu_type_infos) --=20 2.41.0 From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695664783; cv=none; d=zohomail.com; s=zohoarc; b=ZsfOjtMcRRfXM5OCQQtIb7NsrNpj4AoKvb12AtJ4C1CLZmGYWXnWRCb0az0t+01UPVSNWWt4uCUh7AaUoBgCVHJaNWWQdMgDmT54EpUnMbsr0Makeiyf1WobWDcPPWH1c+CufYFA8NGhQ4wGv6LngrJLcIbucNswHi0weyC5LZk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695664783; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=brvKvDoSqQKvpWZjq/dDqg6MkMEWHqYpCPo6SUgM1h4=; b=lhO8ByzS+ZMjS7hbCV6PpSfG1jZ+HjjzOt8VDKn/vs3h21arfVpnojWynF/124NKXhiDyhJQtgvImux2T47Z/cpOS4fNrUd7cDZ9UTjA3uFc7eF5uU/hz7fcuqtrMk+JYeWKBlu9eg2m4CFeUWGotJB2m1IafIYMElZSmZfYw3Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695664783325489.8382791888358; Mon, 25 Sep 2023 10:59:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qkpq2-0000dG-NE; Mon, 25 Sep 2023 13:57:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkpq0-0000d3-Lv for qemu-devel@nongnu.org; Mon, 25 Sep 2023 13:57:40 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qkppz-0002CL-2m for qemu-devel@nongnu.org; Mon, 25 Sep 2023 13:57:40 -0400 Received: by mail-pg1-x536.google.com with SMTP id 41be03b00d2f7-578af21ff50so4152632a12.1 for ; Mon, 25 Sep 2023 10:57:38 -0700 (PDT) Received: from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.57.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:57:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664657; x=1696269457; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=brvKvDoSqQKvpWZjq/dDqg6MkMEWHqYpCPo6SUgM1h4=; b=DUcmFMiryFojQJrkpp09isWMLPOhOrv9Hbu9b4JzDEDSeSDwaaNvz//uyHYdF86ldO wIYz6wD7jYvHfBT5ZkSYUNfXqunXFKHOJR58MD1lAmBk4mCeKHwZNETUfUa2wFufDmeC wjXyi+a5IIgED6raVRW5ljv0eIO9gyfbD6HtNiOqA8tkIiyhOT4+cCdhUpIUvEkw8l78 Q6OhXbtiZm4MKl6l5JHmrlumeiHy8NjMLFYQkASgtSKJqdfd1BZbIbSsdx6+OJ/yThjD HqTm88T8/C4LUWX+CRzV+lrqekiH2s+PKzJwgaTxGPIE2Pf6bKkilNVddgPv9ZYpqMJJ 24kA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664657; x=1696269457; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=brvKvDoSqQKvpWZjq/dDqg6MkMEWHqYpCPo6SUgM1h4=; b=h13LabVYu/akiEhIOcH/gyA+KELZo6+FWalUmohPRlA80pMCGNPFlqMGW8+5uaJvNq B0ApYlMlo7DM0D1/oScsfELM02+UDVrdi/p0WwRx+d4EkNcVZNrSrxRHK9Pt4B2AyPOl hr2O8Q7oVDN2in+RsEsdIfqJ2HcNL8XpB4g+7XHKUDrW6y6b/ydkrbGf7FMNHta0Vmlk I/ibaTo5rpr/8WtVFfabisIzYvHjbzRg3YobDjp411XukP2hDqOyPxcBm2bbUy2IlnK3 EQwJ8mC3cor5KQ+9Cg+XJeMHLOc3SNmpiK09AdqghNySPQ3FBZ3CbtPrUYRSTWJzjhqy mBuQ== X-Gm-Message-State: AOJu0Yzhho5jCClKu4FJju2s8bHD1yMSHjKi/PqhDH4+8uOmuKZCmoVU QQHEFY4bTOT1YkCJWhGvlOrS3wF063YOz+UWV+A= X-Google-Smtp-Source: AGHT+IHiVDUlM8Oeen8aZ1QjNrpdEPrYLESDsrTG4/98eHNaxo8bOUtWaLpW6h5iQgla7jxPKt28YQ== X-Received: by 2002:a17:90a:ba0d:b0:276:ae8f:2456 with SMTP id s13-20020a17090aba0d00b00276ae8f2456mr5060521pjr.3.1695664657321; Mon, 25 Sep 2023 10:57:37 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v4 07/19] target/riscv/cpu.c: mark extensions arrays as 'const' Date: Mon, 25 Sep 2023 14:56:57 -0300 Message-ID: <20230925175709.35696-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664784790100003 Content-Type: text/plain; charset="utf-8" We'll need to export these arrays to the accelerator classes in the next patches. Mark them as 'const' now because they should not be modified at runtime. Note that 'riscv_cpu_options' will also be exported, but can't be marked as 'const', because the properties are changed via qdev_property_add_static(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f8368ce274..048a2dbc77 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1407,7 +1407,7 @@ typedef struct RISCVCPUMultiExtConfig { {.name =3D _name, .offset =3D CPU_CFG_OFFSET(_prop), \ .enabled =3D _defval} =20 -static RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { +static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true), @@ -1469,7 +1469,7 @@ static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] =3D { +static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] =3D { MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false), MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false), MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false), @@ -1487,7 +1487,7 @@ static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]= =3D { }; =20 /* These are experimental so mark with 'x-' */ -static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { +static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { /* ePMP 0.9.3 */ MULTI_EXT_CFG_BOOL("x-epmp", epmp, false), MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false), @@ -1558,7 +1558,7 @@ static void cpu_get_multi_ext_cfg(Object *obj, Visito= r *v, const char *name, } =20 static void cpu_add_multi_ext_prop(Object *cpu_obj, - RISCVCPUMultiExtConfig *multi_cfg) + const RISCVCPUMultiExtConfig *multi_cfg) { object_property_add(cpu_obj, multi_cfg->name, "bool", cpu_get_multi_ext_cfg, @@ -1575,11 +1575,13 @@ static void cpu_add_multi_ext_prop(Object *cpu_obj, } =20 static void riscv_cpu_add_multiext_prop_array(Object *obj, - RISCVCPUMultiExtConfig *arra= y) + const RISCVCPUMultiExtConfig *arra= y) { + const RISCVCPUMultiExtConfig *prop; + g_assert(array); =20 - for (RISCVCPUMultiExtConfig *prop =3D array; prop && prop->name; prop+= +) { + for (prop =3D array; prop && prop->name; prop++) { cpu_add_multi_ext_prop(obj, prop); } } @@ -1620,11 +1622,13 @@ static void riscv_cpu_add_kvm_unavail_prop(Object *= obj, const char *prop_name) } =20 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, - RISCVCPUMultiExtConfig *a= rray) + const RISCVCPUMultiExtConfig *arra= y) { + const RISCVCPUMultiExtConfig *prop; + g_assert(array); =20 - for (RISCVCPUMultiExtConfig *prop =3D array; prop && prop->name; prop+= +) { + for (prop =3D array; prop && prop->name; prop++) { riscv_cpu_add_kvm_unavail_prop(obj, prop->name); } } @@ -1687,7 +1691,7 @@ static void riscv_init_max_cpu_extensions(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - RISCVCPUMultiExtConfig *prop; + const RISCVCPUMultiExtConfig *prop; =20 /* Enable RVG, RVJ and RVV that are disabled by default */ set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); --=20 2.41.0 From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.57.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:57:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664660; x=1696269460; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z7GMyJI5zNoOowXtT9uNjVqEjhxMht1XFHvsgI/HHa0=; b=FlYau+qWeKMtHxGgFTbiF+noJLFv2DQEmH3o2KZGr1p+xTXJGaN/TstC2u/iRxJaqO rK6JdFBgtEzrt2FCxRK5Jq+nKoznlEX8dWdPe40qck+YsMEBhHlLECLSxh+/HoSE7Hgo iglr9n0xp9iBBveOMFrs5dnWGUE/UKnzAyyf6I/mOSTfyPqHuN8Yhhe6ektTYztW2b7w 5RxZ8y06hF2BVjiKJ7CQ4Tihlq+aOkzK6EcIu8s03kCTE9aiR5eout+sVJk/sKRXTo2A rZwTMyu2I3dWv/IZm0/zuGjznAxpOSQCfpQj93mgX+LeoQHef2mKQTXNMOzT6ahWxhSR 7Hag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664660; x=1696269460; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z7GMyJI5zNoOowXtT9uNjVqEjhxMht1XFHvsgI/HHa0=; b=mD9SbDZVH+CJxtWOXQSWydvMXBJDypa4idSDldVio1VHTgV4/vaReewloA9owfSQ8G nXhooCp2QXh0UuET6Ghjreeo30+BXPxS9UFRoc/1owD8+Vjv6mQyDX60BhmLQP3shvYS Pl1PG+NGQ42gZRD2Goy9fhUeTPZDx3Z+RIM6L5JvxeAwM9ndRO7k/djOdj8cazsjm0/u ev03ONzmVwLsj4NpTLU4bFlPFhVAIBicRkVUkG2lxEatMHcammyHsmNdPlWsDYw7nxSt pzed+fJxlEvjzsI0xz1GKGeaHLa0I9+ZYLLiPTFxxRRWMOqqtXiu/zjBXIoGsOJ48FN5 NheA== X-Gm-Message-State: AOJu0YwChj9fofjKJLDxlZZkKv6dq4pHA/SqVmMB38q/z8+Ks9aQP18c uAnenbg+YKIxi8xxugWhbpQJDOEWpIQYVXM26EE= X-Google-Smtp-Source: AGHT+IHYsPjUv5g4HAOamzZzaDRkrwpy+AtfGCbmTVxR+QrDAdaO9z4GOkf9M4G3eTD5Yx365mHMyw== X-Received: by 2002:a17:90a:ad43:b0:276:eadf:11af with SMTP id w3-20020a17090aad4300b00276eadf11afmr475871pjv.7.1695664660476; Mon, 25 Sep 2023 10:57:40 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v4 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c Date: Mon, 25 Sep 2023 14:56:58 -0300 Message-ID: <20230925175709.35696-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664823922100005 Content-Type: text/plain; charset="utf-8" We'll introduce the KVM accelerator class with a 'cpu_instance_init' implementation that is going to be invoked during the common riscv_cpu_post_init() (via accel_cpu_instance_init()). This instance_init will execute KVM exclusive code that TCG doesn't care about, such as adding KVM specific properties, initing registers using a KVM scratch CPU and so on. The core of the forementioned cpu_instance_init impl is the current riscv_cpu_add_kvm_properties() that is being used by the common code via riscv_cpu_add_user_properties() in cpu.c. Move it to kvm.c, together will all the relevant artifacts, exporting and renaming it to kvm_riscv_cpu_add_kvm_properties() so cpu.c can keep using it for now. To make this work we'll need to export riscv_cpu_extensions, riscv_cpu_vendor_exts and riscv_cpu_experimental_exts from cpu.c as well. The TCG accelerator will also need to access those in the near future so this export will benefit us in the long run. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 85 +++------------------------------------- target/riscv/cpu.h | 14 +++++++ target/riscv/kvm.c | 68 +++++++++++++++++++++++++++++++- target/riscv/kvm_riscv.h | 3 -- 4 files changed, 86 insertions(+), 84 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 048a2dbc77..0dc9b3201d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1370,7 +1370,7 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { * change MISA bits during realize() (RVG enables MISA * bits but the user is warned about it). */ -static void riscv_cpu_add_misa_properties(Object *cpu_obj) +void riscv_cpu_add_misa_properties(Object *cpu_obj) { int i; =20 @@ -1397,17 +1397,11 @@ static void riscv_cpu_add_misa_properties(Object *c= pu_obj) } } =20 -typedef struct RISCVCPUMultiExtConfig { - const char *name; - uint32_t offset; - bool enabled; -} RISCVCPUMultiExtConfig; - #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \ {.name =3D _name, .offset =3D CPU_CFG_OFFSET(_prop), \ .enabled =3D _defval} =20 -static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { +const RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true), @@ -1469,7 +1463,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_extensi= ons[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] =3D { +const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] =3D { MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false), MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false), MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false), @@ -1487,7 +1481,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_vendor_= exts[] =3D { }; =20 /* These are experimental so mark with 'x-' */ -static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { +const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { /* ePMP 0.9.3 */ MULTI_EXT_CFG_BOOL("x-epmp", epmp, false), MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false), @@ -1513,7 +1507,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_experim= ental_exts[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static Property riscv_cpu_options[] =3D { +Property riscv_cpu_options[] =3D { DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), =20 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), @@ -1586,75 +1580,6 @@ static void riscv_cpu_add_multiext_prop_array(Object= *obj, } } =20 -#ifdef CONFIG_KVM -static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, - const char *name, - void *opaque, Error **errp) -{ - const char *propname =3D opaque; - bool value; - - if (!visit_type_bool(v, name, &value, errp)) { - return; - } - - if (value) { - error_setg(errp, "extension %s is not available with KVM", - propname); - } -} - -static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_n= ame) -{ - /* Check if KVM created the property already */ - if (object_property_find(obj, prop_name)) { - return; - } - - /* - * Set the default to disabled for every extension - * unknown to KVM and error out if the user attempts - * to enable any of them. - */ - object_property_add(obj, prop_name, "bool", - NULL, cpu_set_cfg_unavailable, - NULL, (void *)prop_name); -} - -static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, - const RISCVCPUMultiExtConfig *arra= y) -{ - const RISCVCPUMultiExtConfig *prop; - - g_assert(array); - - for (prop =3D array; prop && prop->name; prop++) { - riscv_cpu_add_kvm_unavail_prop(obj, prop->name); - } -} - -void kvm_riscv_cpu_add_kvm_properties(Object *obj) -{ - Property *prop; - DeviceState *dev =3D DEVICE(obj); - - kvm_riscv_init_user_properties(obj); - riscv_cpu_add_misa_properties(obj); - - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts); - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); - - for (prop =3D riscv_cpu_options; prop && prop->name; prop++) { - /* Check if KVM created the property already */ - if (object_property_find(obj, prop->name)) { - continue; - } - qdev_property_add_static(dev, prop); - } -} -#endif - /* * Add CPU properties with user-facing flags. * diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b2e558f730..9dc4113812 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -22,6 +22,7 @@ =20 #include "hw/core/cpu.h" #include "hw/registerfields.h" +#include "hw/qdev-properties.h" #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" #include "qom/object.h" @@ -713,6 +714,19 @@ bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_of= fset); int cpu_cfg_ext_get_min_version(uint32_t ext_offset); void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); =20 +typedef struct RISCVCPUMultiExtConfig { + const char *name; + uint32_t offset; + bool enabled; +} RISCVCPUMultiExtConfig; + +extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; +extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; +extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; +extern Property riscv_cpu_options[]; + +void riscv_cpu_add_misa_properties(Object *cpu_obj); + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; =20 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 31d2ede4b6..e682a70311 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -345,6 +345,52 @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU = *cpu, CPUState *cs) } } =20 +static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **errp) +{ + const char *propname =3D opaque; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + if (value) { + error_setg(errp, "extension %s is not available with KVM", + propname); + } +} + +static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_n= ame) +{ + /* Check if KVM created the property already */ + if (object_property_find(obj, prop_name)) { + return; + } + + /* + * Set the default to disabled for every extension + * unknown to KVM and error out if the user attempts + * to enable any of them. + */ + object_property_add(obj, prop_name, "bool", + NULL, cpu_set_cfg_unavailable, + NULL, (void *)prop_name); +} + +static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, + const RISCVCPUMultiExtConfig *arra= y) +{ + const RISCVCPUMultiExtConfig *prop; + + g_assert(array); + + for (prop =3D array; prop && prop->name; prop++) { + riscv_cpu_add_kvm_unavail_prop(obj, prop->name); + } +} + static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) { int i; @@ -754,7 +800,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, = KVMScratchCPU *kvmcpu) } } =20 -void kvm_riscv_init_user_properties(Object *cpu_obj) +static void riscv_init_user_properties(Object *cpu_obj) { RISCVCPU *cpu =3D RISCV_CPU(cpu_obj); KVMScratchCPU kvmcpu; @@ -1272,6 +1318,26 @@ void kvm_riscv_aia_create(MachineState *machine, uin= t64_t group_shift, kvm_msi_via_irqfd_allowed =3D kvm_irqfds_enabled(); } =20 +void kvm_riscv_cpu_add_kvm_properties(Object *obj) +{ + DeviceState *dev =3D DEVICE(obj); + + riscv_init_user_properties(obj); + riscv_cpu_add_misa_properties(obj); + + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts); + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); + + for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { + /* Check if KVM created the property already */ + if (object_property_find(obj, prop->name)) { + continue; + } + qdev_property_add_static(dev, prop); + } +} + static void riscv_host_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index 44b850a046..da9630c4af 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -19,10 +19,7 @@ #ifndef QEMU_KVM_RISCV_H #define QEMU_KVM_RISCV_H =20 -/* Temporarily implemented in cpu.c */ void kvm_riscv_cpu_add_kvm_properties(Object *obj); - -void kvm_riscv_init_user_properties(Object *cpu_obj); void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, --=20 2.41.0 From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695664846; cv=none; d=zohomail.com; s=zohoarc; b=BMUg04UIP3fYXVzp7LW8E2Fpmd7Jv1e1A+rRwX2/NgAa13NxZSsJxl0uasZB0XZjTLi9/XJ5QHJBMe+eBOskvxqOOWAG3LN7Fb3OFXtzyGMbjh+qyn+gWbgK2BEfAdKCiB0CTU7qpjfw8g/Up2LR2D6J9D8tZsAv5Tt/aw0o34U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695664846; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.57.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:57:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664663; x=1696269463; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LFmj37VtPhwmOBy897ThcZlVlGy4D5lwpNW6ScnFALE=; b=RkiTx4AqmIEhfCz7dm9pSPXdE11P94luf6IP0h7ueA1DXKBkzwEHQfMbQdpSyKVgKz 6McwyZ5HxDB0bXXGv9WfiXZ+4jdpDdWub7Y+D/hZE/key4bSigaSouimArUwqE+NerED WWGomL2tTZIWT8CvneVTWlnc/ZHAuEVShVZCQaOYNeuAI+wuQvTwxGnNWzYb3A6PizlI kepPTMFq+V+EgLD/af09LhKmcHPILOQ7aCNwcXYQg5/HfisV/L72h5IM3N06d2FtuR8w iWyEflT5cwrPeuo7//NFg8AQv6JcgWlOoU93qGOMquem4N63h4uZdqlCUSUNw79Lqmtt NUjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664663; x=1696269463; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LFmj37VtPhwmOBy897ThcZlVlGy4D5lwpNW6ScnFALE=; b=cw/a5dntEm5FC4J+DXM8lLS31wqX5LZZFDuU5EzcgtEHQY6RQhFAETH8Hpe/EmWSAq h1YbotgrvWj/k9xsxB4CCRsGtvEAoS1TIQmAI8lHjOUNDWaWFavj22AVG1HSVWv2/76w hk8llSsB0kCppb5YloYw0BMLFN9VC7XP2Bk5Y2XdbQ5lJs4MuzDKaQuJWZoqILrioUMM iXaL60++P4HSL3hLCPPRIto78VW6YKvmc6ngJsOyjD4RXY3ptFGUMyQIfF8/TMkxc5o6 Fw77nUQZcnxaoz9RXJ692GG60KhvKDu6IhR6jKTEgaLtQMbvUGsnCRpd/aefqppO3UZg qg0g== X-Gm-Message-State: AOJu0YwUr37TRfG+mJFHEStiABq5C3WccqFY0bURK8O8BB8lcPW5azQY l5MD9aQu+B8wQ6QWnpetuZELU21PzNRkaYSBR6k= X-Google-Smtp-Source: AGHT+IGqQHgJ7qWTODKF7WmWKwesNpQxwbqxDCVYPHpUk71GKI9XsiQGlUnn8+OYzgHlNPOyKugkEQ== X-Received: by 2002:a17:90a:f109:b0:274:c637:4b97 with SMTP id cc9-20020a17090af10900b00274c6374b97mr5237841pjb.16.1695664663423; Mon, 25 Sep 2023 10:57:43 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v4 09/19] target/riscv: make riscv_add_satp_mode_properties() public Date: Mon, 25 Sep 2023 14:56:59 -0300 Message-ID: <20230925175709.35696-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664847043100001 Content-Type: text/plain; charset="utf-8" This function is used for both accelerators. Make it public, and call it from kvm_riscv_cpu_add_kvm_properties(). This will make it easier to split KVM specific code for the KVM accelerator class in the next patch. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 ++--- target/riscv/cpu.h | 1 + target/riscv/kvm.c | 1 + 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0dc9b3201d..50be127f36 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1115,7 +1115,7 @@ static void cpu_riscv_set_satp(Object *obj, Visitor *= v, const char *name, satp_map->init |=3D 1 << satp; } =20 -static void riscv_add_satp_mode_properties(Object *obj) +void riscv_add_satp_mode_properties(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); =20 @@ -1589,12 +1589,11 @@ static void riscv_cpu_add_multiext_prop_array(Objec= t *obj, static void riscv_cpu_add_user_properties(Object *obj) { #ifndef CONFIG_USER_ONLY - riscv_add_satp_mode_properties(obj); - if (kvm_enabled()) { kvm_riscv_cpu_add_kvm_properties(obj); return; } + riscv_add_satp_mode_properties(obj); #endif =20 riscv_cpu_add_misa_properties(obj); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9dc4113812..cb13464ba6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -726,6 +726,7 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_experimen= tal_exts[]; extern Property riscv_cpu_options[]; =20 void riscv_cpu_add_misa_properties(Object *cpu_obj); +void riscv_add_satp_mode_properties(Object *obj); =20 /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index e682a70311..e5e957121f 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -1323,6 +1323,7 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj) DeviceState *dev =3D DEVICE(obj); =20 riscv_init_user_properties(obj); + riscv_add_satp_mode_properties(obj); riscv_cpu_add_misa_properties(obj); =20 riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); --=20 2.41.0 From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695664793; cv=none; d=zohomail.com; s=zohoarc; b=dZF4DO4BBp08XXAH8kNuxj0tMKFaWDizKKTUpahxab2w/DW3RU7TME3gdMoQHQd5ZXBz+CHYxfX8C2EdC9dQoxOS7WoL84mrcsodsC8upl6GvyS8bvEScC1qMBdKM5Di7oGgtiRlOllVUu/VAKYzVUhnLjzw/yTocsdR3HXDHLI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695664793; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9tWUy+Y3YjrpIBChvCNNHtWPQ0l+kZDqCFnD8gAcXHs=; b=ejg35TXYrmUODzdwhmajEydoC9M64H3X0/6FG/AFR6RfJbPa+gR1ZDgxP2IAqzhrFz0ESAnABeYcvqyBF/F/7tqJixZnPyNfbKy3TfLrL4m5YN3lPkpT9nm4Zw0Hbq5nnAFS2le+Ncp3wTqnMCej1rPZBi4OFbzKGaM0L/S8upE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695664793534822.7023956777051; Mon, 25 Sep 2023 10:59:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qkpqC-0000gG-6l; Mon, 25 Sep 2023 13:57:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkpqA-0000fi-CZ for qemu-devel@nongnu.org; Mon, 25 Sep 2023 13:57:50 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qkpq8-0002Dc-9b for qemu-devel@nongnu.org; Mon, 25 Sep 2023 13:57:50 -0400 Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-578b4997decso5429170a12.0 for ; Mon, 25 Sep 2023 10:57:47 -0700 (PDT) Received: from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:57:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664666; x=1696269466; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9tWUy+Y3YjrpIBChvCNNHtWPQ0l+kZDqCFnD8gAcXHs=; b=ETTugtjFSbJBLMCxcMpV0Ikmas+q9fBXB+svUJ6K57uVn0+zS7dwWAOpbE2dHKCCYw AnsCT2hrGLwqgQDXj61aqarFQJlJzaFxiN6IBpwuuwDghYgdKbqP39+HvJSe4P+8hB+n 6JN5QXEQH0bXQG1g17bWnzCggLCyOoPWYQrE9vwUjXmR3E+qKnFBnOb97nozkg+8VNeI 3y1LXWUw/j5hoZzpjkTjIZvUQcQH53gqvJxUaKKtzhG5OiSEz5HyJSZ84vQLGObP4eYx sMmlzgfi9uINrTr7y9eFF1x9NM6RN4gF4AgQeyTSHGOmWWxNPQnckFjou9wierEioD/p joJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664666; x=1696269466; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9tWUy+Y3YjrpIBChvCNNHtWPQ0l+kZDqCFnD8gAcXHs=; b=vmZDeWPvvWA0ACxeMJozDony5Mc8DKcTyH5poZhfPoCDBAPX9NvzufLDMab+0BcVQd u8YLZc41NJHP/a60Jn2aX8wPBcH8ccnNvIDhmjuvF/CHjgwK62ZGVaMGnt1beSQX/x3y jJYFKnt4duZO0saS62daymkKy61EASNWr+jkgJWHAsRGXHBDTQywFQC3CN/RUvXQnR/U QAmsRYW2ap/PyNniQAuvJ9Bh3eZz2qj462I3l5sJkEjFT+B3LMjEZULAJzFZ+gGPPy71 ouW5+Jrsu5SKp4tAYBIZ9+CqUiwd90d3+Xbmj+M89fCBXE24Bku3KeENVtmwoBUzyES5 xCVQ== X-Gm-Message-State: AOJu0Yx1vAAH3jmJCLYvvYeF3D2Mn9MkRQGY3aCsrWUEePbty/L7Ckq9 TWirlBxc0bg88iI5YUJBTirJZhqpxqLl9vbmCWI= X-Google-Smtp-Source: AGHT+IFouv1EeVQ6IF/T8kTz+c1M7MbDEfQYsj53W7J/d5FrM2oOyOwL/lVuqNOB0jkEmkMA/bSHLQ== X-Received: by 2002:a17:90b:4ace:b0:262:f06d:c0fc with SMTP id mh14-20020a17090b4ace00b00262f06dc0fcmr6227116pjb.7.1695664666159; Mon, 25 Sep 2023 10:57:46 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v4 10/19] target/riscv: remove kvm-stub.c Date: Mon, 25 Sep 2023 14:57:00 -0300 Message-ID: <20230925175709.35696-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664795067100003 Content-Type: text/plain; charset="utf-8" This file is not needed for some time now. Both kvm_riscv_reset_vcpu() and kvm_riscv_set_irq() have public declarations in kvm_riscv.h and are wrapped in 'if kvm_enabled()' blocks that the compiler will rip it out in non-KVM builds. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/kvm-stub.c | 30 ------------------------------ target/riscv/meson.build | 2 +- 2 files changed, 1 insertion(+), 31 deletions(-) delete mode 100644 target/riscv/kvm-stub.c diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c deleted file mode 100644 index 4e8fc31a21..0000000000 --- a/target/riscv/kvm-stub.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * QEMU KVM RISC-V specific function stubs - * - * Copyright (c) 2020 Huawei Technologies Co., Ltd - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or - * more details. - * - * You should have received a copy of the GNU General Public License along= with - * this program. If not, see . - */ -#include "qemu/osdep.h" -#include "cpu.h" -#include "kvm_riscv.h" - -void kvm_riscv_reset_vcpu(RISCVCPU *cpu) -{ - abort(); -} - -void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) -{ - abort(); -} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index f0486183fa..3323b78b84 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -24,7 +24,7 @@ riscv_ss.add(files( 'zce_helper.c', 'vcrypto_helper.c' )) -riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files(= 'kvm-stub.c')) +riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 riscv_system_ss =3D ss.source_set() riscv_system_ss.add(files( --=20 2.41.0 From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695664839; cv=none; d=zohomail.com; s=zohoarc; b=S30eCUhpxyRRiimSZAB+ugpoUyEYLYvAI3UFNJuFEH7JYUmkSy1ZUBe2X9Rmk/lgpOQuEAsaV7P4IyvaRiXqZVKns1N0392Ii1YdUEkOHNkBJ+IMOPwgrb560GDmEwJpuwa4Q1Gkydx20kYFUxok2aa+josgivHHWfKKuCKvrvs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695664839; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lDVkCr5LYXxfDA6GCy65wJeT7zywjPXlKXx4Zd0pAI8=; b=DNwzNWv0ZbgKzl1tayb+1pFCZ79UISmltFqyInHo/A9Okg/InvRhjvNykgfnFdmycZVyJVvy1Bl2IiBka1PkRkwBVdJ9+DqYWaY7BKSU1Nt0ECrnV36QME8OiybYCwjCgxLPtvGpPaJioDcLNr68wwMB0Wh/ZlbeSTJet6Rzzq8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695664839717518.3179173240351; Mon, 25 Sep 2023 11:00:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qkpqH-0000mZ-0i; Mon, 25 Sep 2023 13:57:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkpqF-0000lr-TB for qemu-devel@nongnu.org; Mon, 25 Sep 2023 13:57:55 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qkpqA-0002Du-Uw for qemu-devel@nongnu.org; Mon, 25 Sep 2023 13:57:55 -0400 Received: by mail-pg1-x531.google.com with SMTP id 41be03b00d2f7-578d0d94986so5032146a12.2 for ; Mon, 25 Sep 2023 10:57:50 -0700 (PDT) Received: from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.57.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:57:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664669; x=1696269469; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lDVkCr5LYXxfDA6GCy65wJeT7zywjPXlKXx4Zd0pAI8=; b=I2IGWpQIWX14A3FIm9Q+qQMqxvupae3+XlwwGko9LnFjNey0YqwwDySR97xRvgOVYj s2wZU+dLTaB2DRfe6yQuctlspxg1iBUetdHLEouEoadZMOOD9ZRWCbLE1W2ioMwyM0Sc JkpX1BjQdbU6nHIDGvQHv3QlILjexT1fXwKtHaZY946h/AS7HmIgNDkFgCJ1f1mtMpZ3 ZiDGOrJsANLehkMojReBYzgyG0FD2+JgJrL1NvI7vQHAWBnK1TgWq9wtjWPCO7/Z4zcF TZNtHRjYlmNLahu/0sFDVwJziiiZkEY0hpHea5cnLAQgXGTaE8CSrDHp9rIMg5HUUgmA oqMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664669; x=1696269469; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lDVkCr5LYXxfDA6GCy65wJeT7zywjPXlKXx4Zd0pAI8=; b=EeU/hPcYlcXrBYouTwWPJ2T6UxhWftl+U+y4DalxGr5gVeWOq1KLQJaB0THF98LVyB epg3yffa8APtNMTcuJMP8zjF21jUffuEIbkKszQigyeyxyiUWi8ULmtewYaCfwWTnbp3 Yy4abtsGNUyYEQhyyXun0Vrs9pcEYX+uSqM+W3y3xmW6iFsgIUA+7o59xgFpFbF0dyyR S2T9Sb5ghT/A7BuRvcRK9i1LmhxkTvqrZwVJi+9idFtzoKQA5UQdeChjvyTu9J6BwChT OtsgSpkIn2ktU445QP3+bhBvzM+QVZ3GFLEoWc3xA+p9Ns2Hteg2QH8iF3S2i7iUfzaT IKgQ== X-Gm-Message-State: AOJu0Yyd7/WwT1Lh0AAiTpQcyX5Fwg11O1YFpbiP8LjZzQGFpPnVbmIA IZ8og1rIWflFi3WNt/VSUXyC4Dwf3a0+Xbe6yB4= X-Google-Smtp-Source: AGHT+IGxzZSztogBu83hK4+jrL94X0bUoVdEM9JjYCU3cP4hU6tG3wYT+MW5JphU2GDmbP7S8VFRvQ== X-Received: by 2002:a17:90a:bf11:b0:26b:534e:234 with SMTP id c17-20020a17090abf1100b0026b534e0234mr6474257pjs.35.1695664669326; Mon, 25 Sep 2023 10:57:49 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v4 11/19] target/riscv: introduce KVM AccelCPUClass Date: Mon, 25 Sep 2023 14:57:01 -0300 Message-ID: <20230925175709.35696-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664841033100003 Content-Type: text/plain; charset="utf-8" Add a KVM accelerator class like we did with TCG. The difference is that, at least for now, we won't be using a realize() implementation for this accelerator. We'll start by assiging kvm_riscv_cpu_add_kvm_properties(), renamed to kvm_cpu_instance_init(), as a 'cpu_instance_init' implementation. Change riscv_cpu_post_init() to invoke accel_cpu_instance_init(), which will go through the 'cpu_instance_init' impl of the current acceleration (if available) and execute it. The end result is that the KVM initial setup, i.e. starting registers and adding its specific properties, will be done via this hook. Add a 'tcg_enabled()' condition in riscv_cpu_post_init() to avoid calling riscv_cpu_add_user_properties() when running KVM. We'll remove this condition when the TCG accel class get its own 'cpu_instance_init' implementation. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 8 +++----- target/riscv/kvm.c | 26 ++++++++++++++++++++++++-- target/riscv/kvm_riscv.h | 1 - 3 files changed, 27 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 50be127f36..c8a19be1af 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1219,7 +1219,9 @@ static bool riscv_cpu_has_user_properties(Object *cpu= _obj) =20 static void riscv_cpu_post_init(Object *obj) { - if (riscv_cpu_has_user_properties(obj)) { + accel_cpu_instance_init(CPU(obj)); + + if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) { riscv_cpu_add_user_properties(obj); } =20 @@ -1589,10 +1591,6 @@ static void riscv_cpu_add_multiext_prop_array(Object= *obj, static void riscv_cpu_add_user_properties(Object *obj) { #ifndef CONFIG_USER_ONLY - if (kvm_enabled()) { - kvm_riscv_cpu_add_kvm_properties(obj); - return; - } riscv_add_satp_mode_properties(obj); #endif =20 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index e5e957121f..606fdab223 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -31,6 +31,7 @@ #include "sysemu/kvm_int.h" #include "cpu.h" #include "trace.h" +#include "hw/core/accel-cpu.h" #include "hw/pci/pci.h" #include "exec/memattrs.h" #include "exec/address-spaces.h" @@ -1318,8 +1319,9 @@ void kvm_riscv_aia_create(MachineState *machine, uint= 64_t group_shift, kvm_msi_via_irqfd_allowed =3D kvm_irqfds_enabled(); } =20 -void kvm_riscv_cpu_add_kvm_properties(Object *obj) +static void kvm_cpu_instance_init(CPUState *cs) { + Object *obj =3D OBJECT(RISCV_CPU(cs)); DeviceState *dev =3D DEVICE(obj); =20 riscv_init_user_properties(obj); @@ -1331,7 +1333,7 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj) riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); =20 for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { - /* Check if KVM created the property already */ + /* Check if we have a specific KVM handler for the option */ if (object_property_find(obj, prop->name)) { continue; } @@ -1339,6 +1341,26 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj) } } =20 +static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_instance_init =3D kvm_cpu_instance_init; +} + +static const TypeInfo kvm_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("kvm"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D kvm_cpu_accel_class_init, + .abstract =3D true, +}; +static void kvm_cpu_accel_register_types(void) +{ + type_register_static(&kvm_cpu_accel_type_info); +} +type_init(kvm_cpu_accel_register_types); + static void riscv_host_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index da9630c4af..8329cfab82 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -19,7 +19,6 @@ #ifndef QEMU_KVM_RISCV_H #define QEMU_KVM_RISCV_H =20 -void kvm_riscv_cpu_add_kvm_properties(Object *obj); void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, --=20 2.41.0 From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695664833; cv=none; d=zohomail.com; s=zohoarc; b=YZ8W4pXjhiFilXMZy1FmLCFEHELM7yWxONz5XAsV8F9gTZMzh+92JBnAUDdrCdtPgbvR/t1cwGLviDD2L2KFAAqecEm/FX9JA6u4/Re/3rm/KOl/GSAYDtt6Wznz08PATK6p+ooABpR4IT5LPaebQ6jpIx5mwe0RV7Jc4DUpJRg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695664833; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YhVdZG5ANHQJ4UjAGD7i9HzzdNRsmYRrsil2YQszby0=; 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.57.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:57:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664672; x=1696269472; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YhVdZG5ANHQJ4UjAGD7i9HzzdNRsmYRrsil2YQszby0=; b=lb4eKKmwZlSqqJoq6UzECgBiTM7D5G4NYTF4zwG4jP/IccYrcfdQx7dpCv7z3Yfr4U gt9kw4DtdQ6Kars18VDShbKHW1bpXXKVHeI75c84i1bYw9DHTOsjZ8HHTJCAtaVnk/VI tU7J7jjakRn6id1rVUFTun30WzY55JN78W7HUDifoq5fQmQMDL2TY6IAK1ocIYupgh9V MUACNYBLNI+KxdPl+SihAxSpZvAry5Efhcf5DGCLBn5IUDnu979QXqZWbDTCfEBho9yB eSVi8CmxxlZDx3pUz0+8EyzIsFA0ecrnqf12PswbA859MqBwmuTyfFHkr7qoyw+NaYWH aW0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664672; x=1696269472; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YhVdZG5ANHQJ4UjAGD7i9HzzdNRsmYRrsil2YQszby0=; b=nNZER0ynKKVVQ/AYMaQ+5g+Dlw4QoddWUjokG19W0WZjVnU6mFoyj0SU/AcA2gHoq1 2CGBRZwJeKIumzZk74sMiU6SDzHZvBsYVZJGWPzAOqUCRdA4y3jfO7jtaa/RiPSyWi7t 06AAgjG/ueUG4MxbQdtS4/viRmvk44e9hYS7xnQuxNBqPWsoLYTTnWLG/INIO/NeadYd LYLhfySyElmXd0j57SgJ2F6J85bL5HbPJfXJi/2aCY/4b1OO7NkfUzVoES443l2adhvb uR7eVSQ0xz1dt5iUSBkMT/PT6og/nayfPjzT/uEpRuSxf7QV63RbXbqtT9C1am8WcTLW msgQ== X-Gm-Message-State: AOJu0YwFndx8Bx8kGfanmAgby2Fwic9mKhiGzrcBv8y0A9ydsH9uTDx6 alyskF5dEI9M1DlkwiYUd/96EQ7JyExEKxmOMnM= X-Google-Smtp-Source: AGHT+IGmqDVhp3G+ZuZzRoWh2IUc7JaZx2jdHe44KR+UjwfHhqnBUWGdEti6obgzJDrV13sln8R6Hg== X-Received: by 2002:a17:90a:aa81:b0:274:77df:50cd with SMTP id l1-20020a17090aaa8100b0027477df50cdmr5067152pjq.9.1695664672279; Mon, 25 Sep 2023 10:57:52 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v4 12/19] target/riscv: move KVM only files to kvm subdir Date: Mon, 25 Sep 2023 14:57:02 -0300 Message-ID: <20230925175709.35696-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664834110100001 Content-Type: text/plain; charset="utf-8" Move the files to a 'kvm' dir to promote more code separation between accelerators and making our lives easier supporting build options such as --disable-tcg. Rename kvm.c to kvm-cpu.c to keep it in line with its TCG counterpart. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- hw/intc/riscv_aplic.c | 2 +- hw/riscv/virt.c | 2 +- target/riscv/cpu.c | 2 +- target/riscv/{kvm.c =3D> kvm/kvm-cpu.c} | 0 target/riscv/{ =3D> kvm}/kvm_riscv.h | 0 target/riscv/kvm/meson.build | 1 + target/riscv/meson.build | 2 +- 7 files changed, 5 insertions(+), 4 deletions(-) rename target/riscv/{kvm.c =3D> kvm/kvm-cpu.c} (100%) rename target/riscv/{ =3D> kvm}/kvm_riscv.h (100%) create mode 100644 target/riscv/kvm/meson.build diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 99aae8ccbe..c677b5cfbb 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -32,7 +32,7 @@ #include "target/riscv/cpu.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" -#include "kvm_riscv.h" +#include "kvm/kvm_riscv.h" #include "migration/vmstate.h" =20 #define APLIC_MAX_IDC (1UL << 14) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 5edc1d98d2..9de578c756 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -35,7 +35,7 @@ #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" -#include "kvm_riscv.h" +#include "kvm/kvm_riscv.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/riscv_aplic.h" #include "hw/intc/riscv_imsic.h" diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c8a19be1af..51567c2f12 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -33,7 +33,7 @@ #include "fpu/softfloat-helpers.h" #include "sysemu/kvm.h" #include "sysemu/tcg.h" -#include "kvm_riscv.h" +#include "kvm/kvm_riscv.h" #include "tcg/tcg.h" =20 /* RISC-V CPU definitions */ diff --git a/target/riscv/kvm.c b/target/riscv/kvm/kvm-cpu.c similarity index 100% rename from target/riscv/kvm.c rename to target/riscv/kvm/kvm-cpu.c diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h similarity index 100% rename from target/riscv/kvm_riscv.h rename to target/riscv/kvm/kvm_riscv.h diff --git a/target/riscv/kvm/meson.build b/target/riscv/kvm/meson.build new file mode 100644 index 0000000000..7e92415091 --- /dev/null +++ b/target/riscv/kvm/meson.build @@ -0,0 +1 @@ +riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm-cpu.c')) diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 3323b78b84..c53962215f 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -24,7 +24,6 @@ riscv_ss.add(files( 'zce_helper.c', 'vcrypto_helper.c' )) -riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 riscv_system_ss =3D ss.source_set() riscv_system_ss.add(files( @@ -39,6 +38,7 @@ riscv_system_ss.add(files( )) =20 subdir('tcg') +subdir('kvm') =20 target_arch +=3D {'riscv': riscv_ss} target_softmmu_arch +=3D {'riscv': riscv_system_ss} --=20 2.41.0 From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.57.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:57:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664675; x=1696269475; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nj6OwZ0oE0h4rMXiVHPydgLZMcuLmtXGaJHicDsuVXw=; b=ORm8a7Iq2vZ3lEcZt6iqLSQmEfyrjgTidrlGC/Nr5p8KbefxAWJXp8uVewBsrTvPCK ay4uujoCofvoNOZPO9UXB2XckCRrV7X+j6WfQvJN5RzygOBE7C/PsY8VfgqsMDAic6OI omcBLGg+7QyDmHwmTGqrpeO3sLTKwCl6y+CspCcGZfjz/Mym88mJfG+QOFKf/FgqpI/p Qmshok11x54mdykWzvPNHyXv1+86MvMeAhBiBCW8+1OwYGvM8IhzX5qX2wrNtpdkMAEI fvl0J8Gu/pXzPe5YZPTVqZrwtj936l1s3xBoxvGLLPVSvcR9Zds+AOmA4LuXhX817YOG fZ8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664675; x=1696269475; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nj6OwZ0oE0h4rMXiVHPydgLZMcuLmtXGaJHicDsuVXw=; b=jVEngAtrJwXO5N4Wz36ssMH9Pp8B9IsoQENY9iS6332FDS8++3n7+2ek7qTsjAdsT5 wnSGm6ayU2RnRkT5H1DiONjt/MDW68YwIz77nFyKxXXpbQeL451ggy/mNKzkRNFtgNYv Ty8VJT4F6J92lPqQ3Y0Sf2R6+CWxVM2AVgCo2/CQ/EOLgsmblrYPLUTiEqsVo6QFZNRq r2s4AOBRD+ti+wMtscMDQw1FVWgMls61fBpWqFsLyjFZcYT49xqqrU1TOj5B57eggj0U LEyAn79TYt5YAdTYXLsNZFBMfV/GBsQSUQUrj9TaMmIoCAhWp8iUzWwYPBw69Jcyz0gn V5YQ== X-Gm-Message-State: AOJu0YwMq6ezmJWhyiaTFKcfX86FdIaE4Xm3as1VdeXkbVJ7FQ4FRomp OWV69f3OpaF+dDNWcb/1YXVXp8VJII8y6M+G1bA= X-Google-Smtp-Source: AGHT+IGHxaEXSpVbMzMCIkxeFifiXfeomVP0AtXIvsDQw8khkK6HoIWExeo1mNy3UfJnTlNbIVv2Nw== X-Received: by 2002:a17:90b:4f83:b0:263:f630:228f with SMTP id qe3-20020a17090b4f8300b00263f630228fmr7409021pjb.23.1695664675231; Mon, 25 Sep 2023 10:57:55 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v4 13/19] target/riscv/kvm: do not use riscv_cpu_add_misa_properties() Date: Mon, 25 Sep 2023 14:57:03 -0300 Message-ID: <20230925175709.35696-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664752097100013 Content-Type: text/plain; charset="utf-8" riscv_cpu_add_misa_properties() is being used to fill the missing KVM MISA properties but it is a TCG helper that was adapted to do so. We'll move it to tcg-cpu.c in the next patches, meaning that KVM needs to fill the remaining MISA properties on its own. Do not use riscv_cpu_add_misa_properties(). Let's create a new array with all available MISA bits we support that can be read by KVM. The array is zero terminate to allow us to iterate through it without knowing its size. Then, inside kvm_riscv_add_cpu_user_properties(), we'll create all KVM MISA properties as usual and then use this array to add any missing MISA properties with the riscv_cpu_add_kvm_unavail_prop() helper. Note that we're creating misa_bits[], and not using the existing 'riscv_single_letter_exts[]', because the latter is tuned for riscv,isa related functions and it doesn't have all MISA bits we support. Commit 0e2c377023 ("target/riscv: misa to ISA string conversion fix") has the full context. While we're at it, move both satp and the multi-letter extension properties to kvm_riscv_add_cpu_user_properties() as well. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 3 ++- target/riscv/kvm/kvm-cpu.c | 22 ++++++++++++++-------- 3 files changed, 18 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 51567c2f12..665c21af6a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -38,6 +38,8 @@ =20 /* RISC-V CPU definitions */ static const char riscv_single_letter_exts[] =3D "IEMAFDQCPVH"; +const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF, RVD, RVV, + RVC, RVS, RVU, RVH, RVJ, RVG, 0}; =20 struct isa_ext_data { const char *name; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cb13464ba6..7235eafc1a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -43,7 +43,7 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) =20 /* - * Consider updating misa_ext_info_arr[] and misa_ext_cfgs[] + * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] * when adding new MISA bits here. */ #define RVI RV('I') @@ -60,6 +60,7 @@ #define RVJ RV('J') #define RVG RV('G') =20 +extern const uint32_t misa_bits[]; const char *riscv_get_misa_ext_name(uint32_t bit); const char *riscv_get_misa_ext_description(uint32_t bit); =20 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 606fdab223..c6615cb807 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -396,6 +396,8 @@ static void kvm_riscv_add_cpu_user_properties(Object *c= pu_obj) { int i; =20 + riscv_add_satp_mode_properties(cpu_obj); + for (i =3D 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { KVMCPUConfig *misa_cfg =3D &kvm_misa_ext_cfgs[i]; int bit =3D misa_cfg->offset; @@ -411,6 +413,11 @@ static void kvm_riscv_add_cpu_user_properties(Object *= cpu_obj) misa_cfg->description); } =20 + for (i =3D 0; misa_bits[i] !=3D 0; i++) { + const char *ext_name =3D riscv_get_misa_ext_name(misa_bits[i]); + riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); + } + for (i =3D 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { KVMCPUConfig *multi_cfg =3D &kvm_multi_ext_cfgs[i]; =20 @@ -427,6 +434,10 @@ static void kvm_riscv_add_cpu_user_properties(Object *= cpu_obj) object_property_add(cpu_obj, "cboz_blocksize", "uint16", NULL, kvm_cpu_set_cbomz_blksize, NULL, &kvm_cboz_blocksize); + + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_e= xts); } =20 static int kvm_riscv_get_regs_core(CPUState *cs) @@ -801,7 +812,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, = KVMScratchCPU *kvmcpu) } } =20 -static void riscv_init_user_properties(Object *cpu_obj) +static void riscv_init_kvm_registers(Object *cpu_obj) { RISCVCPU *cpu =3D RISCV_CPU(cpu_obj); KVMScratchCPU kvmcpu; @@ -810,7 +821,6 @@ static void riscv_init_user_properties(Object *cpu_obj) return; } =20 - kvm_riscv_add_cpu_user_properties(cpu_obj); kvm_riscv_init_machine_ids(cpu, &kvmcpu); kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); @@ -1324,13 +1334,9 @@ static void kvm_cpu_instance_init(CPUState *cs) Object *obj =3D OBJECT(RISCV_CPU(cs)); DeviceState *dev =3D DEVICE(obj); =20 - riscv_init_user_properties(obj); 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.57.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:57:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664678; x=1696269478; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xcAl6E4VVn0xmnPGiZOmfp8Zyclb9/WUAcvfkWYFhf0=; b=FWiNpKm2ZiCfpZdgos4jfySHUWcOXU+/l7tI/EzHnAuLcI//aPYS/gY14JFpUaDoY/ nCMtwsngl6ae9jArAvWytvBIcMPkxxSQba/0KrRvHq0lnTE8dJLmOusDHDIDNROVDGVY bXRIo60LTkDEI7WPryiu28/G/LmiZLAPJVheWIhmhWoWHnCk99Ba4o1MQYrTivnoSvWW MYVIhusJdk3eTILAUVx+/kkvWb23NFVvpvQvaijTxWAHndH4EwpeMnIaB1MNk90SJViH nkBIAkMsT2H6G6SCM0cRVFqDGiNnFangZI3k0kaKyA/e+SlUPUPK254w5WBgrTVwqOUS +Byw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664678; x=1696269478; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xcAl6E4VVn0xmnPGiZOmfp8Zyclb9/WUAcvfkWYFhf0=; b=MLIkK/VlzkE5b9wPLj0nD3064x+CkEj6atdn23EtZSpY4w2S09oz5VefCDxgbG6DyR 95J8AsoXlPQAP6IsSj7MEDBx47TJMPx3V6I4EjzVy3YILY5HLuKXmI80Jo9Ig6GQpolI yk+flXSHQTAhilfeLq+ZesSIEdIPxohhE4+VT2ceRBde4UdwMwNWsKaDLc6iAITj9uE0 UpzZAEnyJfvGSl2E0/E5QZR974bASl0/Gz6v/P7CqEOHwmqE8OEym8Fc+/bhXEULnV/U fYklruBGEtxgbTUPE7OMNluytZkFy+HD06AZ82rnFMFPSsBn7R0I0tspxcHzpI5XnL3f dZOg== X-Gm-Message-State: AOJu0Yze6gW4FszpbrO//EHNlcaHg2Wx0Mt53ztXTPNE52o/AnDJBvVH zO9yWKQ6f3OJ/lcNxvSER0FeBER+XjUcvnTZtCI= X-Google-Smtp-Source: AGHT+IF05uzZCoszzqIKAC4kZoMMGRRz9tOwnz51tSkmAoCM6E3kT4xXISZWhO3xNWFrrI64azOT/A== X-Received: by 2002:a17:90a:890a:b0:267:fb26:32bd with SMTP id u10-20020a17090a890a00b00267fb2632bdmr6131149pjn.7.1695664678537; Mon, 25 Sep 2023 10:57:58 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Jones Subject: [PATCH v4 14/19] target/riscv/cpu.c: export set_misa() Date: Mon, 25 Sep 2023 14:57:04 -0300 Message-ID: <20230925175709.35696-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664749930100003 We'll move riscv_init_max_cpu_extensions() to tcg-cpu.c in the next patch and set_misa() needs to be usable from there. Rename it to riscv_cpu_set_misa() and make it public. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 34 ++++++++++++++++++---------------- target/riscv/cpu.h | 1 + 2 files changed, 19 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 665c21af6a..cf191d576e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -294,7 +294,7 @@ const char *riscv_cpu_get_trap_name(target_ulong cause,= bool async) } } =20 -static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) +void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) { env->misa_mxl_max =3D env->misa_mxl =3D mxl; env->misa_ext_mask =3D env->misa_ext =3D ext; @@ -399,9 +399,9 @@ static void riscv_any_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; #if defined(TARGET_RISCV32) - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | = RVU); #elif defined(TARGET_RISCV64) - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | = RVU); #endif =20 #ifndef CONFIG_USER_ONLY @@ -428,7 +428,7 @@ static void riscv_max_cpu_init(Object *obj) #ifdef TARGET_RISCV32 mlx =3D MXL_RV32; #endif - set_misa(env, mlx, 0); + riscv_cpu_set_misa(env, mlx, 0); env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), mlx =3D=3D MXL_RV32 ? @@ -441,7 +441,7 @@ static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, MXL_RV64, 0); + riscv_cpu_set_misa(env, MXL_RV64, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -453,7 +453,8 @@ static void rv64_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + riscv_cpu_set_misa(env, MXL_RV64, + RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); @@ -471,7 +472,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -488,7 +489,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); + riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_11_0; =20 cpu->cfg.ext_zfa =3D true; @@ -519,7 +520,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); + riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); env->priv_ver =3D PRIV_VERSION_1_12_0; =20 /* Enable ISA extensions */ @@ -564,7 +565,7 @@ static void rv128_base_cpu_init(Object *obj) } CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, MXL_RV128, 0); + riscv_cpu_set_misa(env, MXL_RV128, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -576,7 +577,7 @@ static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, MXL_RV32, 0); + riscv_cpu_set_misa(env, MXL_RV32, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -588,7 +589,8 @@ static void rv32_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + riscv_cpu_set_misa(env, MXL_RV32, + RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); @@ -606,7 +608,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -623,7 +625,7 @@ static void rv32_ibex_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_11_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -641,7 +643,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -1618,7 +1620,7 @@ static void riscv_init_max_cpu_extensions(Object *obj) const RISCVCPUMultiExtConfig *prop; =20 /* Enable RVG, RVJ and RVV that are disabled by default */ - set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); + riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV= ); =20 for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { isa_ext_update_enabled(cpu, prop->offset, true); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7235eafc1a..9ec0805596 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -713,6 +713,7 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext= _offset, bool en); bool cpu_cfg_ext_is_user_set(uint32_t ext_offset); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); int cpu_cfg_ext_get_min_version(uint32_t ext_offset); +void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); =20 typedef struct RISCVCPUMultiExtConfig { --=20 2.41.0 From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695664799; cv=none; d=zohomail.com; s=zohoarc; b=gNjmnMK9+gGiwU5EHQgaJH5NT8S46BydZa9iBgWNjbIVRMrMr3pzr5S7fntRF6TfWvY7nyZAkAC+DoYTY8tn3rkmAmgGRl13LdhVPZoRXzXxITC0RE17xb30oIdmN0lrDY/ew/m0KCBTXziOiC05DdcjD7/LD7IlN3+vkqFAKX4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695664799; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.57.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:58:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664681; x=1696269481; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AATH1d0EH+CW85hIdXtiW9XhMpw4Ijx1Pp941W8oPRc=; b=B/nQTQNtQf9kA6IoXyxmpAEpFakdtlv7cDsXlr/ZLmHZmmlKt8akH/TlycAFHiGG0I kVfJl+uXQVnYhGu/29h5TBajME+AaMo0/F9+N42wZp+m62XWILJreGR0wkMsOgiDa1y2 rCZ2ahnOn2hSzQaTyOo/wIeJxJ8qzByI1sCYb9tlfaWwuJ2GOWALY788CJf2x+8nICvN C/F2sINifUCd31aCANbpthj7MGjzvi1EdULdCvH05Ak0jEKiJjJuqR2Ko4No7u5/Wd83 dIvOHd9wgE3f8r9ixOOMVKbgCePBrUK/V7KcMG3ctGzqFm19DBfLUpgWO7TCotpRjToV o9Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664681; x=1696269481; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AATH1d0EH+CW85hIdXtiW9XhMpw4Ijx1Pp941W8oPRc=; b=O5zMg6gZcdlQ4Qur7dh09M4lF5S3uhzsqW/3w0okWyahpBYaD+W1WtS8cL+5WIRt1b 5KNoLuUeMDF2p/mIin87gbUeazpNolk+lFdQlmbwoAzT30iwvLeCCGWzob41JlLsAO5l d/9v2MJf1SdcYShJgqNsD3CVHvjhepHjvCOY0ZtCwVKPIUVd4c0O2tV8h+1+YO8bSzto zLgjuDgma6Ciojc4C/vLasFN7tLmBSiGfUFSCnE8o6Lll3X2KrTSHIDR93hviaDvgMF4 K5qwMYOmTnG5o5l98ke4IwiV1WbgWn7UnlB0vUpc+kPa99IZQdcPfnybaXeaWgDQDgQF sX5g== X-Gm-Message-State: AOJu0YwRAnRUskIzbNebPwn4/O2qLGxKudcuTSB2/tIf5+lKNBt/58h1 Bsy5cLOwgLnNL826am6gmKNTYk9u6yK5cfrASoU= X-Google-Smtp-Source: AGHT+IGjL3SyxGywx4IbF7AxOlmyqx+iIbDryKtVVB7dGxxfjBC2AOWxb69WxwVHpLVUf5btxps4UQ== X-Received: by 2002:a17:90b:2388:b0:268:4c01:eb56 with SMTP id mr8-20020a17090b238800b002684c01eb56mr5339418pjb.2.1695664681496; Mon, 25 Sep 2023 10:58:01 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v4 15/19] target/riscv/tcg: introduce tcg_cpu_instance_init() Date: Mon, 25 Sep 2023 14:57:05 -0300 Message-ID: <20230925175709.35696-16-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664801239100001 Content-Type: text/plain; charset="utf-8" tcg_cpu_instance_init() will be the 'cpu_instance_init' impl for the TCG accelerator. It'll be called from within riscv_cpu_post_init(), via accel_cpu_instance_init(), similar to what happens with KVM. In fact, to preserve behavior, the implementation will be similar to what riscv_cpu_post_init() already does. In this patch we'll move riscv_cpu_add_user_properties() and riscv_init_max_cpu_extensions() and all their dependencies to tcg-cpu.c. All multi-extension properties code was moved. The 'multi_ext_user_opts' hash table was also moved to tcg-cpu.c since it's a TCG only structure, meaning that we won't have to worry about initializing a TCG hash table when running a KVM CPU anymore. riscv_cpu_add_user_properties() will remain in cpu.c for now due to how much code it requires to be moved at the same time. We'll do that in the next patch. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 150 ------------------------------------- target/riscv/cpu.h | 1 - target/riscv/tcg/tcg-cpu.c | 149 ++++++++++++++++++++++++++++++++++++ 3 files changed, 149 insertions(+), 151 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cf191d576e..8616c9e2f5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -162,9 +162,6 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaC= ondOps), }; =20 -/* Hash that stores user set extensions */ -static GHashTable *multi_ext_user_opts; - bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) { bool *ext_enabled =3D (void *)&cpu->cfg + ext_offset; @@ -194,12 +191,6 @@ int cpu_cfg_ext_get_min_version(uint32_t ext_offset) g_assert_not_reached(); } =20 -bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) -{ - return g_hash_table_contains(multi_ext_user_opts, - GUINT_TO_POINTER(ext_offset)); -} - const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -280,9 +271,6 @@ static const char * const riscv_intr_names[] =3D { "reserved" }; =20 -static void riscv_cpu_add_user_properties(Object *obj); -static void riscv_init_max_cpu_extensions(Object *obj); - const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { if (async) { @@ -1206,32 +1194,9 @@ static bool riscv_cpu_is_dynamic(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; } =20 -static bool riscv_cpu_has_max_extensions(Object *cpu_obj) -{ - return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) !=3D NULL; -} - -static bool riscv_cpu_has_user_properties(Object *cpu_obj) -{ - if (kvm_enabled() && - object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) !=3D NULL) { - return true; - } - - return riscv_cpu_is_dynamic(cpu_obj); -} - static void riscv_cpu_post_init(Object *obj) { accel_cpu_instance_init(CPU(obj)); - - if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) { - riscv_cpu_add_user_properties(obj); - } - - if (riscv_cpu_has_max_extensions(obj)) { - riscv_init_max_cpu_extensions(obj); - } } =20 static void riscv_cpu_init(Object *obj) @@ -1244,8 +1209,6 @@ static void riscv_cpu_init(Object *obj) qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); #endif /* CONFIG_USER_ONLY */ - - multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); } =20 typedef struct RISCVCPUMisaExtConfig { @@ -1531,119 +1494,6 @@ Property riscv_cpu_options[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, - void *opaque, Error **errp) -{ - const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; - bool value; - - if (!visit_type_bool(v, name, &value, errp)) { - return; - } - - isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value); - - g_hash_table_insert(multi_ext_user_opts, - GUINT_TO_POINTER(multi_ext_cfg->offset), - (gpointer)value); -} - -static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, - void *opaque, Error **errp) -{ - const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; - bool value =3D isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offse= t); - - visit_type_bool(v, name, &value, errp); -} - -static void cpu_add_multi_ext_prop(Object *cpu_obj, - const RISCVCPUMultiExtConfig *multi_cfg) -{ - object_property_add(cpu_obj, multi_cfg->name, "bool", - cpu_get_multi_ext_cfg, - cpu_set_multi_ext_cfg, - NULL, (void *)multi_cfg); - - /* - * Set def val directly instead of using - * object_property_set_bool() to save the set() - * callback hash for user inputs. - */ - isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, - multi_cfg->enabled); -} - -static void riscv_cpu_add_multiext_prop_array(Object *obj, - const RISCVCPUMultiExtConfig *arra= y) -{ - const RISCVCPUMultiExtConfig *prop; - - g_assert(array); - - for (prop =3D array; prop && prop->name; prop++) { - cpu_add_multi_ext_prop(obj, prop); - } -} - -/* - * Add CPU properties with user-facing flags. - * - * This will overwrite existing env->misa_ext values with the - * defaults set via riscv_cpu_add_misa_properties(). - */ -static void riscv_cpu_add_user_properties(Object *obj) -{ -#ifndef CONFIG_USER_ONLY - riscv_add_satp_mode_properties(obj); -#endif - - riscv_cpu_add_misa_properties(obj); - - riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); - riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); - riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); - - for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { - qdev_property_add_static(DEVICE(obj), prop); - } -} - -/* - * The 'max' type CPU will have all possible ratified - * non-vendor extensions enabled. - */ -static void riscv_init_max_cpu_extensions(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - const RISCVCPUMultiExtConfig *prop; - - /* Enable RVG, RVJ and RVV that are disabled by default */ - riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV= ); - - for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { - isa_ext_update_enabled(cpu, prop->offset, true); - } - - /* set vector version */ - env->vext_ver =3D VEXT_VERSION_1_00_0; - - /* Zfinx is not compatible with F. Disable it */ - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); - - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); - - if (env->misa_mxl !=3D MXL_RV32) { - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); - } -} - static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9ec0805596..01cbcbe119 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -710,7 +710,6 @@ enum riscv_pmu_event_idx { =20 /* used by tcg/tcg-cpu.c*/ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); -bool cpu_cfg_ext_is_user_set(uint32_t ext_offset); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); int cpu_cfg_ext_get_min_version(uint32_t ext_offset); void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 7d890823bd..ac3cf4c035 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -24,6 +24,7 @@ #include "pmu.h" #include "time_helper.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "qemu/accel.h" #include "qemu/error-report.h" #include "qemu/log.h" @@ -31,6 +32,15 @@ #include "hw/core/tcg-cpu-ops.h" #include "tcg/tcg.h" =20 +/* Hash that stores user set extensions */ +static GHashTable *multi_ext_user_opts; + +static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) +{ + return g_hash_table_contains(multi_ext_user_opts, + GUINT_TO_POINTER(ext_offset)); +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -570,6 +580,144 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **e= rrp) return true; } =20 +static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value); + + g_hash_table_insert(multi_ext_user_opts, + GUINT_TO_POINTER(multi_ext_cfg->offset), + (gpointer)value); +} + +static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; + bool value =3D isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offse= t); + + visit_type_bool(v, name, &value, errp); +} + +static void cpu_add_multi_ext_prop(Object *cpu_obj, + const RISCVCPUMultiExtConfig *multi_cfg) +{ + object_property_add(cpu_obj, multi_cfg->name, "bool", + cpu_get_multi_ext_cfg, + cpu_set_multi_ext_cfg, + NULL, (void *)multi_cfg); + + /* + * Set def val directly instead of using + * object_property_set_bool() to save the set() + * callback hash for user inputs. + */ + isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, + multi_cfg->enabled); +} + +static void riscv_cpu_add_multiext_prop_array(Object *obj, + const RISCVCPUMultiExtConfig *arra= y) +{ + const RISCVCPUMultiExtConfig *prop; + + g_assert(array); + + for (prop =3D array; prop && prop->name; prop++) { + cpu_add_multi_ext_prop(obj, prop); + } +} + +/* + * Add CPU properties with user-facing flags. + * + * This will overwrite existing env->misa_ext values with the + * defaults set via riscv_cpu_add_misa_properties(). + */ +static void riscv_cpu_add_user_properties(Object *obj) +{ +#ifndef CONFIG_USER_ONLY + riscv_add_satp_mode_properties(obj); +#endif + + riscv_cpu_add_misa_properties(obj); + + riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); + riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); + riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); + + for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { + qdev_property_add_static(DEVICE(obj), prop); + } +} + +/* + * The 'max' type CPU will have all possible ratified + * non-vendor extensions enabled. + */ +static void riscv_init_max_cpu_extensions(Object *obj) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + const RISCVCPUMultiExtConfig *prop; + + /* Enable RVG, RVJ and RVV that are disabled by default */ + riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV= ); + + for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { + isa_ext_update_enabled(cpu, prop->offset, true); + } + + /* set vector version */ + env->vext_ver =3D VEXT_VERSION_1_00_0; + + /* Zfinx is not compatible with F. Disable it */ + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); + + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); + + if (env->misa_mxl !=3D MXL_RV32) { + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); + } +} + +static bool riscv_cpu_has_max_extensions(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) !=3D NULL; +} + +static bool riscv_cpu_has_user_properties(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; +} + +static void tcg_cpu_instance_init(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + Object *obj =3D OBJECT(cpu); + + if (riscv_cpu_has_user_properties(obj)) { + multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); + riscv_cpu_add_user_properties(obj); + } + + if (riscv_cpu_has_max_extensions(obj)) { + riscv_init_max_cpu_extensions(obj); + } +} + static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) { /* @@ -588,6 +736,7 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, v= oid *data) AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); =20 acc->cpu_class_init =3D tcg_cpu_class_init; + acc->cpu_instance_init =3D tcg_cpu_instance_init; acc->cpu_realizefn =3D tcg_cpu_realizefn; } =20 --=20 2.41.0 From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695664812; cv=none; d=zohomail.com; s=zohoarc; b=C06aRVMIIfGpvtrKw+flnvzwRhYfhjTzNKoJOCMOC6ogKbP+FiM0rXgd7PWf9aCB35f61k+NA4uVTqafdHlLJWcW8LGJ+vPkLqBMXGBouXxZq2ofhjiO/5RVB77Q0ah27un3H8tu4BdU/LQlomJyPMBtIFSqP2TP9Jhd+pHmFOQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695664812; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pPRdKO6FGSbBSFrOgeddG0LVwoijigHLj3i7YRRgCqE=; b=eZP51aaFOMBk2n4kQcXhIa2b4Ado9p9feO9a+Po2bdWqevZsnrU10aSXmIhc2etSTWdmPEeZDvyHVclcxjDC19YDmPn0pr3i5djwT8PK/Q4aa2hbXQRIGY5uT5lZC/WPQTsoYMSd+1vZ+o2/nLXcu9YUjJ6cvy6vp0+eAeX47fg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695664812948161.4145908084107; Mon, 25 Sep 2023 11:00:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qkpqT-0001WK-Hg; Mon, 25 Sep 2023 13:58:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkpqR-0001JQ-NA for qemu-devel@nongnu.org; Mon, 25 Sep 2023 13:58:07 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qkpqQ-0002G9-3A for qemu-devel@nongnu.org; Mon, 25 Sep 2023 13:58:07 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1c364fb8a4cso63287965ad.1 for ; Mon, 25 Sep 2023 10:58:05 -0700 (PDT) Received: from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.58.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:58:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664684; x=1696269484; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pPRdKO6FGSbBSFrOgeddG0LVwoijigHLj3i7YRRgCqE=; b=bZVEw0B8qGTISaDvP4ChJtEd4XdCPsuKOyl/ItS4qFPlaetnCFQ1dZpesr0uzBf7j1 jZVpUMWysCVI0lFPEMVSDM9pv+yvvZpjrYOT4xMSSuQG9/dmoA3MF7DBxe0ysCmANqEj D2adjpWid9G2FJw0ExThs6mHeADG7p4dirwa3vgtrsGhiZe42ilBroBzFOJDXRssYdrL O3ixOGqfxRpJTlkzkMV+7y2/eT3vkP/tdfTESZ3dJyK+I1IUuNoPbsyUEXY5cMDH/bco Gb59RqSN1sDua6AcBJlqO3zJkYSK4m3fPW6E6XWQ7f1ODhbatQHp42Nhfp/Z5Ub8yhVY f3PA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664684; x=1696269484; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pPRdKO6FGSbBSFrOgeddG0LVwoijigHLj3i7YRRgCqE=; b=RMNTfWw08UvIaUrdrfEthRdWz/bLpXYl+bhxXccuVI78Is1r6Ko91i8H2xuoeys0Ny 9T52FIbr95lPtx5ox1tm5XnaKqUkjiWgKE7UZNyulKKAMq51xfP15QHAlLjwT3GvKEAR FOpoiHJHpHvUk/C3CzqCfpmdjUwFuZ4mYof6otU4nE5INoUGiPGL2lRvdxVT0qA8rAla yNW1N0tYXswHGFZFxXKrCleJFmtkZbRGbxqHUb8dosLM1cd7tNDGP14oAeTQ/A9PPsNS bBHpLXzMN+RGbUk/A/1kCIiijiHdWiuLf8gs3PPBu9MnOWXEg3t0Z9zIMAgvUfNuklCZ XItA== X-Gm-Message-State: AOJu0YyB4eBRQzIAdPRDMzp7CQIeBwdmkMZhnnkR6NkAsbZNjQgHWFOX 5xqdcfVHKbn0wuyGpS+RxAPABVDPR8DvRHgfdkg= X-Google-Smtp-Source: AGHT+IGfNaRjGmUdIh3FiQU3HIdOStWD2B2D4tTS1lm3Q/cYDWu6XS+O/P/+dUa6eg6E/eDVQJiojw== X-Received: by 2002:a17:90a:9745:b0:277:2d2d:9a37 with SMTP id i5-20020a17090a974500b002772d2d9a37mr5537539pjw.4.1695664684573; Mon, 25 Sep 2023 10:58:04 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v4 16/19] target/riscv/cpu.c: make misa_ext_cfgs[] 'const' Date: Mon, 25 Sep 2023 14:57:06 -0300 Message-ID: <20230925175709.35696-17-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664814245100001 Content-Type: text/plain; charset="utf-8" The array isn't marked as 'const' because we're initializing their elements in riscv_cpu_add_misa_properties(), 'name' and 'description' fields. In a closer look we can see that we're not using these 2 fields after creating the MISA properties. And we can create the properties by using riscv_get_misa_ext_name() and riscv_get_misa_ext_description() directly. Remove the 'name' and 'description' fields from RISCVCPUMisaExtConfig and make misa_ext_cfgs[] a const array. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8616c9e2f5..4875feded7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1212,8 +1212,6 @@ static void riscv_cpu_init(Object *obj) } =20 typedef struct RISCVCPUMisaExtConfig { - const char *name; - const char *description; target_ulong misa_bit; bool enabled; } RISCVCPUMisaExtConfig; @@ -1317,7 +1315,7 @@ const char *riscv_get_misa_ext_description(uint32_t b= it) #define MISA_CFG(_bit, _enabled) \ {.misa_bit =3D _bit, .enabled =3D _enabled} =20 -static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { MISA_CFG(RVA, true), MISA_CFG(RVC, true), MISA_CFG(RVD, true), @@ -1344,25 +1342,22 @@ void riscv_cpu_add_misa_properties(Object *cpu_obj) int i; =20 for (i =3D 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { - RISCVCPUMisaExtConfig *misa_cfg =3D &misa_ext_cfgs[i]; + const RISCVCPUMisaExtConfig *misa_cfg =3D &misa_ext_cfgs[i]; int bit =3D misa_cfg->misa_bit; - - misa_cfg->name =3D riscv_get_misa_ext_name(bit); - misa_cfg->description =3D riscv_get_misa_ext_description(bit); + const char *name =3D riscv_get_misa_ext_name(bit); + const char *desc =3D riscv_get_misa_ext_description(bit); =20 /* Check if KVM already created the property */ - if (object_property_find(cpu_obj, misa_cfg->name)) { + if (object_property_find(cpu_obj, name)) { continue; } =20 - object_property_add(cpu_obj, misa_cfg->name, "bool", + object_property_add(cpu_obj, name, "bool", cpu_get_misa_ext_cfg, cpu_set_misa_ext_cfg, NULL, (void *)misa_cfg); - object_property_set_description(cpu_obj, misa_cfg->name, - misa_cfg->description); - object_property_set_bool(cpu_obj, misa_cfg->name, - misa_cfg->enabled, NULL); + object_property_set_description(cpu_obj, name, desc); + object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL); } } =20 --=20 2.41.0 From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695664750; cv=none; d=zohomail.com; s=zohoarc; b=gwZbGhJVn73EPDrFRQt2jOMqRbtyME5xLMKlUkviotbDEWdY24GBr/jy/gp65FYaWM8lwfsP7rOFlNRYDSBjQz1WsUoZxjypWSFuARJ3nb7Tb/s0OoJ3klTrKS3jeFzCApHDlvTpzTiijfbdqF9D34RnjbrkczHTlAJiIzQM/TI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695664750; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kho0Cg0LudHauk4flCAc4GR46StMyKT+p69RKBrUZjA=; b=lZAdfKWAUHm9SC7ifgoZywOurIAe1ZObHn0c04zqeQeQkBi0/G4bRWn5lv/HW68NCRz8+ht/7VodsHYJiZFOX7ZiczfjUzkrmX1P0UxjLNiLxgTE2p6F3jlS/bijUERnZoRUuUDznThXz7phxdaN4+xepk+DINX6wleorxBvlFM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695664750391177.64897576375552; Mon, 25 Sep 2023 10:59:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qkpqY-00020h-Eh; Mon, 25 Sep 2023 13:58:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkpqW-0001vS-AP for qemu-devel@nongnu.org; Mon, 25 Sep 2023 13:58:12 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qkpqU-0002Hu-B4 for qemu-devel@nongnu.org; Mon, 25 Sep 2023 13:58:12 -0400 Received: by mail-pj1-x102e.google.com with SMTP id 98e67ed59e1d1-2776ca9adb7so1057477a91.1 for ; Mon, 25 Sep 2023 10:58:09 -0700 (PDT) Received: from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.58.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:58:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664687; x=1696269487; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kho0Cg0LudHauk4flCAc4GR46StMyKT+p69RKBrUZjA=; b=TuAc9lUw78I8Umh+U+WAPyfh4tTOargMRagftdz3XlqF5QUMZd5SyEA76CLd5E8TSy FAKUJolBG5ui3vX83+O6ztZcfnZFIoNMYoz2SJCsGmxIhYxUlp0Kw3ikgRpw9ZKaptJl nyrmS1+kSht0ppEpsi0Mz1tdnUOJuK8WF1eJ224Ca7x+WBB8sCiiLtXzJymr/ro8P+Dr 8J4TNm7SGi9Lx8ONkIJbHJed2Zw89NLo8SNaTYpKVJLIekAwOYBmZd8dXzeBCTWug698 m8XntON379DDfa3di1bXtZgF91GWoBl29CKrQcU11PLTwR8e0/krwTOR047+kHXZ+X84 WBrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664687; x=1696269487; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kho0Cg0LudHauk4flCAc4GR46StMyKT+p69RKBrUZjA=; b=lnMeNWEq28hiyWz7eeI4qdNwsEF17mOe1h0mNiJrQ7thm+1JcmG4nzaJ5KgfcaBeu7 f1aTVkXlTVesCC7lyJZHpBF88zHfeK5RX1FhTVhY+xy/Qot7/BXHUZUGE3oG5JPmmKCQ 4jw7E5LVNy+kyfsyx1iTTthDGcF/OV9BSFyPOT+1iF3ztN1IuZ1lu/yGHBhAO/KTVkhH ORtRhE+j2MQVNrj9mTiL9gIm+uJbSIygMqDdmWtnvmUU3BSAI4zikYk3uyNIdK2tFHsc 4MVt6HKpMpO0Ehikd1fe076Cy4tArPbnhiNwCmrUOl2ADtxRWX881QMkZ7UWLlsuByZ5 EsXg== X-Gm-Message-State: AOJu0YzvMocaix3JkqAwCop0pYB7kmZEvrcx0kOgdiCcI2etd8xGTLg2 nMJF2dwKVrKS5kkSdbE8blbTmG8AK6sN0205+tM= X-Google-Smtp-Source: AGHT+IEzTxiECIFJJgUUVcif2Pdv9fbcVAo+g9k+6dapo42/BMn8UjabhBrAkCr2/Clnk89+aPp4BA== X-Received: by 2002:a17:90a:728e:b0:274:6503:26d with SMTP id e14-20020a17090a728e00b002746503026dmr4901847pjg.33.1695664687605; Mon, 25 Sep 2023 10:58:07 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v4 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c Date: Mon, 25 Sep 2023 14:57:07 -0300 Message-ID: <20230925175709.35696-18-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664751322100009 Content-Type: text/plain; charset="utf-8" All code related to MISA TCG properties is also moved. At this point, all TCG properties handling is done in tcg-cpu.c, all KVM properties handling is done in kvm-cpu.c. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 90 -------------------------------------- target/riscv/cpu.h | 1 - target/riscv/tcg/tcg-cpu.c | 90 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 90 insertions(+), 91 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4875feded7..46263e55d5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1211,47 +1211,6 @@ static void riscv_cpu_init(Object *obj) #endif /* CONFIG_USER_ONLY */ } =20 -typedef struct RISCVCPUMisaExtConfig { - target_ulong misa_bit; - bool enabled; -} RISCVCPUMisaExtConfig; - -static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; - target_ulong misa_bit =3D misa_ext_cfg->misa_bit; - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - bool value; - - if (!visit_type_bool(v, name, &value, errp)) { - return; - } - - if (value) { - env->misa_ext |=3D misa_bit; - env->misa_ext_mask |=3D misa_bit; - } else { - env->misa_ext &=3D ~misa_bit; - env->misa_ext_mask &=3D ~misa_bit; - } -} - -static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; - target_ulong misa_bit =3D misa_ext_cfg->misa_bit; - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - bool value; - - value =3D env->misa_ext & misa_bit; - - visit_type_bool(v, name, &value, errp); -} - typedef struct misa_ext_info { const char *name; const char *description; @@ -1312,55 +1271,6 @@ const char *riscv_get_misa_ext_description(uint32_t = bit) return val; } =20 -#define MISA_CFG(_bit, _enabled) \ - {.misa_bit =3D _bit, .enabled =3D _enabled} - -static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { - MISA_CFG(RVA, true), - MISA_CFG(RVC, true), - MISA_CFG(RVD, true), - MISA_CFG(RVF, true), - MISA_CFG(RVI, true), - MISA_CFG(RVE, false), - MISA_CFG(RVM, true), - MISA_CFG(RVS, true), - MISA_CFG(RVU, true), - MISA_CFG(RVH, true), - MISA_CFG(RVJ, false), - MISA_CFG(RVV, false), - MISA_CFG(RVG, false), -}; - -/* - * We do not support user choice tracking for MISA - * extensions yet because, so far, we do not silently - * change MISA bits during realize() (RVG enables MISA - * bits but the user is warned about it). - */ -void riscv_cpu_add_misa_properties(Object *cpu_obj) -{ - int i; - - for (i =3D 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { - const RISCVCPUMisaExtConfig *misa_cfg =3D &misa_ext_cfgs[i]; - int bit =3D misa_cfg->misa_bit; - const char *name =3D riscv_get_misa_ext_name(bit); - const char *desc =3D riscv_get_misa_ext_description(bit); - - /* Check if KVM already created the property */ - if (object_property_find(cpu_obj, name)) { - continue; - } - - object_property_add(cpu_obj, name, "bool", - cpu_get_misa_ext_cfg, - cpu_set_misa_ext_cfg, - NULL, (void *)misa_cfg); - object_property_set_description(cpu_obj, name, desc); - object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL); - } -} - #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \ {.name =3D _name, .offset =3D CPU_CFG_OFFSET(_prop), \ .enabled =3D _defval} diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 01cbcbe119..aba8192c74 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -726,7 +726,6 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_ex= ts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; extern Property riscv_cpu_options[]; =20 -void riscv_cpu_add_misa_properties(Object *cpu_obj); void riscv_add_satp_mode_properties(Object *obj); =20 /* CSR function table */ diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index ac3cf4c035..8065572703 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -580,6 +580,96 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **er= rp) return true; } =20 +typedef struct RISCVCPUMisaExtConfig { + target_ulong misa_bit; + bool enabled; +} RISCVCPUMisaExtConfig; + +static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; + target_ulong misa_bit =3D misa_ext_cfg->misa_bit; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + if (value) { + env->misa_ext |=3D misa_bit; + env->misa_ext_mask |=3D misa_bit; + } else { + env->misa_ext &=3D ~misa_bit; + env->misa_ext_mask &=3D ~misa_bit; + } +} + +static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; + target_ulong misa_bit =3D misa_ext_cfg->misa_bit; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + bool value; + + value =3D env->misa_ext & misa_bit; + + visit_type_bool(v, name, &value, errp); +} + +#define MISA_CFG(_bit, _enabled) \ + {.misa_bit =3D _bit, .enabled =3D _enabled} + +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { + MISA_CFG(RVA, true), + MISA_CFG(RVC, true), + MISA_CFG(RVD, true), + MISA_CFG(RVF, true), + MISA_CFG(RVI, true), + MISA_CFG(RVE, false), + MISA_CFG(RVM, true), + MISA_CFG(RVS, true), + MISA_CFG(RVU, true), + MISA_CFG(RVH, true), + MISA_CFG(RVJ, false), + MISA_CFG(RVV, false), + MISA_CFG(RVG, false), +}; + +/* + * We do not support user choice tracking for MISA + * extensions yet because, so far, we do not silently + * change MISA bits during realize() (RVG enables MISA + * bits but the user is warned about it). + */ +static void riscv_cpu_add_misa_properties(Object *cpu_obj) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { + const RISCVCPUMisaExtConfig *misa_cfg =3D &misa_ext_cfgs[i]; + int bit =3D misa_cfg->misa_bit; + const char *name =3D riscv_get_misa_ext_name(bit); + const char *desc =3D riscv_get_misa_ext_description(bit); + + /* Check if KVM already created the property */ + if (object_property_find(cpu_obj, name)) { + continue; + } + + object_property_add(cpu_obj, name, "bool", + cpu_get_misa_ext_cfg, + cpu_set_misa_ext_cfg, + NULL, (void *)misa_cfg); + object_property_set_description(cpu_obj, name, desc); + object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL); + } +} + static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, void *opaque, Error **errp) { --=20 2.41.0 From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.58.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:58:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664691; x=1696269491; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/8Lb13b8Q/wdMsJx/GAamGQYB3Fb73dJbrCOvlq3S4k=; b=ox8KKazUdBSUHHJ6J5yePxA1dX8BfTpGwg9thK/QzLZjfB3aPrWp8fIXgIKOtMN13F gLdHGe30pTLPrgJOE21WJmFDvlu+wuZU9yyQWJ656eDHggaZ50qYX53AJT3OJKg8tmTM CmuAAgt1cwtym6maBzz+trKtHDrRCdtImUc6N7exrWYu5MQk5T8uR2EF4Ogbk7Tkk4hF +Nw4hdFr6EbdhDs3iLX5bRH4O2aj/YRjJ7BNYqsKlrpnECLi3StbPMaIk98hHABYd+o0 mL7HMqEBNgn33KQXkvohou1/B7tpaIpNf57ZnUTp/TA0P/5reMV1EM/eBbmvgN+6eebf JRXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664691; x=1696269491; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/8Lb13b8Q/wdMsJx/GAamGQYB3Fb73dJbrCOvlq3S4k=; b=bzLh0Tfwd6oHknyfRDXBFgyqNS6aQDiSydqcJXCnKEntKxluAVDC+VTj8GvGykmJ1+ H6KUVUX7O0TDzrzpM0IBR7G18wtqMsu7+pY/r8IpJJN0cofReagPwofz3VRN2Mi66uZ4 wI7WUYujytQHmf2dMyIVDf/tzI6zNIiF1Rs0eSm1+3NdbZJhFFu3mC0CKinWFdugJP+f POx68ulaahLlmuBwosdyX+psCHsh//2seJW+KdI/9MX3eYpB0qb9QhoVbuwsO2BOA9uT yk3OAAgq3j4MR5iV40EI5sEPn38guoMk3j0/NgLYnc8bRPke3TnMSfH5+ViuE4oj5GWa nbMg== X-Gm-Message-State: AOJu0YzHSVpL0jfoVtQHRVdwx2uT1nzSQN/CmyduwGM5mmjiPV3bBGpe lKVUhpKV/FQcAzxcwDgM1z0qkwAsuytV7YKUz44= X-Google-Smtp-Source: AGHT+IHLzAEvZqG8sOZQVLEYfZcXsgxitWtrSVfZhjNYeBDY1/ZOP6MasktAsYiBBuSODbjWDhA5ag== X-Received: by 2002:a17:90a:a795:b0:26f:2c5a:bbb3 with SMTP id f21-20020a17090aa79500b0026f2c5abbb3mr6489443pjq.40.1695664690732; Mon, 25 Sep 2023 10:58:10 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v4 18/19] target/riscv/cpu.c: export isa_edata_arr[] Date: Mon, 25 Sep 2023 14:57:08 -0300 Message-ID: <20230925175709.35696-19-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664836160100007 Content-Type: text/plain; charset="utf-8" This array will be read by the TCG accel class, allowing it to handle priv spec verifications on its own. The array will remain here in cpu.c because it's also used by the riscv,isa string function. To export it we'll finish it with an empty element since ARRAY_SIZE() won't work outside of cpu.c. Get rid of its ARRAY_SIZE() usage now to alleviate the changes for the next patch. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 47 +++++++++++++++++++++------------------------- target/riscv/cpu.h | 7 +++++++ 2 files changed, 28 insertions(+), 26 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 46263e55d5..e97ba3df93 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -41,15 +41,6 @@ static const char riscv_single_letter_exts[] =3D "IEMAFD= QCPVH"; const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF, RVD, RVV, RVC, RVS, RVU, RVH, RVJ, RVG, 0}; =20 -struct isa_ext_data { - const char *name; - int min_version; - int ext_enable_offset; -}; - -#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ - {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} - /* * From vector_helper.c * Note that vector data is stored in host-endian 64-bit chunks, @@ -61,6 +52,9 @@ struct isa_ext_data { #define BYTE(x) (x) #endif =20 +#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ + {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} + /* * Here are the ordering rules of extension naming defined by RISC-V * specification : @@ -81,7 +75,7 @@ struct isa_ext_data { * Single letter extensions are checked in riscv_cpu_validate_misa_priv() * instead. */ -static const struct isa_ext_data isa_edata_arr[] =3D { +const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), @@ -160,6 +154,8 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempa= ir), ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaC= ondOps), + + DEFINE_PROP_END_OF_LIST(), }; =20 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) @@ -178,14 +174,14 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t e= xt_offset, bool en) =20 int cpu_cfg_ext_get_min_version(uint32_t ext_offset) { - int i; + const RISCVIsaExtData *edata; =20 - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_edata_arr[i].ext_enable_offset !=3D ext_offset) { + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (edata->ext_enable_offset !=3D ext_offset) { continue; } =20 - return isa_edata_arr[i].min_version; + return edata->min_version; } =20 g_assert_not_reached(); @@ -932,22 +928,21 @@ static void riscv_cpu_disas_set_info(CPUState *s, dis= assemble_info *info) void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) { CPURISCVState *env =3D &cpu->env; - int i; + const RISCVIsaExtData *edata; =20 /* Force disable extensions if priv spec version does not match */ - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) && - (env->priv_ver < isa_edata_arr[i].min_version)) { - isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset, - false); + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && + (env->priv_ver < edata->min_version)) { + isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); #ifndef CONFIG_USER_ONLY warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx " because privilege spec version does not match", - isa_edata_arr[i].name, env->mhartid); + edata->name, env->mhartid); #else warn_report("disabling %s extension because " "privilege spec version does not match", - isa_edata_arr[i].name); + edata->name); #endif } } @@ -1619,13 +1614,13 @@ static void riscv_cpu_class_init(ObjectClass *c, vo= id *data) static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) { + const RISCVIsaExtData *edata; char *old =3D *isa_str; char *new =3D *isa_str; - int i; =20 - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) { - new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) { + new =3D g_strconcat(old, "_", edata->name, NULL); g_free(old); old =3D new; } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index aba8192c74..3dfcd0732f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -726,6 +726,13 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_e= xts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; extern Property riscv_cpu_options[]; =20 +typedef struct isa_ext_data { + const char *name; + int min_version; + int ext_enable_offset; +} RISCVIsaExtData; +extern const RISCVIsaExtData isa_edata_arr[]; + void riscv_add_satp_mode_properties(Object *obj); =20 /* CSR function table */ --=20 2.41.0 From nobody Sat May 18 18:27:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id i3-20020a17090a65c300b00262ca945cecsm3312722pjs.54.2023.09.25.10.58.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 10:58:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695664694; x=1696269494; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HINIOygEUHoFZdk34h9R7GIclIFZRpgk7MoX3CjEPDU=; b=Vi6oBX8k5XQDW6QYLrRa5pnP6r4pnju2y5D2YytJ8W+YDG3UbfFMb6E9GAVBAe1JbX jr1YMsKjkH8iVkRmUyq5UdbxKItiB1mUh7a0F9li4pkec7iijj1NiUCGYcavSFYehLsL EazLdmw4eAfV9ku7rz1A8EiyzYcZJspdxX4FlrWyvyV2hc9Jm3CfBcz6HXtKUIVYeM8y wWgy/WCc3gSPG56dazPf8yMTPDXe4elTq09/ZDBNiYV6NWE7ixLFYMH7UiR3dpfBCNO4 bliv1w5VHi9yRfbVkCQgRc3wdtyeo4tSX6rvsWn52mCgb+jcMefJUFK2VLgusDewFFkJ /agg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695664694; x=1696269494; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HINIOygEUHoFZdk34h9R7GIclIFZRpgk7MoX3CjEPDU=; b=oamsZVUS/EVdWCW4eQibRGMfvBx01aRupTy8Eu74JgQNJR/aNUZ6ztISQ0p+3/OO9i JkpC0b8SWm9t64iJ28L3PqIUVdNgXnIjBocY16YsW0hOhDslqu1C4KsbLe1Z9pfIioWN mf09L3QqdrwtcKySfNZFYV+zkIYxdIOP5di6xNQJpT96picD1kdcnW+ZK/1w29sZvifB ZNwKWzQ7Y563IeiihUNdqwbd653WkhQYaywRJ3z+zKS/qdJ1Da/3yLQyGAc0ixOct7zh /h2Y7kIx7UjeNlYQ41pIjxvElroCMmMmb8NT01ExfFQtKngrNMN2KKtlmdF5xRIT+AJt 9KPA== X-Gm-Message-State: AOJu0YyvZHm7sCR80wgASDku16iuZRx9mSHSbuLzw6Qv8wnLRl0bmTAP qpWO5W9O2ESsK0lOcWBi7j4KTeaifJbyE20ng8Y= X-Google-Smtp-Source: AGHT+IERn2HJNUxK7Gg1upd04g6cNCYLE6hBLjNflddf2BDR9Zh1pWzd1lBVkkr74AhuA91mGdh0fg== X-Received: by 2002:a17:90a:f298:b0:269:6c5:11a7 with SMTP id fs24-20020a17090af29800b0026906c511a7mr5197967pjb.17.1695664694000; Mon, 25 Sep 2023 10:58:14 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza , Andrew Jones , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c Date: Mon, 25 Sep 2023 14:57:09 -0300 Message-ID: <20230925175709.35696-20-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925175709.35696-1-dbarboza@ventanamicro.com> References: <20230925175709.35696-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695664840895100001 Priv spec validation is TCG specific. Move it to the TCG accel class. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.c | 38 -------------------------------------- target/riscv/cpu.h | 2 -- target/riscv/tcg/tcg-cpu.c | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 38 insertions(+), 40 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e97ba3df93..eeeb08a35a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -172,21 +172,6 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ex= t_offset, bool en) *ext_enabled =3D en; } =20 -int cpu_cfg_ext_get_min_version(uint32_t ext_offset) -{ - const RISCVIsaExtData *edata; - - for (edata =3D isa_edata_arr; edata && edata->name; edata++) { - if (edata->ext_enable_offset !=3D ext_offset) { - continue; - } - - return edata->min_version; - } - - g_assert_not_reached(); -} - const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -925,29 +910,6 @@ static void riscv_cpu_disas_set_info(CPUState *s, disa= ssemble_info *info) } } =20 -void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) -{ - CPURISCVState *env =3D &cpu->env; - const RISCVIsaExtData *edata; - - /* Force disable extensions if priv spec version does not match */ - for (edata =3D isa_edata_arr; edata && edata->name; edata++) { - if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && - (env->priv_ver < edata->min_version)) { - isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); -#ifndef CONFIG_USER_ONLY - warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx - " because privilege spec version does not match", - edata->name, env->mhartid); -#else - warn_report("disabling %s extension because " - "privilege spec version does not match", - edata->name); -#endif - } - } -} - #ifndef CONFIG_USER_ONLY static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3dfcd0732f..219fe2e9b5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -711,9 +711,7 @@ enum riscv_pmu_event_idx { /* used by tcg/tcg-cpu.c*/ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); -int cpu_cfg_ext_get_min_version(uint32_t ext_offset); void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); -void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); =20 typedef struct RISCVCPUMultiExtConfig { const char *name; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8065572703..674cc57b32 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -99,6 +99,21 @@ static const struct TCGCPUOps riscv_tcg_ops =3D { #endif /* !CONFIG_USER_ONLY */ }; =20 +static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) +{ + const RISCVIsaExtData *edata; + + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (edata->ext_enable_offset !=3D ext_offset) { + continue; + } + + return edata->min_version; + } + + g_assert_not_reached(); +} + static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) { @@ -226,6 +241,29 @@ static void riscv_cpu_validate_v(CPURISCVState *env, R= ISCVCPUConfig *cfg, } } =20 +static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) +{ + CPURISCVState *env =3D &cpu->env; + const RISCVIsaExtData *edata; + + /* Force disable extensions if priv spec version does not match */ + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && + (env->priv_ver < edata->min_version)) { + isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); +#ifndef CONFIG_USER_ONLY + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx + " because privilege spec version does not match", + edata->name, env->mhartid); +#else + warn_report("disabling %s extension because " + "privilege spec version does not match", + edata->name); +#endif + } + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. --=20 2.41.0