From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695317891; cv=none; d=zohomail.com; s=zohoarc; b=lR2d9twfAbCqBWauE60+YiGfH+PV9LQM/XPRYHhAjXgsGPaf19Z+i/GQbctlkX6DpZcbFWkjeaLtaCvyHFlbFYexgX7MjoEaM6vOXy2IWpD8usfxSQb4zJec9KqHnkVHA2R7j/YGAEcR+fCJXiLhgTeDLUvdqSEgwyI32b2PmbI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695317891; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cjcMhrWP1zUiCzEV4lG0uJngonIBEvy+btrPgJEisu0=; b=fpp6tb7/IeCZ/NZrXMpyqlJGmVh+8QnMTiEZCqmeK5z9vMFUypPC8LFANhFrptROCfKJpS5sPpa8/Fq+GH7N1Dd3Xndzcl0TQ2lfmr1gNH/u+7M1BaV32cOeIOVyciD6Xn7Q1kJtosDD6+c7oQT1/L8YcztUtQj7n654h7lPSG8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695317891833285.31572205614896; Thu, 21 Sep 2023 10:38:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNcG-0001z3-H1; Thu, 21 Sep 2023 13:37:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNcF-0001yo-PP for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:27 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcC-0007ec-T6 for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:26 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-4050bd2e33aso13258845e9.2 for ; Thu, 21 Sep 2023 10:37:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317843; x=1695922643; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=cjcMhrWP1zUiCzEV4lG0uJngonIBEvy+btrPgJEisu0=; b=ZmT4WFRMk7QcaJROC4mRgvp9Uot9EFcCVW51NP03HbpW6QUcQDHsFaMcw0Vp6CC3th WoW2ZOunKQUcyXXGs8G5vWqEwWbBRbpisE/+9dFwc6zwRp376h9Eh2N48b0aG4IynjKN ZhAAqxYI/GDn9CeY6Y1tEcT3mMyZcpMh194BTOVTA//j5R7UGziOaywHYAMafcEv8ebU W+FH+IWH8Lx6gS2Fp0mpVW9QYPJ2qpZTpYTgbpqFf8+WIB4+u8LbWXWdguHRNfOpIos2 nqO0WaWMfHtFoYQtegocMn2kP7jaec/3K2XWsltFmnAWi959++yKO7Sn/woD//OSxswE XuQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317843; x=1695922643; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cjcMhrWP1zUiCzEV4lG0uJngonIBEvy+btrPgJEisu0=; b=rMXg770+hgEWe5nd+OlfcHBSdtznLav6R9jGp8Ksnl0fsu6VqImQXflUqyw4TyOKg2 Gvwti1KMyCXLF1hj6zUaKzvoE/hXOBE0zSuLW4SK2Ky/HNLIV3ulDre27F2NGXr1qiJq Gbdqe6LocV7p37WErcIuCcWVcO++NS2KZodtnJbwAlf1Ph0kYAPuw9UfWeEr4oFFo3A5 up926mkOHDjDzI2LD3KJKQM/jE3hMa2DTd7ksqrmgw/9+ppiN0j9Gnxfz4Q56D8zdwrH EbRbUk+c7NJIoZdUeNRWHw1BNi+4xEWsOcZt6nffZDT3HDual4k3j6VpAzK0cIRDVrGa Nd+A== X-Gm-Message-State: AOJu0Yxv9i50R28QFhV7mCyrc+k8CzWQE9E2I36oFughCmlw6XFNH2wt K+ftdSSn2DZSerfiFUZfz5ubN6ai9pIxm4tcOzY= X-Google-Smtp-Source: AGHT+IGoRRQbp1anf43RadeToNyDDEb3kow7gx947Qod20fFwTxM0H4/MgrccE6FuS1oxCR2RGCiQQ== X-Received: by 2002:a7b:ca5a:0:b0:402:bda9:74d1 with SMTP id m26-20020a7bca5a000000b00402bda974d1mr5967870wml.8.1695317843084; Thu, 21 Sep 2023 10:37:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/30] target/m68k: Add URL to semihosting spec Date: Thu, 21 Sep 2023 18:36:51 +0100 Message-Id: <20230921173720.3250581-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695317892481100003 The spec for m68k semihosting is documented in the libgloss sources. Add a comment with the URL for it, as we already have for nios2 semihosting. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230801154451.3505492-1-peter.maydell@linaro.org --- target/m68k/m68k-semi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c index 239f6e44e90..80cd8d70dbb 100644 --- a/target/m68k/m68k-semi.c +++ b/target/m68k/m68k-semi.c @@ -15,6 +15,10 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, see . + * + * The semihosting protocol implemented here is described in the + * libgloss sources: + * https://sourceware.org/git/?p=3Dnewlib-cygwin.git;a=3Dblob;f=3Dlibglos= s/m68k/m68k-semi.txt;hb=3DHEAD */ =20 #include "qemu/osdep.h" --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695317914; cv=none; d=zohomail.com; s=zohoarc; b=M3tnfp6oObc1NZUsJDqJPJ9o7YqBzY1mV2aTkKaA99DQeEoiTnGn4Igtya+SgXx9igVYP3bsJnyuUdly3kgc0Fw1RbxqhBCdQ04kjnRQziHJHtc72FHAdSpxjP3CQsnudXF5N4Ik4oSV2alMsHjdzk2VevI3LzvQltXY2T6rmsw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695317914; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XhGk3GBdxEvMx812AhOFNtmmzN8nojmeRnwh2UQUEnk=; b=UPSPc+dWBw1oyhYZ4r5EKDD3DZuPdQcEOc2GQ4ZDqwcCjzARg3Fp1DV6nHIwzQv5ho9WGuO3E4NcFwuRhZ2KRfFyZnsY0LpTYetgJyWfs0q1DLAg3aJ3L4VDQzsmgTWqK0coES/zeT/g0bGAVn3w9XcyfeRC9uR3iEiHx6G0O7I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695317914623563.4829849362092; Thu, 21 Sep 2023 10:38:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNcG-0001z4-HB; Thu, 21 Sep 2023 13:37:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNcF-0001yn-Ou for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:27 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcC-0007ef-TO for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:27 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-403012f27e3so13316735e9.3 for ; Thu, 21 Sep 2023 10:37:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317843; x=1695922643; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=XhGk3GBdxEvMx812AhOFNtmmzN8nojmeRnwh2UQUEnk=; b=IHt3hQwZwB+9hQDYSjqJ2FRYMaDG2Y/cn0MMZ1o9F1Mi0s1i6vU+nv6jg3APsPBfrG 9ZqNeOSG3FiiCSCbHiSIfTIe0QxRwn6LGgiBKfM9QdUdFWtdnDQiRwzYq/eqKu96x5VE XCFS+svaLfDpyuiaEJmky4r/anUH5UCZs//Nl6noUgjDTedvD3PMInt3bkgysunKsf1M w4neee6/L9mzj3ksyzTB75Dp2hNzihbA3Fj/SCS42MLdL6jSEZmVOLDZSKoydA17AKUB Y16RF5sWLjODvrpsKGLpJIydQCg2OXJKScF0o1xaUO98opXLc89ZuC/CL50IYsSOhTvv RKiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317843; x=1695922643; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XhGk3GBdxEvMx812AhOFNtmmzN8nojmeRnwh2UQUEnk=; b=jMLOu01VKmlk8oXo4ZkUxMfJEGck8jktHeQn1F0Rcb7hDg0c1r20RkXt2A4f9ucKWF Z3QMOS62iAivKe0CxRLObWrWOuE0H6F1Pzu1TU7e9Rs6DMa8aAGBRXakc45oDBl+oeFB ApWe1w8onUNbERzRToIBU2w1uLvGCctxluY+7Id0RjKwrg9xRi0uJEAPGxNTihwM5q7v wNRnK3bjN+l9o3we6QyKsb46H0xGO+CjxMPHQG5EiTADimf1xoXly93GtVnctPxWGaNr BdHWL8mBOpA7+gn1Cj8B03hXgjQqgixAAKi7TDhEP293RMbYLRiWs7DGwSyE5+SjbnJs Efvg== X-Gm-Message-State: AOJu0Yzf+8BpYdNetKNWV0e6s6/hknhn0IaWZdku8HOxmssYO7bmJe/H aukdrbzKtxRitCazvdeCh8wYS85Ba18tfpfP0M0= X-Google-Smtp-Source: AGHT+IFS/bfxvbtjwhtp8jbOwAZX+r6a9adDZY1phpdut+3Qsz3aMLdBkzJjiEwpXNxOZHnII2N6CA== X-Received: by 2002:a05:6000:1108:b0:320:121:2300 with SMTP id z8-20020a056000110800b0032001212300mr5490617wrw.1.1695317843429; Thu, 21 Sep 2023 10:37:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/30] docs/devel/loads-stores: Fix git grep regexes Date: Thu, 21 Sep 2023 18:36:52 +0100 Message-Id: <20230921173720.3250581-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695317915408100005 The loads-and-stores documentation includes git grep regexes to find occurrences of the various functions. Some of these regexes have errors, typically failing to escape the '?', '(' and ')' when they should be metacharacters (since these are POSIX basic REs). We also weren't consistent about whether to have a ':' on the end of the line introducing the list of regexes in each section. Fix the errors. The following shell rune will complain about any REs in the file which don't have any matches in the codebase: for re in $(sed -ne 's/ - ``\(\\<.*\)``/\1/p' docs/devel/loads-stores.rst)= ; do git grep -q "$re" || echo "no matches for re $re"; done Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230904161703.3996734-1-peter.maydell@linaro.org --- docs/devel/loads-stores.rst | 40 ++++++++++++++++++------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/docs/devel/loads-stores.rst b/docs/devel/loads-stores.rst index dab6dfa0acc..ec627aa9c06 100644 --- a/docs/devel/loads-stores.rst +++ b/docs/devel/loads-stores.rst @@ -63,12 +63,12 @@ which stores ``val`` to ``ptr`` as an ``{endian}`` orde= r value of size ``sz`` bytes. =20 =20 -Regexes for git grep +Regexes for git grep: - ``\`` - ``\`` - ``\`` - - ``\`` - - ``\`` + - ``\`` + - ``\`` =20 ``cpu_{ld,st}*_mmu`` ~~~~~~~~~~~~~~~~~~~~ @@ -121,8 +121,8 @@ store: ``cpu_st{size}{end}_mmu(env, ptr, val, oi, retad= dr)`` - ``_le`` : little endian =20 Regexes for git grep: - - ``\`` - - ``\`` + - ``\`` + - ``\`` =20 =20 ``cpu_{ld,st}*_mmuidx_ra`` @@ -155,8 +155,8 @@ store: ``cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmu= idx, retaddr)`` - ``_le`` : little endian =20 Regexes for git grep: - - ``\`` - - ``\`` + - ``\`` + - ``\`` =20 ``cpu_{ld,st}*_data_ra`` ~~~~~~~~~~~~~~~~~~~~~~~~ @@ -193,8 +193,8 @@ store: ``cpu_st{size}{end}_data_ra(env, ptr, val, ra)`` - ``_le`` : little endian =20 Regexes for git grep: - - ``\`` - - ``\`` + - ``\`` + - ``\`` =20 ``cpu_{ld,st}*_data`` ~~~~~~~~~~~~~~~~~~~~~ @@ -231,9 +231,9 @@ store: ``cpu_st{size}{end}_data(env, ptr, val)`` - ``_be`` : big endian - ``_le`` : little endian =20 -Regexes for git grep - - ``\`` - - ``\`` +Regexes for git grep: + - ``\`` + - ``\`` =20 ``cpu_ld*_code`` ~~~~~~~~~~~~~~~~ @@ -296,7 +296,7 @@ swap: ``translator_ld{sign}{size}_swap(env, ptr, swap)`` - ``l`` : 32 bits - ``q`` : 64 bits =20 -Regexes for git grep +Regexes for git grep: - ``\`` =20 ``helper_{ld,st}*_mmu`` @@ -325,7 +325,7 @@ store: ``helper_{size}_mmu(env, addr, val, opindex, ret= addr)`` - ``l`` : 32 bits - ``q`` : 64 bits =20 -Regexes for git grep +Regexes for git grep: - ``\`` - ``\`` =20 @@ -382,7 +382,7 @@ succeeded using a MemTxResult return code. =20 The ``_{endian}`` suffix is omitted for byte accesses. =20 -Regexes for git grep +Regexes for git grep: - ``\`` - ``\`` - ``\`` @@ -400,7 +400,7 @@ Note that portions of the write which attempt to write = data to a device will be silently ignored -- only real RAM and ROM will be written to. =20 -Regexes for git grep +Regexes for git grep: - ``address_space_write_rom`` =20 ``{ld,st}*_phys`` @@ -438,7 +438,7 @@ device doing the access has no way to report such an er= ror. =20 The ``_{endian}_`` infix is omitted for byte accesses. =20 -Regexes for git grep +Regexes for git grep: - ``\`` - ``\`` =20 @@ -462,7 +462,7 @@ For new code they are better avoided: =20 ``cpu_physical_memory_rw`` =20 -Regexes for git grep +Regexes for git grep: - ``\`` =20 ``cpu_memory_rw_debug`` @@ -497,7 +497,7 @@ make sure our existing code is doing things correctly. =20 ``dma_memory_rw`` =20 -Regexes for git grep +Regexes for git grep: - ``\`` - ``\`` - ``\`` @@ -538,7 +538,7 @@ correct address space for that device. =20 The ``_{endian}_`` infix is omitted for byte accesses. =20 -Regexes for git grep +Regexes for git grep: - ``\`` - ``\`` - ``\`` --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317844; x=1695922644; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=PKp1eQrVUMTaEf0w4kuHa7A8lBLx9ISnYKLL0swOrb0=; b=OtHpPxgB1aFkh732mf/gyrDL+qfEn4md+Mccjy3RlnZ25rNGrNExg7pt6t0W2Nbbyg v2j9UohTAxlVEEab5GW6/guMYmz9+hgZl2kHknx5D4owBvtngeGAISUqj+ItdDUVUiUn 3d3NvT4Oeg6KqPC5KxdeIeqR1cshWmId2BRbfUbpzoACeQOymXh03bnQ4OIFBLGx9BSV fQsGkVNrtBrKAQIcbOGVYE5XIjfs9c2NXSNTez5cFm6sP25gjvzXt1C9p7gyDhpJNqmv kxHVUIdSzGiQn+q6G1uZNNNWOwxKHHcJTcJnWEu4RYWE6DVBm1if84G4QyQR5tqk0JQI O9ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317844; x=1695922644; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PKp1eQrVUMTaEf0w4kuHa7A8lBLx9ISnYKLL0swOrb0=; b=DHlxQcH0FYEpurvUKskHjWfpUOX8AMIxX0h9K3ZPdfUbeWqDFPjiC7cGL1q4lWHjmm eS6pgIH2b/1ZiiA6lyuHagGREsP0kvnxJbid2ZxdBD811EOuE8AYxhobAXYSrtdUc2Vw BVPK+pyWTqOszvCVcY3d9XKIpZgLCQAKNhPqOPxijcSKbydSAEKWR6C041MlrImDOhRn JH0D/xW47wJMN0e9OXNAjrZqdGqhlb+isyEe8FZvig4MjvUew7UQXoR73pHHGK50WKZe k9t0ScVP7T1PmkekS+6ubAZVLTramf6L9SR515GGXsEkGXZz8+b04eO7qFbQPYetSWTH 9xpA== X-Gm-Message-State: AOJu0YyghE/SSxH1jdvacKcBba/FrlBCqwPf6sbwPAKY557mzlJ/XaX5 YVA+btT+42uYJwmcEWt6QCn2RjG3P3fM41JhLkQ= X-Google-Smtp-Source: AGHT+IHluQKW8YPXNvY0VdYSbZvMbeBATCGgMkA9eoRCK7VzASNdPRoJOuOR6n5YbvITZJ24PYVmKQ== X-Received: by 2002:a5d:452d:0:b0:321:677d:98b0 with SMTP id j13-20020a5d452d000000b00321677d98b0mr5195203wra.11.1695317843812; Thu, 21 Sep 2023 10:37:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/30] hw/arm/boot: Set SCR_EL3.FGTEn when booting kernel Date: Thu, 21 Sep 2023 18:36:53 +0100 Message-Id: <20230921173720.3250581-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318098959100007 Content-Type: text/plain; charset="utf-8" From: Fabian Vogt Just like d7ef5e16a17c sets SCR_EL3.HXEn for FEAT_HCX, this commit handles SCR_EL3.FGTEn for FEAT_FGT: When we direct boot a kernel on a CPU which emulates EL3, we need to set up the EL3 system registers as the Linux kernel documentation specifies: https://www.kernel.org/doc/Documentation/arm64/booting.rst > For CPUs with the Fine Grained Traps (FEAT_FGT) extension present: > - If EL3 is present and the kernel is entered at EL2: > - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1. Cc: qemu-stable@nongnu.org Signed-off-by: Fabian Vogt Message-id: 4831384.GXAFRqVoOG@linux-e202.suse.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/boot.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 720f22531a6..24fa1690600 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -761,6 +761,10 @@ static void do_cpu_reset(void *opaque) if (cpu_isar_feature(aa64_hcx, cpu)) { env->cp15.scr_el3 |=3D SCR_HXEN; } + if (cpu_isar_feature(aa64_fgt, cpu)) { + env->cp15.scr_el3 |=3D SCR_FGTEN; + } + /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); /* This hook is only supported for AArch32 currently: --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695318143; cv=none; d=zohomail.com; s=zohoarc; b=H6PUuj6GjmlTjVi7BOP2K/Uy3/3207wnm/PsIOq8dVU6ju8xcD80wUfUXwdaXB8yBxT7QyO0HDOv++EFKdPNC2xcsNv2pJJzyZvH6/js2Sw/VvZNdEF0nI1nDYJ+wLYcbIIXx6QL4RbSlEINQ5D8mlabOabYs/CH0WzgvBbZzAk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695318143; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=i8mYcSOzJNDt14r6Qxj12i2esU5F/4qLdh6bfLg75T4=; b=m0XPn2S7IGYc7CcyDONV0eWZTUbjSNlAqZixqSGxqat50fyHHgfbx+yiIXvuq4Wa10Er9CAFvybGv6ao+Gsx7wewBqzJx2kUNrCltTFG59X7MOq4/71eFgTRXc3hWNSp1Zl7qkwyMcWgwMZ3Sqgb9vUv9sM42hlUR5bIzHv4LFY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169531814335544.97351750935252; Thu, 21 Sep 2023 10:42:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNcO-00021g-MN; Thu, 21 Sep 2023 13:37:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNcJ-00020L-OX for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:32 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcE-0007eq-0t for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:31 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-401187f8071so8439615e9.0 for ; Thu, 21 Sep 2023 10:37:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317844; x=1695922644; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=i8mYcSOzJNDt14r6Qxj12i2esU5F/4qLdh6bfLg75T4=; b=RRgyHXsuzOZdXFEHk6ppCKvGE62nzTCe7QiG2umA9q4UvMCyunSIxSMT2p8VmDNRxN KUfs4wsnTbK3dvh9fsXoMQ8YGT27A4ZVVj/TsmC4pVyj/DtSQgYc2VvQdE5v4+IbvXUd Ua6KIUSIGFrEQiNx31ahBkFIfgGQfm3xcBADasV+fRqbFrDTJeLxvNfFY2I37BkxatNT fay8T2rNteRwwNQyu0h+l2RyjYWseL8KOAB98kH81Jm8z0Llk46rP08vFf6pQ3ZWe9k6 WfqaTlO5RBJdy7CIdZIz5u/wNcASVyJxB8PCocavyBqafBElT8p5H8qVFfeit+QhzJb8 gu5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317844; x=1695922644; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i8mYcSOzJNDt14r6Qxj12i2esU5F/4qLdh6bfLg75T4=; b=pWMh1UlfFgsjJK5keS3OE5OKdBs4eMm6BJjg+H09HSmkqO3YtUzTNXwdMxlqw5/+hZ LXH6VUlsLWbbItkvtJ7fKzhbElT7iq+ei3oHwRsEV2VKUB/Mq2xx+IortyTDXhvxtTAU U6lAzdUWBftx2GZyfz8N0hIkfwUm8SVYjWHFo7Z2tfjVsv8jIPCZ/+rFImzZ1ydab1Ex KppezkTTM55DNp/Tp3BrwPu5FHkdxYwt7rKDuhs/0eNgduVESmHIRAZX0oTEKKiLo7vd oGQY1Qhs8jaix22SeMjE3NdS+zJiuGcyBGiH9pfKZh1KXd9o4opsDUbuAGEuN+TpjN3c 9Tzg== X-Gm-Message-State: AOJu0YwlfNJOSwzgFVzxZYhQAmiPnbWj6isQwv221WoUJfd39V/eQJ+8 am2tmi5gj80WWTGtxXDIH63XlQMgYWftc7Z62cU= X-Google-Smtp-Source: AGHT+IFAHej+KMFWsKDvJCkjdXblVdKeePdu+UjdJZsBv57PtrZ8f5NNH89ePI+EMOUncfGG2UKf6A== X-Received: by 2002:a7b:c8cb:0:b0:405:251f:8455 with SMTP id f11-20020a7bc8cb000000b00405251f8455mr257741wml.7.1695317844281; Thu, 21 Sep 2023 10:37:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/30] linux-user/elfload.c: Correct SME feature names reported in cpuinfo Date: Thu, 21 Sep 2023 18:36:54 +0100 Message-Id: <20230921173720.3250581-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318144438100001 Some of the names we use for CPU features in linux-user's dummy /proc/cpuinfo don't match the strings in the real kernel in arch/arm64/kernel/cpuinfo.c. Specifically, the SME related features have an underscore in the HWCAP_FOO define name, but (like the SVE ones) they do not have an underscore in the string in cpuinfo. Correct the errors. Fixes: a55b9e7226708 ("linux-user: Emulate /proc/cpuinfo on aarch64 and arm= ") Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- linux-user/elfload.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index a5b28fa3e7a..5ce009d7137 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -844,13 +844,13 @@ const char *elf_hwcap2_str(uint32_t bit) [__builtin_ctz(ARM_HWCAP2_A64_RPRES )] =3D "rpres", [__builtin_ctz(ARM_HWCAP2_A64_MTE3 )] =3D "mte3", [__builtin_ctz(ARM_HWCAP2_A64_SME )] =3D "sme", - [__builtin_ctz(ARM_HWCAP2_A64_SME_I16I64 )] =3D "sme_i16i64", - [__builtin_ctz(ARM_HWCAP2_A64_SME_F64F64 )] =3D "sme_f64f64", - [__builtin_ctz(ARM_HWCAP2_A64_SME_I8I32 )] =3D "sme_i8i32", - [__builtin_ctz(ARM_HWCAP2_A64_SME_F16F32 )] =3D "sme_f16f32", - [__builtin_ctz(ARM_HWCAP2_A64_SME_B16F32 )] =3D "sme_b16f32", - [__builtin_ctz(ARM_HWCAP2_A64_SME_F32F32 )] =3D "sme_f32f32", - [__builtin_ctz(ARM_HWCAP2_A64_SME_FA64 )] =3D "sme_fa64", + [__builtin_ctz(ARM_HWCAP2_A64_SME_I16I64 )] =3D "smei16i64", + [__builtin_ctz(ARM_HWCAP2_A64_SME_F64F64 )] =3D "smef64f64", + [__builtin_ctz(ARM_HWCAP2_A64_SME_I8I32 )] =3D "smei8i32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_F16F32 )] =3D "smef16f32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_B16F32 )] =3D "smeb16f32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_F32F32 )] =3D "smef32f32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_FA64 )] =3D "smefa64", }; =20 return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695318035; cv=none; d=zohomail.com; s=zohoarc; b=e1uGzyfTLxizWvuS7zuzmkzdEySCFiiQecpwqyMAVO8C4c0H82IrNnZNPcGUvOpHHEoLxinFv+eku6QTFxGLA9dspyM/11cgiPfu1GrBr8D4uyrHH2jiOGBYihx2ZlgEKPuC2CaEK6Zd5tkor2vwn5te3NWjl8yMJVomh1lPlRs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695318035; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YMpZc+ao0tb5Q8uHDZ6byfjSVRiy68kz9Ei7aM1MfcM=; b=VD6pRF65MT4CHscjmtrogknPFKJW++5ZCvZbovgo3i29S9yiBWZ1igpSL4eacykMyylyDMb2/d+JZa/G46mc4AyAqunfDhCT1wf1wJOANlSLb855sKxrJE3Qx8tBTUYr4Wmvn3tl4bst9zIpEKYnHrtVvKNOzgZ5aQf/RP66dTo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695318035359916.7643963884052; Thu, 21 Sep 2023 10:40:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNcP-00022b-AV; Thu, 21 Sep 2023 13:37:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNcL-000210-Ev for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:34 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcE-0007es-6w for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:32 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-401187f8071so8439725e9.0 for ; Thu, 21 Sep 2023 10:37:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317844; x=1695922644; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=YMpZc+ao0tb5Q8uHDZ6byfjSVRiy68kz9Ei7aM1MfcM=; b=lQkv4veMEFHlouWhqyPdE/DHB65dCfRluroMuqLFizmZKNHXZt1UsbUZhqnkmLUWgD ovBac8gUnZkCvon0YQQlfi09bvBbPpNirjNoe+WfLHbnDndT1R9pqs02uED/L/ffKcqf mkAJO4QXfAAI2K7E0BDm4X/Ms6VrJ9/q8Yil9RzHlWa7ATep8nUMh3wXNRfHujoLaNZU IL+kbYC875RCWWj7kSo2B/adHL3Voz9c7Ml34kzixeGX+1WbSfAIk3H4WGy1omCzCNRt 67WVwtsJznazYFW2+Ffueu0sYEP8LOP8VbTina8vjTkF9C9hNRW1Fc1B/gU/B+NYwtu7 9uEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317844; x=1695922644; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YMpZc+ao0tb5Q8uHDZ6byfjSVRiy68kz9Ei7aM1MfcM=; b=jcSsm8iLi8QRJIRAs8zOGh9PE3ux8VnQAWhAXXZ1HP4M27levoXdFVa1Jj5H+Q4tA4 /88/e/YkgSyK88E+2iNEioXFzfMo+74o8tz2HNaUGOcndRi7aZdYPpVc/u0oL2jIohX1 hW99QJB0OkpCHkYCVZay5nKAqOmvJyBgciDfgLS5Sku7ZrwRTT+w4Pbn6QmeV1PiI7t7 wCGk7/regE8F8jAnio2mlPS+syqkW0Y45UjdIPIgJ+D/6LhSnpBpk8LWaN8qQL1XuwKl CHpyFR/3PfiCDa86k55BWVzz7E592EnCjicczjnof6dIlxjK7dRiReI6ITXsBk1mt7l2 9mYQ== X-Gm-Message-State: AOJu0Ywd9TlzOe5ea/W3A6NoqGMye7oFLYOs8Uxnj08WLeJ3gNvm7ctY 6Kuc4Ds39fi9gzlW5DxaAqo+mwFAcSFWbQG/YME= X-Google-Smtp-Source: AGHT+IFTLcBbhrA/0twD58G5gjvsprjXtYz+6PcEK2tQJsn/Q6gpGIGtpL1IHnwbSeYbIOkjN8vWkw== X-Received: by 2002:a05:600c:468f:b0:402:f91e:df80 with SMTP id p15-20020a05600c468f00b00402f91edf80mr262189wmo.3.1695317844647; Thu, 21 Sep 2023 10:37:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/30] linux-user/elfload.c: Add missing arm and arm64 hwcap values Date: Thu, 21 Sep 2023 18:36:55 +0100 Message-Id: <20230921173720.3250581-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318036037100001 Our lists of Arm 32 and 64 bit hwcap values have lagged behind the Linux kernel. Update them to include all the bits defined as of upstream Linux git commit a48fa7efaf1161c1 (in the middle of the kernel 6.6 dev cycle). For 64-bit, we don't yet implement any of the features reported via these hwcap bits. For 32-bit we do in fact already implement them all; we'll add the code to set them in a subsequent commit. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- linux-user/elfload.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 5ce009d7137..d51d077998a 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -402,6 +402,12 @@ enum ARM_HWCAP_ARM_VFPD32 =3D 1 << 19, ARM_HWCAP_ARM_LPAE =3D 1 << 20, ARM_HWCAP_ARM_EVTSTRM =3D 1 << 21, + ARM_HWCAP_ARM_FPHP =3D 1 << 22, + ARM_HWCAP_ARM_ASIMDHP =3D 1 << 23, + ARM_HWCAP_ARM_ASIMDDP =3D 1 << 24, + ARM_HWCAP_ARM_ASIMDFHM =3D 1 << 25, + ARM_HWCAP_ARM_ASIMDBF16 =3D 1 << 26, + ARM_HWCAP_ARM_I8MM =3D 1 << 27, }; =20 enum { @@ -410,6 +416,8 @@ enum { ARM_HWCAP2_ARM_SHA1 =3D 1 << 2, ARM_HWCAP2_ARM_SHA2 =3D 1 << 3, ARM_HWCAP2_ARM_CRC32 =3D 1 << 4, + ARM_HWCAP2_ARM_SB =3D 1 << 5, + ARM_HWCAP2_ARM_SSBS =3D 1 << 6, }; =20 /* The commpage only exists for 32 bit kernels */ @@ -540,6 +548,12 @@ const char *elf_hwcap_str(uint32_t bit) [__builtin_ctz(ARM_HWCAP_ARM_VFPD32 )] =3D "vfpd32", [__builtin_ctz(ARM_HWCAP_ARM_LPAE )] =3D "lpae", [__builtin_ctz(ARM_HWCAP_ARM_EVTSTRM )] =3D "evtstrm", + [__builtin_ctz(ARM_HWCAP_ARM_FPHP )] =3D "fphp", + [__builtin_ctz(ARM_HWCAP_ARM_ASIMDHP )] =3D "asimdhp", + [__builtin_ctz(ARM_HWCAP_ARM_ASIMDDP )] =3D "asimddp", + [__builtin_ctz(ARM_HWCAP_ARM_ASIMDFHM )] =3D "asimdfhm", + [__builtin_ctz(ARM_HWCAP_ARM_ASIMDBF16)] =3D "asimdbf16", + [__builtin_ctz(ARM_HWCAP_ARM_I8MM )] =3D "i8mm", }; =20 return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; @@ -553,6 +567,8 @@ const char *elf_hwcap2_str(uint32_t bit) [__builtin_ctz(ARM_HWCAP2_ARM_SHA1 )] =3D "sha1", [__builtin_ctz(ARM_HWCAP2_ARM_SHA2 )] =3D "sha2", [__builtin_ctz(ARM_HWCAP2_ARM_CRC32)] =3D "crc32", + [__builtin_ctz(ARM_HWCAP2_ARM_SB )] =3D "sb", + [__builtin_ctz(ARM_HWCAP2_ARM_SSBS )] =3D "ssbs", }; =20 return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; @@ -696,6 +712,20 @@ enum { ARM_HWCAP2_A64_SME_B16F32 =3D 1 << 28, ARM_HWCAP2_A64_SME_F32F32 =3D 1 << 29, ARM_HWCAP2_A64_SME_FA64 =3D 1 << 30, + ARM_HWCAP2_A64_WFXT =3D 1ULL << 31, + ARM_HWCAP2_A64_EBF16 =3D 1ULL << 32, + ARM_HWCAP2_A64_SVE_EBF16 =3D 1ULL << 33, + ARM_HWCAP2_A64_CSSC =3D 1ULL << 34, + ARM_HWCAP2_A64_RPRFM =3D 1ULL << 35, + ARM_HWCAP2_A64_SVE2P1 =3D 1ULL << 36, + ARM_HWCAP2_A64_SME2 =3D 1ULL << 37, + ARM_HWCAP2_A64_SME2P1 =3D 1ULL << 38, + ARM_HWCAP2_A64_SME_I16I32 =3D 1ULL << 39, + ARM_HWCAP2_A64_SME_BI32I32 =3D 1ULL << 40, + ARM_HWCAP2_A64_SME_B16B16 =3D 1ULL << 41, + ARM_HWCAP2_A64_SME_F16F16 =3D 1ULL << 42, + ARM_HWCAP2_A64_MOPS =3D 1ULL << 43, + ARM_HWCAP2_A64_HBC =3D 1ULL << 44, }; =20 #define ELF_HWCAP get_elf_hwcap() @@ -851,6 +881,20 @@ const char *elf_hwcap2_str(uint32_t bit) [__builtin_ctz(ARM_HWCAP2_A64_SME_B16F32 )] =3D "smeb16f32", [__builtin_ctz(ARM_HWCAP2_A64_SME_F32F32 )] =3D "smef32f32", [__builtin_ctz(ARM_HWCAP2_A64_SME_FA64 )] =3D "smefa64", + [__builtin_ctz(ARM_HWCAP2_A64_WFXT )] =3D "wfxt", + [__builtin_ctzll(ARM_HWCAP2_A64_EBF16 )] =3D "ebf16", + [__builtin_ctzll(ARM_HWCAP2_A64_SVE_EBF16 )] =3D "sveebf16", + [__builtin_ctzll(ARM_HWCAP2_A64_CSSC )] =3D "cssc", + [__builtin_ctzll(ARM_HWCAP2_A64_RPRFM )] =3D "rprfm", + [__builtin_ctzll(ARM_HWCAP2_A64_SVE2P1 )] =3D "sve2p1", + [__builtin_ctzll(ARM_HWCAP2_A64_SME2 )] =3D "sme2", + [__builtin_ctzll(ARM_HWCAP2_A64_SME2P1 )] =3D "sme2p1", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_I16I32 )] =3D "smei16i32", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_BI32I32)] =3D "smebi32i32", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_B16B16 )] =3D "smeb16b16", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_F16F16 )] =3D "smef16f16", + [__builtin_ctzll(ARM_HWCAP2_A64_MOPS )] =3D "mops", + [__builtin_ctzll(ARM_HWCAP2_A64_HBC )] =3D "hbc", }; =20 return bit < ARRAY_SIZE(hwcap_str) ? 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317845; x=1695922645; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=f4JCz6oW705FmXRb/erPYyuDAbijRvdAgvDYCus9zWk=; b=qlLGZQsBGPwwyTyon1DmDLyIGi0tqkCAtvllaHQI7W/MrQ3WqtKQ0SGHKErdYrr7om J3XMXFrwd3dHLO/Fnt7RojKSu4qiEdcdr21WSxtzXu+Zc/BbnSEn/s1L3AZDYpL3K5Uh d/rgugPVk4Zn84O4lu8k9xCaAIfZRz2IR8S7aeBh1KcM+jFMuqSDxZvWzlmuL6DUFQHb YVMVOE/NkF+KFBJSG17CHAt16UpoeyZe7P8XM8HO86bZgvxhvpOLp94yNwq+PcWG4IDw 3c4JPXZoF+eqhL0LRPBCOzI5gbnFS2NbhbSD75qlBEOc/Euzb0Dhvi4B8hxpBfkdBdLe JuyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317845; x=1695922645; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f4JCz6oW705FmXRb/erPYyuDAbijRvdAgvDYCus9zWk=; b=VZZ/nOnm4zgZCZMrKa+3mPTfCAZwUlzIsloT2O+Y9YQkFoLX7Atz6rfUvSG6rkeuuR /lvFaPLjLQS688RIwBoHdysH18UgE1OSJcG2fzY99GAwWcuz5j7vSiq4LaslDxnpX4pA Ald9MEVfhigN2hN+knZNV/xu1P0/LsFiFWD9JnRNJEoWIp3A5MdT4OiRdDJTr59MEJUM /1QfAmDnRTLoXhmK7jd3PnISG+ehf9Ssg/ZA4MzfBMrHetoF7U//bOGqxP0nypLQYDzh qewwQTGnHmzewSP8nG/jKzpnbTJXuWuAs+B/pNE+8grooxfHNq5WsWiqtbDedL/E0yxB RXmw== X-Gm-Message-State: AOJu0YznNgfL8fPbVF1tI+hfToN5AQYVeyiwqhwlXp8KMGqUHhWEeX7B rXRYlGkRLkyjlr8r0mWZJcIoKdTrjQqdTMIA+bU= X-Google-Smtp-Source: AGHT+IFYnn8gutmAThGQAgO6c69LAwKfPfGMYS4nijGn/ZdaopC3IiR9rkXk8BD9C1gt1UKEsriSMg== X-Received: by 2002:a05:600c:2312:b0:3fe:d71a:d84e with SMTP id 18-20020a05600c231200b003fed71ad84emr5450548wmo.1.1695317845030; Thu, 21 Sep 2023 10:37:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/30] linux-user/elfload.c: Report previously missing arm32 hwcaps Date: Thu, 21 Sep 2023 18:36:56 +0100 Message-Id: <20230921173720.3250581-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695317954401100003 Content-Type: text/plain; charset="utf-8" Add the code to report the arm32 hwcaps we were previously missing: ss, ssbs, fphp, asimdhp, asimddp, asimdfhm, asimdbf16, i8mm Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- linux-user/elfload.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index d51d077998a..bbb4f08109c 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -506,6 +506,16 @@ uint32_t get_elf_hwcap(void) } } GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4); + /* + * MVFR1.FPHP and .SIMDHP must be in sync, and QEMU uses the same + * isar_feature function for both. The kernel reports them as two hwca= ps. + */ + GET_FEATURE_ID(aa32_fp16_arith, ARM_HWCAP_ARM_FPHP); + GET_FEATURE_ID(aa32_fp16_arith, ARM_HWCAP_ARM_ASIMDHP); + GET_FEATURE_ID(aa32_dp, ARM_HWCAP_ARM_ASIMDDP); + GET_FEATURE_ID(aa32_fhm, ARM_HWCAP_ARM_ASIMDFHM); + GET_FEATURE_ID(aa32_bf16, ARM_HWCAP_ARM_ASIMDBF16); + GET_FEATURE_ID(aa32_i8mm, ARM_HWCAP_ARM_I8MM); =20 return hwcaps; } @@ -520,6 +530,8 @@ uint32_t get_elf_hwcap2(void) GET_FEATURE_ID(aa32_sha1, ARM_HWCAP2_ARM_SHA1); GET_FEATURE_ID(aa32_sha2, ARM_HWCAP2_ARM_SHA2); GET_FEATURE_ID(aa32_crc32, ARM_HWCAP2_ARM_CRC32); + GET_FEATURE_ID(aa32_sb, ARM_HWCAP2_ARM_SB); + GET_FEATURE_ID(aa32_ssbs, ARM_HWCAP2_ARM_SSBS); return hwcaps; } =20 --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695317990; cv=none; d=zohomail.com; s=zohoarc; b=JGGSFWA2jBSiicl3+2nhi0334aRNs1AstYGV17EoI3mjnfQI5uunh3PI82CGiQ0jiSHRRS0/luzzas/cSdl3uOBvnLZbSqaDS0dbBu6eTP0GM6HTwnPIVhQvTjvGMbTXmF+ImttsLQHs/orhgFs0dfRRAwLjn0F2PLVdMsdZiao= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695317990; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4t8raamjkiKMFho/Exbq5puDMqJZ2LBIGrDxmNB/Oe8=; b=nibMq7rLcxe59dMtSpACA5o55ZiZ7Ai6jlMV+92uVvuegYcYLYt5HFCZgznduMAatHX4P2F8Etp2HTZGLHTHTjWnyGq8C1SZ1afq1/byzZbgPDjdVRvtfm0NRyIrtoftCtSjZSAzMy6U/s2n30Dqc9+MBzoke81N+7J7NfDq3cI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695317990013769.1919906707165; Thu, 21 Sep 2023 10:39:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNcM-000211-5E; Thu, 21 Sep 2023 13:37:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNcJ-00020I-Mi for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:31 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcG-0007f4-As for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:31 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-4053c6f0d3dso533725e9.1 for ; Thu, 21 Sep 2023 10:37:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695317992027100003 Content-Type: text/plain; charset="utf-8" Update our AArch64 ID register field definitions from the 2023-06 system register XML release: https://developer.arm.com/documentation/ddi0601/2023-06/ Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f2e3dc49a66..7ba2402f727 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2166,6 +2166,7 @@ FIELD(ID_AA64ISAR0, SHA1, 8, 4) FIELD(ID_AA64ISAR0, SHA2, 12, 4) FIELD(ID_AA64ISAR0, CRC32, 16, 4) FIELD(ID_AA64ISAR0, ATOMIC, 20, 4) +FIELD(ID_AA64ISAR0, TME, 24, 4) FIELD(ID_AA64ISAR0, RDM, 28, 4) FIELD(ID_AA64ISAR0, SHA3, 32, 4) FIELD(ID_AA64ISAR0, SM3, 36, 4) @@ -2200,6 +2201,13 @@ FIELD(ID_AA64ISAR2, APA3, 12, 4) FIELD(ID_AA64ISAR2, MOPS, 16, 4) FIELD(ID_AA64ISAR2, BC, 20, 4) FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) +FIELD(ID_AA64ISAR2, CLRBHB, 28, 4) +FIELD(ID_AA64ISAR2, SYSREG_128, 32, 4) +FIELD(ID_AA64ISAR2, SYSINSTR_128, 36, 4) +FIELD(ID_AA64ISAR2, PRFMSLC, 40, 4) +FIELD(ID_AA64ISAR2, RPRFM, 48, 4) +FIELD(ID_AA64ISAR2, CSSC, 52, 4) +FIELD(ID_AA64ISAR2, ATS1A, 60, 4) =20 FIELD(ID_AA64PFR0, EL0, 0, 4) FIELD(ID_AA64PFR0, EL1, 4, 4) @@ -2227,6 +2235,12 @@ FIELD(ID_AA64PFR1, SME, 24, 4) FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) FIELD(ID_AA64PFR1, NMI, 36, 4) +FIELD(ID_AA64PFR1, MTE_FRAC, 40, 4) +FIELD(ID_AA64PFR1, GCS, 44, 4) +FIELD(ID_AA64PFR1, THE, 48, 4) +FIELD(ID_AA64PFR1, MTEX, 52, 4) +FIELD(ID_AA64PFR1, DF2, 56, 4) +FIELD(ID_AA64PFR1, PFAR, 60, 4) =20 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) @@ -2258,6 +2272,7 @@ FIELD(ID_AA64MMFR1, AFP, 44, 4) FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) FIELD(ID_AA64MMFR1, CMOW, 56, 4) +FIELD(ID_AA64MMFR1, ECBHB, 60, 4) =20 FIELD(ID_AA64MMFR2, CNP, 0, 4) FIELD(ID_AA64MMFR2, UAO, 4, 4) @@ -2279,7 +2294,9 @@ FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) FIELD(ID_AA64DFR0, TRACEVER, 4, 4) FIELD(ID_AA64DFR0, PMUVER, 8, 4) FIELD(ID_AA64DFR0, BRPS, 12, 4) +FIELD(ID_AA64DFR0, PMSS, 16, 4) FIELD(ID_AA64DFR0, WRPS, 20, 4) +FIELD(ID_AA64DFR0, SEBEP, 24, 4) FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) FIELD(ID_AA64DFR0, PMSVER, 32, 4) FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) @@ -2287,12 +2304,14 @@ FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) FIELD(ID_AA64DFR0, MTPMU, 48, 4) FIELD(ID_AA64DFR0, BRBE, 52, 4) +FIELD(ID_AA64DFR0, EXTTRCBUFF, 56, 4) FIELD(ID_AA64DFR0, HPMN0, 60, 4) =20 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) FIELD(ID_AA64ZFR0, AES, 4, 4) FIELD(ID_AA64ZFR0, BITPERM, 16, 4) FIELD(ID_AA64ZFR0, BFLOAT16, 20, 4) +FIELD(ID_AA64ZFR0, B16B16, 24, 4) FIELD(ID_AA64ZFR0, SHA3, 32, 4) FIELD(ID_AA64ZFR0, SM4, 40, 4) FIELD(ID_AA64ZFR0, I8MM, 44, 4) @@ -2300,9 +2319,13 @@ FIELD(ID_AA64ZFR0, F32MM, 52, 4) FIELD(ID_AA64ZFR0, F64MM, 56, 4) =20 FIELD(ID_AA64SMFR0, F32F32, 32, 1) +FIELD(ID_AA64SMFR0, BI32I32, 33, 1) FIELD(ID_AA64SMFR0, B16F32, 34, 1) FIELD(ID_AA64SMFR0, F16F32, 35, 1) FIELD(ID_AA64SMFR0, I8I32, 36, 4) +FIELD(ID_AA64SMFR0, F16F16, 42, 1) +FIELD(ID_AA64SMFR0, B16B16, 43, 1) +FIELD(ID_AA64SMFR0, I16I32, 44, 4) FIELD(ID_AA64SMFR0, F64F64, 48, 1) FIELD(ID_AA64SMFR0, I16I64, 52, 4) FIELD(ID_AA64SMFR0, SMEVER, 56, 4) --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317846; x=1695922646; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=P2MjKlOVigf+xWAScg3HKbXgKT5sjpXRoKt4/wbnDZI=; b=FaKgVP2qT3U0DphZ+coVFDGFUCSxRfgOZrJaCgP7UAFtBeSYsHele6DJCB42rBAOHY dsC3mkqbSkybtBzy7ctcPFojenpJxb+81HWW0UyXTpOvf7IjlDt9Nv2gguXC+FdURwhI BbpcnsdnEYe8x3CCqyLzKbaRNkI8zFz386ol5Cktl3eb+533BdGaeX7w/D25ZXIcTz2N faTQQCVhfHFaft4ccuTYfxANTVpa93/MaqOwiaxnZMjFR7xSnGfXAfjQtAWPcPp4JPhP p+YDFIT+ZjaXyyMopbfyBweFTLHEf2vVkI07E4+S3v01HR5yxvbmYW2x3aLpR+yO+Ilk MpMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317846; x=1695922646; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P2MjKlOVigf+xWAScg3HKbXgKT5sjpXRoKt4/wbnDZI=; b=E7ZKZoDaljO6fygHZcyAqJ/+FxFy6RCLxzGYaX1elDrG3qRIoXR5D7gjJzc1FmRz2S xMmR/Nch1dXOxzInCO2U7lWBbIFdm9S+epTN2RmWHwYU5m7fEb8UFhaBX7SqYMLKWaX6 /jwsOIniD1M/JZOaeAhKQ8s0Lnha2m1a/DTzFpSNSOgWi0NW0twTjm1qX18Mop+XW9aB JEDPSLco4bZigqMAhgnYRaYrmaIJMopxvZDq3hqW2BJRMtTlfQA2VvLgxFF60SjSEcmy Jgt7M+xRZUpWwqDUKjZabiwisHgGtiFX3lQk+O7loK91iYj3/pO5zGIdJISndGx3X9HC zlaA== X-Gm-Message-State: AOJu0YzJ6khf7cqym3Jeyk4PxdEnYyT9+PT2RpAgKVhq+plSQii/Ob0t RlVXvg04ILryVmOgoztJYv/3eBmLcrSv7Ug00ec= X-Google-Smtp-Source: AGHT+IFdZI3GE6KqN7Moq0Mhq42Orq46VZx4L5iYKMDggAU7ZMfsW2vFfStXZ1ZWKWgwfGZTzI7uig== X-Received: by 2002:a05:600c:25a:b0:3fe:4341:a5aa with SMTP id 26-20020a05600c025a00b003fe4341a5aamr235068wmj.8.1695317846023; Thu, 21 Sep 2023 10:37:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/30] target/arm: Update user-mode ID reg mask values Date: Thu, 21 Sep 2023 18:36:58 +0100 Message-Id: <20230921173720.3250581-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318149163100005 Content-Type: text/plain; charset="utf-8" For user-only mode we reveal a subset of the AArch64 ID registers to the guest, to emulate the kernel's trap-and-emulate-ID-regs handling. Update the feature bit masks to match upstream kernel commit a48fa7efaf1161c1c. None of these features are yet implemented by QEMU, so this doesn't yet have a behavioural change, but implementation of FEAT_MOPS and FEAT_HBC is imminent. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 11 ++++++++++- tests/tcg/aarch64/sysregs.c | 4 ++-- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3b22596eabf..594985d7c8c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8621,11 +8621,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) R_ID_AA64ZFR0_F64MM_MASK }, { .name =3D "ID_AA64SMFR0_EL1", .exported_bits =3D R_ID_AA64SMFR0_F32F32_MASK | + R_ID_AA64SMFR0_BI32I32_MASK | R_ID_AA64SMFR0_B16F32_MASK | R_ID_AA64SMFR0_F16F32_MASK | R_ID_AA64SMFR0_I8I32_MASK | + R_ID_AA64SMFR0_F16F16_MASK | + R_ID_AA64SMFR0_B16B16_MASK | + R_ID_AA64SMFR0_I16I32_MASK | R_ID_AA64SMFR0_F64F64_MASK | R_ID_AA64SMFR0_I16I64_MASK | + R_ID_AA64SMFR0_SMEVER_MASK | R_ID_AA64SMFR0_FA64_MASK }, { .name =3D "ID_AA64MMFR0_EL1", .exported_bits =3D R_ID_AA64MMFR0_ECV_MASK, @@ -8676,7 +8681,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .exported_bits =3D R_ID_AA64ISAR2_WFXT_MASK | R_ID_AA64ISAR2_RPRES_MASK | R_ID_AA64ISAR2_GPA3_MASK | - R_ID_AA64ISAR2_APA3_MASK }, + R_ID_AA64ISAR2_APA3_MASK | + R_ID_AA64ISAR2_MOPS_MASK | + R_ID_AA64ISAR2_BC_MASK | + R_ID_AA64ISAR2_RPRFM_MASK | + R_ID_AA64ISAR2_CSSC_MASK }, { .name =3D "ID_AA64ISAR*_EL1_RESERVED", .is_glob =3D true }, }; diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c index d8eb06abcf2..f7a055f1d5f 100644 --- a/tests/tcg/aarch64/sysregs.c +++ b/tests/tcg/aarch64/sysregs.c @@ -126,7 +126,7 @@ int main(void) */ get_cpu_reg_check_mask(id_aa64isar0_el1, _m(f0ff,ffff,f0ff,fff0)); get_cpu_reg_check_mask(id_aa64isar1_el1, _m(00ff,f0ff,ffff,ffff)); - get_cpu_reg_check_mask(SYS_ID_AA64ISAR2_EL1, _m(0000,0000,0000,ffff)); + get_cpu_reg_check_mask(SYS_ID_AA64ISAR2_EL1, _m(00ff,0000,00ff,ffff)); /* TGran4 & TGran64 as pegged to -1 */ get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(f000,0000,ff00,0000)); get_cpu_reg_check_mask(id_aa64mmfr1_el1, _m(0000,f000,0000,0000)); @@ -138,7 +138,7 @@ int main(void) get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006)); get_cpu_reg_check_zero(id_aa64dfr1_el1); get_cpu_reg_check_mask(SYS_ID_AA64ZFR0_EL1, _m(0ff0,ff0f,00ff,00ff)); - get_cpu_reg_check_mask(SYS_ID_AA64SMFR0_EL1, _m(80f1,00fd,0000,0000)); + get_cpu_reg_check_mask(SYS_ID_AA64SMFR0_EL1, _m(8ff1,fcff,0000,0000)); =20 get_cpu_reg_check_zero(id_aa64afr0_el1); get_cpu_reg_check_zero(id_aa64afr1_el1); --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695317913; cv=none; d=zohomail.com; s=zohoarc; b=mr/qcroQxvshQmsh3iHgTVvgWDVmx0E6ce0e90VVVMkwBGYALqF3aIoH7tUMoSBo3Uk1I3gtf6keHeyseTO7rkuo5SWvG7LuoFTg7np8OiqDmonhi2wIG/+4RdtqfFq/mXUcGG1tdMhxWUk2PsDn2LCQJYXEJqlW4ue4a2ajM5M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695317913; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=t2XxQEkbUIbrufa38MGz1qprxVFgYcv2dQMKgqOxxd8=; b=lH1NsXAMf/Lkg6qk1Pdu96yY158flJwCmlorGsd+plSdkBUB74fZmZeJLyHL6pT8ITDTWNA6i/dgVzshqgXrEzHXqU3VA0ZDynjKJyw7a802HmbIGQF5sdWpxxBp714qxQd9nngwZnfMtUQ3kN9VockzHks99GxgvJo4/CsiPiw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695317913325929.5969715078799; Thu, 21 Sep 2023 10:38:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNcL-00020w-Ds; Thu, 21 Sep 2023 13:37:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNcI-000205-5A for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:30 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcF-0007fE-VC for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:29 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-40537481094so7505225e9.0 for ; Thu, 21 Sep 2023 10:37:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317846; x=1695922646; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=t2XxQEkbUIbrufa38MGz1qprxVFgYcv2dQMKgqOxxd8=; b=z7E41OWO3CF+jBtukMu7ad00n6h6TgT4Ii/b2e8SEUSxjx0yavmrU/t1JkKR0+voMr bKfmH1k7qxn2jafQo2d01z9EzCfYgw7LJyLpjpcENyQj8OnCc7ViyrAYNVa0ncaCUmor voCDQIbHDkNPOdIpXNjAcP2UiH3RFneFXpNt0sMJ5MnmKuUSonWydplKqispUPfw5nVh BNBjis1FCAlaOGmMDg1fYN6k6aGFvWqy/M234KkXDo7ME9I7cQ4/IhuKDYD1t2p44Zxr qSzSKF85FF5OK95qVI2OYryU6pnLUylTuvxg+NtQbCE3EJS6OwEK+hnPQ3sCtye5QNPr P+Eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317846; x=1695922646; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t2XxQEkbUIbrufa38MGz1qprxVFgYcv2dQMKgqOxxd8=; b=xEoLC5gzlPwq/HhuuBeBkDPKNPk52kxVeD1ulnywG/UD2paEZyyYX5diap0HYaIr5i jnSlwywAB1VbFh4meWpS+J4LxwT7uZJEIccIUMd+NI+crOHUDyLLPriTBIU7nXiCAeBH vsih/0GNh1rgmvmE7WkZ8x0KUu6YIEQX2v+qgDaNy1CCBox/McVKl75NQl6/MHrc7Tjd ptQ18SAuy8x4FhMei8riQxni4XNVPXRmtZ7O8q2idF9YijA580TwdNk+c6J8uQr+7oLO 4DISDji4fR/gu64rtFBHabKnOdahBn0avtv4XY/WpLFp4LvxPS7nkrikWN+D/qt2tSOv n0Iw== X-Gm-Message-State: AOJu0YwBNZoXwj+YuZ/ea+kGUriq893kwNbcefN9sI7Wz0cBHqQq/wD4 GMT4bwgv22H4vISRp7D37G1MX3T2bQbSu7oOYlw= X-Google-Smtp-Source: AGHT+IFtAoMkTZdXBMPrY64CfepFNE4+9L+WsH00vQus69402khkhFsNJzqq4uPdnQFFdVCYz8aSIA== X-Received: by 2002:a05:600c:3c93:b0:405:3455:d603 with SMTP id bg19-20020a05600c3c9300b004053455d603mr2217264wmb.17.1695317846503; Thu, 21 Sep 2023 10:37:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/30] target/arm: Implement FEAT_HBC Date: Thu, 21 Sep 2023 18:36:59 +0100 Message-Id: <20230921173720.3250581-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695317913737100001 FEAT_HBC (Hinted conditional branches) provides a new instruction BC.cond, which behaves exactly like the existing B.cond except that it provides a hint to the branch predictor about the likely behaviour of the branch. Since QEMU does not implement branch prediction, we can treat this identically to B.cond. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 5 +++++ target/arm/tcg/a64.decode | 3 ++- linux-user/elfload.c | 1 + target/arm/tcg/cpu64.c | 4 ++++ target/arm/tcg/translate-a64.c | 4 ++++ 6 files changed, 17 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 3df936fc356..1fb6a2e8c3e 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -42,6 +42,7 @@ the following architecture extensions: - FEAT_FlagM2 (Enhancements to flag manipulation instructions) - FEAT_GTG (Guest translation granule size) - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state) +- FEAT_HBC (Hinted conditional branches) - FEAT_HCX (Support for the HCRX_EL2 register) - FEAT_HPDS (Hierarchical permission disables) - FEAT_HPDS2 (Translation table page-based hardware attributes) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7ba2402f727..bc7a69a8753 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4088,6 +4088,11 @@ static inline bool isar_feature_aa64_i8mm(const ARMI= SARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) !=3D 0; } =20 +static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) !=3D 0; +} + static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) { return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >=3D 1; diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index ef64a3f9cba..71113173020 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -126,7 +126,8 @@ CBZ sf:1 011010 nz:1 ................... rt= :5 &cbz imm=3D%imm19 =20 TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=3D%imm14= bitpos=3D%imm31_19 =20 -B_cond 0101010 0 ................... 0 cond:4 imm=3D%imm19 +# B.cond and BC.cond +B_cond 0101010 0 ................... c:1 cond:4 imm=3D%imm19 =20 BR 1101011 0000 11111 000000 rn:5 00000 &r BLR 1101011 0001 11111 000000 rn:5 00000 &r diff --git a/linux-user/elfload.c b/linux-user/elfload.c index bbb4f08109c..203a2b790d5 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -815,6 +815,7 @@ uint32_t get_elf_hwcap2(void) GET_FEATURE_ID(aa64_sme_f64f64, ARM_HWCAP2_A64_SME_F64F64); GET_FEATURE_ID(aa64_sme_i16i64, ARM_HWCAP2_A64_SME_I16I64); GET_FEATURE_ID(aa64_sme_fa64, ARM_HWCAP2_A64_SME_FA64); + GET_FEATURE_ID(aa64_hbc, ARM_HWCAP2_A64_HBC); =20 return hwcaps; } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 7264ab5ead1..57abaea00cd 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1027,6 +1027,10 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ cpu->isar.id_aa64isar1 =3D t; =20 + t =3D cpu->isar.id_aa64isar2; + t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ + cpu->isar.id_aa64isar2 =3D t; + t =3D cpu->isar.id_aa64pfr0; t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1b6fbb61e2b..1dd86edae13 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1453,6 +1453,10 @@ static bool trans_TBZ(DisasContext *s, arg_tbz *a) =20 static bool trans_B_cond(DisasContext *s, arg_B_cond *a) { + /* BC.cond is only present with FEAT_HBC */ + if (a->c && !dc_isar_feature(aa64_hbc, s)) { + return false; + } reset_btype(s); if (a->cond < 0x0e) { /* genuinely conditional branches */ --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695318102; cv=none; d=zohomail.com; s=zohoarc; b=nsGhRl/ZEJD9iFPbCX6H6N7qztsYgQo/+0pi6uK5FYidMqCBbBhUguNglKfpQ6HzsmyK4EOVd7AAWMuAktbRk4yYNrmpqcyaXttPf3JXN4VUVVfWUq81sK08mmlCOQEeXwnqUGxSiESvju0fbGX45zCOCiR7kEpGeh5EPjTb57o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695318102; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bwOul3+f13BVG4rdOd+Q2KpVCyeubelgJwfI2HbCULQ=; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317847; x=1695922647; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bwOul3+f13BVG4rdOd+Q2KpVCyeubelgJwfI2HbCULQ=; b=wxlVe8+hv0iSVqNO9LS53eBXjKLG8xFPOzQiPa+C+J+Vt/5xHWTzVokOblRTuRkgiW pekyFDIgi8YvPoFrEC9wfLtAWveFxaumFSyJCetcuUElLT/7brg1fRaoj22xMd5QSkbx XAogY5dOJen3AZCMLCYkw1WOwvHAdh3L87rEpWyD2hBHo0z/Ta3y469MFLu9ukaubl0f tCoIP2ha8oBJtKDwv0zVQrYRvSeIHkl3LKknjfhXTxj22XPIn6NRMgg7RG7pnZkke76a 0E3U75qRnQzctaeQrMPe/8fa1ji40Ma1qsmAaSTFZNZMF3gFZmReidJdc+LV4hZZdHuk j4BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317847; x=1695922647; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bwOul3+f13BVG4rdOd+Q2KpVCyeubelgJwfI2HbCULQ=; b=VfGj9Zn/QJOaTAAeVWrNDWYKlIov6xMqtgTRRpJMo9cQkOa53XG9JEQPPyhsC9itri iibUkPuOHwdavuaqP5KKrEcf4lrbB9pXElvFiVdKDVStFnFnCfKh/fjO37k6HJlrE9dc VJGMr1jQgJgXWk4YHiEWyq7kSEg2UOVriZh1R2q7CVNF3zS13RbpI85jifymX1n56nkS nQf2aI0VW9p99XeOkY8kIBrp4NBcHfGfoYcTpj9Y9ZSx+OkAaxDKI9GI8wbDN4hPfn1s r5ndnii5avyLyNwiisRk+MRXAoZchcyxb87kIi0A2K8B4CTqS8BlZP9mMTr2g9tAunu/ WVsA== X-Gm-Message-State: AOJu0YyfyGqLXBf4bfXabiz3h5ixQAc9gV8AUnHt+LiU+JNwX3WGbc9J 4JNk93WkKMDckpVE1nPiuKZ16/mzwYih0H6JlWg= X-Google-Smtp-Source: AGHT+IEL+vU/YWSmmctjFRpGnS2mqPzNGK8+ZpwTN2cyNKpq6R5hRSNTtjDSDskY3u6T1jSqo1urUA== X-Received: by 2002:a7b:cb86:0:b0:402:f07c:4b48 with SMTP id m6-20020a7bcb86000000b00402f07c4b48mr5164727wmi.28.1695317846996; Thu, 21 Sep 2023 10:37:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/30] target/arm: Remove unused allocation_tag_mem() argument Date: Thu, 21 Sep 2023 18:37:00 +0100 Message-Id: <20230921173720.3250581-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318103037100001 The allocation_tag_mem() function takes an argument tag_size, but it never uses it. Remove the argument. In mte_probe_int() in particular this also lets us delete the code computing the value we were passing in. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/tcg/mte_helper.c | 42 +++++++++++++------------------------ 1 file changed, 14 insertions(+), 28 deletions(-) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index b23d11563ab..e2494f73cf3 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -57,7 +57,6 @@ static int choose_nonexcluded_tag(int tag, int offset, ui= nt16_t exclude) * @ptr_access: the access to use for the virtual address * @ptr_size: the number of bytes in the normal memory access * @tag_access: the access to use for the tag memory - * @tag_size: the number of bytes in the tag memory access * @ra: the return address for exception handling * * Our tag memory is formatted as a sequence of little-endian nibbles. @@ -69,15 +68,12 @@ static int choose_nonexcluded_tag(int tag, int offset, = uint16_t exclude) * a pointer to the corresponding tag byte. Exit with exception if the * virtual address is not accessible for @ptr_access. * - * The @ptr_size and @tag_size values may not have an obvious relation - * due to the alignment of @ptr, and the number of tag checks required. - * * If there is no tag storage corresponding to @ptr, return NULL. */ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, uint64_t ptr, MMUAccessType ptr_access, int ptr_size, MMUAccessType tag_access, - int tag_size, uintptr_t ra) + uintptr_t ra) { #ifdef CONFIG_USER_ONLY uint64_t clean_ptr =3D useronly_clean_ptr(ptr); @@ -275,7 +271,7 @@ uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, ui= nt64_t xt) =20 /* Trap if accessing an invalid page. */ mem =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, 1, - MMU_DATA_LOAD, 1, GETPC()); + MMU_DATA_LOAD, GETPC()); =20 /* Load if page supports tags. */ if (mem) { @@ -329,7 +325,7 @@ static inline void do_stg(CPUARMState *env, uint64_t pt= r, uint64_t xt, =20 /* Trap if accessing an invalid page. */ mem =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, TAG_GRAN= ULE, - MMU_DATA_STORE, 1, ra); + MMU_DATA_STORE, ra); =20 /* Store if page supports tags. */ if (mem) { @@ -372,10 +368,10 @@ static inline void do_st2g(CPUARMState *env, uint64_t= ptr, uint64_t xt, if (ptr & TAG_GRANULE) { /* Two stores unaligned mod TAG_GRANULE*2 -- modify two bytes. */ mem1 =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, - TAG_GRANULE, MMU_DATA_STORE, 1, ra); + TAG_GRANULE, MMU_DATA_STORE, ra); mem2 =3D allocation_tag_mem(env, mmu_idx, ptr + TAG_GRANULE, MMU_DATA_STORE, TAG_GRANULE, - MMU_DATA_STORE, 1, ra); + MMU_DATA_STORE, ra); =20 /* Store if page(s) support tags. */ if (mem1) { @@ -387,7 +383,7 @@ static inline void do_st2g(CPUARMState *env, uint64_t p= tr, uint64_t xt, } else { /* Two stores aligned mod TAG_GRANULE*2 -- modify one byte. */ mem1 =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, - 2 * TAG_GRANULE, MMU_DATA_STORE, 1, ra); + 2 * TAG_GRANULE, MMU_DATA_STORE, ra); if (mem1) { tag |=3D tag << 4; qatomic_set(mem1, tag); @@ -435,8 +431,7 @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) =20 /* Trap if accessing an invalid page. */ tag_mem =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, - gm_bs_bytes, MMU_DATA_LOAD, - gm_bs_bytes / (2 * TAG_GRANULE), ra); + gm_bs_bytes, MMU_DATA_LOAD, ra); =20 /* The tag is squashed to zero if the page does not support tags. */ if (!tag_mem) { @@ -495,8 +490,7 @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint6= 4_t val) =20 /* Trap if accessing an invalid page. */ tag_mem =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, - gm_bs_bytes, MMU_DATA_LOAD, - gm_bs_bytes / (2 * TAG_GRANULE), ra); + gm_bs_bytes, MMU_DATA_LOAD, ra); =20 /* * Tag store only happens if the page support tags, @@ -552,7 +546,7 @@ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr,= uint64_t val) ptr &=3D -dcz_bytes; =20 mem =3D allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, dcz_byte= s, - MMU_DATA_STORE, tag_bytes, ra); + MMU_DATA_STORE, ra); if (mem) { int tag_pair =3D (val & 0xf) * 0x11; memset(mem, tag_pair, tag_bytes); @@ -732,8 +726,7 @@ static int mte_probe_int(CPUARMState *env, uint32_t des= c, uint64_t ptr, int mmu_idx, ptr_tag, bit55; uint64_t ptr_last, prev_page, next_page; uint64_t tag_first, tag_last; - uint64_t tag_byte_first, tag_byte_last; - uint32_t sizem1, tag_count, tag_size, n, c; + uint32_t sizem1, tag_count, n, c; uint8_t *mem1, *mem2; MMUAccessType type; =20 @@ -763,19 +756,14 @@ static int mte_probe_int(CPUARMState *env, uint32_t d= esc, uint64_t ptr, tag_last =3D QEMU_ALIGN_DOWN(ptr_last, TAG_GRANULE); tag_count =3D ((tag_last - tag_first) / TAG_GRANULE) + 1; =20 - /* Round the bounds to twice the tag granule, and compute the bytes. */ - tag_byte_first =3D QEMU_ALIGN_DOWN(ptr, 2 * TAG_GRANULE); - tag_byte_last =3D QEMU_ALIGN_DOWN(ptr_last, 2 * TAG_GRANULE); - /* Locate the page boundaries. */ prev_page =3D ptr & TARGET_PAGE_MASK; next_page =3D prev_page + TARGET_PAGE_SIZE; =20 if (likely(tag_last - prev_page < TARGET_PAGE_SIZE)) { /* Memory access stays on one page. */ - tag_size =3D ((tag_byte_last - tag_byte_first) / (2 * TAG_GRANULE)= ) + 1; mem1 =3D allocation_tag_mem(env, mmu_idx, ptr, type, sizem1 + 1, - MMU_DATA_LOAD, tag_size, ra); + MMU_DATA_LOAD, ra); if (!mem1) { return 1; } @@ -783,14 +771,12 @@ static int mte_probe_int(CPUARMState *env, uint32_t d= esc, uint64_t ptr, n =3D checkN(mem1, ptr & TAG_GRANULE, ptr_tag, tag_count); } else { /* Memory access crosses to next page. */ - tag_size =3D (next_page - tag_byte_first) / (2 * TAG_GRANULE); mem1 =3D allocation_tag_mem(env, mmu_idx, ptr, type, next_page - p= tr, - MMU_DATA_LOAD, tag_size, ra); + MMU_DATA_LOAD, ra); =20 - tag_size =3D ((tag_byte_last - next_page) / (2 * TAG_GRANULE)) + 1; mem2 =3D allocation_tag_mem(env, mmu_idx, next_page, type, ptr_last - next_page + 1, - MMU_DATA_LOAD, tag_size, ra); + MMU_DATA_LOAD, ra); =20 /* * Perform all of the comparisons. @@ -918,7 +904,7 @@ uint64_t HELPER(mte_check_zva)(CPUARMState *env, uint32= _t desc, uint64_t ptr) mmu_idx =3D FIELD_EX32(desc, MTEDESC, MIDX); (void) probe_write(env, ptr, 1, mmu_idx, ra); mem =3D allocation_tag_mem(env, mmu_idx, align_ptr, MMU_DATA_STORE, - dcz_bytes, MMU_DATA_LOAD, tag_bytes, ra); + dcz_bytes, MMU_DATA_LOAD, ra); if (!mem) { goto done; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317847; x=1695922647; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=xqicFx4SLmYdVA1B6BSjmTvNZt1hFvhyCtMsK7qBhx4=; b=f84o5UM0KDIGekTb8zd0rZbbXkmjKDbfOmXY418EdLidBqvt+pB3foiV8H3OkDg3mr Pl/VCIVMAGGhE1CKh9xXOTUaGaItLj9gcnBaIl4Gm1Xcm3EXXp9ftPXWAO2rqfRw7pbh ofwgeSnyC+k0VatK07X9UIwdyB+1DyDh6oQzQSdE6JtnAUsevsqEQopHfZsGRxTY3/SI 6DuSe67A0RLyYC05lYCHeLZqXuSGq/FqVt8QfsAmODHMWBBvXqM9vsMjDrs9KCOA0j7P Tt0KtRowUgT63fsMkOGPoqdOePFtdhc3qe1YjnNb0RFJd/o0hehr7A1rjd4dyaGDlQBa tv8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317847; x=1695922647; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xqicFx4SLmYdVA1B6BSjmTvNZt1hFvhyCtMsK7qBhx4=; b=r/f/QC7ussEIg5bFcG3hnPG09hemXkjPzBLcrRZ54JLCTxmG2xWyYLA/+un2qaajeR htbLI1PplP+aWvopnMrxUP8r/lCswvQ8pQ/rwZrvK6+qX1poUypPHmn9OEev4fdRYeqb JBSag1AmkQ9DHgzGPh9JOQDg/h3mKGGsEuTbr1UgpgwuRCG4haiBmy5cxzYLQnlywKh2 BumsQANStywY/k7TYqiuFRVF1zedL0FhJZmiqKrSUhtxsCYr4dNwkprvVODAB3I7THrb LRhrdXLO9I+Bi/PKaMF69lSvzVVYh0kEZU/RtHjfdu/Dd8vVQGZGsHcK8VWgUuQu94Ro XyQg== X-Gm-Message-State: AOJu0YwDYbV3mTB5lUjps1at+z9E3dctYl+PByLY145pkT75F/a7sOTw oUkehUgXZI0HG8RdgCdXps7iwUiuUsZ7QtALb1E= X-Google-Smtp-Source: AGHT+IGyNOTYNGM5G07ub1jpnJ7ggRyr+xIhIfbk+eBr3ZIYnhfuWg07JOm+mmjHBhyl9I9jncZm0g== X-Received: by 2002:a5d:56c4:0:b0:31f:a277:4cde with SMTP id m4-20020a5d56c4000000b0031fa2774cdemr5786934wrw.43.1695317847365; Thu, 21 Sep 2023 10:37:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/30] target/arm: Don't skip MTE checks for LDRT/STRT at EL0 Date: Thu, 21 Sep 2023 18:37:01 +0100 Message-Id: <20230921173720.3250581-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318117328100011 Content-Type: text/plain; charset="utf-8" The LDRT/STRT "unprivileged load/store" instructions behave like normal ones if executed at EL0. We handle this correctly for the load/store semantics, but get the MTE checking wrong. We always look at s->mte_active[is_unpriv] to see whether we should be doing MTE checks, but in hflags.c when we set the TB flags that will be used to fill the mte_active[] array we only set the MTE0_ACTIVE bit if UNPRIV is true (i.e. we are not at EL0). This means that a LDRT at EL0 will see s->mte_active[1] as 0, and will not do MTE checks even when MTE is enabled. To avoid the translate-time code having to do an explicit check on s->unpriv to see if it is OK to index into the mte_active[] array, duplicate MTE_ACTIVE into MTE0_ACTIVE when UNPRIV is false. (This isn't a very serious bug because generally nobody executes LDRT/STRT at EL0, because they have no use there.) Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230912140434.1333369-2-peter.maydell@linaro.org --- target/arm/tcg/hflags.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 616c5fa7237..ea642384f5a 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -306,6 +306,15 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, && !(env->pstate & PSTATE_TCO) && (sctlr & (el =3D=3D 0 ? SCTLR_TCF0 : SCTLR_TCF))) { DP_TBFLAG_A64(flags, MTE_ACTIVE, 1); + if (!EX_TBFLAG_A64(flags, UNPRIV)) { + /* + * In non-unpriv contexts (eg EL0), unpriv load/stores + * act like normal ones; duplicate the MTE info to + * avoid translate-a64.c having to check UNPRIV to see + * whether it is OK to index into MTE_ACTIVE[]. + */ + DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); + } } } /* And again for unprivileged accesses, if required. */ --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695318130; cv=none; d=zohomail.com; s=zohoarc; b=c1YU2sKktwKWnZnqtctXYI1eklCXEyRfkRb+h9V+ddoR/V/JA7z9lb8l4PUKeEQOa7IdlbY8eZYqP1SMf+Eo59ehcK3eGNvligilfVen+rkvfgWXv51n0d4OGx5K1IkFZJivhkHIzIdvJdvFQLI5ldvikR4Q1RNaL2UI6h9omt0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695318130; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PPqQ/LS6jA6MW0fhtCDmF52VOMvdr3igAcdZ+no8ZbI=; b=luEoAm5Gma4nwT07GKB869Mu01F/GhheRdS0hk7LJNjhDtZ6rd7Y/hHHooZGbfmDNwTSiYJ5j3IemLuPIZMVBA/R55Ry2rZcupG/1kBGOhmbZoBc1yhi1jCERm5lSvWodFcN2nuyYval0g1gygiEw95ePiQvJtCrmdcpv3frURw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695318130514519.3816628781448; Thu, 21 Sep 2023 10:42:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNcO-00022J-HC; Thu, 21 Sep 2023 13:37:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNcM-00021Q-A5 for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:34 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcH-0007ff-AQ for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:34 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-4053c6f0d3dso533965e9.1 for ; Thu, 21 Sep 2023 10:37:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317848; x=1695922648; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=PPqQ/LS6jA6MW0fhtCDmF52VOMvdr3igAcdZ+no8ZbI=; b=jd3u5Kwz7Av/2VT8oZiEknYkaDfTdpenorIxJjmd/s/qiTHJpaJFxHQM2uiAd0wvIA z1n+Mr/UrwzGcmwOqaeodzdMDbEhuoFyMBVKJ3wvkdOScEpgZuUAyFRK3eFFaCfzosaz 3FX3L/z5uMbCHD/9Eb0y5vs94Dp6jpbC9bJcIlxhOiDE7TGDDbevVZ5M09hjXXNqTwBD mYHlOU79sPHGfGx/2x1p57qJRlmlqW8ziCwdymGhkcCEYrhcthVRPsBp/3ym0ivWjavX 5hoP63BpO4oYcQ9GUxZyPLxIhYO7I6u/bl/0gtSrZIw7uF3CooI8j0Y+OhsIwLvb2hoE dfOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317848; x=1695922648; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PPqQ/LS6jA6MW0fhtCDmF52VOMvdr3igAcdZ+no8ZbI=; b=Q+V9nzMwjO5IFoG125QilAJG9jU0MzKHMto2O3rTIYxQQmf/IgBkwr0GSZoyr9fUqw /4UglpCOk91KDh5YdEJGg1VGAaB6AQe5sIJHIPIo7IU6lq5OXArgACWqQ02X8OU4+OkP JNCNLi7dRHWxc+i7k1PMTGwOcFrO2Q0JVtz/faemkW7V1f4JMkEiRtm6xq9b/ilEW8CF McJZhWXygRnKbCtMVZQ9W8teGzdVkOable8XPTLczPQLYNH3Me+bWiqWVGP2cCWu4xBM 6Mivds9GzUjjBR7xw1RfzFWztOK8cZO1hHNXNqjlptt04UBVMHSo5YsBXeDM8s/tpOwD uYWg== X-Gm-Message-State: AOJu0YzmE/X2dhtA3uFdH+dymxwhPwxDAt3WU43ZCTWCmxSbvvslaAiY aB81wz9r4+b9Wk4K8CAek1eW6iNJUsZxoY7R80U= X-Google-Smtp-Source: AGHT+IFR65nUWh8TfhSYJ5z56ifMDXY9DN/2csL4ExSg63DN/q0oJ/Va7bzqyTio31VfPx/iztNRHg== X-Received: by 2002:adf:de0c:0:b0:31a:d450:c513 with SMTP id b12-20020adfde0c000000b0031ad450c513mr5526316wrm.26.1695317847767; Thu, 21 Sep 2023 10:37:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/30] target/arm: Implement FEAT_MOPS enable bits Date: Thu, 21 Sep 2023 18:37:02 +0100 Message-Id: <20230921173720.3250581-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318132421100007 Content-Type: text/plain; charset="utf-8" FEAT_MOPS defines a handful of new enable bits: * HCRX_EL2.MSCEn, SCTLR_EL1.MSCEn, SCTLR_EL2.MSCen: define whether the new insns should UNDEF or not * HCRX_EL2.MCE2: defines whether memops exceptions from EL1 should be taken to EL1 or EL2 Since we don't sanitise what bits can be written for the SCTLR registers, we only need to handle the new bits in HCRX_EL2, and define SCTLR_MSCEN for the new SCTLR bit value. The precedence of "HCRX bits acts as 0 if SCR_EL3.HXEn is 0" versus "bit acts as 1 if EL2 disabled" is not clear from the register definition text, but it is clear in the CheckMOPSEnabled() pseudocode(), so we follow that. We'll have to check whether other bits we need to implement in future follow the same logic or not. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230912140434.1333369-3-peter.maydell@linaro.org --- target/arm/cpu.h | 6 ++++++ target/arm/helper.c | 28 +++++++++++++++++++++------- 2 files changed, 27 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bc7a69a8753..266c1a9ea1b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1315,6 +1315,7 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */ #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */ #define SCTLR_DSSBS_32 (1U << 31) /* v8.5, AArch32 only */ +#define SCTLR_MSCEN (1ULL << 33) /* FEAT_MOPS */ #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */ #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */ #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */ @@ -4281,6 +4282,11 @@ static inline bool isar_feature_aa64_doublelock(cons= t ARMISARegisters *id) return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >=3D 0; } =20 +static inline bool isar_feature_aa64_mops(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS); +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 594985d7c8c..83620787b45 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5980,7 +5980,10 @@ static void hcrx_write(CPUARMState *env, const ARMCP= RegInfo *ri, { uint64_t valid_mask =3D 0; =20 - /* No features adding bits to HCRX are implemented. */ + /* FEAT_MOPS adds MSCEn and MCE2 */ + if (cpu_isar_feature(aa64_mops, env_archcpu(env))) { + valid_mask |=3D HCRX_MSCEN | HCRX_MCE2; + } =20 /* Clear RES0 bits. */ env->cp15.hcrx_el2 =3D value & valid_mask; @@ -6009,13 +6012,24 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env) { /* * The bits in this register behave as 0 for all purposes other than - * direct reads of the register if: - * - EL2 is not enabled in the current security state, - * - SCR_EL3.HXEn is 0. + * direct reads of the register if SCR_EL3.HXEn is 0. + * If EL2 is not enabled in the current security state, then the + * bit may behave as if 0, or as if 1, depending on the bit. + * For the moment, we treat the EL2-disabled case as taking + * priority over the HXEn-disabled case. This is true for the only + * bit for a feature which we implement where the answer is different + * for the two cases (MSCEn for FEAT_MOPS). + * This may need to be revisited for future bits. */ - if (!arm_is_el2_enabled(env) - || (arm_feature(env, ARM_FEATURE_EL3) - && !(env->cp15.scr_el3 & SCR_HXEN))) { + if (!arm_is_el2_enabled(env)) { + uint64_t hcrx =3D 0; + if (cpu_isar_feature(aa64_mops, env_archcpu(env))) { + /* MSCEn behaves as 1 if EL2 is not enabled */ + hcrx |=3D HCRX_MSCEN; + } + return hcrx; + } + if (arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXE= N)) { return 0; } return env->cp15.hcrx_el2; --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695318131; cv=none; d=zohomail.com; s=zohoarc; b=Ca/GW9CG8a8OtPldwZ0egHGr4kt3aNT3srUj2FdlaCbxaovJ04NuzPk5QNSHyseYCXc/F5S6YvWEwRl5S3M1TcXbZNJ9x6kV5ZaBbg+60MThyK8JGsuquw9X7IsO7HyltT20M/qHxBn4jLFEWtiv5KnLqjcgIhf0WRB7JdS25CI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695318131; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=a5oDc+Yq+g+grY1ZGCS7U6eCrdf7ur5IfU4giqXKmlM=; b=HOx3B/CS1KWRyW6Gz/EW6dMGfhqpFy/PZO6uhMSksmIglYNcimC0B+ZVTB40FNbmpaYfOUpCV8ujvoa5hxcA5Qz6msXAFTZlmkkbhmzlvbGi7OlbTjtVAK1qXVjfKX4XFWfU4v8WODxEu01Db8sO2glQ2Y6AWVVfuUNdvZP/Z14= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695318131080682.139409195253; Thu, 21 Sep 2023 10:42:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNcW-00026c-Aw; Thu, 21 Sep 2023 13:37:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNcO-00022K-Kv for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:36 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcH-0007fo-Ln for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:34 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-404314388ceso13929315e9.2 for ; Thu, 21 Sep 2023 10:37:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317848; x=1695922648; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=a5oDc+Yq+g+grY1ZGCS7U6eCrdf7ur5IfU4giqXKmlM=; b=Yj7B0IBqU/fuDMrrItQnpSdDgfbjDAI9x0CH7wG0OF7/PdF5K2mmwcTFWnXj+7tJro +psMwSUsOqK4utOExVAmzpdxMGH0FqOG7Xv3+UpC+JaZwastTmP+o8gxFa83e7u2YW8D Dh4KOAI+ckP5DCU0RebXSutTQLax3IrHskhNvh+A5kTHPL3+vQSJXgv+bhMZ/P3fh/s4 VVm9pXmtR/Cg24piSwW2bT3uhJJPtUNHsiXkzT8qA69HqXJsYDQfmzhADU4bruT3xtwl JtyOkD9mK8h0hkCGmkEVzF+F8EWCzj598f0HT+FzMIS/pvPz50P23jv2VTZeZzCwGROM 3gsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317848; x=1695922648; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a5oDc+Yq+g+grY1ZGCS7U6eCrdf7ur5IfU4giqXKmlM=; b=G7fPpny1ss3LRs/JHKAHYENajRLFeE9TfKSBNhxMe55bQEUgdJTFX6Z38/rT72tjTU s/8rXV5BJKOi7iSPJpwO1kjgXx5m9FSdLKRqqsWWhFd5C/Hq+U0wafOQYpz6mCVtIvfa BVjzDkIDHMU/PtWVRRsrSV5ZgLhIjot07Del4AlUnqOkWSCGvXyhTVim9xBJKV3pOCcQ 6P4hkZWLpb+SUELF5rg1v5bDgcu8T/7/gEy18WABkvdEGcpjUz8kH7ErviLX1HS4bZrj lhCLpg4g6LRd1ydO2zAdwqtmVX5poo+OgQ+A0nzco+/nRNdRGj9qUCyE0MiuT5uPaKAh zdyQ== X-Gm-Message-State: AOJu0Yw1COrr7spnCAzeLuG1Me5653OcpPD3u7dlzg3Sv14ynw4Zz8up +g1DSIYf44TS9TWnfmtTLgv3OcWoBbeQ9Orchho= X-Google-Smtp-Source: AGHT+IEAvb4qQt8t4vYEl/kUpjbakwZp/JdIpYdmk3Ey4fti+HY9IW6QDBDs8X/ESHGbFjgyYi5ptg== X-Received: by 2002:a05:600c:21c2:b0:405:1ba9:e862 with SMTP id x2-20020a05600c21c200b004051ba9e862mr5734560wmj.10.1695317848178; Thu, 21 Sep 2023 10:37:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/30] target/arm: Pass unpriv bool to get_a64_user_mem_index() Date: Thu, 21 Sep 2023 18:37:03 +0100 Message-Id: <20230921173720.3250581-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318132350100002 Content-Type: text/plain; charset="utf-8" In every place that we call the get_a64_user_mem_index() function we do it like this: memidx =3D a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); Refactor so the caller passes in the bool that says whether they want the 'unpriv' or 'normal' mem_index rather than having to do the ?: themselves. Signed-off-by: Peter Maydell Message-id: 20230912140434.1333369-4-peter.maydell@linaro.org --- target/arm/tcg/translate-a64.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1dd86edae13..24afd929144 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -105,9 +105,17 @@ void a64_translate_init(void) } =20 /* - * Return the core mmu_idx to use for A64 "unprivileged load/store" insns + * Return the core mmu_idx to use for A64 load/store insns which + * have a "unprivileged load/store" variant. Those insns access + * EL0 if executed from an EL which has control over EL0 (usually + * EL1) but behave like normal loads and stores if executed from + * elsewhere (eg EL3). + * + * @unpriv : true for the unprivileged encoding; false for the + * normal encoding (in which case we will return the same + * thing as get_mem_index(). */ -static int get_a64_user_mem_index(DisasContext *s) +static int get_a64_user_mem_index(DisasContext *s, bool unpriv) { /* * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL, @@ -115,7 +123,7 @@ static int get_a64_user_mem_index(DisasContext *s) */ ARMMMUIdx useridx =3D s->mmu_idx; =20 - if (s->unpriv) { + if (unpriv && s->unpriv) { /* * We have pre-computed the condition for AccType_UNPRIV. * Therefore we should never get here with a mmu_idx for @@ -3088,7 +3096,7 @@ static void op_addr_ldst_imm_pre(DisasContext *s, arg= _ldst_imm *a, if (!a->p) { tcg_gen_addi_i64(*dirty_addr, *dirty_addr, offset); } - memidx =3D a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); + memidx =3D get_a64_user_mem_index(s, a->unpriv); *clean_addr =3D gen_mte_check1_mmuidx(s, *dirty_addr, is_store, a->w || a->rn !=3D 31, mop, a->unpriv, memidx); @@ -3109,7 +3117,7 @@ static bool trans_STR_i(DisasContext *s, arg_ldst_imm= *a) { bool iss_sf, iss_valid =3D !a->w; TCGv_i64 clean_addr, dirty_addr, tcg_rt; - int memidx =3D a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s= ); + int memidx =3D get_a64_user_mem_index(s, a->unpriv); MemOp mop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); =20 op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true, mop= ); @@ -3127,7 +3135,7 @@ static bool trans_LDR_i(DisasContext *s, arg_ldst_imm= *a) { bool iss_sf, iss_valid =3D !a->w; TCGv_i64 clean_addr, dirty_addr, tcg_rt; - int memidx =3D a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s= ); + int memidx =3D get_a64_user_mem_index(s, a->unpriv); MemOp mop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); =20 op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false, mo= p); --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695317908; cv=none; d=zohomail.com; s=zohoarc; b=isaAKS/81h7kwUqyRGc7sX/8SmdgO5jHVGHXO/UUq/7kNRblmMJ0jPdCx/qrfvBGC+WEDSt4s8o3OefoN30Jri7W31x/KBlARPcbSKKWFZzkdq9/bzCj1cZ7ILvyz38mbDWqWWH+PqAsShQIfeQYi2zl1v4GEmTz/mErm99GfWE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695317908; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qQViptMVSdrRp9VfBJYI4Acm+qff4tHoiCsPi2XOdW4=; b=F/5iSf1PCYAPUsdzJQU6Uy6GCnqFv+KM9XKwoXUa92NqgsRCSmEbOVPakggx1kH66U0ZZKWVDiCts/VUJeAa5lik2rFJYOQYQqTLEalXHON7LuStVeRLIXS2wunTwu5l6jZN10XG7NPv5bDJ99LKUE3NHMOyAyB82EiK8f3uCgg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695317908788631.9780213772649; Thu, 21 Sep 2023 10:38:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNcP-00022q-Nb; Thu, 21 Sep 2023 13:37:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNcO-00021h-L1 for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:36 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcI-0007fw-Es for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:34 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-40528376459so12853815e9.3 for ; Thu, 21 Sep 2023 10:37:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317849; x=1695922649; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=qQViptMVSdrRp9VfBJYI4Acm+qff4tHoiCsPi2XOdW4=; b=sOtS7RUwDcekYN4b2FEkx7Hyj0TbMkHcFTWhNAL0K1KUXiTNVBEBLAZZSWASajiMPj 0DqP+PdhsLdEiaeTqke/OElkln3DgEMXLMDFY/j2mcw4JiqKc0fvXqmdtp4D0k5KH4yC RkafU5r17D1ktwVhrMQ7SIA6FqKsyWhL0SdqeQvkR65tq1p4i2K6moXttcFbeS5dLIoJ y+ur2HcEPkeT2wmuzWhz9I2TRZPi0j2SJObRBFkQAE46fd19L309LICO1CjiKNFSyQyH jQB9JBcQqrXOtMMOJw+eOcmNW9wF7KeiSkl9HzMmmKpomwItwJMWxKrAhP9EtQq43crk t7UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317849; x=1695922649; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qQViptMVSdrRp9VfBJYI4Acm+qff4tHoiCsPi2XOdW4=; b=RDXykLfgiwmDC6qFWvYpqO7zEcIKzMdqK2nWX9vO+psFnxUMXvWw98R30+nYSXe4D4 oaur64xIcGiWhDpzNVfs0whRLA4dGeTBH3+mdhEVlQE7mrCrnxITbYnkBB2MQ5NZusFk 06mMGZtySUypdlc2ThrGBOVU8HU9y1w+zPio09cIatcj2So8bcR2Tb7NOF7wUJs0RUFa KQU0kc8ea9AETFB9QLvLZE1gCWUyroNjftmJvshFZnB3brKGlW4YDNwyrMLmxoheJUa8 hgZZnRRBxtIAJAmPVMUL5nyyG/UwpQ2fnH8qZ99KQTMqfcKLiCGMK3unMvdkr0lSY7yl 89Cg== X-Gm-Message-State: AOJu0YwD4xzXDqlczLk1z7UFe7k/dyq7Uxbqy+eBp7sP2r3cRAGOhZjh N0m80dARHvgwjxmfsjAu75LNPTlsWm/y2moc48Y= X-Google-Smtp-Source: AGHT+IEfd5bttzi0oyS3PZSghi65H8s3hH+Vpli+ry8RYk8WrnYd3zXif+BVVBlm0Pn6nBlqbnsS2A== X-Received: by 2002:a05:600c:3b1d:b0:405:36d7:4581 with SMTP id m29-20020a05600c3b1d00b0040536d74581mr1738731wms.9.1695317849141; Thu, 21 Sep 2023 10:37:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/30] target/arm: Define syndrome function for MOPS exceptions Date: Thu, 21 Sep 2023 18:37:04 +0100 Message-Id: <20230921173720.3250581-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695317909364100001 Content-Type: text/plain; charset="utf-8" The FEAT_MOPS memory operations can raise a Memory Copy or Memory Set exception if a copy or set instruction is executed when the CPU register state is not correct for that instruction. Define the usual syn_* function that constructs the syndrome register value for these exceptions. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230912140434.1333369-5-peter.maydell@linaro.org --- target/arm/syndrome.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 8a6b8f8162a..5d34755508d 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -58,6 +58,7 @@ enum arm_exception_class { EC_DATAABORT =3D 0x24, EC_DATAABORT_SAME_EL =3D 0x25, EC_SPALIGNMENT =3D 0x26, + EC_MOP =3D 0x27, EC_AA32_FPTRAP =3D 0x28, EC_AA64_FPTRAP =3D 0x2c, EC_SERROR =3D 0x2f, @@ -334,4 +335,15 @@ static inline uint32_t syn_serror(uint32_t extra) return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; } =20 +static inline uint32_t syn_mop(bool is_set, bool is_setg, int options, + bool epilogue, bool wrong_option, bool opti= on_a, + int destreg, int srcreg, int sizereg) +{ + return (EC_MOP << ARM_EL_EC_SHIFT) | ARM_EL_IL | + (is_set << 24) | (is_setg << 23) | (options << 19) | + (epilogue << 18) | (wrong_option << 17) | (option_a << 16) | + (destreg << 10) | (srcreg << 5) | sizereg; +} + + #endif /* TARGET_ARM_SYNDROME_H */ --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695318096; cv=none; d=zohomail.com; s=zohoarc; b=W2hCouR9Ge1QNWCkjpWDZixRKqDRhcDnFzNzT6FzpemLFGzW2h8jqPQPDaERHe24XdZpol7v8Wh6IcZfn9R042kUHLdVVfV2MjGWzcH/8ryErbOrif7fE7YhACXLjucEJ1j70ch8cK/quPZaoBVLz3Km5hbwIJLb4a/e8dK6Ud4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695318096; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cApx3eQTNx/NXklzfkHdVWI6Q+C1GtZo1CUTP5Shfvo=; b=hU8g8ATewg04gHqA4nAZ5ruUrMQIEVhVP+TQcTCSAjVsSZXGJ8dD+geMBjTkyn9h4Emr8PMcaD3yT4CpS+bpyrg4EJYxHYU1Cdvl9skPibX2ZtCDjmGFHu22vQuRcIC9ZR81NRGYJWFDYXiRGPOMtqKobFXFXxcjK2MK+dsXUZs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695318096867530.4810691967482; Thu, 21 Sep 2023 10:41:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNcb-0002AX-Qq; Thu, 21 Sep 2023 13:37:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNcZ-00028x-KI for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:47 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcJ-0007g0-AN for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:47 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-4018af103bcso8330315e9.1 for ; Thu, 21 Sep 2023 10:37:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317849; x=1695922649; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=cApx3eQTNx/NXklzfkHdVWI6Q+C1GtZo1CUTP5Shfvo=; b=rxApj94iMdkHB6PKMl/G1hTUcbFMTUvmIz4yxeKnqtEGln5rml/gQNBfOIRlsORsny 2ngXLr+QrN+tSJNPUnXiwQbGvNlHRoKZIQHtJZEr1PlgXE1TdoCcBp3z0Cyh1xaFYR5v hk9c8Ks+VY3+qTwx/+4tNVFyhSbwGHK5JC/G4aRwl1N0I29aTruhEROe3dACCcTJaQUN aV25lbr/thi+XIniLUbtrReGbrLli2BMo5X8r5OtkIPalnHzjpGiRSEeWUYAP1ZyUKFJ wWfYVSDMvinIB3KFnEjIti/nfYakpXNUo3H/BONucmvtAh4sga+3vNTQr+JaEO+N4Znd /Zzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317849; x=1695922649; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cApx3eQTNx/NXklzfkHdVWI6Q+C1GtZo1CUTP5Shfvo=; b=ifoWW85i278vh0C78WHWxzmG9B4+v7Z5tE+a1w2PUbr00q954J6OieUy1Yw+7q2zei Fz7q3fPJ/tsZxXDE+FlV788EQOd2Q/11X9Ig36ZgSGcLDS6Ja4kRMIpbwP4GybMnDs4c /W+LUu1VlEiLOgs393Q2VsoDA1chjdNNdrgFl2hrtQ6qWXwzVZ8Om7qJDNx7/doxY0+U CK/mazunZExLxmLxIQm9WBECOdPAX7s5xBJ8XPDGSHYSGkSvhxr6Bd+yZfk1DkttXPd+ t6uZMTRC5Y7NU6RXT7DJWa7uHpMaEXxv6TomP+BBc4737Qj0BPQwv5J1ADlC2QfTC8pS CPtQ== X-Gm-Message-State: AOJu0Yzlz7st9IBZdubkKRvBFC2tTC7Czu4nTRhdZyGtNJvzDqf1Lq0y EWJz4P/JRAwG9bAnnVSPJAxiMiV4uAS1OCJpdS4= X-Google-Smtp-Source: AGHT+IFdqhtSZeOcyl0FLK9q9S1BtNrP3IsPLKbH7+CANgs8C9N8BwjRCSexWhriyRYCN9haxSHQgw== X-Received: by 2002:a7b:c850:0:b0:402:ea8c:ea57 with SMTP id c16-20020a7bc850000000b00402ea8cea57mr249083wml.7.1695317849606; Thu, 21 Sep 2023 10:37:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/30] target/arm: New function allocation_tag_mem_probe() Date: Thu, 21 Sep 2023 18:37:05 +0100 Message-Id: <20230921173720.3250581-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318097310100001 Content-Type: text/plain; charset="utf-8" For the FEAT_MOPS operations, the existing allocation_tag_mem() function almost does what we want, but it will take a watchpoint exception even for an ra =3D=3D 0 probe request, and it requires that the caller guarantee that the memory is accessible. For FEAT_MOPS we want a function that will not take any kind of exception, and will return NULL for the not-accessible case. Rename allocation_tag_mem() to allocation_tag_mem_probe() and add an extra 'probe' argument that lets us distinguish these cases; allocation_tag_mem() is now a wrapper that always passes 'false'. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230912140434.1333369-6-peter.maydell@linaro.org --- target/arm/tcg/mte_helper.c | 48 ++++++++++++++++++++++++++++--------- 1 file changed, 37 insertions(+), 11 deletions(-) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index e2494f73cf3..303bcc7fd84 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -50,13 +50,14 @@ static int choose_nonexcluded_tag(int tag, int offset, = uint16_t exclude) } =20 /** - * allocation_tag_mem: + * allocation_tag_mem_probe: * @env: the cpu environment * @ptr_mmu_idx: the addressing regime to use for the virtual address * @ptr: the virtual address for which to look up tag memory * @ptr_access: the access to use for the virtual address * @ptr_size: the number of bytes in the normal memory access * @tag_access: the access to use for the tag memory + * @probe: true to merely probe, never taking an exception * @ra: the return address for exception handling * * Our tag memory is formatted as a sequence of little-endian nibbles. @@ -65,15 +66,25 @@ static int choose_nonexcluded_tag(int tag, int offset, = uint16_t exclude) * for the higher addr. * * Here, resolve the physical address from the virtual address, and return - * a pointer to the corresponding tag byte. Exit with exception if the - * virtual address is not accessible for @ptr_access. + * a pointer to the corresponding tag byte. * * If there is no tag storage corresponding to @ptr, return NULL. + * + * If the page is inaccessible for @ptr_access, or has a watchpoint, there= are + * three options: + * (1) probe =3D true, ra =3D 0 : pure probe -- we return NULL if the page= is not + * accessible, and do not take watchpoint traps. The calling code must + * handle those cases in the right priority compared to MTE traps. + * (2) probe =3D false, ra =3D 0 : probe, no fault expected -- the caller = guarantees + * that the page is going to be accessible. We will take watchpoint tr= aps. + * (3) probe =3D false, ra !=3D 0 : non-probe -- we will take both memory = access + * traps and watchpoint traps. + * (probe =3D true, ra !=3D 0 is invalid and will assert.) */ -static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, - uint64_t ptr, MMUAccessType ptr_access, - int ptr_size, MMUAccessType tag_access, - uintptr_t ra) +static uint8_t *allocation_tag_mem_probe(CPUARMState *env, int ptr_mmu_idx, + uint64_t ptr, MMUAccessType ptr_a= ccess, + int ptr_size, MMUAccessType tag_a= ccess, + bool probe, uintptr_t ra) { #ifdef CONFIG_USER_ONLY uint64_t clean_ptr =3D useronly_clean_ptr(ptr); @@ -81,6 +92,8 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int = ptr_mmu_idx, uint8_t *tags; uintptr_t index; =20 + assert(!(probe && ra)); + if (!(flags & (ptr_access =3D=3D MMU_DATA_STORE ? PAGE_WRITE_ORG : PAG= E_READ))) { cpu_loop_exit_sigsegv(env_cpu(env), ptr, ptr_access, !(flags & PAGE_VALID), ra); @@ -111,12 +124,16 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, = int ptr_mmu_idx, * exception for inaccessible pages, and resolves the virtual address * into the softmmu tlb. * - * When RA =3D=3D 0, this is for mte_probe. The page is expected to be - * valid. Indicate to probe_access_flags no-fault, then assert that - * we received a valid page. + * When RA =3D=3D 0, this is either a pure probe or a no-fault-expecte= d probe. + * Indicate to probe_access_flags no-fault, then either return NULL + * for the pure probe, or assert that we received a valid page for the + * no-fault-expected probe. */ flags =3D probe_access_full(env, ptr, 0, ptr_access, ptr_mmu_idx, ra =3D=3D 0, &host, &full, ra); + if (probe && (flags & TLB_INVALID_MASK)) { + return NULL; + } assert(!(flags & TLB_INVALID_MASK)); =20 /* If the virtual page MemAttr !=3D Tagged, access unchecked. */ @@ -157,7 +174,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, } =20 /* Any debug exception has priority over a tag check exception. */ - if (unlikely(flags & TLB_WATCHPOINT)) { + if (!probe && unlikely(flags & TLB_WATCHPOINT)) { int wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_= WRITE; assert(ra !=3D 0); cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, attrs, wp, ra); @@ -199,6 +216,15 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, i= nt ptr_mmu_idx, #endif } =20 +static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, + uint64_t ptr, MMUAccessType ptr_access, + int ptr_size, MMUAccessType tag_access, + uintptr_t ra) +{ + return allocation_tag_mem_probe(env, ptr_mmu_idx, ptr, ptr_access, + ptr_size, tag_access, false, ra); +} + uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) { uint16_t exclude =3D extract32(rm | env->cp15.gcr_el1, 0, 16); --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695317963; cv=none; d=zohomail.com; s=zohoarc; b=m4Z+p0iaGqp+/kiEStPzeu4bO4yfauSnqypi6ncf5wiayDPAlyVVmIPJLdrWoDXMoKPNoBCFpaLcLQEVwA9AhIM5uPE7LIzWjqoyuVH5FWgvrozdWZMOsWM2avQYJBPDCqPR1GV2rPMSOKrDP299IxMxIHwDx+hKzuObKkk44Ag= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695317963; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LcRcGJor0MGZo2nDNYWDJWZqyFuxFvZG3QWQOj74XxU=; b=gsQFISTBfqkbaJYj6yfmOjiSdXzoL3DdnImpUR4T+OWMknu8KnemoNg5gXVZDAzn9cbCbzk1p2U/jrfTHxbiVkE6s/a2GeuAiHoMRP4puxbcl30aogpMD/JxCE6Fg1ryyAbcZ/RXyonMTHgHMgSCAqkF3H+ks39QhctWjQZaQbo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695317963573565.7940060633701; Thu, 21 Sep 2023 10:39:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNcV-00026S-2v; Thu, 21 Sep 2023 13:37:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNcN-00021m-PI for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:35 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcJ-0007g8-Hi for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:35 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4050bd2e33aso13260055e9.2 for ; Thu, 21 Sep 2023 10:37:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695317964101100003 Content-Type: text/plain; charset="utf-8" The FEAT_MOPS instructions need a couple of helper routines that check for MTE tag failures: * mte_mops_probe() checks whether there is going to be a tag error in the next up-to-a-page worth of data * mte_check_fail() is an existing function to record the fact of a tag failure, which we need to make global so we can call it from helper-a64.c Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230912140434.1333369-7-peter.maydell@linaro.org --- target/arm/internals.h | 28 +++++++++++++++++++ target/arm/tcg/mte_helper.c | 54 +++++++++++++++++++++++++++++++++++-- 2 files changed, 80 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 5f5393b25c4..a70a7fd50f6 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1272,6 +1272,34 @@ FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - 12) /* = size - 1 */ bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr); uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_= t ra); =20 +/** + * mte_mops_probe: Check where the next MTE failure is for a FEAT_MOPS ope= ration + * @env: CPU env + * @ptr: start address of memory region (dirty pointer) + * @size: length of region (guaranteed not to cross a page boundary) + * @desc: MTEDESC descriptor word (0 means no MTE checks) + * Returns: the size of the region that can be copied without hitting + * an MTE tag failure + * + * Note that we assume that the caller has already checked the TBI + * and TCMA bits with mte_checks_needed() and an MTE check is definitely + * required. + */ +uint64_t mte_mops_probe(CPUARMState *env, uint64_t ptr, uint64_t size, + uint32_t desc); + +/** + * mte_check_fail: Record an MTE tag check failure + * @env: CPU env + * @desc: MTEDESC descriptor word + * @dirty_ptr: Failing dirty address + * @ra: TCG retaddr + * + * This may never return (if the MTE tag checks are configured to fault). + */ +void mte_check_fail(CPUARMState *env, uint32_t desc, + uint64_t dirty_ptr, uintptr_t ra); + static inline int allocation_tag_from_addr(uint64_t ptr) { return extract64(ptr, 56, 4); diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 303bcc7fd84..1cb61cea7af 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -617,8 +617,8 @@ static void mte_async_check_fail(CPUARMState *env, uint= 64_t dirty_ptr, } =20 /* Record a tag check failure. */ -static void mte_check_fail(CPUARMState *env, uint32_t desc, - uint64_t dirty_ptr, uintptr_t ra) +void mte_check_fail(CPUARMState *env, uint32_t desc, + uint64_t dirty_ptr, uintptr_t ra) { int mmu_idx =3D FIELD_EX32(desc, MTEDESC, MIDX); ARMMMUIdx arm_mmu_idx =3D core_to_aa64_mmu_idx(mmu_idx); @@ -991,3 +991,53 @@ uint64_t HELPER(mte_check_zva)(CPUARMState *env, uint3= 2_t desc, uint64_t ptr) done: return useronly_clean_ptr(ptr); } + +uint64_t mte_mops_probe(CPUARMState *env, uint64_t ptr, uint64_t size, + uint32_t desc) +{ + int mmu_idx, tag_count; + uint64_t ptr_tag, tag_first, tag_last; + void *mem; + bool w =3D FIELD_EX32(desc, MTEDESC, WRITE); + uint32_t n; + + mmu_idx =3D FIELD_EX32(desc, MTEDESC, MIDX); + /* True probe; this will never fault */ + mem =3D allocation_tag_mem_probe(env, mmu_idx, ptr, + w ? MMU_DATA_STORE : MMU_DATA_LOAD, + size, MMU_DATA_LOAD, true, 0); + if (!mem) { + return size; + } + + /* + * TODO: checkN() is not designed for checks of the size we expect + * for FEAT_MOPS operations, so we should implement this differently. + * Maybe we should do something like + * if (region start and size are aligned nicely) { + * do direct loads of 64 tag bits at a time; + * } else { + * call checkN() + * } + */ + /* Round the bounds to the tag granule, and compute the number of tags= . */ + ptr_tag =3D allocation_tag_from_addr(ptr); + tag_first =3D QEMU_ALIGN_DOWN(ptr, TAG_GRANULE); + tag_last =3D QEMU_ALIGN_DOWN(ptr + size - 1, TAG_GRANULE); + tag_count =3D ((tag_last - tag_first) / TAG_GRANULE) + 1; + n =3D checkN(mem, ptr & TAG_GRANULE, ptr_tag, tag_count); + if (likely(n =3D=3D tag_count)) { + return size; + } + + /* + * Failure; for the first granule, it's at @ptr. Otherwise + * it's at the first byte of the nth granule. Calculate how + * many bytes we can access without hitting that failure. + */ + if (n =3D=3D 0) { + return 0; + } else { + return n * TAG_GRANULE - (ptr - tag_first); + } +} --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695318116; cv=none; d=zohomail.com; s=zohoarc; b=BIAIT3LXvhUiCr/rBYUsR0jVayixEG+l50Hy1RPgwDkjiOcdJU8lun+EiFFN8wtudbKmE315urL2kJPzKcXQgmfB8+AxA9FjPRrrhOdHbSA7i6r0thGYeV1aD2x/+rhvnJoVLKN9kT8OxO9OQkfpanxUmEuo2lVb2lW1l/PSY+4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695318116; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=agiLXpKMvtdbqhZ2UJ0uU0nE66S4BmzY7JC9reZnd9A=; b=VbBy1LV7iZW/S9sj1nkKk+d2BlQF3KhLc3sP4UTt9eXbS1lyBQnpi3AxxNzPnGHW7BJs1pqhvLj8mwJ8pR+Hxf3BbUy2CaDIYlt6hEB1cfjL2SEDqJygSEHzSAfpPEip2ez0ngNz57kIhrJQpaf4ZLIyfv4rfrsQe5N5vp2G0/I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695318116815956.5385064766693; Thu, 21 Sep 2023 10:41:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNcQ-00023W-Dj; Thu, 21 Sep 2023 13:37:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNcP-00022Z-88 for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:37 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcL-0007gF-4O for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:36 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-4053c6f0d55so552145e9.0 for ; Thu, 21 Sep 2023 10:37:32 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317851; x=1695922651; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=agiLXpKMvtdbqhZ2UJ0uU0nE66S4BmzY7JC9reZnd9A=; b=adbmXJN8S12gwY4utLdQZdh86+EA/Fs2JS+t3ILDsZTch8zdV/wnPsaszLlN3UmiBw r9q9vz0Z5E5/48qAoyTye51DiFYAnvSWDKwz8Z2kzmeOTU0zkycKqJqmtCGLPWEV8+eN Ov6RbNrQdReM2+dZTRCPSSv4DAa903kmohqPTsNzwIuTkCn3fXXcSpG1w86ElwsXxkEn kqEvXn3kE3QaxLC+P876/uZLv/UpNw9L7l+BgWN6ZkPuQLiWBkHdLOUbccIl8SzWUiJ9 OOvoi9KL+VoSvujLGVWFHRr6HKLKwcSmUIHI/qfE64yESWkriIj6EKlPee4Na+z0STKb rtIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317851; x=1695922651; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=agiLXpKMvtdbqhZ2UJ0uU0nE66S4BmzY7JC9reZnd9A=; b=l0YSRp+cH7RnZmzed7GEEsCMwyIx37GOxS2XFHMWqYzPnlfDowhzf06v7aFizYcSFc Wxn9sozY3t8jc+KI1BOch/MIESuMh1RUtfxfMMXC/ySA86fXd3/hDQW/U3tvLZqeit76 65rPgCzQ4SPqHNoFRnzs1/gEDV1bSK7aGVsdDrP0BnUhbHoVvGN8mI5FnwZT76OA/Ns+ Udp/j4z26W1G8rjVXvaAU+RRkkB0zH5klh1QcbHFwRlYoqNoFiEt0cvuUs4ENLyTPEPR ExvUc7NdS0cN5DOBxLWQOwrLypeOW34L0s/W6cDu9SJpjXB6GTzOW3VyhYNB3+T+ilD2 XzFg== X-Gm-Message-State: AOJu0Yx1YDnuudqWRFJkxmcfuxcnL07FkY/0m3yCfveDVbJVwZkLf5kH M4wRIkUfWuuzLkqsUNihbxJkSTOu3131tTI2OIc= X-Google-Smtp-Source: AGHT+IE3vZTQ2kfevFPnHIlR8GUxPULncRkmgh0ACqbSg4m8ctL/2cGMt8kNGHF6QNZByILs5H81Ug== X-Received: by 2002:a1c:ed04:0:b0:401:daf2:2737 with SMTP id l4-20020a1ced04000000b00401daf22737mr5544341wmh.30.1695317850617; Thu, 21 Sep 2023 10:37:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/30] target/arm: Implement the SET* instructions Date: Thu, 21 Sep 2023 18:37:07 +0100 Message-Id: <20230921173720.3250581-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318117993100013 Content-Type: text/plain; charset="utf-8" Implement the SET* instructions which collectively implement a "memset" operation. These come in a set of three, eg SETP (prologue), SETM (main), SETE (epilogue), and each of those has different flavours to indicate whether memory accesses should be unpriv or non-temporal. This commit does not include the "memset with tag setting" SETG* instructions. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230912140434.1333369-8-peter.maydell@linaro.org --- target/arm/tcg/helper-a64.h | 4 + target/arm/tcg/a64.decode | 16 ++ target/arm/tcg/helper-a64.c | 344 +++++++++++++++++++++++++++++++++ target/arm/tcg/translate-a64.c | 49 +++++ 4 files changed, 413 insertions(+) diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h index 57cfd68569e..7ce5d2105ad 100644 --- a/target/arm/tcg/helper-a64.h +++ b/target/arm/tcg/helper-a64.h @@ -117,3 +117,7 @@ DEF_HELPER_FLAGS_3(stzgm_tags, TCG_CALL_NO_WG, void, en= v, i64, i64) =20 DEF_HELPER_FLAGS_4(unaligned_access, TCG_CALL_NO_WG, noreturn, env, i64, i32, i32) + +DEF_HELPER_3(setp, void, env, i32, i32) +DEF_HELPER_3(setm, void, env, i32, i32) +DEF_HELPER_3(sete, void, env, i32, i32) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 71113173020..c2a97328eeb 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -554,3 +554,19 @@ LDGM 11011001 11 1 ......... 00 ..... .....= @ldst_tag_mult p=3D0 w=3D0 STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=3D1 w= =3D1 STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=3D0 w= =3D0 STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=3D0 w= =3D1 + +# Memory operations (memset, memcpy, memmove) +# Each of these comes in a set of three, eg SETP (prologue), SETM (main), +# SETE (epilogue), and each of those has different flavours to +# indicate whether memory accesses should be unpriv or non-temporal. +# We don't distinguish temporal and non-temporal accesses, but we +# do need to report it in syndrome register values. + +# Memset +&set rs rn rd unpriv nontemp +# op2 bit 1 is nontemporal bit +@set .. ......... rs:5 .. nontemp:1 unpriv:1 .. rn:5 rd:5 &set + +SETP 00 011001110 ..... 00 . . 01 ..... ..... @set +SETM 00 011001110 ..... 01 . . 01 ..... ..... @set +SETE 00 011001110 ..... 10 . . 01 ..... ..... @set diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 0cf56f6dc44..24ae5ecf32e 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -968,3 +968,347 @@ void HELPER(unaligned_access)(CPUARMState *env, uint6= 4_t addr, arm_cpu_do_unaligned_access(env_cpu(env), addr, access_type, mmu_idx, GETPC()); } + +/* Memory operations (memset, memmove, memcpy) */ + +/* + * Return true if the CPY* and SET* insns can execute; compare + * pseudocode CheckMOPSEnabled(), though we refactor it a little. + */ +static bool mops_enabled(CPUARMState *env) +{ + int el =3D arm_current_el(env); + + if (el < 2 && + (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE) && + !(arm_hcrx_el2_eff(env) & HCRX_MSCEN)) { + return false; + } + + if (el =3D=3D 0) { + if (!el_is_in_host(env, 0)) { + return env->cp15.sctlr_el[1] & SCTLR_MSCEN; + } else { + return env->cp15.sctlr_el[2] & SCTLR_MSCEN; + } + } + return true; +} + +static void check_mops_enabled(CPUARMState *env, uintptr_t ra) +{ + if (!mops_enabled(env)) { + raise_exception_ra(env, EXCP_UDEF, syn_uncategorized(), + exception_target_el(env), ra); + } +} + +/* + * Return the target exception level for an exception due + * to mismatched arguments in a FEAT_MOPS copy or set. + * Compare pseudocode MismatchedCpySetTargetEL() + */ +static int mops_mismatch_exception_target_el(CPUARMState *env) +{ + int el =3D arm_current_el(env); + + if (el > 1) { + return el; + } + if (el =3D=3D 0 && (arm_hcr_el2_eff(env) & HCR_TGE)) { + return 2; + } + if (el =3D=3D 1 && (arm_hcrx_el2_eff(env) & HCRX_MCE2)) { + return 2; + } + return 1; +} + +/* + * Check whether an M or E instruction was executed with a CF value + * indicating the wrong option for this implementation. + * Assumes we are always Option A. + */ +static void check_mops_wrong_option(CPUARMState *env, uint32_t syndrome, + uintptr_t ra) +{ + if (env->CF !=3D 0) { + syndrome |=3D 1 << 17; /* Set the wrong-option bit */ + raise_exception_ra(env, EXCP_UDEF, syndrome, + mops_mismatch_exception_target_el(env), ra); + } +} + +/* + * Return the maximum number of bytes we can transfer starting at addr + * without crossing a page boundary. + */ +static uint64_t page_limit(uint64_t addr) +{ + return TARGET_PAGE_ALIGN(addr + 1) - addr; +} + +/* + * Perform part of a memory set on an area of guest memory starting at + * toaddr (a dirty address) and extending for setsize bytes. + * + * Returns the number of bytes actually set, which might be less than + * setsize; the caller should loop until the whole set has been done. + * The caller should ensure that the guest registers are correct + * for the possibility that the first byte of the set encounters + * an exception or watchpoint. We guarantee not to take any faults + * for bytes other than the first. + */ +static uint64_t set_step(CPUARMState *env, uint64_t toaddr, + uint64_t setsize, uint32_t data, int memidx, + uint32_t *mtedesc, uintptr_t ra) +{ + void *mem; + + setsize =3D MIN(setsize, page_limit(toaddr)); + if (*mtedesc) { + uint64_t mtesize =3D mte_mops_probe(env, toaddr, setsize, *mtedesc= ); + if (mtesize =3D=3D 0) { + /* Trap, or not. All CPU state is up to date */ + mte_check_fail(env, *mtedesc, toaddr, ra); + /* Continue, with no further MTE checks required */ + *mtedesc =3D 0; + } else { + /* Advance to the end, or to the tag mismatch */ + setsize =3D MIN(setsize, mtesize); + } + } + + toaddr =3D useronly_clean_ptr(toaddr); + /* + * Trapless lookup: returns NULL for invalid page, I/O, + * watchpoints, clean pages, etc. + */ + mem =3D tlb_vaddr_to_host(env, toaddr, MMU_DATA_STORE, memidx); + +#ifndef CONFIG_USER_ONLY + if (unlikely(!mem)) { + /* + * Slow-path: just do one byte write. This will handle the + * watchpoint, invalid page, etc handling correctly. + * For clean code pages, the next iteration will see + * the page dirty and will use the fast path. + */ + cpu_stb_mmuidx_ra(env, toaddr, data, memidx, ra); + return 1; + } +#endif + /* Easy case: just memset the host memory */ + memset(mem, data, setsize); + return setsize; +} + +typedef uint64_t StepFn(CPUARMState *env, uint64_t toaddr, + uint64_t setsize, uint32_t data, + int memidx, uint32_t *mtedesc, uintptr_t ra); + +/* Extract register numbers from a MOPS exception syndrome value */ +static int mops_destreg(uint32_t syndrome) +{ + return extract32(syndrome, 10, 5); +} + +static int mops_srcreg(uint32_t syndrome) +{ + return extract32(syndrome, 5, 5); +} + +static int mops_sizereg(uint32_t syndrome) +{ + return extract32(syndrome, 0, 5); +} + +/* + * Return true if TCMA and TBI bits mean we need to do MTE checks. + * We only need to do this once per MOPS insn, not for every page. + */ +static bool mte_checks_needed(uint64_t ptr, uint32_t desc) +{ + int bit55 =3D extract64(ptr, 55, 1); + + /* + * Note that tbi_check() returns true for "access checked" but + * tcma_check() returns true for "access unchecked". + */ + if (!tbi_check(desc, bit55)) { + return false; + } + return !tcma_check(desc, bit55, allocation_tag_from_addr(ptr)); +} + +/* + * For the Memory Set operation, our implementation chooses + * always to use "option A", where we update Xd to the final + * address in the SETP insn, and set Xn to be -(bytes remaining). + * On SETM and SETE insns we only need update Xn. + * + * @env: CPU + * @syndrome: syndrome value for mismatch exceptions + * (also contains the register numbers we need to use) + * @mtedesc: MTE descriptor word + * @stepfn: function which does a single part of the set operation + * @is_setg: true if this is the tag-setting SETG variant + */ +static void do_setp(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc, + StepFn *stepfn, bool is_setg, uintptr_t ra) +{ + /* Prologue: we choose to do up to the next page boundary */ + int rd =3D mops_destreg(syndrome); + int rs =3D mops_srcreg(syndrome); + int rn =3D mops_sizereg(syndrome); + uint8_t data =3D env->xregs[rs]; + uint32_t memidx =3D FIELD_EX32(mtedesc, MTEDESC, MIDX); + uint64_t toaddr =3D env->xregs[rd]; + uint64_t setsize =3D env->xregs[rn]; + uint64_t stagesetsize, step; + + check_mops_enabled(env, ra); + + if (setsize > INT64_MAX) { + setsize =3D INT64_MAX; + } + + if (!mte_checks_needed(toaddr, mtedesc)) { + mtedesc =3D 0; + } + + stagesetsize =3D MIN(setsize, page_limit(toaddr)); + while (stagesetsize) { + env->xregs[rd] =3D toaddr; + env->xregs[rn] =3D setsize; + step =3D stepfn(env, toaddr, stagesetsize, data, memidx, &mtedesc,= ra); + toaddr +=3D step; + setsize -=3D step; + stagesetsize -=3D step; + } + /* Insn completed, so update registers to the Option A format */ + env->xregs[rd] =3D toaddr + setsize; + env->xregs[rn] =3D -setsize; + + /* Set NZCV =3D 0000 to indicate we are an Option A implementation */ + env->NF =3D 0; + env->ZF =3D 1; /* our env->ZF encoding is inverted */ + env->CF =3D 0; + env->VF =3D 0; + return; +} + +void HELPER(setp)(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc) +{ + do_setp(env, syndrome, mtedesc, set_step, false, GETPC()); +} + +static void do_setm(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc, + StepFn *stepfn, bool is_setg, uintptr_t ra) +{ + /* Main: we choose to do all the full-page chunks */ + CPUState *cs =3D env_cpu(env); + int rd =3D mops_destreg(syndrome); + int rs =3D mops_srcreg(syndrome); + int rn =3D mops_sizereg(syndrome); + uint8_t data =3D env->xregs[rs]; + uint64_t toaddr =3D env->xregs[rd] + env->xregs[rn]; + uint64_t setsize =3D -env->xregs[rn]; + uint32_t memidx =3D FIELD_EX32(mtedesc, MTEDESC, MIDX); + uint64_t step, stagesetsize; + + check_mops_enabled(env, ra); + + /* + * We're allowed to NOP out "no data to copy" before the consistency + * checks; we choose to do so. + */ + if (env->xregs[rn] =3D=3D 0) { + return; + } + + check_mops_wrong_option(env, syndrome, ra); + + /* + * Our implementation will work fine even if we have an unaligned + * destination address, and because we update Xn every time around + * the loop below and the return value from stepfn() may be less + * than requested, we might find toaddr is unaligned. So we don't + * have an IMPDEF check for alignment here. + */ + + if (!mte_checks_needed(toaddr, mtedesc)) { + mtedesc =3D 0; + } + + /* Do the actual memset: we leave the last partial page to SETE */ + stagesetsize =3D setsize & TARGET_PAGE_MASK; + while (stagesetsize > 0) { + step =3D stepfn(env, toaddr, setsize, data, memidx, &mtedesc, ra); + toaddr +=3D step; + setsize -=3D step; + stagesetsize -=3D step; + env->xregs[rn] =3D -setsize; + if (stagesetsize > 0 && unlikely(cpu_loop_exit_requested(cs))) { + cpu_loop_exit_restore(cs, ra); + } + } +} + +void HELPER(setm)(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc) +{ + do_setm(env, syndrome, mtedesc, set_step, false, GETPC()); +} + +static void do_sete(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc, + StepFn *stepfn, bool is_setg, uintptr_t ra) +{ + /* Epilogue: do the last partial page */ + int rd =3D mops_destreg(syndrome); + int rs =3D mops_srcreg(syndrome); + int rn =3D mops_sizereg(syndrome); + uint8_t data =3D env->xregs[rs]; + uint64_t toaddr =3D env->xregs[rd] + env->xregs[rn]; + uint64_t setsize =3D -env->xregs[rn]; + uint32_t memidx =3D FIELD_EX32(mtedesc, MTEDESC, MIDX); + uint64_t step; + + check_mops_enabled(env, ra); + + /* + * We're allowed to NOP out "no data to copy" before the consistency + * checks; we choose to do so. + */ + if (setsize =3D=3D 0) { + return; + } + + check_mops_wrong_option(env, syndrome, ra); + + /* + * Our implementation has no address alignment requirements, but + * we do want to enforce the "less than a page" size requirement, + * so we don't need to have the "check for interrupts" here. + */ + if (setsize >=3D TARGET_PAGE_SIZE) { + raise_exception_ra(env, EXCP_UDEF, syndrome, + mops_mismatch_exception_target_el(env), ra); + } + + if (!mte_checks_needed(toaddr, mtedesc)) { + mtedesc =3D 0; + } + + /* Do the actual memset */ + while (setsize > 0) { + step =3D stepfn(env, toaddr, setsize, data, memidx, &mtedesc, ra); + toaddr +=3D step; + setsize -=3D step; + env->xregs[rn] =3D -setsize; + } +} + +void HELPER(sete)(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc) +{ + do_sete(env, syndrome, mtedesc, set_step, false, GETPC()); +} diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 24afd929144..bb7b15cb6cb 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3962,6 +3962,55 @@ TRANS_FEAT(STZG, aa64_mte_insn_reg, do_STG, a, true,= false) TRANS_FEAT(ST2G, aa64_mte_insn_reg, do_STG, a, false, true) TRANS_FEAT(STZ2G, aa64_mte_insn_reg, do_STG, a, true, true) =20 +typedef void SetFn(TCGv_env, TCGv_i32, TCGv_i32); + +static bool do_SET(DisasContext *s, arg_set *a, bool is_epilogue, SetFn fn) +{ + int memidx; + uint32_t syndrome, desc =3D 0; + + /* + * UNPREDICTABLE cases: we choose to UNDEF, which allows + * us to pull this check before the CheckMOPSEnabled() test + * (which we do in the helper function) + */ + if (a->rs =3D=3D a->rn || a->rs =3D=3D a->rd || a->rn =3D=3D a->rd || + a->rd =3D=3D 31 || a->rn =3D=3D 31) { + return false; + } + + memidx =3D get_a64_user_mem_index(s, a->unpriv); + + /* + * We pass option_a =3D=3D true, matching our implementation; + * we pass wrong_option =3D=3D false: helper function may set that bit. + */ + syndrome =3D syn_mop(true, false, (a->nontemp << 1) | a->unpriv, + is_epilogue, false, true, a->rd, a->rs, a->rn); + + if (s->mte_active[a->unpriv]) { + /* We may need to do MTE tag checking, so assemble the descriptor = */ + desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); + desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); + desc =3D FIELD_DP32(desc, MTEDESC, WRITE, true); + /* SIZEM1 and ALIGN we leave 0 (byte write) */ + } + /* The helper function always needs the memidx even with MTE disabled = */ + desc =3D FIELD_DP32(desc, MTEDESC, MIDX, memidx); + + /* + * The helper needs the register numbers, but since they're in + * the syndrome anyway, we let it extract them from there rather + * than passing in an extra three integer arguments. + */ + fn(cpu_env, tcg_constant_i32(syndrome), tcg_constant_i32(desc)); + return true; +} + +TRANS_FEAT(SETP, aa64_mops, do_SET, a, false, gen_helper_setp) +TRANS_FEAT(SETM, aa64_mops, do_SET, a, false, gen_helper_setm) +TRANS_FEAT(SETE, aa64_mops, do_SET, a, true, gen_helper_sete) + typedef void ArithTwoOp(TCGv_i64, TCGv_i64, TCGv_i64); =20 static bool gen_rri(DisasContext *s, arg_rri_sf *a, --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695317960; cv=none; d=zohomail.com; s=zohoarc; b=gdBbjqaxkLNUo3mDUoTKN7pp3ijPFeNNPZBnGLB/coXbMuli+R+/8cPCXFml6A3BLTjpZWpecmmeTPi2HRZE+u0rioQejLbP6reft5khLEU8l+pEYBv4rVX2d74t6UHJOrazLpCGd8F8IVXQm+yzDGptB4yx2OvOdNKVK+P/MVU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317851; x=1695922651; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=dmuvaaYoP/Fi5t0N0sksvsjI9aosmFW5msIPLrKstQI=; b=Bxq94pLSyoMSU3gCfwT9Ve9IHyxAxUl4j482clX8lHI8HgKLDTXy11NFtAHMeDC970 VdNfqeFYN1gBhf495RyeJexDYv6syf89t5iX/7pV6Uj+P3JFHl962FxwFQuilDuCSK12 4M2oSkmfyo3lqRozH7I9aGJ2W/EetzAwzMB8cN39QxHenqCCoxcaMDbx/89jbD3b3lYP 6SzQCbbMvco9dQk450kUh7e+KOxYJj/vTeL9KzIW/2ivFu2p76Td2yZVpaZXHNgjm0CE Y0snPU3WjUNR7yID9UK3Zo3ssi0RCauSoO3u6GgPoF9ZfOGEu/GCJYI1MOxmJy5eSGux KNvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317851; x=1695922651; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dmuvaaYoP/Fi5t0N0sksvsjI9aosmFW5msIPLrKstQI=; b=xB5H6wyLnNtJJHmj3Uni3onz0yfKDOauMH+ETj1POs8EEmeDLE0DuahcKjNwvK6if6 3vlmasJvR6PmNKYt5IvHlgj3484OSL7Vd6K9oJueGBh0MnYpAijrafTP78kFE/aLDB9n kNTfKf2/TnSNp3ARxo/V8/3As8Q01b8VOhy4+1FFjjyDfIeQkyYlh0hZqGL9Gb+k8SQd o9PGfdsVPN8YyPpw5VTLPFZEd+uSYLKd3RoHOkeglw9PxI9wnLLcrItCbNihv3PhHrK6 IgG6oSjU/qjZzkQjH23QhAOIWoBY1QN/2rhXBjq10VzLJjgk4lgNjXuC8J32nnq3HIp9 2b2g== X-Gm-Message-State: AOJu0Yxchx1aadvHbHbpkr2Rc3jl8fxrLZY8O/6tCVgHu9BM/5mfFr0+ 2nr2266yaNbCCDMloC6lOJ0Fa7RNzg+64wKeBNw= X-Google-Smtp-Source: AGHT+IFAwsjY1hjah6RdnLYGuBsndFZjcoaINjWA9cM4OrfrPzJvnjDc6ukpUzuNSkevd7qdHMeLjw== X-Received: by 2002:adf:9dc5:0:b0:321:9979:99ef with SMTP id q5-20020adf9dc5000000b00321997999efmr2429963wre.48.1695317851042; Thu, 21 Sep 2023 10:37:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/30] target/arm: Define new TB flag for ATA0 Date: Thu, 21 Sep 2023 18:37:08 +0100 Message-Id: <20230921173720.3250581-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695317960446100001 Content-Type: text/plain; charset="utf-8" Currently the only tag-setting instructions always do so in the context of the current EL, and so we only need one ATA bit in the TB flags. The FEAT_MOPS SETG instructions include ones which set tags for a non-privileged access, so we now also need the equivalent "are tags enabled?" information for EL0. Add the new TB flag, and convert the existing 'bool ata' field in DisasContext to a 'bool ata[2]' that can be indexed by the is_unpriv bit in an instruction, similarly to mte[2]. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230912140434.1333369-9-peter.maydell@linaro.org --- target/arm/cpu.h | 1 + target/arm/tcg/translate.h | 4 ++-- target/arm/tcg/hflags.c | 12 ++++++++++++ target/arm/tcg/translate-a64.c | 23 ++++++++++++----------- 4 files changed, 27 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 266c1a9ea1b..bd55c5dabfd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3171,6 +3171,7 @@ FIELD(TBFLAG_A64, SVL, 24, 4) FIELD(TBFLAG_A64, SME_TRAP_NONSTREAMING, 28, 1) FIELD(TBFLAG_A64, FGT_ERET, 29, 1) FIELD(TBFLAG_A64, NAA, 30, 1) +FIELD(TBFLAG_A64, ATA0, 31, 1) =20 /* * Helpers for using the above. diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index f748ba6f394..63922f8bad1 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -114,8 +114,8 @@ typedef struct DisasContext { bool unpriv; /* True if v8.3-PAuth is active. */ bool pauth_active; - /* True if v8.5-MTE access to tags is enabled. */ - bool ata; + /* True if v8.5-MTE access to tags is enabled; index with is_unpriv. = */ + bool ata[2]; /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv. */ bool mte_active[2]; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index ea642384f5a..cea1adb7b62 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -325,6 +325,18 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, && allocation_tag_access_enabled(env, 0, sctlr)) { DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1); } + /* + * For unpriv tag-setting accesses we alse need ATA0. Again, in + * contexts where unpriv and normal insns are the same we + * duplicate the ATA bit to save effort for translate-a64.c. + */ + if (EX_TBFLAG_A64(flags, UNPRIV)) { + if (allocation_tag_access_enabled(env, 0, sctlr)) { + DP_TBFLAG_A64(flags, ATA0, 1); + } + } else { + DP_TBFLAG_A64(flags, ATA0, EX_TBFLAG_A64(flags, ATA)); + } /* Cache TCMA as well as TBI. */ DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx)); } diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index bb7b15cb6cb..da4aabbaf4e 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2272,7 +2272,7 @@ static void handle_sys(DisasContext *s, bool isread, clean_addr =3D clean_data_tbi(s, tcg_rt); gen_probe_access(s, clean_addr, MMU_DATA_STORE, MO_8); =20 - if (s->ata) { + if (s->ata[0]) { /* Extract the tag from the register to match STZGM. */ tag =3D tcg_temp_new_i64(); tcg_gen_shri_i64(tag, tcg_rt, 56); @@ -2289,7 +2289,7 @@ static void handle_sys(DisasContext *s, bool isread, clean_addr =3D clean_data_tbi(s, tcg_rt); gen_helper_dc_zva(cpu_env, clean_addr); =20 - if (s->ata) { + if (s->ata[0]) { /* Extract the tag from the register to match STZGM. */ tag =3D tcg_temp_new_i64(); tcg_gen_shri_i64(tag, tcg_rt, 56); @@ -3070,7 +3070,7 @@ static bool trans_STGP(DisasContext *s, arg_ldstpair = *a) tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mop); =20 /* Perform the tag store, if tag access enabled. */ - if (s->ata) { + if (s->ata[0]) { if (tb_cflags(s->base.tb) & CF_PARALLEL) { gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr); } else { @@ -3768,7 +3768,7 @@ static bool trans_STZGM(DisasContext *s, arg_ldst_tag= *a) tcg_gen_addi_i64(addr, addr, a->imm); tcg_rt =3D cpu_reg(s, a->rt); =20 - if (s->ata) { + if (s->ata[0]) { gen_helper_stzgm_tags(cpu_env, addr, tcg_rt); } /* @@ -3800,7 +3800,7 @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag = *a) tcg_gen_addi_i64(addr, addr, a->imm); tcg_rt =3D cpu_reg(s, a->rt); =20 - if (s->ata) { + if (s->ata[0]) { gen_helper_stgm(cpu_env, addr, tcg_rt); } else { MMUAccessType acc =3D MMU_DATA_STORE; @@ -3832,7 +3832,7 @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag = *a) tcg_gen_addi_i64(addr, addr, a->imm); tcg_rt =3D cpu_reg(s, a->rt); =20 - if (s->ata) { + if (s->ata[0]) { gen_helper_ldgm(tcg_rt, cpu_env, addr); } else { MMUAccessType acc =3D MMU_DATA_LOAD; @@ -3867,7 +3867,7 @@ static bool trans_LDG(DisasContext *s, arg_ldst_tag *= a) =20 tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); tcg_rt =3D cpu_reg(s, a->rt); - if (s->ata) { + if (s->ata[0]) { gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); } else { /* @@ -3904,7 +3904,7 @@ static bool do_STG(DisasContext *s, arg_ldst_tag *a, = bool is_zero, bool is_pair) tcg_gen_addi_i64(addr, addr, a->imm); } tcg_rt =3D cpu_reg_sp(s, a->rt); - if (!s->ata) { + if (!s->ata[0]) { /* * For STG and ST2G, we need to check alignment and probe memory. * TODO: For STZG and STZ2G, we could rely on the stores below, @@ -4073,7 +4073,7 @@ static bool gen_add_sub_imm_with_tags(DisasContext *s= , arg_rri_tag *a, tcg_rn =3D cpu_reg_sp(s, a->rn); tcg_rd =3D cpu_reg_sp(s, a->rd); =20 - if (s->ata) { + if (s->ata[0]) { gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, tcg_constant_i32(imm), tcg_constant_i32(a->uimm4)); @@ -5460,7 +5460,7 @@ static void disas_data_proc_2src(DisasContext *s, uin= t32_t insn) if (sf =3D=3D 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { goto do_unallocated; } - if (s->ata) { + if (s->ata[0]) { gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, cpu_reg_sp(s, rn), cpu_reg(s, rm)); } else { @@ -13951,7 +13951,8 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->bt =3D EX_TBFLAG_A64(tb_flags, BT); dc->btype =3D EX_TBFLAG_A64(tb_flags, BTYPE); dc->unpriv =3D EX_TBFLAG_A64(tb_flags, UNPRIV); - dc->ata =3D EX_TBFLAG_A64(tb_flags, ATA); + dc->ata[0] =3D EX_TBFLAG_A64(tb_flags, ATA); + dc->ata[1] =3D EX_TBFLAG_A64(tb_flags, ATA0); dc->mte_active[0] =3D EX_TBFLAG_A64(tb_flags, MTE_ACTIVE); dc->mte_active[1] =3D EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE); dc->pstate_sm =3D EX_TBFLAG_A64(tb_flags, PSTATE_SM); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317851; x=1695922651; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TkAGl7nEcz85enCyFYeSLbqB64U4Fpu8wADrowboWnM=; b=uVHDXQ+2vpM7TqbJzP0soXX+aX2hjZE4LWgysNArxTqvD2J/jrTJPQYTeAjSoFUyoO Oc0L5NAEsMIS3hipAnxkLCInqbQmqyda6Dp57Vq48CVo/2cGvdTLmWNfrd5PgTo73hOr 58RU0fWTg2vWBrQGfjWxajEgq67Q6KMWFXnpr9rb6dHJrVYs35pgLc7KRT0Ly4+Psnm2 dfkyNCzBggwjmkHr5C42SqJlV6aqu0VAyTmf+13Hyy+fR2LsqVaD43UT7ceMiKgbHv/5 xYHk1pz+BG6DDr4BFwvtOMKdgxyKLBpRcsLF+qhmV655oEEsCqgO8DNmT/sWERIUYLle OjFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317851; x=1695922651; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TkAGl7nEcz85enCyFYeSLbqB64U4Fpu8wADrowboWnM=; b=HPbyeTykWrN/QfHOJGwCS5L+Kpo66V+7LZxT5vhLCHuEhnPzTZ33B+F5tSf18wxpuI C+L+wTXwL7flSQWZlvAPU4WxFoLP+uv0XyRllEiT038ZDdiz192J1XGVAUU1wfSw2TUx /v/XeR8W+tSLAYeG9PFEQHGHcPH8KiUHVlUPhcyXs7N2c4GwSZFSgMZyC4B4ZhJ/M2kI 00009mu9/QkbHZpn1KPa/77dcVGj8XCYqIsDKLk4ba+/ju+1mNwXvRfYaLL4RCpvWSLD 9k9y6vstHTf1I8j7nRfH/lmNZHZximJGN2c7iIirQcoFWOSN7MFj47y61smXOI8tVRcI xEng== X-Gm-Message-State: AOJu0Yz9j8rWTr2dnvkZ7JVZ6y+AxswAe7Tdpq0hPt6OiU1fC1pL8cYp qJSkiRN6EYFZ9LqmxQ9RmkS9/fiXiEdQDnZZjv8= X-Google-Smtp-Source: AGHT+IGHOFnTMddioUoKFxO/ZZll4XPCUOtsI8gspVHKLPR6F/ziwrrBvwbqrXfIP/e1KV52rZdpjg== X-Received: by 2002:adf:f84e:0:b0:31c:804b:5ec3 with SMTP id d14-20020adff84e000000b0031c804b5ec3mr5432384wrq.67.1695317851494; Thu, 21 Sep 2023 10:37:31 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/30] target/arm: Implement the SETG* instructions Date: Thu, 21 Sep 2023 18:37:09 +0100 Message-Id: <20230921173720.3250581-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318011583100001 Content-Type: text/plain; charset="utf-8" The FEAT_MOPS SETG* instructions are very similar to the SET* instructions, but as well as setting memory contents they also set the MTE tags. They are architecturally required to operate on tag-granule aligned regions only. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230912140434.1333369-10-peter.maydell@linaro.org --- target/arm/internals.h | 10 ++++ target/arm/tcg/helper-a64.h | 3 ++ target/arm/tcg/a64.decode | 5 ++ target/arm/tcg/helper-a64.c | 86 ++++++++++++++++++++++++++++++++-- target/arm/tcg/mte_helper.c | 40 ++++++++++++++++ target/arm/tcg/translate-a64.c | 20 +++++--- 6 files changed, 155 insertions(+), 9 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a70a7fd50f6..642f77df29b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1300,6 +1300,16 @@ uint64_t mte_mops_probe(CPUARMState *env, uint64_t p= tr, uint64_t size, void mte_check_fail(CPUARMState *env, uint32_t desc, uint64_t dirty_ptr, uintptr_t ra); =20 +/** + * mte_mops_set_tags: Set MTE tags for a portion of a FEAT_MOPS operation + * @env: CPU env + * @dirty_ptr: Start address of memory region (dirty pointer) + * @size: length of region (guaranteed not to cross page boundary) + * @desc: MTEDESC descriptor word + */ +void mte_mops_set_tags(CPUARMState *env, uint64_t dirty_ptr, uint64_t size, + uint32_t desc); + static inline int allocation_tag_from_addr(uint64_t ptr) { return extract64(ptr, 56, 4); diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h index 7ce5d2105ad..10a99107124 100644 --- a/target/arm/tcg/helper-a64.h +++ b/target/arm/tcg/helper-a64.h @@ -121,3 +121,6 @@ DEF_HELPER_FLAGS_4(unaligned_access, TCG_CALL_NO_WG, DEF_HELPER_3(setp, void, env, i32, i32) DEF_HELPER_3(setm, void, env, i32, i32) DEF_HELPER_3(sete, void, env, i32, i32) +DEF_HELPER_3(setgp, void, env, i32, i32) +DEF_HELPER_3(setgm, void, env, i32, i32) +DEF_HELPER_3(setge, void, env, i32, i32) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index c2a97328eeb..a202faa17bc 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -570,3 +570,8 @@ STZ2G 11011001 11 1 ......... 11 ..... ..... = @ldst_tag p=3D0 w=3D1 SETP 00 011001110 ..... 00 . . 01 ..... ..... @set SETM 00 011001110 ..... 01 . . 01 ..... ..... @set SETE 00 011001110 ..... 10 . . 01 ..... ..... @set + +# Like SET, but also setting MTE tags +SETGP 00 011101110 ..... 00 . . 01 ..... ..... @set +SETGM 00 011101110 ..... 01 . . 01 ..... ..... @set +SETGE 00 011101110 ..... 10 . . 01 ..... ..... @set diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 24ae5ecf32e..2cf89184d77 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -1103,6 +1103,50 @@ static uint64_t set_step(CPUARMState *env, uint64_t = toaddr, return setsize; } =20 +/* + * Similar, but setting tags. The architecture requires us to do this + * in 16-byte chunks. SETP accesses are not tag checked; they set + * the tags. + */ +static uint64_t set_step_tags(CPUARMState *env, uint64_t toaddr, + uint64_t setsize, uint32_t data, int memidx, + uint32_t *mtedesc, uintptr_t ra) +{ + void *mem; + uint64_t cleanaddr; + + setsize =3D MIN(setsize, page_limit(toaddr)); + + cleanaddr =3D useronly_clean_ptr(toaddr); + /* + * Trapless lookup: returns NULL for invalid page, I/O, + * watchpoints, clean pages, etc. + */ + mem =3D tlb_vaddr_to_host(env, cleanaddr, MMU_DATA_STORE, memidx); + +#ifndef CONFIG_USER_ONLY + if (unlikely(!mem)) { + /* + * Slow-path: just do one write. This will handle the + * watchpoint, invalid page, etc handling correctly. + * The architecture requires that we do 16 bytes at a time, + * and we know both ptr and size are 16 byte aligned. + * For clean code pages, the next iteration will see + * the page dirty and will use the fast path. + */ + uint64_t repldata =3D data * 0x0101010101010101ULL; + MemOpIdx oi16 =3D make_memop_idx(MO_TE | MO_128, memidx); + cpu_st16_mmu(env, toaddr, int128_make128(repldata, repldata), oi16= , ra); + mte_mops_set_tags(env, toaddr, 16, *mtedesc); + return 16; + } +#endif + /* Easy case: just memset the host memory */ + memset(mem, data, setsize); + mte_mops_set_tags(env, toaddr, setsize, *mtedesc); + return setsize; +} + typedef uint64_t StepFn(CPUARMState *env, uint64_t toaddr, uint64_t setsize, uint32_t data, int memidx, uint32_t *mtedesc, uintptr_t ra); @@ -1141,6 +1185,18 @@ static bool mte_checks_needed(uint64_t ptr, uint32_t= desc) return !tcma_check(desc, bit55, allocation_tag_from_addr(ptr)); } =20 +/* Take an exception if the SETG addr/size are not granule aligned */ +static void check_setg_alignment(CPUARMState *env, uint64_t ptr, uint64_t = size, + uint32_t memidx, uintptr_t ra) +{ + if ((size !=3D 0 && !QEMU_IS_ALIGNED(ptr, TAG_GRANULE)) || + !QEMU_IS_ALIGNED(size, TAG_GRANULE)) { + arm_cpu_do_unaligned_access(env_cpu(env), ptr, MMU_DATA_STORE, + memidx, ra); + + } +} + /* * For the Memory Set operation, our implementation chooses * always to use "option A", where we update Xd to the final @@ -1171,9 +1227,14 @@ static void do_setp(CPUARMState *env, uint32_t syndr= ome, uint32_t mtedesc, =20 if (setsize > INT64_MAX) { setsize =3D INT64_MAX; + if (is_setg) { + setsize &=3D ~0xf; + } } =20 - if (!mte_checks_needed(toaddr, mtedesc)) { + if (unlikely(is_setg)) { + check_setg_alignment(env, toaddr, setsize, memidx, ra); + } else if (!mte_checks_needed(toaddr, mtedesc)) { mtedesc =3D 0; } =20 @@ -1203,6 +1264,11 @@ void HELPER(setp)(CPUARMState *env, uint32_t syndrom= e, uint32_t mtedesc) do_setp(env, syndrome, mtedesc, set_step, false, GETPC()); } =20 +void HELPER(setgp)(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc) +{ + do_setp(env, syndrome, mtedesc, set_step_tags, true, GETPC()); +} + static void do_setm(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc, StepFn *stepfn, bool is_setg, uintptr_t ra) { @@ -1237,7 +1303,9 @@ static void do_setm(CPUARMState *env, uint32_t syndro= me, uint32_t mtedesc, * have an IMPDEF check for alignment here. */ =20 - if (!mte_checks_needed(toaddr, mtedesc)) { + if (unlikely(is_setg)) { + check_setg_alignment(env, toaddr, setsize, memidx, ra); + } else if (!mte_checks_needed(toaddr, mtedesc)) { mtedesc =3D 0; } =20 @@ -1260,6 +1328,11 @@ void HELPER(setm)(CPUARMState *env, uint32_t syndrom= e, uint32_t mtedesc) do_setm(env, syndrome, mtedesc, set_step, false, GETPC()); } =20 +void HELPER(setgm)(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc) +{ + do_setm(env, syndrome, mtedesc, set_step_tags, true, GETPC()); +} + static void do_sete(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc, StepFn *stepfn, bool is_setg, uintptr_t ra) { @@ -1295,7 +1368,9 @@ static void do_sete(CPUARMState *env, uint32_t syndro= me, uint32_t mtedesc, mops_mismatch_exception_target_el(env), ra); } =20 - if (!mte_checks_needed(toaddr, mtedesc)) { + if (unlikely(is_setg)) { + check_setg_alignment(env, toaddr, setsize, memidx, ra); + } else if (!mte_checks_needed(toaddr, mtedesc)) { mtedesc =3D 0; } =20 @@ -1312,3 +1387,8 @@ void HELPER(sete)(CPUARMState *env, uint32_t syndrome= , uint32_t mtedesc) { do_sete(env, syndrome, mtedesc, set_step, false, GETPC()); } + +void HELPER(setge)(CPUARMState *env, uint32_t syndrome, uint32_t mtedesc) +{ + do_sete(env, syndrome, mtedesc, set_step_tags, true, GETPC()); +} diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 1cb61cea7af..66a80eeb950 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -1041,3 +1041,43 @@ uint64_t mte_mops_probe(CPUARMState *env, uint64_t p= tr, uint64_t size, return n * TAG_GRANULE - (ptr - tag_first); } } + +void mte_mops_set_tags(CPUARMState *env, uint64_t ptr, uint64_t size, + uint32_t desc) +{ + int mmu_idx, tag_count; + uint64_t ptr_tag; + void *mem; + + if (!desc) { + /* Tags not actually enabled */ + return; + } + + mmu_idx =3D FIELD_EX32(desc, MTEDESC, MIDX); + /* True probe: this will never fault */ + mem =3D allocation_tag_mem_probe(env, mmu_idx, ptr, MMU_DATA_STORE, si= ze, + MMU_DATA_STORE, true, 0); + if (!mem) { + return; + } + + /* + * We know that ptr and size are both TAG_GRANULE aligned; store + * the tag from the pointer value into the tag memory. + */ + ptr_tag =3D allocation_tag_from_addr(ptr); + tag_count =3D size / TAG_GRANULE; + if (ptr & TAG_GRANULE) { + /* Not 2*TAG_GRANULE-aligned: store tag to first nibble */ + store_tag1_parallel(TAG_GRANULE, mem, ptr_tag); + mem++; + tag_count--; + } + memset(mem, ptr_tag | (ptr_tag << 4), tag_count / 2); + if (tag_count & 1) { + /* Final trailing unaligned nibble */ + mem +=3D tag_count / 2; + store_tag1_parallel(0, mem, ptr_tag); + } +} diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index da4aabbaf4e..27bb3039b4d 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3964,11 +3964,16 @@ TRANS_FEAT(STZ2G, aa64_mte_insn_reg, do_STG, a, tru= e, true) =20 typedef void SetFn(TCGv_env, TCGv_i32, TCGv_i32); =20 -static bool do_SET(DisasContext *s, arg_set *a, bool is_epilogue, SetFn fn) +static bool do_SET(DisasContext *s, arg_set *a, bool is_epilogue, + bool is_setg, SetFn fn) { int memidx; uint32_t syndrome, desc =3D 0; =20 + if (is_setg && !dc_isar_feature(aa64_mte, s)) { + return false; + } + /* * UNPREDICTABLE cases: we choose to UNDEF, which allows * us to pull this check before the CheckMOPSEnabled() test @@ -3985,10 +3990,10 @@ static bool do_SET(DisasContext *s, arg_set *a, boo= l is_epilogue, SetFn fn) * We pass option_a =3D=3D true, matching our implementation; * we pass wrong_option =3D=3D false: helper function may set that bit. */ - syndrome =3D syn_mop(true, false, (a->nontemp << 1) | a->unpriv, + syndrome =3D syn_mop(true, is_setg, (a->nontemp << 1) | a->unpriv, is_epilogue, false, true, a->rd, a->rs, a->rn); =20 - if (s->mte_active[a->unpriv]) { + if (is_setg ? s->ata[a->unpriv] : s->mte_active[a->unpriv]) { /* We may need to do MTE tag checking, so assemble the descriptor = */ desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); @@ -4007,9 +4012,12 @@ static bool do_SET(DisasContext *s, arg_set *a, bool= is_epilogue, SetFn fn) return true; } =20 -TRANS_FEAT(SETP, aa64_mops, do_SET, a, false, gen_helper_setp) -TRANS_FEAT(SETM, aa64_mops, do_SET, a, false, gen_helper_setm) -TRANS_FEAT(SETE, aa64_mops, do_SET, a, true, gen_helper_sete) +TRANS_FEAT(SETP, aa64_mops, do_SET, a, false, false, gen_helper_setp) +TRANS_FEAT(SETM, aa64_mops, do_SET, a, false, false, gen_helper_setm) +TRANS_FEAT(SETE, aa64_mops, do_SET, a, true, false, gen_helper_sete) +TRANS_FEAT(SETGP, aa64_mops, do_SET, a, false, true, gen_helper_setgp) +TRANS_FEAT(SETGM, aa64_mops, do_SET, a, false, true, gen_helper_setgm) +TRANS_FEAT(SETGE, aa64_mops, do_SET, a, true, true, gen_helper_setge) =20 typedef void ArithTwoOp(TCGv_i64, TCGv_i64, TCGv_i64); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318040198100005 Content-Type: text/plain; charset="utf-8" The FEAT_MOPS memory copy operations need an extra helper routine for checking for MTE tag checking failures beyond the ones we already added for memory set operations: * mte_mops_probe_rev() does the same job as mte_mops_probe(), but it checks tags starting at the provided address and working backwards, rather than forwards Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230912140434.1333369-11-peter.maydell@linaro.org --- target/arm/internals.h | 17 +++++++ target/arm/tcg/mte_helper.c | 99 +++++++++++++++++++++++++++++++++++++ 2 files changed, 116 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index 642f77df29b..1dd9182a54a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1288,6 +1288,23 @@ uint64_t mte_check(CPUARMState *env, uint32_t desc, = uint64_t ptr, uintptr_t ra); uint64_t mte_mops_probe(CPUARMState *env, uint64_t ptr, uint64_t size, uint32_t desc); =20 +/** + * mte_mops_probe_rev: Check where the next MTE failure is for a FEAT_MOPS + * operation going in the reverse direction + * @env: CPU env + * @ptr: *end* address of memory region (dirty pointer) + * @size: length of region (guaranteed not to cross a page boundary) + * @desc: MTEDESC descriptor word (0 means no MTE checks) + * Returns: the size of the region that can be copied without hitting + * an MTE tag failure + * + * Note that we assume that the caller has already checked the TBI + * and TCMA bits with mte_checks_needed() and an MTE check is definitely + * required. + */ +uint64_t mte_mops_probe_rev(CPUARMState *env, uint64_t ptr, uint64_t size, + uint32_t desc); + /** * mte_check_fail: Record an MTE tag check failure * @env: CPU env diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 66a80eeb950..2dd7eb3edbf 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -734,6 +734,55 @@ static int checkN(uint8_t *mem, int odd, int cmp, int = count) return n; } =20 +/** + * checkNrev: + * @tag: tag memory to test + * @odd: true to begin testing at tags at odd nibble + * @cmp: the tag to compare against + * @count: number of tags to test + * + * Return the number of successful tests. + * Thus a return value < @count indicates a failure. + * + * This is like checkN, but it runs backwards, checking the + * tags starting with @tag and then the tags preceding it. + * This is needed by the backwards-memory-copying operations. + */ +static int checkNrev(uint8_t *mem, int odd, int cmp, int count) +{ + int n =3D 0, diff; + + /* Replicate the test tag and compare. */ + cmp *=3D 0x11; + diff =3D *mem-- ^ cmp; + + if (!odd) { + goto start_even; + } + + while (1) { + /* Test odd tag. */ + if (unlikely((diff) & 0xf0)) { + break; + } + if (++n =3D=3D count) { + break; + } + + start_even: + /* Test even tag. */ + if (unlikely((diff) & 0x0f)) { + break; + } + if (++n =3D=3D count) { + break; + } + + diff =3D *mem-- ^ cmp; + } + return n; +} + /** * mte_probe_int() - helper for mte_probe and mte_check * @env: CPU environment @@ -1042,6 +1091,56 @@ uint64_t mte_mops_probe(CPUARMState *env, uint64_t p= tr, uint64_t size, } } =20 +uint64_t mte_mops_probe_rev(CPUARMState *env, uint64_t ptr, uint64_t size, + uint32_t desc) +{ + int mmu_idx, tag_count; + uint64_t ptr_tag, tag_first, tag_last; + void *mem; + bool w =3D FIELD_EX32(desc, MTEDESC, WRITE); + uint32_t n; + + mmu_idx =3D FIELD_EX32(desc, MTEDESC, MIDX); + /* True probe; this will never fault */ + mem =3D allocation_tag_mem_probe(env, mmu_idx, ptr, + w ? MMU_DATA_STORE : MMU_DATA_LOAD, + size, MMU_DATA_LOAD, true, 0); + if (!mem) { + return size; + } + + /* + * TODO: checkNrev() is not designed for checks of the size we expect + * for FEAT_MOPS operations, so we should implement this differently. + * Maybe we should do something like + * if (region start and size are aligned nicely) { + * do direct loads of 64 tag bits at a time; + * } else { + * call checkN() + * } + */ + /* Round the bounds to the tag granule, and compute the number of tags= . */ + ptr_tag =3D allocation_tag_from_addr(ptr); + tag_first =3D QEMU_ALIGN_DOWN(ptr - (size - 1), TAG_GRANULE); + tag_last =3D QEMU_ALIGN_DOWN(ptr, TAG_GRANULE); + tag_count =3D ((tag_last - tag_first) / TAG_GRANULE) + 1; + n =3D checkNrev(mem, ptr & TAG_GRANULE, ptr_tag, tag_count); + if (likely(n =3D=3D tag_count)) { + return size; + } + + /* + * Failure; for the first granule, it's at @ptr. Otherwise + * it's at the last byte of the nth granule. Calculate how + * many bytes we can access without hitting that failure. + */ + if (n =3D=3D 0) { + return 0; + } else { + return (n - 1) * TAG_GRANULE + ((ptr + 1) - tag_last); + } +} + void mte_mops_set_tags(CPUARMState *env, uint64_t ptr, uint64_t size, uint32_t desc) { --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695317931; cv=none; d=zohomail.com; s=zohoarc; b=JzQrfsLVaCMjh6fjXDio83q7/29lXRMSW5sF6v+fu8/5qiW8mcXpmqPeNTS+B2Z08nOXN2mxiZrBgmH+k+eYgf6ScrHxyKVpqQMK4CF3oT4Po4lFVykAroyZUaTJvK9T7h0ZOOLww7nggmwIWzKVk7nZqrHTrBEC3ACznZxBjAc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695317931; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bGiNrtJpiQZpVI92N0ql6rcv6ob4bc59+qgz0fMI5Zc=; b=nURbsDwZabGJuXUdUyhsCOK3fVNQslIwAQ9AhZzsxqEivG3zpviw2SWsO5+QCQ9ApL6LdeqqkUk2RRJ8O6XWD4frF/zMJ+Abv9K92s/J+th1xOW2Lge7QfXIY//23KetB933hprEwqXup4Qsvv0/84Xe8DKev5um2iSV/vwzd38= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695317931600512.31806706936; Thu, 21 Sep 2023 10:38:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNcY-00027v-F0; Thu, 21 Sep 2023 13:37:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNcU-00025o-4D for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:42 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcL-0007h0-Q4 for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:40 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-321fa040ae7so764534f8f.1 for ; Thu, 21 Sep 2023 10:37:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317852; x=1695922652; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bGiNrtJpiQZpVI92N0ql6rcv6ob4bc59+qgz0fMI5Zc=; b=Sfr9A5UZ81eMVvIvfAXlBfuJ1uM65Q0RgMrOcHwuW8O11pjk3d8HVZTFaP05sJ8C3u USOOqDQA3bqZge7C9spAnbwcn1DF9plf1SZgKY7YHkNUrW5cYpHqZmUoESsi2BElxzp5 9QHK5lY+fqwEgEJeT2QwxdVh63C9IoD2NBbhTq5J8UP/Ma6pMXJHArJCYaeJybaTDYfF /9UrcSS5PmwRJK0F+MO3ZnhUYfJOjTdcbMIxOMkmjqI9vDBwUxG+Ma9P8euiY5ZfWNe2 z5Z8zreeXhn3FtJK6XO2h11t618e+DY8rQOtSxGIY6u7J0fEPzh2tQnNN79TA/qbAen+ VV+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317852; x=1695922652; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bGiNrtJpiQZpVI92N0ql6rcv6ob4bc59+qgz0fMI5Zc=; b=v2ihRyWmDvqsaTad0FSgypNFa6KmqvXVI0dYd+a33aCOmB58OyqPbvSU+CYNzzbtG4 VW+xb/WNksA3Vcq6k6yVS2rxqrVZ8WV3cBBOoIj84RKZB+qpkB0mr8HsOD5iETFywDI0 DV2P2I40xsoQ7ulYBmW7X4qreSTRuVlHuDEsi0A562lIm05pUS6RjKvhb9z8dVTslf9f AC+huNv8rrqTGLcAqPi6V6gqZdcohe5evHwlL0kXgNwSMzkCYr50NBH60jPtOUi/HLBT KSOH1edRYZ4qmUp2tJRPYUrDNSN9/6d7bU6mza8socvhsbW04unvpO9ne85wUFpvASVS BSpQ== X-Gm-Message-State: AOJu0Yxt2tRN4qPfhuPyUZyLPGKDSLOJhorVdd5BS4DJz5/+DbeUyt/l eeIAtISr3EWGsIBECgvGFgFWJN+9aF6TqpVud/4= X-Google-Smtp-Source: AGHT+IH5DY2TMODkF5jbxk53D0eQopxVCbox9xTHbDGTc8LNAMeQ8aH9zkwC0AxAiZnih3qeHBAghA== X-Received: by 2002:a05:6000:108:b0:320:1c6:628c with SMTP id o8-20020a056000010800b0032001c6628cmr5568687wrx.65.1695317852365; Thu, 21 Sep 2023 10:37:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/30] target/arm: Implement the CPY* instructions Date: Thu, 21 Sep 2023 18:37:11 +0100 Message-Id: <20230921173720.3250581-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695317933498100003 Content-Type: text/plain; charset="utf-8" The FEAT_MOPS CPY* instructions implement memory copies. These come in both "always forwards" (memcpy-style) and "overlap OK" (memmove-style) flavours. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230912140434.1333369-12-peter.maydell@linaro.org --- target/arm/tcg/helper-a64.h | 7 + target/arm/tcg/a64.decode | 14 + target/arm/tcg/helper-a64.c | 454 +++++++++++++++++++++++++++++++++ target/arm/tcg/translate-a64.c | 60 +++++ 4 files changed, 535 insertions(+) diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h index 10a99107124..575a5dab7dc 100644 --- a/target/arm/tcg/helper-a64.h +++ b/target/arm/tcg/helper-a64.h @@ -124,3 +124,10 @@ DEF_HELPER_3(sete, void, env, i32, i32) DEF_HELPER_3(setgp, void, env, i32, i32) DEF_HELPER_3(setgm, void, env, i32, i32) DEF_HELPER_3(setge, void, env, i32, i32) + +DEF_HELPER_4(cpyp, void, env, i32, i32, i32) +DEF_HELPER_4(cpym, void, env, i32, i32, i32) +DEF_HELPER_4(cpye, void, env, i32, i32, i32) +DEF_HELPER_4(cpyfp, void, env, i32, i32, i32) +DEF_HELPER_4(cpyfm, void, env, i32, i32, i32) +DEF_HELPER_4(cpyfe, void, env, i32, i32, i32) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index a202faa17bc..0cf11470741 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -575,3 +575,17 @@ SETE 00 011001110 ..... 10 . . 01 ..... ...= .. @set SETGP 00 011101110 ..... 00 . . 01 ..... ..... @set SETGM 00 011101110 ..... 01 . . 01 ..... ..... @set SETGE 00 011101110 ..... 10 . . 01 ..... ..... @set + +# Memmove/Memcopy: the CPY insns allow overlapping src/dest and +# copy in the correct direction; the CPYF insns always copy forwards. +# +# options has the nontemporal and unpriv bits for src and dest +&cpy rs rn rd options +@cpy .. ... . ..... rs:5 options:4 .. rn:5 rd:5 &cpy + +CPYFP 00 011 0 01000 ..... .... 01 ..... ..... @cpy +CPYFM 00 011 0 01010 ..... .... 01 ..... ..... @cpy +CPYFE 00 011 0 01100 ..... .... 01 ..... ..... @cpy +CPYP 00 011 1 01000 ..... .... 01 ..... ..... @cpy +CPYM 00 011 1 01010 ..... .... 01 ..... ..... @cpy +CPYE 00 011 1 01100 ..... .... 01 ..... ..... @cpy diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 2cf89184d77..84f54750fc2 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -1048,6 +1048,15 @@ static uint64_t page_limit(uint64_t addr) return TARGET_PAGE_ALIGN(addr + 1) - addr; } =20 +/* + * Return the number of bytes we can copy starting from addr and working + * backwards without crossing a page boundary. + */ +static uint64_t page_limit_rev(uint64_t addr) +{ + return (addr & ~TARGET_PAGE_MASK) + 1; +} + /* * Perform part of a memory set on an area of guest memory starting at * toaddr (a dirty address) and extending for setsize bytes. @@ -1392,3 +1401,448 @@ void HELPER(setge)(CPUARMState *env, uint32_t syndr= ome, uint32_t mtedesc) { do_sete(env, syndrome, mtedesc, set_step_tags, true, GETPC()); } + +/* + * Perform part of a memory copy from the guest memory at fromaddr + * and extending for copysize bytes, to the guest memory at + * toaddr. Both addreses are dirty. + * + * Returns the number of bytes actually set, which might be less than + * copysize; the caller should loop until the whole copy has been done. + * The caller should ensure that the guest registers are correct + * for the possibility that the first byte of the copy encounters + * an exception or watchpoint. We guarantee not to take any faults + * for bytes other than the first. + */ +static uint64_t copy_step(CPUARMState *env, uint64_t toaddr, uint64_t from= addr, + uint64_t copysize, int wmemidx, int rmemidx, + uint32_t *wdesc, uint32_t *rdesc, uintptr_t ra) +{ + void *rmem; + void *wmem; + + /* Don't cross a page boundary on either source or destination */ + copysize =3D MIN(copysize, page_limit(toaddr)); + copysize =3D MIN(copysize, page_limit(fromaddr)); + /* + * Handle MTE tag checks: either handle the tag mismatch for byte 0, + * or else copy up to but not including the byte with the mismatch. + */ + if (*rdesc) { + uint64_t mtesize =3D mte_mops_probe(env, fromaddr, copysize, *rdes= c); + if (mtesize =3D=3D 0) { + mte_check_fail(env, *rdesc, fromaddr, ra); + *rdesc =3D 0; + } else { + copysize =3D MIN(copysize, mtesize); + } + } + if (*wdesc) { + uint64_t mtesize =3D mte_mops_probe(env, toaddr, copysize, *wdesc); + if (mtesize =3D=3D 0) { + mte_check_fail(env, *wdesc, toaddr, ra); + *wdesc =3D 0; + } else { + copysize =3D MIN(copysize, mtesize); + } + } + + toaddr =3D useronly_clean_ptr(toaddr); + fromaddr =3D useronly_clean_ptr(fromaddr); + /* Trapless lookup of whether we can get a host memory pointer */ + wmem =3D tlb_vaddr_to_host(env, toaddr, MMU_DATA_STORE, wmemidx); + rmem =3D tlb_vaddr_to_host(env, fromaddr, MMU_DATA_LOAD, rmemidx); + +#ifndef CONFIG_USER_ONLY + /* + * If we don't have host memory for both source and dest then just + * do a single byte copy. This will handle watchpoints, invalid pages, + * etc correctly. For clean code pages, the next iteration will see + * the page dirty and will use the fast path. + */ + if (unlikely(!rmem || !wmem)) { + uint8_t byte; + if (rmem) { + byte =3D *(uint8_t *)rmem; + } else { + byte =3D cpu_ldub_mmuidx_ra(env, fromaddr, rmemidx, ra); + } + if (wmem) { + *(uint8_t *)wmem =3D byte; + } else { + cpu_stb_mmuidx_ra(env, toaddr, byte, wmemidx, ra); + } + return 1; + } +#endif + /* Easy case: just memmove the host memory */ + memmove(wmem, rmem, copysize); + return copysize; +} + +/* + * Do part of a backwards memory copy. Here toaddr and fromaddr point + * to the *last* byte to be copied. + */ +static uint64_t copy_step_rev(CPUARMState *env, uint64_t toaddr, + uint64_t fromaddr, + uint64_t copysize, int wmemidx, int rmemidx, + uint32_t *wdesc, uint32_t *rdesc, uintptr_t = ra) +{ + void *rmem; + void *wmem; + + /* Don't cross a page boundary on either source or destination */ + copysize =3D MIN(copysize, page_limit_rev(toaddr)); + copysize =3D MIN(copysize, page_limit_rev(fromaddr)); + + /* + * Handle MTE tag checks: either handle the tag mismatch for byte 0, + * or else copy up to but not including the byte with the mismatch. + */ + if (*rdesc) { + uint64_t mtesize =3D mte_mops_probe_rev(env, fromaddr, copysize, *= rdesc); + if (mtesize =3D=3D 0) { + mte_check_fail(env, *rdesc, fromaddr, ra); + *rdesc =3D 0; + } else { + copysize =3D MIN(copysize, mtesize); + } + } + if (*wdesc) { + uint64_t mtesize =3D mte_mops_probe_rev(env, toaddr, copysize, *wd= esc); + if (mtesize =3D=3D 0) { + mte_check_fail(env, *wdesc, toaddr, ra); + *wdesc =3D 0; + } else { + copysize =3D MIN(copysize, mtesize); + } + } + + toaddr =3D useronly_clean_ptr(toaddr); + fromaddr =3D useronly_clean_ptr(fromaddr); + /* Trapless lookup of whether we can get a host memory pointer */ + wmem =3D tlb_vaddr_to_host(env, toaddr, MMU_DATA_STORE, wmemidx); + rmem =3D tlb_vaddr_to_host(env, fromaddr, MMU_DATA_LOAD, rmemidx); + +#ifndef CONFIG_USER_ONLY + /* + * If we don't have host memory for both source and dest then just + * do a single byte copy. This will handle watchpoints, invalid pages, + * etc correctly. For clean code pages, the next iteration will see + * the page dirty and will use the fast path. + */ + if (unlikely(!rmem || !wmem)) { + uint8_t byte; + if (rmem) { + byte =3D *(uint8_t *)rmem; + } else { + byte =3D cpu_ldub_mmuidx_ra(env, fromaddr, rmemidx, ra); + } + if (wmem) { + *(uint8_t *)wmem =3D byte; + } else { + cpu_stb_mmuidx_ra(env, toaddr, byte, wmemidx, ra); + } + return 1; + } +#endif + /* + * Easy case: just memmove the host memory. Note that wmem and + * rmem here point to the *last* byte to copy. + */ + memmove(wmem - (copysize - 1), rmem - (copysize - 1), copysize); + return copysize; +} + +/* + * for the Memory Copy operation, our implementation chooses always + * to use "option A", where we update Xd and Xs to the final addresses + * in the CPYP insn, and then in CPYM and CPYE only need to update Xn. + * + * @env: CPU + * @syndrome: syndrome value for mismatch exceptions + * (also contains the register numbers we need to use) + * @wdesc: MTE descriptor for the writes (destination) + * @rdesc: MTE descriptor for the reads (source) + * @move: true if this is CPY (memmove), false for CPYF (memcpy forwards) + */ +static void do_cpyp(CPUARMState *env, uint32_t syndrome, uint32_t wdesc, + uint32_t rdesc, uint32_t move, uintptr_t ra) +{ + int rd =3D mops_destreg(syndrome); + int rs =3D mops_srcreg(syndrome); + int rn =3D mops_sizereg(syndrome); + uint32_t rmemidx =3D FIELD_EX32(rdesc, MTEDESC, MIDX); + uint32_t wmemidx =3D FIELD_EX32(wdesc, MTEDESC, MIDX); + bool forwards =3D true; + uint64_t toaddr =3D env->xregs[rd]; + uint64_t fromaddr =3D env->xregs[rs]; + uint64_t copysize =3D env->xregs[rn]; + uint64_t stagecopysize, step; + + check_mops_enabled(env, ra); + + + if (move) { + /* + * Copy backwards if necessary. The direction for a non-overlapping + * copy is IMPDEF; we choose forwards. + */ + if (copysize > 0x007FFFFFFFFFFFFFULL) { + copysize =3D 0x007FFFFFFFFFFFFFULL; + } + uint64_t fs =3D extract64(fromaddr, 0, 56); + uint64_t ts =3D extract64(toaddr, 0, 56); + uint64_t fe =3D extract64(fromaddr + copysize, 0, 56); + + if (fs < ts && fe > ts) { + forwards =3D false; + } + } else { + if (copysize > INT64_MAX) { + copysize =3D INT64_MAX; + } + } + + if (!mte_checks_needed(fromaddr, rdesc)) { + rdesc =3D 0; + } + if (!mte_checks_needed(toaddr, wdesc)) { + wdesc =3D 0; + } + + if (forwards) { + stagecopysize =3D MIN(copysize, page_limit(toaddr)); + stagecopysize =3D MIN(stagecopysize, page_limit(fromaddr)); + while (stagecopysize) { + env->xregs[rd] =3D toaddr; + env->xregs[rs] =3D fromaddr; + env->xregs[rn] =3D copysize; + step =3D copy_step(env, toaddr, fromaddr, stagecopysize, + wmemidx, rmemidx, &wdesc, &rdesc, ra); + toaddr +=3D step; + fromaddr +=3D step; + copysize -=3D step; + stagecopysize -=3D step; + } + /* Insn completed, so update registers to the Option A format */ + env->xregs[rd] =3D toaddr + copysize; + env->xregs[rs] =3D fromaddr + copysize; + env->xregs[rn] =3D -copysize; + } else { + /* + * In a reverse copy the to and from addrs in Xs and Xd are the st= art + * of the range, but it's more convenient for us to work with poin= ters + * to the last byte being copied. + */ + toaddr +=3D copysize - 1; + fromaddr +=3D copysize - 1; + stagecopysize =3D MIN(copysize, page_limit_rev(toaddr)); + stagecopysize =3D MIN(stagecopysize, page_limit_rev(fromaddr)); + while (stagecopysize) { + env->xregs[rn] =3D copysize; + step =3D copy_step_rev(env, toaddr, fromaddr, stagecopysize, + wmemidx, rmemidx, &wdesc, &rdesc, ra); + copysize -=3D step; + stagecopysize -=3D step; + toaddr -=3D step; + fromaddr -=3D step; + } + /* + * Insn completed, so update registers to the Option A format. + * For a reverse copy this is no different to the CPYP input forma= t. + */ + env->xregs[rn] =3D copysize; + } + + /* Set NZCV =3D 0000 to indicate we are an Option A implementation */ + env->NF =3D 0; + env->ZF =3D 1; /* our env->ZF encoding is inverted */ + env->CF =3D 0; + env->VF =3D 0; + return; +} + +void HELPER(cpyp)(CPUARMState *env, uint32_t syndrome, uint32_t wdesc, + uint32_t rdesc) +{ + do_cpyp(env, syndrome, wdesc, rdesc, true, GETPC()); +} + +void HELPER(cpyfp)(CPUARMState *env, uint32_t syndrome, uint32_t wdesc, + uint32_t rdesc) +{ + do_cpyp(env, syndrome, wdesc, rdesc, false, GETPC()); +} + +static void do_cpym(CPUARMState *env, uint32_t syndrome, uint32_t wdesc, + uint32_t rdesc, uint32_t move, uintptr_t ra) +{ + /* Main: we choose to copy until less than a page remaining */ + CPUState *cs =3D env_cpu(env); + int rd =3D mops_destreg(syndrome); + int rs =3D mops_srcreg(syndrome); + int rn =3D mops_sizereg(syndrome); + uint32_t rmemidx =3D FIELD_EX32(rdesc, MTEDESC, MIDX); + uint32_t wmemidx =3D FIELD_EX32(wdesc, MTEDESC, MIDX); + bool forwards =3D true; + uint64_t toaddr, fromaddr, copysize, step; + + check_mops_enabled(env, ra); + + /* We choose to NOP out "no data to copy" before consistency checks */ + if (env->xregs[rn] =3D=3D 0) { + return; + } + + check_mops_wrong_option(env, syndrome, ra); + + if (move) { + forwards =3D (int64_t)env->xregs[rn] < 0; + } + + if (forwards) { + toaddr =3D env->xregs[rd] + env->xregs[rn]; + fromaddr =3D env->xregs[rs] + env->xregs[rn]; + copysize =3D -env->xregs[rn]; + } else { + copysize =3D env->xregs[rn]; + /* This toaddr and fromaddr point to the *last* byte to copy */ + toaddr =3D env->xregs[rd] + copysize - 1; + fromaddr =3D env->xregs[rs] + copysize - 1; + } + + if (!mte_checks_needed(fromaddr, rdesc)) { + rdesc =3D 0; + } + if (!mte_checks_needed(toaddr, wdesc)) { + wdesc =3D 0; + } + + /* Our implementation has no particular parameter requirements for CPY= M */ + + /* Do the actual memmove */ + if (forwards) { + while (copysize >=3D TARGET_PAGE_SIZE) { + step =3D copy_step(env, toaddr, fromaddr, copysize, + wmemidx, rmemidx, &wdesc, &rdesc, ra); + toaddr +=3D step; + fromaddr +=3D step; + copysize -=3D step; + env->xregs[rn] =3D -copysize; + if (copysize >=3D TARGET_PAGE_SIZE && + unlikely(cpu_loop_exit_requested(cs))) { + cpu_loop_exit_restore(cs, ra); + } + } + } else { + while (copysize >=3D TARGET_PAGE_SIZE) { + step =3D copy_step_rev(env, toaddr, fromaddr, copysize, + wmemidx, rmemidx, &wdesc, &rdesc, ra); + toaddr -=3D step; + fromaddr -=3D step; + copysize -=3D step; + env->xregs[rn] =3D copysize; + if (copysize >=3D TARGET_PAGE_SIZE && + unlikely(cpu_loop_exit_requested(cs))) { + cpu_loop_exit_restore(cs, ra); + } + } + } +} + +void HELPER(cpym)(CPUARMState *env, uint32_t syndrome, uint32_t wdesc, + uint32_t rdesc) +{ + do_cpym(env, syndrome, wdesc, rdesc, true, GETPC()); +} + +void HELPER(cpyfm)(CPUARMState *env, uint32_t syndrome, uint32_t wdesc, + uint32_t rdesc) +{ + do_cpym(env, syndrome, wdesc, rdesc, false, GETPC()); +} + +static void do_cpye(CPUARMState *env, uint32_t syndrome, uint32_t wdesc, + uint32_t rdesc, uint32_t move, uintptr_t ra) +{ + /* Epilogue: do the last partial page */ + int rd =3D mops_destreg(syndrome); + int rs =3D mops_srcreg(syndrome); + int rn =3D mops_sizereg(syndrome); + uint32_t rmemidx =3D FIELD_EX32(rdesc, MTEDESC, MIDX); + uint32_t wmemidx =3D FIELD_EX32(wdesc, MTEDESC, MIDX); + bool forwards =3D true; + uint64_t toaddr, fromaddr, copysize, step; + + check_mops_enabled(env, ra); + + /* We choose to NOP out "no data to copy" before consistency checks */ + if (env->xregs[rn] =3D=3D 0) { + return; + } + + check_mops_wrong_option(env, syndrome, ra); + + if (move) { + forwards =3D (int64_t)env->xregs[rn] < 0; + } + + if (forwards) { + toaddr =3D env->xregs[rd] + env->xregs[rn]; + fromaddr =3D env->xregs[rs] + env->xregs[rn]; + copysize =3D -env->xregs[rn]; + } else { + copysize =3D env->xregs[rn]; + /* This toaddr and fromaddr point to the *last* byte to copy */ + toaddr =3D env->xregs[rd] + copysize - 1; + fromaddr =3D env->xregs[rs] + copysize - 1; + } + + if (!mte_checks_needed(fromaddr, rdesc)) { + rdesc =3D 0; + } + if (!mte_checks_needed(toaddr, wdesc)) { + wdesc =3D 0; + } + + /* Check the size; we don't want to have do a check-for-interrupts */ + if (copysize >=3D TARGET_PAGE_SIZE) { + raise_exception_ra(env, EXCP_UDEF, syndrome, + mops_mismatch_exception_target_el(env), ra); + } + + /* Do the actual memmove */ + if (forwards) { + while (copysize > 0) { + step =3D copy_step(env, toaddr, fromaddr, copysize, + wmemidx, rmemidx, &wdesc, &rdesc, ra); + toaddr +=3D step; + fromaddr +=3D step; + copysize -=3D step; + env->xregs[rn] =3D -copysize; + } + } else { + while (copysize > 0) { + step =3D copy_step_rev(env, toaddr, fromaddr, copysize, + wmemidx, rmemidx, &wdesc, &rdesc, ra); + toaddr -=3D step; + fromaddr -=3D step; + copysize -=3D step; + env->xregs[rn] =3D copysize; + } + } +} + +void HELPER(cpye)(CPUARMState *env, uint32_t syndrome, uint32_t wdesc, + uint32_t rdesc) +{ + do_cpye(env, syndrome, wdesc, rdesc, true, GETPC()); +} + +void HELPER(cpyfe)(CPUARMState *env, uint32_t syndrome, uint32_t wdesc, + uint32_t rdesc) +{ + do_cpye(env, syndrome, wdesc, rdesc, false, GETPC()); +} diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 27bb3039b4d..97f25b4451c 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4019,6 +4019,66 @@ TRANS_FEAT(SETGP, aa64_mops, do_SET, a, false, true,= gen_helper_setgp) TRANS_FEAT(SETGM, aa64_mops, do_SET, a, false, true, gen_helper_setgm) TRANS_FEAT(SETGE, aa64_mops, do_SET, a, true, true, gen_helper_setge) =20 +typedef void CpyFn(TCGv_env, TCGv_i32, TCGv_i32, TCGv_i32); + +static bool do_CPY(DisasContext *s, arg_cpy *a, bool is_epilogue, CpyFn fn) +{ + int rmemidx, wmemidx; + uint32_t syndrome, rdesc =3D 0, wdesc =3D 0; + bool wunpriv =3D extract32(a->options, 0, 1); + bool runpriv =3D extract32(a->options, 1, 1); + + /* + * UNPREDICTABLE cases: we choose to UNDEF, which allows + * us to pull this check before the CheckMOPSEnabled() test + * (which we do in the helper function) + */ + if (a->rs =3D=3D a->rn || a->rs =3D=3D a->rd || a->rn =3D=3D a->rd || + a->rd =3D=3D 31 || a->rs =3D=3D 31 || a->rn =3D=3D 31) { + return false; + } + + rmemidx =3D get_a64_user_mem_index(s, runpriv); + wmemidx =3D get_a64_user_mem_index(s, wunpriv); + + /* + * We pass option_a =3D=3D true, matching our implementation; + * we pass wrong_option =3D=3D false: helper function may set that bit. + */ + syndrome =3D syn_mop(false, false, a->options, is_epilogue, + false, true, a->rd, a->rs, a->rn); + + /* If we need to do MTE tag checking, assemble the descriptors */ + if (s->mte_active[runpriv]) { + rdesc =3D FIELD_DP32(rdesc, MTEDESC, TBI, s->tbid); + rdesc =3D FIELD_DP32(rdesc, MTEDESC, TCMA, s->tcma); + } + if (s->mte_active[wunpriv]) { + wdesc =3D FIELD_DP32(wdesc, MTEDESC, TBI, s->tbid); + wdesc =3D FIELD_DP32(wdesc, MTEDESC, TCMA, s->tcma); + wdesc =3D FIELD_DP32(wdesc, MTEDESC, WRITE, true); + } + /* The helper function needs these parts of the descriptor regardless = */ + rdesc =3D FIELD_DP32(rdesc, MTEDESC, MIDX, rmemidx); + wdesc =3D FIELD_DP32(wdesc, MTEDESC, MIDX, wmemidx); + + /* + * The helper needs the register numbers, but since they're in + * the syndrome anyway, we let it extract them from there rather + * than passing in an extra three integer arguments. + */ + fn(cpu_env, tcg_constant_i32(syndrome), tcg_constant_i32(wdesc), + tcg_constant_i32(rdesc)); + return true; +} + +TRANS_FEAT(CPYP, aa64_mops, do_CPY, a, false, gen_helper_cpyp) +TRANS_FEAT(CPYM, aa64_mops, do_CPY, a, false, gen_helper_cpym) +TRANS_FEAT(CPYE, aa64_mops, do_CPY, a, true, gen_helper_cpye) +TRANS_FEAT(CPYFP, aa64_mops, do_CPY, a, false, gen_helper_cpyfp) +TRANS_FEAT(CPYFM, aa64_mops, do_CPY, a, false, gen_helper_cpyfm) +TRANS_FEAT(CPYFE, aa64_mops, do_CPY, a, true, gen_helper_cpyfe) + typedef void ArithTwoOp(TCGv_i64, TCGv_i64, TCGv_i64); =20 static bool gen_rri(DisasContext *s, arg_rri_sf *a, --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695318029; cv=none; d=zohomail.com; s=zohoarc; b=hIPlVS0xD9VfW0p84hgwBceV7SqLS8ffI5MSULX03YrLVEVL2CIgbskhq/l6yKTigOeuImsNtEqcY/3gbyx8CkCZjhwAQ+026oijHFKsLmT60+Aj6q0zK5LdTpoK19hQcPToXoZjSaOGuVinF8apBrUivDPCEwL7mLWzvtEIkrM= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317853; x=1695922653; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TtwEtjp3KEwvsq3yjTwyNthKzsgdN8hPlxUQdpQeNjE=; b=eAu+IgiD1noTz2kplEgJ8yU76gQdYv0erYX4qHnS75Y1RkK8kOVYkr0BYvbDlw1bdD 5a0T/lIAGriWQbV2k2Ljtwur+T/ZxOiiPOpgLJSvkar/aQxNbFP23uMU8LzqKyW/2Q+Q iuJYhkwVU3PmmDnEiycrpvpG6fMEd759er03kp3FD/roSWsM9JHbsYYi5WoFbccUzQWm xt/BUj0aZrkqrVNr8U1aUiw04CWrnM0GkC4L+TT7wRqeRV4HBLIM4PSRA410t58/mcV3 QHcCl2lJ+KqoMFV54qV3lq1EoM2XUqN3crfT6K/9uDpytzv8x5T19smeEDCFnQpiLUDL M8wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317853; x=1695922653; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TtwEtjp3KEwvsq3yjTwyNthKzsgdN8hPlxUQdpQeNjE=; b=BtrBmeIe2QJowqepepd6WqBiu18Grio13YKQDEUCTPE7p6DIVNMMXxAGKMFxt5sdrx j8SqNx094Mg3B8A8i9iNnBMC8lf42BleRdkX6dBjfPQdbRLNhEkiEwy7JJ2lxM1v+ex3 +DROk1Egyo3Q4fFu2Dx3rSP5uZfMVm1ScxlNY/VYkl1OLHSKqQjRFyHEsi22i3VthuLa kMzXaTbcl1MOSP7230y0eUzoJVPuw4vKoLUceHPWZM/KU7/ZWa9nyKIBQBtS0/uxKw45 6z0bMSObn+/a291/Zd6Z6n+QNK4vJZ9sYD835ISzE5t1dsV1/NU+XDzNQxq+b+p+dIFW cVTQ== X-Gm-Message-State: AOJu0YzCxg1Jnl4BLiEedrhnhQkjhVdzWDwHdvSI6EpTsW4Am74SEKfc D2g/lM75Z+aPG8JBND2B7psSNI4OP4piAe/0F7U= X-Google-Smtp-Source: AGHT+IFJRHtqYdMWxwYv/28J8JBmygD098slB/M1IIopr+daLnPEOL7+EhPk4I9umWod/185RNw+CA== X-Received: by 2002:a7b:c415:0:b0:3fe:22a9:910 with SMTP id k21-20020a7bc415000000b003fe22a90910mr5846737wmi.14.1695317852751; Thu, 21 Sep 2023 10:37:32 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/30] target/arm: Enable FEAT_MOPS for CPU 'max' Date: Thu, 21 Sep 2023 18:37:12 +0100 Message-Id: <20230921173720.3250581-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318031825100003 Content-Type: text/plain; charset="utf-8" Enable FEAT_MOPS on the AArch64 'max' CPU, and add it to the list of features we implement. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230912140434.1333369-13-peter.maydell@linaro.org --- docs/system/arm/emulation.rst | 1 + linux-user/elfload.c | 1 + target/arm/tcg/cpu64.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 1fb6a2e8c3e..965cbf84c51 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -58,6 +58,7 @@ the following architecture extensions: - FEAT_LSE (Large System Extensions) - FEAT_LSE2 (Large System Extensions v2) - FEAT_LVA (Large Virtual Address space) +- FEAT_MOPS (Standardization of memory operations) - FEAT_MTE (Memory Tagging Extension) - FEAT_MTE2 (Memory Tagging Extension) - FEAT_MTE3 (MTE Asymmetric Fault Handling) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 203a2b790d5..db75cd4b33f 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -816,6 +816,7 @@ uint32_t get_elf_hwcap2(void) GET_FEATURE_ID(aa64_sme_i16i64, ARM_HWCAP2_A64_SME_I16I64); GET_FEATURE_ID(aa64_sme_fa64, ARM_HWCAP2_A64_SME_FA64); GET_FEATURE_ID(aa64_hbc, ARM_HWCAP2_A64_HBC); + GET_FEATURE_ID(aa64_mops, ARM_HWCAP2_A64_MOPS); =20 return hwcaps; } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 57abaea00cd..68928e51272 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1028,6 +1028,7 @@ void aarch64_max_tcg_initfn(Object *obj) cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64isar2; + t =3D FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */ t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ cpu->isar.id_aa64isar2 =3D t; =20 --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695318146; cv=none; d=zohomail.com; s=zohoarc; b=ZoD+r1xVkgx5WxmEb1PFtu4GRHTPqOpRdeLH5UtRREFopMVi2lTv828JVn0ONrGT9gaZY0HUCg4I7t2zZrRP1l9QDfNEGa6KvLVViLpNHZ5LQZeV+nACkyyptzUzk0f70CkYcCraMyjqtIhSyrEM0+haQoKCyehZytpDkSslxfA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695318146; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YmquttdWOUZO2zoSRHgCppwJQPOrmr0UTW6yGeHagaU=; b=hEq7bu8Rj24T7ycpkdzBIwKlM0cNmqd1cFw19ZJuSIvohG5F3bfB6CfvNJ1IhwgkKFS4Ks+ej5PFrOLolNG0D4ZfQoACK8H3I5FkVsJsKIcg1/61t3K99yc2DAg1yTi48QM8BTh5I5gD/uHgBBH64/cDcQIugjrNAuAsnFoDJD8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695318146506231.1055268281467; Thu, 21 Sep 2023 10:42:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNcW-000273-Pv; Thu, 21 Sep 2023 13:37:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNcV-00026j-Dv for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:43 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcN-0007hW-0I for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:43 -0400 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-403004a96eeso12870165e9.3 for ; Thu, 21 Sep 2023 10:37:34 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317853; x=1695922653; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=YmquttdWOUZO2zoSRHgCppwJQPOrmr0UTW6yGeHagaU=; b=BI676u0MTqHGLRDopJUbL8wadSPpaoKQeCR4w4jVyXG781MkEn059Y8tWtSI6/9aAR SG3RZww7nrfGymxZd1hJl30m+EtfFrn1VOAck21j/+LaX3cqmqnQgcRQ3HWFUamoqIrU p1o7ZeAmz6YOCa8v10oCa3rAZ1tp20zpUnCalrv/8bXX8a0SQGSb0eYJIAhLhZrRrw/5 0kiaRKd7lzbg6nOTeoUiCsUAgAYbjVqsWbgmyHLPo/YGJLKZnJkpnhSSctjXqvM3hD8b R2opYa9WNVR+aX7Pc9NUXVv4jjTTvMiTKdlQ85zV3ceBKCe5Yx6zmD7QqO7RuO6qd1d2 o/qA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317853; x=1695922653; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YmquttdWOUZO2zoSRHgCppwJQPOrmr0UTW6yGeHagaU=; b=K5qE90HZTxCJ3T5I11b564dmY5B2ZxRy1A62WC7bEP5V2bfsc6y4sAeLJbDaNU+cg7 bGe+dej28vf/uugLJzmJQ2+IKDwh3xJqXa4fScdv9OEoIvM9GEn5iq5I82D5y/8fw2Dl u9Dsbp8BkaRL7Mx1/k/qV2t/OUb0crwORo39Bb9UxkOYbZ0mFrfQKdtKeH5b/duTMeVI wplJEMSXFsFXectSbgHnFG7dRa5ZnrQcDq4l+egwDmEntJobjM0OpVlyNxWWr4XZyWr0 gi73mO7uifqxL4B86m/gC3dn/X8Owep4mtw2IpuGtYjEWiiZwa3ar5d2RwjldaevAuA9 csiQ== X-Gm-Message-State: AOJu0Yzy59ADmS9NiCezt54D1bUjzVgkEwiAXcWmxSyMVPiOgZDVlGe7 AqBrkoMTM/tJiNqJ85ho60nKnpvMMg7e4xeZrTo= X-Google-Smtp-Source: AGHT+IHRdIMgjJ08pWCuUzRUHO+oBaUMHgBDO+5UnEoEsTS3jqRoshDGVbli5BNmczPfaJvuJN9sTg== X-Received: by 2002:a05:600c:a381:b0:3fb:a0fc:1ba1 with SMTP id hn1-20020a05600ca38100b003fba0fc1ba1mr5546340wmb.35.1695317853192; Thu, 21 Sep 2023 10:37:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/30] audio/jackaudio: Avoid dynamic stack allocation in qjack_client_init Date: Thu, 21 Sep 2023 18:37:13 +0100 Message-Id: <20230921173720.3250581-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318147775100001 Avoid a dynamic stack allocation in qjack_client_init(), by using a g_autofree heap allocation instead. (We stick with allocate + snprintf() because the JACK API requires the name to be no more than its maximum size, so g_strdup_printf() would require an extra truncation step.) The codebase has very few VLAs, and if we can get rid of them all we can make the compiler error on new additions. This is a defensive measure against security bugs where an on-stack dynamic allocation isn't correctly size-checked (e.g. CVE-2021-3527). Signed-off-by: Peter Maydell Reviewed-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Francisco Iglesias Reviewed-by: Christian Schoenebeck Message-id: 20230818155846.1651287-2-peter.maydell@linaro.org --- audio/jackaudio.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/audio/jackaudio.c b/audio/jackaudio.c index 5bdf3d7a78d..7cb2a49f971 100644 --- a/audio/jackaudio.c +++ b/audio/jackaudio.c @@ -400,7 +400,8 @@ static void qjack_client_connect_ports(QJackClient *c) static int qjack_client_init(QJackClient *c) { jack_status_t status; - char client_name[jack_client_name_size()]; + int client_name_len =3D jack_client_name_size(); /* includes NUL */ + g_autofree char *client_name =3D g_new(char, client_name_len); jack_options_t options =3D JackNullOption; =20 if (c->state =3D=3D QJACK_STATE_RUNNING) { @@ -409,7 +410,7 @@ static int qjack_client_init(QJackClient *c) =20 c->connect_ports =3D true; =20 - snprintf(client_name, sizeof(client_name), "%s-%s", + snprintf(client_name, client_name_len, "%s-%s", c->out ? "out" : "in", c->opt->client_name ? c->opt->client_name : audio_application_name= ()); =20 --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695318038; cv=none; d=zohomail.com; s=zohoarc; b=cA9fo0M0HxmhM+jJ4RuAdbeel1tMmOEiiwiqYdfx/qROoOdoB/RkPyfbvLXR4K1vU/4Sjl8Et7l4pwnCP2jfuxrYBIgH2pLFkW2gscwFy14u+xhcQSlcWFe17Fi194Y8xGhON0E57X1TYshOSmEgkzuL5yjoISRQWthIWWAOD2U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695318038; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TcYlraAFAOOQRcPGC3TvQT/INQls2RJxIkH/pggGmhw=; b=DuNaKGu5n/OJZ2pRVlpcWKuEPerCd9Lrj6fRl8CZqMEqUXCJcoFmBRIQlfSdPM9MsLaZjWdfqUZXenRUnjdO6G1zzelUriG1mvtBJ/aBKznyE5VX/1YuTbO+RKSK23pZAqjMgVwEnPmtNdxHbx5k1LNDPLBhOOOeYdUZ+9YO66o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695318038943941.1854439349213; Thu, 21 Sep 2023 10:40:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNcb-0002A7-8e; Thu, 21 Sep 2023 13:37:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNcY-00028K-Lt for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:46 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcO-0007hi-Vo for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:46 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-404fbfac998so14385095e9.3 for ; Thu, 21 Sep 2023 10:37:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317853; x=1695922653; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=TcYlraAFAOOQRcPGC3TvQT/INQls2RJxIkH/pggGmhw=; b=pQx5C5rDXJIkYEL9Fxor9YnSPw5MMZ6NAsjeErWduNTK+JC5RAAsusxHRzPcp7UMfR c66mZdcCHHFsN0XAm8l1b5AkRqi1HQSuwOsJ+VN+vlF3O6k5MgA+ZhRahEbt2oxfj74T LC3w12r+NEWCInaynhjsvwIstK4WeV383VigCROLiXiM6KMvM6SGQRrXrFR0wQQKNwnw l7Jhznvyd9UDSTZY2sSA52hbPnyK64/lh4cMME/DJq4LdEy8m+OUkdvkuJOqvnlOxdp9 SmIPikofrLQmeyNrTYtNP3RsmCQn58JxacV5Ommr6+jHkaCUEPcQMXIolRX8ukMfYBcl j5aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317853; x=1695922653; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TcYlraAFAOOQRcPGC3TvQT/INQls2RJxIkH/pggGmhw=; b=p++6rodwqHk4g8hTGZzuXaejY42wcBxYCrzuMqZbKN1NFxF4H6z8/EV9+yzzNnIovK aew/FCTzQ/H3wersQo1MoftDSMyKqnpwZnTIuvZCNB8I5i4Wk3UT54LsC5x/N/vr81y/ P7/g/So04gtJLXbp0985h5P5nHhVjzzo5uuVjF/S7vAPmK+f3CyM2vzfPCi+l0tCFDXb TDy7tGGjO73fPHA7bUsgHMFi0uHjI/cKuVnDWZYHtzZ2lLncF4gkcHI0sdTvAZPk/Iz6 v4E05E1jfDZxkI2x2vJxsl+6LHgnfd1MO9wtnkcz+3ljECn84AiberhANNZ/271y103w el8w== X-Gm-Message-State: AOJu0YzYu6enalqeds2JeRd9f6MoHMI/FIcYxp2xAE4/mG+ZQRNZO/GK QgLdCU8plUTUqHeBUVMHM5gSeeqVCunr+U+o/LM= X-Google-Smtp-Source: AGHT+IEmhWQvU1jpiNMnyyKFUa+gFvsWa8XAcg+MViTVf78LdBGvAVaA0NdQVEqajsKs3Y+2pBDxFQ== X-Received: by 2002:a1c:4b0e:0:b0:402:ea83:45cf with SMTP id y14-20020a1c4b0e000000b00402ea8345cfmr6069426wma.2.1695317853590; Thu, 21 Sep 2023 10:37:33 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/30] audio/jackaudio: Avoid dynamic stack allocation in qjack_process() Date: Thu, 21 Sep 2023 18:37:14 +0100 Message-Id: <20230921173720.3250581-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318040101100003 Avoid a dynamic stack allocation in qjack_process(). Since this function is a JACK process callback, we are not permitted to malloc() here, so we allocate a working buffer in qjack_client_init() instead. The codebase has very few VLAs, and if we can get rid of them all we can make the compiler error on new additions. This is a defensive measure against security bugs where an on-stack dynamic allocation isn't correctly size-checked (e.g. CVE-2021-3527). Signed-off-by: Peter Maydell Reviewed-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Francisco Iglesias Reviewed-by: Christian Schoenebeck Message-id: 20230818155846.1651287-3-peter.maydell@linaro.org --- audio/jackaudio.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/audio/jackaudio.c b/audio/jackaudio.c index 7cb2a49f971..e1eaa3477dc 100644 --- a/audio/jackaudio.c +++ b/audio/jackaudio.c @@ -70,6 +70,9 @@ typedef struct QJackClient { int buffersize; jack_port_t **port; QJackBuffer fifo; + + /* Used as workspace by qjack_process() */ + float **process_buffers; } QJackClient; =20 @@ -267,22 +270,21 @@ static int qjack_process(jack_nframes_t nframes, void= *arg) } =20 /* get the buffers for the ports */ - float *buffers[c->nchannels]; for (int i =3D 0; i < c->nchannels; ++i) { - buffers[i] =3D jack_port_get_buffer(c->port[i], nframes); + c->process_buffers[i] =3D jack_port_get_buffer(c->port[i], nframes= ); } =20 if (c->out) { if (likely(c->enabled)) { - qjack_buffer_read_l(&c->fifo, buffers, nframes); + qjack_buffer_read_l(&c->fifo, c->process_buffers, nframes); } else { for (int i =3D 0; i < c->nchannels; ++i) { - memset(buffers[i], 0, nframes * sizeof(float)); + memset(c->process_buffers[i], 0, nframes * sizeof(float)); } } } else { if (likely(c->enabled)) { - qjack_buffer_write_l(&c->fifo, buffers, nframes); + qjack_buffer_write_l(&c->fifo, c->process_buffers, nframes); } } =20 @@ -448,6 +450,9 @@ static int qjack_client_init(QJackClient *c) jack_get_client_name(c->client)); } =20 + /* Allocate working buffer for process callback */ + c->process_buffers =3D g_new(float *, c->nchannels); + jack_set_process_callback(c->client, qjack_process , c); jack_set_port_registration_callback(c->client, qjack_port_registration= , c); jack_set_xrun_callback(c->client, qjack_xrun, c); @@ -579,6 +584,7 @@ static void qjack_client_fini_locked(QJackClient *c) =20 qjack_buffer_free(&c->fifo); g_free(c->port); + g_free(c->process_buffers); =20 c->state =3D QJACK_STATE_DISCONNECTED; /* fallthrough */ --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695318120; cv=none; d=zohomail.com; s=zohoarc; b=BMeEuJtlbw04ZQlb9fV9pTMgFBn9mYVet1/23lqdcDjfWJDt6PN1O73iyNUtdhO0Sv3BtGUbb+D0BoiOcF1NdYFq9EQlHWdgjPu0xPPVN6GuohnSSvZfKLDP5dCFGJOBmuc4EtaRNMUSbMOTX2rIgqRRMxV7YzaUnL0jEmLhfn0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695318120; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+K0O4G1OJUoEa5KBlRvuRwUc3XEOy61zeM7fZ8Tl0gw=; b=jYncmP07wywa/vcMf6akYesm61KRRnAEs9sIlnM3hW13MoVZhLq1qiCg1BTQ/Xpt3oqTrQWG8pVClXo1+tY8nbk354eCFrjDKOOcH612kcPUs1I4eZ3ZYxh1/I7caLwxe0s0Qa+8O8U6bsbx3tBf4ofHZOIK5OQNLBI2YfYpEyo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695318120758925.5789630964852; Thu, 21 Sep 2023 10:42:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNcd-0002Bu-Ja; Thu, 21 Sep 2023 13:37:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNca-00029z-OV for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:48 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcP-0007i8-Bk for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:48 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-40413ccdd4cso16425935e9.0 for ; Thu, 21 Sep 2023 10:37:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317854; x=1695922654; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+K0O4G1OJUoEa5KBlRvuRwUc3XEOy61zeM7fZ8Tl0gw=; b=GkTWZXUhg2HwHlCUYWhRoLIjT3IWhehXtgFngPbqs4IIbk68oqTQ1Noz6SERClOIyO qa09AesR7Y11YiRz/4DWnkZ06Vzl0ZOzZWPUiXorJcRcaRVxxrb3fHH5LeJZsacgHb78 w9yjcQ+qkVmuQ8k5JA3nW/3rL1B7ZXE3+rjxNEkZ63kmdxoRmZIbYTv1tgjIIuYdsSKM phVxDtMucNJGikWpmmlrW4y/voAY71EEvlURyVl96FOewyt5M/lYagjqIt3csv4bgz29 APIq5J2IN/3N2CovGcCsVk2CTFWCMfL72bOGrd5O3Gd5uty/oEoWGqEwPIVC/ZTybBvV axcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317854; x=1695922654; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+K0O4G1OJUoEa5KBlRvuRwUc3XEOy61zeM7fZ8Tl0gw=; b=M3bp7sp2Tk3y6ZKuz0jZrU6a0DWKqElKPku3yLs/IyKIAUsP7vFesJDIjV874dCN/e x1bkbHVKrQ7fi/6i7s4Q1nEEJDTEHs884PZcMSvCGSkYa/z1fT01N8MunYV1h/fGxC3g 6SEJ1dY/AbAvmHCkkwtG3knqL15yWSTYoIrqVIsHf4acuScsJ3MgfG1TfXnddtoLhYb/ BCTLx4cf7Wc+/oJsZFG4J8mh6MD1kia/w64dY6OTa5vFyScaW8duaY6qeiEl3UnOqhDI QjRw/9/an5oq+EU/wKrcZirnYt+34l+MgsM5w01Q3P7vD5SCmKnD6yqHYijrG42N0TGU w83A== X-Gm-Message-State: AOJu0Yytts4SpTCMSxPCofgX4YEndmDKyFX8MdQ060eJ+HwRYrmdOSGu kQdXQdcrMlU2DziS2hYHtpioqeFXdg7t7K+X3D4= X-Google-Smtp-Source: AGHT+IHQj38NN7Gl0dVyS1EwXryJFDdQtfvQdhMn+mIA+2uINbPS1NCqLvFgIRyMHmWhevA3oXniQQ== X-Received: by 2002:a05:600c:8608:b0:400:140c:6083 with SMTP id ha8-20020a05600c860800b00400140c6083mr270393wmb.2.1695317854037; Thu, 21 Sep 2023 10:37:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/30] sbsa-ref: add non-secure EL2 virtual timer Date: Thu, 21 Sep 2023 18:37:15 +0100 Message-Id: <20230921173720.3250581-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318122343100023 Content-Type: text/plain; charset="utf-8" From: Marcin Juszkiewicz Armv8.1+ cpus have Virtual Host Extension (VHE) which added non-secure EL2 virtual timer. This change adds it to fullfil Arm BSA (Base System Architecture) requirements. Signed-off-by: Marcin Juszkiewicz Message-id: 20230913140610.214893-2-marcin.juszkiewicz@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index bc89eb48062..3c7dfcd6dc5 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -61,6 +61,7 @@ #define ARCH_TIMER_S_EL1_IRQ 13 #define ARCH_TIMER_NS_EL1_IRQ 14 #define ARCH_TIMER_NS_EL2_IRQ 10 +#define ARCH_TIMER_NS_EL2_VIRT_IRQ 12 =20 enum { SBSA_FLASH, @@ -489,6 +490,7 @@ static void create_gic(SBSAMachineState *sms, MemoryReg= ion *mem) [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ, + [GTIMER_HYPVIRT] =3D ARCH_TIMER_NS_EL2_VIRT_IRQ, }; =20 for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695317978; cv=none; d=zohomail.com; s=zohoarc; b=Fo3Cgntrqd808eTT5G2HU9TxUiSbBXa/YDqAw0gWMu35UGf/hmPcUDOX/BoTZ/VbLgF9tSHbg/09imupDoFU9nUco0+SMpQ7EPUXEYwxWFF2rT3Nnn5I9MZOLaki7WlSU1vOtW6Wo2Uytf3OEVEXlNQzlhu9I+1xo4B5XR6bh8E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695317978; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vZDpPDL7VYx+NDtQ2pIz8KgGd+MM5dll5CqhqvtnfHo=; b=WDgrL0vDpMMiFXV4pxCIW/xzrdEtXrd4qYznHWPaFGzKw24hF23u5yrLkC5hZLFT9wP4yD9HINpeRBLoBOhfLJJIStlkLy0KWcXqjwAHUq4rCLigQ0GSd+pswKQK/jMkMZp+cMPQh7vdFR36EIdk886NztEQdL1U/42iOql2klk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695317978133554.7875840298112; Thu, 21 Sep 2023 10:39:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNci-0002D4-9E; Thu, 21 Sep 2023 13:37:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNcg-0002C9-Uf for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:54 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcN-0007iG-Vx for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:54 -0400 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-313e742a787so820267f8f.1 for ; Thu, 21 Sep 2023 10:37:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317854; x=1695922654; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=vZDpPDL7VYx+NDtQ2pIz8KgGd+MM5dll5CqhqvtnfHo=; b=p4oBAAb5WRhVfPXj838iDyoLzqwu9lsAqLPZcEsgnblA/vMp2UyQcdAisqpLAmi7Iv l/BL1eggAnjgTBvEnPKkpK99VeWCPtZgAhR2T5nNdLAHdi2kFYPPVTq1VTqFnwuR+yVh zGi7Y2qLMxy1k4IDvCaHC6Uv3a/JgUKs5wwerCcyZ218H8R2xIeMe5J4OEIXU5kZaTvw H08seop1nSNuFjxieL6oq0w3euUt7/XyzsK6vO+YoOOzCdEVDTrmsF0BUXxbyNhWD+Es jdItVcNUMt0SOb0ox1bWbMKM2dMJQfyKq4dd/RONSowBSsJDFRLPaMVCYlnJEwinjL9m dEAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317854; x=1695922654; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vZDpPDL7VYx+NDtQ2pIz8KgGd+MM5dll5CqhqvtnfHo=; b=rkQnjIGlKDAjvMZPIvZCj8VI3o2cn0EOgCVKWBDZPa3gZMNFL3ntqrGwJv5oGP5ZzY LZPzwNF0g3c0Zq97llYgl3KHZnsFJleB+CncqyUbfVqWj6lB/oBKXK25gCevgnCEdVwt 1CyFswwtSS2BG38db/73dxxSZ/Wde+oQHCOf2MhpN0l0vq2AKbaq6ux7rDrXKZ26a+qQ aQP+bq9IizJh3XePCrO2odbQiaewmkgcqgtRw8fI3WxrwBBrFwYjPm9K07jivA+DVgMv C3fU329h3y2XyAVHioBVulNZOgLA/UF9yLtBddSEobe/kymYiNG7XjQVQ3MRJkxJC0SJ YX5w== X-Gm-Message-State: AOJu0YyrOnHi0QAayei9gd3gm8LPxFQ+iAnZ8OGnwUcVcVc7wjZEqERR liBMhRQB7YnZvWwUcQCUljHjJo0yELYr/2YVllI= X-Google-Smtp-Source: AGHT+IGfGhlJ71UO5PON7FYd2p1+Q2BMpYQhtY0fpYVm4q+u3Mif34p61SgrFnwD/1EJz3Vj7JfO9Q== X-Received: by 2002:adf:cc8c:0:b0:320:2b29:7041 with SMTP id p12-20020adfcc8c000000b003202b297041mr199934wrj.24.1695317854416; Thu, 21 Sep 2023 10:37:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/30] elf2dmp: replace PE export name check with PDB name check Date: Thu, 21 Sep 2023 18:37:16 +0100 Message-Id: <20230921173720.3250581-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695317978492100001 Content-Type: text/plain; charset="utf-8" From: Viktor Prutyanov PE export name check introduced in d399d6b179 isn't reliable enough, because a page with the export directory may be not present for some reason. On the other hand, elf2dmp retrieves the PDB name in any case. It can be also used to check that a PE image is the kernel image. So, check PDB name when searching for Windows kernel image. Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=3D2165917 Signed-off-by: Viktor Prutyanov Reviewed-by: Akihiko Odaki Message-id: 20230915170153.10959-2-viktor@daynix.com Signed-off-by: Peter Maydell --- contrib/elf2dmp/main.c | 93 +++++++++++++++--------------------------- 1 file changed, 33 insertions(+), 60 deletions(-) diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c index 6d4d18501a3..bb6744c0cd6 100644 --- a/contrib/elf2dmp/main.c +++ b/contrib/elf2dmp/main.c @@ -411,89 +411,64 @@ static int write_dump(struct pa_space *ps, return fclose(dmp_file); } =20 -static bool pe_check_export_name(uint64_t base, void *start_addr, - struct va_space *vs) -{ - IMAGE_EXPORT_DIRECTORY export_dir; - const char *pe_name; - - if (pe_get_data_dir_entry(base, start_addr, IMAGE_FILE_EXPORT_DIRECTOR= Y, - &export_dir, sizeof(export_dir), vs)) { - return false; - } - - pe_name =3D va_space_resolve(vs, base + export_dir.Name); - if (!pe_name) { - return false; - } - - return !strcmp(pe_name, PE_NAME); -} - -static int pe_get_pdb_symstore_hash(uint64_t base, void *start_addr, - char *hash, struct va_space *vs) +static bool pe_check_pdb_name(uint64_t base, void *start_addr, + struct va_space *vs, OMFSignatureRSDS *rsds) { const char sign_rsds[4] =3D "RSDS"; IMAGE_DEBUG_DIRECTORY debug_dir; - OMFSignatureRSDS rsds; - char *pdb_name; - size_t pdb_name_sz; - size_t i; + char pdb_name[sizeof(PDB_NAME)]; =20 if (pe_get_data_dir_entry(base, start_addr, IMAGE_FILE_DEBUG_DIRECTORY, &debug_dir, sizeof(debug_dir), vs)) { eprintf("Failed to get Debug Directory\n"); - return 1; + return false; } =20 if (debug_dir.Type !=3D IMAGE_DEBUG_TYPE_CODEVIEW) { - return 1; + eprintf("Debug Directory type is not CodeView\n"); + return false; } =20 if (va_space_rw(vs, base + debug_dir.AddressOfRawData, - &rsds, sizeof(rsds), 0)) { - return 1; + rsds, sizeof(*rsds), 0)) { + eprintf("Failed to resolve OMFSignatureRSDS\n"); + return false; } =20 - printf("CodeView signature is \'%.4s\'\n", rsds.Signature); - - if (memcmp(&rsds.Signature, sign_rsds, sizeof(sign_rsds))) { - return 1; + if (memcmp(&rsds->Signature, sign_rsds, sizeof(sign_rsds))) { + eprintf("CodeView signature is \'%.4s\', \'%s\' expected\n", + rsds->Signature, sign_rsds); + return false; } =20 - pdb_name_sz =3D debug_dir.SizeOfData - sizeof(rsds); - pdb_name =3D malloc(pdb_name_sz); - if (!pdb_name) { - return 1; + if (debug_dir.SizeOfData - sizeof(*rsds) !=3D sizeof(PDB_NAME)) { + eprintf("PDB name size doesn't match\n"); + return false; } =20 if (va_space_rw(vs, base + debug_dir.AddressOfRawData + - offsetof(OMFSignatureRSDS, name), pdb_name, pdb_name_sz, 0= )) { - free(pdb_name); - return 1; + offsetof(OMFSignatureRSDS, name), pdb_name, sizeof(PDB_NAM= E), + 0)) { + eprintf("Failed to resolve PDB name\n"); + return false; } =20 printf("PDB name is \'%s\', \'%s\' expected\n", pdb_name, PDB_NAME); =20 - if (strcmp(pdb_name, PDB_NAME)) { - eprintf("Unexpected PDB name, it seems the kernel isn't found\n"); - free(pdb_name); - return 1; - } + return !strcmp(pdb_name, PDB_NAME); +} =20 - free(pdb_name); - - sprintf(hash, "%.08x%.04x%.04x%.02x%.02x", rsds.guid.a, rsds.guid.b, - rsds.guid.c, rsds.guid.d[0], rsds.guid.d[1]); +static void pe_get_pdb_symstore_hash(OMFSignatureRSDS *rsds, char *hash) +{ + sprintf(hash, "%.08x%.04x%.04x%.02x%.02x", rsds->guid.a, rsds->guid.b, + rsds->guid.c, rsds->guid.d[0], rsds->guid.d[1]); hash +=3D 20; - for (i =3D 0; i < 6; i++, hash +=3D 2) { - sprintf(hash, "%.02x", rsds.guid.e[i]); + for (unsigned int i =3D 0; i < 6; i++, hash +=3D 2) { + sprintf(hash, "%.02x", rsds->guid.e[i]); } =20 - sprintf(hash, "%.01x", rsds.age); - - return 0; + sprintf(hash, "%.01x", rsds->age); } =20 int main(int argc, char *argv[]) @@ -515,6 +490,7 @@ int main(int argc, char *argv[]) KDDEBUGGER_DATA64 *kdbg; uint64_t KdVersionBlock; bool kernel_found =3D false; + OMFSignatureRSDS rsds; =20 if (argc !=3D 3) { eprintf("usage:\n\t%s elf_file dmp_file\n", argv[0]); @@ -562,7 +538,8 @@ int main(int argc, char *argv[]) } =20 if (*(uint16_t *)nt_start_addr =3D=3D 0x5a4d) { /* MZ */ - if (pe_check_export_name(KernBase, nt_start_addr, &vs)) { + printf("Checking candidate KernBase =3D 0x%016"PRIx64"\n", Ker= nBase); + if (pe_check_pdb_name(KernBase, nt_start_addr, &vs, &rsds)) { kernel_found =3D true; break; } @@ -578,11 +555,7 @@ int main(int argc, char *argv[]) printf("KernBase =3D 0x%016"PRIx64", signature is \'%.2s\'\n", KernBas= e, (char *)nt_start_addr); =20 - if (pe_get_pdb_symstore_hash(KernBase, nt_start_addr, pdb_hash, &vs)) { - eprintf("Failed to get PDB symbol store hash\n"); - err =3D 1; - goto out_ps; - } + pe_get_pdb_symstore_hash(&rsds, pdb_hash); =20 sprintf(pdb_url, "%s%s/%s/%s", SYM_URL_BASE, PDB_NAME, pdb_hash, PDB_N= AME); printf("PDB URL is %s\n", pdb_url); --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695318121; cv=none; d=zohomail.com; s=zohoarc; b=C7QcLORBCgTnLShWCzu6ThjbMD499j04McScEErLU4OfPhYy2uHASKZFub0ne0gH5meKkDui6kPets8SGo40EmSSX5DQQXmUHSIpvnKRzzBnzIotZnTK48kmrTBvVq54i8qQwdNdVZW8gWlk9gQbrYBXPfmlABmMUP0CdmsW4hs= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317855; x=1695922655; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=tpP7WvKkmw1P1SqkcMNN7UBPT2euBBFe5uh9vcxXSwE=; b=c1BQo2gYW29AceuPVkr6eld4+Cja0HwMR8XMKithGZp/VjFwpDaNG1TWVfccGIEUCd pDe5Rt9zqL6hW74xIBnE0iwrSde7Ob+cwUpooV40zuoBsoBHLBnZajMS15lGO1sd1gCK KU0zXWwjxpj07LvizmqOzlVivYIGjNIKOoubU1JaVzcD6egB8XzHzRXpPCc73BOZM4ZJ e6RdqQC5ns0GCELud1FQ8Mfag5VDp4AOG5cvkq3BeDHXr6uLoYJDiNSM++2EB6KUQXWT +y7pE1jqd2+IBksUiwAdk3/5lJvlPp66ewnNPC1SpFVC1hVXji6bWsNxzeO7uvt+flp7 yjxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317855; x=1695922655; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tpP7WvKkmw1P1SqkcMNN7UBPT2euBBFe5uh9vcxXSwE=; b=aXkBRDa9SD9H9w9KMq/z43uSCyoUL2KaqN3epMc8zAhrLcO2wPjaQGrcyOoDfZq1kj 7CwCpovvsLEFZEdT4JqcVwCgpFw8oQ0/4AHnCr8XSde+8bkadqx8pzMc6ExT464K3+uy rTTi1PsEKI4KU90tbzNe6X0DmKklRKZf8jPa8KoFRpJQ5+cFkG7BvI3SQcAetYLMtaxR 57k2Ojdr5uRMCVKZNNzoL6ApeYdMBaULxxO7CbgDlY8MHcqyP/FVZR+3Qszf+zczUENu LcElyo8vwgBOSdmcREbNFdEorSDYPwogl+zwkyIiCI/8Dh/cBwwle4GPpmVC8EsxAWF1 fGWg== X-Gm-Message-State: AOJu0YwHVh0CllltO+4lsZBFnPVmniQifM7Lvs5KbNZRviiMiCEkB5cb R2qnCfeKk9BsKpiZxsiFlaYKTmcHDYYR1UyNmcw= X-Google-Smtp-Source: AGHT+IH7r4ugyOxzVjNWfgYNl6YlesOHsq999nDG4SUbzTexgs0pDk0yeWUToTZIhsKArMqCqhPMKw== X-Received: by 2002:a5d:6346:0:b0:31f:e5cf:6724 with SMTP id b6-20020a5d6346000000b0031fe5cf6724mr6508426wrw.46.1695317854816; Thu, 21 Sep 2023 10:37:34 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/30] elf2dmp: introduce physical block alignment Date: Thu, 21 Sep 2023 18:37:17 +0100 Message-Id: <20230921173720.3250581-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318121840100019 Content-Type: text/plain; charset="utf-8" From: Viktor Prutyanov Physical memory ranges may not be aligned to page size in QEMU ELF, but DMP can only contain page-aligned runs. So, align them. Signed-off-by: Viktor Prutyanov Reviewed-by: Akihiko Odaki Message-id: 20230915170153.10959-3-viktor@daynix.com Signed-off-by: Peter Maydell --- contrib/elf2dmp/addrspace.h | 1 + contrib/elf2dmp/addrspace.c | 31 +++++++++++++++++++++++++++++-- contrib/elf2dmp/main.c | 5 +++-- 3 files changed, 33 insertions(+), 4 deletions(-) diff --git a/contrib/elf2dmp/addrspace.h b/contrib/elf2dmp/addrspace.h index 00b44c12180..039c70c5b07 100644 --- a/contrib/elf2dmp/addrspace.h +++ b/contrib/elf2dmp/addrspace.h @@ -12,6 +12,7 @@ =20 #define ELF2DMP_PAGE_BITS 12 #define ELF2DMP_PAGE_SIZE (1ULL << ELF2DMP_PAGE_BITS) +#define ELF2DMP_PAGE_MASK (ELF2DMP_PAGE_SIZE - 1) #define ELF2DMP_PFN_MASK (~(ELF2DMP_PAGE_SIZE - 1)) =20 #define INVALID_PA UINT64_MAX diff --git a/contrib/elf2dmp/addrspace.c b/contrib/elf2dmp/addrspace.c index 0b04cba00e5..64b5d680adc 100644 --- a/contrib/elf2dmp/addrspace.c +++ b/contrib/elf2dmp/addrspace.c @@ -14,7 +14,7 @@ static struct pa_block *pa_space_find_block(struct pa_spa= ce *ps, uint64_t pa) =20 for (i =3D 0; i < ps->block_nr; i++) { if (ps->block[i].paddr <=3D pa && - pa <=3D ps->block[i].paddr + ps->block[i].size) { + pa < ps->block[i].paddr + ps->block[i].size) { return ps->block + i; } } @@ -33,6 +33,30 @@ static uint8_t *pa_space_resolve(struct pa_space *ps, ui= nt64_t pa) return block->addr + (pa - block->paddr); } =20 +static void pa_block_align(struct pa_block *b) +{ + uint64_t low_align =3D ((b->paddr - 1) | ELF2DMP_PAGE_MASK) + 1 - b->p= addr; + uint64_t high_align =3D (b->paddr + b->size) & ELF2DMP_PAGE_MASK; + + if (low_align =3D=3D 0 && high_align =3D=3D 0) { + return; + } + + if (low_align + high_align < b->size) { + printf("Block 0x%"PRIx64"+:0x%"PRIx64" will be aligned to " + "0x%"PRIx64"+:0x%"PRIx64"\n", b->paddr, b->size, + b->paddr + low_align, b->size - low_align - high_align); + b->size -=3D low_align + high_align; + } else { + printf("Block 0x%"PRIx64"+:0x%"PRIx64" is too small to align\n", + b->paddr, b->size); + b->size =3D 0; + } + + b->addr +=3D low_align; + b->paddr +=3D low_align; +} + int pa_space_create(struct pa_space *ps, QEMU_Elf *qemu_elf) { Elf64_Half phdr_nr =3D elf_getphdrnum(qemu_elf->map); @@ -60,10 +84,13 @@ int pa_space_create(struct pa_space *ps, QEMU_Elf *qemu= _elf) .paddr =3D phdr[i].p_paddr, .size =3D phdr[i].p_filesz, }; - block_i++; + pa_block_align(&ps->block[block_i]); + block_i =3D ps->block[block_i].size ? (block_i + 1) : block_i; } } =20 + ps->block_nr =3D block_i; + return 0; } =20 diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c index bb6744c0cd6..b7e39301641 100644 --- a/contrib/elf2dmp/main.c +++ b/contrib/elf2dmp/main.c @@ -400,9 +400,10 @@ static int write_dump(struct pa_space *ps, for (i =3D 0; i < ps->block_nr; i++) { struct pa_block *b =3D &ps->block[i]; =20 - printf("Writing block #%zu/%zu to file...\n", i, ps->block_nr); + printf("Writing block #%zu/%zu of %"PRIu64" bytes to file...\n", i, + ps->block_nr, b->size); if (fwrite(b->addr, b->size, 1, dmp_file) !=3D 1) { - eprintf("Failed to write dump header\n"); + eprintf("Failed to write block\n"); fclose(dmp_file); return 1; } --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695318139; cv=none; d=zohomail.com; s=zohoarc; b=SciQVnrRX7uT/lLH4UwdBl76DogXIuVTs61FGinov+LZh4b08yj8/RXzbRZpjsqmWc9IxBtCcsWftCS6a1ksE1h7xgEdcegIbtAUKJBw+2CeQCMY6JNt76JHYASK+3bt4WPenxdJhZxJP0qYmhgO0JO1I8B1oCZt/6BcvqBGzbU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695318139; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hhll5MSt7inD7Gvy+K2LRa4bhUXToZUa0sCF87IjAjw=; b=NOoytpOTIwncR85tINzwzHKWmhGvSvgL06SAhWN3h0Uplzv8C+ckrUwSvqwmU1InUmQi6NGuf46MrfopBZvh5wxPkmJFlDl7ldaHPpa5Vuxu81pWKE8LFftMAGosqdQpbxoARrSIA7iX00vINx45bC44oMAW1ooGCMBb/oUuhgc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169531813967911.681661741662424; Thu, 21 Sep 2023 10:42:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qjNcZ-00028w-KT; Thu, 21 Sep 2023 13:37:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qjNcX-00027V-Bi for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:45 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qjNcO-0007iW-Jp for qemu-devel@nongnu.org; Thu, 21 Sep 2023 13:37:45 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-4051fea48a8so14402235e9.2 for ; Thu, 21 Sep 2023 10:37:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317855; x=1695922655; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=hhll5MSt7inD7Gvy+K2LRa4bhUXToZUa0sCF87IjAjw=; b=fkzi59TXjCgC2g4vlEfg0AarpdcBxTo30RnCBiKybc4fAhfUM+gDEmu4RDvA979piJ HLj58faS8eT6MY1FVEgPVkTBhjA+L9kDHjz2M1Qi8VClq/xZL1xXklpNZp8ky4J5ica2 kVNaURyKkmtkFy+EEPFsI7fQmv+cirO9W8nQZoh6A+EMv1NzhttzzBsxKQNtGV83oUZ2 sKngUDUhuNne3iqhPGP8zji3QvggftWWFh9sR7ZsgwS9OhUJUuXJ8P3nmWE28Dv4nfub TPISiMXzB6zmm/Ctc1M7yI8FJ5UGR7/z7S7IrbgJLkIg9WsMMLYUiD1qXWfzhJFsbfXr AW+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317855; x=1695922655; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hhll5MSt7inD7Gvy+K2LRa4bhUXToZUa0sCF87IjAjw=; b=Utwcz4brG8cX2fyZxhNJYuG3VQ+qJUhMysABLZUUXoNcYkY5BavBuTuU3WHyCW7wlD 0FV1+OYuk8+pNBCIwwtnPsXPpDsNWYyrffOIhChiL3PlIBxk4UGJoLA74byLdHJHJAjB VJWldHJnjex2XZ7iTnDhgOuLCLuJlZVjj3L8Rnj/Q1T0opX7gEkaOPYE8B1VVtCJffiU 51KqFmJzjZ9n78QGR7pSCE7hS2eDVRfW8fDcS1cY4B10ualzopN10ApLlj9FrCY1xCd/ Pjhh/y5Oq0p3DOvoLKoVFCYDkI0FJe01h9MgS6H1coZRmxImSfgYsa0KK7yPH1MW6G11 b2jg== X-Gm-Message-State: AOJu0Yyuk0UvOLhC3xrid8YVO9cGd2g2I9Ijo7QupSV+R4IeEBcnmigN 1e+NJG7G2CHMOlWXzRNVY64UgqvvZYauB0ikXAw= X-Google-Smtp-Source: AGHT+IFnYHgGyKgFIg662xzfX53i7vf3uGvxlcchKJug6mi57gD6A55LqmS7srmV98cEAcQAHHOILQ== X-Received: by 2002:a05:600c:364a:b0:401:dc7c:2488 with SMTP id y10-20020a05600c364a00b00401dc7c2488mr5366494wmq.11.1695317855215; Thu, 21 Sep 2023 10:37:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/30] elf2dmp: introduce merging of physical memory runs Date: Thu, 21 Sep 2023 18:37:18 +0100 Message-Id: <20230921173720.3250581-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318140157100001 Content-Type: text/plain; charset="utf-8" From: Viktor Prutyanov DMP supports 42 physical memory runs at most. So, merge adjacent physical memory ranges from QEMU ELF when possible to minimize total number of runs. Signed-off-by: Viktor Prutyanov Reviewed-by: Akihiko Odaki Message-id: 20230915170153.10959-4-viktor@daynix.com [PMM: fixed format string for printing size_t values] Signed-off-by: Peter Maydell --- contrib/elf2dmp/main.c | 56 ++++++++++++++++++++++++++++++++++++------ 1 file changed, 48 insertions(+), 8 deletions(-) diff --git a/contrib/elf2dmp/main.c b/contrib/elf2dmp/main.c index b7e39301641..5db163bdbe8 100644 --- a/contrib/elf2dmp/main.c +++ b/contrib/elf2dmp/main.c @@ -20,6 +20,7 @@ #define PE_NAME "ntoskrnl.exe" =20 #define INITIAL_MXCSR 0x1f80 +#define MAX_NUMBER_OF_RUNS 42 =20 typedef struct idt_desc { uint16_t offset1; /* offset bits 0..15 */ @@ -234,6 +235,42 @@ static int fix_dtb(struct va_space *vs, QEMU_Elf *qe) return 1; } =20 +static void try_merge_runs(struct pa_space *ps, + WinDumpPhyMemDesc64 *PhysicalMemoryBlock) +{ + unsigned int merge_cnt =3D 0, run_idx =3D 0; + + PhysicalMemoryBlock->NumberOfRuns =3D 0; + + for (size_t idx =3D 0; idx < ps->block_nr; idx++) { + struct pa_block *blk =3D ps->block + idx; + struct pa_block *next =3D blk + 1; + + PhysicalMemoryBlock->NumberOfPages +=3D blk->size / ELF2DMP_PAGE_S= IZE; + + if (idx + 1 !=3D ps->block_nr && blk->paddr + blk->size =3D=3D nex= t->paddr) { + printf("Block #%zu 0x%"PRIx64"+:0x%"PRIx64" and %u previous wi= ll be" + " merged\n", idx, blk->paddr, blk->size, merge_cnt); + merge_cnt++; + } else { + struct pa_block *first_merged =3D blk - merge_cnt; + + printf("Block #%zu 0x%"PRIx64"+:0x%"PRIx64" and %u previous wi= ll be" + " merged to 0x%"PRIx64"+:0x%"PRIx64" (run #%u)\n", + idx, blk->paddr, blk->size, merge_cnt, first_merged->p= addr, + blk->paddr + blk->size - first_merged->paddr, run_idx); + PhysicalMemoryBlock->Run[run_idx] =3D (WinDumpPhyMemRun64) { + .BasePage =3D first_merged->paddr / ELF2DMP_PAGE_SIZE, + .PageCount =3D (blk->paddr + blk->size - first_merged->pad= dr) / + ELF2DMP_PAGE_SIZE, + }; + PhysicalMemoryBlock->NumberOfRuns++; + run_idx++; + merge_cnt =3D 0; + } + } +} + static int fill_header(WinDumpHeader64 *hdr, struct pa_space *ps, struct va_space *vs, uint64_t KdDebuggerDataBlock, KDDEBUGGER_DATA64 *kdbg, uint64_t KdVersionBlock, int nr_cpus) @@ -244,7 +281,6 @@ static int fill_header(WinDumpHeader64 *hdr, struct pa_= space *ps, KUSD_OFFSET_PRODUCT_TYPE); DBGKD_GET_VERSION64 kvb; WinDumpHeader64 h; - size_t i; =20 QEMU_BUILD_BUG_ON(KUSD_OFFSET_SUITE_MASK >=3D ELF2DMP_PAGE_SIZE); QEMU_BUILD_BUG_ON(KUSD_OFFSET_PRODUCT_TYPE >=3D ELF2DMP_PAGE_SIZE); @@ -282,13 +318,17 @@ static int fill_header(WinDumpHeader64 *hdr, struct p= a_space *ps, .RequiredDumpSpace =3D sizeof(h), }; =20 - for (i =3D 0; i < ps->block_nr; i++) { - h.PhysicalMemoryBlock.NumberOfPages +=3D - ps->block[i].size / ELF2DMP_PAGE_SIZE; - h.PhysicalMemoryBlock.Run[i] =3D (WinDumpPhyMemRun64) { - .BasePage =3D ps->block[i].paddr / ELF2DMP_PAGE_SIZE, - .PageCount =3D ps->block[i].size / ELF2DMP_PAGE_SIZE, - }; + if (h.PhysicalMemoryBlock.NumberOfRuns <=3D MAX_NUMBER_OF_RUNS) { + for (size_t idx =3D 0; idx < ps->block_nr; idx++) { + h.PhysicalMemoryBlock.NumberOfPages +=3D + ps->block[idx].size / ELF2DMP_PAGE_SIZE; + h.PhysicalMemoryBlock.Run[idx] =3D (WinDumpPhyMemRun64) { + .BasePage =3D ps->block[idx].paddr / ELF2DMP_PAGE_SIZE, + .PageCount =3D ps->block[idx].size / ELF2DMP_PAGE_SIZE, + }; + } + } else { + try_merge_runs(ps, &h.PhysicalMemoryBlock); } =20 h.RequiredDumpSpace +=3D --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695318115; cv=none; d=zohomail.com; s=zohoarc; b=gm0L8+w0JhlMj6GE9uc0muzaTKJsLdHRIR2YdSqDnlUsFLly8J7i4NEitrKXa6iIrjKvCO0e68FiWsgRDMlrz9grmZ37abO3Vm6ZBu/6chm2ULFtEA91LSY5nziHqe6ALb4wTwx9Pobl+oC+VAoZHK/qE+T+sX2Ssr9CQa+MW4M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695318115; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=okurW1rZE+ASazRHBXqN9Qp4RNXWE3FoF9D8aOYfxp8=; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317855; x=1695922655; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=okurW1rZE+ASazRHBXqN9Qp4RNXWE3FoF9D8aOYfxp8=; b=KIfK6ZaK4vvv9jkyufJprjry8lKeuE8V/6xcMxIKwag4zKFl2Ylr+npNF1Je01+egB G8VBGV3SHoY1ZsdGt+er5RA/HodDA/wo+5m7caNS+nsQRNb4lTg4JmrVFvJnmCREsqiK wq+IzfmatE6RONHylMVg18Nu72m3PIg/Gni32xk4RDuBnkQ/y7wIiKTP2mFTeWNG3f7D 6GRUmKjz91nuMXadFu6xI1OG7ewBRhievm+mQb4AdFxt/SArkEybzi+LUABO7tofCBVW S7+KNfavzPQ7wh3ME855DZ/96EjVVJIxmfQCVt2J4p+33qfPm175LHd83l66HPDKy4HO UioA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317855; x=1695922655; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=okurW1rZE+ASazRHBXqN9Qp4RNXWE3FoF9D8aOYfxp8=; b=FoMbSjGdVE6BqjtA0X8nrVV/x2oVcJvkktopnE9YqnlGGEZnSaildfIqx7AP+qcEd1 tGQb5ZuQLHJu89kNYFMI+j1+BfILRq07+kfCV38ys90IXVbo+BhHmlwUG5O8UYRV+KOl ubjq8pHArQG2UjR8JMmxP8iCHE+9VSCEc4h82+CEby017IaGXOgqV6lv4a+XBLOCk/WD ZM5FyEPtM7H8SqL3nNwhtJw2DSP1mf320bDY5wEywrUarGM+7m6QYeL8FbM73P8dbZcT ZEwVINDkIMgSq11ZRu5wjiYy8Gy76fE1wJ4UCJAT1oWH8fguYConGg7OolbVPayxlInc 90UQ== X-Gm-Message-State: AOJu0YwqHg0rl6FqyOzh6Mnd98QIMLknxJhOnQ6voF3dEk7SpemYPbQh b7qSclfuRWf+dP1uPOE611FBoBoME+WziU0SqGg= X-Google-Smtp-Source: AGHT+IEKI7llB3o9ft/iD+y0ASIv4CdIIrJBdNBgkWaAbSC+yiI2nQR/aPj9zVywcUjq92BPGiXWwQ== X-Received: by 2002:a1c:771a:0:b0:401:bf56:8ba0 with SMTP id t26-20020a1c771a000000b00401bf568ba0mr5368012wmi.28.1695317855655; Thu, 21 Sep 2023 10:37:35 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/30] elf2dmp: use Linux mmap with MAP_NORESERVE when possible Date: Thu, 21 Sep 2023 18:37:19 +0100 Message-Id: <20230921173720.3250581-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318115933100003 Content-Type: text/plain; charset="utf-8" From: Viktor Prutyanov Glib's g_mapped_file_new maps file with PROT_READ|PROT_WRITE and MAP_PRIVATE. This leads to premature physical memory allocation of dump file size on Linux hosts and may fail. On Linux, mapping the file with MAP_NORESERVE limits the allocation by available memory. Signed-off-by: Viktor Prutyanov Reviewed-by: Akihiko Odaki Message-id: 20230915170153.10959-5-viktor@daynix.com Signed-off-by: Peter Maydell --- contrib/elf2dmp/qemu_elf.h | 2 ++ contrib/elf2dmp/qemu_elf.c | 68 +++++++++++++++++++++++++++++++------- 2 files changed, 58 insertions(+), 12 deletions(-) diff --git a/contrib/elf2dmp/qemu_elf.h b/contrib/elf2dmp/qemu_elf.h index b2f0d9cbc9b..afa75f10b2d 100644 --- a/contrib/elf2dmp/qemu_elf.h +++ b/contrib/elf2dmp/qemu_elf.h @@ -32,7 +32,9 @@ typedef struct QEMUCPUState { int is_system(QEMUCPUState *s); =20 typedef struct QEMU_Elf { +#ifndef CONFIG_LINUX GMappedFile *gmf; +#endif size_t size; void *map; QEMUCPUState **state; diff --git a/contrib/elf2dmp/qemu_elf.c b/contrib/elf2dmp/qemu_elf.c index ebda60dcb8a..de6ad744c6d 100644 --- a/contrib/elf2dmp/qemu_elf.c +++ b/contrib/elf2dmp/qemu_elf.c @@ -165,10 +165,40 @@ static bool check_ehdr(QEMU_Elf *qe) return true; } =20 -int QEMU_Elf_init(QEMU_Elf *qe, const char *filename) +static int QEMU_Elf_map(QEMU_Elf *qe, const char *filename) { +#ifdef CONFIG_LINUX + struct stat st; + int fd; + + printf("Using Linux mmap\n"); + + fd =3D open(filename, O_RDONLY, 0); + if (fd =3D=3D -1) { + eprintf("Failed to open ELF dump file \'%s\'\n", filename); + return 1; + } + + if (fstat(fd, &st)) { + eprintf("Failed to get size of ELF dump file\n"); + close(fd); + return 1; + } + qe->size =3D st.st_size; + + qe->map =3D mmap(NULL, qe->size, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_NORESERVE, fd, 0); + if (qe->map =3D=3D MAP_FAILED) { + eprintf("Failed to map ELF file\n"); + close(fd); + return 1; + } + + close(fd); +#else GError *gerr =3D NULL; - int err =3D 0; + + printf("Using GLib mmap\n"); =20 qe->gmf =3D g_mapped_file_new(filename, TRUE, &gerr); if (gerr) { @@ -179,29 +209,43 @@ int QEMU_Elf_init(QEMU_Elf *qe, const char *filename) =20 qe->map =3D g_mapped_file_get_contents(qe->gmf); qe->size =3D g_mapped_file_get_length(qe->gmf); +#endif + + return 0; +} + +static void QEMU_Elf_unmap(QEMU_Elf *qe) +{ +#ifdef CONFIG_LINUX + munmap(qe->map, qe->size); +#else + g_mapped_file_unref(qe->gmf); +#endif +} + +int QEMU_Elf_init(QEMU_Elf *qe, const char *filename) +{ + if (QEMU_Elf_map(qe, filename)) { + return 1; + } =20 if (!check_ehdr(qe)) { eprintf("Input file has the wrong format\n"); - err =3D 1; - goto out_unmap; + QEMU_Elf_unmap(qe); + return 1; } =20 if (init_states(qe)) { eprintf("Failed to extract QEMU CPU states\n"); - err =3D 1; - goto out_unmap; + QEMU_Elf_unmap(qe); + return 1; } =20 return 0; - -out_unmap: - g_mapped_file_unref(qe->gmf); - - return err; } =20 void QEMU_Elf_exit(QEMU_Elf *qe) { exit_states(qe); - g_mapped_file_unref(qe->gmf); + QEMU_Elf_unmap(qe); } --=20 2.34.1 From nobody Sat May 18 09:48:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1695318115; cv=none; d=zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id m14-20020a7bce0e000000b003feff926fc5sm2464122wmc.17.2023.09.21.10.37.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 10:37:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695317856; x=1695922656; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=yrJfngMZeFXFPS0lgWoyofdpWugV34Omj7KHLp5edtM=; b=ORVtK0PQKqXj5RLBh/INzryz6oC+3tRiF2rHB0koayxEp4tqXWmNLB/KF9SY4qDdeq 3jHN0etGTZ5IeLydzCCyg5174+v1cOBaPvQa9Dkd84YOR/5TPK6FKL6xH9NgtZ2I9EFT 9e8i7jyjYzqw8b2a1ifHQGgQPdfkHBRaxWgY5nFKjhv//dtR0JM7wvDNfiPsjcVWqyD+ re0bfS/FAjFs/2yT0Bh2pFc7ndEn5rm5daaQlwYDZg6JCPzynWJfJBiq/igWSyuEXT5t nBJo0BTDVQAoDEuxaA3jEMUBuFOBTgD38PD+7cRt3nWOk1YaJImUeCB14e9T4q1/N++N zpAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695317856; x=1695922656; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yrJfngMZeFXFPS0lgWoyofdpWugV34Omj7KHLp5edtM=; b=u8jR6ynZlr/k0izne8KIcsDv0cVCYE/q4xor7f9gLm0+MW26v71t/AFK7msCNgFOW3 wap1F6MxOH/q2NviFGzrrb4OMUcFWjMbRQmg+XWBJVwPbFyVs6UZOD/pGtw999ax7GmE Y9toC3amwf8RlIlRofe80zGFlCOMSyLfMfK4NChkIhVZt7QVig2F2pAjZH8paxTrrCaB M0h5bPJIXqecQz4nBqz/G/OJsDFBAqQbobB/CqHP79fexh/EGbeIfM0m0aHI7wu8xet0 G9JIbjgRd0C63eJ+ztpnHyoOtD4LgmjORKV+IaRUtvSe30mfEFhts6CQT8M/iVPdIoUY DSpw== X-Gm-Message-State: AOJu0YxHuH+FIMwcGVK7U0SvJ1HodpJ0axMbh8Zxr1tDXFn6Q9L4GQcL aAcYYToe60Y5xUyex/wvCnAN4g5daLHb0evwWrQ= X-Google-Smtp-Source: AGHT+IErwpX7FoyOBKahkSrQqA9bj/JJ2v/g5JaSJ0Wf3616m3YoB6mNUVePR5UEddwUsOaG/INPgQ== X-Received: by 2002:a05:600c:a381:b0:3fb:a0fc:1ba1 with SMTP id hn1-20020a05600ca38100b003fba0fc1ba1mr5546438wmb.35.1695317856170; Thu, 21 Sep 2023 10:37:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/30] elf2dmp: rework PDB_STREAM_INDEXES::segments obtaining Date: Thu, 21 Sep 2023 18:37:20 +0100 Message-Id: <20230921173720.3250581-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230921173720.3250581-1-peter.maydell@linaro.org> References: <20230921173720.3250581-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1695318116478100005 Content-Type: text/plain; charset="utf-8" From: Viktor Prutyanov PDB for Windows 11 kernel has slightly different structure compared to previous versions. Since elf2dmp don't use the other fields, copy only 'segments' field from PDB_STREAM_INDEXES. Signed-off-by: Viktor Prutyanov Reviewed-by: Akihiko Odaki Message-id: 20230915170153.10959-6-viktor@daynix.com Signed-off-by: Peter Maydell --- contrib/elf2dmp/pdb.h | 2 +- contrib/elf2dmp/pdb.c | 15 ++++----------- 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/contrib/elf2dmp/pdb.h b/contrib/elf2dmp/pdb.h index 4ea8925ee82..2a50da56ac9 100644 --- a/contrib/elf2dmp/pdb.h +++ b/contrib/elf2dmp/pdb.h @@ -227,7 +227,7 @@ struct pdb_reader { } ds; uint32_t file_used[1024]; PDB_SYMBOLS *symbols; - PDB_STREAM_INDEXES sidx; + uint16_t segments; uint8_t *modimage; char *segs; size_t segs_size; diff --git a/contrib/elf2dmp/pdb.c b/contrib/elf2dmp/pdb.c index adcfa7e154c..6ca5086f02e 100644 --- a/contrib/elf2dmp/pdb.c +++ b/contrib/elf2dmp/pdb.c @@ -160,7 +160,7 @@ static void *pdb_ds_read_file(struct pdb_reader* r, uin= t32_t file_number) static int pdb_init_segments(struct pdb_reader *r) { char *segs; - unsigned stream_idx =3D r->sidx.segments; + unsigned stream_idx =3D r->segments; =20 segs =3D pdb_ds_read_file(r, stream_idx); if (!segs) { @@ -177,9 +177,6 @@ static int pdb_init_symbols(struct pdb_reader *r) { int err =3D 0; PDB_SYMBOLS *symbols; - PDB_STREAM_INDEXES *sidx =3D &r->sidx; - - memset(sidx, -1, sizeof(*sidx)); =20 symbols =3D pdb_ds_read_file(r, 3); if (!symbols) { @@ -188,15 +185,11 @@ static int pdb_init_symbols(struct pdb_reader *r) =20 r->symbols =3D symbols; =20 - if (symbols->stream_index_size !=3D sizeof(PDB_STREAM_INDEXES)) { - err =3D 1; - goto out_symbols; - } - - memcpy(sidx, (const char *)symbols + sizeof(PDB_SYMBOLS) + + r->segments =3D *(uint16_t *)((const char *)symbols + sizeof(PDB_SYMBO= LS) + symbols->module_size + symbols->offset_size + symbols->hash_size + symbols->srcmodule_size + - symbols->pdbimport_size + symbols->unknown2_size, sizeof(*sidx= )); + symbols->pdbimport_size + symbols->unknown2_size + + offsetof(PDB_STREAM_INDEXES, segments)); =20 /* Read global symbol table */ r->modimage =3D pdb_ds_read_file(r, symbols->gsym_file); --=20 2.34.1