From nobody Sat May 18 06:31:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695245963; cv=none; d=zohomail.com; s=zohoarc; b=M2wGu3xvcg6YZimn20ek4ndOfZCdMIiv5nmGIlzED7i9kyU+tjXOW5q+v31CafKrcZgAks2Dy+HYaQSrst4ddidDE00ileZ052NSKxVRcN1e6jKqxvkDD9N39wkk+G4t1a9J0u8kedUvtiqIJIDoDNRJoaTWMBWBVWX+V3qaBz4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695245963; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wuGegwgck8ZEFasbqFPHbzSlisDssAI2uj1gevUmTVY=; b=CkHqUMcolWp/xI7GkhkbxhAbfH6LxGw5ifDrnD66ImxIKzafwQtqLWJmLAFA8iWGC84wmIch8p/TSWmjz3f5XWL19LlS7+1I/lJyQQAHvo28RnU9xShUflw6L//rDmyrvS3MT139+U2iCcaGvQ6qnhxFsoKZpl6VKjlFQEmMJYk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695245963680950.707771949434; Wed, 20 Sep 2023 14:39:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qj4tS-0004yP-BR; Wed, 20 Sep 2023 17:37:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qj4tQ-0004xh-DV for qemu-devel@nongnu.org; Wed, 20 Sep 2023 17:37:56 -0400 Received: from mail-ot1-x333.google.com ([2607:f8b0:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qj4tO-0006UY-Ro for qemu-devel@nongnu.org; Wed, 20 Sep 2023 17:37:56 -0400 Received: by mail-ot1-x333.google.com with SMTP id 46e09a7af769-6bc9c01e154so768065a34.0 for ; Wed, 20 Sep 2023 14:37:54 -0700 (PDT) Received: from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id e1-20020a9d7301000000b006b83a36c08bsm64415otk.53.2023.09.20.14.37.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 14:37:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695245873; x=1695850673; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wuGegwgck8ZEFasbqFPHbzSlisDssAI2uj1gevUmTVY=; b=CJNTg+XIarrDxpOvJpzkF1L82ZlAPQcXd/ztUufOEMpPguc0lmsYWxLqiFTD2bSI56 Jar6LV8XRntEw6olWxi2z5LsYBKmc4pl2btHBISB0JzC4QIObvYcC2aFmAb/U7rSM4si +f1LKmORmf5ezYj2YUBkHU7PWRfoFy8IXhdTzyaf+L/OPbeAVd9Ke5HfyxorY9/US2BU WQDVicM7Pq7YeGM0RdLTOwm3l2x2DhF8/ELWL2W3Ieuz4iT8eKKyGsIwNoYBbKeLXQ1G 82UHEPEa4KybxJwvn2ILUXA5mU9mIOoIs/1VlkGWU1B9BNzgALLkLUnN9coxPY8KvkRf SMYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695245873; x=1695850673; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wuGegwgck8ZEFasbqFPHbzSlisDssAI2uj1gevUmTVY=; b=JLT1lVCu3pJzUAcN8MxAdANVXJDAF/xas87vVXWm4hWZnlPUAZFmghXaCnbEmi1EWn SdiCiJROlgFrlTi0HjVP9gP28MKE3UCYQfTM1YPC6kxs2IE1nWi52eM5/pV9VdWXYH/l AAjpt0Qxf8S01fQa/TSD7/dQmHXFGujV/lL0y03y2CU7fGeLYmgTT3Cy1yRK3OYhjP7h vZaQPJZ4Oy3sAFkc9OjYcqhf60T4Fjc2m8z3/NHWxis1R6EcxOEB5j70w8TQc4v2sdTe zmwUkfYxXhSM0PbI9MDdDTb0Q/zwuQLn1G2vo3gdQ+aX6nBU6XpWxEDZ1A1LxNIqe4zL XyzA== X-Gm-Message-State: AOJu0Yyf75X82Fz9ADlMdb9KTOQvU0Ql7xfvFXPAjob3ox5+z5R/CwBo OK5IKrNjbGh6Ko22S4EoziFt35gEvGGOPt6rJ+8= X-Google-Smtp-Source: AGHT+IE0FQIXsImOFGvdL0B26UMsqCNheb/XWcMEh7MnJ0IcUpMYaEqRIDBvuLIdFjNOE6P/XcgBLg== X-Received: by 2002:a05:6808:1a16:b0:3aa:1306:96e8 with SMTP id bk22-20020a0568081a1600b003aa130696e8mr4620035oib.1.1695245873364; Wed, 20 Sep 2023 14:37:53 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 1/8] target/riscv: add riscv_cpu_get_name() Date: Wed, 20 Sep 2023 18:37:36 -0300 Message-ID: <20230920213743.716265-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920213743.716265-1-dbarboza@ventanamicro.com> References: <20230920213743.716265-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695245965485100011 Content-Type: text/plain; charset="utf-8" We'll introduce generic errors that will output a CPU type name via its RISCVCPU pointer. Create a helper for that. Use the helper in tcg_cpu_realizefn() instead of hardcoding the 'host' CPU name. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 11 +++++++++++ target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 4 +++- 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eeeb08a35a..521bb88538 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -643,6 +643,17 @@ static ObjectClass *riscv_cpu_class_by_name(const char= *cpu_model) return oc; } =20 +char *riscv_cpu_get_name(RISCVCPU *cpu) +{ + RISCVCPUClass *rcc =3D RISCV_CPU_GET_CLASS(cpu); + const char *typename =3D object_class_get_name(OBJECT_CLASS(rcc)); + + g_assert(g_str_has_suffix(typename, RISCV_CPU_TYPE_SUFFIX)); + + return g_strndup(typename, + strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX)); +} + static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) { RISCVCPU *cpu =3D RISCV_CPU(cs); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 219fe2e9b5..3f11e69223 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -730,6 +730,7 @@ typedef struct isa_ext_data { int ext_enable_offset; } RISCVIsaExtData; extern const RISCVIsaExtData isa_edata_arr[]; +char *riscv_cpu_get_name(RISCVCPU *cpu); =20 void riscv_add_satp_mode_properties(Object *obj); =20 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 8c052d6fcd..f31aa9bcc4 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -563,7 +563,9 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **err= p) Error *local_err =3D NULL; =20 if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { - error_setg(errp, "'host' CPU is not compatible with TCG accelerati= on"); + g_autofree char *name =3D riscv_cpu_get_name(cpu); + error_setg(errp, "'%s' CPU is not compatible with TCG acceleration= ", + name); return false; } =20 --=20 2.41.0 From nobody Sat May 18 06:31:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695245940; cv=none; d=zohomail.com; s=zohoarc; b=KIFC/qU1d5DrdW2F9OdcSRgVFPevpi36JIxXOyuxomUU2XchfnIyvfBPR2fJ+4+rPE8PFJppYY6lhGLTgjsMGFKPHoB86aCkD8jhyYmCoC8Um0AdmIJovEax9o1N5iy2aVUYL1E0XKY+7tdHADwwtFxwANJYWJDFJlpgTjV1Iaw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695245940; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cv6lw/UDU2mmgm0nArWAGoChrZBEcccRRUUgz2CCcZg=; b=PNggmHYdgWnBr3W3doAmYhlATNRUEmgpASgLxcLcifbt4/oEKyab+0iFR9pmTizDiRLa0vBcNKx6aeXvK30tCmTaxpqJBIbaaOtA6jYuUsVOHaG4NxFYBEuCtHkLUEoXFDEM7MAHaPvcDkgoQSoMvy5O1YPs+QMe0uDLpRUgZkc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695245940799251.81928327111427; Wed, 20 Sep 2023 14:39:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qj4tV-000517-3m; Wed, 20 Sep 2023 17:38:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qj4tT-0004zF-Pr for qemu-devel@nongnu.org; Wed, 20 Sep 2023 17:37:59 -0400 Received: from mail-ot1-x335.google.com ([2607:f8b0:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qj4tR-0006VH-V5 for qemu-devel@nongnu.org; Wed, 20 Sep 2023 17:37:59 -0400 Received: by mail-ot1-x335.google.com with SMTP id 46e09a7af769-6c21b2c6868so208625a34.1 for ; Wed, 20 Sep 2023 14:37:57 -0700 (PDT) Received: from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id e1-20020a9d7301000000b006b83a36c08bsm64415otk.53.2023.09.20.14.37.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 14:37:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695245876; x=1695850676; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cv6lw/UDU2mmgm0nArWAGoChrZBEcccRRUUgz2CCcZg=; b=lnhfZgVKUqAQZqDFjs9vPNRfHGPQY75g5IF2dGATAvVt15adCVpvbCjrF9diPPWffF okGCzTFBgaTLLqge5fn9bqkd9reOvejK1iTorn+Z1PzmDJaSrdv2n6F2HhfAHCPlOGod UPrKtkpCxscgH5N/rUX7EeiYZJwDtvlxpB6SkqlGTa465Pfb6sddFzt8Zx04girOzBw0 XB4ysJ6+PtZLdG4k7uUx9lAZnaciD2mKY/iTXEvovqmxjMYwEXMGtjq7OxasBSR/x0C5 0N1MvvVzMnJiML5wwNJ9qOQqMWFps3U3Y6h5KWiDlEq3Mk7wdAfFTEiWQ67KpVrpasP1 mCXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695245876; x=1695850676; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cv6lw/UDU2mmgm0nArWAGoChrZBEcccRRUUgz2CCcZg=; b=C35C5/rmVaZ88slZZIqcg8Vg1lR8XFWMhjzunNfNhc93cCMwx8ca4I3LOKmWXtJy8s hfSFWDjHr0z8s0NjTK1ukdURlhB1EqGqpkGx7eTzLl6ItoHZ9QcztL+Tub0hzmCCLIrU GEH/sb2iiEiU08e1S2V/FMo4AseRsf3Z8jd0yGeRUOV5eIEDqqxDowIFBLURpyhqgsgM OxYmRbNbFUXNnmmM50d5o/4hDyaqxujjdf/vOHMROwmVN1dtm1XDJleciM53nFAKcNHE SB+5AT99FEtxgILdwpgtCUOH3rlEAvz4IEA4+0s2dQU2+sZUOd8ooO4Y2wnW7IeCDDpQ 0O0w== X-Gm-Message-State: AOJu0Yybd9/6kmi8Yumrj5JkS3s6Z66/laE/TSpkW48DVsSDi8V/S1a4 5/X55W/Hz/5vHYhmi8TpfeLAdnouray9lXFg5wo= X-Google-Smtp-Source: AGHT+IGH1U2Cl3nF73fVy93IXIruHU5PN1D7cKqZPa9DPdoMSGfrKsFskZ5J4NzYNkjElOecH2P/xw== X-Received: by 2002:a05:6830:128d:b0:6b9:c49f:1af7 with SMTP id z13-20020a056830128d00b006b9c49f1af7mr3930933otp.20.1695245876254; Wed, 20 Sep 2023 14:37:56 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 2/8] target/riscv/tcg-cpu.c: add extension properties for all cpus Date: Wed, 20 Sep 2023 18:37:37 -0300 Message-ID: <20230920213743.716265-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920213743.716265-1-dbarboza@ventanamicro.com> References: <20230920213743.716265-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695245942502100004 Content-Type: text/plain; charset="utf-8" At this moment we do not expose extension properties for vendor CPUs because that would allow users to change them via command line. But that comes at a cost: if we were to add an API that shows all CPU properties, e.g. qmp-query-cpu-model-expansion, we won't be able to show the extension state of vendor CPUs. We have the required machinery to create extension properties for vendor CPUs while not allowing users to enable extensions. Disabling existing extensions is allowed since it can be useful for debugging. Change the set() callback cpu_set_multi_ext_cfg() to allow enabling extensions only for generic CPUs. In cpu_add_multi_ext_prop() let's not set the default values for the properties if we're not dealing with generic CPUs, otherwise the values set in cpu_init() of vendor CPUs will be overwritten. And finally, in tcg_cpu_instance_init(), add cpu user properties for all CPUs. For the veyron-v1 CPU, we're now able to disable existing extensions like smstateen: $ ./build/qemu-system-riscv64 --nographic -M virt \ -cpu veyron-v1,smstateen=3Dfalse But setting extensions that the CPU didn't set during cpu_init(), like V, is not allowed: $ ./build/qemu-system-riscv64 --nographic -M virt \ -cpu veyron-v1,v=3Dtrue qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.v=3Dtrue: 'veyron-v1' CPU does not allow enabling extensions Signed-off-by: Daniel Henrique Barboza --- target/riscv/tcg/tcg-cpu.c | 64 +++++++++++++++++++++++++++++--------- 1 file changed, 50 insertions(+), 14 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f31aa9bcc4..a90ee63b06 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -549,6 +549,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) riscv_cpu_disable_priv_spec_isa_exts(cpu); } =20 +static bool riscv_cpu_is_generic(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; +} + /* * We'll get here via the following path: * @@ -632,13 +637,27 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor= *v, const char *name, target_ulong misa_bit =3D misa_ext_cfg->misa_bit; RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - bool value; + bool generic_cpu =3D riscv_cpu_is_generic(obj); + bool prev_val, value; =20 if (!visit_type_bool(v, name, &value, errp)) { return; } =20 + prev_val =3D env->misa_ext & misa_bit; + + if (value =3D=3D prev_val) { + return; + } + if (value) { + if (!generic_cpu) { + g_autofree char *cpuname =3D riscv_cpu_get_name(cpu); + error_setg(errp, "'%s' CPU does not allow enabling extensions", + cpuname); + return; + } + env->misa_ext |=3D misa_bit; env->misa_ext_mask |=3D misa_bit; } else { @@ -688,6 +707,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { + bool use_def_vals =3D riscv_cpu_is_generic(cpu_obj); int i; =20 for (i =3D 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { @@ -706,7 +726,9 @@ static void riscv_cpu_add_misa_properties(Object *cpu_o= bj) cpu_set_misa_ext_cfg, NULL, (void *)misa_cfg); object_property_set_description(cpu_obj, name, desc); - object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL); + if (use_def_vals) { + object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NUL= L); + } } } =20 @@ -714,17 +736,32 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visito= r *v, const char *name, void *opaque, Error **errp) { const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; - bool value; + RISCVCPU *cpu =3D RISCV_CPU(obj); + bool generic_cpu =3D riscv_cpu_is_generic(obj); + bool prev_val, value; =20 if (!visit_type_bool(v, name, &value, errp)) { return; } =20 - isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value); - g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(multi_ext_cfg->offset), (gpointer)value); + + prev_val =3D isa_ext_is_enabled(cpu, multi_ext_cfg->offset); + + if (value =3D=3D prev_val) { + return; + } + + if (value && !generic_cpu) { + g_autofree char *cpuname =3D riscv_cpu_get_name(cpu); + error_setg(errp, "'%s' CPU does not allow enabling extensions", + cpuname); + return; + } + + isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); } =20 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, @@ -739,11 +776,17 @@ static void cpu_get_multi_ext_cfg(Object *obj, Visito= r *v, const char *name, static void cpu_add_multi_ext_prop(Object *cpu_obj, const RISCVCPUMultiExtConfig *multi_cfg) { + bool generic_cpu =3D riscv_cpu_is_generic(cpu_obj); + object_property_add(cpu_obj, multi_cfg->name, "bool", cpu_get_multi_ext_cfg, cpu_set_multi_ext_cfg, NULL, (void *)multi_cfg); =20 + if (!generic_cpu) { + return; + } + /* * Set def val directly instead of using * object_property_set_bool() to save the set() @@ -828,20 +871,13 @@ static bool riscv_cpu_has_max_extensions(Object *cpu_= obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) !=3D NULL; } =20 -static bool riscv_cpu_has_user_properties(Object *cpu_obj) -{ - return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; -} - static void tcg_cpu_instance_init(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); Object *obj =3D OBJECT(cpu); =20 - if (riscv_cpu_has_user_properties(obj)) { - multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); - riscv_cpu_add_user_properties(obj); - } + multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); + riscv_cpu_add_user_properties(obj); =20 if (riscv_cpu_has_max_extensions(obj)) { riscv_init_max_cpu_extensions(obj); --=20 2.41.0 From nobody Sat May 18 06:31:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695245969; cv=none; d=zohomail.com; s=zohoarc; b=DcdWHdiOvKI1WYKuhU8V/cK53LGwooXhqe781uRqNrGUnm8KL29EIEza5isbfU/fJQamgMJbPpyIL/g5xGPg07YaSH9TYmthi1Z4rSdkbwH8k2CV+op4IJheHQwdF124LPXkgFmXL/pZzdvSepeLRNSIJeacuPTnVnUUmafxQ1c= ARC-Message-Signature: i=1; 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id e1-20020a9d7301000000b006b83a36c08bsm64415otk.53.2023.09.20.14.37.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 14:37:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695245879; x=1695850679; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m97eKcYhxutpzHRkswwj8gKLRsf806rl8f4MNHOdJoo=; b=Z/orPlfORXiVQQFuoTtCJ9Pm8wGDUf3qD4+kJUaAaqs4sktI1i/rmteXqx9AQbH9O6 jMXsNF9acBnZPr5pzi1/KanwOqnlbaKjedGRP3nJfTK6v8PCTles2GI9TscN4dWbFaXp 3+afvVntP0rclbSG53OjzXfw30gR/TXHds88Anc6rz3xcX40hW4pzXBUffw/tQEUpphr UHT9hYIf6ZitX/Ujbf68kx/WiU9WLz5XScrV+O3HMqtX5A2OKpb/qJrkdCB8CJKmQKvl wyiO4cm2n8h4FbeDI2ajGRq6Vm9iAo7+MA7UmclrvNj2mvW8M9dbCeqg5MVHTzBUx0vd dMfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695245879; x=1695850679; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m97eKcYhxutpzHRkswwj8gKLRsf806rl8f4MNHOdJoo=; b=Jdp8uv5PIoR0KvYIaIsLBgX8OVlmoc+h2gUhafMzF1yrGLlQQlFbH+zs9bJsCut7+Y R52BPwrZQDPgtisP7uBCVi4ppPqoraZXA5t+sc2SzrQ4J3qRusHJA82BpEysUdv5lAlE vu/R3WWddh1Ds89PUkg1WupLK/CYTZXNsDHN0EPc5spNQVavWHP/jmlBg1q0G7mmW1R5 SvZWCO2fQ7Ofp0nWbKQ8YGWo/qThwqkRGxUL6T7zpW5pztjEtEL3cWcTS9g9YJ7oWW49 BN0SKzZfLz6O6JDvPtRT3rMDli6OSlWggMwhqh9DCSrV1oRDb75Ig6vaTSESPI4c0aDi jasQ== X-Gm-Message-State: AOJu0YxMiGB6Fr+WDuSCiguaLX1KXOFIX+f5qZ0DLX7pyk/GLyH89P7d p2h7XYLAEluE4TqGReIQgjewAXOIrCJpOaF4vZE= X-Google-Smtp-Source: AGHT+IGLTEZg/5Sfg+80fwR0tsb7jfVM/dQjz37uyZEVZWfO14MX3sUnh5byC/XkQMIcMYjt61q9CQ== X-Received: by 2002:a05:6830:1d85:b0:6b8:6a83:2b17 with SMTP id y5-20020a0568301d8500b006b86a832b17mr4039342oti.33.1695245879133; Wed, 20 Sep 2023 14:37:59 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 3/8] target/riscv/kvm/kvm-cpu.c: add missing property getters() Date: Wed, 20 Sep 2023 18:37:38 -0300 Message-ID: <20230920213743.716265-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920213743.716265-1-dbarboza@ventanamicro.com> References: <20230920213743.716265-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695245971351100001 Content-Type: text/plain; charset="utf-8" We got along without property getters in the KVM driver because we never needed them. But the incoming query-cpu-model-expansion API will use property getters and setters to retrieve the CPU characteristics. Add the missing getters for the KVM driver for both MISA and multi-letter extension properties. We're also adding an special getter for absent multi-letter properties that KVM doesn't implement that always return false. Signed-off-by: Daniel Henrique Barboza --- target/riscv/kvm/kvm-cpu.c | 40 +++++++++++++++++++++++++++++++++++--- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index c6615cb807..b4c231f231 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -140,6 +140,19 @@ static KVMCPUConfig kvm_misa_ext_cfgs[] =3D { KVM_MISA_CFG(RVM, KVM_RISCV_ISA_EXT_M), }; =20 +static void kvm_cpu_get_misa_ext_cfg(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **errp) +{ + KVMCPUConfig *misa_ext_cfg =3D opaque; + target_ulong misa_bit =3D misa_ext_cfg->offset; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + bool value =3D env->misa_ext_mask & misa_bit; + + visit_type_bool(v, name, &value, errp); +} + static void kvm_cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) @@ -244,6 +257,17 @@ static uint32_t kvm_cpu_cfg_get(RISCVCPU *cpu, return *ext_enabled; } =20 +static void kvm_cpu_get_multi_ext_cfg(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **errp) +{ + KVMCPUConfig *multi_ext_cfg =3D opaque; + RISCVCPU *cpu =3D RISCV_CPU(obj); + bool value =3D kvm_cpu_cfg_get(cpu, multi_ext_cfg); + + visit_type_bool(v, name, &value, errp); +} + static void kvm_cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) @@ -346,6 +370,15 @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU = *cpu, CPUState *cs) } } =20 +static void cpu_get_cfg_unavailable(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **errp) +{ + bool value =3D false; + + visit_type_bool(v, name, &value, errp); +} + static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) @@ -376,7 +409,8 @@ static void riscv_cpu_add_kvm_unavail_prop(Object *obj,= const char *prop_name) * to enable any of them. */ object_property_add(obj, prop_name, "bool", - NULL, cpu_set_cfg_unavailable, + cpu_get_cfg_unavailable, + cpu_set_cfg_unavailable, NULL, (void *)prop_name); } =20 @@ -406,7 +440,7 @@ static void kvm_riscv_add_cpu_user_properties(Object *c= pu_obj) misa_cfg->description =3D riscv_get_misa_ext_description(bit); =20 object_property_add(cpu_obj, misa_cfg->name, "bool", - NULL, + kvm_cpu_get_misa_ext_cfg, kvm_cpu_set_misa_ext_cfg, NULL, misa_cfg); object_property_set_description(cpu_obj, misa_cfg->name, @@ -422,7 +456,7 @@ static void kvm_riscv_add_cpu_user_properties(Object *c= pu_obj) KVMCPUConfig *multi_cfg =3D &kvm_multi_ext_cfgs[i]; =20 object_property_add(cpu_obj, multi_cfg->name, "bool", - NULL, + kvm_cpu_get_multi_ext_cfg, kvm_cpu_set_multi_ext_cfg, NULL, multi_cfg); } --=20 2.41.0 From nobody Sat May 18 06:31:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695245961; cv=none; d=zohomail.com; s=zohoarc; b=CbJV7CNVaThDvdj0n70cEtcJBbY+rSL8RI3O8lvlqGEI2lAmzZJPVdZ6CuowNLy7ahntSiTnoMqJEY5G3gobn6RA5/4bQ5/HTztPPok39TWdwp4vWDR9N08C5kvkl3bFsd/S34ogDs6Yp6H86kZ4as9V4vquGIrISucvpjaiiDs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695245961; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=V0XSgeSJnnKLgredxyHN7Vr6x9UEJtXe7wlJUBcuLMY=; b=Tt/VupwLJeZO6hApwyQJq8R2+UvWr/FKkWxgXmjYTjtbWkJCLfmmIf8XKAYD0x9IJl30kLh0AT+0AG8SmbGLrX2IdsdK5YFHU+rJWhCS6U28lWs/HmkQ0bxA4drUmxk9tt2Q+81YN21UpJ8uI+Aefk25d72PE8du24nJXmZr2Wk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695245961149126.18167964628094; Wed, 20 Sep 2023 14:39:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qj4tb-00054K-8r; Wed, 20 Sep 2023 17:38:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qj4ta-000546-Gh for qemu-devel@nongnu.org; Wed, 20 Sep 2023 17:38:06 -0400 Received: from mail-ot1-x32a.google.com ([2607:f8b0:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qj4tX-0006WP-RA for qemu-devel@nongnu.org; Wed, 20 Sep 2023 17:38:06 -0400 Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-6c0c6370e5eso198585a34.3 for ; Wed, 20 Sep 2023 14:38:03 -0700 (PDT) Received: from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id e1-20020a9d7301000000b006b83a36c08bsm64415otk.53.2023.09.20.14.37.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 14:38:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695245882; x=1695850682; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V0XSgeSJnnKLgredxyHN7Vr6x9UEJtXe7wlJUBcuLMY=; b=FmViiTuiCebDl/Tma63NHbiSMUzU3W16OhUJJ0usxTl9GyY2nQ9DY0FxGP1w0FT4jz RSaB8Rre49P+Xbxc6J5fgGmnPWoJIYgQkPJnKJ1qVtM/tu6I/2FFEna89iewQ0UHAO09 ZtnLZ2X41Zwt+VAV0QlJMWVrmD/ibgItNYLEuKu6T68zgEIa5ck9cGRaAdJogmGExwS1 YPYIT4qFVxXZxgJ4RrDSLxqSkcaud4v8ZVQvY7pLKs6wDjwop5kbDB9RtjDBZfergTmU g5hBxoKso+jLgJUHpxQRu8GwW+RgzkV8Dhl6k8nf9yFGXSL1QzBj7EXomCfah+w/li83 PEaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695245882; x=1695850682; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V0XSgeSJnnKLgredxyHN7Vr6x9UEJtXe7wlJUBcuLMY=; b=P1Gt5lZ3n4koFo8GwzZngd4oMDw7zZ9Ly04+qVALBmP+sJeFvPhhUiU0+dSP5e8NYP HpT5GcBjVt3mt8sz9Gn+2gO9HynylSgpvUhp3F8JZxPF0CBFsdzrEzcnY3DIG4Cv5nsr Bw1NQFGxRRgD2zXwvP/hg6VeNGGabWlEGnjDd9tl4UYq5U5itKTUW0kXuTyjIQL+l+Kl McrdpQSkNlgzFKodWQnDV1IaUnxF8pqUV0TAqIhjNV22TMGuDrIk2zFR6l903/kMOgVE xNkZNcHVuymyTgk8yHQp4l6b/dN8S2BagBba9VsmglQh5pGY734gs8pvJgb6L986z5qS AjlQ== X-Gm-Message-State: AOJu0YxKXxjbcw7DfSduXc66CnjJtdo7VuC9NcZ9RfDRgDXQbvNJPHzQ N/ri5nELfpG1QjeuKPxE8a1rNpPaE3QJgUdhv2U= X-Google-Smtp-Source: AGHT+IEzzchsRo2mkFhzasTHKIvUveQEsbVx4lcK/6d8ZKkKOotGhrfi2itMXitBKEw2lSt94+zkFA== X-Received: by 2002:a05:6830:18ee:b0:6bf:f75:1ad6 with SMTP id d14-20020a05683018ee00b006bf0f751ad6mr4189872otf.26.1695245882284; Wed, 20 Sep 2023 14:38:02 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 4/8] qapi,risc-v: add query-cpu-model-expansion Date: Wed, 20 Sep 2023 18:37:39 -0300 Message-ID: <20230920213743.716265-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920213743.716265-1-dbarboza@ventanamicro.com> References: <20230920213743.716265-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695245962133100005 Content-Type: text/plain; charset="utf-8" This API is used to inspect the characteristics of a given CPU model. It also allows users to validate a CPU model with a certain configuration, e.g. if "-cpu X,a=3Dtrue,b=3Dfalse" is a valid setup for a given QEMU binary. We'll start implementing the first part. The second requires more changes in RISC-V CPU boot flow. The implementation is inspired by the existing ARM query-cpu-model-expansion impl in target/arm/arm-qmp-cmds.c. We'll create a RISCVCPU object with the required model, fetch its existing properties, add a couple of relevant boolean options (pmp and mmu) and display it to users. Here's an usage example: ./build/qemu-system-riscv64 -S -M virt -display none \ -qmp tcp:localhost:1234,server,wait=3Doff ./scripts/qmp/qmp-shell localhost:1234 Welcome to the QMP low-level shell! Connected to QEMU 8.1.50 (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"rv64"} {"return": {"model": {"name": "rv64", "props": {"zicond": false, "x-zvfh": = false, "mmu": true, "x-zvfbfwma": false, "x-zvfbfmin": false, "xtheadbs": f= alse, "xtheadbb": false, "xtheadba": false, "xtheadmemidx": false, "smstate= en": false, "zfinx": false, "Zve64f": false, "Zve32f": false, "x-zvfhmin": = false, "xventanacondops": false, "xtheadcondmov": false, "svpbmt": false, "= zbs": true, "zbc": true, "zbb": true, "zba": true, "zicboz": true, "xtheadm= ac": false, "Zfh": false, "Zfa": true, "zbkx": false, "zbkc": false, "zbkb"= : false, "Zve64d": false, "x-zfbfmin": false, "zk": false, "x-epmp": false,= "xtheadmempair": false, "zkt": false, "zks": false, "zkr": false, "zkn": f= alse, "Zfhmin": false, "zksh": false, "zknh": false, "zkne": false, "zknd":= false, "zhinx": false, "Zicsr": true, "sscofpmf": false, "Zihintntl": true= , "sstc": true, "xtheadcmo": false, "x-zvbb": false, "zksed": false, "x-zvk= ned": false, "xtheadsync": false, "x-zvkg": false, "zhinxmin": false, "svad= u": true, "xtheadfmv": false, "x-zvksed": false, "svnapot": false, "pmp": t= rue, "x-zvknhb": false, "x-zvknha": false, "xtheadfmemidx": false, "x-zvksh= ": false, "zdinx": false, "zicbom": true, "Zihintpause": true, "svinval": f= alse, "zcf": false, "zce": false, "zcd": false, "zcb": false, "zca": false,= "x-ssaia": false, "x-smaia": false, "zmmul": false, "x-zvbc": false, "Zife= ncei": true, "zcmt": false, "zcmp": false, "Zawrs": true}}}} Signed-off-by: Daniel Henrique Barboza --- qapi/machine-target.json | 6 ++- target/riscv/riscv-qmp-cmds.c | 75 +++++++++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+), 2 deletions(-) diff --git a/qapi/machine-target.json b/qapi/machine-target.json index f0a6b72414..e5630e73aa 100644 --- a/qapi/machine-target.json +++ b/qapi/machine-target.json @@ -228,7 +228,8 @@ 'data': { 'model': 'CpuModelInfo' }, 'if': { 'any': [ 'TARGET_S390X', 'TARGET_I386', - 'TARGET_ARM' ] } } + 'TARGET_ARM', + 'TARGET_RISCV' ] } } =20 ## # @query-cpu-model-expansion: @@ -273,7 +274,8 @@ 'returns': 'CpuModelExpansionInfo', 'if': { 'any': [ 'TARGET_S390X', 'TARGET_I386', - 'TARGET_ARM' ] } } + 'TARGET_ARM', + 'TARGET_RISCV' ] } } =20 ## # @CpuDefinitionInfo: diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index 5ecff1afb3..2170562e3a 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -24,8 +24,12 @@ =20 #include "qemu/osdep.h" =20 +#include "qapi/error.h" #include "qapi/qapi-commands-machine-target.h" +#include "qapi/qmp/qdict.h" +#include "qom/qom-qobject.h" #include "cpu-qom.h" +#include "cpu.h" =20 static void riscv_cpu_add_definition(gpointer data, gpointer user_data) { @@ -55,3 +59,74 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error *= *errp) =20 return cpu_list; } + +static void riscv_obj_add_qdict_prop(Object *obj, QDict *qdict_out, + const char *name) +{ + ObjectProperty *prop =3D object_property_find(obj, name); + + if (prop) { + QObject *value; + + assert(prop->get); + value =3D object_property_get_qobject(obj, name, &error_abort); + + qdict_put_obj(qdict_out, name, value); + } +} + +static void riscv_obj_add_multiext_props(Object *obj, QDict *qdict_out, + const RISCVCPUMultiExtConfig *arr) +{ + for (int i =3D 0; arr[i].name !=3D NULL; i++) { + riscv_obj_add_qdict_prop(obj, qdict_out, arr[i].name); + } +} + +CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType= type, + CpuModelInfo *model, + Error **errp) +{ + CpuModelExpansionInfo *expansion_info; + QDict *qdict_out; + ObjectClass *oc; + Object *obj; + + if (type !=3D CPU_MODEL_EXPANSION_TYPE_FULL) { + error_setg(errp, "The requested expansion type is not supported"); + return NULL; + } + + oc =3D cpu_class_by_name(TYPE_RISCV_CPU, model->name); + if (!oc) { + error_setg(errp, "The CPU type '%s' is not a known RISC-V CPU type= ", + model->name); + return NULL; + } + + obj =3D object_new(object_class_get_name(oc)); + + expansion_info =3D g_new0(CpuModelExpansionInfo, 1); + expansion_info->model =3D g_malloc0(sizeof(*expansion_info->model)); + expansion_info->model->name =3D g_strdup(model->name); + + qdict_out =3D qdict_new(); + + riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_extensions); + riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_experimental_ex= ts); + riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_vendor_exts); + + /* Add our CPU boolean options too */ + riscv_obj_add_qdict_prop(obj, qdict_out, "mmu"); + riscv_obj_add_qdict_prop(obj, qdict_out, "pmp"); + + if (!qdict_size(qdict_out)) { + qobject_unref(qdict_out); + } else { + expansion_info->model->props =3D QOBJECT(qdict_out); + } + + object_unref(obj); + + return expansion_info; +} --=20 2.41.0 From nobody Sat May 18 06:31:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id e1-20020a9d7301000000b006b83a36c08bsm64415otk.53.2023.09.20.14.38.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 14:38:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695245885; x=1695850685; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nEmwZ9vMlhj3Ze5psNqYIbXyqepgesAeFvMZiBAsj+4=; b=NnW8xNju4nvONb4FXdMMiFLlFq03mlHrhhhfn2F3p16J2BWSvL29czD/GcfYvnP2Cu /dW/5Zckaar3hFI+kuColmB5Kfz6hT7hCxyLz3vpp/dYkWnjUAFkHFBdsMQ+A0MC9qFy oLLZIA3pak+/cBB5ajZnkQTskrZo9zKOFdGq/6+WAFnKkIgqdE6GECOBDjtvKQW8K5f4 Y3jnPVTZKIMsfcz0Ny0T6DrQcQOswrRxnNYpj3QNLxy7DBBgCQMxNu1QJiaFBHqyzn0Z dloRblcc0k2W9oIyEtQmCkC/ObtHvTaORSDDN6UfQrO1tQPnaKW1P2Fmj6PuzONNNasP zYFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695245885; x=1695850685; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nEmwZ9vMlhj3Ze5psNqYIbXyqepgesAeFvMZiBAsj+4=; b=nZkWKOgdJ7l/Q0ox4pMM/LkvH/ScUljZHeRcIrzLvqrLgDnSjCoHt5vbUI45GFmuLp 6VAVwhBMxEQJtnpE08WuZ4khGkToMJ+9jtmB5CvgbJ+nE1DLeUDyGnm4mZ4Pd/ieEkbE sTuiMQV4X/CnmMLPHD/ArI9lf+O3IS0nxBX+xQgafQUR/KLtkGUjXbV4x9azPFl3QECD aHjyL6xo7LzRfIE1BtOjtaQTEZHPv7A1q6GU2za85UA4ojULezjM45ia21+ycE0RsYRF +0yusNH9TIR6DdldHvDY1yZCOu/M34T0Z+8rMozH8S+VnrkiTduahcizjqI7vzjuhYM7 6PCQ== X-Gm-Message-State: AOJu0Ywdm00y9UnixO58Y+dKgmj/p7rQjT6oP0ZnygsffQH5JxZ6Pf02 6+nIxX0qM+QnEbVmQs1HkGRyQODTrpP8QWOEcts= X-Google-Smtp-Source: AGHT+IHIL609JKU+0zd48ptLpF20l/XE+KZTRSJ7xQIPQWspkM0Tkm2bmWNkp/1neyTvmrLnGd89BQ== X-Received: by 2002:a05:6830:181:b0:6b9:350e:4051 with SMTP id q1-20020a056830018100b006b9350e4051mr3641340ota.4.1695245885059; Wed, 20 Sep 2023 14:38:05 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 5/8] target/riscv/tcg: add tcg_cpu_finalize_features() Date: Wed, 20 Sep 2023 18:37:40 -0300 Message-ID: <20230920213743.716265-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920213743.716265-1-dbarboza@ventanamicro.com> References: <20230920213743.716265-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695245952077100003 Content-Type: text/plain; charset="utf-8" The query-cpu-model-expansion API is capable of passing extra properties to a given CPU model and tell callers if this custom configuration is valid. The RISC-V version of the API is not quite there yet. The reason is the realize() flow in the TCG driver, where most of the validation is done in tcg_cpu_realizefn(). riscv_cpu_finalize_features() is then used to validate satp_mode for both TCG and KVM CPUs. Our ARM friends uses a concept of 'finalize_features()', a step done in the end of realize() where the CPU features are validated. We have a riscv_cpu_finalize_features() helper that, at this moment, is only validating satp_mode. Re-use this existing helper to do all CPU extension validation we required after at the end of realize(). Make it public to allow APIs to use it. At this moment only the TCG driver requires a realize() time validation, thus, to avoid adding accelerator specific helpers in the API, riscv_cpu_finalize_features() uses riscv_tcg_cpu_finalize_features() if we are running TCG. The API will then use riscv_cpu_finalize_features() regardless of the current accelerator. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 18 +++++++++-- target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 61 +++++++++++++++++++++----------------- target/riscv/tcg/tcg-cpu.h | 1 + 4 files changed, 51 insertions(+), 30 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 521bb88538..272baaf6c7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -34,6 +34,7 @@ #include "sysemu/kvm.h" #include "sysemu/tcg.h" #include "kvm/kvm_riscv.h" +#include "tcg/tcg-cpu.h" #include "tcg/tcg.h" =20 /* RISC-V CPU definitions */ @@ -996,11 +997,24 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cp= u, Error **errp) } #endif =20 -static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) +void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) { -#ifndef CONFIG_USER_ONLY Error *local_err =3D NULL; =20 + /* + * KVM accel does not have a specialized finalize() + * callback because its extensions are validated + * in the get()/set() callbacks of each property. + */ + if (tcg_enabled()) { + riscv_tcg_cpu_finalize_features(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + } + +#ifndef CONFIG_USER_ONLY riscv_cpu_satp_mode_finalize(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3f11e69223..1bfa3da55b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -732,6 +732,7 @@ typedef struct isa_ext_data { extern const RISCVIsaExtData isa_edata_arr[]; char *riscv_cpu_get_name(RISCVCPU *cpu); =20 +void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); void riscv_add_satp_mode_properties(Object *obj); =20 /* CSR function table */ diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index a90ee63b06..52cd87db0c 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -549,6 +549,39 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) riscv_cpu_disable_priv_spec_isa_exts(cpu); } =20 +void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + Error *local_err =3D NULL; + + riscv_cpu_validate_priv_spec(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + + riscv_cpu_validate_misa_priv(env, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + + if (cpu->cfg.epmp && !cpu->cfg.pmp) { + /* + * Enhanced PMP should only be available + * on harts with PMP support + */ + error_setg(errp, "Invalid configuration: EPMP requires PMP support= "); + return; + } + + riscv_cpu_validate_set_extensions(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } +} + static bool riscv_cpu_is_generic(Object *cpu_obj) { return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; @@ -564,7 +597,6 @@ static bool riscv_cpu_is_generic(Object *cpu_obj) static bool tcg_cpu_realizefn(CPUState *cs, Error **errp) { RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; =20 if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { @@ -580,33 +612,6 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **er= rp) return false; } =20 - riscv_cpu_validate_priv_spec(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return false; - } - - riscv_cpu_validate_misa_priv(env, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return false; - } - - if (cpu->cfg.epmp && !cpu->cfg.pmp) { - /* - * Enhanced PMP should only be available - * on harts with PMP support - */ - error_setg(errp, "Invalid configuration: EPMP requires PMP support= "); - return false; - } - - riscv_cpu_validate_set_extensions(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return false; - } - #ifndef CONFIG_USER_ONLY CPU(cs)->tcg_cflags |=3D CF_PCREL; =20 diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h index 630184759d..aa00fbc253 100644 --- a/target/riscv/tcg/tcg-cpu.h +++ b/target/riscv/tcg/tcg-cpu.h @@ -23,5 +23,6 @@ #include "cpu.h" =20 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); +void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp); 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id e1-20020a9d7301000000b006b83a36c08bsm64415otk.53.2023.09.20.14.38.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 14:38:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695245888; x=1695850688; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YZB/Eo7+yUhj7MB+Xte6Mc3Nr/qRQpQ36eJpX2OrNeA=; b=di1RTnWFvQEUD3dFceROBDGdDEE9ZbeTFJuDXVwt0t08ooAaH9enytF746QJMU0ao6 DqYFEfZoTEdMkQWBysR9NP+rpG9UPtqiM/ikIxLYumndY2ABfMJW12Fh85bcGEgq6yd0 hicn4YqMuNlEspUmMenUhITxkjZVcGhRbG97nd7dKGZKA899q6OAay0I8EkrvC8M4JV2 SNzAHQTcFiwAhe0vlR3NPpdglaGHgEFTJn332GCFIkt1diRpAK0aLDiNLp2UF86XXhHT nx1j6+vD2HiKqVl6vaRB1ASHAe3tP079G4i1nF/Hfg0NjQlVY/EnokLZd9fgFLe6veGF CH3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695245888; x=1695850688; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YZB/Eo7+yUhj7MB+Xte6Mc3Nr/qRQpQ36eJpX2OrNeA=; b=DqlW3jO6V/oXTmwC7JL/39hCYgbgj84QPD0LCZOPg5zK0Ow7zKbkF8b6GYx1cBf4dP SHDj1hICaS1oz0Gy69A3EbSMUYxcyBGyMRmCOMWE2v0BDcI+9trIkuntft7lfABbyg2p eoCwv9F/ttDneZfOhTrqbuc3mmEgiRpQ5zzi+OVTQb0pCKKrIqe1qLFHR5cwOP6iJ2z5 g10FEAot8k2r+j+03asND0lida51AX2kKtCUquD9S4PMGieAOcsjtYuxp05BRWyDGypr pSs7DRcQOHfwFlhcPOQAwkKb76CrIeIaNhGRg0/ev2JK+z9yRIv3ZNdwMG/Ccc8ajJQL F1Xw== X-Gm-Message-State: AOJu0YxWhGk/CpaVLGn35OzsaF8QgMaQMHSoLKk5eXbpQtWLsTC24oD1 On9WaTYnhjmJ9cuMFp8UJS1r3w/508mUdP9l+cc= X-Google-Smtp-Source: AGHT+IHA09yNF5sB1fGwLfJmr7d/3d2IkVuLDh+cYhvruCP+4rmdqw4nLgabx7EXJ9WH3MILTTfJWw== X-Received: by 2002:a9d:7487:0:b0:6b9:cba0:93a9 with SMTP id t7-20020a9d7487000000b006b9cba093a9mr3671811otk.31.1695245887982; Wed, 20 Sep 2023 14:38:07 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 6/8] target/riscv: handle custom props in qmp_query_cpu_model_expansion Date: Wed, 20 Sep 2023 18:37:41 -0300 Message-ID: <20230920213743.716265-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920213743.716265-1-dbarboza@ventanamicro.com> References: <20230920213743.716265-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695245959010100001 Content-Type: text/plain; charset="utf-8" Callers can add 'props' when querying for a cpu model expansion to see if a given CPU model supports a certain criteria, and what's the resulting CPU object. If we have 'props' to handle, gather it in a QDict and use the new riscv_cpuobj_validate_qdict_in() helper to validate it. This helper will add the custom properties in the CPU object and validate it using riscv_cpu_finalize_features(). Users will be aware of validation errors if any occur, if not a CPU object with 'props' will be returned. Here's an example with the veyron-v1 vendor CPU. Disabling vendor CPU extensions is allowed, assuming the final config is valid. Disabling 'smstateen' is a valid expansion: (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"veyron-v1","p= rops":{"smstateen":false}} {"return": {"model": {"name": "veyron-v1", "props": {"zicond": false, ..., = "smstateen": false, ...} But enabling extensions isn't allowed for vendor CPUs. E.g. enabling 'V' for the veyron-v1 CPU isn't allowed: (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"veyron-v1","p= rops":{"v":true}} {"error": {"class": "GenericError", "desc": "'veyron-v1' CPU does not allow= enabling extensions"}} Signed-off-by: Daniel Henrique Barboza --- target/riscv/riscv-qmp-cmds.c | 65 +++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index 2170562e3a..5b2d186c83 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -27,6 +27,9 @@ #include "qapi/error.h" #include "qapi/qapi-commands-machine-target.h" #include "qapi/qmp/qdict.h" +#include "qapi/qmp/qerror.h" +#include "qapi/qobject-input-visitor.h" +#include "qapi/visitor.h" #include "qom/qom-qobject.h" #include "cpu-qom.h" #include "cpu.h" @@ -83,14 +86,58 @@ static void riscv_obj_add_multiext_props(Object *obj, Q= Dict *qdict_out, } } =20 +static void riscv_cpuobj_validate_qdict_in(Object *obj, QObject *props, + const QDict *qdict_in, + Error **errp) +{ + const QDictEntry *qe; + Visitor *visitor; + Error *local_err =3D NULL; + + visitor =3D qobject_input_visitor_new(props); + if (!visit_start_struct(visitor, NULL, NULL, 0, &local_err)) { + goto err; + } + + for (qe =3D qdict_first(qdict_in); qe; qe =3D qdict_next(qdict_in, qe)= ) { + object_property_find_err(obj, qe->key, &local_err); + if (local_err) { + goto err; + } + + object_property_set(obj, qe->key, visitor, &local_err); + if (local_err) { + goto err; + } + } + + visit_check_struct(visitor, &local_err); + if (local_err) { + goto err; + } + + riscv_cpu_finalize_features(RISCV_CPU(obj), &local_err); + if (local_err) { + goto err; + } + + visit_end_struct(visitor, NULL); + +err: + error_propagate(errp, local_err); + visit_free(visitor); +} + CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType= type, CpuModelInfo *model, Error **errp) { CpuModelExpansionInfo *expansion_info; + const QDict *qdict_in =3D NULL; QDict *qdict_out; ObjectClass *oc; Object *obj; + Error *local_err =3D NULL; =20 if (type !=3D CPU_MODEL_EXPANSION_TYPE_FULL) { error_setg(errp, "The requested expansion type is not supported"); @@ -104,8 +151,26 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(C= puModelExpansionType type, return NULL; } =20 + if (model->props) { + qdict_in =3D qobject_to(QDict, model->props); + if (!qdict_in) { + error_setg(errp, QERR_INVALID_PARAMETER_TYPE, "props", "dict"); + return NULL; + } + } + obj =3D object_new(object_class_get_name(oc)); =20 + if (qdict_in) { + riscv_cpuobj_validate_qdict_in(obj, model->props, qdict_in, + &local_err); + if (local_err) { + error_propagate(errp, local_err); + object_unref(obj); + return NULL; + } + } + expansion_info =3D g_new0(CpuModelExpansionInfo, 1); expansion_info->model =3D g_malloc0(sizeof(*expansion_info->model)); expansion_info->model->name =3D g_strdup(model->name); --=20 2.41.0 From nobody Sat May 18 06:31:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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([177.94.42.59]) by smtp.gmail.com with ESMTPSA id e1-20020a9d7301000000b006b83a36c08bsm64415otk.53.2023.09.20.14.38.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 14:38:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695245891; x=1695850691; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JPhfOSWnkLU5mAYkYDZTdFs/AmMh6zDJgUbX9Hh0aqI=; b=h6MaQUBjTm8hoPjvqAu/3SRTjcSdr2VeXtOD84I2ZPL1LF+8l2XG1d0t67MHhZp9Zv bgrPOYdASzfNF/xi3wy8TG5ULzGaeX5iTh1hr+WbllrGQde7i2B+yXjQ6rOpJ5/kzneA WFNmuW/prEY8344uV2OaoqxOCRGhnkoTiEYE8nVYX7DP9IIaYMMVOFD6H6lueSWrkjyN rzCcdlpHEkt2bQvwq07/eCVAz+CrfK9pRrJ9n1KvqLjfEAwEnPV0tCik0cZ/dQ1pkkbw BQyCIxtEY0clXzYCVmJRplw0/aARmI993tkZnDamN++QTOQvVUGkUuyvnn2bUPMs2IBI oQSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695245891; x=1695850691; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JPhfOSWnkLU5mAYkYDZTdFs/AmMh6zDJgUbX9Hh0aqI=; b=JD7C+TXMbhaCxcbbFoh/t9PtPC0WqDnJx817FDKXKserGu1vDlO+BTSVOoAhUfav0x o3faSDkNmtt047y9s6Rlyvf3ECQhtjPBgraOzO4HHjupmPws55M7GPXvfB/JQHnxGIIp x8W+muNKR4wTlwyGya2MQNFoEPZM8ZdDVhXGzeszGxp0X5vs/J1uTnc4eP2qNl5AyAi9 5ROHo+aRaBeVL9hv9Le+kM5iVqnEDzJUI3A3PSYwnYn/cJKuClEHn2o3ZmVuOYXkclSo gn3l6ggsTnnPpbcJLvOKDoMDVtPbnQgvT5F9aKGB2MWs/i3hN8a5o9Vzx6v20oRbtlte zG6A== X-Gm-Message-State: AOJu0Ywupshc8CphMi7rRTf+T5KM9jCsH0umrBTf9TsrlVHTXyQpumOp Qa7unSky5CUXPZY9IBWwy0ZPLYpI45S0nvUSQEg= X-Google-Smtp-Source: AGHT+IFIE5fmxWsb3FJMWCSjJDrf9x7l4DmQoTjen455wyMSUD5aj5/uM/IOAaqPGiKYP5sz+JKL5Q== X-Received: by 2002:a05:6870:170a:b0:1d5:a377:f389 with SMTP id h10-20020a056870170a00b001d5a377f389mr2589488oae.22.1695245890893; Wed, 20 Sep 2023 14:38:10 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 7/8] target/riscv: add riscv_cpu_accelerator_compatible() Date: Wed, 20 Sep 2023 18:37:42 -0300 Message-ID: <20230920213743.716265-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920213743.716265-1-dbarboza@ventanamicro.com> References: <20230920213743.716265-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695245969159100003 Content-Type: text/plain; charset="utf-8" Add an API to check if a given CPU is compatible with the current accelerator. This will allow query-cpu-model-expansion to work properly in conditions where QEMU supports both accelerators (TCG and KVM), QEMU is then launched using TCG, and the API requests information about a KVM only CPU (e.g. 'host' CPU). KVM doesn't have such restrictions and, at least in theory, all CPUs models should work with KVM. We will revisit this API in case we decide to restrict the amount of KVM CPUs we support. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 9 +++++++++ target/riscv/cpu.h | 1 + target/riscv/tcg/tcg-cpu.c | 7 ++++++- target/riscv/tcg/tcg-cpu.h | 1 + 4 files changed, 17 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 272baaf6c7..8bdf6dbd5d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1061,6 +1061,15 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) mcc->parent_realize(dev, errp); } =20 +bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu) +{ + if (tcg_enabled()) { + return riscv_cpu_tcg_compatible(cpu); + } + + return true; +} + #ifndef CONFIG_USER_ONLY static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1bfa3da55b..00b0507b17 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -734,6 +734,7 @@ char *riscv_cpu_get_name(RISCVCPU *cpu); =20 void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); void riscv_add_satp_mode_properties(Object *obj); +bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); =20 /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 52cd87db0c..071a744a43 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -582,6 +582,11 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Er= ror **errp) } } =20 +bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) +{ + return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) =3D=3D NU= LL; +} + static bool riscv_cpu_is_generic(Object *cpu_obj) { return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; @@ -599,7 +604,7 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **err= p) RISCVCPU *cpu =3D RISCV_CPU(cs); Error *local_err =3D NULL; =20 - if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { + if (!riscv_cpu_tcg_compatible(cpu)) { g_autofree char *name =3D riscv_cpu_get_name(cpu); error_setg(errp, "'%s' CPU is not compatible with TCG acceleration= ", name); diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h index aa00fbc253..f7b32417f8 100644 --- a/target/riscv/tcg/tcg-cpu.h +++ b/target/riscv/tcg/tcg-cpu.h @@ -24,5 +24,6 @@ =20 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp); +bool riscv_cpu_tcg_compatible(RISCVCPU *cpu); =20 #endif --=20 2.41.0 From nobody Sat May 18 06:31:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695245971; cv=none; d=zohomail.com; s=zohoarc; b=JZ5auoYo5VXhXtaM0E/ATRf+p3aE5x868xRRCkNwxkmANSUmaEKXkDoukvIiy8no1V9dZZLCFUvETKyCmIICN2Pr+zLrlJ7ct7Cej4uRaS/gdNBPa8NBH2MhayBCEm6PjiJv2GtL+4cTf77jRolzGhZu9OAeb+KB0mJb5pt22QU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695245971; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Hx2unC6bkbnK4o1a4tu1Rh/59GQGOMC47WGlP68Q50I=; b=KtwRJc/KUSf3sHcgzlooXT65guW6rjv0GtIy3LKx4gg23jp8fhsMnb58xxlWjF/UIdq7TDMLlxVYR0ndvWoVPYA7L0ACRe/wroihVeF0wNuAVD/am3amJNpcxol3LjfUUAaFbApqlrEDaNSLDXxbUpYP0bGx79uQ+Fa1Vzti/YQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695245971591142.5869156307175; Wed, 20 Sep 2023 14:39:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qj4tm-0005Hx-6F; Wed, 20 Sep 2023 17:38:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qj4tk-0005HQ-In for qemu-devel@nongnu.org; Wed, 20 Sep 2023 17:38:16 -0400 Received: from mail-ot1-x335.google.com ([2607:f8b0:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qj4ti-0006Yp-Sn for qemu-devel@nongnu.org; Wed, 20 Sep 2023 17:38:16 -0400 Received: by mail-ot1-x335.google.com with SMTP id 46e09a7af769-6c21b2c6868so208755a34.1 for ; Wed, 20 Sep 2023 14:38:14 -0700 (PDT) Received: from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id e1-20020a9d7301000000b006b83a36c08bsm64415otk.53.2023.09.20.14.38.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 14:38:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695245893; x=1695850693; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hx2unC6bkbnK4o1a4tu1Rh/59GQGOMC47WGlP68Q50I=; b=Ld6q3iKVJPTOKUR9U4tViy3UA2xGMMcOFSiteNVZ6+C9MfN9Cq1YARuR/qI+q5gO2I gLf4S736QQh271VgSHb9W17wjuretX3ULNMuZ+TWOMTdGdNJexG1UuRuKxkmtwXgRgyB bplwfw6PmT6poPSQoo0cfr28X9QvFdnR3OxiXYQt8lZlQGencWzXyRPxyG0oPL/s1o4y S2vpscDNiqLq9eZOHKxOsKlfJyTWdX3rpDBXcz7vvCyJhJLJ59e7e6YM7z8i8UqQQszD 3ASOp9D2Sn+BhZNaZH5pvdZzrz+hi32I1h+tQmfMDBUw2T5bMGkEsehf4On2mO3ceuTP 0J9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695245893; x=1695850693; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hx2unC6bkbnK4o1a4tu1Rh/59GQGOMC47WGlP68Q50I=; b=goIaHcqLY52QidfPCmDOfEsaIAUKvwJzHig1WDB9AzNtlF09GEWBmQriR/W1vgw1vc gRwlbZMksEbaduynBryz86gJdDIFc0SOjBqBiLzOEeiohqf0Dp+saqgi51cwuPJ4LOvB fpqtHbJXpgSniKZsmSbSo036pejcHpvNrMDM/i9NWlqCmRm5kJEj9Uj1iiXlAN5bDDX3 0KOYuv0GFn0aP/Y7kf02mbhvh5HRSj2o4s9AidpCLCxs2U0USznM/IS/XyY4lJuNBL2b CxH2xVS33MJecb91ytJQTRJA10DXBUa6WFQYQ3uqtEIEZb68P3HbVoNesT+Mh7YSZzgr g49A== X-Gm-Message-State: AOJu0Yyiif+qBtqFJb95yNtGEbOOO8GEDAqUv9kjwSpPGTWbwyw/Cif1 IgiOlumQWRuxbaghH7Uo0WJyAlT6BP3dRMgzjwU= X-Google-Smtp-Source: AGHT+IHAbdJgwxcLYI9WO80PBIBUO00fg5Y2K1CMkoAkcd20AZdC32o/eNuFePPqEzKUlKFzZrpQ4g== X-Received: by 2002:a05:6830:2059:b0:6bc:bd1a:26d with SMTP id f25-20020a056830205900b006bcbd1a026dmr3670368otp.15.1695245893673; Wed, 20 Sep 2023 14:38:13 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH 8/8] target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion Date: Wed, 20 Sep 2023 18:37:43 -0300 Message-ID: <20230920213743.716265-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920213743.716265-1-dbarboza@ventanamicro.com> References: <20230920213743.716265-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695245973536100006 Content-Type: text/plain; charset="utf-8" Use the recently added API to filter unavailable CPUs for a given accelerator. At this moment this is the case for a QEMU built with KVM and TCG support querying a binary running with TCG: qemu-system-riscv64 -S -M virt,accel=3Dtcg -display none -qmp tcp:localhost:1234,server,wait=3Doff ./qemu/scripts/qmp/qmp-shell localhost:1234 (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"host"} {"error": {"class": "GenericError", "desc": "'host' CPU not available with = tcg"}} Signed-off-by: Daniel Henrique Barboza --- target/riscv/riscv-qmp-cmds.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index 5b2d186c83..2f2dbae7c8 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -31,6 +31,8 @@ #include "qapi/qobject-input-visitor.h" #include "qapi/visitor.h" #include "qom/qom-qobject.h" +#include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "cpu-qom.h" #include "cpu.h" =20 @@ -63,6 +65,17 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error *= *errp) return cpu_list; } =20 +static void riscv_check_if_cpu_available(RISCVCPU *cpu, Error **errp) +{ + if (!riscv_cpu_accelerator_compatible(cpu)) { + g_autofree char *name =3D riscv_cpu_get_name(cpu); + const char *accel =3D kvm_enabled() ? "kvm" : "tcg"; + + error_setg(errp, "'%s' CPU not available with %s", name, accel); + return; + } +} + static void riscv_obj_add_qdict_prop(Object *obj, QDict *qdict_out, const char *name) { @@ -161,6 +174,13 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(C= puModelExpansionType type, =20 obj =3D object_new(object_class_get_name(oc)); =20 + riscv_check_if_cpu_available(RISCV_CPU(obj), &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + object_unref(obj); + return NULL; + } + if (qdict_in) { riscv_cpuobj_validate_qdict_in(obj, model->props, qdict_in, &local_err); --=20 2.41.0