From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695208967; cv=none; d=zohomail.com; s=zohoarc; b=nviBk/aDBKvf5XuN5UY7xSa6DeQfHZEK3bWC+sd9WJqdjX5WQlaB5TpT6ow8w/wwPvkxb3MmZCSZDWo6zloGTlNWNhI2PC9oZKXVzRXky7Yj/QczzjLGzENetUuC0yXTeszDCO5fLlpIP2ptISQItPsOTdWvadB25v0ELbghCT8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695208967; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xy3sdxHckIJLkbIHgCa8lSOZ46hovx/gncs+ScoAQf4=; b=b0aboTi4vHNFdC2Bq58VGIUr3trUhK5YrtSVFHKJANllNMPAutWP2Te9gYyIzkxJoiCV62HyLtP27nQ8A5f8AKZVwg1O9yIbHDEfnUodhMyFRicJzFDkMNKXUX/eganBr/rcD0RXKmGdTpWpTNlE9oBjsdn2Kxp0UoZZVmhkt8g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695208967494402.10696629350105; Wed, 20 Sep 2023 04:22:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivFy-0005Ua-If; Wed, 20 Sep 2023 07:20:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivFx-0005UO-Da for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:33 -0400 Received: from mail-ot1-x32a.google.com ([2607:f8b0:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivFv-00024P-Hu for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:33 -0400 Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-6c07e122a78so4389476a34.2 for ; Wed, 20 Sep 2023 04:20:31 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.20.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:20:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208830; x=1695813630; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xy3sdxHckIJLkbIHgCa8lSOZ46hovx/gncs+ScoAQf4=; b=E8t9VnL/wb2O96s01IuXgrZmE0MeMmBzI8m23tkwvqTFNCrw3oxYE9FlLr7PcNLWP+ m24qKfilyJ1s+Kp1MDwumFX4H8HVSrSV/PezWy83892Qmn6hqV03LqH0vSArv3ULRVCf IrxOtcIiPFIJ2HvemWeG9wn0Ufbcw/oN6qEQIKhwM8VGvp0+HOCqlnbzeNOxWdDWE5S9 HnT8YbKrCiksN6UkWc6rnJUToOUjd3C7RgaaGgQzbARwFW/V2LEAvg0elEcFPAEVFZqh w1cuVANBGDWXG5MF3buJmzpkU9l8zX6eoI07wHxxih/EXYyFLnt7uSFzXEk47PbZM/0j HOMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208830; x=1695813630; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xy3sdxHckIJLkbIHgCa8lSOZ46hovx/gncs+ScoAQf4=; b=wo09NnJai9J6fTyJ4TjdBot42MKM7+atyoFFiugSvY/BBCJvMZn4ObfORyE1AWSmtg he3hSE9SIo2lQnK3D85M85fNVgBxWrnsdcbR8PNmw3jBzcryCBgMn8VhjdLYl7eGkB7I lPK482yu98QgRTXlR4tYNH5AP/dvFd69cgZDV/Y52rxq2Be+QUCcv6FE5ryWnQN4vb4n /pI6XCTtiI2Qw/FBZPN5v4yH8efbJ4HowSl5dIUaOPEhCIxOTLHiL/Ac80gfJ+eVycdB 1yBWRj10+n46E/5bfxiOzuldFM9qzMK5cwH6JuGWFqRtgnqzZp5zJOj9jsm7dDRGpPo4 id3A== X-Gm-Message-State: AOJu0Yz5RzEkSPTUpDaiX6hijXnt14Oo44xqcnG81w3YpCO/QUOdLb0+ E9BqxyA187KOWEbFOjy0HPuRpUERQwwlS9sH5c4= X-Google-Smtp-Source: AGHT+IH/TM/xp0pvELzvkQz+wiTDViTLQVLdMxLmtQq1SIg4NYjWkDJ9PgPC091PaPMtPUQ5K7hl/A== X-Received: by 2002:a05:6830:1bd6:b0:6bd:cf64:d105 with SMTP id v22-20020a0568301bd600b006bdcf64d105mr2339593ota.12.1695208830126; Wed, 20 Sep 2023 04:20:30 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 01/19] target/riscv: introduce TCG AccelCPUClass Date: Wed, 20 Sep 2023 08:20:02 -0300 Message-ID: <20230920112020.651006-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695208967962100001 Content-Type: text/plain; charset="utf-8" target/riscv/cpu.c needs to handle all possible accelerators (TCG and KVM at this moment) during both init() and realize() time. This forces us to resort to a lot of "if tcg" and "if kvm" throughout the code, which isn't wrong, but can get cluttered over time. Splitting acceleration specific code from cpu.c to its own file will help to declutter the existing code and it will also make it easier to support KVM/TCG only builds in the future. We'll start by adding a new subdir called 'tcg' and a new file called 'tcg-cpu.c'. This file will be used to introduce a new accelerator class for TCG acceleration in RISC-V, allowing us to center all TCG exclusive code in its file instead of using 'cpu.c' for everything. This design is inpired by the work Claudio Fontana did in x86 a few years ago in commit f5cc5a5c1 ("i386: split cpu accelerators from cpu.c, using AccelCPUClass"). To avoid moving too much code at once we'll start by adding the new file and TCG AccelCPUClass declaration. The 'class_init' from the accel class will init 'tcg_ops', relieving the common riscv_cpu_class_init() from doing it. 'riscv_tcg_ops' is being exported from 'cpu.c' for now to avoid having to deal with moving code and files around right now. We'll focus on decoupling the realize() logic first. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +--- target/riscv/cpu.h | 4 +++ target/riscv/meson.build | 2 ++ target/riscv/tcg/meson.build | 2 ++ target/riscv/tcg/tcg-cpu.c | 58 ++++++++++++++++++++++++++++++++++++ 5 files changed, 67 insertions(+), 4 deletions(-) create mode 100644 target/riscv/tcg/meson.build create mode 100644 target/riscv/tcg/tcg-cpu.c diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2644638b11..e72c49c881 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2288,9 +2288,7 @@ static const struct SysemuCPUOps riscv_sysemu_ops =3D= { }; #endif =20 -#include "hw/core/tcg-cpu-ops.h" - -static const struct TCGCPUOps riscv_tcg_ops =3D { +const struct TCGCPUOps riscv_tcg_ops =3D { .initialize =3D riscv_translate_init, .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, .restore_state_to_opc =3D riscv_restore_state_to_opc, @@ -2449,7 +2447,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; - cc->tcg_ops =3D &riscv_tcg_ops; =20 object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, cpu_set_mvendorid, NULL, NULL); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7d6cfb07ea..16a2dfa8c7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -707,6 +707,10 @@ enum riscv_pmu_event_idx { RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS =3D 0x10021, }; =20 +/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */ +#include "hw/core/tcg-cpu-ops.h" +extern const struct TCGCPUOps riscv_tcg_ops; + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; =20 diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 660078bda1..f0486183fa 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -38,5 +38,7 @@ riscv_system_ss.add(files( 'riscv-qmp-cmds.c', )) =20 +subdir('tcg') + target_arch +=3D {'riscv': riscv_ss} target_softmmu_arch +=3D {'riscv': riscv_system_ss} diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build new file mode 100644 index 0000000000..061df3d74a --- /dev/null +++ b/target/riscv/tcg/meson.build @@ -0,0 +1,2 @@ +riscv_ss.add(when: 'CONFIG_TCG', if_true: files( + 'tcg-cpu.c')) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c new file mode 100644 index 0000000000..0326cead0d --- /dev/null +++ b/target/riscv/tcg/tcg-cpu.c @@ -0,0 +1,58 @@ +/* + * riscv TCG cpu class initialization + * + * Copyright (c) 2023 Ventana Micro Systems Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "qemu/accel.h" +#include "hw/core/accel-cpu.h" + +static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) +{ + /* + * All cpus use the same set of operations. + * riscv_tcg_ops is being imported from cpu.c for now. + */ + cc->tcg_ops =3D &riscv_tcg_ops; +} + +static void tcg_cpu_class_init(CPUClass *cc) +{ + cc->init_accel_cpu =3D tcg_cpu_init_ops; +} + +static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_class_init =3D tcg_cpu_class_init; +} + +static const TypeInfo tcg_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("tcg"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D tcg_cpu_accel_class_init, + .abstract =3D true, +}; + +static void tcg_cpu_accel_register_types(void) +{ + type_register_static(&tcg_cpu_accel_type_info); +} +type_init(tcg_cpu_accel_register_types); --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695209091; cv=none; d=zohomail.com; s=zohoarc; b=iIdlKMXZ3F6My8GqGG42tda+qsN/6zgIzhbwd+KnBBXDfNL9wLHeN7meN6j2maSXdd0soRuSrqZbpb9JrHMSu2bMK0+8yd5phF7zJSsE5p9eeKspysaLvDfMDzVlpt7UmOUdh+4SqTRPXav7CUYJddE2JGPLrTVnFweC1GdVMPI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695209091; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=W23+YMA81pe1MZLk6lJUhJF08L4nB1r5s31TNWjrm+M=; b=UmoMWSVqzWY/9/PLSriJmv1DtbFOkd3YdJiJwGRyKl18bis4VsSmrTGmiOKZl2MvUIOa47duNgKN2aEnkvUYevA3Om2J/RbexTxrl+Yb5izX8ccz++LfUfvv2tF9PW/J6GTiTeX7gypHBjbu08LmkhBtcCrLPQJb/ZjeO3tVBbE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695209091743965.2639216041811; Wed, 20 Sep 2023 04:24:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivG4-0005Vi-3x; Wed, 20 Sep 2023 07:20:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivG0-0005VD-UL for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:36 -0400 Received: from mail-oa1-x31.google.com ([2001:4860:4864:20::31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivFz-00024r-4g for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:36 -0400 Received: by mail-oa1-x31.google.com with SMTP id 586e51a60fabf-1d682fd3c58so3240964fac.3 for ; Wed, 20 Sep 2023 04:20:34 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.20.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:20:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208833; x=1695813633; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W23+YMA81pe1MZLk6lJUhJF08L4nB1r5s31TNWjrm+M=; b=UTqhBlhsBN1f4UxuNlanbaIif/2Aj5gwuWLAkYZR13WHN5Kl7ilIomhWgbyUKT4egY IoysdjqJPV8kJ9QVqI8KH6wMxO3jJOOwcTIxWTx+klQZjr3B387txGGga+KLy42cFZKY XFR1wWKLquEZ0gmBYYdv0Gsenf7cdDHCNYOxQJ9eh7pujVuhCQkxpCnnXmEwVv8prCr0 JlaD0AvaTjzs5ZYTOBjRsrXc2RNfGi0DKWEdEaFwvjuNiKa8pDS023uSNQ8hE7OrOlm1 8VAkpAFyETT70iCZ218WDQdxRyzQpNDQEu+snuCUWVolmM9gPkatG68Kfwct0YRWhKDq /QfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208833; x=1695813633; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W23+YMA81pe1MZLk6lJUhJF08L4nB1r5s31TNWjrm+M=; b=hue6xrFHLlF6DQt/JkB23X0R2tGQv0OFvDm7RPdPKg2tlOE/bTpSxHWptMP8R25gdk 299fLyVfJ/hSv1pf05J/XFixQB0b1C/69VpCVu/tTuAto1ycRTPe/lz+fzQUCoGag38i O1SBovAsVa3eXFr5KNDguGg+/lflFPmEB3NYlkHFSwovkZUx1abbnzv6HmCm/J7RWjIk bnu1QpZiFiMGLEqF0PDfKUwjVLAZ8uzjyAjmn4BnxqtpWRQhpcN4nWtnMyWzitoSvlxW 8a5p2o4XLnyu1by5n0Z4flLzAl1MVrBmqsJ/h1mo0epWVhg3WGbKnrKijJDfvnDLNWqi mm0g== X-Gm-Message-State: AOJu0Ywqy9S9FViopYKCF1H2hGYFKTz9SqKoN/VdCAeTAumJN1AZYYcU u9lLJ1eHDX2Pp9L/yOwPGk0VPYZwNBY+pIEc0vI= X-Google-Smtp-Source: AGHT+IG1lkfRV6y5pXbsehqVnF2oVS4i63PF2hIPznSxjZGjyDEMoSbmldE4JtI8kK+UK3IUqD4ULg== X-Received: by 2002:a05:6870:589a:b0:1c8:b82b:cbdb with SMTP id be26-20020a056870589a00b001c8b82bcbdbmr2340796oab.33.1695208833320; Wed, 20 Sep 2023 04:20:33 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 02/19] target/riscv: move riscv_cpu_realize_tcg() to TCG::cpu_realizefn() Date: Wed, 20 Sep 2023 08:20:03 -0300 Message-ID: <20230920112020.651006-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695209095029100001 Content-Type: text/plain; charset="utf-8" riscv_cpu_realize_tcg() was added to allow TCG cpus to have a different realize() path during the common riscv_cpu_realize(), making it a good choice to start moving TCG exclusive code to tcg-cpu.c. Rename it to tcg_cpu_realizefn() and assign it as a implementation of accel::cpu_realizefn(). tcg_cpu_realizefn() will then be called during riscv_cpu_realize() via cpu_exec_realizefn(). We'll use a similar approach with KVM in the near future. riscv_cpu_validate_set_extensions() is too big and with too many dependencies to be moved in this same patch. We'll do that next. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 128 ----------------------------------- target/riscv/tcg/tcg-cpu.c | 133 +++++++++++++++++++++++++++++++++++++ 2 files changed, 133 insertions(+), 128 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e72c49c881..030629294f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -23,9 +23,7 @@ #include "qemu/log.h" #include "cpu.h" #include "cpu_vendorid.h" -#include "pmu.h" #include "internals.h" -#include "time_helper.h" #include "exec/exec-all.h" #include "qapi/error.h" #include "qapi/visitor.h" @@ -1064,29 +1062,6 @@ static void riscv_cpu_validate_v(CPURISCVState *env,= RISCVCPUConfig *cfg, } } =20 -static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) -{ - CPURISCVState *env =3D &cpu->env; - int priv_version =3D -1; - - if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { - priv_version =3D PRIV_VERSION_1_12_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { - priv_version =3D PRIV_VERSION_1_11_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { - priv_version =3D PRIV_VERSION_1_10_0; - } else { - error_setg(errp, - "Unsupported privilege spec version '%s'", - cpu->cfg.priv_spec); - return; - } - - env->priv_ver =3D priv_version; - } -} - static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) { CPURISCVState *env =3D &cpu->env; @@ -1111,33 +1086,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RIS= CVCPU *cpu) } } =20 -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) -{ - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); - CPUClass *cc =3D CPU_CLASS(mcc); - CPURISCVState *env =3D &cpu->env; - - /* Validate that MISA_MXL is set properly. */ - switch (env->misa_mxl_max) { -#ifdef TARGET_RISCV64 - case MXL_RV64: - case MXL_RV128: - cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; - break; -#endif - case MXL_RV32: - cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; - break; - default: - g_assert_not_reached(); - } - - if (env->misa_mxl_max !=3D env->misa_mxl) { - error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); - return; - } -} - /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. @@ -1511,74 +1459,6 @@ static void riscv_cpu_finalize_features(RISCVCPU *cp= u, Error **errp) #endif } =20 -static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) -{ - if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { - error_setg(errp, "H extension requires priv spec 1.12.0"); - return; - } -} - -static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) -{ - RISCVCPU *cpu =3D RISCV_CPU(dev); - CPURISCVState *env =3D &cpu->env; - Error *local_err =3D NULL; - - if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) { - error_setg(errp, "'host' CPU is not compatible with TCG accelerati= on"); - return; - } - - riscv_cpu_validate_misa_mxl(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - - riscv_cpu_validate_priv_spec(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - - riscv_cpu_validate_misa_priv(env, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - - if (cpu->cfg.epmp && !cpu->cfg.pmp) { - /* - * Enhanced PMP should only be available - * on harts with PMP support - */ - error_setg(errp, "Invalid configuration: EPMP requires PMP support= "); - return; - } - - riscv_cpu_validate_set_extensions(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - -#ifndef CONFIG_USER_ONLY - CPU(dev)->tcg_cflags |=3D CF_PCREL; - - if (cpu->cfg.ext_sstc) { - riscv_timer_init(cpu); - } - - if (cpu->cfg.pmu_num) { - if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpm= f) { - cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, - riscv_pmu_timer_cb, cpu); - } - } -#endif -} - static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -1597,14 +1477,6 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 - if (tcg_enabled()) { - riscv_cpu_realize_tcg(dev, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - } - riscv_cpu_finalize_features(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 0326cead0d..f47dc2064f 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -18,10 +18,142 @@ */ =20 #include "qemu/osdep.h" +#include "exec/exec-all.h" #include "cpu.h" +#include "pmu.h" +#include "time_helper.h" +#include "qapi/error.h" #include "qemu/accel.h" #include "hw/core/accel-cpu.h" =20 + +static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) +{ + if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { + error_setg(errp, "H extension requires priv spec 1.12.0"); + return; + } +} + +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); + CPUClass *cc =3D CPU_CLASS(mcc); + CPURISCVState *env =3D &cpu->env; + + /* Validate that MISA_MXL is set properly. */ + switch (env->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + case MXL_RV128: + cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; + break; +#endif + case MXL_RV32: + cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; + break; + default: + g_assert_not_reached(); + } + + if (env->misa_mxl_max !=3D env->misa_mxl) { + error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); + return; + } +} + +static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + int priv_version =3D -1; + + if (cpu->cfg.priv_spec) { + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { + priv_version =3D PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { + priv_version =3D PRIV_VERSION_1_11_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { + priv_version =3D PRIV_VERSION_1_10_0; + } else { + error_setg(errp, + "Unsupported privilege spec version '%s'", + cpu->cfg.priv_spec); + return; + } + + env->priv_ver =3D priv_version; + } +} + +/* + * We'll get here via the following path: + * + * riscv_cpu_realize() + * -> cpu_exec_realizefn() + * -> tcg_cpu_realizefn() (via accel_cpu_realizefn()) + */ +static bool tcg_cpu_realizefn(CPUState *cs, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + Error *local_err =3D NULL; + + if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) { + error_setg(errp, "'host' CPU is not compatible with TCG accelerati= on"); + return false; + } + + riscv_cpu_validate_misa_mxl(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return false; + } + + riscv_cpu_validate_priv_spec(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return false; + } + + riscv_cpu_validate_misa_priv(env, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return false; + } + + if (cpu->cfg.epmp && !cpu->cfg.pmp) { + /* + * Enhanced PMP should only be available + * on harts with PMP support + */ + error_setg(errp, "Invalid configuration: EPMP requires PMP support= "); + return false; + } + + riscv_cpu_validate_set_extensions(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return false; + } + +#ifndef CONFIG_USER_ONLY + CPU(cs)->tcg_cflags |=3D CF_PCREL; + + if (cpu->cfg.ext_sstc) { + riscv_timer_init(cpu); + } + + if (cpu->cfg.pmu_num) { + if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpm= f) { + cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + riscv_pmu_timer_cb, cpu); + } + } +#endif + + return true; +} + static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) { /* @@ -41,6 +173,7 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, vo= id *data) AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); =20 acc->cpu_class_init =3D tcg_cpu_class_init; + acc->cpu_realizefn =3D tcg_cpu_realizefn; } =20 static const TypeInfo tcg_cpu_accel_type_info =3D { --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695208966; cv=none; d=zohomail.com; s=zohoarc; b=nB3KvB5ngvOGZrO5A7Q8KmwRSAlJxXxyIANuABqMoGsXi5ZxJL2mh0JiFfXtsUB6+EJfrE4Z3IYT7sKGu/rzqXuuNfTLQbn6WXXqhdPsTbxbEo++fswFQBB3iqRSD457F1GSCvLEdHdIxZrRDChYrpQmnnQR6yMvbYIGMfcnwdk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695208966; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uM6cneBXrwp4UoecZN+VoWc7fFgYU2W+/c2ij/5c0+A=; b=S/Rq8Am83B5b2wDuYSUl1L1HIcx6N0obmPqsh0Zdt0qYHSOB55AhenpNrdoanynZwiwJNV7dAdrQRc10P6jxytkWit2VBkI7cgA0Du3zqK2Gl0C8XsT1WE9zpnSi/6Sfs5Pk35uy7kjyUdd1Bsb1jEvtKjMCI8nlCY9cw0APWpA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695208966781544.3493447411532; Wed, 20 Sep 2023 04:22:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivG8-0005Wz-Oj; Wed, 20 Sep 2023 07:20:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivG5-0005W1-Gh for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:41 -0400 Received: from mail-ot1-x332.google.com ([2607:f8b0:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivG2-00026o-G8 for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:41 -0400 Received: by mail-ot1-x332.google.com with SMTP id 46e09a7af769-6b9a2416b1cso4383643a34.2 for ; Wed, 20 Sep 2023 04:20:38 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.20.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:20:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208837; x=1695813637; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uM6cneBXrwp4UoecZN+VoWc7fFgYU2W+/c2ij/5c0+A=; b=XImUFY7A5Fiwx7YiTnys1IjAF7AwEu22jhGgjNzVm0aZWlgTxGXYKU5WDOVCqK4CFv rg1ep6NtofzigGZiI1MCkNkrPdlioOiH9QPfgpfpi2AJOd0KeZFBKgX2OQM24j1g0sv5 3LCq/QtMSyrwDvCfdOFBeYqKVFW89nFbrGHmDmFREfPY5nyGbgNa3GhQYza/cw/S1zmt F9XC0ysoltEjrOHVbdjdsg10d4RfX02WtQHDDkUfIzdXyLVLGpIWqxsj2UbUkco+BcGR VjdyKGZXU6cT8UDpQEAOOi7UvnEwDXkbmpTrc9E5bdCYCzG79zhSP45nie6jDHbh/lcT lr0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208837; x=1695813637; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uM6cneBXrwp4UoecZN+VoWc7fFgYU2W+/c2ij/5c0+A=; b=kPbfCd826PJabJdOZuiq5ttDDZdWO2P2zfkjTVkzefZHhV5/IU56Pf5IpEmkbQJhVX sDIzgJZUy8ieWJNkH5qGbcshE2+4aJlePdaG73JbX4irUEre3XTVSbQauZNvM5QUiGlh WdcxX/OmnRGa/P/Shv/E1Jwugw1pwf9na3J97imMUKj9RNaCiRNSjD+zvxtlG1FjIjRU 1Frhoq8eVypHQguZGkXwQx7X/e+gkHfcQx521MyCa3hftqVcc655v1dxvB0ctmIHIqVo avkrzc1Zggxu6YeFSdm7riVYL3iErC49pjiMzwYm9Q3kJthHzcjsClnog+DKvpX4i7yh bYqQ== X-Gm-Message-State: AOJu0YzWwTRvJmPZVrJToorODvAV6d4q5wyny+uAsTPc/vsBuCDQ9lbF 5ea3fVwWSLC1q/+RgVpQPOA1ys8+O+MEvurjE00= X-Google-Smtp-Source: AGHT+IEpN0GQ/oTceSs3AgP/yediO+GN38RHBXMKpcqB9Kbxr1Fei+39s25cWsgtqOcV65dorx0h2Q== X-Received: by 2002:a05:6871:551:b0:1d6:8e92:1e55 with SMTP id t17-20020a056871055100b001d68e921e55mr2056320oal.50.1695208836624; Wed, 20 Sep 2023 04:20:36 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 03/19] target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c Date: Wed, 20 Sep 2023 08:20:04 -0300 Message-ID: <20230920112020.651006-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695208967968100002 Content-Type: text/plain; charset="utf-8" This function is the core of the RISC-V validations for TCG CPUs, and it has a lot going on. Functions in cpu.c were made public to allow them to be used by the KVM accelerator class later on. 'cpu_cfg_ext_get_min_version()' is notably hard to move it to another file due to its dependency with isa_edata_arr[] array, thus make it public and use it as is for now. riscv_cpu_validate_set_extensions() is kept public because it's used by csr.c in write_misa(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 361 +------------------------------------ target/riscv/cpu.h | 8 +- target/riscv/csr.c | 1 + target/riscv/tcg/tcg-cpu.c | 357 ++++++++++++++++++++++++++++++++++++ target/riscv/tcg/tcg-cpu.h | 27 +++ 5 files changed, 397 insertions(+), 357 deletions(-) create mode 100644 target/riscv/tcg/tcg-cpu.h diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 030629294f..7215a29324 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -163,22 +163,21 @@ static const struct isa_ext_data isa_edata_arr[] =3D { /* Hash that stores user set extensions */ static GHashTable *multi_ext_user_opts; =20 -static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) +bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) { bool *ext_enabled =3D (void *)&cpu->cfg + ext_offset; =20 return *ext_enabled; } =20 -static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, - bool en) +void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en) { bool *ext_enabled =3D (void *)&cpu->cfg + ext_offset; =20 *ext_enabled =3D en; } =20 -static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) +int cpu_cfg_ext_get_min_version(uint32_t ext_offset) { int i; =20 @@ -193,38 +192,12 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_o= ffset) g_assert_not_reached(); } =20 -static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) +bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) { return g_hash_table_contains(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset)); } =20 -static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, - bool value) -{ - CPURISCVState *env =3D &cpu->env; - bool prev_val =3D isa_ext_is_enabled(cpu, ext_offset); - int min_version; - - if (prev_val =3D=3D value) { - return; - } - - if (cpu_cfg_ext_is_user_set(ext_offset)) { - return; - } - - if (value && env->priv_ver !=3D PRIV_VERSION_LATEST) { - /* Do not enable it if priv_ver is older than min_version */ - min_version =3D cpu_cfg_ext_get_min_version(ext_offset); - if (env->priv_ver < min_version) { - return; - } - } - - isa_ext_update_enabled(cpu, ext_offset, value); -} - const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -1023,46 +996,7 @@ static void riscv_cpu_disas_set_info(CPUState *s, dis= assemble_info *info) } } =20 -static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, - Error **errp) -{ - if (!is_power_of_2(cfg->vlen)) { - error_setg(errp, "Vector extension VLEN must be power of 2"); - return; - } - if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { - error_setg(errp, - "Vector extension implementation only supports VLEN " - "in the range [128, %d]", RV_VLEN_MAX); - return; - } - if (!is_power_of_2(cfg->elen)) { - error_setg(errp, "Vector extension ELEN must be power of 2"); - return; - } - if (cfg->elen > 64 || cfg->elen < 8) { - error_setg(errp, - "Vector extension implementation only supports ELEN " - "in the range [8, 64]"); - return; - } - if (cfg->vext_spec) { - if (!g_strcmp0(cfg->vext_spec, "v1.0")) { - env->vext_ver =3D VEXT_VERSION_1_00_0; - } else { - error_setg(errp, "Unsupported vector spec version '%s'", - cfg->vext_spec); - return; - } - } else if (env->vext_ver =3D=3D 0) { - qemu_log("vector version is not specified, " - "use the default value v1.0\n"); - - env->vext_ver =3D VEXT_VERSION_1_00_0; - } -} - -static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) +void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) { CPURISCVState *env =3D &cpu->env; int i; @@ -1086,291 +1020,6 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RI= SCVCPU *cpu) } } =20 -/* - * Check consistency between chosen extensions while setting - * cpu->cfg accordingly. - */ -void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) -{ - CPURISCVState *env =3D &cpu->env; - Error *local_err =3D NULL; - - /* Do some ISA extension error checking */ - if (riscv_has_ext(env, RVG) && - !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && - riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && - riscv_has_ext(env, RVD) && - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { - - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) && - !cpu->cfg.ext_icsr) { - error_setg(errp, "RVG requires Zicsr but user set Zicsr to fal= se"); - return; - } - - if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) && - !cpu->cfg.ext_ifencei) { - error_setg(errp, "RVG requires Zifencei but user set " - "Zifencei to false"); - return; - } - - warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true); - - env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; - env->misa_ext_mask |=3D RVI | RVM | RVA | RVF | RVD; - } - - if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { - error_setg(errp, - "I and E extensions are incompatible"); - return; - } - - if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { - error_setg(errp, - "Either I or E extension must be set"); - return; - } - - if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { - error_setg(errp, - "Setting S extension without U extension is illegal"); - return; - } - - if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { - error_setg(errp, - "H depends on an I base integer ISA with 32 x registers= "); - return; - } - - if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { - error_setg(errp, "H extension implicitly requires S-mode"); - return; - } - - if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { - error_setg(errp, "F extension requires Zicsr"); - return; - } - - if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { - error_setg(errp, "Zawrs extension requires A extension"); - return; - } - - if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { - error_setg(errp, "Zfa extension requires F extension"); - return; - } - - if (cpu->cfg.ext_zfh) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true); - } - - if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { - error_setg(errp, "Zfh/Zfhmin extensions require F extension"); - return; - } - - if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { - error_setg(errp, "Zfbfmin extension depends on F extension"); - return; - } - - if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { - error_setg(errp, "D extension requires F extension"); - return; - } - - if (riscv_has_ext(env, RVV)) { - riscv_cpu_validate_v(env, &cpu->cfg, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - - /* The V vector extension depends on the Zve64d extension */ - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true); - } - - /* The Zve64d extension depends on the Zve64f extension */ - if (cpu->cfg.ext_zve64d) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); - } - - /* The Zve64f extension depends on the Zve32f extension */ - if (cpu->cfg.ext_zve64f) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); - } - - if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { - error_setg(errp, "Zve64d/V extensions require D extension"); - return; - } - - if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { - error_setg(errp, "Zve32f/Zve64f extensions require F extension"); - return; - } - - if (cpu->cfg.ext_zvfh) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true); - } - - if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { - error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension= "); - return; - } - - if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { - error_setg(errp, "Zvfh extensions requires Zfhmin extension"); - return; - } - - if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) { - error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension"= ); - return; - } - - if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { - error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); - return; - } - - if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { - error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension= "); - return; - } - - /* Set the ISA extensions, checks should have happened above */ - if (cpu->cfg.ext_zhinx) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - } - - if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfi= nx) { - error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); - return; - } - - if (cpu->cfg.ext_zfinx) { - if (!cpu->cfg.ext_icsr) { - error_setg(errp, "Zfinx extension requires Zicsr"); - return; - } - if (riscv_has_ext(env, RVF)) { - error_setg(errp, - "Zfinx cannot be supported together with F extensio= n"); - return; - } - } - - if (cpu->cfg.ext_zce) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); - if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); - } - } - - /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ - if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); - if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); - } - if (riscv_has_ext(env, RVD)) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); - } - } - - if (env->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { - error_setg(errp, "Zcf extension is only relevant to RV32"); - return; - } - - if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { - error_setg(errp, "Zcf extension requires F extension"); - return; - } - - if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { - error_setg(errp, "Zcd extension requires D extension"); - return; - } - - if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || - cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { - error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " - "extension"); - return; - } - - if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { - error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " - "Zcd extension"); - return; - } - - if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { - error_setg(errp, "Zcmt extension requires Zicsr extension"); - return; - } - - /* - * In principle Zve*x would also suffice here, were they supported - * in qemu - */ - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || - cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh)= && - !cpu->cfg.ext_zve32f) { - error_setg(errp, - "Vector crypto extensions require V or Zve* extensions"= ); - return; - } - - if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f= ) { - error_setg( - errp, - "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions= "); - return; - } - - if (cpu->cfg.ext_zk) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); - } - - if (cpu->cfg.ext_zkn) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); - } - - if (cpu->cfg.ext_zks) { - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); - cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); - } - - /* - * Disable isa extensions based on priv spec after we - * validated and set everything we need. - */ - riscv_cpu_disable_priv_spec_isa_exts(cpu); -} - #ifndef CONFIG_USER_ONLY static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 16a2dfa8c7..409d198635 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -445,7 +445,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); -void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); =20 #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index @@ -711,6 +710,13 @@ enum riscv_pmu_event_idx { #include "hw/core/tcg-cpu-ops.h" extern const struct TCGCPUOps riscv_tcg_ops; =20 +/* used by tcg/tcg-cpu.c*/ +void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); +bool cpu_cfg_ext_is_user_set(uint32_t ext_offset); +bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); +int cpu_cfg_ext_get_min_version(uint32_t ext_offset); +void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 85a31dc420..4b4ab56c40 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "qemu/timer.h" #include "cpu.h" +#include "tcg/tcg-cpu.h" #include "pmu.h" #include "time_helper.h" #include "exec/exec-all.h" diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f47dc2064f..d86172f725 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -19,14 +19,43 @@ =20 #include "qemu/osdep.h" #include "exec/exec-all.h" +#include "tcg-cpu.h" #include "cpu.h" #include "pmu.h" #include "time_helper.h" #include "qapi/error.h" #include "qemu/accel.h" +#include "qemu/error-report.h" +#include "qemu/log.h" #include "hw/core/accel-cpu.h" =20 =20 +static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, + bool value) +{ + CPURISCVState *env =3D &cpu->env; + bool prev_val =3D isa_ext_is_enabled(cpu, ext_offset); + int min_version; + + if (prev_val =3D=3D value) { + return; + } + + if (cpu_cfg_ext_is_user_set(ext_offset)) { + return; + } + + if (value && env->priv_ver !=3D PRIV_VERSION_LATEST) { + /* Do not enable it if priv_ver is older than min_version */ + min_version =3D cpu_cfg_ext_get_min_version(ext_offset); + if (env->priv_ver < min_version) { + return; + } + } + + isa_ext_update_enabled(cpu, ext_offset, value); +} + static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) { if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { @@ -85,6 +114,334 @@ static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu= , Error **errp) } } =20 +static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, + Error **errp) +{ + if (!is_power_of_2(cfg->vlen)) { + error_setg(errp, "Vector extension VLEN must be power of 2"); + return; + } + + if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLEN " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + + if (!is_power_of_2(cfg->elen)) { + error_setg(errp, "Vector extension ELEN must be power of 2"); + return; + } + + if (cfg->elen > 64 || cfg->elen < 8) { + error_setg(errp, + "Vector extension implementation only supports ELEN " + "in the range [8, 64]"); + return; + } + + if (cfg->vext_spec) { + if (!g_strcmp0(cfg->vext_spec, "v1.0")) { + env->vext_ver =3D VEXT_VERSION_1_00_0; + } else { + error_setg(errp, "Unsupported vector spec version '%s'", + cfg->vext_spec); + return; + } + } else if (env->vext_ver =3D=3D 0) { + qemu_log("vector version is not specified, " + "use the default value v1.0\n"); + + env->vext_ver =3D VEXT_VERSION_1_00_0; + } +} + +/* + * Check consistency between chosen extensions while setting + * cpu->cfg accordingly. + */ +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + Error *local_err =3D NULL; + + /* Do some ISA extension error checking */ + if (riscv_has_ext(env, RVG) && + !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && + riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && + riscv_has_ext(env, RVD) && + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { + + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_icsr)) && + !cpu->cfg.ext_icsr) { + error_setg(errp, "RVG requires Zicsr but user set Zicsr to fal= se"); + return; + } + + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_ifencei)) && + !cpu->cfg.ext_ifencei) { + error_setg(errp, "RVG requires Zifencei but user set " + "Zifencei to false"); + return; + } + + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_icsr), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_ifencei), true); + + env->misa_ext |=3D RVI | RVM | RVA | RVF | RVD; + env->misa_ext_mask |=3D RVI | RVM | RVA | RVF | RVD; + } + + if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { + error_setg(errp, + "I and E extensions are incompatible"); + return; + } + + if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { + error_setg(errp, + "Either I or E extension must be set"); + return; + } + + if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { + error_setg(errp, + "Setting S extension without U extension is illegal"); + return; + } + + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { + error_setg(errp, + "H depends on an I base integer ISA with 32 x registers= "); + return; + } + + if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { + error_setg(errp, "H extension implicitly requires S-mode"); + return; + } + + if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { + error_setg(errp, "F extension requires Zicsr"); + return; + } + + if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { + error_setg(errp, "Zawrs extension requires A extension"); + return; + } + + if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { + error_setg(errp, "Zfa extension requires F extension"); + return; + } + + if (cpu->cfg.ext_zfh) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zfhmin), true); + } + + if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { + error_setg(errp, "Zfh/Zfhmin extensions require F extension"); + return; + } + + if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { + error_setg(errp, "Zfbfmin extension depends on F extension"); + return; + } + + if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { + error_setg(errp, "D extension requires F extension"); + return; + } + + if (riscv_has_ext(env, RVV)) { + riscv_cpu_validate_v(env, &cpu->cfg, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + + /* The V vector extension depends on the Zve64d extension */ + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64d), true); + } + + /* The Zve64d extension depends on the Zve64f extension */ + if (cpu->cfg.ext_zve64d) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve64f), true); + } + + /* The Zve64f extension depends on the Zve32f extension */ + if (cpu->cfg.ext_zve64f) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zve32f), true); + } + + if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { + error_setg(errp, "Zve64d/V extensions require D extension"); + return; + } + + if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { + error_setg(errp, "Zve32f/Zve64f extensions require F extension"); + return; + } + + if (cpu->cfg.ext_zvfh) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvfhmin), true); + } + + if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension= "); + return; + } + + if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { + error_setg(errp, "Zvfh extensions requires Zfhmin extension"); + return; + } + + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) { + error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension"= ); + return; + } + + if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { + error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); + return; + } + + if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { + error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension= "); + return; + } + + /* Set the ISA extensions, checks should have happened above */ + if (cpu->cfg.ext_zhinx) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + } + + if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfi= nx) { + error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); + return; + } + + if (cpu->cfg.ext_zfinx) { + if (!cpu->cfg.ext_icsr) { + error_setg(errp, "Zfinx extension requires Zicsr"); + return; + } + if (riscv_has_ext(env, RVF)) { + error_setg(errp, + "Zfinx cannot be supported together with F extensio= n"); + return; + } + } + + if (cpu->cfg.ext_zce) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); + if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); + } + } + + /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ + if (riscv_has_ext(env, RVC) && env->priv_ver >=3D PRIV_VERSION_1_12_0)= { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); + if (riscv_has_ext(env, RVF) && env->misa_mxl_max =3D=3D MXL_RV32) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); + } + if (riscv_has_ext(env, RVD)) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); + } + } + + if (env->misa_mxl_max !=3D MXL_RV32 && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension is only relevant to RV32"); + return; + } + + if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension requires F extension"); + return; + } + + if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { + error_setg(errp, "Zcd extension requires D extension"); + return; + } + + if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || + cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { + error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " + "extension"); + return; + } + + if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { + error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " + "Zcd extension"); + return; + } + + if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { + error_setg(errp, "Zcmt extension requires Zicsr extension"); + return; + } + + /* + * In principle Zve*x would also suffice here, were they supported + * in qemu + */ + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || + cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh)= && + !cpu->cfg.ext_zve32f) { + error_setg(errp, + "Vector crypto extensions require V or Zve* extensions"= ); + return; + } + + if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f= ) { + error_setg( + errp, + "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions= "); + return; + } + + if (cpu->cfg.ext_zk) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkn), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkr), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkt), true); + } + + if (cpu->cfg.ext_zkn) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zkne), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknd), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zknh), true); + } + + if (cpu->cfg.ext_zks) { + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkb), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkc), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zbkx), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksed), true); + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true); + } + + /* + * Disable isa extensions based on priv spec after we + * validated and set everything we need. + */ + riscv_cpu_disable_priv_spec_isa_exts(cpu); +} + /* * We'll get here via the following path: * diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h new file mode 100644 index 0000000000..630184759d --- /dev/null +++ b/target/riscv/tcg/tcg-cpu.h @@ -0,0 +1,27 @@ +/* + * riscv TCG cpu class initialization + * + * Copyright (c) 2023 Ventana Micro Systems Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef RISCV_TCG_CPU_H +#define RISCV_TCG_CPU_H + +#include "cpu.h" + +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); + +#endif --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695209120; cv=none; d=zohomail.com; s=zohoarc; b=AvcoYFoyuDgFOZvHSmL/xjHb27wi0QJk3G6l1TirnfxWTaVy/GQ9A1QSweP16MLu+XEzeeqwcS8VFAojzBjnNL/RZVuFYZI0Vz48Pf+nNg+h+WGn4av2xUm+vlP1cb3kJRqpIRcFXpuOvS682jsoLPmnwZ2Wb1uDDCn0rZT3n44= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695209120; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wXv2+rM6xv0lgenn9DSNpamz4f2qyYAqYB7MzAGEA5k=; b=M3aJBv0MrHJqZYkdBopC8kHSYjLlvgTcEsrrT0rBoKyinzTRdMdQAbH4271yv1orb7EIm4YNQux45FGxCAbUGxKRR4usM9c40UyTq7V/QSNUaJyk47z0hLMRqd/V/UvnEf7fg1K9Vt4lu7lpHb/k0pGMLc7OUy3Rehkybs4xkFo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16952091202861018.957543806252; Wed, 20 Sep 2023 04:25:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivGA-0005YB-Mh; Wed, 20 Sep 2023 07:20:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivG7-0005WT-GG for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:43 -0400 Received: from mail-ot1-x32c.google.com ([2607:f8b0:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivG5-00028j-BC for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:42 -0400 Received: by mail-ot1-x32c.google.com with SMTP id 46e09a7af769-6befdb1f545so4627076a34.3 for ; Wed, 20 Sep 2023 04:20:40 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.20.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:20:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208840; x=1695813640; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wXv2+rM6xv0lgenn9DSNpamz4f2qyYAqYB7MzAGEA5k=; b=BmKKpqwmKApgXfW7cVO+oSsOje9zin2HRqXnEAVh3iMtytFf5h0oFWe6QWE/8dizAf iYiymFay3zm9NuPRSSr8pNg4vgkydcXJ4L1Nn9Wy/bl2xAChaD/Ui5bytdnnr6oGy5Rh oWSF/LokimeJfqDILRrSrWVtAkJ32FwQphIvkTIt7ihwAApLl0Z6IwsEDdPc/JUQIWia jxE9k8NBuszZBD27lypJmr68YR3ugL3YPtnNHyOVuFTZb/ZtKz+/0tp4BtVMXXRwPTwy HuPpMvFOKnhGNz8U3E6LgMz7hP1oFK7iQcREqkVM72SOI6TeafgARfymiDqHt1xW+syL RlLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208840; x=1695813640; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wXv2+rM6xv0lgenn9DSNpamz4f2qyYAqYB7MzAGEA5k=; b=VuLdpPLFvz7i1s7wvYecu9jkc4oh7gRgT9Pab+cNqmxoy9yiLcjsISpNuT6fg5CGRy ubivdUBA3MY/YIqcuwasE13ECT2f3Ndk1Kh3GNBi0B9hGS2datvI2UK+/k0JDx0htwRr OiUnUW2vt8/RRfedpolpakzpzEdGE803upTZhoU4sVnaQhICwBXRYgrajD2/RDv9R70+ EJrW607YoTaBgSGGBy7HJVkzXMUnxaQCeOKaEvwE6+aXbSZg78F7s94xKBAFg9+7YsCg jFDBdnxV+I7FfM2AabT9dw10IRDyl0CyNnmxgxS9sZvM/hdrdiRhmRvEdEKhlB2Xr9Ri yHmg== X-Gm-Message-State: AOJu0YxQtHufuAEH6gJrH7G52V7PyYtFjxuKjyDV+mzYaFNHy9+DiDIa +28du0ON19cAJCOxIkdvlFMo4APjhsYd+c9Rkkg= X-Google-Smtp-Source: AGHT+IHn76HtS4SIGI2N95inf18MHqYuxbHBBSvDAwbaupp5vMOg/y5fiokNg5dFw2cW9D1UZQ+DdA== X-Received: by 2002:a9d:6396:0:b0:6bd:749:f5cc with SMTP id w22-20020a9d6396000000b006bd0749f5ccmr2256536otk.26.1695208839813; Wed, 20 Sep 2023 04:20:39 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 04/19] target/riscv: move riscv_tcg_ops to tcg-cpu.c Date: Wed, 20 Sep 2023 08:20:05 -0300 Message-ID: <20230920112020.651006-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695209121797100001 Move the remaining of riscv_tcg_ops now that we have a working realize() implementation. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 58 ------------------------------------ target/riscv/cpu.h | 4 --- target/riscv/tcg/tcg-cpu.c | 60 +++++++++++++++++++++++++++++++++++++- 3 files changed, 59 insertions(+), 63 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7215a29324..9426b3b9d6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -838,24 +838,6 @@ static vaddr riscv_cpu_get_pc(CPUState *cs) return env->pc; } =20 -static void riscv_cpu_synchronize_from_tb(CPUState *cs, - const TranslationBlock *tb) -{ - if (!(tb_cflags(tb) & CF_PCREL)) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); - - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); - - if (xl =3D=3D MXL_RV32) { - env->pc =3D (int32_t) tb->pc; - } else { - env->pc =3D tb->pc; - } - } -} - static bool riscv_cpu_has_work(CPUState *cs) { #ifndef CONFIG_USER_ONLY @@ -871,29 +853,6 @@ static bool riscv_cpu_has_work(CPUState *cs) #endif } =20 -static void riscv_restore_state_to_opc(CPUState *cs, - const TranslationBlock *tb, - const uint64_t *data) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); - target_ulong pc; - - if (tb_cflags(tb) & CF_PCREL) { - pc =3D (env->pc & TARGET_PAGE_MASK) | data[0]; - } else { - pc =3D data[0]; - } - - if (xl =3D=3D MXL_RV32) { - env->pc =3D (int32_t)pc; - } else { - env->pc =3D pc; - } - env->bins =3D data[1]; -} - static void riscv_cpu_reset_hold(Object *obj) { #ifndef CONFIG_USER_ONLY @@ -1809,23 +1768,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -const struct TCGCPUOps riscv_tcg_ops =3D { - .initialize =3D riscv_translate_init, - .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, - .restore_state_to_opc =3D riscv_restore_state_to_opc, - -#ifndef CONFIG_USER_ONLY - .tlb_fill =3D riscv_cpu_tlb_fill, - .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, - .do_interrupt =3D riscv_cpu_do_interrupt, - .do_transaction_failed =3D riscv_cpu_do_transaction_failed, - .do_unaligned_access =3D riscv_cpu_do_unaligned_access, - .debug_excp_handler =3D riscv_cpu_debug_excp_handler, - .debug_check_breakpoint =3D riscv_cpu_debug_check_breakpoint, - .debug_check_watchpoint =3D riscv_cpu_debug_check_watchpoint, -#endif /* !CONFIG_USER_ONLY */ -}; - static bool riscv_cpu_is_dynamic(Object *cpu_obj) { return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 409d198635..b2e558f730 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -706,10 +706,6 @@ enum riscv_pmu_event_idx { RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS =3D 0x10021, }; =20 -/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */ -#include "hw/core/tcg-cpu-ops.h" -extern const struct TCGCPUOps riscv_tcg_ops; - /* used by tcg/tcg-cpu.c*/ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool cpu_cfg_ext_is_user_set(uint32_t ext_offset); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index d86172f725..e480b9f726 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -28,7 +28,66 @@ #include "qemu/error-report.h" #include "qemu/log.h" #include "hw/core/accel-cpu.h" +#include "hw/core/tcg-cpu-ops.h" +#include "tcg/tcg.h" =20 +static void riscv_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) +{ + if (!(tb_cflags(tb) & CF_PCREL)) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); + + tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); + + if (xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t) tb->pc; + } else { + env->pc =3D tb->pc; + } + } +} + +static void riscv_restore_state_to_opc(CPUState *cs, + const TranslationBlock *tb, + const uint64_t *data) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); + target_ulong pc; + + if (tb_cflags(tb) & CF_PCREL) { + pc =3D (env->pc & TARGET_PAGE_MASK) | data[0]; + } else { + pc =3D data[0]; + } + + if (xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t)pc; + } else { + env->pc =3D pc; + } + env->bins =3D data[1]; +} + +static const struct TCGCPUOps riscv_tcg_ops =3D { + .initialize =3D riscv_translate_init, + .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, + .restore_state_to_opc =3D riscv_restore_state_to_opc, + +#ifndef CONFIG_USER_ONLY + .tlb_fill =3D riscv_cpu_tlb_fill, + .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, + .do_interrupt =3D riscv_cpu_do_interrupt, + .do_transaction_failed =3D riscv_cpu_do_transaction_failed, + .do_unaligned_access =3D riscv_cpu_do_unaligned_access, + .debug_excp_handler =3D riscv_cpu_debug_excp_handler, + .debug_check_breakpoint =3D riscv_cpu_debug_check_breakpoint, + .debug_check_watchpoint =3D riscv_cpu_debug_check_watchpoint, +#endif /* !CONFIG_USER_ONLY */ +}; =20 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) @@ -515,7 +574,6 @@ static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, = CPUClass *cc) { /* * All cpus use the same set of operations. - * riscv_tcg_ops is being imported from cpu.c for now. */ cc->tcg_ops =3D &riscv_tcg_ops; } --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695209082; cv=none; d=zohomail.com; s=zohoarc; b=ahuqlEjhUWU6D4Pz3JgNIs49NlE2b0Xtb0YC/JITjE/NWsP74Xg7h7MShSDl9+fbnJFDQtc4926jmX00KhktTcnNg9fDcqHNLHemuxgZOyuJ/2r8RAefLmKlFqDyA41VPzeBMyCRqLeEvm2tbBu+c5u+jwFMsZYWy5CzeJrTLio= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695209082; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VYZpogAnNMvf9lHAyK1WoXxa37bMCFKb0Dk4AIyTLEU=; b=gz6UeRooM8Vcs01OMaEyDI6QH9EHV9bDSJedA0oIBQ3dadjaCNKRsHk6CtOkSJE0BlrgaWa7NsrJKtQZ6OkQp87h7mUjNquUUq8wl0lBZ6dKGYIoZyYw/IxkFs3aQh8Z4MN2/7v+r7d6twSqqwzBJ8mzTMNR0gj9m44pXRiC7Og= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695209082752789.9804106368742; Wed, 20 Sep 2023 04:24:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivGD-0005ZZ-01; Wed, 20 Sep 2023 07:20:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivG9-0005XY-V1 for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:45 -0400 Received: from mail-ot1-x32a.google.com ([2607:f8b0:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivG8-0002AT-AH for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:45 -0400 Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-6c09d760cb9so4186862a34.2 for ; Wed, 20 Sep 2023 04:20:43 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.20.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:20:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208843; x=1695813643; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VYZpogAnNMvf9lHAyK1WoXxa37bMCFKb0Dk4AIyTLEU=; b=QpqUn9w53NbzNxB3SYEgVX/sVb64uW2UxBAg4FgZXSjyn6Li4CYhntjA87d7jNc3DY DDfZGZ7PF09III6nnOBnegg3GVV2c0iBQil/UAq6ype4HMgiYegW61qFkt2rPl6V1SHF y8djLTm2LiT2E8+pFGEZsBD8sphsWp6BVkOV6WC4BiD04aV/5htKu5kSOM/DRmBuLZN/ 9lGBzO3wvw1iPsMoEoDpUrAx3o3dMn1oZctBnTg16izq3hO6SqTU+ldEdcDgR+morrif VUd6BXY0pYAI+X1iyaazUeYZDd5EQOBG4I41dg5Dhyq1IRNaOaDQPrkGbCbwvRBoTRC1 lubA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208843; x=1695813643; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VYZpogAnNMvf9lHAyK1WoXxa37bMCFKb0Dk4AIyTLEU=; b=F+vxhXFL1rNcA03Phc1713y9RX+UjNiygoSLGQB9AvEqNL0X7LinfDWawEiXOryaHK gJgKe6M4k1cCNJglyD5Ztw0H5OLnD8ppeQQOiAC9mxgA+9U/NR4ybiaREVrPiPU5IGbI SVTRVSUTze1yq118P5exQPRsOJmE4pvjj1FP978wJAC5Q4UHs1bDdVKeeQfhBjYJY6v3 X4B4vcyQ40dESzUwpXikA1LESQDKJpn8mXa52x6wrWtr4zAnaEuivQFKMybNfVjG2LT6 Iu0lDhfdnfL8MUrMIRyofE7ycBnkrKbqeyDlCPxgTFX0v0nXfbs4vs37PwBx8b2HXP55 XR6g== X-Gm-Message-State: AOJu0Yz48gOOVph8pGhP5d+gJcz35fUGiiHUgYiHN/jl3ajMrj+G4VD0 i8zttEO2o3iC/tfPua3Nk2vZJt5wHFNs7KAIlHE= X-Google-Smtp-Source: AGHT+IEe0/oLvsl9Z8OEZQmqAZ1Qt6gJXlIvMAf+hoVTQpL+lj3HqXPheTPLySaQvg48hI6x8dR5qw== X-Received: by 2002:a05:6830:11c7:b0:6b9:414e:dc7d with SMTP id v7-20020a05683011c700b006b9414edc7dmr2029366otq.35.1695208842986; Wed, 20 Sep 2023 04:20:42 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 05/19] target/riscv/cpu.c: add .instance_post_init() Date: Wed, 20 Sep 2023 08:20:06 -0300 Message-ID: <20230920112020.651006-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695209083075100001 Content-Type: text/plain; charset="utf-8" All generic CPUs call riscv_cpu_add_user_properties(). The 'max' CPU calls riscv_init_max_cpu_extensions(). Both can be moved to a common instance_post_init() callback, implemented in riscv_cpu_post_init(), called by all CPUs. The call order then becomes: riscv_cpu_init() -> cpu_init() of each CPU -> .instance_post_init() In the near future riscv_cpu_post_init() will call the init() function of the current accelerator, providing a hook for KVM and TCG accel classes to change the init() process of the CPU. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 43 ++++++++++++++++++++++++++++++++----------- 1 file changed, 32 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9426b3b9d6..848b58e7c4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -427,8 +427,6 @@ static void riscv_max_cpu_init(Object *obj) mlx =3D MXL_RV32; #endif set_misa(env, mlx, 0); - riscv_cpu_add_user_properties(obj); - riscv_init_max_cpu_extensions(obj); env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), mlx =3D=3D MXL_RV32 ? @@ -442,7 +440,6 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -566,7 +563,6 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -579,7 +575,6 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - riscv_cpu_add_user_properties(obj); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -666,7 +661,6 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - riscv_cpu_add_user_properties(obj); } #endif /* CONFIG_KVM */ =20 @@ -1215,6 +1209,37 @@ static void riscv_cpu_set_irq(void *opaque, int irq,= int level) } #endif /* CONFIG_USER_ONLY */ =20 +static bool riscv_cpu_is_dynamic(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; +} + +static bool riscv_cpu_has_max_extensions(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) !=3D NULL; +} + +static bool riscv_cpu_has_user_properties(Object *cpu_obj) +{ + if (kvm_enabled() && + object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) !=3D NULL) { + return true; + } + + return riscv_cpu_is_dynamic(cpu_obj); +} + +static void riscv_cpu_post_init(Object *obj) +{ + if (riscv_cpu_has_user_properties(obj)) { + riscv_cpu_add_user_properties(obj); + } + + if (riscv_cpu_has_max_extensions(obj)) { + riscv_init_max_cpu_extensions(obj); + } +} + static void riscv_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); @@ -1768,11 +1793,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -static bool riscv_cpu_is_dynamic(Object *cpu_obj) -{ - return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; -} - static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -2009,6 +2029,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .instance_size =3D sizeof(RISCVCPU), .instance_align =3D __alignof__(RISCVCPU), .instance_init =3D riscv_cpu_init, + .instance_post_init =3D riscv_cpu_post_init, .abstract =3D true, .class_size =3D sizeof(RISCVCPUClass), .class_init =3D riscv_cpu_class_init, --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695208967; cv=none; d=zohomail.com; s=zohoarc; b=lvisaRfexa/Tx1so/y9DIhCa2YbKt7qPW/QZn4fP2iKgq7Ufg5ji7yOIHd1X5+T78sjmfxWflhh1Su/y8IYU/ZlWda9mRjlRyr1xPmp8UGy2iwhYBF9AdLcGK7TUyDvH8/KXYD/VTysBSwj1uOr9blzc1de76X+p1YtUhLODxjs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695208967; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=z34lnycwKSt8MQkk4aJUxrt7LNLfPdCkA0rJx8DGw4o=; b=lCYZdhcDl/iXa8161ZJOwsKIzpLo0jjV3BmpbJeEB//RKedZ6ow+htbJXomzDKVZBDUCwO9djvCtUWEbnw+JGd8KlJhceHMXV/fBPJjKPQWsCjqC8ZDJYvM/LA3jO9Xfsq7fz0Fhto6AOf3ShmHi3L6M2NDS1YNBlBEmIJEn5YI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695208967680983.3560953345108; Wed, 20 Sep 2023 04:22:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivGG-0005cg-LH; Wed, 20 Sep 2023 07:20:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivGF-0005c1-CO for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:51 -0400 Received: from mail-ot1-x331.google.com ([2607:f8b0:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivGB-0002C0-Hh for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:50 -0400 Received: by mail-ot1-x331.google.com with SMTP id 46e09a7af769-6bdacc5ed66so446259a34.1 for ; Wed, 20 Sep 2023 04:20:47 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.20.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:20:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208846; x=1695813646; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=z34lnycwKSt8MQkk4aJUxrt7LNLfPdCkA0rJx8DGw4o=; b=L69PIHIqoKASwJRpxeX6mtApb1KuwuxaDgepdhVxfCSyMENtPPgLKnPBLtsw+zK1vX 9Fco2FAI3zbCbZKjbI4CE0HrbjO+7QOMR0C8EoJ8HHF+wLDoARxOUrbcpZyP1lPxFI7f AIZbjUQQ67LKefBnuTX6Pp6DyCtm4Rz4CNaMuWCFHNTQW+Kbbi6KzByWdhioXNlEXVjE U1tZUMCwDbu9jzU9dNPBiG5KZP8pGFfkzCKSQjMFWbK9eSQSfbVTvqXpVMEJo07IVVTZ JB5C+XJumEFlsi8o5AYXkBzrxj1Ab9yjUyQ7RV5VaSeV03+sfhZD9KaiP3+iIFrznUGt tYag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208846; x=1695813646; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=z34lnycwKSt8MQkk4aJUxrt7LNLfPdCkA0rJx8DGw4o=; b=DEYqE19CT/dATmgR+gMiwq25PbkT4M0tlFAVEQPmXV25T2eMU+npBxRVERjS3YO9Ng sFf2z52A+wzT0La7E7b09uiIdl3yrpKysN3wnvSgBGAkxIL3AA2ZEtfDKBbES3WpAGZr ZJNYCdpHE44QwKvjrMGDcmG5+6j3RP6dQcdTJssOiN3MXPtxL/F/Hj/nmCUdnBAw16nF ixf9RNOlvYGbXIhH+9cZwICi4YngiKimQLZOXI1YF9cHtqJTmyiqb329m9EvV7K/7dVD OkJQNhidbqecTjVIirNQpue2TbbzbZGeEyjbgA5lF9uYkKaPrrTilMrYm8xxTn+FUem4 opSQ== X-Gm-Message-State: AOJu0YxAYdu0A/1CeZhmZYq9Y3/YAwCoP2YAVSE3bROKpWpbn6zN6B3n G4lWAwrDalgxPggOHUII0AUFQfKvx/GqVjEawbk= X-Google-Smtp-Source: AGHT+IFateV7jbgTo6ALi8PviF6dW8ECRFBQSR6PNF5FvgxESe0k4ZODYbHLpvto4JtZdzP0lkEO9A== X-Received: by 2002:a05:6830:3687:b0:6b9:5735:d9dc with SMTP id bk7-20020a056830368700b006b95735d9dcmr2932100otb.14.1695208846298; Wed, 20 Sep 2023 04:20:46 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 06/19] target/riscv: move 'host' CPU declaration to kvm.c Date: Wed, 20 Sep 2023 08:20:07 -0300 Message-ID: <20230920112020.651006-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695208968925100009 This CPU only exists if we're compiling with KVM so move it to the kvm specific file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 15 --------------- target/riscv/kvm.c | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 848b58e7c4..f8368ce274 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -652,18 +652,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) } #endif =20 -#if defined(CONFIG_KVM) -static void riscv_host_cpu_init(Object *obj) -{ - CPURISCVState *env =3D &RISCV_CPU(obj)->env; -#if defined(TARGET_RISCV32) - set_misa(env, MXL_RV32, 0); -#elif defined(TARGET_RISCV64) - set_misa(env, MXL_RV64, 0); -#endif -} -#endif /* CONFIG_KVM */ - static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; @@ -2041,9 +2029,6 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { }, DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), -#if defined(CONFIG_KVM) - DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), -#endif #if defined(TARGET_RISCV32) DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 1e4e4456b3..31d2ede4b6 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -1271,3 +1271,24 @@ void kvm_riscv_aia_create(MachineState *machine, uin= t64_t group_shift, =20 kvm_msi_via_irqfd_allowed =3D kvm_irqfds_enabled(); } + +static void riscv_host_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + +#if defined(TARGET_RISCV32) + env->misa_mxl_max =3D env->misa_mxl =3D MXL_RV32; +#elif defined(TARGET_RISCV64) + env->misa_mxl_max =3D env->misa_mxl =3D MXL_RV64; +#endif +} + +static const TypeInfo riscv_kvm_cpu_type_infos[] =3D { + { + .name =3D TYPE_RISCV_CPU_HOST, + .parent =3D TYPE_RISCV_CPU, + .instance_init =3D riscv_host_cpu_init, + } +}; + +DEFINE_TYPES(riscv_kvm_cpu_type_infos) --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695208885; cv=none; d=zohomail.com; s=zohoarc; b=i4CZCM1o6YiG3Y79RPfw1kHzmF7ZeRGaYoVf3E06Ej12mUCfGcASKxlg4d0DeXg1da+Nj2sg1ymOyPMDWDGpRmvOwxjNakTNo4jUPzMxtBwIoCSkVzZg+aFbZs3GwJBGLSlzkBJuxkCWJHaSxZAoMxCqkY96Rsd7RwkGF0JStnk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695208885; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/VkbHu3ro5dFtNXMh6G6f1KNKstsUOQ9pg5TPerqopg=; b=MVo/lRpx0ZZ78qPHF2tNn7cLA12dNNTn/B96EruyKjxylCss60sQmwvwSTvRd4W5OEPnqFZpeCHkunGssnKa7CCzRZCn59C6sbqgY/OZB4weQPT87oc5qJXJU8CoLrB3INz3ZqCC3le3s+6XV3yOADstb1F3GoojR9EVdTtxUZk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695208885050712.3440881771586; Wed, 20 Sep 2023 04:21:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivGI-0005di-KU; Wed, 20 Sep 2023 07:20:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivGG-0005d6-Sd for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:52 -0400 Received: from mail-ot1-x329.google.com ([2607:f8b0:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivGF-0002CI-5g for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:52 -0400 Received: by mail-ot1-x329.google.com with SMTP id 46e09a7af769-6c0e8345c1eso4471065a34.0 for ; Wed, 20 Sep 2023 04:20:50 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.20.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:20:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208849; x=1695813649; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/VkbHu3ro5dFtNXMh6G6f1KNKstsUOQ9pg5TPerqopg=; b=pebfWqcYf5Wg5Y8k9RgrtbQxHKLrgWwb4K7OYWJDKbDMdWmh9+y+sll1WfaHW+h80k w8onVMd90IkROEiURSTNMVoKi6lkrbIEBhDIqmJVSS0QHWrxdU66mw9Ns5G7Ka1tr35f nPDckj8iuNMLFvyjfdTEBmKfIHzAE8pAqufzT0sfrJT+XRodgIwHkihh9NxGc1qEJfZc SJ7yZ9IMmjBUpBOPObnNiC+oEOGlg7NShGogRZ+WXubJhx5w3GoZieYZiy+rOvFL7MhI msMkR12zDtOgbHK+05e4I23inPNQYPkWn/tK6jY7Dl9cMqagCmFwowY6JhP440k1iRbg IkNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208849; x=1695813649; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/VkbHu3ro5dFtNXMh6G6f1KNKstsUOQ9pg5TPerqopg=; b=rEY5sIUrZUFKO1ssfJdAs2pyMfdzANJguSytLGIIIKQlUhqEXnOBRxtZuURGqcD1kA P0o3HiiTjDfS/xWSmCo6zfG5Bvu6YTcaUgpMfShSk3fPo2SxXY+nyxzkm+YHrW9tWwv2 ZY2fZoXuTauBARiqX7EL94f+uizLOm3fihWBfFAZ1MQfvwwlKvA0k1jF/q2MMT4RL4OY sA36koDMz8Pegqldj0ub895Gyq+JLr8ssYSz4LKrgpAiYSBRGwPpI7CpVPHxyvQKzvGo H3M4dIkFYmTMJLiCz0EhI+9x0mBsDpuxJvZWzqLldAluTAc1snNVHU5MRRElkYxo4XJ2 Jpww== X-Gm-Message-State: AOJu0Ywn83g8U64yDI16a7rO/TrG+p2wRVGh3hKl1WTHrl3V8MxaijQE CcmdQiv1HlogCZKX7Zhfwvpk2bRvY+blIj6yxDw= X-Google-Smtp-Source: AGHT+IHgCTC6zStbb7GVnCyU5OgVdnU3gJLw9wEYkRO97AmNE9uimk1DiDRRFrijQn1GbQytW1/Y5A== X-Received: by 2002:a9d:4f04:0:b0:6bd:b40:8912 with SMTP id d4-20020a9d4f04000000b006bd0b408912mr2097412otl.35.1695208849562; Wed, 20 Sep 2023 04:20:49 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 07/19] target/riscv/cpu.c: mark extensions arrays as 'const' Date: Wed, 20 Sep 2023 08:20:08 -0300 Message-ID: <20230920112020.651006-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695208886852100003 Content-Type: text/plain; charset="utf-8" We'll need to export these arrays to the accelerator classes in the next patches. Mark them as 'const' now because they should not be modified at runtime. Note that 'riscv_cpu_options' will also be exported, but can't be marked as 'const', because the properties are changed via qdev_property_add_static(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f8368ce274..048a2dbc77 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1407,7 +1407,7 @@ typedef struct RISCVCPUMultiExtConfig { {.name =3D _name, .offset =3D CPU_CFG_OFFSET(_prop), \ .enabled =3D _defval} =20 -static RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { +static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true), @@ -1469,7 +1469,7 @@ static RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] =3D { +static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] =3D { MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false), MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false), MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false), @@ -1487,7 +1487,7 @@ static RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]= =3D { }; =20 /* These are experimental so mark with 'x-' */ -static RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { +static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { /* ePMP 0.9.3 */ MULTI_EXT_CFG_BOOL("x-epmp", epmp, false), MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false), @@ -1558,7 +1558,7 @@ static void cpu_get_multi_ext_cfg(Object *obj, Visito= r *v, const char *name, } =20 static void cpu_add_multi_ext_prop(Object *cpu_obj, - RISCVCPUMultiExtConfig *multi_cfg) + const RISCVCPUMultiExtConfig *multi_cfg) { object_property_add(cpu_obj, multi_cfg->name, "bool", cpu_get_multi_ext_cfg, @@ -1575,11 +1575,13 @@ static void cpu_add_multi_ext_prop(Object *cpu_obj, } =20 static void riscv_cpu_add_multiext_prop_array(Object *obj, - RISCVCPUMultiExtConfig *arra= y) + const RISCVCPUMultiExtConfig *arra= y) { + const RISCVCPUMultiExtConfig *prop; + g_assert(array); =20 - for (RISCVCPUMultiExtConfig *prop =3D array; prop && prop->name; prop+= +) { + for (prop =3D array; prop && prop->name; prop++) { cpu_add_multi_ext_prop(obj, prop); } } @@ -1620,11 +1622,13 @@ static void riscv_cpu_add_kvm_unavail_prop(Object *= obj, const char *prop_name) } =20 static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, - RISCVCPUMultiExtConfig *a= rray) + const RISCVCPUMultiExtConfig *arra= y) { + const RISCVCPUMultiExtConfig *prop; + g_assert(array); =20 - for (RISCVCPUMultiExtConfig *prop =3D array; prop && prop->name; prop+= +) { + for (prop =3D array; prop && prop->name; prop++) { riscv_cpu_add_kvm_unavail_prop(obj, prop->name); } } @@ -1687,7 +1691,7 @@ static void riscv_init_max_cpu_extensions(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - RISCVCPUMultiExtConfig *prop; + const RISCVCPUMultiExtConfig *prop; =20 /* Enable RVG, RVJ and RVV that are disabled by default */ set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695209100; cv=none; d=zohomail.com; s=zohoarc; b=LNW1rC0O0PUE6WwY9FI+8bYy0CpsIamYTsp5Crk9c+SMyrrMzGp09fXt/mbTNSIC/TR2b71/tefrVEBWGPoAbucCRTwvZd9ZVbouB/j/ihhQYAPmQtaDqwemG8wXkquy1xWqZWdlxav0Q5cN3FxlP3fnHA6+in7QNwWP8ojDvHM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695209100; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DmVkKvTAOuUNt4UAtysRt2NatN2A0KygpSkxpaxrMiM=; b=P33YaSMFstTtoJaA6E012ugs5S344J5iYPyX4oqEBFbphngUBBvL9woFvuUsXzB/8WfWUwg/WbNUchdSrPvIhLfc+bP70GVWoNr1YNBp9XyZIjbxX9+r5QHc82si71UaLo6FrqTM6jcOhi9oUTfQOo0QMG7EByfxPjvVKAr6/f8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695209100953183.98348850178274; Wed, 20 Sep 2023 04:25:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivGL-0005f8-S1; Wed, 20 Sep 2023 07:20:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivGK-0005eY-6a for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:56 -0400 Received: from mail-ot1-x32c.google.com ([2607:f8b0:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivGI-0002Cp-AL for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:55 -0400 Received: by mail-ot1-x32c.google.com with SMTP id 46e09a7af769-6c0b8f42409so4041430a34.0 for ; Wed, 20 Sep 2023 04:20:53 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.20.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:20:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208853; x=1695813653; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DmVkKvTAOuUNt4UAtysRt2NatN2A0KygpSkxpaxrMiM=; b=BPTz8iC9u4jGUy+TzsFWQjqLU52ewchYBKqCH53m24xIE1iUmvaYVh3o6Tuifjpxsh /R6Yocc3eOb2nSLqxP75ll8EV8bEAmcM+FmPQwZzvnqqZUDvEZGucVsph3wSkr38Fs0o FDvDYkl9qAJp23PkEdILTcC+b+BETq4n9iyeQrVz/UjnJmc9o9Zk6U8hwE2zbjoLll5f 3yjBpgOBcUo47Bkr8WRgztqdjOdtHd6/MFigPyPGDQylEhUi7zXO8cFrgme80tgsATMB QH0jffv/nLRwVqYZx+ysntc9aG36amUjObsDbV3gasgLUovvrhF9kNodcePzAWyzIiMa iJSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208853; x=1695813653; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DmVkKvTAOuUNt4UAtysRt2NatN2A0KygpSkxpaxrMiM=; b=xTLGLDfNL3BJsSwo8kxbhqg2eGpJZHcA4eJsJnL7a7XWh5RLwaaBHoeKF9sTYSMPmE QhJ0llexDMCe5ZXLm3bN/GlWdfmL2of6d8AVtdpS+7gytJ/GiwsR+TXg5Ftt8HS40rZU v0hnJwXifyRB5JjJsVaX3OovP98kyFxStdMtcsHjU3ytIDhT7QbT6TkV+2nGMknujd3/ 42AtEKrBoQgr8igi7SnvJs8bgx9sJQy5AXjX9Sp7aeXzYszu84+K6Y3I0Hx7zGX1pcN6 8/9agbs1fnGRcsE1XLWq7VvieIijGMgwhLnepVRHUqrXZxID3RcuYlghTD1bwzp5wUz0 hW+A== X-Gm-Message-State: AOJu0YxXG83OCCQJoh6I7QgRJtXaCTeF/R53MQJT15hRZfjeBjSlBlrc nf/8W0mIX85XB6456tykCVMUeX/t7Ac0fjl/p7M= X-Google-Smtp-Source: AGHT+IFeMLgCOFQO1Ungn5IHRT4qQjkzoN+lKOepZQqQeNmiYXk84JhUVRwM1U2Z4bZyMoAeSBEELw== X-Received: by 2002:a05:6870:b506:b0:1c8:c313:3e0d with SMTP id v6-20020a056870b50600b001c8c3133e0dmr2707915oap.46.1695208852847; Wed, 20 Sep 2023 04:20:52 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 08/19] target/riscv: move riscv_cpu_add_kvm_properties() to kvm.c Date: Wed, 20 Sep 2023 08:20:09 -0300 Message-ID: <20230920112020.651006-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695209102387100001 Content-Type: text/plain; charset="utf-8" We'll introduce the KVM accelerator class with a 'cpu_instance_init' implementation that is going to be invoked during the common riscv_cpu_post_init() (via accel_cpu_instance_init()). This instance_init will execute KVM exclusive code that TCG doesn't care about, such as adding KVM specific properties, initing registers using a KVM scratch CPU and so on. The core of the forementioned cpu_instance_init impl is the current riscv_cpu_add_kvm_properties() that is being used by the common code via riscv_cpu_add_user_properties() in cpu.c. Move it to kvm.c, together will all the relevant artifacts, exporting and renaming it to kvm_riscv_cpu_add_kvm_properties() so cpu.c can keep using it for now. To make this work we'll need to export riscv_cpu_extensions, riscv_cpu_vendor_exts and riscv_cpu_experimental_exts from cpu.c as well. The TCG accelerator will also need to access those in the near future so this export will benefit us in the long run. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 85 +++------------------------------------- target/riscv/cpu.h | 14 +++++++ target/riscv/kvm.c | 68 +++++++++++++++++++++++++++++++- target/riscv/kvm_riscv.h | 3 -- 4 files changed, 86 insertions(+), 84 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 048a2dbc77..0dc9b3201d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1370,7 +1370,7 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { * change MISA bits during realize() (RVG enables MISA * bits but the user is warned about it). */ -static void riscv_cpu_add_misa_properties(Object *cpu_obj) +void riscv_cpu_add_misa_properties(Object *cpu_obj) { int i; =20 @@ -1397,17 +1397,11 @@ static void riscv_cpu_add_misa_properties(Object *c= pu_obj) } } =20 -typedef struct RISCVCPUMultiExtConfig { - const char *name; - uint32_t offset; - bool enabled; -} RISCVCPUMultiExtConfig; - #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \ {.name =3D _name, .offset =3D CPU_CFG_OFFSET(_prop), \ .enabled =3D _defval} =20 -static const RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { +const RISCVCPUMultiExtConfig riscv_cpu_extensions[] =3D { /* Defaults for standard extensions */ MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true), @@ -1469,7 +1463,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_extensi= ons[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] =3D { +const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] =3D { MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false), MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false), MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false), @@ -1487,7 +1481,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_vendor_= exts[] =3D { }; =20 /* These are experimental so mark with 'x-' */ -static const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { +const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { /* ePMP 0.9.3 */ MULTI_EXT_CFG_BOOL("x-epmp", epmp, false), MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false), @@ -1513,7 +1507,7 @@ static const RISCVCPUMultiExtConfig riscv_cpu_experim= ental_exts[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static Property riscv_cpu_options[] =3D { +Property riscv_cpu_options[] =3D { DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), =20 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), @@ -1586,75 +1580,6 @@ static void riscv_cpu_add_multiext_prop_array(Object= *obj, } } =20 -#ifdef CONFIG_KVM -static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, - const char *name, - void *opaque, Error **errp) -{ - const char *propname =3D opaque; - bool value; - - if (!visit_type_bool(v, name, &value, errp)) { - return; - } - - if (value) { - error_setg(errp, "extension %s is not available with KVM", - propname); - } -} - -static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_n= ame) -{ - /* Check if KVM created the property already */ - if (object_property_find(obj, prop_name)) { - return; - } - - /* - * Set the default to disabled for every extension - * unknown to KVM and error out if the user attempts - * to enable any of them. - */ - object_property_add(obj, prop_name, "bool", - NULL, cpu_set_cfg_unavailable, - NULL, (void *)prop_name); -} - -static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, - const RISCVCPUMultiExtConfig *arra= y) -{ - const RISCVCPUMultiExtConfig *prop; - - g_assert(array); - - for (prop =3D array; prop && prop->name; prop++) { - riscv_cpu_add_kvm_unavail_prop(obj, prop->name); - } -} - -void kvm_riscv_cpu_add_kvm_properties(Object *obj) -{ - Property *prop; - DeviceState *dev =3D DEVICE(obj); - - kvm_riscv_init_user_properties(obj); - riscv_cpu_add_misa_properties(obj); - - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts); - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); - - for (prop =3D riscv_cpu_options; prop && prop->name; prop++) { - /* Check if KVM created the property already */ - if (object_property_find(obj, prop->name)) { - continue; - } - qdev_property_add_static(dev, prop); - } -} -#endif - /* * Add CPU properties with user-facing flags. * diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b2e558f730..9dc4113812 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -22,6 +22,7 @@ =20 #include "hw/core/cpu.h" #include "hw/registerfields.h" +#include "hw/qdev-properties.h" #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" #include "qom/object.h" @@ -713,6 +714,19 @@ bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_of= fset); int cpu_cfg_ext_get_min_version(uint32_t ext_offset); void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); =20 +typedef struct RISCVCPUMultiExtConfig { + const char *name; + uint32_t offset; + bool enabled; +} RISCVCPUMultiExtConfig; + +extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; +extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; +extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; +extern Property riscv_cpu_options[]; + +void riscv_cpu_add_misa_properties(Object *cpu_obj); + /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; =20 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 31d2ede4b6..e682a70311 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -345,6 +345,52 @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU = *cpu, CPUState *cs) } } =20 +static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, + const char *name, + void *opaque, Error **errp) +{ + const char *propname =3D opaque; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + if (value) { + error_setg(errp, "extension %s is not available with KVM", + propname); + } +} + +static void riscv_cpu_add_kvm_unavail_prop(Object *obj, const char *prop_n= ame) +{ + /* Check if KVM created the property already */ + if (object_property_find(obj, prop_name)) { + return; + } + + /* + * Set the default to disabled for every extension + * unknown to KVM and error out if the user attempts + * to enable any of them. + */ + object_property_add(obj, prop_name, "bool", + NULL, cpu_set_cfg_unavailable, + NULL, (void *)prop_name); +} + +static void riscv_cpu_add_kvm_unavail_prop_array(Object *obj, + const RISCVCPUMultiExtConfig *arra= y) +{ + const RISCVCPUMultiExtConfig *prop; + + g_assert(array); + + for (prop =3D array; prop && prop->name; prop++) { + riscv_cpu_add_kvm_unavail_prop(obj, prop->name); + } +} + static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj) { int i; @@ -754,7 +800,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, = KVMScratchCPU *kvmcpu) } } =20 -void kvm_riscv_init_user_properties(Object *cpu_obj) +static void riscv_init_user_properties(Object *cpu_obj) { RISCVCPU *cpu =3D RISCV_CPU(cpu_obj); KVMScratchCPU kvmcpu; @@ -1272,6 +1318,26 @@ void kvm_riscv_aia_create(MachineState *machine, uin= t64_t group_shift, kvm_msi_via_irqfd_allowed =3D kvm_irqfds_enabled(); } =20 +void kvm_riscv_cpu_add_kvm_properties(Object *obj) +{ + DeviceState *dev =3D DEVICE(obj); + + riscv_init_user_properties(obj); + riscv_cpu_add_misa_properties(obj); + + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts); + riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); + + for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { + /* Check if KVM created the property already */ + if (object_property_find(obj, prop->name)) { + continue; + } + qdev_property_add_static(dev, prop); + } +} + static void riscv_host_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index 44b850a046..da9630c4af 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -19,10 +19,7 @@ #ifndef QEMU_KVM_RISCV_H #define QEMU_KVM_RISCV_H =20 -/* Temporarily implemented in cpu.c */ void kvm_riscv_cpu_add_kvm_properties(Object *obj); - -void kvm_riscv_init_user_properties(Object *cpu_obj); void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695209075; cv=none; d=zohomail.com; s=zohoarc; b=IfyM5V/RKwcE9e3oW19vWamaOzbqysKX+gbFu/z/DYqdRKvH2nzQHp0E7SWqsW4Oxzb7tjw+eRXIgW3P9vscw5jZI/SlCTlZPYxnGJ2GAI80avwIUFgVUhtzxOMdVUU7vayxEpvzvL6X65xikGMRCO5lA0cj17nX+H6Ne+zsFtI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695209075; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=29CXHps3Zqp4qnuZZFbf9i6nyFjwkzzwGbOnN7RJ9eU=; b=XePXWog3ReB3POR3nVYmX3Ht1nl3Phh6AVX/5xdG28A2DiWSIujcATpJtKvL/fvuUCF+HN4srUrNkbHiNJUoVM7WvubrHFLUCfD52Dizn34NwVO2OoyC/TTTnNZx6Sm3YPxdEtXwMjaPr5pcG22aBOmstODdko+HoNr3JPRnnlU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695209075248396.55711258369206; Wed, 20 Sep 2023 04:24:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivGO-0005gL-T2; Wed, 20 Sep 2023 07:21:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivGM-0005fe-Qc for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:58 -0400 Received: from mail-ot1-x335.google.com ([2607:f8b0:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivGL-0002DE-8l for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:20:58 -0400 Received: by mail-ot1-x335.google.com with SMTP id 46e09a7af769-6befdb1f545so4627247a34.3 for ; Wed, 20 Sep 2023 04:20:56 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.20.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:20:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208856; x=1695813656; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=29CXHps3Zqp4qnuZZFbf9i6nyFjwkzzwGbOnN7RJ9eU=; b=ScgwkZbuO2ZH+P3BKahoNLAkzy6cbcu/w/MYxq2y6Fh0nZhRMx5KysP8cFGE3E/q1l b6AIdMWug1nNstSQfSnPTHID2meH91qW4+BoUg+E0yE190LWsOEQY33CVqr4lH5xyRof Kd3cod9tjNTPDTQ0T4mQtyN1DVnQrxxyw2ijsZLP3cl+ZpxOQ5MftpjF9h8xbpoWbHR5 EJoJnZOVtcBW1fy82w5i93nyjj5kLmr8lvd1ePU5hYfKUdP+spaJAcXFhJE6laRJHLE4 WErq61MzH64pq/xRB9BbAiIUOn4zI74DjbnPIJmDf4sDedzspychsHIbyVia+iwV+nV1 yoZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208856; x=1695813656; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=29CXHps3Zqp4qnuZZFbf9i6nyFjwkzzwGbOnN7RJ9eU=; b=F9w0fLpbstfL4/n7Kvq8MCmmuawlXNV1BetvyuUYLwoLlRL/j/rjIfWHErpoPHBWo6 We8vUJyw0uimnT1Z899JTsocdrcXILG2+o8lh84wv71eFf0Du46nuWHIUfWnBK6CkV/G CxDtUJDrOUQZ/1n8A0A1VmqPIe48QepDvC9lfsSvu0M/xaBPK7w1J/DgJNlpZWQtVkM/ CqIdLQjry3kNooZU3lAOfgC47jandgI5Ep0rxCGuKiURZ2Y0R5Ltd6EbLKSVHBrEtF76 hFpQQaWT/ttKwURnoaXvXc6OvX4Bl3jBpS7+/jzAThz+uT0hpbrwdcD+toYNfkEtKFPX smRg== X-Gm-Message-State: AOJu0Yz6r3uL5bKdugXnlRdkEDqdAYiMBwElt+Tssnodene9p9NvicA9 OrHpgnKBj+O8/7wnKxiC9DKQqT/biX3+YVakl9E= X-Google-Smtp-Source: AGHT+IHEyvmwlf2eVfPiSAoDdPIfG5dXun5TgLUT7VyTP5HfccVVu1sF6aOTAAzb+kznGn7FsQb64g== X-Received: by 2002:a9d:6396:0:b0:6bd:749:f5cc with SMTP id w22-20020a9d6396000000b006bd0749f5ccmr2257092otk.26.1695208856006; Wed, 20 Sep 2023 04:20:56 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 09/19] target/riscv: make riscv_add_satp_mode_properties() public Date: Wed, 20 Sep 2023 08:20:10 -0300 Message-ID: <20230920112020.651006-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695209076853100001 Content-Type: text/plain; charset="utf-8" This function is used for both accelerators. Make it public, and call it from kvm_riscv_cpu_add_kvm_properties(). This will make it easier to split KVM specific code for the KVM accelerator class in the next patch. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 ++--- target/riscv/cpu.h | 1 + target/riscv/kvm.c | 1 + 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0dc9b3201d..50be127f36 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1115,7 +1115,7 @@ static void cpu_riscv_set_satp(Object *obj, Visitor *= v, const char *name, satp_map->init |=3D 1 << satp; } =20 -static void riscv_add_satp_mode_properties(Object *obj) +void riscv_add_satp_mode_properties(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); =20 @@ -1589,12 +1589,11 @@ static void riscv_cpu_add_multiext_prop_array(Objec= t *obj, static void riscv_cpu_add_user_properties(Object *obj) { #ifndef CONFIG_USER_ONLY - riscv_add_satp_mode_properties(obj); - if (kvm_enabled()) { kvm_riscv_cpu_add_kvm_properties(obj); return; } + riscv_add_satp_mode_properties(obj); #endif =20 riscv_cpu_add_misa_properties(obj); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9dc4113812..cb13464ba6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -726,6 +726,7 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_experimen= tal_exts[]; extern Property riscv_cpu_options[]; =20 void riscv_cpu_add_misa_properties(Object *cpu_obj); +void riscv_add_satp_mode_properties(Object *obj); =20 /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index e682a70311..e5e957121f 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -1323,6 +1323,7 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj) DeviceState *dev =3D DEVICE(obj); =20 riscv_init_user_properties(obj); + riscv_add_satp_mode_properties(obj); riscv_cpu_add_misa_properties(obj); =20 riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695209108; cv=none; d=zohomail.com; s=zohoarc; b=Cj0A0EIh8cF5GkNIjNxSxnzBekXEY9PhW0s5bF8bYKPI81XIbhneP2XgocG5yUS5fLDHo5EDWkVfpPk2BqGLRC7m2x5VNKLPk+ELZiApjVtFiAHMbWUSUOF7bP/pMlQlcgJ/aMpR45XUCRsEGX4rpgCHIrJfHvP1alRBq423IeY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695209108; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4iqSa97kifihOyS34EWLsGufneSccwIDqZP7TtE5e2Q=; b=JB0502eDOqHXygoLoCk4yjSij2q/Vw6PzHzc88CuQkyl9Zw8QkwMI2mL1u8nWbid96ev+OF0v+gI4BZ1Q41bv9SMWSdqgzUeUU9AiW6eAAAenT1SxHzg4rxC9H/QQPDtgr2c36Q/Cavs2ksgNe0KP3h7bMpKUwS5D9GvmqrG2n0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695209108748293.76727905462747; Wed, 20 Sep 2023 04:25:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivGR-0005hg-No; Wed, 20 Sep 2023 07:21:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivGQ-0005gZ-3u for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:02 -0400 Received: from mail-ot1-x332.google.com ([2607:f8b0:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivGO-0002Dh-G8 for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:01 -0400 Received: by mail-ot1-x332.google.com with SMTP id 46e09a7af769-6bdcbde9676so4377739a34.3 for ; Wed, 20 Sep 2023 04:21:00 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.20.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:20:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208859; x=1695813659; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4iqSa97kifihOyS34EWLsGufneSccwIDqZP7TtE5e2Q=; b=EqR9JlfI9e632rfM6pcv9J7pcEcrq2ObyjKoRgiNunArdBqtJ3GyFxg4RWfyId0uJ0 pEh3t+pDKtg3C6G24yef6FxviOyIo+kKPbuME/HCtZS/3Kp9XqdP1YKy2wxwGt5AAxdx ZIgzh3rs+/CGWZ6q8FWH+x5vrJxMCKRu7b9Ox8xsZ6oGnpGspHyPdLhuIWjeTmjS2Gsc eiS5mwAfHl3P/RXOg1Ow/HLPNPsqyZezB6Le9wOiYTRL8DYeoEg7pqHoftkOltf7r8AW PgBgsqX98h92vjt+EUyPWzVf7qBZYv4UtMPoKEdisFPWSmobg9tqp5+xFjP+QhHDwC3/ qbQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208859; x=1695813659; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4iqSa97kifihOyS34EWLsGufneSccwIDqZP7TtE5e2Q=; b=EbfoFVFISpiVdQcvySZdckOC6Y2HpN0vQB3Gv56s/7qnEYI4d8up3/Xg5lgudqDg1a MvCVu3NAJ9+F/JzW9RQ76kxuhiE6fo96agNDHcQpYKJHPBliz6yrgyyVsV/xLvBToEIU 6y9ZRZh6Ji3Ojy0ySO52WZZKo74HLVuoHZKh0K2My4r9A5mS3vJOYGncpEAAx+f5hIA1 t3W5OrFAZd5p5FkKzhpfbY69caKQh4+H34sdnuWdCfg12fsztgLs9EVP7c/q7LTasWuu r6Zv8wY9/mKeKGlH6VVfQ/dWuJJN0i0/IaQ9JdFLzPZnq//5UlMmZ0pobt9v7FE7wiwX 8fcA== X-Gm-Message-State: AOJu0YxZS/UsrSNq0Cvd9iy8lEB+51Ymkdy2pF/2XkMf9VJdPfh/lGC8 szu8h4VHYLpAizMa28O1GP52HcIlgZZ+y71jxZU= X-Google-Smtp-Source: AGHT+IEcb8XdQEI5zLF+FWFQgsPNcu5TX8hZZ0rDFMQ2Y8cqvqZ5fRTQm/XaVHp/s5YOGm0lDL3qAg== X-Received: by 2002:a9d:6f06:0:b0:6b9:1af3:3307 with SMTP id n6-20020a9d6f06000000b006b91af33307mr2184051otq.17.1695208859263; Wed, 20 Sep 2023 04:20:59 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 10/19] target/riscv: remove kvm-stub.c Date: Wed, 20 Sep 2023 08:20:11 -0300 Message-ID: <20230920112020.651006-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695209109570100001 Content-Type: text/plain; charset="utf-8" This file is not needed for some time now. Both kvm_riscv_reset_vcpu() and kvm_riscv_set_irq() have public declarations in kvm_riscv.h and are wrapped in 'if kvm_enabled()' blocks that the compiler will rip it out in non-KVM builds. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/kvm-stub.c | 30 ------------------------------ target/riscv/meson.build | 2 +- 2 files changed, 1 insertion(+), 31 deletions(-) delete mode 100644 target/riscv/kvm-stub.c diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c deleted file mode 100644 index 4e8fc31a21..0000000000 --- a/target/riscv/kvm-stub.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * QEMU KVM RISC-V specific function stubs - * - * Copyright (c) 2020 Huawei Technologies Co., Ltd - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or - * more details. - * - * You should have received a copy of the GNU General Public License along= with - * this program. If not, see . - */ -#include "qemu/osdep.h" -#include "cpu.h" -#include "kvm_riscv.h" - -void kvm_riscv_reset_vcpu(RISCVCPU *cpu) -{ - abort(); -} - -void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) -{ - abort(); -} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index f0486183fa..3323b78b84 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -24,7 +24,7 @@ riscv_ss.add(files( 'zce_helper.c', 'vcrypto_helper.c' )) -riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files(= 'kvm-stub.c')) +riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 riscv_system_ss =3D ss.source_set() riscv_system_ss.add(files( --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695209016; cv=none; d=zohomail.com; s=zohoarc; b=PzhyA1Sriueayrvkh46q0XH6R3Rjh/01Xx0n/J+dA1P/hfpTMHxcSt/vcyqWVQ7hqW9A37DTsldbuDFN+X+ApX+fpQxKD4jnnTmtsEvhv5PF7IrAT91l8m0T1LhyV5xXFObybUjALK5JksC1rtPJHddyJWlWQWZ4aS2eEBiWkQU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695209016; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yJJg/5xS5XwAgSAEim4oLXXodpGlL87OO1OMv9s7SjU=; b=CJSxVR3uCPN0wJ15gKjoeA3J/J/7fyDD2scH92IPtyBRTHvCgjjaorsBr7QMgsE20JRbYjcX55/D6XheFJlPvJWrazh6WeQ95R+qieK+RMsh8HRGFSdI/8Iu4xRPGy7jBepAhr3r7coRWSZsZ0u/XMs4j5OqHmuHWLlK60IS1cM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695209016135657.0944849953765; Wed, 20 Sep 2023 04:23:36 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivGU-0005iY-Oz; Wed, 20 Sep 2023 07:21:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivGT-0005i6-HX for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:05 -0400 Received: from mail-ot1-x329.google.com ([2607:f8b0:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivGR-0002E8-U3 for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:05 -0400 Received: by mail-ot1-x329.google.com with SMTP id 46e09a7af769-6c0f3f24c27so4026435a34.2 for ; Wed, 20 Sep 2023 04:21:03 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.20.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:21:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208862; x=1695813662; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yJJg/5xS5XwAgSAEim4oLXXodpGlL87OO1OMv9s7SjU=; b=QCvqmbFMH97uj07sP5xTJT389TiubPgvlSbWxGXv491+4ei2iA7rrMdrJN9lGVKkQ+ yO9JbHM7bwEGsifYtIUC8REg5z4VNw/OiEdEVh01npUeLIrzTUr4iSEyq4mRYek7xtOc FhsX1wSku8Nc0NsBdLiyOFxU6qg+QXtihiRyfcjbP6Vj5kn98rrEIW9Dg5ToGt3x3APF nyICch+yzX1eW25cgJUilxGOdEau5SIyLV7HVQwyID3/bdmkbQmvyL6cT/P+ddfHx37s MuAjsJs513cQmPkal30y2lGzZf2p/Vax9C3npY9UJgEmHsxl4FUflwuPjm1F7o2fqiRe +IUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208862; x=1695813662; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yJJg/5xS5XwAgSAEim4oLXXodpGlL87OO1OMv9s7SjU=; b=i8awWpL4wCwffPJs1ZdMnu22vbIHWWZAE9OLEO0c/AUdUdts3kB3YwYxADkt96HLpn S47rEzkwBFs6f5voJ69fcLx37WOnlrQBEexleJgexGHntAdU0iW+sK9x3glov+7Zi42c hOf0XoTCQQF2Vs/Bm+7jkuwF1W6HIp+JKGhrj9hf50lixh5MGatkonSPPkQeeGeWuuAd unyleRDdM0rp2XDWR738O+Xh+UiLosxuwp38CirDgt1618T2qutrWD6gSXBRsZIu7pmW 1Q7L/bMxSvr1k89OGdCxwBmw0uct48C+3W+8OJHut/kZRzohX0lcStyWajKuqumYzAU9 ELEw== X-Gm-Message-State: AOJu0Yxb6NfQ3DqTGWtYjksolLhxtvUkGRPOkSDKfrmcfDc12p+i4Tqu GZp4+297g8Guh7aK4uxvQrtB8DmvJeXg4lRav8w= X-Google-Smtp-Source: AGHT+IFi2iDsGkZhiGY/IMDf0X5FNmo9m9nE57LZbbwRDTziJUbhOLRJr+wq/qUxwrhVrtvuUqIwCg== X-Received: by 2002:a05:6830:39e1:b0:6bd:844:69d5 with SMTP id bt33-20020a05683039e100b006bd084469d5mr2089400otb.4.1695208862656; Wed, 20 Sep 2023 04:21:02 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 11/19] target/riscv: introduce KVM AccelCPUClass Date: Wed, 20 Sep 2023 08:20:12 -0300 Message-ID: <20230920112020.651006-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695209016863100001 Content-Type: text/plain; charset="utf-8" Add a KVM accelerator class like we did with TCG. The difference is that, at least for now, we won't be using a realize() implementation for this accelerator. We'll start by assiging kvm_riscv_cpu_add_kvm_properties(), renamed to kvm_cpu_instance_init(), as a 'cpu_instance_init' implementation. Change riscv_cpu_post_init() to invoke accel_cpu_instance_init(), which will go through the 'cpu_instance_init' impl of the current acceleration (if available) and execute it. The end result is that the KVM initial setup, i.e. starting registers and adding its specific properties, will be done via this hook. Add a 'tcg_enabled()' condition in riscv_cpu_post_init() to avoid calling riscv_cpu_add_user_properties() when running KVM. We'll remove this condition when the TCG accel class get its own 'cpu_instance_init' implementation. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 8 +++----- target/riscv/kvm.c | 26 ++++++++++++++++++++++++-- target/riscv/kvm_riscv.h | 1 - 3 files changed, 27 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 50be127f36..c8a19be1af 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1219,7 +1219,9 @@ static bool riscv_cpu_has_user_properties(Object *cpu= _obj) =20 static void riscv_cpu_post_init(Object *obj) { - if (riscv_cpu_has_user_properties(obj)) { + accel_cpu_instance_init(CPU(obj)); + + if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) { riscv_cpu_add_user_properties(obj); } =20 @@ -1589,10 +1591,6 @@ static void riscv_cpu_add_multiext_prop_array(Object= *obj, static void riscv_cpu_add_user_properties(Object *obj) { #ifndef CONFIG_USER_ONLY - if (kvm_enabled()) { - kvm_riscv_cpu_add_kvm_properties(obj); - return; - } riscv_add_satp_mode_properties(obj); #endif =20 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index e5e957121f..606fdab223 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -31,6 +31,7 @@ #include "sysemu/kvm_int.h" #include "cpu.h" #include "trace.h" +#include "hw/core/accel-cpu.h" #include "hw/pci/pci.h" #include "exec/memattrs.h" #include "exec/address-spaces.h" @@ -1318,8 +1319,9 @@ void kvm_riscv_aia_create(MachineState *machine, uint= 64_t group_shift, kvm_msi_via_irqfd_allowed =3D kvm_irqfds_enabled(); } =20 -void kvm_riscv_cpu_add_kvm_properties(Object *obj) +static void kvm_cpu_instance_init(CPUState *cs) { + Object *obj =3D OBJECT(RISCV_CPU(cs)); DeviceState *dev =3D DEVICE(obj); =20 riscv_init_user_properties(obj); @@ -1331,7 +1333,7 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj) riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); =20 for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { - /* Check if KVM created the property already */ + /* Check if we have a specific KVM handler for the option */ if (object_property_find(obj, prop->name)) { continue; } @@ -1339,6 +1341,26 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj) } } =20 +static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_instance_init =3D kvm_cpu_instance_init; +} + +static const TypeInfo kvm_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("kvm"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D kvm_cpu_accel_class_init, + .abstract =3D true, +}; +static void kvm_cpu_accel_register_types(void) +{ + type_register_static(&kvm_cpu_accel_type_info); +} +type_init(kvm_cpu_accel_register_types); + static void riscv_host_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index da9630c4af..8329cfab82 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -19,7 +19,6 @@ #ifndef QEMU_KVM_RISCV_H #define QEMU_KVM_RISCV_H =20 -void kvm_riscv_cpu_add_kvm_properties(Object *obj); void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695209034; cv=none; d=zohomail.com; s=zohoarc; b=ceIaFWjhCCnEyDweQU17V28YR0T9mhsxFg8esjpt4wbMsGCXK5NXrQjMMlFONZuu2c9DIxz0do3VFv76DZXd99awAQa0fX0flyw1KjyVFK85+cKuaA1PrIhfs9M6ulVYmP/4SqwN8Djfkj5wRraZDf7AV0mlU882+ghzdICHNd4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695209034; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KyXIVQ6oXB882FE4SAxwRzZIe3agCcsRwcqsPA0bJps=; b=UIh/zVfmRBQx55/I+7wElKHW15CRJ0wKlrL7MuNaFtEiOaM5fVKxnozxboK5TUAtTog8ONTtDWAc0Kh5vATcvsYVby1lBQXu35S3VwH4/RWYShOi2QvdB52uZ8DtTGo9TMTCSI7SlTNJHPdirVTGLAcLZ6Y0JVNSsRJIGEO0sjM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169520903457432.92465422816258; Wed, 20 Sep 2023 04:23:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivGY-0005k8-VT; Wed, 20 Sep 2023 07:21:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivGW-0005jY-Vk for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:08 -0400 Received: from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivGV-0002EY-CM for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:08 -0400 Received: by mail-oi1-x230.google.com with SMTP id 5614622812f47-3add37de892so1888549b6e.1 for ; Wed, 20 Sep 2023 04:21:07 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.21.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:21:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208866; x=1695813666; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KyXIVQ6oXB882FE4SAxwRzZIe3agCcsRwcqsPA0bJps=; b=QO+I+b6NHOW5Xr0AvWKGX0Ovi2rFkFjpqUnZxlDJvSnviZr2UWk8TxZkL3elOZ2ly0 oX37hJKwK7Pub1LVEnC9kiVyQ0Wg6uIc75Uqe1ScghLehFpiAKFtSJjol2nNgj4OwFlS 2b6tI0sFKO3u4Jbc9Ug8VQF8h5yyV+FYxzNSr4gqqG34NYr4il1RMuyN6HsD7JejM+JN y7n4NECAGLuDUGc6m+gFw5kbjZOY0dxL8/vywRBiVsx+7wwPt4UgJcEVJsJnYVLdkSHE 9XbnolbAATr1OAOjMcYfl3mJV8XGISG3RuSeanO3WVeB17lPLczZVjsq5i+2sHTvJw0Y 2Y7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208866; x=1695813666; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KyXIVQ6oXB882FE4SAxwRzZIe3agCcsRwcqsPA0bJps=; b=mM2CfHMwAb1IBwDBmBHKeRQoDhk3/76XAsgSX8RVv1zUXvBRUgN0HKCWCaUXieRyVK QfI+HIIzScb2ViDuELldJX0BOhw9LmDeM1Fz3QF8K5+Y55vmfIE1F+LfvvZlZJLdIzOq wXieTN+Y8lOnyW04TebRoKBPJg2PwQsSt+4X35KXkpZgMXXvsmDn2YIIHhW1WlWPbVrr Bh37kZyhTR3nzYqXBIT18dMjCMlggVd0pdUxvwkYFoS8RZzHdIEBZPKDo4dlmIHAhuh7 3B0y2v7FCG3ngE8njVP3rmGO0Q/nopNUG4uw7ggr/oHHrs8SSvneAhNquWpFRPyQGuOQ 5iSA== X-Gm-Message-State: AOJu0YxBY/WCoPxoS4y2t4XRw4BUBxl4Xf1w7dzoDm0kR281XM1YnzXj mB3cevvkLlFBbEGF/hI1L/kwIIQy/WRuI1tikdI= X-Google-Smtp-Source: AGHT+IFtcjxZp6AVUCBuVeXKOZGKP7nlSFfkPnzSwlZ9DANzdiearRf7pBM1VX83L8NsZp6qyaBX7Q== X-Received: by 2002:a05:6870:4411:b0:1d5:a955:8bb3 with SMTP id u17-20020a056870441100b001d5a9558bb3mr2180527oah.43.1695208865984; Wed, 20 Sep 2023 04:21:05 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 12/19] target/riscv: move KVM only files to kvm subdir Date: Wed, 20 Sep 2023 08:20:13 -0300 Message-ID: <20230920112020.651006-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695209035398100001 Content-Type: text/plain; charset="utf-8" Move the files to a 'kvm' dir to promote more code separation between accelerators and making our lives easier supporting build options such as --disable-tcg. Rename kvm.c to kvm-cpu.c to keep it in line with its TCG counterpart. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- hw/intc/riscv_aplic.c | 2 +- hw/riscv/virt.c | 2 +- target/riscv/cpu.c | 2 +- target/riscv/{kvm.c =3D> kvm/kvm-cpu.c} | 0 target/riscv/{ =3D> kvm}/kvm_riscv.h | 0 target/riscv/kvm/meson.build | 1 + target/riscv/meson.build | 2 +- 7 files changed, 5 insertions(+), 4 deletions(-) rename target/riscv/{kvm.c =3D> kvm/kvm-cpu.c} (100%) rename target/riscv/{ =3D> kvm}/kvm_riscv.h (100%) create mode 100644 target/riscv/kvm/meson.build diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 99aae8ccbe..c677b5cfbb 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -32,7 +32,7 @@ #include "target/riscv/cpu.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" -#include "kvm_riscv.h" +#include "kvm/kvm_riscv.h" #include "migration/vmstate.h" =20 #define APLIC_MAX_IDC (1UL << 14) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 5edc1d98d2..9de578c756 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -35,7 +35,7 @@ #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" -#include "kvm_riscv.h" +#include "kvm/kvm_riscv.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/riscv_aplic.h" #include "hw/intc/riscv_imsic.h" diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c8a19be1af..51567c2f12 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -33,7 +33,7 @@ #include "fpu/softfloat-helpers.h" #include "sysemu/kvm.h" #include "sysemu/tcg.h" -#include "kvm_riscv.h" +#include "kvm/kvm_riscv.h" #include "tcg/tcg.h" =20 /* RISC-V CPU definitions */ diff --git a/target/riscv/kvm.c b/target/riscv/kvm/kvm-cpu.c similarity index 100% rename from target/riscv/kvm.c rename to target/riscv/kvm/kvm-cpu.c diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm/kvm_riscv.h similarity index 100% rename from target/riscv/kvm_riscv.h rename to target/riscv/kvm/kvm_riscv.h diff --git a/target/riscv/kvm/meson.build b/target/riscv/kvm/meson.build new file mode 100644 index 0000000000..7e92415091 --- /dev/null +++ b/target/riscv/kvm/meson.build @@ -0,0 +1 @@ +riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm-cpu.c')) diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 3323b78b84..c53962215f 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -24,7 +24,6 @@ riscv_ss.add(files( 'zce_helper.c', 'vcrypto_helper.c' )) -riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 riscv_system_ss =3D ss.source_set() riscv_system_ss.add(files( @@ -39,6 +38,7 @@ riscv_system_ss.add(files( )) =20 subdir('tcg') +subdir('kvm') =20 target_arch +=3D {'riscv': riscv_ss} target_softmmu_arch +=3D {'riscv': riscv_system_ss} --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695208957; cv=none; d=zohomail.com; s=zohoarc; b=dj7wHoKC2RGTJwHBtqLcwIKoPZzYPabrCnQGT5gK07+/rppiRgqZivDG1u9cAK2vQrrHhHnwAtq5Jn7Jruc47vVylMu8RIzeZxc8N+69NgFtyEXiVMvCHX1Cax25l2jFFztw4qBZszaKemGFokSqOCdu2/CA79o+4U+LEwkKUnU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695208957; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2SRAOYy3nrauylPPbNRfnwD+GnkGS9IdCDiSB1G4rb0=; b=FEUuF9t2Dk2lK/nzsRHqfI0asDFOV4gSUnmcZA+QpYh9g2srXc7N6EWprcATrlh+aL0AK6y9uN86Or27i7D2WthNDYQu+GbnwFJiKyRJdSw1Fz3m3/xLY/XWo8tlR14+JiXN8Np/Wxzs9IKnUH22sFtqckq9MrsJfgttANvom3I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695208957107874.1799854373108; Wed, 20 Sep 2023 04:22:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivGc-0005l7-Jz; Wed, 20 Sep 2023 07:21:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivGa-0005kg-JG for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:12 -0400 Received: from mail-ot1-x333.google.com ([2607:f8b0:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivGY-0002F5-Tb for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:12 -0400 Received: by mail-ot1-x333.google.com with SMTP id 46e09a7af769-6c21b2c6868so3874177a34.1 for ; Wed, 20 Sep 2023 04:21:10 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.21.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:21:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208869; x=1695813669; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2SRAOYy3nrauylPPbNRfnwD+GnkGS9IdCDiSB1G4rb0=; b=QsswpfeW4g55b6A+fOGea1+VcnhFh+Kkw/+ry4i5luaX5JRZY3WeU5iCNT3pGm+TlR fu0EqpVBI4w+ugfV3B+QAPEiPgl3yb0gKeYyzSZ7QLT4srXRcwUffRnRSUMZzPW5oTRF ETCoIjd8ORnfLYc7jdfLLlvvcE/AvLQyvK8LQopvuw2LR29mDyvxYi3ugCuBkOa7YGI+ 5/rJRJ4TiMGoSqSKk8wr22RmqiKSkgIIye4GXOHGx2GLx8lizzTNozQEgCru328pOEui DpUZlhGfGa8wwP42v2CN3etkv0NO90U/RnvaTKuT1VEbtiHX2gM9VhaP2e0FqkjJP/sg dU+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208869; x=1695813669; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2SRAOYy3nrauylPPbNRfnwD+GnkGS9IdCDiSB1G4rb0=; b=lhP9XRKI2ouApKFpu0nJDprAxTQoUxt+1VlE4JDi21WtVXMmmbfU/42ORWBOUIWMjo tE+V5ZakLTaDLRHCOUHYdpZuFuSq0LEnyOqWmuJWAPvW1l5VNT5/EJyBb3eb830ncGZU LZqgAfxTIMJ+fRNJWqW64pFNc7DycECpFIwabUoyLBxAeXtlBuY7K+n3W8Se452I7DBt nNdDvjJMVafdc8ZVAhNctChZS+kZKLimo3xlfQTRhpBIKx3FVcwjO6cjWGgz3oTN0tEl b2JbiL3xpwd/PgSMQd8g5Ji2+k42g3UXJk4+uyosg0/VFSjoO8bp8OhFg79MiRhUFEz7 y2pA== X-Gm-Message-State: AOJu0YxtMQpIPCCUDOTsU8bvNdcv82t4VAfUUJY9D1maaJe7L/V6wwT+ kocSxzLyPwF6ABaODNIhVEPTFX69+XlU63a1h4w= X-Google-Smtp-Source: AGHT+IH1hrzFCHqfl6xf8PV2tvjLRSiRk+7xP6qlaICg90su5uVfXdA8b235eDB5gzhZQajuTqRwYw== X-Received: by 2002:a05:6830:208b:b0:6bf:17d3:4268 with SMTP id y11-20020a056830208b00b006bf17d34268mr2172358otq.25.1695208869370; Wed, 20 Sep 2023 04:21:09 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 13/19] target/riscv/kvm: do not use riscv_cpu_add_misa_properties() Date: Wed, 20 Sep 2023 08:20:14 -0300 Message-ID: <20230920112020.651006-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695208957772100006 Content-Type: text/plain; charset="utf-8" riscv_cpu_add_misa_properties() is being used to fill the missing KVM MISA properties but it is a TCG helper that was adapted to do so. We'll move it to tcg-cpu.c in the next patches, meaning that KVM needs to fill the remaining MISA properties on its own. Do not use riscv_cpu_add_misa_properties(). Let's create a new array with all available MISA bits we support that can be read by KVM. The array is zero terminate to allow us to iterate through it without knowing its size. Then, inside kvm_riscv_add_cpu_user_properties(), we'll create all KVM MISA properties as usual and then use this array to add any missing MISA properties with the riscv_cpu_add_kvm_unavail_prop() helper. Note that we're creating misa_bits[], and not using the existing 'riscv_single_letter_exts[]', because the latter is tuned for riscv,isa related functions and it doesn't have all MISA bits we support. Commit 0e2c377023 ("target/riscv: misa to ISA string conversion fix") has the full context. While we're at it, move both satp and the multi-letter extension properties to kvm_riscv_add_cpu_user_properties() as well. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 3 ++- target/riscv/kvm/kvm-cpu.c | 22 ++++++++++++++-------- 3 files changed, 18 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 51567c2f12..665c21af6a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -38,6 +38,8 @@ =20 /* RISC-V CPU definitions */ static const char riscv_single_letter_exts[] =3D "IEMAFDQCPVH"; +const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF, RVD, RVV, + RVC, RVS, RVU, RVH, RVJ, RVG, 0}; =20 struct isa_ext_data { const char *name; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index cb13464ba6..7235eafc1a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -43,7 +43,7 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) =20 /* - * Consider updating misa_ext_info_arr[] and misa_ext_cfgs[] + * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] * when adding new MISA bits here. */ #define RVI RV('I') @@ -60,6 +60,7 @@ #define RVJ RV('J') #define RVG RV('G') =20 +extern const uint32_t misa_bits[]; const char *riscv_get_misa_ext_name(uint32_t bit); const char *riscv_get_misa_ext_description(uint32_t bit); =20 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 606fdab223..c6615cb807 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -396,6 +396,8 @@ static void kvm_riscv_add_cpu_user_properties(Object *c= pu_obj) { int i; =20 + riscv_add_satp_mode_properties(cpu_obj); + for (i =3D 0; i < ARRAY_SIZE(kvm_misa_ext_cfgs); i++) { KVMCPUConfig *misa_cfg =3D &kvm_misa_ext_cfgs[i]; int bit =3D misa_cfg->offset; @@ -411,6 +413,11 @@ static void kvm_riscv_add_cpu_user_properties(Object *= cpu_obj) misa_cfg->description); } =20 + for (i =3D 0; misa_bits[i] !=3D 0; i++) { + const char *ext_name =3D riscv_get_misa_ext_name(misa_bits[i]); + riscv_cpu_add_kvm_unavail_prop(cpu_obj, ext_name); + } + for (i =3D 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) { KVMCPUConfig *multi_cfg =3D &kvm_multi_ext_cfgs[i]; =20 @@ -427,6 +434,10 @@ static void kvm_riscv_add_cpu_user_properties(Object *= cpu_obj) object_property_add(cpu_obj, "cboz_blocksize", "uint16", NULL, kvm_cpu_set_cbomz_blksize, NULL, &kvm_cboz_blocksize); + + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_extensions); + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_vendor_exts); + riscv_cpu_add_kvm_unavail_prop_array(cpu_obj, riscv_cpu_experimental_e= xts); } =20 static int kvm_riscv_get_regs_core(CPUState *cs) @@ -801,7 +812,7 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, = KVMScratchCPU *kvmcpu) } } =20 -static void riscv_init_user_properties(Object *cpu_obj) +static void riscv_init_kvm_registers(Object *cpu_obj) { RISCVCPU *cpu =3D RISCV_CPU(cpu_obj); KVMScratchCPU kvmcpu; @@ -810,7 +821,6 @@ static void riscv_init_user_properties(Object *cpu_obj) return; } =20 - kvm_riscv_add_cpu_user_properties(cpu_obj); kvm_riscv_init_machine_ids(cpu, &kvmcpu); kvm_riscv_init_misa_ext_mask(cpu, &kvmcpu); kvm_riscv_init_multiext_cfg(cpu, &kvmcpu); @@ -1324,13 +1334,9 @@ static void kvm_cpu_instance_init(CPUState *cs) Object *obj =3D OBJECT(RISCV_CPU(cs)); DeviceState *dev =3D DEVICE(obj); =20 - riscv_init_user_properties(obj); - riscv_add_satp_mode_properties(obj); - riscv_cpu_add_misa_properties(obj); + riscv_init_kvm_registers(obj); =20 - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions); - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_vendor_exts); - riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_experimental_exts); + kvm_riscv_add_cpu_user_properties(obj); =20 for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { /* Check if we have a specific KVM handler for the option */ --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695209059; cv=none; d=zohomail.com; s=zohoarc; b=hMF2O316+0yxkWm3t+uSQxtJm2ECqIAU9ZXxFp5k6wDbjUlnhzslhRqhYnLbE2hpVDK/HSeoGks6FkoRWpht+Ru/RNhJSV4Y2Cz1oAmzMFAkrxCyPijSkPXibdsp7FcM3wsY+/AlZFbL/wUw0mMHERI8/rG2y8G2BOvbSFU0WMU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695209059; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TDUcGph4CZ8HDjwOAIL5zgaK26mCNRaSbKQqrKCL4Kw=; b=Ix0jroKaSbtCQc8OXhU4KJ1fsaS0bQLah1pgiusnozwRINfNmN9bk7rVNRaSlIcSf13bO/wPCCUYg2padgjlWd9HfzgWgPjX22VySJDm6ncvX7uNefiNNEXw0ajRG4bxKqa477NhI7k8UVK61HigTmIsUPbILoMK3E0GpedpOJg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695209059086845.5140635292319; Wed, 20 Sep 2023 04:24:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivGf-0005wt-VN; Wed, 20 Sep 2023 07:21:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivGe-0005pB-4g for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:16 -0400 Received: from mail-ot1-x32c.google.com ([2607:f8b0:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivGb-0002Fi-V9 for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:15 -0400 Received: by mail-ot1-x32c.google.com with SMTP id 46e09a7af769-6bf04263dc8so4456127a34.3 for ; Wed, 20 Sep 2023 04:21:13 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.21.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:21:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208872; x=1695813672; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TDUcGph4CZ8HDjwOAIL5zgaK26mCNRaSbKQqrKCL4Kw=; b=DKPp746UQcx6cymDyZBbAzyhB5cXbU1QKfPGFWWAJqJY+GkicXD5K5ImosPPVp3MFg nyy9dE4QyFNPMAiVlz02BavG9SsHXVZ52PakI9zgVdjqbxW92/9+xUO2OyrZVhqpaT0s UsejzIJN994j7/znq/InoqAQR/4/rdvAT7Iij+rieerRX92y43xf0MoOioWyhP2kP7ph ADnvjHxfmPlCDg1fZp9cbENGnG+NwN5PZ+tWB+onbPexYWFSnU43R+fdsJJcj2NyJVun yHl3YqEMfUuOdbL2Cva7CdAhxIlAKLmPNL+jTeLlp+wzjnt+qY+bWc+MaIU/FlmeebSU 8y9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208872; x=1695813672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TDUcGph4CZ8HDjwOAIL5zgaK26mCNRaSbKQqrKCL4Kw=; b=k0epxelxpxNdX93IaVBrQ4Ccj3AdU7m72amnA/SkqeN8qb5oYO21tDx0AazEqid5fX taXmPsBntWf1DUsvokr/ngPMlGKnMiKWs/z3NSP9heDhR91Eu+qFzDNte2fCKHtOrE6+ RLSHUFZjSqKo8LT5aW/dkDFUfdiJHXKi+6yfK3LRrC6GkadQG1zoYl24misc21mL/tfM CWkDaTBjH0iMm72Ns1iXgjDO7WfCnTvYtWmLQfK7m+QKRaRwP1WPHjNaeDcCFq+nhPJX bCkcoGP81/mNQRg36Y39X1h9B39C7+4Y012gs1O/S4wo6gC9cu9r7y8BHrwJsk1eTCzu E1zg== X-Gm-Message-State: AOJu0YxBHLCDQoCztL7Kge+2jIUPzWgVz5d8bi33T77AAX8H1BFeMPa+ ZGuHpo9ZHA70ETCY76bL8FkpQuYTiyQsw8EeCKs= X-Google-Smtp-Source: AGHT+IHYH2VtI1x766/TL5qL8sbWEMMp12O/8Tr/uP1vfglsWrGdFgvX4wyd/0Q5EAvrZll3DYxM+Q== X-Received: by 2002:a9d:6b14:0:b0:6b9:4d79:e08a with SMTP id g20-20020a9d6b14000000b006b94d79e08amr2319905otp.32.1695208872658; Wed, 20 Sep 2023 04:21:12 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 14/19] target/riscv/cpu.c: export set_misa() Date: Wed, 20 Sep 2023 08:20:15 -0300 Message-ID: <20230920112020.651006-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695209060552100003 We'll move riscv_init_max_cpu_extensions() to tcg-cpu.c in the next patch and set_misa() needs to be usable from there. Rename it to riscv_cpu_set_misa() and make it public. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 34 ++++++++++++++++++---------------- target/riscv/cpu.h | 1 + 2 files changed, 19 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 665c21af6a..cf191d576e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -294,7 +294,7 @@ const char *riscv_cpu_get_trap_name(target_ulong cause,= bool async) } } =20 -static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) +void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) { env->misa_mxl_max =3D env->misa_mxl =3D mxl; env->misa_ext_mask =3D env->misa_ext =3D ext; @@ -399,9 +399,9 @@ static void riscv_any_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; #if defined(TARGET_RISCV32) - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | = RVU); #elif defined(TARGET_RISCV64) - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | = RVU); #endif =20 #ifndef CONFIG_USER_ONLY @@ -428,7 +428,7 @@ static void riscv_max_cpu_init(Object *obj) #ifdef TARGET_RISCV32 mlx =3D MXL_RV32; #endif - set_misa(env, mlx, 0); + riscv_cpu_set_misa(env, mlx, 0); env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), mlx =3D=3D MXL_RV32 ? @@ -441,7 +441,7 @@ static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, MXL_RV64, 0); + riscv_cpu_set_misa(env, MXL_RV64, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -453,7 +453,8 @@ static void rv64_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + riscv_cpu_set_misa(env, MXL_RV64, + RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); @@ -471,7 +472,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -488,7 +489,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); + riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_11_0; =20 cpu->cfg.ext_zfa =3D true; @@ -519,7 +520,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); + riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); env->priv_ver =3D PRIV_VERSION_1_12_0; =20 /* Enable ISA extensions */ @@ -564,7 +565,7 @@ static void rv128_base_cpu_init(Object *obj) } CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, MXL_RV128, 0); + riscv_cpu_set_misa(env, MXL_RV128, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -576,7 +577,7 @@ static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ - set_misa(env, MXL_RV32, 0); + riscv_cpu_set_misa(env, MXL_RV32, 0); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -588,7 +589,8 @@ static void rv32_sifive_u_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + riscv_cpu_set_misa(env, MXL_RV32, + RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); @@ -606,7 +608,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -623,7 +625,7 @@ static void rv32_ibex_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_11_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -641,7 +643,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); + riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -1618,7 +1620,7 @@ static void riscv_init_max_cpu_extensions(Object *obj) const RISCVCPUMultiExtConfig *prop; =20 /* Enable RVG, RVJ and RVV that are disabled by default */ - set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); + riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV= ); =20 for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { isa_ext_update_enabled(cpu, prop->offset, true); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7235eafc1a..9ec0805596 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -713,6 +713,7 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext= _offset, bool en); bool cpu_cfg_ext_is_user_set(uint32_t ext_offset); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); int cpu_cfg_ext_get_min_version(uint32_t ext_offset); +void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); =20 typedef struct RISCVCPUMultiExtConfig { --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695208977; cv=none; d=zohomail.com; s=zohoarc; b=IABI5F0LbnODPNRlZd8JiBLqjwgwvERWJP0ANpC/lhgHMYlCDwSEJAqbVa/aXW+1ad9+9ACcHmKIMKuTMg8hktSBVkDBTS+4i/xqmJmdhuWZ1E3wYYHZC9l8W5RVoTGg6gqVPZODQKrS9PrL1O/t3cX8H1VSazONdp70kA/0zUM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695208977; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8fTIARqf/+AdW9snvxl+EkvuKgUqraZHzDTf8qZJ9YA=; b=NELSXREsB+m5MnWbOS+oCQ/VqAusaMZOGjo+gYBcjxaf8UwofsNqZ/sAe0COwtP4eK8MofPa8UfpJR6mmPsTMnPwBQsH/3KBkWIgLiDq6EdWtOb06/3IqXADJu985A8D8S2sjdmGh7fWX/OLtNDj0oOi0n6oFD0gtN1jNhJBpaM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695208977159168.93513500227857; Wed, 20 Sep 2023 04:22:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivGk-0006Jf-Go; Wed, 20 Sep 2023 07:21:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivGi-00067t-Ki for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:20 -0400 Received: from mail-oo1-xc33.google.com ([2607:f8b0:4864:20::c33]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivGg-0002GR-EC for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:20 -0400 Received: by mail-oo1-xc33.google.com with SMTP id 006d021491bc7-575f45e255dso3835136eaf.2 for ; Wed, 20 Sep 2023 04:21:17 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.21.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:21:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208876; x=1695813676; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8fTIARqf/+AdW9snvxl+EkvuKgUqraZHzDTf8qZJ9YA=; b=CccjhtR2rBT2HaLGc7Z+BaQlwjqP+LaOtGPGMD+yqvgdHnHa4IqzsG/kN6ncuHxLNv mRYw2vQO3Mog6b6KhNxf5L8tMYtVQoGOKwWBmKOJrr47FD8ALqhP66eesqO0sLk8yT00 /JjX3Xw5ZJJX1OzX33dUIzi+dG1pvAquYNBF+fyZBckJ9uidRbZFU06nPdL3DTFmbxkR a7Hepne/5s8DN+HWJRAz5UHdM4TPtCMHHeKC7YAz1zJL/IlNZTHR4gjV1isdEcOpdPKj +VwtCcS7Ao1RI8Db1Sxce597YwiAg147Rt3ns/WJ1TsIuMpWOHfP+iTxZbUyB3QBlGdt aZGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208876; x=1695813676; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8fTIARqf/+AdW9snvxl+EkvuKgUqraZHzDTf8qZJ9YA=; b=CXffecwTA3iFIODERYB2KbLtCXXP+rcUQf42+fpvADlwkI+z7Yx6JlIBN+A3oJeHLX 9j6pHI3SrTZhCYEU402XRZ4KRKPFm2SknSu1zzU8mkHgyh1qLbY1udlxmPmeEFSYKFm7 pwN5LDZGNWn7ZsZVX2N/yQ+iLeGSxTaboAhrk8/2mx0mL/Q2KvNVJLxLsGzN/Mr4CGFg 7AqxMNMFlM/8f9QGWwrN824+DQXg+rsfhj+zGqMW1StHvW1AlDMfbDy9bGqTtjClOWJW DlLkHSpKoYF+97yqH/UPqgg7xEELIY2HQ0Jm0Mx9XbSkZT5Ag5zUTr5xxiWJv4MAwoWp MUCw== X-Gm-Message-State: AOJu0YyH8z5rn0wo/+7SWf3ZsvFePcPn/G9boXza/PdY/Sp7x8Vd6PnA pAcF16YX4cL4Tf0Hezb7qIm8Rg2VKvkNaGvbotM= X-Google-Smtp-Source: AGHT+IHxvs2fWiHIMUw+P8AR3P+cgHxFG2euBj4Ol0uaTC/7j2mzWMBKBFLH7RxtHJDcWn8dgn7F1g== X-Received: by 2002:a05:6870:1651:b0:1be:dbd2:2bfa with SMTP id c17-20020a056870165100b001bedbd22bfamr2224239oae.20.1695208876045; Wed, 20 Sep 2023 04:21:16 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 15/19] target/riscv/tcg: introduce tcg_cpu_instance_init() Date: Wed, 20 Sep 2023 08:20:16 -0300 Message-ID: <20230920112020.651006-16-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c33; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695208979265100003 Content-Type: text/plain; charset="utf-8" tcg_cpu_instance_init() will be the 'cpu_instance_init' impl for the TCG accelerator. It'll be called from within riscv_cpu_post_init(), via accel_cpu_instance_init(), similar to what happens with KVM. In fact, to preserve behavior, the implementation will be similar to what riscv_cpu_post_init() already does. In this patch we'll move riscv_cpu_add_user_properties() and riscv_init_max_cpu_extensions() and all their dependencies to tcg-cpu.c. All multi-extension properties code was moved. The 'multi_ext_user_opts' hash table was also moved to tcg-cpu.c since it's a TCG only structure, meaning that we won't have to worry about initializing a TCG hash table when running a KVM CPU anymore. riscv_cpu_add_user_properties() will remain in cpu.c for now due to how much code it requires to be moved at the same time. We'll do that in the next patch. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 150 ------------------------------------- target/riscv/cpu.h | 1 - target/riscv/tcg/tcg-cpu.c | 149 ++++++++++++++++++++++++++++++++++++ 3 files changed, 149 insertions(+), 151 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cf191d576e..8616c9e2f5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -162,9 +162,6 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaC= ondOps), }; =20 -/* Hash that stores user set extensions */ -static GHashTable *multi_ext_user_opts; - bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) { bool *ext_enabled =3D (void *)&cpu->cfg + ext_offset; @@ -194,12 +191,6 @@ int cpu_cfg_ext_get_min_version(uint32_t ext_offset) g_assert_not_reached(); } =20 -bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) -{ - return g_hash_table_contains(multi_ext_user_opts, - GUINT_TO_POINTER(ext_offset)); -} - const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -280,9 +271,6 @@ static const char * const riscv_intr_names[] =3D { "reserved" }; =20 -static void riscv_cpu_add_user_properties(Object *obj); -static void riscv_init_max_cpu_extensions(Object *obj); - const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { if (async) { @@ -1206,32 +1194,9 @@ static bool riscv_cpu_is_dynamic(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; } =20 -static bool riscv_cpu_has_max_extensions(Object *cpu_obj) -{ - return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) !=3D NULL; -} - -static bool riscv_cpu_has_user_properties(Object *cpu_obj) -{ - if (kvm_enabled() && - object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) !=3D NULL) { - return true; - } - - return riscv_cpu_is_dynamic(cpu_obj); -} - static void riscv_cpu_post_init(Object *obj) { accel_cpu_instance_init(CPU(obj)); - - if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) { - riscv_cpu_add_user_properties(obj); - } - - if (riscv_cpu_has_max_extensions(obj)) { - riscv_init_max_cpu_extensions(obj); - } } =20 static void riscv_cpu_init(Object *obj) @@ -1244,8 +1209,6 @@ static void riscv_cpu_init(Object *obj) qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); #endif /* CONFIG_USER_ONLY */ - - multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); } =20 typedef struct RISCVCPUMisaExtConfig { @@ -1531,119 +1494,6 @@ Property riscv_cpu_options[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 -static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, - void *opaque, Error **errp) -{ - const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; - bool value; - - if (!visit_type_bool(v, name, &value, errp)) { - return; - } - - isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value); - - g_hash_table_insert(multi_ext_user_opts, - GUINT_TO_POINTER(multi_ext_cfg->offset), - (gpointer)value); -} - -static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, - void *opaque, Error **errp) -{ - const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; - bool value =3D isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offse= t); - - visit_type_bool(v, name, &value, errp); -} - -static void cpu_add_multi_ext_prop(Object *cpu_obj, - const RISCVCPUMultiExtConfig *multi_cfg) -{ - object_property_add(cpu_obj, multi_cfg->name, "bool", - cpu_get_multi_ext_cfg, - cpu_set_multi_ext_cfg, - NULL, (void *)multi_cfg); - - /* - * Set def val directly instead of using - * object_property_set_bool() to save the set() - * callback hash for user inputs. - */ - isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, - multi_cfg->enabled); -} - -static void riscv_cpu_add_multiext_prop_array(Object *obj, - const RISCVCPUMultiExtConfig *arra= y) -{ - const RISCVCPUMultiExtConfig *prop; - - g_assert(array); - - for (prop =3D array; prop && prop->name; prop++) { - cpu_add_multi_ext_prop(obj, prop); - } -} - -/* - * Add CPU properties with user-facing flags. - * - * This will overwrite existing env->misa_ext values with the - * defaults set via riscv_cpu_add_misa_properties(). - */ -static void riscv_cpu_add_user_properties(Object *obj) -{ -#ifndef CONFIG_USER_ONLY - riscv_add_satp_mode_properties(obj); -#endif - - riscv_cpu_add_misa_properties(obj); - - riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); - riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); - riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); - - for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { - qdev_property_add_static(DEVICE(obj), prop); - } -} - -/* - * The 'max' type CPU will have all possible ratified - * non-vendor extensions enabled. - */ -static void riscv_init_max_cpu_extensions(Object *obj) -{ - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - const RISCVCPUMultiExtConfig *prop; - - /* Enable RVG, RVJ and RVV that are disabled by default */ - riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV= ); - - for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { - isa_ext_update_enabled(cpu, prop->offset, true); - } - - /* set vector version */ - env->vext_ver =3D VEXT_VERSION_1_00_0; - - /* Zfinx is not compatible with F. Disable it */ - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); - - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); - - if (env->misa_mxl !=3D MXL_RV32) { - isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); - } -} - static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9ec0805596..01cbcbe119 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -710,7 +710,6 @@ enum riscv_pmu_event_idx { =20 /* used by tcg/tcg-cpu.c*/ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); -bool cpu_cfg_ext_is_user_set(uint32_t ext_offset); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); int cpu_cfg_ext_get_min_version(uint32_t ext_offset); void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e480b9f726..5d71ff2cce 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -24,6 +24,7 @@ #include "pmu.h" #include "time_helper.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "qemu/accel.h" #include "qemu/error-report.h" #include "qemu/log.h" @@ -31,6 +32,15 @@ #include "hw/core/tcg-cpu-ops.h" #include "tcg/tcg.h" =20 +/* Hash that stores user set extensions */ +static GHashTable *multi_ext_user_opts; + +static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) +{ + return g_hash_table_contains(multi_ext_user_opts, + GUINT_TO_POINTER(ext_offset)); +} + static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -570,6 +580,144 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **e= rrp) return true; } =20 +static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value); + + g_hash_table_insert(multi_ext_user_opts, + GUINT_TO_POINTER(multi_ext_cfg->offset), + (gpointer)value); +} + +static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, + void *opaque, Error **errp) +{ + const RISCVCPUMultiExtConfig *multi_ext_cfg =3D opaque; + bool value =3D isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offse= t); + + visit_type_bool(v, name, &value, errp); +} + +static void cpu_add_multi_ext_prop(Object *cpu_obj, + const RISCVCPUMultiExtConfig *multi_cfg) +{ + object_property_add(cpu_obj, multi_cfg->name, "bool", + cpu_get_multi_ext_cfg, + cpu_set_multi_ext_cfg, + NULL, (void *)multi_cfg); + + /* + * Set def val directly instead of using + * object_property_set_bool() to save the set() + * callback hash for user inputs. + */ + isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, + multi_cfg->enabled); +} + +static void riscv_cpu_add_multiext_prop_array(Object *obj, + const RISCVCPUMultiExtConfig *arra= y) +{ + const RISCVCPUMultiExtConfig *prop; + + g_assert(array); + + for (prop =3D array; prop && prop->name; prop++) { + cpu_add_multi_ext_prop(obj, prop); + } +} + +/* + * Add CPU properties with user-facing flags. + * + * This will overwrite existing env->misa_ext values with the + * defaults set via riscv_cpu_add_misa_properties(). + */ +static void riscv_cpu_add_user_properties(Object *obj) +{ +#ifndef CONFIG_USER_ONLY + riscv_add_satp_mode_properties(obj); +#endif + + riscv_cpu_add_misa_properties(obj); + + riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); + riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); + riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); + + for (Property *prop =3D riscv_cpu_options; prop && prop->name; prop++)= { + qdev_property_add_static(DEVICE(obj), prop); + } +} + +/* + * The 'max' type CPU will have all possible ratified + * non-vendor extensions enabled. + */ +static void riscv_init_max_cpu_extensions(Object *obj) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + const RISCVCPUMultiExtConfig *prop; + + /* Enable RVG, RVJ and RVV that are disabled by default */ + riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV= ); + + for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { + isa_ext_update_enabled(cpu, prop->offset, true); + } + + /* set vector version */ + env->vext_ver =3D VEXT_VERSION_1_00_0; + + /* Zfinx is not compatible with F. Disable it */ + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); + + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); + + if (env->misa_mxl !=3D MXL_RV32) { + isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); + } +} + +static bool riscv_cpu_has_max_extensions(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) !=3D NULL; +} + +static bool riscv_cpu_has_user_properties(Object *cpu_obj) +{ + return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; +} + +static void tcg_cpu_instance_init(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + Object *obj =3D OBJECT(cpu); + + if (riscv_cpu_has_user_properties(obj)) { + multi_ext_user_opts =3D g_hash_table_new(NULL, g_direct_equal); + riscv_cpu_add_user_properties(obj); + } + + if (riscv_cpu_has_max_extensions(obj)) { + riscv_init_max_cpu_extensions(obj); + } +} + static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) { /* @@ -588,6 +736,7 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, v= oid *data) AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); =20 acc->cpu_class_init =3D tcg_cpu_class_init; + acc->cpu_instance_init =3D tcg_cpu_instance_init; acc->cpu_realizefn =3D tcg_cpu_realizefn; } =20 --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695208998; cv=none; d=zohomail.com; s=zohoarc; b=XnwaC8SP6WLRBfSZBcytCWN7RBGrO27e1Lyy0lUjdnqbEJSWT2EHROhg6RwqiLiDGbtoBYUZDfoU9/KtYGrT8OlqSQ0XYe0a3V106NTwbl487DvrlnLrnSz1oFgLN4xtIzH3NAJMeoZH4jyv1uiInx98JyPdta0gq3OFoDmlktg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695208998; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OqRIPHqWNZqBqf0cRIFbikY5Mcx8YHmevSxy1+cC3Ns=; b=LHCOptBxRN4uCHDa/ss60pZHgkkbMfJRf0I2ZeiozJCORrC3wxnHJ8iP95Z1zf6sLz3I7qIQZOcpvqNPBS4oenboFESCVhhcvewlUnaU5KA0kSMU4FKq5qecWqWoxpeVq/sXR3ked/H9Wv5Foq/WdTa0t0/oLTMwmx9ZZazvtpA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695208998159716.6487556865833; Wed, 20 Sep 2023 04:23:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivHM-0006t9-1o; Wed, 20 Sep 2023 07:22:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivGy-0006nT-TI for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:37 -0400 Received: from mail-ot1-x32b.google.com ([2607:f8b0:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivGi-0002Gp-T5 for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:35 -0400 Received: by mail-ot1-x32b.google.com with SMTP id 46e09a7af769-6bdcbde9676so4377880a34.3 for ; Wed, 20 Sep 2023 04:21:20 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.21.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:21:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208879; x=1695813679; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OqRIPHqWNZqBqf0cRIFbikY5Mcx8YHmevSxy1+cC3Ns=; b=NSnegTBO2y+/tAxXJmv1nUr6Eq5tj3zqUZMpf3qFXivIK49F7VipMesdAbqatF0AQp rBTPiB7vP4sYhzKNaQGMR3v0ZUB4/HbhtjwAmQCOvG2QmPsz09nObvxRpwNdE5Y/0uL0 0B/GlAJdDEUdfLIoCYUcURtpO2TMMksqoFXxd1QXXHviKivjMkIUbbvDkjmOdtz4RQN5 0S4s42PLdqON5OJkiJqAvrgX+icHMjP/CFh3u05v8MIp27eIN3d9gvPatkFbcAcLfoe7 7ZHZtsXZ4u57gFbrlSS0uEINfhedZSNyUR2rRjBjK/7+caZXRQrK7O8S5fL7i0RULJeG m4PA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208879; x=1695813679; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OqRIPHqWNZqBqf0cRIFbikY5Mcx8YHmevSxy1+cC3Ns=; b=HEx8rsDH6pOVH9eNdoVuM/FFeJHYvaw+FUgcxi40Gtr+6Lq/eF0g0tbFO4uaL5+gFO 5+SHjT679bl0R63gglIjvaH7PJyUUVYfLkMN1ucq/WiGFAGunY2mny6UowopwfVIdguL TRlfRyBAJDTpU3f+t48pbD4OK4Nq6SoEJPBD9xWmKVdUHa/+F/l0PIaUe9jW64f+cSO1 Zu1SDE3fMe9gY+PEK1OMhFCRA0KSHMRvyHbWLKhg7XYrUghA0OFu4TydimevlSulQ5VG Da/JVlrwIq1h20MoM+/VyxcysEbb1pbvDKZw1yKKp71JyPe2zHYIdfV39awaiz6jbBwe rGIw== X-Gm-Message-State: AOJu0Yw9Tqb4prNKroqXFuB7vROVf/QBtrfmSY8iJsbf7hYHTBmgvnTf Dknt1p6GcHce0bhSV0DZRBGnTT8GNmvDMs3Wz2k= X-Google-Smtp-Source: AGHT+IGzprlPuLIgkPvCLvfjs/MwgzuuL1qNTbtriAS5JAWkZuyB1UrHQ5IG8lkKWFYrrXjT27Wg+Q== X-Received: by 2002:a9d:6b98:0:b0:6b8:73df:da64 with SMTP id b24-20020a9d6b98000000b006b873dfda64mr2303995otq.7.1695208879454; Wed, 20 Sep 2023 04:21:19 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 16/19] target/riscv/cpu.c: make misa_ext_cfgs[] 'const' Date: Wed, 20 Sep 2023 08:20:17 -0300 Message-ID: <20230920112020.651006-17-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695208998905100003 Content-Type: text/plain; charset="utf-8" The array isn't marked as 'const' because we're initializing their elements in riscv_cpu_add_misa_properties(), 'name' and 'description' fields. In a closer look we can see that we're not using these 2 fields after creating the MISA properties. And we can create the properties by using riscv_get_misa_ext_name() and riscv_get_misa_ext_description() directly. Remove the 'name' and 'description' fields from RISCVCPUMisaExtConfig and make misa_ext_cfgs[] a const array. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8616c9e2f5..4875feded7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1212,8 +1212,6 @@ static void riscv_cpu_init(Object *obj) } =20 typedef struct RISCVCPUMisaExtConfig { - const char *name; - const char *description; target_ulong misa_bit; bool enabled; } RISCVCPUMisaExtConfig; @@ -1317,7 +1315,7 @@ const char *riscv_get_misa_ext_description(uint32_t b= it) #define MISA_CFG(_bit, _enabled) \ {.misa_bit =3D _bit, .enabled =3D _enabled} =20 -static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { MISA_CFG(RVA, true), MISA_CFG(RVC, true), MISA_CFG(RVD, true), @@ -1344,25 +1342,22 @@ void riscv_cpu_add_misa_properties(Object *cpu_obj) int i; =20 for (i =3D 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { - RISCVCPUMisaExtConfig *misa_cfg =3D &misa_ext_cfgs[i]; + const RISCVCPUMisaExtConfig *misa_cfg =3D &misa_ext_cfgs[i]; int bit =3D misa_cfg->misa_bit; - - misa_cfg->name =3D riscv_get_misa_ext_name(bit); - misa_cfg->description =3D riscv_get_misa_ext_description(bit); + const char *name =3D riscv_get_misa_ext_name(bit); + const char *desc =3D riscv_get_misa_ext_description(bit); =20 /* Check if KVM already created the property */ - if (object_property_find(cpu_obj, misa_cfg->name)) { + if (object_property_find(cpu_obj, name)) { continue; } =20 - object_property_add(cpu_obj, misa_cfg->name, "bool", + object_property_add(cpu_obj, name, "bool", cpu_get_misa_ext_cfg, cpu_set_misa_ext_cfg, NULL, (void *)misa_cfg); - object_property_set_description(cpu_obj, misa_cfg->name, - misa_cfg->description); - object_property_set_bool(cpu_obj, misa_cfg->name, - misa_cfg->enabled, NULL); + object_property_set_description(cpu_obj, name, desc); + object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL); } } =20 --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695209152; cv=none; d=zohomail.com; s=zohoarc; b=dQOFThyZaqJb2ZYdIFIdW0S4FA5oKs2xPYDYF1EJh35iC/atuApRyWjBSJhBF+AUi+rMuJVRdfb/fxw7prDMOJg4IDQv/9PD2+jayNr/P5dxYIrlC8H0sZ2HxemFzma8VJAE0R33aDkus65SbAQWL9W/s1kn+8p3IFIc1JdiE/0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695209152; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qwxpmKgNT9HC7Ykdf7MYYoEt86HIsFBzpyqPrCOE5ak=; b=BH0OHMCts2pMPNKtIKInQCvREk2BgG8kBg5WGTQ3d22XhJJxenEh5gUdSVUWzxxv4HPo8EiP7Ockcv2ScivXFcERKD2+2P/2IYAVu9FCnV8gr5dUcnHL/fz7OPZE/7UTZtIo7kwWLsV7PGeU1+tj/6epvFKZu18eH+DjQgBDyvo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695209152084742.1739612312982; Wed, 20 Sep 2023 04:25:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivGr-0006m3-GB; Wed, 20 Sep 2023 07:21:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivGp-0006jL-Hw for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:27 -0400 Received: from mail-ot1-x32f.google.com ([2607:f8b0:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivGm-0002HG-42 for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:27 -0400 Received: by mail-ot1-x32f.google.com with SMTP id 46e09a7af769-6bf2427b947so3865199a34.3 for ; Wed, 20 Sep 2023 04:21:23 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.21.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:21:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208883; x=1695813683; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qwxpmKgNT9HC7Ykdf7MYYoEt86HIsFBzpyqPrCOE5ak=; b=H07o3yfarDFHPmrtB9JOc5yQrlqlwIA76bXNnuQY66zZes4g+RMbM6SHA2YmzQRvib ndnmPB6XZsvCn0SVP/qrms0vP+8890V7vVYJSWuKteeUUfM+4Obc/zCOTqw1LrGDgsOQ 3MxG8F3AVWAyhmhob7QD581gLuD0FpQIjUbGH+Zw3T+9Lz79qWoMSGo87VLlzc+W9JJv Zhx1zLdflkRGg4HqE9APfuTRkT5OzPuHDhjyNQEKxC2AVi5jA0usQ594YrLcC5VDVai0 AEEiy7EbAmWPElntvM8BWqHoSu3jSVprUrqRkmoqKzQG0o/VUjeEhFF121MWMohrnfvu VFWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208883; x=1695813683; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qwxpmKgNT9HC7Ykdf7MYYoEt86HIsFBzpyqPrCOE5ak=; b=kT9Y8zwuxYqbdW1WVkTvdwOKeZLBqPpSUGbBjGEkqcKGF1PctcriXQSyZLIU/SpVgy PeGvdfmLagw+WqlwVfAa350ckT/WfpBuVceqI+CoiFsllxScq16mxgBhcix57TamdhY5 uBJslQ6o9+85LwTjkSMEK738z8mfZ2IAYWNUnrcr1D7B5QVyMoZkNURNKT5lp4/83thV WrMW7CiOLlNk2rnhf77ysF4pccD/WiJW2zb2xo8GAosLgge1rYekdQpTsrzUKEY6vxF7 TgVET2QgmS9m2f6UQ9z3SNvC7IYBFLSjWB0WCX6F5NqU5vhQQ3XhluJAUM3yV09/a3RW BEAQ== X-Gm-Message-State: AOJu0YyTFcd/kKZCTkLqR2Dv1sRUwiYPohQ8ma54MmV5T3yK4zXmeA52 05l+6LWS1mG1G1pzWlw4OdEsqCvQsmphDkPAEjs= X-Google-Smtp-Source: AGHT+IF5RlVWsCtCl7qElTKH3VsXRsz41x+O+fR2iAf2errMhvsqvMkpwHZ+tWoNXb/REObbt5RJ0Q== X-Received: by 2002:a05:6830:1d5c:b0:6b8:9932:b8ad with SMTP id p28-20020a0568301d5c00b006b89932b8admr2128099oth.1.1695208882767; Wed, 20 Sep 2023 04:21:22 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 17/19] target/riscv/tcg: move riscv_cpu_add_misa_properties() to tcg-cpu.c Date: Wed, 20 Sep 2023 08:20:18 -0300 Message-ID: <20230920112020.651006-18-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695209152538100001 Content-Type: text/plain; charset="utf-8" All code related to MISA TCG properties is also moved. At this point, all TCG properties handling is done in tcg-cpu.c, all KVM properties handling is done in kvm-cpu.c. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 90 -------------------------------------- target/riscv/cpu.h | 1 - target/riscv/tcg/tcg-cpu.c | 90 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 90 insertions(+), 91 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4875feded7..46263e55d5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1211,47 +1211,6 @@ static void riscv_cpu_init(Object *obj) #endif /* CONFIG_USER_ONLY */ } =20 -typedef struct RISCVCPUMisaExtConfig { - target_ulong misa_bit; - bool enabled; -} RISCVCPUMisaExtConfig; - -static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; - target_ulong misa_bit =3D misa_ext_cfg->misa_bit; - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - bool value; - - if (!visit_type_bool(v, name, &value, errp)) { - return; - } - - if (value) { - env->misa_ext |=3D misa_bit; - env->misa_ext_mask |=3D misa_bit; - } else { - env->misa_ext &=3D ~misa_bit; - env->misa_ext_mask &=3D ~misa_bit; - } -} - -static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; - target_ulong misa_bit =3D misa_ext_cfg->misa_bit; - RISCVCPU *cpu =3D RISCV_CPU(obj); - CPURISCVState *env =3D &cpu->env; - bool value; - - value =3D env->misa_ext & misa_bit; - - visit_type_bool(v, name, &value, errp); -} - typedef struct misa_ext_info { const char *name; const char *description; @@ -1312,55 +1271,6 @@ const char *riscv_get_misa_ext_description(uint32_t = bit) return val; } =20 -#define MISA_CFG(_bit, _enabled) \ - {.misa_bit =3D _bit, .enabled =3D _enabled} - -static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { - MISA_CFG(RVA, true), - MISA_CFG(RVC, true), - MISA_CFG(RVD, true), - MISA_CFG(RVF, true), - MISA_CFG(RVI, true), - MISA_CFG(RVE, false), - MISA_CFG(RVM, true), - MISA_CFG(RVS, true), - MISA_CFG(RVU, true), - MISA_CFG(RVH, true), - MISA_CFG(RVJ, false), - MISA_CFG(RVV, false), - MISA_CFG(RVG, false), -}; - -/* - * We do not support user choice tracking for MISA - * extensions yet because, so far, we do not silently - * change MISA bits during realize() (RVG enables MISA - * bits but the user is warned about it). - */ -void riscv_cpu_add_misa_properties(Object *cpu_obj) -{ - int i; - - for (i =3D 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { - const RISCVCPUMisaExtConfig *misa_cfg =3D &misa_ext_cfgs[i]; - int bit =3D misa_cfg->misa_bit; - const char *name =3D riscv_get_misa_ext_name(bit); - const char *desc =3D riscv_get_misa_ext_description(bit); - - /* Check if KVM already created the property */ - if (object_property_find(cpu_obj, name)) { - continue; - } - - object_property_add(cpu_obj, name, "bool", - cpu_get_misa_ext_cfg, - cpu_set_misa_ext_cfg, - NULL, (void *)misa_cfg); - object_property_set_description(cpu_obj, name, desc); - object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL); - } -} - #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \ {.name =3D _name, .offset =3D CPU_CFG_OFFSET(_prop), \ .enabled =3D _defval} diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 01cbcbe119..aba8192c74 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -726,7 +726,6 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_ex= ts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; extern Property riscv_cpu_options[]; =20 -void riscv_cpu_add_misa_properties(Object *cpu_obj); void riscv_add_satp_mode_properties(Object *obj); =20 /* CSR function table */ diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 5d71ff2cce..c326ab37a2 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -580,6 +580,96 @@ static bool tcg_cpu_realizefn(CPUState *cs, Error **er= rp) return true; } =20 +typedef struct RISCVCPUMisaExtConfig { + target_ulong misa_bit; + bool enabled; +} RISCVCPUMisaExtConfig; + +static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; + target_ulong misa_bit =3D misa_ext_cfg->misa_bit; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + if (value) { + env->misa_ext |=3D misa_bit; + env->misa_ext_mask |=3D misa_bit; + } else { + env->misa_ext &=3D ~misa_bit; + env->misa_ext_mask &=3D ~misa_bit; + } +} + +static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + const RISCVCPUMisaExtConfig *misa_ext_cfg =3D opaque; + target_ulong misa_bit =3D misa_ext_cfg->misa_bit; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + bool value; + + value =3D env->misa_ext & misa_bit; + + visit_type_bool(v, name, &value, errp); +} + +#define MISA_CFG(_bit, _enabled) \ + {.misa_bit =3D _bit, .enabled =3D _enabled} + +static const RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { + MISA_CFG(RVA, true), + MISA_CFG(RVC, true), + MISA_CFG(RVD, true), + MISA_CFG(RVF, true), + MISA_CFG(RVI, true), + MISA_CFG(RVE, false), + MISA_CFG(RVM, true), + MISA_CFG(RVS, true), + MISA_CFG(RVU, true), + MISA_CFG(RVH, true), + MISA_CFG(RVJ, false), + MISA_CFG(RVV, false), + MISA_CFG(RVG, false), +}; + +/* + * We do not support user choice tracking for MISA + * extensions yet because, so far, we do not silently + * change MISA bits during realize() (RVG enables MISA + * bits but the user is warned about it). + */ +static void riscv_cpu_add_misa_properties(Object *cpu_obj) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { + const RISCVCPUMisaExtConfig *misa_cfg =3D &misa_ext_cfgs[i]; + int bit =3D misa_cfg->misa_bit; + const char *name =3D riscv_get_misa_ext_name(bit); + const char *desc =3D riscv_get_misa_ext_description(bit); + + /* Check if KVM already created the property */ + if (object_property_find(cpu_obj, name)) { + continue; + } + + object_property_add(cpu_obj, name, "bool", + cpu_get_misa_ext_cfg, + cpu_set_misa_ext_cfg, + NULL, (void *)misa_cfg); + object_property_set_description(cpu_obj, name, desc); + object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL); + } +} + static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *nam= e, void *opaque, Error **errp) { --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695208955; cv=none; d=zohomail.com; s=zohoarc; b=j/fSqUcriUc9IRp4LGw/DVea8Fmna+RrOZeI8I9Ql7Krq0238/p2lh7NwtdJQwzZYMSo6Q0FkSDwdsbBjN6JU7jrhnEfvgZLIRku19oZUuvWH6hvwpkTw7EMVgLjU243jkycyq2G4MpjvlbiQ/TBU0arDVKiIkd8bEqdE5aKQfE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695208955; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=u8O5rBYIXDm6c3f9dmM8e697v+RoKN0fqk80mWnEKzg=; b=e7uohDjYXDn0Q/wZdVDwGHP2PaaycRcTbg4QvFut6q6Mw7I74+lZiT67S2bfhCqj+DdBF/IEh3lpfi4g8aj/HQRVERkry96k8L87Dy2d9DsEmASxjIa88h9WYzoGCF7RHsApZPJFf70DBwl1KUuWZ3mHm8zw5p0gQvC7YrSrZG0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695208955301406.49901336781363; Wed, 20 Sep 2023 04:22:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivGx-0006nC-24; Wed, 20 Sep 2023 07:21:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivGr-0006lv-Ad for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:29 -0400 Received: from mail-oa1-x32.google.com ([2001:4860:4864:20::32]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivGp-0002JC-L3 for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:29 -0400 Received: by mail-oa1-x32.google.com with SMTP id 586e51a60fabf-1d6baffcac2so2704371fac.2 for ; Wed, 20 Sep 2023 04:21:27 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.21.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:21:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208886; x=1695813686; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u8O5rBYIXDm6c3f9dmM8e697v+RoKN0fqk80mWnEKzg=; b=QyKECqKFJ/OJa8gUT5/9xpJmd00eGbqj5AhYFmJ9zMYibyk6w8vcUrMe9W4c+N5LPH l0hkBzrOml+CTopLHHf9hobrgNtcVw6EV5OafJ+7hJNO8K5jD0NEjhbC4EApkAvFADcp wZO+aC5lIxsI7B3qGeqtaJoP4xSbcplRi5Ky+wpsWA5u2iBzDCGmOUoaQA+8wfLrEIT0 JfW4tJm/QechFxgwA32BdbklDByq13WP4hheOCF+Zv+6SljG62z1lYfngsmivp/+k/wZ kFlqchXfNBU0USsbff1Jg5NGK4AhWcKicsvlyQHGeLCNJEdWCcv9lXmTUFxYIw8E20bB 3Uyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208886; x=1695813686; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u8O5rBYIXDm6c3f9dmM8e697v+RoKN0fqk80mWnEKzg=; b=URGw8NwrUe1SUHHTXR5FxnDiV7SE2gbpzEPytWQ+NC/5oALhJP+BI7EqmjmBGV/zLR U+6mLFWyAxV2cR3+ERlLG9VBX5cf9NIKgOq7S8iu7BA+Y2TbjfzsNDk7Q20G1tRbEyiL 4aNxku+IB0TknsjIMFjaYVg6wvuq0al2ojhPOXtPmBATHfG6ixQXmC+bs3USD7OZsL5Y R0JQV3fkDrEt6jO4h80BJQ2x0K367OZooyNHTNyyK8peRl0fdgx50gXwVnuq+W1nhFCA BbJVo4jox+FzcZuHs/nW+I0ss/5ubC+g57WI2mr5JGIMkOnpEfYfyYAT5lxqMOtjsFJG RQtA== X-Gm-Message-State: AOJu0YwNPJQqS+q5LpAjyApj/0ZOm3FB3DFsVlC+mXarwhVvmMw0+G4R 4nvUgq3Cwj/7S9E3TTFNFMlUydgIT7W5JuoQWYM= X-Google-Smtp-Source: AGHT+IFwmIJh/IO2N5qpccqe4CqfdOqMhvvcM3jt17u9tz5s0YezqOuyIeOMdbv9i330d/6XzULGsQ== X-Received: by 2002:a05:6870:1cc:b0:1d7:1533:6869 with SMTP id n12-20020a05687001cc00b001d715336869mr2086920oad.31.1695208886141; Wed, 20 Sep 2023 04:21:26 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 18/19] target/riscv/cpu.c: export isa_edata_arr[] Date: Wed, 20 Sep 2023 08:20:19 -0300 Message-ID: <20230920112020.651006-19-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695208956121100003 Content-Type: text/plain; charset="utf-8" This array will be read by the TCG accel class, allowing it to handle priv spec verifications on its own. The array will remain here in cpu.c because it's also used by the riscv,isa string function. To export it we'll finish it with an empty element since ARRAY_SIZE() won't work outside of cpu.c. Get rid of its ARRAY_SIZE() usage now to alleviate the changes for the next patch. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 47 +++++++++++++++++++++------------------------- target/riscv/cpu.h | 7 +++++++ 2 files changed, 28 insertions(+), 26 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 46263e55d5..e97ba3df93 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -41,15 +41,6 @@ static const char riscv_single_letter_exts[] =3D "IEMAFD= QCPVH"; const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF, RVD, RVV, RVC, RVS, RVU, RVH, RVJ, RVG, 0}; =20 -struct isa_ext_data { - const char *name; - int min_version; - int ext_enable_offset; -}; - -#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ - {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} - /* * From vector_helper.c * Note that vector data is stored in host-endian 64-bit chunks, @@ -61,6 +52,9 @@ struct isa_ext_data { #define BYTE(x) (x) #endif =20 +#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ + {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} + /* * Here are the ordering rules of extension naming defined by RISC-V * specification : @@ -81,7 +75,7 @@ struct isa_ext_data { * Single letter extensions are checked in riscv_cpu_validate_misa_priv() * instead. */ -static const struct isa_ext_data isa_edata_arr[] =3D { +const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), @@ -160,6 +154,8 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempa= ir), ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaC= ondOps), + + DEFINE_PROP_END_OF_LIST(), }; =20 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) @@ -178,14 +174,14 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t e= xt_offset, bool en) =20 int cpu_cfg_ext_get_min_version(uint32_t ext_offset) { - int i; + const RISCVIsaExtData *edata; =20 - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_edata_arr[i].ext_enable_offset !=3D ext_offset) { + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (edata->ext_enable_offset !=3D ext_offset) { continue; } =20 - return isa_edata_arr[i].min_version; + return edata->min_version; } =20 g_assert_not_reached(); @@ -932,22 +928,21 @@ static void riscv_cpu_disas_set_info(CPUState *s, dis= assemble_info *info) void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) { CPURISCVState *env =3D &cpu->env; - int i; + const RISCVIsaExtData *edata; =20 /* Force disable extensions if priv spec version does not match */ - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) && - (env->priv_ver < isa_edata_arr[i].min_version)) { - isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset, - false); + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && + (env->priv_ver < edata->min_version)) { + isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); #ifndef CONFIG_USER_ONLY warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx " because privilege spec version does not match", - isa_edata_arr[i].name, env->mhartid); + edata->name, env->mhartid); #else warn_report("disabling %s extension because " "privilege spec version does not match", - isa_edata_arr[i].name); + edata->name); #endif } } @@ -1619,13 +1614,13 @@ static void riscv_cpu_class_init(ObjectClass *c, vo= id *data) static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) { + const RISCVIsaExtData *edata; char *old =3D *isa_str; char *new =3D *isa_str; - int i; =20 - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) { - new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) { + new =3D g_strconcat(old, "_", edata->name, NULL); g_free(old); old =3D new; } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index aba8192c74..3dfcd0732f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -726,6 +726,13 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_e= xts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; extern Property riscv_cpu_options[]; =20 +typedef struct isa_ext_data { + const char *name; + int min_version; + int ext_enable_offset; +} RISCVIsaExtData; +extern const RISCVIsaExtData isa_edata_arr[]; + void riscv_add_satp_mode_properties(Object *obj); =20 /* CSR function table */ --=20 2.41.0 From nobody Sat May 18 21:26:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695209082; cv=none; d=zohomail.com; s=zohoarc; b=adqhxSpYWm21bF3ssdbQ7eS4WLxX7n/3MRf5VoZvKn3KFBkO4Et6OwiqNmIlj4FDwZvfGLH3DapBGPLz+3E4qgotgKkPm7RtkqDUtCSVFt8QpMbwpp3j1fmOGaAitDhhCFmkd+CdgmlB6VJAkrVwsizujGKAQ7L/YbiBavSwXh0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695209082; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2sZfZHqt2jnUylehekGfpy+3Is34Ky+f68MpC7nUPlE=; b=Ed/ce0eGdKe/Sh6ZykduWNOD1yYdTEaVBaZXbIzxD1zWrDGyAWQCAm3KpKvfo2CYDJHdGmWCgieJ8Ir9DqX6Vas+essGS6NXDGDKP+haC2ZzzUBWWLgypeDaK16LIUymtTez+Ct265OveVFRV09CZ61qV361hRmuE7Dteug7cQI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695209082920317.1459625469719; Wed, 20 Sep 2023 04:24:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qivH0-0006nj-Qe; Wed, 20 Sep 2023 07:21:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qivGu-0006ml-9t for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:33 -0400 Received: from mail-oa1-x36.google.com ([2001:4860:4864:20::36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qivGs-0002Je-Oi for qemu-devel@nongnu.org; Wed, 20 Sep 2023 07:21:32 -0400 Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-1d544a4a315so4274639fac.3 for ; Wed, 20 Sep 2023 04:21:30 -0700 (PDT) Received: from grind.. ([2804:7f0:bcc0:bdf2:b7ba:a476:c0e3:fb59]) by smtp.gmail.com with ESMTPSA id q4-20020a9d7c84000000b006b45be2fdc2sm5863955otn.65.2023.09.20.04.21.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 04:21:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695208889; x=1695813689; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2sZfZHqt2jnUylehekGfpy+3Is34Ky+f68MpC7nUPlE=; b=nVBYR1suCo40nUHlyvQbmrv5NPxxoUzOUtvIWJWMW+UYdeX7wm0xVsNa7gFGgDXhXJ bAxfk4wu/WwKwK3ixbov+lUb2EYA+eh49dpCk7tiSmY0SF+ypwlgqtPuge5aHQ/bDV/Y hYYcu947ZfGGCeKMd2vTCIKweRhQpPC/i3Ca3gHm97YjOC9q4hYz3TvpXfDLTPGJaVLv 933PhLBswchH0sz5A6hApUEN98Dll3HDsERTa3CSJufIyEcM9nNTMLFcMWU9R/bNklDO 1JpZP1NrQw9zJJDBnNgMWUgfpbzCuPTYRIFaMTVp1QGeMmApdKv2SeoGi1T59tPG8sIj DijA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695208889; x=1695813689; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2sZfZHqt2jnUylehekGfpy+3Is34Ky+f68MpC7nUPlE=; b=Rorg1/SdlEzuejS33RPD2p2pRxyKsVPxJwrVmpR8uPNAIp5mk+onWaAWMpxFu7YOQN 9mzcPl4qhuy456xUym6WTO/Y36MAyMld0Jmnp86gCHO+2AEE6/X0LypZ7rXSCwAGoyha 4nnl/uygQsYIDOa9Mw4VVILcwkYApVsQQKofHaxLxnQll8G4/WlLJYhmrrT+ogKiz94e lM3NiqkBmSio5ox4d8//FzmbEKDypj4u7xSO06bhJEqGSizKzV0Tcc/ON8hgEmlTJSkI X3DKMMqFxse/lGzJ14kC2gemjtSYZN8trtuUIltzf+CzNMiGjyhf0uggvT3RJI/E4rhK M4aw== X-Gm-Message-State: AOJu0Yz8v0T8oQlRJHZ/8zglEyb+dgiMlMLyCUTc4svmoX9qV1149wZJ mLRppq3T1ZQIFLn3fjr7o9T5BgPAl/jL7Aw6WYQ= X-Google-Smtp-Source: AGHT+IFSU3C1ewkYbQO7Jb9I++mfmHjae7FRnEHtkjjXwJw0ZDFVrCXnzupXoraRmqqGmP4BYDqbww== X-Received: by 2002:a05:6870:4189:b0:1db:71b9:419c with SMTP id y9-20020a056870418900b001db71b9419cmr2423712oac.58.1695208889332; Wed, 20 Sep 2023 04:21:29 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, philmd@linaro.org, ajones@ventanamicro.com, Daniel Henrique Barboza Subject: [PATCH v3 19/19] target/riscv/cpu: move priv spec functions to tcg-cpu.c Date: Wed, 20 Sep 2023 08:20:20 -0300 Message-ID: <20230920112020.651006-20-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920112020.651006-1-dbarboza@ventanamicro.com> References: <20230920112020.651006-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1695209084788100007 Content-Type: text/plain; charset="utf-8" Priv spec validation is TCG specific. Move it to the TCG accel class. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.c | 38 -------------------------------------- target/riscv/cpu.h | 2 -- target/riscv/tcg/tcg-cpu.c | 38 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 38 insertions(+), 40 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e97ba3df93..eeeb08a35a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -172,21 +172,6 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ex= t_offset, bool en) *ext_enabled =3D en; } =20 -int cpu_cfg_ext_get_min_version(uint32_t ext_offset) -{ - const RISCVIsaExtData *edata; - - for (edata =3D isa_edata_arr; edata && edata->name; edata++) { - if (edata->ext_enable_offset !=3D ext_offset) { - continue; - } - - return edata->min_version; - } - - g_assert_not_reached(); -} - const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -925,29 +910,6 @@ static void riscv_cpu_disas_set_info(CPUState *s, disa= ssemble_info *info) } } =20 -void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) -{ - CPURISCVState *env =3D &cpu->env; - const RISCVIsaExtData *edata; - - /* Force disable extensions if priv spec version does not match */ - for (edata =3D isa_edata_arr; edata && edata->name; edata++) { - if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && - (env->priv_ver < edata->min_version)) { - isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); -#ifndef CONFIG_USER_ONLY - warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx - " because privilege spec version does not match", - edata->name, env->mhartid); -#else - warn_report("disabling %s extension because " - "privilege spec version does not match", - edata->name); -#endif - } - } -} - #ifndef CONFIG_USER_ONLY static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3dfcd0732f..219fe2e9b5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -711,9 +711,7 @@ enum riscv_pmu_event_idx { /* used by tcg/tcg-cpu.c*/ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); -int cpu_cfg_ext_get_min_version(uint32_t ext_offset); void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); -void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu); =20 typedef struct RISCVCPUMultiExtConfig { const char *name; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c326ab37a2..8c052d6fcd 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -99,6 +99,21 @@ static const struct TCGCPUOps riscv_tcg_ops =3D { #endif /* !CONFIG_USER_ONLY */ }; =20 +static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) +{ + const RISCVIsaExtData *edata; + + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (edata->ext_enable_offset !=3D ext_offset) { + continue; + } + + return edata->min_version; + } + + g_assert_not_reached(); +} + static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) { @@ -226,6 +241,29 @@ static void riscv_cpu_validate_v(CPURISCVState *env, R= ISCVCPUConfig *cfg, } } =20 +static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) +{ + CPURISCVState *env =3D &cpu->env; + const RISCVIsaExtData *edata; + + /* Force disable extensions if priv spec version does not match */ + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && + (env->priv_ver < edata->min_version)) { + isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); +#ifndef CONFIG_USER_ONLY + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx + " because privilege spec version does not match", + edata->name, env->mhartid); +#else + warn_report("disabling %s extension because " + "privilege spec version does not match", + edata->name); +#endif + } + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly. --=20 2.41.0