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charset="utf-8" From: Hao Wu The PCI Mailbox Module is a high-bandwidth communcation module between a Nuvoton BMC and CPU. It features 16KB RAM that are both accessible by the BMC and core CPU. and supports interrupt for both sides. This patch implements the BMC side of the PCI mailbox module. Communication with the core CPU is emulated via a chardev and will be in a follow-up patch. Signed-off-by: Hao Wu --- hw/misc/meson.build | 1 + hw/misc/npcm7xx_pci_mbox.c | 176 +++++++++++++++++++++++++++++ hw/misc/trace-events | 5 + include/hw/misc/npcm7xx_pci_mbox.h | 63 +++++++++++ 4 files changed, 245 insertions(+) create mode 100644 hw/misc/npcm7xx_pci_mbox.c create mode 100644 include/hw/misc/npcm7xx_pci_mbox.h diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 892f8b91c5..1f4ec94584 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -70,6 +70,7 @@ system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files( 'npcm7xx_clk.c', 'npcm7xx_gcr.c', 'npcm7xx_mft.c', + 'npcm7xx_pci_mbox.c', 'npcm7xx_pwm.c', 'npcm7xx_rng.c', )) diff --git a/hw/misc/npcm7xx_pci_mbox.c b/hw/misc/npcm7xx_pci_mbox.c new file mode 100644 index 0000000000..d82a87fc41 --- /dev/null +++ b/hw/misc/npcm7xx_pci_mbox.c @@ -0,0 +1,176 @@ +/* + * Nuvoton NPCM7xx PCI Mailbox Module + * + * Copyright 2021 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "hw/irq.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-properties-system.h" +#include "hw/misc/npcm7xx_pci_mbox.h" +#include "hw/registerfields.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "qemu/bitops.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/timer.h" +#include "qemu/units.h" +#include "trace.h" + +REG32(NPCM7XX_PCI_MBOX_BMBXSTAT, 0x00); +REG32(NPCM7XX_PCI_MBOX_BMBXCTL, 0x04); +REG32(NPCM7XX_PCI_MBOX_BMBXCMD, 0x08); + + +#define NPCM7XX_PCI_MBOX_NR_CI 8 +#define NPCM7XX_PCI_MBOX_CI_MASK MAKE_64BIT_MASK(0, NPCM7XX_PCI_MBOX_NR_CI) + +static void npcm7xx_pci_mbox_update_irq(NPCM7xxPCIMBoxState *s) +{ + /* We should send an interrupt when one of the CIE and CIF are both 1.= */ + if (s->regs[R_NPCM7XX_PCI_MBOX_BMBXSTAT] & + s->regs[R_NPCM7XX_PCI_MBOX_BMBXCTL] & + NPCM7XX_PCI_MBOX_CI_MASK) { + qemu_irq_raise(s->irq); + trace_npcm7xx_pci_mbox_irq(1); + } else { + qemu_irq_lower(s->irq); + trace_npcm7xx_pci_mbox_irq(0); + } +} + +static uint64_t npcm7xx_pci_mbox_read(void *opaque, hwaddr offset, unsigne= d size) +{ + NPCM7xxPCIMBoxState *s =3D NPCM7XX_PCI_MBOX(opaque); + uint16_t value =3D 0; + + if (offset / sizeof(uint32_t) >=3D NPCM7XX_PCI_MBOX_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: offset 0x%04" HWADDR_PRIx " out of range\n", + __func__, offset); + return 0; + } + + value =3D s->regs[offset / sizeof(uint32_t)]; + trace_npcm7xx_pci_mbox_read(DEVICE(s)->canonical_path, offset, value, = size); + return value; +} + +static void npcm7xx_pci_mbox_write(void *opaque, hwaddr offset, + uint64_t v, unsigned size) +{ + NPCM7xxPCIMBoxState *s =3D NPCM7XX_PCI_MBOX(opaque); + + trace_npcm7xx_pci_mbox_write(DEVICE(s)->canonical_path, offset, v, siz= e); + switch (offset) { + case A_NPCM7XX_PCI_MBOX_BMBXSTAT: + /* Clear bits that are 1. */ + s->regs[R_NPCM7XX_PCI_MBOX_BMBXSTAT] &=3D ~v; + break; + + case A_NPCM7XX_PCI_MBOX_BMBXCTL: + s->regs[R_NPCM7XX_PCI_MBOX_BMBXCTL] =3D v; + break; + + case A_NPCM7XX_PCI_MBOX_BMBXCMD: + /* Set the bits that are 1. */ + s->regs[R_NPCM7XX_PCI_MBOX_BMBXCMD] |=3D v; + /* TODO: Set interrupt to host. */ + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: offset 0x%04" HWADDR_PRIx " out of range\n", + __func__, offset); + } + npcm7xx_pci_mbox_update_irq(s); +} + +static const struct MemoryRegionOps npcm7xx_pci_mbox_ops =3D { + .read =3D npcm7xx_pci_mbox_read, + .write =3D npcm7xx_pci_mbox_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void npcm7xx_pci_mbox_enter_reset(Object *obj, ResetType type) +{ + NPCM7xxPCIMBoxState *s =3D NPCM7XX_PCI_MBOX(obj); + + memset(s->regs, 0, 4 * NPCM7XX_PCI_MBOX_NR_REGS); +} + +static void npcm7xx_pci_mbox_hold_reset(Object *obj) +{ + NPCM7xxPCIMBoxState *s =3D NPCM7XX_PCI_MBOX(obj); + + qemu_irq_lower(s->irq); +} + +static void npcm7xx_pci_mbox_init(Object *obj) +{ + NPCM7xxPCIMBoxState *s =3D NPCM7XX_PCI_MBOX(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_ram_device_ptr(&s->ram, obj, "pci-mbox-ram", + NPCM7XX_PCI_MBOX_RAM_SIZE, s->conten= t); + memory_region_init_io(&s->iomem, obj, &npcm7xx_pci_mbox_ops, s, + "pci-mbox-iomem", 4 * KiB); + sysbus_init_mmio(sbd, &s->ram); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); +} + +static const VMStateDescription vmstate_npcm7xx_pci_mbox =3D { + .name =3D "npcm7xx-pci-mbox-module", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, NPCM7xxPCIMBoxState, + NPCM7XX_PCI_MBOX_NR_REGS), + VMSTATE_END_OF_LIST(), + }, +}; + +static void npcm7xx_pci_mbox_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "NPCM7xx PCI Mailbox Controller"; + dc->vmsd =3D &vmstate_npcm7xx_pci_mbox; + rc->phases.enter =3D npcm7xx_pci_mbox_enter_reset; + rc->phases.hold =3D npcm7xx_pci_mbox_hold_reset; +} + +static const TypeInfo npcm7xx_pci_mbox_info =3D { + .name =3D TYPE_NPCM7XX_PCI_MBOX, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NPCM7xxPCIMBoxState), + .class_init =3D npcm7xx_pci_mbox_class_init, + .instance_init =3D npcm7xx_pci_mbox_init, +}; + +static void npcm7xx_pci_mbox_register_type(void) +{ + type_register_static(&npcm7xx_pci_mbox_info); +} +type_init(npcm7xx_pci_mbox_register_type); diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 4d1a0e17af..32743e00ce 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -148,6 +148,11 @@ npcm7xx_pwm_write(const char *id, uint64_t offset, uin= t32_t value) "%s offset: 0 npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value,= uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u" npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value,= uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u" =20 +# npcm7xx_pci_mbox.c +npcm7xx_pci_mbox_read(const char *id, uint64_t offset, uint64_t value, uns= igned size) "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" +npcm7xx_pci_mbox_write(const char *id, uint64_t offset, uint64_t value, un= signed size) "%s offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u" +npcm7xx_pci_mbox_irq(int irq_level) "irq level: %d" + # stm32f4xx_syscfg.c stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interrupt: GPIO: = %d, Line: %d; Level: %d" stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d" diff --git a/include/hw/misc/npcm7xx_pci_mbox.h b/include/hw/misc/npcm7xx_p= ci_mbox.h new file mode 100644 index 0000000000..0f8fda0db1 --- /dev/null +++ b/include/hw/misc/npcm7xx_pci_mbox.h @@ -0,0 +1,63 @@ +/* + * Nuvoton NPCM7xx PCI Mailbox Module + * + * Copyright 2021 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#ifndef NPCM7XX_PCI_MBOX_H +#define NPCM7XX_PCI_MBOX_H + +#include "chardev/char-fe.h" +#include "exec/memory.h" +#include "hw/clock.h" +#include "hw/irq.h" +#include "hw/pci/pci.h" +#include "hw/sysbus.h" +#include "qom/object.h" + +#define NPCM7XX_PCI_MBOX_RAM_SIZE 0x4000 + +#define NPCM7XX_PCI_VENDOR_ID 0x1050 +#define NPCM7XX_PCI_DEVICE_ID 0x0750 +#define NPCM7XX_PCI_REVISION 0 +#define NPCM7XX_PCI_CLASS_CODE 0xff + +/* + * Maximum amount of control registers in PCI Mailbox module. Do not incre= ase + * this value without bumping vm version. + */ +#define NPCM7XX_PCI_MBOX_NR_REGS 3 + +/** + * struct NPCM7xxPciMboxState - PCI Mailbox Device + * @parent: System bus device. + * @ram: the mailbox RAM memory space + * @iomem: Memory region through which registers are accessed. + * @content: The content of the PCI mailbox, initialized to 0. + * @regs: The MMIO registers. + */ +typedef struct NPCM7xxPCIMBoxState { + SysBusDevice parent; + + MemoryRegion ram; + MemoryRegion iomem; + + qemu_irq irq; + uint8_t content[NPCM7XX_PCI_MBOX_RAM_SIZE]; + uint32_t regs[NPCM7XX_PCI_MBOX_NR_REGS]; +} NPCM7xxPCIMBoxState; + +#define TYPE_NPCM7XX_PCI_MBOX "npcm7xx-pci-mbox" +#define NPCM7XX_PCI_MBOX(obj) \ + OBJECT_CHECK(NPCM7xxPCIMBoxState, (obj), TYPE_NPCM7XX_PCI_MBOX) + +#endif /* NPCM7XX_PCI_MBOX_H */ --=20 2.42.0.459.ge4e396fd5e-goog From nobody Sat May 18 22:31:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: Hao Wu This patch wires the PCI mailbox module to Nuvoton SoC. hw/misc: Add chardev to PCI mailbox This patches adds a chardev to PCI mailbox that can be used to receive external read and write request from the host. Signed-off-by: Hao Wu --- hw/arm/npcm7xx.c | 16 +++- hw/misc/npcm7xx_pci_mbox.c | 147 +++++++++++++++++++++++++++++ include/hw/arm/npcm7xx.h | 1 + include/hw/misc/npcm7xx_pci_mbox.h | 18 ++++ 4 files changed, 181 insertions(+), 1 deletion(-) diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 15ff21d047..c69e936669 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -53,6 +53,9 @@ /* ADC Module */ #define NPCM7XX_ADC_BA (0xf000c000) =20 +/* PCI Mailbox Module */ +#define NPCM7XX_PCI_MBOX_BA (0xf0848000) + /* Internal AHB SRAM */ #define NPCM7XX_RAM3_BA (0xc0008000) #define NPCM7XX_RAM3_SZ (4 * KiB) @@ -83,6 +86,10 @@ enum NPCM7xxInterrupt { NPCM7XX_UART1_IRQ, NPCM7XX_UART2_IRQ, NPCM7XX_UART3_IRQ, + NPCM7XX_PECI_IRQ =3D 6, + NPCM7XX_PCI_MBOX_IRQ =3D 8, + NPCM7XX_KCS_HIB_IRQ =3D 9, + NPCM7XX_GMAC1_IRQ =3D 14, NPCM7XX_EMC1RX_IRQ =3D 15, NPCM7XX_EMC1TX_IRQ, NPCM7XX_MMC_IRQ =3D 26, @@ -706,6 +713,14 @@ static void npcm7xx_realize(DeviceState *dev, Error **= errp) } } =20 + /* PCI Mailbox. Cannot fail */ + sysbus_realize(SYS_BUS_DEVICE(&s->pci_mbox), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->pci_mbox), 0, NPCM7XX_PCI_MBOX_BA); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->pci_mbox), 1, + NPCM7XX_PCI_MBOX_BA + NPCM7XX_PCI_MBOX_RAM_SIZE); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pci_mbox), 0, + npcm7xx_irq(s, NPCM7XX_PCI_MBOX_IRQ)); + /* RAM2 (SRAM) */ memory_region_init_ram(&s->sram, OBJECT(dev), "ram2", NPCM7XX_RAM2_SZ, &error_abort); @@ -765,7 +780,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **e= rrp) create_unimplemented_device("npcm7xx.usbd[8]", 0xf0838000, 4 * = KiB); create_unimplemented_device("npcm7xx.usbd[9]", 0xf0839000, 4 * = KiB); create_unimplemented_device("npcm7xx.sd", 0xf0840000, 8 * = KiB); - create_unimplemented_device("npcm7xx.pcimbx", 0xf0848000, 512 * = KiB); create_unimplemented_device("npcm7xx.aes", 0xf0858000, 4 * = KiB); create_unimplemented_device("npcm7xx.des", 0xf0859000, 4 * = KiB); create_unimplemented_device("npcm7xx.sha", 0xf085a000, 4 * = KiB); diff --git a/hw/misc/npcm7xx_pci_mbox.c b/hw/misc/npcm7xx_pci_mbox.c index d82a87fc41..8f971a1b0d 100644 --- a/hw/misc/npcm7xx_pci_mbox.c +++ b/hw/misc/npcm7xx_pci_mbox.c @@ -15,6 +15,7 @@ */ =20 #include "qemu/osdep.h" +#include "chardev/char-fe.h" #include "hw/irq.h" #include "hw/qdev-clock.h" #include "hw/qdev-properties-system.h" @@ -35,6 +36,18 @@ REG32(NPCM7XX_PCI_MBOX_BMBXSTAT, 0x00); REG32(NPCM7XX_PCI_MBOX_BMBXCTL, 0x04); REG32(NPCM7XX_PCI_MBOX_BMBXCMD, 0x08); =20 +enum NPCM7xxPCIMBoxOperation { + NPCM7XX_PCI_MBOX_OP_READ =3D 1, + NPCM7XX_PCI_MBOX_OP_WRITE, +}; + +#define NPCM7XX_PCI_MBOX_OFFSET_BYTES 8 + +/* Response code */ +#define NPCM7XX_PCI_MBOX_OK 0 +#define NPCM7XX_PCI_MBOX_INVALID_OP 0xa0 +#define NPCM7XX_PCI_MBOX_INVALID_SIZE 0xa1 +#define NPCM7XX_PCI_MBOX_UNSPECIFIED_ERROR 0xff =20 #define NPCM7XX_PCI_MBOX_NR_CI 8 #define NPCM7XX_PCI_MBOX_CI_MASK MAKE_64BIT_MASK(0, NPCM7XX_PCI_MBOX_NR_CI) @@ -53,6 +66,92 @@ static void npcm7xx_pci_mbox_update_irq(NPCM7xxPCIMBoxSt= ate *s) } } =20 +static void npcm7xx_pci_mbox_send_response(NPCM7xxPCIMBoxState *s, uint8_t= code) +{ + qemu_chr_fe_write(&s->chr, &code, 1); + if (code =3D=3D NPCM7XX_PCI_MBOX_OK && s->op =3D=3D NPCM7XX_PCI_MBOX_O= P_READ) { + qemu_chr_fe_write(&s->chr, (uint8_t *)(&s->data), s->size); + } +} + +static void npcm7xx_pci_mbox_handle_read(NPCM7xxPCIMBoxState *s) +{ + MemTxResult r =3D memory_region_dispatch_read( + &s->ram, s->offset, &s->data, MO_LE | size_memop(s->size), + MEMTXATTRS_UNSPECIFIED); + + npcm7xx_pci_mbox_send_response(s, (uint8_t)r); +} + +static void npcm7xx_pci_mbox_handle_write(NPCM7xxPCIMBoxState *s) +{ + MemTxResult r =3D memory_region_dispatch_write( + &s->ram, s->offset, s->data, MO_LE | size_memop(s->size), + MEMTXATTRS_UNSPECIFIED); + + npcm7xx_pci_mbox_send_response(s, (uint8_t)r); +} + +static void npcm7xx_pci_mbox_receive_char(NPCM7xxPCIMBoxState *s, uint8_t = byte) +{ + switch (s->state) { + case NPCM7XX_PCI_MBOX_STATE_IDLE: + switch (byte) { + case NPCM7XX_PCI_MBOX_OP_READ: + case NPCM7XX_PCI_MBOX_OP_WRITE: + s->op =3D byte; + s->state =3D NPCM7XX_PCI_MBOX_STATE_OFFSET; + s->offset =3D 0; + s->receive_count =3D 0; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "received invalid op type: 0x%" PRIx8, byte); + npcm7xx_pci_mbox_send_response(s, NPCM7XX_PCI_MBOX_INVALID_OP); + break; + } + break; + + case NPCM7XX_PCI_MBOX_STATE_OFFSET: + s->offset +=3D (uint64_t)byte << (s->receive_count * BITS_PER_BYTE= ); + if (++s->receive_count >=3D NPCM7XX_PCI_MBOX_OFFSET_BYTES) { + s->state =3D NPCM7XX_PCI_MBOX_STATE_SIZE; + } + break; + + case NPCM7XX_PCI_MBOX_STATE_SIZE: + s->size =3D byte; + if (s->size < 1 || s->size > sizeof(uint64_t)) { + qemu_log_mask(LOG_GUEST_ERROR, "received invalid size: %u", by= te); + npcm7xx_pci_mbox_send_response(s, NPCM7XX_PCI_MBOX_INVALID_SIZ= E); + s->state =3D NPCM7XX_PCI_MBOX_STATE_IDLE; + break; + } + if (s->op =3D=3D NPCM7XX_PCI_MBOX_OP_READ) { + npcm7xx_pci_mbox_handle_read(s); + s->state =3D NPCM7XX_PCI_MBOX_STATE_IDLE; + } else { + s->receive_count =3D 0; + s->data =3D 0; + s->state =3D NPCM7XX_PCI_MBOX_STATE_DATA; + } + break; + + case NPCM7XX_PCI_MBOX_STATE_DATA: + g_assert(s->op =3D=3D NPCM7XX_PCI_MBOX_OP_WRITE); + s->data +=3D (uint64_t)byte << (s->receive_count * BITS_PER_BYTE); + if (++s->receive_count >=3D s->size) { + npcm7xx_pci_mbox_handle_write(s); + s->state =3D NPCM7XX_PCI_MBOX_STATE_IDLE; + } + break; + + default: + g_assert_not_reached(); + } +} + static uint64_t npcm7xx_pci_mbox_read(void *opaque, hwaddr offset, unsigne= d size) { NPCM7xxPCIMBoxState *s =3D NPCM7XX_PCI_MBOX(opaque); @@ -116,6 +215,8 @@ static void npcm7xx_pci_mbox_enter_reset(Object *obj, R= esetType type) NPCM7xxPCIMBoxState *s =3D NPCM7XX_PCI_MBOX(obj); =20 memset(s->regs, 0, 4 * NPCM7XX_PCI_MBOX_NR_REGS); + s->state =3D NPCM7XX_PCI_MBOX_STATE_IDLE; + s->receive_count =3D 0; } =20 static void npcm7xx_pci_mbox_hold_reset(Object *obj) @@ -125,6 +226,37 @@ static void npcm7xx_pci_mbox_hold_reset(Object *obj) qemu_irq_lower(s->irq); } =20 +static int can_receive(void *opaque) +{ + return 1; +} + +static void receive(void *opaque, const uint8_t *buf, int size) +{ + NPCM7xxPCIMBoxState *s =3D NPCM7XX_PCI_MBOX(opaque); + int i; + + for (i =3D 0; i < size; ++i) { + npcm7xx_pci_mbox_receive_char(s, buf[i]); + } +} + +static void chr_event(void *opaque, QEMUChrEvent event) +{ + switch (event) { + case CHR_EVENT_OPENED: + case CHR_EVENT_CLOSED: + case CHR_EVENT_BREAK: + case CHR_EVENT_MUX_IN: + case CHR_EVENT_MUX_OUT: + /* Ignore */ + break; + + default: + g_assert_not_reached(); + } +} + static void npcm7xx_pci_mbox_init(Object *obj) { NPCM7xxPCIMBoxState *s =3D NPCM7XX_PCI_MBOX(obj); @@ -139,6 +271,14 @@ static void npcm7xx_pci_mbox_init(Object *obj) sysbus_init_irq(sbd, &s->irq); } =20 +static void npcm7xx_pci_mbox_realize(DeviceState *dev, Error **errp) +{ + NPCM7xxPCIMBoxState *s =3D NPCM7XX_PCI_MBOX(dev); + + qemu_chr_fe_set_handlers(&s->chr, can_receive, receive, + chr_event, NULL, OBJECT(dev), NULL, true); +} + static const VMStateDescription vmstate_npcm7xx_pci_mbox =3D { .name =3D "npcm7xx-pci-mbox-module", .version_id =3D 0, @@ -150,6 +290,11 @@ static const VMStateDescription vmstate_npcm7xx_pci_mb= ox =3D { }, }; =20 +static Property npcm7xx_pci_mbox_properties[] =3D { + DEFINE_PROP_CHR("chardev", NPCM7xxPCIMBoxState, chr), + DEFINE_PROP_END_OF_LIST(), +}; + static void npcm7xx_pci_mbox_class_init(ObjectClass *klass, void *data) { ResettableClass *rc =3D RESETTABLE_CLASS(klass); @@ -157,8 +302,10 @@ static void npcm7xx_pci_mbox_class_init(ObjectClass *k= lass, void *data) =20 dc->desc =3D "NPCM7xx PCI Mailbox Controller"; dc->vmsd =3D &vmstate_npcm7xx_pci_mbox; + dc->realize =3D npcm7xx_pci_mbox_realize; rc->phases.enter =3D npcm7xx_pci_mbox_enter_reset; rc->phases.hold =3D npcm7xx_pci_mbox_hold_reset; + device_class_set_props(dc, npcm7xx_pci_mbox_properties); } =20 static const TypeInfo npcm7xx_pci_mbox_info =3D { diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index 72c7722096..273090ac60 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -26,6 +26,7 @@ #include "hw/misc/npcm7xx_clk.h" #include "hw/misc/npcm7xx_gcr.h" #include "hw/misc/npcm7xx_mft.h" +#include "hw/misc/npcm7xx_pci_mbox.h" #include "hw/misc/npcm7xx_pwm.h" #include "hw/misc/npcm7xx_rng.h" #include "hw/net/npcm7xx_emc.h" diff --git a/include/hw/misc/npcm7xx_pci_mbox.h b/include/hw/misc/npcm7xx_p= ci_mbox.h index 0f8fda0db1..e595fbcc70 100644 --- a/include/hw/misc/npcm7xx_pci_mbox.h +++ b/include/hw/misc/npcm7xx_pci_mbox.h @@ -31,6 +31,13 @@ #define NPCM7XX_PCI_REVISION 0 #define NPCM7XX_PCI_CLASS_CODE 0xff =20 +typedef enum NPCM7xxPCIMBoxHostState { + NPCM7XX_PCI_MBOX_STATE_IDLE, + NPCM7XX_PCI_MBOX_STATE_OFFSET, + NPCM7XX_PCI_MBOX_STATE_SIZE, + NPCM7XX_PCI_MBOX_STATE_DATA, +} NPCM7xxPCIMBoxHostState ; + /* * Maximum amount of control registers in PCI Mailbox module. Do not incre= ase * this value without bumping vm version. @@ -44,6 +51,8 @@ * @iomem: Memory region through which registers are accessed. * @content: The content of the PCI mailbox, initialized to 0. * @regs: The MMIO registers. + * @chr: The chardev backend used to communicate with core CPU. + * @offset: The offset to start transfer. */ typedef struct NPCM7xxPCIMBoxState { SysBusDevice parent; @@ -54,6 +63,15 @@ typedef struct NPCM7xxPCIMBoxState { qemu_irq irq; uint8_t content[NPCM7XX_PCI_MBOX_RAM_SIZE]; uint32_t regs[NPCM7XX_PCI_MBOX_NR_REGS]; + CharBackend chr; + + /* aux data for receiving host commands. */ + NPCM7xxPCIMBoxHostState state; + uint8_t op; + hwaddr offset; + uint8_t size; + uint64_t data; + int receive_count; } NPCM7xxPCIMBoxState; =20 #define TYPE_NPCM7XX_PCI_MBOX "npcm7xx-pci-mbox" --=20 2.42.0.459.ge4e396fd5e-goog From nobody Sat May 18 22:31:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: Hao Wu This patches adds a qtest for NPCM7XX PCI Mailbox module. It sends read and write requests to the module, and verifies that the module contains the correct data after the requests. Signed-off-by: Hao Wu --- tests/qtest/meson.build | 1 + tests/qtest/npcm7xx_pci_mbox-test.c | 238 ++++++++++++++++++++++++++++ 2 files changed, 239 insertions(+) create mode 100644 tests/qtest/npcm7xx_pci_mbox-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index b071d400b3..5adf12b45f 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -183,6 +183,7 @@ qtests_sparc64 =3D \ qtests_npcm7xx =3D \ ['npcm7xx_adc-test', 'npcm7xx_gpio-test', + 'npcm7xx_pci_mbox-test', 'npcm7xx_pwm-test', 'npcm7xx_rng-test', 'npcm7xx_sdhci-test', diff --git a/tests/qtest/npcm7xx_pci_mbox-test.c b/tests/qtest/npcm7xx_pci_= mbox-test.c new file mode 100644 index 0000000000..24eec18e3c --- /dev/null +++ b/tests/qtest/npcm7xx_pci_mbox-test.c @@ -0,0 +1,238 @@ +/* + * QTests for Nuvoton NPCM7xx PCI Mailbox Modules. + * + * Copyright 2021 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "qapi/qmp/qdict.h" +#include "qapi/qmp/qnum.h" +#include "libqtest-single.h" + +#define PCI_MBOX_BA 0xf0848000 +#define PCI_MBOX_IRQ 8 + +/* register offset */ +#define PCI_MBOX_STAT 0x00 +#define PCI_MBOX_CTL 0x04 +#define PCI_MBOX_CMD 0x08 + +#define CODE_OK 0x00 +#define CODE_INVALID_OP 0xa0 +#define CODE_INVALID_SIZE 0xa1 +#define CODE_ERROR 0xff + +#define OP_READ 0x01 +#define OP_WRITE 0x02 +#define OP_INVALID 0x41 + + +static int sock; +static int fd; + +/* + * Create a local TCP socket with any port, then save off the port we got. + */ +static in_port_t open_socket(void) +{ + struct sockaddr_in myaddr; + socklen_t addrlen; + + myaddr.sin_family =3D AF_INET; + myaddr.sin_addr.s_addr =3D htonl(INADDR_LOOPBACK); + myaddr.sin_port =3D 0; + sock =3D socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); + g_assert(sock !=3D -1); + g_assert(bind(sock, (struct sockaddr *) &myaddr, sizeof(myaddr)) !=3D = -1); + addrlen =3D sizeof(myaddr); + g_assert(getsockname(sock, (struct sockaddr *) &myaddr , &addrlen) != =3D -1); + g_assert(listen(sock, 1) !=3D -1); + return ntohs(myaddr.sin_port); +} + +static void setup_fd(void) +{ + fd_set readfds; + + FD_ZERO(&readfds); + FD_SET(sock, &readfds); + g_assert(select(sock + 1, &readfds, NULL, NULL, NULL) =3D=3D 1); + + fd =3D accept(sock, NULL, 0); + g_assert(fd >=3D 0); +} + +static uint8_t read_response(uint8_t *buf, size_t len) +{ + uint8_t code; + ssize_t ret =3D read(fd, &code, 1); + + if (ret =3D=3D -1) { + return CODE_ERROR; + } + if (code !=3D CODE_OK) { + return code; + } + g_test_message("response code: %x", code); + if (len > 0) { + ret =3D read(fd, buf, len); + if (ret < len) { + return CODE_ERROR; + } + } + return CODE_OK; +} + +static void receive_data(uint64_t offset, uint8_t *buf, size_t len) +{ + uint8_t op =3D OP_READ; + uint8_t code; + ssize_t rv; + + while (len > 0) { + uint8_t size; + + if (len >=3D 8) { + size =3D 8; + } else if (len >=3D 4) { + size =3D 4; + } else if (len >=3D 2) { + size =3D 2; + } else { + size =3D 1; + } + + g_test_message("receiving %u bytes", size); + /* Write op */ + rv =3D write(fd, &op, 1); + g_assert_cmpint(rv, =3D=3D, 1); + /* Write offset */ + rv =3D write(fd, (uint8_t *)&offset, sizeof(uint64_t)); + g_assert_cmpint(rv, =3D=3D, sizeof(uint64_t)); + /* Write size */ + g_assert_cmpint(write(fd, &size, 1), =3D=3D, 1); + + /* Read data and Expect response */ + code =3D read_response(buf, size); + g_assert_cmphex(code, =3D=3D, CODE_OK); + + buf +=3D size; + offset +=3D size; + len -=3D size; + } +} + +static void send_data(uint64_t offset, const uint8_t *buf, size_t len) +{ + uint8_t op =3D OP_WRITE; + uint8_t code; + ssize_t rv; + + while (len > 0) { + uint8_t size; + + if (len >=3D 8) { + size =3D 8; + } else if (len >=3D 4) { + size =3D 4; + } else if (len >=3D 2) { + size =3D 2; + } else { + size =3D 1; + } + + g_test_message("sending %u bytes", size); + /* Write op */ + rv =3D write(fd, &op, 1); + g_assert_cmpint(rv, =3D=3D, 1); + /* Write offset */ + rv =3D write(fd, (uint8_t *)&offset, sizeof(uint64_t)); + g_assert_cmpint(rv, =3D=3D, sizeof(uint64_t)); + /* Write size */ + g_assert_cmpint(write(fd, &size, 1), =3D=3D, 1); + /* Write data */ + g_assert_cmpint(write(fd, buf, size), =3D=3D, size); + + /* Expect response */ + code =3D read_response(NULL, 0); + g_assert_cmphex(code, =3D=3D, CODE_OK); + + buf +=3D size; + offset +=3D size; + len -=3D size; + } +} + +static void test_invalid_op(void) +{ + uint8_t op =3D OP_INVALID; + uint8_t code; + uint8_t buf[1]; + + g_assert_cmpint(write(fd, &op, 1), =3D=3D, 1); + code =3D read_response(buf, 1); + g_assert_cmphex(code, =3D=3D, CODE_INVALID_OP); +} + +/* Send data via chardev and read them in guest. */ +static void test_guest_read(void) +{ + const char *data =3D "Hello World!"; + uint64_t offset =3D 0xa0; + char buf[100]; + size_t len =3D strlen(data); + + send_data(offset, (uint8_t *)data, len); + memread(PCI_MBOX_BA + offset, buf, len); + g_assert_cmpint(strncmp(data, buf, len), =3D=3D, 0); +} + +/* Write data in guest and read out via chardev. */ +static void test_guest_write(void) +{ + const char *data =3D "Hello World!"; + uint64_t offset =3D 0xa0; + char buf[100]; + size_t len =3D strlen(data); + + memwrite(PCI_MBOX_BA + offset, data, len); + receive_data(offset, (uint8_t *)buf, len); + g_assert_cmpint(strncmp(data, buf, len), =3D=3D, 0); +} + +int main(int argc, char **argv) +{ + int ret; + int port; + + g_test_init(&argc, &argv, NULL); + port =3D open_socket(); + g_test_message("port=3D%d", port); + global_qtest =3D qtest_initf("-machine npcm750-evb " + "-chardev socket,id=3Dnpcm7xx-pcimbox-chr,host=3Dlocalhost," + "port=3D%d,reconnect=3D10 " + "-global driver=3Dnpcm7xx-pci-mbox,property=3Dchardev," + "value=3Dnpcm7xx-pcimbox-chr", + port); + setup_fd(); + qtest_irq_intercept_in(global_qtest, "/machine/soc/a9mpcore/gic"); + + qtest_add_func("/npcm7xx_pci_mbox/invalid_op", test_invalid_op); + qtest_add_func("/npcm7xx_pci_mbox/read", test_guest_read); + qtest_add_func("/npcm7xx_pci_mbox/write", test_guest_write); + ret =3D g_test_run(); + qtest_quit(global_qtest); + + return ret; +} --=20 2.42.0.459.ge4e396fd5e-goog From nobody Sat May 18 22:31:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1695154116; cv=none; d=zohomail.com; s=zohoarc; b=lp0lrrjZl+ej2MLxbW0G6cYuYEOnr3GrwBgamln2iOrx7hoKCJo8YfITK/Aybins7eJrO764/VDJXHx3BfPhnLXJaygBiVUgTD26sxp4aJdRuDARRtLXyzgkM2UsNPPWHKXUmXtmRfVWJ/1QbcJzwKu5rG7OqlY9dWhcKFKhqaM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695154116; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CHvC5wTahjfuba5l0G0vPMgx/0zA9GANXVfDsJXwy+c=; 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Tue, 19 Sep 2023 10:57:46 -0700 (PDT) Date: Tue, 19 Sep 2023 17:57:15 +0000 In-Reply-To: <20230919175725.3413108-1-nabihestefan@google.com> Mime-Version: 1.0 References: <20230919175725.3413108-1-nabihestefan@google.com> X-Mailer: git-send-email 2.42.0.459.ge4e396fd5e-goog Message-ID: <20230919175725.3413108-5-nabihestefan@google.com> Subject: [PATCH 04/14] hw/net: Add NPCM8XX PCS Module From: Nabih Estefan To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kfting@nuvoton.com, wuhaotsh@google.com, jasonwang@redhat.com, Avi.Fishman@nuvoton.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::549; envelope-from=3GuEJZQwKCjMcPQXWThiTUPcVddVaT.RdbfTbj-STkTacdcVcj.dgV@flex--nabihestefan.bounces.google.com; helo=mail-pg1-x549.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 19 Sep 2023 16:04:51 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1695154117313100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hao Wu The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII PHY. This implementation contains all the default registers and the soft reset feature that are required to load the Linux kernel driver. Further features have not been implemented yet. Signed-off-by: Hao Wu --- hw/net/npcm_pcs.c | 409 ++++++++++++++++++++++++++++++++++++++ include/hw/net/npcm_pcs.h | 42 ++++ 2 files changed, 451 insertions(+) create mode 100644 hw/net/npcm_pcs.c create mode 100644 include/hw/net/npcm_pcs.h diff --git a/hw/net/npcm_pcs.c b/hw/net/npcm_pcs.c new file mode 100644 index 0000000000..efe5f68d9c --- /dev/null +++ b/hw/net/npcm_pcs.c @@ -0,0 +1,409 @@ +/* + * Nuvoton NPCM8xx PCS Module + * + * Copyright 2022 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +/* + * Disclaimer: + * Currently we only implemented the default values of the registers and + * the soft reset feature. These are required to boot up the GMAC module + * in Linux kernel for NPCM845 boards. Other functionalities are not model= ed. + */ + +#include "qemu/osdep.h" + +#include "exec/hwaddr.h" +#include "hw/registerfields.h" +#include "hw/net/npcm_pcs.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/units.h" +#include "trace.h" + +#define NPCM_PCS_IND_AC_BA 0x1fe +#define NPCM_PCS_IND_SR_CTL 0x1e00 +#define NPCM_PCS_IND_SR_MII 0x1f00 +#define NPCM_PCS_IND_SR_TIM 0x1f07 +#define NPCM_PCS_IND_VR_MII 0x1f80 + +REG16(NPCM_PCS_SR_CTL_ID1, 0x08) +REG16(NPCM_PCS_SR_CTL_ID2, 0x0a) +REG16(NPCM_PCS_SR_CTL_STS, 0x10) + +REG16(NPCM_PCS_SR_MII_CTRL, 0x00) +REG16(NPCM_PCS_SR_MII_STS, 0x02) +REG16(NPCM_PCS_SR_MII_DEV_ID1, 0x04) +REG16(NPCM_PCS_SR_MII_DEV_ID2, 0x06) +REG16(NPCM_PCS_SR_MII_AN_ADV, 0x08) +REG16(NPCM_PCS_SR_MII_LP_BABL, 0x0a) +REG16(NPCM_PCS_SR_MII_AN_EXPN, 0x0c) +REG16(NPCM_PCS_SR_MII_EXT_STS, 0x1e) + +REG16(NPCM_PCS_SR_TIM_SYNC_ABL, 0x10) +REG16(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x12) +REG16(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0x14) +REG16(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x16) +REG16(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0x18) +REG16(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x1a) +REG16(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0x1c) +REG16(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x1e) +REG16(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0x20) + +REG16(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x000) +REG16(NPCM_PCS_VR_MII_AN_CTRL, 0x002) +REG16(NPCM_PCS_VR_MII_AN_INTR_STS, 0x004) +REG16(NPCM_PCS_VR_MII_TC, 0x006) +REG16(NPCM_PCS_VR_MII_DBG_CTRL, 0x00a) +REG16(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x00c) +REG16(NPCM_PCS_VR_MII_EEE_TXTIMER, 0x010) +REG16(NPCM_PCS_VR_MII_EEE_RXTIMER, 0x012) +REG16(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0x014) +REG16(NPCM_PCS_VR_MII_EEE_MCTRL1, 0x016) +REG16(NPCM_PCS_VR_MII_DIG_STS, 0x020) +REG16(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0x022) +REG16(NPCM_PCS_VR_MII_MISC_STS, 0x030) +REG16(NPCM_PCS_VR_MII_RX_LSTS, 0x040) +REG16(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x070) +REG16(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x074) +REG16(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x07a) +REG16(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0x07c) +REG16(NPCM_PCS_VR_MII_MP_TX_STS, 0x090) +REG16(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0b0) +REG16(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x0b2) +REG16(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x0ba) +REG16(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0f0) +REG16(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0f2) +REG16(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x110) +REG16(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0x126) +REG16(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x130) +REG16(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0x132) +REG16(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0x134) +REG16(NPCM_PCS_VR_MII_DIG_CTRL2, 0x1c2) +REG16(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0x1c4) + +/* Register Fields */ +#define NPCM_PCS_SR_MII_CTRL_RST BIT(15) + +static const uint16_t npcm_pcs_sr_ctl_cold_reset_values[NPCM_PCS_NR_SR_CTL= S] =3D { + [R_NPCM_PCS_SR_CTL_ID1] =3D 0x699e, + [R_NPCM_PCS_SR_CTL_STS] =3D 0x8000, +}; + +static const uint16_t npcm_pcs_sr_mii_cold_reset_values[NPCM_PCS_NR_SR_MII= S] =3D { + [R_NPCM_PCS_SR_MII_CTRL] =3D 0x1140, + [R_NPCM_PCS_SR_MII_STS] =3D 0x0109, + [R_NPCM_PCS_SR_MII_DEV_ID1] =3D 0x699e, + [R_NPCM_PCS_SR_MII_DEV_ID2] =3D 0xced0, + [R_NPCM_PCS_SR_MII_AN_ADV] =3D 0x0020, + [R_NPCM_PCS_SR_MII_EXT_STS] =3D 0xc000, +}; + +static const uint16_t npcm_pcs_sr_tim_cold_reset_values[NPCM_PCS_NR_SR_TIM= S] =3D { + [R_NPCM_PCS_SR_TIM_SYNC_ABL] =3D 0x0003, + [R_NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR] =3D 0x0038, + [R_NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR] =3D 0x0038, + [R_NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR] =3D 0x0058, + [R_NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR] =3D 0x0048, +}; + +static const uint16_t npcm_pcs_vr_mii_cold_reset_values[NPCM_PCS_NR_VR_MII= S] =3D { + [R_NPCM_PCS_VR_MII_MMD_DIG_CTRL1] =3D 0x2400, + [R_NPCM_PCS_VR_MII_AN_INTR_STS] =3D 0x000a, + [R_NPCM_PCS_VR_MII_EEE_MCTRL0] =3D 0x899c, + [R_NPCM_PCS_VR_MII_DIG_STS] =3D 0x0010, + [R_NPCM_PCS_VR_MII_MP_TX_BSTCTRL0] =3D 0x000a, + [R_NPCM_PCS_VR_MII_MP_TX_LVLCTRL0] =3D 0x007f, + [R_NPCM_PCS_VR_MII_MP_TX_GENCTRL0] =3D 0x0001, + [R_NPCM_PCS_VR_MII_MP_RX_GENCTRL0] =3D 0x0100, + [R_NPCM_PCS_VR_MII_MP_RX_GENCTRL1] =3D 0x1100, + [R_NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0] =3D 0x000e, + [R_NPCM_PCS_VR_MII_MP_MPLL_CTRL0] =3D 0x0100, + [R_NPCM_PCS_VR_MII_MP_MPLL_CTRL1] =3D 0x0032, + [R_NPCM_PCS_VR_MII_MP_MPLL_STS] =3D 0x0001, + [R_NPCM_PCS_VR_MII_MP_LVL_CTRL] =3D 0x0019, +}; + +static void npcm_pcs_soft_reset(NPCMPCSState *s) +{ + memcpy(s->sr_ctl, npcm_pcs_sr_ctl_cold_reset_values, + NPCM_PCS_NR_SR_CTLS * sizeof(uint16_t)); + memcpy(s->sr_mii, npcm_pcs_sr_mii_cold_reset_values, + NPCM_PCS_NR_SR_MIIS * sizeof(uint16_t)); + memcpy(s->sr_tim, npcm_pcs_sr_tim_cold_reset_values, + NPCM_PCS_NR_SR_TIMS * sizeof(uint16_t)); + memcpy(s->vr_mii, npcm_pcs_vr_mii_cold_reset_values, + NPCM_PCS_NR_VR_MIIS * sizeof(uint16_t)); +} + +static uint16_t npcm_pcs_read_sr_ctl(NPCMPCSState *s, hwaddr offset) +{ + hwaddr regno =3D offset / sizeof(uint16_t); + + if (regno >=3D NPCM_PCS_NR_SR_CTLS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: SR_CTL read offset 0x%04" HWADDR_PRIx + " is out of range.", + DEVICE(s)->canonical_path, offset); + return 0; + } + + return s->sr_ctl[regno]; +} + +static uint16_t npcm_pcs_read_sr_mii(NPCMPCSState *s, hwaddr offset) +{ + hwaddr regno =3D offset / sizeof(uint16_t); + + if (regno >=3D NPCM_PCS_NR_SR_MIIS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: SR_MII read offset 0x%04" HWADDR_PRIx + " is out of range.", + DEVICE(s)->canonical_path, offset); + return 0; + } + + return s->sr_mii[regno]; +} + +static uint16_t npcm_pcs_read_sr_tim(NPCMPCSState *s, hwaddr offset) +{ + hwaddr regno =3D offset / sizeof(uint16_t); + + if (regno >=3D NPCM_PCS_NR_SR_TIMS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: SR_TIM read offset 0x%04" HWADDR_PRIx + " is out of range.", + DEVICE(s)->canonical_path, offset); + return 0; + } + + return s->sr_tim[regno]; +} + +static uint16_t npcm_pcs_read_vr_mii(NPCMPCSState *s, hwaddr offset) +{ + hwaddr regno =3D offset / sizeof(uint16_t); + + if (regno >=3D NPCM_PCS_NR_VR_MIIS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: VR_MII read offset 0x%04" HWADDR_PRIx + " is out of range.", + DEVICE(s)->canonical_path, offset); + return 0; + } + + return s->vr_mii[regno]; +} + +static void npcm_pcs_write_sr_ctl(NPCMPCSState *s, hwaddr offset, uint16_t= v) +{ + hwaddr regno =3D offset / sizeof(uint16_t); + + if (regno >=3D NPCM_PCS_NR_SR_CTLS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: SR_CTL write offset 0x%04" HWADDR_PRIx + " is out of range.", + DEVICE(s)->canonical_path, offset); + return; + } + + s->sr_ctl[regno] =3D v; +} + +static void npcm_pcs_write_sr_mii(NPCMPCSState *s, hwaddr offset, uint16_t= v) +{ + hwaddr regno =3D offset / sizeof(uint16_t); + + if (regno >=3D NPCM_PCS_NR_SR_MIIS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: SR_MII write offset 0x%04" HWADDR_PRIx + " is out of range.", + DEVICE(s)->canonical_path, offset); + return; + } + + s->sr_mii[regno] =3D v; + + if ((offset =3D=3D A_NPCM_PCS_SR_MII_CTRL) && (v & NPCM_PCS_SR_MII_CTR= L_RST)) { + /* Trigger a soft reset */ + npcm_pcs_soft_reset(s); + } +} + +static void npcm_pcs_write_sr_tim(NPCMPCSState *s, hwaddr offset, uint16_t= v) +{ + hwaddr regno =3D offset / sizeof(uint16_t); + + if (regno >=3D NPCM_PCS_NR_SR_TIMS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: SR_TIM write offset 0x%04" HWADDR_PRIx + " is out of range.", + DEVICE(s)->canonical_path, offset); + return; + } + + s->sr_tim[regno] =3D v; +} + +static void npcm_pcs_write_vr_mii(NPCMPCSState *s, hwaddr offset, uint16_t= v) +{ + hwaddr regno =3D offset / sizeof(uint16_t); + + if (regno >=3D NPCM_PCS_NR_VR_MIIS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: VR_MII write offset 0x%04" HWADDR_PRIx + " is out of range.", + DEVICE(s)->canonical_path, offset); + return; + } + + s->vr_mii[regno] =3D v; +} + +static uint64_t npcm_pcs_read(void *opaque, hwaddr offset, unsigned size) +{ + NPCMPCSState *s =3D opaque; + uint16_t v =3D 0; + + if (offset =3D=3D NPCM_PCS_IND_AC_BA) { + v =3D s->indirect_access_base; + } else { + switch (s->indirect_access_base) { + case NPCM_PCS_IND_SR_CTL: + v =3D npcm_pcs_read_sr_ctl(s, offset); + break; + + case NPCM_PCS_IND_SR_MII: + v =3D npcm_pcs_read_sr_mii(s, offset); + break; + + case NPCM_PCS_IND_SR_TIM: + v =3D npcm_pcs_read_sr_tim(s, offset); + break; + + case NPCM_PCS_IND_VR_MII: + v =3D npcm_pcs_read_vr_mii(s, offset); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Read with invalid indirect address base: 0x= %02" + PRIx16 "\n", DEVICE(s)->canonical_path, + s->indirect_access_base); + } + } + + trace_npcm_pcs_reg_read(DEVICE(s)->canonical_path, s->indirect_access_= base, + offset, v); + return v; +} + +static void npcm_pcs_write(void *opaque, hwaddr offset, + uint64_t v, unsigned size) +{ + NPCMPCSState *s =3D opaque; + + trace_npcm_pcs_reg_write(DEVICE(s)->canonical_path, s->indirect_access= _base, + offset, v); + if (offset =3D=3D NPCM_PCS_IND_AC_BA) { + s->indirect_access_base =3D v; + } else { + switch (s->indirect_access_base) { + case NPCM_PCS_IND_SR_CTL: + npcm_pcs_write_sr_ctl(s, offset, v); + break; + + case NPCM_PCS_IND_SR_MII: + npcm_pcs_write_sr_mii(s, offset, v); + break; + + case NPCM_PCS_IND_SR_TIM: + npcm_pcs_write_sr_tim(s, offset, v); + break; + + case NPCM_PCS_IND_VR_MII: + npcm_pcs_write_vr_mii(s, offset, v); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Write with invalid indirect address base: 0= x%02" + PRIx16 "\n", DEVICE(s)->canonical_path, + s->indirect_access_base); + } + } +} + +static void npcm_pcs_reset(DeviceState *dev) +{ + NPCMPCSState *s =3D NPCM_PCS(dev); + + npcm_pcs_soft_reset(s); +} + +static const struct MemoryRegionOps npcm_pcs_ops =3D { + .read =3D npcm_pcs_read, + .write =3D npcm_pcs_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 2, + .max_access_size =3D 2, + .unaligned =3D false, + }, +}; + +static void npcm_pcs_realize(DeviceState *dev, Error **errp) +{ + NPCMPCSState *pcs =3D NPCM_PCS(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + memory_region_init_io(&pcs->iomem, OBJECT(pcs), &npcm_pcs_ops, pcs, + TYPE_NPCM_PCS, 8 * KiB); + sysbus_init_mmio(sbd, &pcs->iomem); +} + +static const VMStateDescription vmstate_npcm_pcs =3D { + .name =3D TYPE_NPCM_PCS, + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT16(indirect_access_base, NPCMPCSState), + VMSTATE_UINT16_ARRAY(sr_ctl, NPCMPCSState, NPCM_PCS_NR_SR_CTLS), + VMSTATE_UINT16_ARRAY(sr_mii, NPCMPCSState, NPCM_PCS_NR_SR_MIIS), + VMSTATE_UINT16_ARRAY(sr_tim, NPCMPCSState, NPCM_PCS_NR_SR_TIMS), + VMSTATE_UINT16_ARRAY(vr_mii, NPCMPCSState, NPCM_PCS_NR_VR_MIIS), + VMSTATE_END_OF_LIST(), + }, +}; + +static void npcm_pcs_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); + dc->desc =3D "NPCM PCS Controller"; + dc->realize =3D npcm_pcs_realize; + dc->reset =3D npcm_pcs_reset; + dc->vmsd =3D &vmstate_npcm_pcs; +} + +static const TypeInfo npcm_pcs_types[] =3D { + { + .name =3D TYPE_NPCM_PCS, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NPCMPCSState), + .class_init =3D npcm_pcs_class_init, + }, +}; +DEFINE_TYPES(npcm_pcs_types) diff --git a/include/hw/net/npcm_pcs.h b/include/hw/net/npcm_pcs.h new file mode 100644 index 0000000000..bd4f71bf3c --- /dev/null +++ b/include/hw/net/npcm_pcs.h @@ -0,0 +1,42 @@ +/* + * Nuvoton NPCM8xx PCS Module + * + * Copyright 2022 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef NPCM_PCS_H +#define NPCM_PCS_H + +#include "hw/sysbus.h" + +#define NPCM_PCS_NR_SR_CTLS (0x12 / sizeof(uint16_t)) +#define NPCM_PCS_NR_SR_MIIS (0x20 / sizeof(uint16_t)) +#define NPCM_PCS_NR_SR_TIMS (0x22 / sizeof(uint16_t)) +#define NPCM_PCS_NR_VR_MIIS (0x1c6 / sizeof(uint16_t)) + +typedef struct NPCMPCSState { + SysBusDevice parent; + + MemoryRegion iomem; + + uint16_t indirect_access_base; + uint16_t sr_ctl[NPCM_PCS_NR_SR_CTLS]; + uint16_t sr_mii[NPCM_PCS_NR_SR_MIIS]; + uint16_t sr_tim[NPCM_PCS_NR_SR_TIMS]; + uint16_t vr_mii[NPCM_PCS_NR_VR_MIIS]; +} NPCMPCSState; + +#define TYPE_NPCM_PCS "npcm-pcs" +OBJECT_DECLARE_SIMPLE_TYPE(NPCMPCSState, NPCM_PCS) + +#endif /* NPCM_PCS_H */ --=20 2.42.0.459.ge4e396fd5e-goog From nobody Sat May 18 22:31:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: Hao Wu This patch implements the basic registers of GMAC device. Actual network communications are not supported yet. Signed-off-by: Hao Wu include/hw: Fix type problem in NPCMGMACState - Fix type problem in NPCMGMACState - Fix Register Initalization which was breaking boot-up in driver - Added trace for NPCM_GMAC reset - Added nd_table to npcm8xx.c for GMAC bootup Signed-off-by: Nabih Estefan Diaz hw/net: Add BCM54612E PHY regs for GMAC This patch adds default values for PHYs to make the driver happy. The device is derived from an actual Izumi machine. Signed-off-by: Hao Wu hw/net: change GMAC PHY regs to indicate link is up This change makes NPCM GMAC module to use BCM54612E unconditionally and make some fake PHY registers such that the kernel driver thinks the link partner is up. Tested: The following message shows up with the change: Broadcom BCM54612E stmmac-0:00: attached PHY driver [Broadcom BCM54612E] (m= ii_bus:phy_addr=3Dstmmac-0:00, irq=3DPOLL) stmmaceth f0802000.eth eth0: Link is Up - 1Gbps/Full - flow control rx/tx Signed-off-by: Hao Wu --- hw/arm/npcm8xx.c | 905 +++++++++++++++++++++++++++++++++++++ hw/net/meson.build | 3 +- hw/net/npcm_gmac.c | 395 ++++++++++++++++ hw/net/trace-events | 11 + include/hw/net/npcm_gmac.h | 172 +++++++ 5 files changed, 1485 insertions(+), 1 deletion(-) create mode 100644 hw/arm/npcm8xx.c create mode 100644 hw/net/npcm_gmac.c create mode 100644 include/hw/net/npcm_gmac.h diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c new file mode 100644 index 0000000000..a05dcfed5c --- /dev/null +++ b/hw/arm/npcm8xx.c @@ -0,0 +1,905 @@ +/* + * Nuvoton NPCM8xx SoC family. + * + * Copyright 2022 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" + +#include "hw/arm/boot.h" +#include "hw/arm/npcm8xx.h" +#include "hw/char/serial.h" +#include "hw/intc/arm_gic.h" +#include "hw/loader.h" +#include "hw/misc/unimp.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/units.h" +#include "sysemu/sysemu.h" + +#define ARM_PHYS_TIMER_PPI 30 +#define ARM_VIRT_TIMER_PPI 27 +#define ARM_HYP_TIMER_PPI 26 +#define ARM_SEC_TIMER_PPI 29 + +/* + * This covers the whole MMIO space. We'll use this to catch any MMIO acce= sses + * that aren't handled by a device. + */ +#define NPCM8XX_MMIO_BA (0x80000000) +#define NPCM8XX_MMIO_SZ (0x7ffd0000) + +/* OTP fuse array */ +#define NPCM8XX_OTP_BA (0xf0189000) + +/* GIC Distributor */ +#define NPCM8XX_GICD_BA (0xdfff9000) +#define NPCM8XX_GICC_BA (0xdfffa000) + +/* Core system modules. */ +#define NPCM8XX_CPUP_BA (0xf03fe000) +#define NPCM8XX_GCR_BA (0xf0800000) +#define NPCM8XX_CLK_BA (0xf0801000) +#define NPCM8XX_MC_BA (0xf0824000) +#define NPCM8XX_RNG_BA (0xf000b000) +#define NPCM8XX_KCS_BA (0xf0007000) +#define NPCM8XX_PECI_BA (0xf0100000) +#define NPCM8XX_PCIERC_BA (0xe1000000) +#define NPCM8XX_PCIE_ROOT_BA (0xe8000000) + +/* ADC Module */ +#define NPCM8XX_ADC_BA (0xf000c000) + +/* Internal AHB SRAM */ +#define NPCM8XX_RAM3_BA (0xc0008000) +#define NPCM8XX_RAM3_SZ (4 * KiB) + +/* Memory blocks at the end of the address space */ +#define NPCM8XX_RAM2_BA (0xfffb0000) +#define NPCM8XX_RAM2_SZ (256 * KiB) +#define NPCM8XX_ROM_BA (0xffff0100) +#define NPCM8XX_ROM_SZ (64 * KiB) + +/* SDHCI Modules */ +#define NPCM8XX_MMC_BA (0xf0842000) + +/* PCS Module */ +#define NPCM8XX_PCS_BA (0xf0780000) + +/* Run PLL1 at 1600 MHz */ +#define NPCM8XX_PLLCON1_FIXUP_VAL (0x00402101) +/* Run the CPU from PLL1 and UART from PLL2 */ +#define NPCM8XX_CLKSEL_FIXUP_VAL (0x004aaba9) + +/* Clock configuration values to be fixed up when bypassing bootloader */ + +/* + * Interrupt lines going into the GIC. This does not include internal Cort= ex-A9 + * interrupts. + */ +enum NPCM8xxInterrupt { + NPCM8XX_ADC_IRQ =3D 0, + NPCM8XX_PECI_IRQ =3D 6, + NPCM8XX_KCS_HIB_IRQ =3D 9, + NPCM8XX_GMAC1_IRQ =3D 14, + NPCM8XX_GMAC2_IRQ, + NPCM8XX_GMAC3_IRQ, + NPCM8XX_GMAC4_IRQ, + NPCM8XX_MMC_IRQ =3D 26, + NPCM8XX_TIMER0_IRQ =3D 32, /* Timer Module 0 */ + NPCM8XX_TIMER1_IRQ, + NPCM8XX_TIMER2_IRQ, + NPCM8XX_TIMER3_IRQ, + NPCM8XX_TIMER4_IRQ, + NPCM8XX_TIMER5_IRQ, /* Timer Module 1 */ + NPCM8XX_TIMER6_IRQ, + NPCM8XX_TIMER7_IRQ, + NPCM8XX_TIMER8_IRQ, + NPCM8XX_TIMER9_IRQ, + NPCM8XX_TIMER10_IRQ, /* Timer Module 2 */ + NPCM8XX_TIMER11_IRQ, + NPCM8XX_TIMER12_IRQ, + NPCM8XX_TIMER13_IRQ, + NPCM8XX_TIMER14_IRQ, + NPCM8XX_WDG0_IRQ =3D 47, /* Timer Module 0 Watchdog */ + NPCM8XX_WDG1_IRQ, /* Timer Module 1 Watchdog */ + NPCM8XX_WDG2_IRQ, /* Timer Module 2 Watchdog */ + NPCM8XX_EHCI1_IRQ =3D 61, + NPCM8XX_OHCI1_IRQ, + NPCM8XX_EHCI2_IRQ, + NPCM8XX_OHCI2_IRQ, + NPCM8XX_PWM0_IRQ =3D 93, /* PWM module 0 */ + NPCM8XX_PWM1_IRQ, /* PWM module 1 */ + NPCM8XX_MFT0_IRQ =3D 96, /* MFT module 0 */ + NPCM8XX_MFT1_IRQ, /* MFT module 1 */ + NPCM8XX_MFT2_IRQ, /* MFT module 2 */ + NPCM8XX_MFT3_IRQ, /* MFT module 3 */ + NPCM8XX_MFT4_IRQ, /* MFT module 4 */ + NPCM8XX_MFT5_IRQ, /* MFT module 5 */ + NPCM8XX_MFT6_IRQ, /* MFT module 6 */ + NPCM8XX_MFT7_IRQ, /* MFT module 7 */ + NPCM8XX_PCI_MBOX1_IRQ =3D 105, + NPCM8XX_PCI_MBOX2_IRQ, + NPCM8XX_GPIO0_IRQ =3D 116, + NPCM8XX_GPIO1_IRQ, + NPCM8XX_GPIO2_IRQ, + NPCM8XX_GPIO3_IRQ, + NPCM8XX_GPIO4_IRQ, + NPCM8XX_GPIO5_IRQ, + NPCM8XX_GPIO6_IRQ, + NPCM8XX_GPIO7_IRQ, + NPCM8XX_PCIE_RC_IRQ =3D 127, + NPCM8XX_SMBUS0_IRQ =3D 128, + NPCM8XX_SMBUS1_IRQ, + NPCM8XX_SMBUS2_IRQ, + NPCM8XX_SMBUS3_IRQ, + NPCM8XX_SMBUS4_IRQ, + NPCM8XX_SMBUS5_IRQ, + NPCM8XX_SMBUS6_IRQ, + NPCM8XX_SMBUS7_IRQ, + NPCM8XX_SMBUS8_IRQ, + NPCM8XX_SMBUS9_IRQ, + NPCM8XX_SMBUS10_IRQ, + NPCM8XX_SMBUS11_IRQ, + NPCM8XX_SMBUS12_IRQ, + NPCM8XX_SMBUS13_IRQ, + NPCM8XX_SMBUS14_IRQ, + NPCM8XX_SMBUS15_IRQ, + NPCM8XX_SMBUS16_IRQ, + NPCM8XX_SMBUS17_IRQ, + NPCM8XX_SMBUS18_IRQ, + NPCM8XX_SMBUS19_IRQ, + NPCM8XX_SMBUS20_IRQ, + NPCM8XX_SMBUS21_IRQ, + NPCM8XX_SMBUS22_IRQ, + NPCM8XX_SMBUS23_IRQ, + NPCM8XX_SMBUS24_IRQ, + NPCM8XX_SMBUS25_IRQ, + NPCM8XX_SMBUS26_IRQ, + NPCM8XX_UART0_IRQ =3D 192, + NPCM8XX_UART1_IRQ, + NPCM8XX_UART2_IRQ, + NPCM8XX_UART3_IRQ, + NPCM8XX_UART4_IRQ, + NPCM8XX_UART5_IRQ, + NPCM8XX_UART6_IRQ, +}; + +/* Total number of GIC interrupts, including internal Cortex-A35 interrupt= s. */ +#define NPCM8XX_NUM_IRQ (288) +#define NPCM8XX_PPI_BASE(cpu) ((NPCM8XX_NUM_IRQ - 32) + (cpu) * 32) + +/* Register base address for each Timer Module */ +static const hwaddr npcm8xx_tim_addr[] =3D { + 0xf0008000, + 0xf0009000, + 0xf000a000, +}; + +/* Register base address for each 16550 UART */ +static const hwaddr npcm8xx_uart_addr[] =3D { + 0xf0000000, + 0xf0001000, + 0xf0002000, + 0xf0003000, + 0xf0004000, + 0xf0005000, + 0xf0006000, +}; + +/* Direct memory-mapped access to SPI0 CS0-1. */ +static const hwaddr npcm8xx_fiu0_flash_addr[] =3D { + 0x80000000, /* CS0 */ + 0x88000000, /* CS1 */ +}; + +/* Direct memory-mapped access to SPI1 CS0-3. */ +static const hwaddr npcm8xx_fiu1_flash_addr[] =3D { + 0x90000000, /* CS0 */ + 0x91000000, /* CS1 */ + 0x92000000, /* CS2 */ + 0x93000000, /* CS3 */ +}; + +/* Direct memory-mapped access to SPI3 CS0-3. */ +static const hwaddr npcm8xx_fiu3_flash_addr[] =3D { + 0xa0000000, /* CS0 */ + 0xa8000000, /* CS1 */ + 0xb0000000, /* CS2 */ + 0xb8000000, /* CS3 */ +}; + +/* Register base address for each PWM Module */ +static const hwaddr npcm8xx_pwm_addr[] =3D { + 0xf0103000, + 0xf0104000, + 0xf0105000, +}; + +/* Register base address for each MFT Module */ +static const hwaddr npcm8xx_mft_addr[] =3D { + 0xf0180000, + 0xf0181000, + 0xf0182000, + 0xf0183000, + 0xf0184000, + 0xf0185000, + 0xf0186000, + 0xf0187000, +}; + +/* Direct memory-mapped access to each SMBus Module. */ +static const hwaddr npcm8xx_smbus_addr[] =3D { + 0xf0080000, + 0xf0081000, + 0xf0082000, + 0xf0083000, + 0xf0084000, + 0xf0085000, + 0xf0086000, + 0xf0087000, + 0xf0088000, + 0xf0089000, + 0xf008a000, + 0xf008b000, + 0xf008c000, + 0xf008d000, + 0xf008e000, + 0xf008f000, + 0xfff00000, + 0xfff01000, + 0xfff02000, + 0xfff03000, + 0xfff04000, + 0xfff05000, + 0xfff06000, + 0xfff07000, + 0xfff08000, + 0xfff09000, + 0xfff0a000, +}; + +/* Register base address for each GMAC Module */ +static const hwaddr npcm8xx_gmac_addr[] =3D { + 0xf0802000, + 0xf0804000, + 0xf0806000, + 0xf0808000, +}; + +/* Register base address for each USB host EHCI registers */ +static const hwaddr npcm8xx_ehci_addr[] =3D { + 0xf0828100, + 0xf082a100, +}; + +/* Register base address for each USB host OHCI registers */ +static const hwaddr npcm8xx_ohci_addr[] =3D { + 0xf0829000, + 0xf082b000, +}; + +/* Register base address for each PCI mailbox module */ +static const hwaddr npcm8xx_pci_mbox_addr[] =3D { + 0xf0848000, + 0xf0868000, +}; + +static const struct { + hwaddr regs_addr; + uint32_t reset_pu; + uint32_t reset_pd; + uint32_t reset_osrc; + uint32_t reset_odsc; +} npcm8xx_gpio[] =3D { + { + .regs_addr =3D 0xf0010000, + .reset_pu =3D 0x00000300, + .reset_pd =3D 0x000f0000, + }, { + .regs_addr =3D 0xf0011000, + .reset_pu =3D 0xe0fefe01, + .reset_pd =3D 0x07000000, + }, { + .regs_addr =3D 0xf0012000, + .reset_pu =3D 0xc00fffff, + .reset_pd =3D 0x3ff00000, + }, { + .regs_addr =3D 0xf0013000, + .reset_pd =3D 0x00003000, + }, { + .regs_addr =3D 0xf0014000, + .reset_pu =3D 0xffff0000, + }, { + .regs_addr =3D 0xf0015000, + .reset_pu =3D 0xff8387fe, + .reset_pd =3D 0x007c0001, + .reset_osrc =3D 0x08000000, + }, { + .regs_addr =3D 0xf0016000, + .reset_pu =3D 0x00000801, + .reset_pd =3D 0x00000302, + }, { + .regs_addr =3D 0xf0017000, + .reset_pu =3D 0x000002ff, + .reset_pd =3D 0x00000c00, + }, +}; + +static const struct { + const char *name; + hwaddr regs_addr; + int cs_count; + const hwaddr *flash_addr; + size_t flash_size; +} npcm8xx_fiu[] =3D { + { + .name =3D "fiu0", + .regs_addr =3D 0xfb000000, + .cs_count =3D ARRAY_SIZE(npcm8xx_fiu0_flash_addr), + .flash_addr =3D npcm8xx_fiu0_flash_addr, + .flash_size =3D 128 * MiB, + }, + { + .name =3D "fiu1", + .regs_addr =3D 0xfb002000, + .cs_count =3D ARRAY_SIZE(npcm8xx_fiu1_flash_addr), + .flash_addr =3D npcm8xx_fiu1_flash_addr, + .flash_size =3D 16 * MiB, + }, { + .name =3D "fiu3", + .regs_addr =3D 0xc0000000, + .cs_count =3D ARRAY_SIZE(npcm8xx_fiu3_flash_addr), + .flash_addr =3D npcm8xx_fiu3_flash_addr, + .flash_size =3D 128 * MiB, + }, +}; + +static struct arm_boot_info npcm8xx_binfo =3D { + .loader_start =3D NPCM8XX_LOADER_START, + .smp_loader_start =3D NPCM8XX_SMP_LOADER_START, + .smp_bootreg_addr =3D NPCM8XX_SMP_BOOTREG_ADDR, + .gic_cpu_if_addr =3D NPCM8XX_GICC_BA, + .secure_boot =3D false, + .board_id =3D -1, + .board_setup_addr =3D NPCM8XX_BOARD_SETUP_ADDR, +}; + +void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc) +{ + npcm8xx_binfo.ram_size =3D machine->ram_size; + + arm_load_kernel(&soc->cpu[0], machine, &npcm8xx_binfo); +} + +static void npcm8xx_init_fuses(NPCM8xxState *s) +{ + NPCM8xxClass *nc =3D NPCM8XX_GET_CLASS(s); + uint32_t value; + + /* + * The initial mask of disabled modules indicates the chip derivative = (e.g. + * NPCM750 or NPCM730). + */ + value =3D tswap32(nc->disabled_modules); + npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIV= E, + sizeof(value)); +} + +static void npcm8xx_write_adc_calibration(NPCM8xxState *s) +{ + /* Both ADC and the fuse array must have realized. */ + QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) !=3D 4); + npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values, + NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values)); +} + +static qemu_irq npcm8xx_irq(NPCM8xxState *s, int n) +{ + return qdev_get_gpio_in(DEVICE(&s->gic), n); +} + +static void npcm8xx_init(Object *obj) +{ + NPCM8xxState *s =3D NPCM8XX(obj); + int i; + + object_initialize_child(obj, "cpu-cluster", &s->cpu_cluster, + TYPE_CPU_CLUSTER); + for (i =3D 0; i < NPCM8XX_MAX_NUM_CPUS; i++) { + object_initialize_child(OBJECT(&s->cpu_cluster), "cpu[*]", &s->cpu= [i], + ARM_CPU_TYPE_NAME("cortex-a53")); + } + object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); + object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM8XX_GCR); + object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr), + "power-on-straps"); + object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM8XX_CLK); + object_initialize_child(obj, "otp", &s->fuse_array, + TYPE_NPCM7XX_FUSE_ARRAY); + object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC); + object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG); + object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC); + + for (i =3D 0; i < ARRAY_SIZE(s->tim); i++) { + object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TI= MER); + } + + for (i =3D 0; i < ARRAY_SIZE(s->gpio); i++) { + object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_= GPIO); + } + + object_initialize_child(obj, "gpiotx", &s->gpiotx, + TYPE_GOOGLE_GPIO_TRANSMITTER); + + for (i =3D 0; i < ARRAY_SIZE(s->smbus); i++) { + object_initialize_child(obj, "smbus[*]", &s->smbus[i], + TYPE_NPCM8XX_SMBUS); + DEVICE(&s->smbus[i])->id =3D g_strdup_printf("smbus[%d]", i); + } + + object_initialize_child(obj, "kcs", &s->kcs, TYPE_NPCM7XX_KCS); + + for (i =3D 0; i < ARRAY_SIZE(s->ehci); i++) { + object_initialize_child(obj, "ehci[*]", &s->ehci[i], TYPE_NPCM7XX_= EHCI); + } + for (i =3D 0; i < ARRAY_SIZE(s->ohci); i++) { + object_initialize_child(obj, "ohci[*]", &s->ohci[i], TYPE_SYSBUS_O= HCI); + } + + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_fiu) !=3D ARRAY_SIZE(s->fiu)); + for (i =3D 0; i < ARRAY_SIZE(s->fiu); i++) { + object_initialize_child(obj, npcm8xx_fiu[i].name, &s->fiu[i], + TYPE_NPCM7XX_FIU); + } + + for (i =3D 0; i < ARRAY_SIZE(s->pwm); i++) { + object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PW= M); + } + + for (i =3D 0; i < ARRAY_SIZE(s->mft); i++) { + object_initialize_child(obj, "mft[*]", &s->mft[i], TYPE_NPCM7XX_MF= T); + } + + for (i =3D 0; i < ARRAY_SIZE(s->gmac); i++) { + object_initialize_child(obj, "gmac[*]", &s->gmac[i], TYPE_NPCM_GMA= C); + } + object_initialize_child(obj, "pcs", &s->pcs, TYPE_NPCM_PCS); + + for (i =3D 0; i < ARRAY_SIZE(s->pci_mbox); i++) { + object_initialize_child(obj, "pci-mbox[*]", &s->pci_mbox[i], + TYPE_NPCM7XX_PCI_MBOX); + } + object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); + object_initialize_child(obj, "peci", &s->peci, TYPE_NPCM7XX_PECI); + object_initialize_child(obj, "pcierc", &s->pcierc, TYPE_NPCM_PCIERC); +} + +static void npcm8xx_realize(DeviceState *dev, Error **errp) +{ + NPCM8xxState *s =3D NPCM8XX(dev); + NPCM8xxClass *nc =3D NPCM8XX_GET_CLASS(s); + int i; + + if (memory_region_size(s->dram) > NPCM8XX_DRAM_SZ) { + error_setg(errp, "%s: NPCM8xx cannot address more than %" PRIu64 + " MiB of DRAM", __func__, NPCM8XX_DRAM_SZ / MiB); + return; + } + + /* CPUs */ + for (i =3D 0; i < nc->num_cpus; i++) { + object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", + arm_cpu_mp_affinity(i, NPCM8XX_MAX_NUM_CPU= S), + &error_abort); + object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, + &error_abort); + object_property_set_int(OBJECT(&s->cpu[i]), "core-count", + nc->num_cpus, &error_abort); + + /* Disable security extensions. */ + object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false, + &error_abort); + + if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { + return; + } + } + + /* ARM GIC for Cortex A35. Can only fail if we pass bad parameters her= e. */ + object_property_set_uint(OBJECT(&s->gic), "num-cpu", nc->num_cpus, err= p); + object_property_set_uint(OBJECT(&s->gic), "num-irq", NPCM8XX_NUM_IRQ, = errp); + object_property_set_uint(OBJECT(&s->gic), "revision", 2, errp); + object_property_set_bool(OBJECT(&s->gic), "has-security-extensions", t= rue, + errp); + object_property_set_bool(OBJECT(&s->gic), "irq-reset-nonsecure", true, + errp); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { + return; + } + for (i =3D 0; i < nc->num_cpus; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, + qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IR= Q)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus, + qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FI= Q)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus * 2, + qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_VI= RQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + nc->num_cpus * 3, + qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_VF= IQ)); + + qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_PHYS, + qdev_get_gpio_in(DEVICE(&s->gic), + NPCM8XX_PPI_BASE(i) + ARM_PHYS_TIMER_PPI)); + qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_VIRT, + qdev_get_gpio_in(DEVICE(&s->gic), + NPCM8XX_PPI_BASE(i) + ARM_VIRT_TIMER_PPI)); + qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_HYP, + qdev_get_gpio_in(DEVICE(&s->gic), + NPCM8XX_PPI_BASE(i) + ARM_HYP_TIMER_PPI)); + qdev_connect_gpio_out(DEVICE(&s->cpu[i]), GTIMER_SEC, + qdev_get_gpio_in(DEVICE(&s->gic), + NPCM8XX_PPI_BASE(i) + ARM_SEC_TIMER_PPI)); + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, NPCM8XX_GICD_BA); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, NPCM8XX_GICC_BA); + + /* CPU cluster */ + qdev_prop_set_uint32(DEVICE(&s->cpu_cluster), "cluster-id", 0); + qdev_realize(DEVICE(&s->cpu_cluster), NULL, &error_fatal); + + /* System Global Control Registers (GCR). Can fail due to user input. = */ + object_property_set_int(OBJECT(&s->gcr), "disabled-modules", + nc->disabled_modules, &error_abort); + object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->d= ram)); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM8XX_GCR_BA); + + /* Clock Control Registers (CLK). Cannot fail. */ + sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM8XX_CLK_BA); + + /* OTP fuse strap array. Cannot fail. */ + sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM8XX_OTP_BA); + npcm8xx_init_fuses(s); + + /* Fake Memory Controller (MC). Cannot fail. */ + sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM8XX_MC_BA); + + /* ADC Modules. Cannot fail. */ + qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out( + DEVICE(&s->clk), "adc-clock")); + sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM8XX_ADC_BA); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, + npcm8xx_irq(s, NPCM8XX_ADC_IRQ)); + npcm8xx_write_adc_calibration(s); + + /* Timer Modules (TIM). Cannot fail. */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_tim_addr) !=3D ARRAY_SIZE(s->tim)= ); + for (i =3D 0; i < ARRAY_SIZE(s->tim); i++) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->tim[i]); + int first_irq; + int j; + + /* Connect the timer clock. */ + qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_= out( + DEVICE(&s->clk), "timer-clock")); + + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, npcm8xx_tim_addr[i]); + + first_irq =3D NPCM8XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL; + for (j =3D 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) { + qemu_irq irq =3D npcm8xx_irq(s, first_irq + j); + sysbus_connect_irq(sbd, j, irq); + } + + /* IRQ for watchdogs */ + sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL, + npcm8xx_irq(s, NPCM8XX_WDG0_IRQ + i)); + /* GPIO that connects clk module with watchdog */ + /* TODO: Check this.*/ + qdev_connect_gpio_out_named(DEVICE(&s->tim[i]), + NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0, + qdev_get_gpio_in_named(DEVICE(&s->clk), + NPCM7XX_WATCHDOG_RESET_GPIO_IN, i)); + } + + /* UART0..6 (16550 compatible) */ + for (i =3D 0; i < ARRAY_SIZE(npcm8xx_uart_addr); i++) { + serial_mm_init(get_system_memory(), npcm8xx_uart_addr[i], 2, + npcm8xx_irq(s, NPCM8XX_UART0_IRQ + i), 115200, + serial_hd(i), DEVICE_LITTLE_ENDIAN); + } + + /* Random Number Generator. Cannot fail. */ + sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM8XX_RNG_BA); + + /* GPIO modules. Cannot fail. */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_gpio) !=3D ARRAY_SIZE(s->gpio)); + sysbus_realize(SYS_BUS_DEVICE(&s->gpiotx), &error_abort); + for (i =3D 0; i < ARRAY_SIZE(s->gpio); i++) { + Object *obj =3D OBJECT(&s->gpio[i]); + + object_property_set_link(obj, "gpio-tx", OBJECT(&s->gpiotx), + &error_abort); + object_property_set_uint(obj, "reset-pullup", + npcm8xx_gpio[i].reset_pu, &error_abort); + object_property_set_uint(obj, "reset-pulldown", + npcm8xx_gpio[i].reset_pd, &error_abort); + object_property_set_uint(obj, "reset-osrc", + npcm8xx_gpio[i].reset_osrc, &error_abort); + object_property_set_uint(obj, "reset-odsc", + npcm8xx_gpio[i].reset_odsc, &error_abort); + sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm8xx_gpio[i].regs_addr); + sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, + npcm8xx_irq(s, NPCM8XX_GPIO0_IRQ + i)); + } + + /* SMBus modules. Cannot fail. */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_smbus_addr) !=3D ARRAY_SIZE(s->sm= bus)); + for (i =3D 0; i < ARRAY_SIZE(s->smbus); i++) { + Object *obj =3D OBJECT(&s->smbus[i]); + + sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm8xx_smbus_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0, + npcm8xx_irq(s, NPCM8XX_SMBUS0_IRQ + i)); + } + + /* KCS modules*/ + sysbus_realize(SYS_BUS_DEVICE(&s->kcs), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->kcs), 0, NPCM8XX_KCS_BA); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->kcs), 0, + npcm8xx_irq(s, NPCM8XX_KCS_HIB_IRQ)); + + /* USB Host */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->ohci) !=3D ARRAY_SIZE(s->ehci)); + for (i =3D 0; i < ARRAY_SIZE(s->ehci); i++) { + object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", = true, + &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, npcm8xx_ehci_addr[= i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, + npcm8xx_irq(s, NPCM8XX_EHCI1_IRQ + 2 * i)); + } + for (i =3D 0; i < ARRAY_SIZE(s->ohci); i++) { + object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", "usb-bus= .0", + &error_abort); + object_property_set_uint(OBJECT(&s->ohci[i]), "num-ports", 1, + &error_abort); + object_property_set_uint(OBJECT(&s->ohci[i]), "firstport", i, + &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0, npcm8xx_ohci_addr[= i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0, + npcm8xx_irq(s, NPCM8XX_OHCI1_IRQ + 2 * i)); + } + + /* PWM Modules. Cannot fail. */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_pwm_addr) !=3D ARRAY_SIZE(s->pwm)= ); + for (i =3D 0; i < ARRAY_SIZE(s->pwm); i++) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->pwm[i]); + + qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_= out( + DEVICE(&s->clk), "apb3-clock")); + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, npcm8xx_pwm_addr[i]); + sysbus_connect_irq(sbd, i, npcm8xx_irq(s, NPCM8XX_PWM0_IRQ + i)); + } + + /* MFT Modules. Cannot fail. */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_mft_addr) !=3D ARRAY_SIZE(s->mft)= ); + for (i =3D 0; i < ARRAY_SIZE(s->mft); i++) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->mft[i]); + + qdev_connect_clock_in(DEVICE(&s->mft[i]), "clock-in", + qdev_get_clock_out(DEVICE(&s->clk), + "apb4-clock")); + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, npcm8xx_mft_addr[i]); + sysbus_connect_irq(sbd, 0, npcm8xx_irq(s, NPCM8XX_MFT0_IRQ + i)); + } + + /* + * GMAC Modules. Cannot fail. + */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_gmac_addr) !=3D ARRAY_SIZE(s->gma= c)); + for (i =3D 0; i < ARRAY_SIZE(s->gmac); i++) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->gmac[i]); + + /* This is used to make sure that the NIC can create the device */ + if (nd_table[i].used) { + qemu_check_nic_model(&nd_table[i], TYPE_NPCM_GMAC); + qdev_set_nic_properties(DEVICE(sbd), &nd_table[i]); + } + + /* + * The device exists regardless of whether it's connected to a QEMU + * netdev backend. So always instantiate it even if there is no + * backend. + */ + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, npcm8xx_gmac_addr[i]); + /* + * N.B. The values for the second argument sysbus_connect_irq are + * chosen to match the registration order in npcm7xx_emc_realize. + */ + sysbus_connect_irq(sbd, 0, npcm8xx_irq(s, NPCM8XX_GMAC1_IRQ + i)); + } + /* + * GMAC Physical Coding Sublayer(PCS) Module. Cannot fail. + */ + sysbus_realize(SYS_BUS_DEVICE(&s->pcs), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcs), 0, NPCM8XX_PCS_BA); + s->gmac[0].pcs =3D &s->pcs; + + /* + * Flash Interface Unit (FIU). Can fail if incorrect number of chip se= lects + * specified, but this is a programming error. + */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_fiu) !=3D ARRAY_SIZE(s->fiu)); + for (i =3D 0; i < ARRAY_SIZE(s->fiu); i++) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->fiu[i]); + int j; + + object_property_set_int(OBJECT(sbd), "cs-count", + npcm8xx_fiu[i].cs_count, &error_abort); + object_property_set_int(OBJECT(sbd), "flash-size", + npcm8xx_fiu[i].flash_size, &error_abort); + sysbus_realize(sbd, &error_abort); + + sysbus_mmio_map(sbd, 0, npcm8xx_fiu[i].regs_addr); + for (j =3D 0; j < npcm8xx_fiu[i].cs_count; j++) { + sysbus_mmio_map(sbd, j + 1, npcm8xx_fiu[i].flash_addr[j]); + } + } + + /* PCI Mailbox. Cannot fail */ + for (i =3D 0; i < ARRAY_SIZE(s->pci_mbox); i++) { + sysbus_realize(SYS_BUS_DEVICE(&s->pci_mbox[i]), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->pci_mbox[i]), 0, + npcm8xx_pci_mbox_addr[i]); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->pci_mbox[i]), 1, + npcm8xx_pci_mbox_addr[i] + NPCM7XX_PCI_MBOX_RAM_SI= ZE); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pci_mbox), 0, + npcm8xx_irq(s, NPCM8XX_PCI_MBOX1_IRQ + i)); + } + + /* RAM2 (SRAM) */ + memory_region_init_ram(&s->sram, OBJECT(dev), "ram2", + NPCM8XX_RAM2_SZ, &error_abort); + memory_region_add_subregion(get_system_memory(), NPCM8XX_RAM2_BA, &s->= sram); + + /* RAM3 (SRAM) */ + memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3", + NPCM8XX_RAM3_SZ, &error_abort); + memory_region_add_subregion(get_system_memory(), NPCM8XX_RAM3_BA, &s->= ram3); + + /* Internal ROM */ + memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM8XX_ROM_SZ, + &error_abort); + memory_region_add_subregion(get_system_memory(), NPCM8XX_ROM_BA, &s->i= rom); + + /* SDHCI */ + sysbus_realize(SYS_BUS_DEVICE(&s->mmc), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc), 0, NPCM8XX_MMC_BA); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc), 0, + npcm8xx_irq(s, NPCM8XX_MMC_IRQ)); + + /* PECI */ + sysbus_realize(SYS_BUS_DEVICE(&s->peci), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->peci), 0, NPCM8XX_PECI_BA); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, + npcm8xx_irq(s, NPCM8XX_PECI_IRQ)); + /* PCIe RC */ + sysbus_realize(SYS_BUS_DEVICE(&s->pcierc), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcierc), 0, NPCM8XX_PCIERC_BA); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcierc), 0, + npcm8xx_irq(s, NPCM8XX_PCIE_RC_IRQ)); + + create_unimplemented_device("npcm8xx.shm", 0xc0001000, 4 * = KiB); + create_unimplemented_device("npcm8xx.gicextra", 0xdfffa000, 24 * = KiB); + create_unimplemented_device("npcm8xx.vdmx", 0xe0800000, 4 * = KiB); + create_unimplemented_device("npcm8xx.gfxi", 0xf000e000, 4 * = KiB); + create_unimplemented_device("npcm8xx.fsw", 0xf000f000, 4 * = KiB); + create_unimplemented_device("npcm8xx.bt", 0xf0030000, 4 * = KiB); + create_unimplemented_device("npcm8xx.espi", 0xf009f000, 4 * = KiB); + create_unimplemented_device("npcm8xx.peci", 0xf0100000, 4 * = KiB); + create_unimplemented_device("npcm8xx.siox[1]", 0xf0101000, 4 * = KiB); + create_unimplemented_device("npcm8xx.siox[2]", 0xf0102000, 4 * = KiB); + create_unimplemented_device("npcm8xx.tmps", 0xf0188000, 4 * = KiB); + create_unimplemented_device("npcm8xx.pspi", 0xf0201000, 4 * = KiB); + create_unimplemented_device("npcm8xx.viru1", 0xf0204000, 4 * = KiB); + create_unimplemented_device("npcm8xx.viru2", 0xf0205000, 4 * = KiB); + create_unimplemented_device("npcm8xx.jtm1", 0xf0208000, 4 * = KiB); + create_unimplemented_device("npcm8xx.jtm2", 0xf0209000, 4 * = KiB); + create_unimplemented_device("npcm8xx.flm0", 0xf0210000, 4 * = KiB); + create_unimplemented_device("npcm8xx.flm1", 0xf0211000, 4 * = KiB); + create_unimplemented_device("npcm8xx.flm2", 0xf0212000, 4 * = KiB); + create_unimplemented_device("npcm8xx.flm3", 0xf0213000, 4 * = KiB); + create_unimplemented_device("npcm8xx.ahbpci", 0xf0400000, 1 * = MiB); + create_unimplemented_device("npcm8xx.dap", 0xf0500000, 960 * = KiB); + create_unimplemented_device("npcm8xx.mcphy", 0xf05f0000, 64 * = KiB); + create_unimplemented_device("npcm8xx.tsgen", 0xf07fc000, 8 * = KiB); + create_unimplemented_device("npcm8xx.copctl", 0xf080c000, 4 * = KiB); + create_unimplemented_device("npcm8xx.tipctl", 0xf080d000, 4 * = KiB); + create_unimplemented_device("npcm8xx.rst", 0xf080e000, 4 * = KiB); + create_unimplemented_device("npcm8xx.vcd", 0xf0810000, 64 * = KiB); + create_unimplemented_device("npcm8xx.ece", 0xf0820000, 8 * = KiB); + create_unimplemented_device("npcm8xx.vdma", 0xf0822000, 8 * = KiB); + create_unimplemented_device("npcm8xx.usbd[0]", 0xf0830000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[1]", 0xf0831000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[2]", 0xf0832000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[3]", 0xf0833000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[4]", 0xf0834000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[5]", 0xf0835000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[6]", 0xf0836000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[7]", 0xf0837000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[8]", 0xf0838000, 4 * = KiB); + create_unimplemented_device("npcm8xx.usbd[9]", 0xf0839000, 4 * = KiB); + create_unimplemented_device("npcm8xx.gdma0", 0xf0850000, 4 * = KiB); + create_unimplemented_device("npcm8xx.gdma1", 0xf0851000, 4 * = KiB); + create_unimplemented_device("npcm8xx.gdma2", 0xf0852000, 4 * = KiB); + create_unimplemented_device("npcm8xx.aes", 0xf0858000, 4 * = KiB); + create_unimplemented_device("npcm8xx.des", 0xf0859000, 4 * = KiB); + create_unimplemented_device("npcm8xx.sha", 0xf085a000, 4 * = KiB); + create_unimplemented_device("npcm8xx.i3c0", 0xfff10000, 4 * = KiB); + create_unimplemented_device("npcm8xx.i3c1", 0xfff11000, 4 * = KiB); + create_unimplemented_device("npcm8xx.i3c2", 0xfff12000, 4 * = KiB); + create_unimplemented_device("npcm8xx.i3c3", 0xfff13000, 4 * = KiB); + create_unimplemented_device("npcm8xx.i3c4", 0xfff14000, 4 * = KiB); + create_unimplemented_device("npcm8xx.i3c5", 0xfff15000, 4 * = KiB); + create_unimplemented_device("npcm8xx.spixcs0", 0xf8000000, 16 * = MiB); + create_unimplemented_device("npcm8xx.spixcs1", 0xf9000000, 16 * = MiB); + create_unimplemented_device("npcm8xx.spix", 0xfb001000, 4 * = KiB); + create_unimplemented_device("npcm8xx.vect", 0xffff0000, 256); +} + +static Property npcm8xx_properties[] =3D { + DEFINE_PROP_LINK("dram-mr", NPCM8xxState, dram, TYPE_MEMORY_REGION, + MemoryRegion *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void npcm8xx_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + NPCM8xxClass *nc =3D NPCM8XX_CLASS(oc); + + dc->realize =3D npcm8xx_realize; + dc->user_creatable =3D false; + nc->disabled_modules =3D 0x00000000; + nc->num_cpus =3D NPCM8XX_MAX_NUM_CPUS; + device_class_set_props(dc, npcm8xx_properties); +} + +static const TypeInfo npcm8xx_soc_types[] =3D { + { + .name =3D TYPE_NPCM8XX, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(NPCM8xxState), + .instance_init =3D npcm8xx_init, + .class_size =3D sizeof(NPCM8xxClass), + .class_init =3D npcm8xx_class_init, + }, +}; + +DEFINE_TYPES(npcm8xx_soc_types); diff --git a/hw/net/meson.build b/hw/net/meson.build index 2632634df3..a60f05b6c4 100644 --- a/hw/net/meson.build +++ b/hw/net/meson.build @@ -38,7 +38,8 @@ system_ss.add(when: 'CONFIG_I82596_COMMON', if_true: file= s('i82596.c')) system_ss.add(when: 'CONFIG_SUNHME', if_true: files('sunhme.c')) system_ss.add(when: 'CONFIG_FTGMAC100', if_true: files('ftgmac100.c')) system_ss.add(when: 'CONFIG_SUNGEM', if_true: files('sungem.c')) -system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_emc.c')) +system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_emc.c', 'npc= m_gmac.c')) +system_ss.add(when: 'CONFIG_NPCM8XX', if_true: files('npcm_pcs.c')) =20 system_ss.add(when: 'CONFIG_ETRAXFS', if_true: files('etraxfs_eth.c')) system_ss.add(when: 'CONFIG_COLDFIRE', if_true: files('mcf_fec.c')) diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm_gmac.c new file mode 100644 index 0000000000..5ce632858d --- /dev/null +++ b/hw/net/npcm_gmac.c @@ -0,0 +1,395 @@ +/* + * Nuvoton NPCM7xx/8xx GMAC Module + * + * Copyright 2022 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * Unsupported/unimplemented features: + * - MII is not implemented, MII_ADDR.BUSY and MII_DATA always return zero + * - Precision timestamp (PTP) is not implemented. + */ + +#include "qemu/osdep.h" + +#include "hw/registerfields.h" +#include "hw/net/mii.h" +#include "hw/net/npcm_gmac.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/units.h" +#include "sysemu/dma.h" +#include "trace.h" + +REG32(NPCM_DMA_BUS_MODE, 0x1000) +REG32(NPCM_DMA_XMT_POLL_DEMAND, 0x1004) +REG32(NPCM_DMA_RCV_POLL_DEMAND, 0x1008) +REG32(NPCM_DMA_RCV_BASE_ADDR, 0x100c) +REG32(NPCM_DMA_TX_BASE_ADDR, 0x1010) +REG32(NPCM_DMA_STATUS, 0x1014) +REG32(NPCM_DMA_CONTROL, 0x1018) +REG32(NPCM_DMA_INTR_ENA, 0x101c) +REG32(NPCM_DMA_MISSED_FRAME_CTR, 0x1020) +REG32(NPCM_DMA_HOST_TX_DESC, 0x1048) +REG32(NPCM_DMA_HOST_RX_DESC, 0x104c) +REG32(NPCM_DMA_CUR_TX_BUF_ADDR, 0x1050) +REG32(NPCM_DMA_CUR_RX_BUF_ADDR, 0x1054) +REG32(NPCM_DMA_HW_FEATURE, 0x1058) + +REG32(NPCM_GMAC_MAC_CONFIG, 0x0) +REG32(NPCM_GMAC_FRAME_FILTER, 0x4) +REG32(NPCM_GMAC_HASH_HIGH, 0x8) +REG32(NPCM_GMAC_HASH_LOW, 0xc) +REG32(NPCM_GMAC_MII_ADDR, 0x10) +REG32(NPCM_GMAC_MII_DATA, 0x14) +REG32(NPCM_GMAC_FLOW_CTRL, 0x18) +REG32(NPCM_GMAC_VLAN_FLAG, 0x1c) +REG32(NPCM_GMAC_VERSION, 0x20) +REG32(NPCM_GMAC_WAKEUP_FILTER, 0x28) +REG32(NPCM_GMAC_PMT, 0x2c) +REG32(NPCM_GMAC_LPI_CTRL, 0x30) +REG32(NPCM_GMAC_TIMER_CTRL, 0x34) +REG32(NPCM_GMAC_INT_STATUS, 0x38) +REG32(NPCM_GMAC_INT_MASK, 0x3c) +REG32(NPCM_GMAC_MAC0_ADDR_HI, 0x40) +REG32(NPCM_GMAC_MAC0_ADDR_LO, 0x44) +REG32(NPCM_GMAC_MAC1_ADDR_HI, 0x48) +REG32(NPCM_GMAC_MAC1_ADDR_LO, 0x4c) +REG32(NPCM_GMAC_MAC2_ADDR_HI, 0x50) +REG32(NPCM_GMAC_MAC2_ADDR_LO, 0x54) +REG32(NPCM_GMAC_MAC3_ADDR_HI, 0x58) +REG32(NPCM_GMAC_MAC3_ADDR_LO, 0x5c) +REG32(NPCM_GMAC_RGMII_STATUS, 0xd8) +REG32(NPCM_GMAC_WATCHDOG, 0xdc) +REG32(NPCM_GMAC_PTP_TCR, 0x700) +REG32(NPCM_GMAC_PTP_SSIR, 0x704) +REG32(NPCM_GMAC_PTP_STSR, 0x708) +REG32(NPCM_GMAC_PTP_STNSR, 0x70c) +REG32(NPCM_GMAC_PTP_STSUR, 0x710) +REG32(NPCM_GMAC_PTP_STNSUR, 0x714) +REG32(NPCM_GMAC_PTP_TAR, 0x718) +REG32(NPCM_GMAC_PTP_TTSR, 0x71c) + +/* Register Fields */ +#define NPCM_GMAC_MII_ADDR_BUSY BIT(0) +#define NPCM_GMAC_MII_ADDR_WRITE BIT(1) +#define NPCM_GMAC_MII_ADDR_GR(rv) extract16((rv), 6, 5) +#define NPCM_GMAC_MII_ADDR_PA(rv) extract16((rv), 11, 5) + +#define NPCM_GMAC_INT_MASK_LPIIM BIT(10) +#define NPCM_GMAC_INT_MASK_PMTM BIT(3) +#define NPCM_GMAC_INT_MASK_RGIM BIT(0) + +#define NPCM_DMA_BUS_MODE_SWR BIT(0) + +static const uint32_t npcm_gmac_cold_reset_values[NPCM_GMAC_NR_REGS] =3D { + [R_NPCM_GMAC_VERSION] =3D 0x00001037, + [R_NPCM_GMAC_TIMER_CTRL] =3D 0x03e80000, + [R_NPCM_GMAC_MAC0_ADDR_HI] =3D 0x8000ffff, + [R_NPCM_GMAC_MAC0_ADDR_LO] =3D 0xffffffff, + [R_NPCM_GMAC_MAC1_ADDR_HI] =3D 0x0000ffff, + [R_NPCM_GMAC_MAC1_ADDR_LO] =3D 0xffffffff, + [R_NPCM_GMAC_MAC2_ADDR_HI] =3D 0x0000ffff, + [R_NPCM_GMAC_MAC2_ADDR_LO] =3D 0xffffffff, + [R_NPCM_GMAC_MAC3_ADDR_HI] =3D 0x0000ffff, + [R_NPCM_GMAC_MAC3_ADDR_LO] =3D 0xffffffff, + [R_NPCM_GMAC_PTP_TCR] =3D 0x00002000, + [R_NPCM_DMA_BUS_MODE] =3D 0x00020101, + [R_NPCM_DMA_HW_FEATURE] =3D 0x100d4f37, +}; + +static const uint16_t phy_reg_init[] =3D { + [MII_BMCR] =3D MII_BMCR_AUTOEN | MII_BMCR_FD | MII_BMCR_SPEED1000, + [MII_BMSR] =3D MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_1= 0T_FD | + MII_BMSR_10T_HD | MII_BMSR_EXTSTAT | MII_BMSR_AUTONE= G | + MII_BMSR_LINK_ST | MII_BMSR_EXTCAP, + [MII_PHYID1] =3D 0x0362, + [MII_PHYID2] =3D 0x5e6a, + [MII_ANAR] =3D MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD | + MII_ANAR_10 | MII_ANAR_CSMACD, + [MII_ANLPAR] =3D MII_ANLPAR_ACK | MII_ANLPAR_PAUSE | + MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD | + MII_ANLPAR_10 | MII_ANLPAR_CSMACD, + [MII_ANER] =3D 0x64 | MII_ANER_NWAY, + [MII_ANNP] =3D 0x2001, + [MII_CTRL1000] =3D MII_CTRL1000_FULL, + [MII_STAT1000] =3D MII_STAT1000_FULL, + [MII_EXTSTAT] =3D 0x3000, /* 1000BASTE_T full-duplex capable */ +}; + +static void npcm_gmac_soft_reset(NPCMGMACState *s) +{ + memcpy(s->regs, npcm_gmac_cold_reset_values, + NPCM_GMAC_NR_REGS * sizeof(uint32_t)); + /* Clear reset bits */ + s->regs[R_NPCM_DMA_BUS_MODE] &=3D ~NPCM_DMA_BUS_MODE_SWR; +} + +static void gmac_phy_set_link(NPCMGMACState *s, bool active) +{ + /* Autonegotiation status mirrors link status. */ + if (active) { + s->phy_regs[0][MII_BMSR] |=3D (MII_BMSR_LINK_ST | MII_BMSR_AN_COMP= ); + } else { + s->phy_regs[0][MII_BMSR] &=3D ~(MII_BMSR_LINK_ST | MII_BMSR_AN_COM= P); + } +} + +static bool gmac_can_receive(NetClientState *nc) +{ + return true; +} + +static ssize_t gmac_receive(NetClientState *nc, const uint8_t *buf, size_t= len1) +{ + return 0; +} + +static void gmac_cleanup(NetClientState *nc) +{ + /* Nothing to do yet. */ +} + +static void gmac_set_link(NetClientState *nc) +{ + NPCMGMACState *s =3D qemu_get_nic_opaque(nc); + + trace_npcm_gmac_set_link(!nc->link_down); + gmac_phy_set_link(s, !nc->link_down); +} + +static void npcm_gmac_mdio_access(NPCMGMACState *s, uint16_t v) +{ + bool busy =3D v & NPCM_GMAC_MII_ADDR_BUSY; + uint8_t is_write; + uint8_t pa, gr; + uint16_t data; + + if (busy) { + is_write =3D v & NPCM_GMAC_MII_ADDR_WRITE; + pa =3D NPCM_GMAC_MII_ADDR_PA(v); + gr =3D NPCM_GMAC_MII_ADDR_GR(v); + /* Both pa and gr are 5 bits, so they are less than 32. */ + g_assert(pa < NPCM_GMAC_MAX_PHYS); + g_assert(gr < NPCM_GMAC_MAX_PHY_REGS); + + + if (v & NPCM_GMAC_MII_ADDR_WRITE) { + data =3D s->regs[R_NPCM_GMAC_MII_DATA]; + /* Clear reset bit for BMCR register */ + switch (gr) { + case MII_BMCR: + data &=3D ~MII_BMCR_RESET; + /* Complete auto-negotiation immediately and set as comple= te */ + if (data & MII_BMCR_AUTOEN) { + /* Tells autonegotiation to not restart again */ + data &=3D ~MII_BMCR_ANRESTART; + /* sets autonegotiation as complete */ + s->phy_regs[pa][MII_BMSR] |=3D MII_BMSR_AN_COMP; + } + } + s->phy_regs[pa][gr] =3D data; + } else { + data =3D s->phy_regs[pa][gr]; + s->regs[R_NPCM_GMAC_MII_DATA] =3D data; + } + trace_npcm_gmac_mdio_access(DEVICE(s)->canonical_path, is_write, p= a, + gr, data); + } + s->regs[R_NPCM_GMAC_MII_ADDR] =3D v & ~NPCM_GMAC_MII_ADDR_BUSY; +} + +static uint64_t npcm_gmac_read(void *opaque, hwaddr offset, unsigned size) +{ + NPCMGMACState *s =3D opaque; + uint32_t v =3D 0; + + switch (offset) { + /* Write only registers */ + case A_NPCM_DMA_XMT_POLL_DEMAND: + case A_NPCM_DMA_RCV_POLL_DEMAND: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Read of write-only reg: offset: 0x%04" HWADDR_P= RIx + "\n", DEVICE(s)->canonical_path, offset); + break; + + default: + v =3D s->regs[offset / sizeof(uint32_t)]; + } + trace_npcm_gmac_reg_read(DEVICE(s)->canonical_path, offset, v); + return v; +} + +static void npcm_gmac_write(void *opaque, hwaddr offset, + uint64_t v, unsigned size) +{ + NPCMGMACState *s =3D opaque; + + trace_npcm_gmac_reg_write(DEVICE(s)->canonical_path, offset, v); + switch (offset) { + /* Read only registers */ + case A_NPCM_GMAC_VERSION: + case A_NPCM_GMAC_INT_STATUS: + case A_NPCM_GMAC_RGMII_STATUS: + case A_NPCM_GMAC_PTP_STSR: + case A_NPCM_GMAC_PTP_STNSR: + case A_NPCM_DMA_MISSED_FRAME_CTR: + case A_NPCM_DMA_HOST_TX_DESC: + case A_NPCM_DMA_HOST_RX_DESC: + case A_NPCM_DMA_CUR_TX_BUF_ADDR: + case A_NPCM_DMA_CUR_RX_BUF_ADDR: + case A_NPCM_DMA_HW_FEATURE: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Write of read-only reg: offset: 0x%04" HWADDR_P= RIx + ", value: 0x%04" PRIx64 "\n", + DEVICE(s)->canonical_path, offset, v); + break; + + case A_NPCM_GMAC_MII_ADDR: + npcm_gmac_mdio_access(s, v); + break; + + case A_NPCM_GMAC_MAC0_ADDR_HI: + s->regs[offset / sizeof(uint32_t)] =3D v; + s->conf.macaddr.a[0] =3D v >> 8; + s->conf.macaddr.a[1] =3D v >> 0; + break; + + case A_NPCM_GMAC_MAC0_ADDR_LO: + s->regs[offset / sizeof(uint32_t)] =3D v; + s->conf.macaddr.a[2] =3D v >> 24; + s->conf.macaddr.a[3] =3D v >> 16; + s->conf.macaddr.a[4] =3D v >> 8; + s->conf.macaddr.a[5] =3D v >> 0; + break; + + case A_NPCM_GMAC_MAC1_ADDR_HI: + case A_NPCM_GMAC_MAC1_ADDR_LO: + case A_NPCM_GMAC_MAC2_ADDR_HI: + case A_NPCM_GMAC_MAC2_ADDR_LO: + case A_NPCM_GMAC_MAC3_ADDR_HI: + case A_NPCM_GMAC_MAC3_ADDR_LO: + s->regs[offset / sizeof(uint32_t)] =3D v; + qemu_log_mask(LOG_UNIMP, + "%s: Only MAC Address 0 is supported. This request " + "is ignored.\n", DEVICE(s)->canonical_path); + break; + + case A_NPCM_DMA_BUS_MODE: + s->regs[offset / sizeof(uint32_t)] =3D v; + if (v & NPCM_DMA_BUS_MODE_SWR) { + npcm_gmac_soft_reset(s); + } + break; + + default: + s->regs[offset / sizeof(uint32_t)] =3D v; + break; + } +} + +static void npcm_gmac_reset(DeviceState *dev) +{ + NPCMGMACState *s =3D NPCM_GMAC(dev); + + npcm_gmac_soft_reset(s); + memcpy(s->phy_regs[0], phy_reg_init, sizeof(phy_reg_init)); + + trace_npcm_gmac_reset(DEVICE(s)->canonical_path, s->phy_regs[0][MII_BM= SR]); +} + +static NetClientInfo net_npcm_gmac_info =3D { + .type =3D NET_CLIENT_DRIVER_NIC, + .size =3D sizeof(NICState), + .can_receive =3D gmac_can_receive, + .receive =3D gmac_receive, + .cleanup =3D gmac_cleanup, + .link_status_changed =3D gmac_set_link, +}; + +static const struct MemoryRegionOps npcm_gmac_ops =3D { + .read =3D npcm_gmac_read, + .write =3D npcm_gmac_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void npcm_gmac_realize(DeviceState *dev, Error **errp) +{ + NPCMGMACState *gmac =3D NPCM_GMAC(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + memory_region_init_io(&gmac->iomem, OBJECT(gmac), &npcm_gmac_ops, gmac, + TYPE_NPCM_GMAC, 8 * KiB); + sysbus_init_mmio(sbd, &gmac->iomem); + sysbus_init_irq(sbd, &gmac->irq); + + qemu_macaddr_default_if_unset(&gmac->conf.macaddr); + + gmac->nic =3D qemu_new_nic(&net_npcm_gmac_info, &gmac->conf, TYPE_NPCM= _GMAC, + dev->id, gmac); + qemu_format_nic_info_str(qemu_get_queue(gmac->nic), gmac->conf.macaddr= .a); + gmac->regs[R_NPCM_GMAC_MAC0_ADDR_HI] =3D (gmac->conf.macaddr.a[0] << 8= ) + \ + gmac->conf.macaddr.a[1]; + gmac->regs[R_NPCM_GMAC_MAC0_ADDR_LO] =3D (gmac->conf.macaddr.a[2] << 2= 4) + \ + (gmac->conf.macaddr.a[3] << 16)= + \ + (gmac->conf.macaddr.a[4] << 8) = + \ + gmac->conf.macaddr.a[5]; +} + +static void npcm_gmac_unrealize(DeviceState *dev) +{ + NPCMGMACState *gmac =3D NPCM_GMAC(dev); + + qemu_del_nic(gmac->nic); +} + +static const VMStateDescription vmstate_npcm_gmac =3D { + .name =3D TYPE_NPCM_GMAC, + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, NPCMGMACState, NPCM_GMAC_NR_REGS), + VMSTATE_END_OF_LIST(), + }, +}; + +static Property npcm_gmac_properties[] =3D { + DEFINE_NIC_PROPERTIES(NPCMGMACState, conf), + DEFINE_PROP_END_OF_LIST(), +}; + +static void npcm_gmac_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); + dc->desc =3D "NPCM GMAC Controller"; + dc->realize =3D npcm_gmac_realize; + dc->unrealize =3D npcm_gmac_unrealize; + dc->reset =3D npcm_gmac_reset; + dc->vmsd =3D &vmstate_npcm_gmac; + device_class_set_props(dc, npcm_gmac_properties); +} + +static const TypeInfo npcm_gmac_types[] =3D { + { + .name =3D TYPE_NPCM_GMAC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NPCMGMACState), + .class_init =3D npcm_gmac_class_init, + }, +}; +DEFINE_TYPES(npcm_gmac_types) diff --git a/hw/net/trace-events b/hw/net/trace-events index 6b5ba669a2..27b006f40a 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -464,6 +464,17 @@ npcm7xx_emc_rx_done(uint32_t crxdsa) "RX done, CRXDSA= =3D0x%x" npcm7xx_emc_reg_read(int emc_num, uint32_t result, const char *name, int r= egno) "emc%d: 0x%x =3D reg[%s/%d]" npcm7xx_emc_reg_write(int emc_num, const char *name, int regno, uint32_t v= alue) "emc%d: reg[%s/%d] =3D 0x%x" =20 +# npcm_gmac.c +npcm_gmac_reg_read(const char *name, uint64_t offset, uint32_t value) "%s:= offset: 0x%04" PRIx64 " value: 0x%04" PRIx32 +npcm_gmac_reg_write(const char *name, uint64_t offset, uint32_t value) "%s= : offset: 0x%04" PRIx64 " value: 0x%04" PRIx32 +npcm_gmac_mdio_access(const char *name, uint8_t is_write, uint8_t pa, uint= 8_t gr, uint16_t val) "%s: is_write: %" PRIu8 " pa: %" PRIu8 " gr: %" PRIu8= " val: 0x%04" PRIx16 +npcm_gmac_reset(const char *name, uint16_t value) "%s: phy_regs[0][1]: 0x%= 04" PRIx16 +npcm_gmac_set_link(bool active) "Set link: active=3D%u" + +# npcm_pcs.c +npcm_pcs_reg_read(const char *name, uint16_t indirect_access_baes, uint64_= t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 "= value: 0x%04" PRIx16 +npcm_pcs_reg_write(const char *name, uint16_t indirect_access_baes, uint64= _t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 = " value: 0x%04" PRIx16 + # dp8398x.c dp8393x_raise_irq(int isr) "raise irq, isr is 0x%04x" dp8393x_lower_irq(void) "lower irq" diff --git a/include/hw/net/npcm_gmac.h b/include/hw/net/npcm_gmac.h new file mode 100644 index 0000000000..03529db1d6 --- /dev/null +++ b/include/hw/net/npcm_gmac.h @@ -0,0 +1,172 @@ +/* + * Nuvoton NPCM7xx/8xx GMAC Module + * + * Copyright 2022 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#ifndef NPCM_GMAC_H +#define NPCM_GMAC_H + +#include "hw/irq.h" +#include "hw/sysbus.h" +#include "hw/net/npcm_pcs.h" +#include "net/net.h" + +#define NPCM_GMAC_NR_REGS (0x1060 / sizeof(uint32_t)) + +#define NPCM_GMAC_MAX_PHYS 32 +#define NPCM_GMAC_MAX_PHY_REGS 32 + +struct NPCMGMACRxDesc { + uint32_t rdes0; + uint32_t rdes1; + uint32_t rdes2; + uint32_t rdes3; +}; + +/* NPCMGMACRxDesc.flags values */ +/* RDES2 and RDES3 are buffer address pointers */ +/* Owner: 0 =3D software, 1 =3D gmac */ +#define RX_DESC_RDES0_OWNER_MASK BIT(31) +/* Owner*/ +#define RX_DESC_RDES0_OWNER_SHIFT 31 +/* Destination Address Filter Fail */ +#define RX_DESC_RDES0_DEST_ADDR_FILT_FAIL_MASK BIT(30) +/* Frame length*/ +#define RX_DESC_RDES0_FRAME_LEN_MASK(word) extract32(word, 16, 29) +/* Error Summary */ +#define RX_DESC_RDES0_ERR_SUMM_MASK BIT(15) +/* Descriptor Error */ +#define RX_DESC_RDES0_DESC_ERR_MASK BIT(14) +/* Source Address Filter Fail */ +#define RX_DESC_RDES0_SRC_ADDR_FILT_FAIL_MASK BIT(13) +/* Length Error */ +#define RX_DESC_RDES0_LEN_ERR_MASK BIT(12) +/* Overflow Error */ +#define RX_DESC_RDES0_OVRFLW_ERR_MASK BIT(11) +/* VLAN Tag */ +#define RX_DESC_RDES0_VLAN_TAG_MASK BIT(10) +/* First Descriptor */ +#define RX_DESC_RDES0_FIRST_DESC_MASK BIT(9) +/* Last Descriptor */ +#define RX_DESC_RDES0_LAST_DESC_MASK BIT(8) +/* IPC Checksum Error/Giant Frame */ +#define RX_DESC_RDES0_IPC_CHKSM_ERR_GNT_FRM_MASK BIT(7) +/* Late Collision */ +#define RX_DESC_RDES0_LT_COLL_MASK BIT(6) +/* Frame Type */ +#define RX_DESC_RDES0_FRM_TYPE_MASK BIT(5) +/* Receive Watchdog Timeout */ +#define RX_DESC_RDES0_REC_WTCHDG_TMT_MASK BIT(4) +/* Receive Error */ +#define RX_DESC_RDES0_RCV_ERR_MASK BIT(3) +/* Dribble Bit Error */ +#define RX_DESC_RDES0_DRBL_BIT_ERR_MASK BIT(2) +/* Cyclcic Redundancy Check Error */ +#define RX_DESC_RDES0_CRC_ERR_MASK BIT(1) +/* Rx MAC Address/Payload Checksum Error */ +#define RC_DESC_RDES0_RCE_MASK BIT(0) + +/* Disable Interrupt on Completion */ +#define RX_DESC_RDES1_DIS_INTR_COMP_MASK BIT(31) +/* Recieve end of ring */ +#define RX_DESC_RDES1_RC_END_RING_MASK BIT(25) +/* Second Address Chained */ +#define RX_DESC_RDES1_SEC_ADDR_CHND_MASK BIT(24) +/* Receive Buffer 2 Size */ +#define RX_DESC_RDES1_BFFR2_SZ_SHIFT 11 +#define RX_DESC_RDES1_BFFR2_SZ_MASK(word) extract32(word, \ + RX_DESC_RDES1_BFFR2_SZ_SHIFT, 10 + RX_DESC_RDES1_BFFR2_SZ_SHIFT) +/* Receive Buffer 1 Size */ +#define RX_DESC_RDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 10) + + +struct NPCMGMACTxDesc { + uint32_t tdes0; + uint32_t tdes1; + uint32_t tdes2; + uint32_t tdes3; +}; + +/* NPCMGMACTxDesc.flags values */ +/* TDES2 and TDES3 are buffer address pointers */ +/* Owner: 0 =3D software, 1 =3D gmac */ +#define TX_DESC_TDES0_OWNER_MASK BIT(31) +/* Tx Time Stamp Status */ +#define TX_DESC_TDES0_TTSS_MASK BIT(17) +/* IP Header Error */ +#define TX_DESC_TDES0_IP_HEAD_ERR_MASK BIT(16) +/* Error Summary */ +#define TX_DESC_TDES0_ERR_SUMM_MASK BIT(15) +/* Jabber Timeout */ +#define TX_DESC_TDES0_JBBR_TMT_MASK BIT(14) +/* Frame Flushed */ +#define TX_DESC_TDES0_FRM_FLSHD_MASK BIT(13) +/* Payload Checksum Error */ +#define TX_DESC_TDES0_PYLD_CHKSM_ERR_MASK BIT(12) +/* Loss of Carrier */ +#define TX_DESC_TDES0_LSS_CARR_MASK BIT(11) +/* No Carrier */ +#define TX_DESC_TDES0_NO_CARR_MASK BIT(10) +/* Late Collision */ +#define TX_DESC_TDES0_LATE_COLL_MASK BIT(9) +/* Excessive Collision */ +#define TX_DESC_TDES0_EXCS_COLL_MASK BIT(8) +/* VLAN Frame */ +#define TX_DESC_TDES0_VLAN_FRM_MASK BIT(7) +/* Collision Count */ +#define TX_DESC_TDES0_COLL_CNT_MASK(word) extract32(word, 3, 6) +/* Excessive Deferral */ +#define TX_DESC_TDES0_EXCS_DEF_MASK BIT(2) +/* Underflow Error */ +#define TX_DESC_TDES0_UNDRFLW_ERR_MASK BIT(1) +/* Deferred Bit */ +#define TX_DESC_TDES0_DFRD_BIT_MASK BIT(0) + +/* Interrupt of Completion */ +#define TX_DESC_TDES1_INTERR_COMP_MASK BIT(31) +/* Last Segment */ +#define TX_DESC_TDES1_LAST_SEG_MASK BIT(30) +/* Last Segment */ +#define TX_DESC_TDES1_FIRST_SEG_MASK BIT(29) +/* Checksum Insertion Control */ +#define TX_DESC_TDES1_CHKSM_INS_CTRL_MASK(word) extract32(word, 27, 28) +/* Disable Cyclic Redundancy Check */ +#define TX_DESC_TDES1_DIS_CDC_MASK BIT(26) +/* Transmit End of Ring */ +#define TX_DESC_TDES1_TX_END_RING_MASK BIT(25) +/* Secondary Address Chained */ +#define TX_DESC_TDES1_SEC_ADDR_CHND_MASK BIT(24) +/* Transmit Buffer 2 Size */ +#define TX_DESC_TDES1_BFFR2_SZ_MASK(word) extract32(word, 11, 21) +/* Transmit Buffer 1 Size */ +#define TX_DESC_TDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 10) + +typedef struct NPCMGMACState { + SysBusDevice parent; + + MemoryRegion iomem; + qemu_irq irq; + + NICState *nic; + NICConf conf; + + NPCMPCSState *pcs; + uint32_t regs[NPCM_GMAC_NR_REGS]; + uint16_t phy_regs[NPCM_GMAC_MAX_PHYS][NPCM_GMAC_MAX_PHY_REGS]; +} NPCMGMACState; + +#define TYPE_NPCM_GMAC "npcm-gmac" +OBJECT_DECLARE_SIMPLE_TYPE(NPCMGMACState, NPCM_GMAC) + +#endif /* NPCM_GMAC_H */ --=20 2.42.0.459.ge4e396fd5e-goog From nobody Sat May 18 22:31:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1695154018; cv=none; d=zohomail.com; s=zohoarc; b=nMHVnyjSPnUXsLuI8FhW9tT9Q9oOGkTzcLN8FdxyK+cQ8kH5LKU8ukagDbf/cqwMnjgvf38JegHdOAJcC8otcsv+kdiyuG9qe3ttoJ+Bh0NUZCp50b55ZoRWiAdX3TjnQhYxZYPQoJM8vHwd/l2rzSmXwK9YSKpAzaSiLrOxhEA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Tue, 19 Sep 2023 10:57:50 -0700 (PDT) Date: Tue, 19 Sep 2023 17:57:17 +0000 In-Reply-To: <20230919175725.3413108-1-nabihestefan@google.com> Mime-Version: 1.0 References: <20230919175725.3413108-1-nabihestefan@google.com> X-Mailer: git-send-email 2.42.0.459.ge4e396fd5e-goog Message-ID: <20230919175725.3413108-7-nabihestefan@google.com> Subject: [PATCH 06/14] hw/arm: Add GMAC devices to NPCM8XX SoC From: Nabih Estefan To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kfting@nuvoton.com, wuhaotsh@google.com, jasonwang@redhat.com, Avi.Fishman@nuvoton.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::114a; envelope-from=3HuEJZQwKCjcgTUbaXlmXYTgZhhZeX.VhfjXfn-WXoXeghgZgn.hkZ@flex--nabihestefan.bounces.google.com; helo=mail-yw1-x114a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 19 Sep 2023 16:04:51 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1695154019443100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hao Wu Signed-off-by: Hao Wu --- hw/arm/npcm8xx.c | 12 ---- include/hw/arm/npcm8xx.h | 118 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 118 insertions(+), 12 deletions(-) create mode 100644 include/hw/arm/npcm8xx.h diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c index a05dcfed5c..a9eb2b894c 100644 --- a/hw/arm/npcm8xx.c +++ b/hw/arm/npcm8xx.c @@ -440,9 +440,6 @@ static void npcm8xx_init(Object *obj) object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_= GPIO); } =20 - object_initialize_child(obj, "gpiotx", &s->gpiotx, - TYPE_GOOGLE_GPIO_TRANSMITTER); - for (i =3D 0; i < ARRAY_SIZE(s->smbus); i++) { object_initialize_child(obj, "smbus[*]", &s->smbus[i], TYPE_NPCM8XX_SMBUS); @@ -633,12 +630,9 @@ static void npcm8xx_realize(DeviceState *dev, Error **= errp) =20 /* GPIO modules. Cannot fail. */ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_gpio) !=3D ARRAY_SIZE(s->gpio)); - sysbus_realize(SYS_BUS_DEVICE(&s->gpiotx), &error_abort); for (i =3D 0; i < ARRAY_SIZE(s->gpio); i++) { Object *obj =3D OBJECT(&s->gpio[i]); =20 - object_property_set_link(obj, "gpio-tx", OBJECT(&s->gpiotx), - &error_abort); object_property_set_uint(obj, "reset-pullup", npcm8xx_gpio[i].reset_pu, &error_abort); object_property_set_uint(obj, "reset-pulldown", @@ -725,12 +719,6 @@ static void npcm8xx_realize(DeviceState *dev, Error **= errp) for (i =3D 0; i < ARRAY_SIZE(s->gmac); i++) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->gmac[i]); =20 - /* This is used to make sure that the NIC can create the device */ - if (nd_table[i].used) { - qemu_check_nic_model(&nd_table[i], TYPE_NPCM_GMAC); - qdev_set_nic_properties(DEVICE(sbd), &nd_table[i]); - } - /* * The device exists regardless of whether it's connected to a QEMU * netdev backend. So always instantiate it even if there is no diff --git a/include/hw/arm/npcm8xx.h b/include/hw/arm/npcm8xx.h new file mode 100644 index 0000000000..0c0488b641 --- /dev/null +++ b/include/hw/arm/npcm8xx.h @@ -0,0 +1,118 @@ +/* + * Nuvoton NPCM8xx SoC family. + * + * Copyright 2022 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ +#ifndef NPCM8XX_H +#define NPCM8XX_H + +#include "hw/boards.h" +#include "hw/adc/npcm7xx_adc.h" +#include "hw/core/split-irq.h" +#include "hw/cpu/cluster.h" +#include "hw/gpio/npcm7xx_gpio.h" +#include "hw/i2c/npcm_smbus.h" +#include "hw/ipmi/npcm7xx_kcs.h" +#include "hw/intc/arm_gic_common.h" +#include "hw/mem/npcm7xx_mc.h" +#include "hw/misc/npcm_clk.h" +#include "hw/misc/npcm_gcr.h" +#include "hw/misc/npcm7xx_mft.h" +#include "hw/misc/npcm7xx_pci_mbox.h" +#include "hw/misc/npcm7xx_pwm.h" +#include "hw/misc/npcm7xx_rng.h" +#include "hw/net/npcm_gmac.h" +#include "hw/net/npcm_pcs.h" +#include "hw/nvram/npcm7xx_otp.h" +#include "hw/peci/npcm7xx_peci.h" +#include "hw/pci-host/npcm_pcierc.h" +#include "hw/sd/npcm7xx_sdhci.h" +#include "hw/timer/npcm7xx_timer.h" +#include "hw/ssi/npcm7xx_fiu.h" +#include "hw/usb/hcd-ehci.h" +#include "hw/usb/hcd-ohci.h" +#include "target/arm/cpu.h" + +#define NPCM8XX_MAX_NUM_CPUS (4) + +/* The first half of the address space is reserved for DDR4 DRAM. */ +#define NPCM8XX_DRAM_BA (0x00000000) +#define NPCM8XX_DRAM_SZ (2 * GiB) + +/* Magic addresses for setting up direct kernel booting and SMP boot stubs= . */ +#define NPCM8XX_LOADER_START (0x00000000) /* Start of SDRAM */ +#define NPCM8XX_SMP_LOADER_START (0xffff0000) /* Boot ROM */ +#define NPCM8XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */ +#define NPCM8XX_BOARD_SETUP_ADDR (0xffff1000) /* Boot ROM */ + +#define NPCM8XX_NR_PWM_MODULES 3 + +typedef struct NPCM8xxState { + DeviceState parent; + + ARMCPU cpu[NPCM8XX_MAX_NUM_CPUS]; + CPUClusterState cpu_cluster; + GICState gic; + + MemoryRegion sram; + MemoryRegion irom; + MemoryRegion ram3; + MemoryRegion *dram; + + NPCMGCRState gcr; + NPCMCLKState clk; + NPCM7xxTimerCtrlState tim[3]; + NPCM7xxADCState adc; + NPCM7xxPWMState pwm[NPCM8XX_NR_PWM_MODULES]; + NPCM7xxMFTState mft[8]; + NPCM7xxOTPState fuse_array; + NPCM7xxMCState mc; + NPCM7xxRNGState rng; + NPCM7xxGPIOState gpio[8]; + NPCMSMBusState smbus[27]; + NPCM7xxKCSState kcs; + EHCISysBusState ehci[2]; + OHCISysBusState ohci[2]; + NPCM7xxFIUState fiu[3]; + NPCMGMACState gmac[4]; + NPCMPCSState pcs; + NPCM7xxPCIMBoxState pci_mbox[2]; + NPCM7xxSDHCIState mmc; + NPCM7xxPECIState peci; + NPCMPCIERCState pcierc; +} NPCM8xxState; + +typedef struct NPCM8xxClass { + DeviceClass parent; + + /* Bitmask of modules that are permanently disabled on this chip. */ + uint32_t disabled_modules; + /* Number of CPU cores enabled in this SoC class. */ + uint32_t num_cpus; +} NPCM8xxClass; + +#define TYPE_NPCM8XX "npcm8xx" +OBJECT_DECLARE_TYPE(NPCM8xxState, NPCM8xxClass, NPCM8XX) + +/** + * npcm8xx_load_kernel - Loads memory with everything needed to boot + * @machine - The machine containing the SoC to be booted. + * @soc - The SoC containing the CPU to be booted. + * + * This will set up the ARM boot info structure for the specific NPCM8xx + * derivative and call arm_load_kernel() to set up loading of the kernel, = etc. + * into memory, if requested by the user. + */ +void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc); + +#endif /* NPCM8XX_H */ --=20 2.42.0.459.ge4e396fd5e-goog From nobody Sat May 18 22:31:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1695154082; cv=none; d=zohomail.com; s=zohoarc; b=NCerX6Nq0oQRFJLCYwLIwM67Oeo2mJltAALRpcvjIusfvyfDTLMYOT+ClEF/6EIMyI4fIJDiVLr5ZroBHo8qMbMkJi/RPlXLauc9MVCCKkZqNvN8sw+DJFVhmGw6vdS0xTV73Bn5liPBvVCI1fBWEdbh01y/V5vojpDkTU5L8kE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695154082; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0joMDJfdVcSOlSumVdw9F57UYMZZhd+yugc3hviET2M=; b=B2Gr6kijjLojpxN/k+r9LkQ4gk+KAvevcnXfM36WwlvcRLoHhjPj1zsEIqGe632Th4o8EzjBb7KHTTfiTwaWpeWgQvRWbwf9QrU2+B2gtiMvqD+XctVVXjor2IxNGwlIP4VjccmFRn4jVEwJ/IVMrnxceDfOd+lUyLaegvYtEDg= ARC-Authentication-Results: i=1; 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charset="utf-8" From: Hao Wu Signed-off-by: Hao Wu --- hw/arm/npcm7xx.c | 38 ++++++++++++++++++++++++++++++++++++-- include/hw/arm/npcm7xx.h | 3 +++ 2 files changed, 39 insertions(+), 2 deletions(-) diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index c69e936669..15c58ef4a9 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -92,6 +92,7 @@ enum NPCM7xxInterrupt { NPCM7XX_GMAC1_IRQ =3D 14, NPCM7XX_EMC1RX_IRQ =3D 15, NPCM7XX_EMC1TX_IRQ, + NPCM7XX_GMAC2_IRQ, NPCM7XX_MMC_IRQ =3D 26, NPCM7XX_PSPI2_IRQ =3D 28, NPCM7XX_PSPI1_IRQ =3D 31, @@ -235,6 +236,12 @@ static const hwaddr npcm7xx_pspi_addr[] =3D { 0xf0201000, }; =20 +/* Register base address for each GMAC Module */ +static const hwaddr npcm7xx_gmac_addr[] =3D { + 0xf0802000, + 0xf0804000, +}; + static const struct { hwaddr regs_addr; uint32_t unconnected_pins; @@ -463,6 +470,12 @@ static void npcm7xx_init(Object *obj) object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSP= I); } =20 + for (i =3D 0; i < ARRAY_SIZE(s->gmac); i++) { + object_initialize_child(obj, "gmac[*]", &s->gmac[i], TYPE_NPCM_GMA= C); + } + + object_initialize_child(obj, "pci-mbox", &s->pci_mbox, + TYPE_NPCM7XX_PCI_MBOX); object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI); } =20 @@ -694,6 +707,29 @@ static void npcm7xx_realize(DeviceState *dev, Error **= errp) sysbus_connect_irq(sbd, 1, npcm7xx_irq(s, rx_irq)); } =20 + /* + * GMAC Modules. Cannot fail. + */ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gmac_addr) !=3D ARRAY_SIZE(s->gma= c)); + QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->gmac) !=3D 2); + for (i =3D 0; i < ARRAY_SIZE(s->gmac); i++) { + SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->gmac[i]); + + /* + * The device exists regardless of whether it's connected to a QEMU + * netdev backend. So always instantiate it even if there is no + * backend. + */ + sysbus_realize(sbd, &error_abort); + sysbus_mmio_map(sbd, 0, npcm7xx_gmac_addr[i]); + int irq =3D i =3D=3D 0 ? NPCM7XX_GMAC1_IRQ : NPCM7XX_GMAC2_IRQ; + /* + * N.B. The values for the second argument sysbus_connect_irq are + * chosen to match the registration order in npcm7xx_emc_realize. + */ + sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq)); + } + /* * Flash Interface Unit (FIU). Can fail if incorrect number of chip se= lects * specified, but this is a programming error. @@ -764,8 +800,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **e= rrp) create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * = KiB); create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * = MiB); create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * = KiB); - create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * = KiB); - create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * = KiB); create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * = KiB); create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * = KiB); create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * = KiB); diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index 273090ac60..9e5cf639a2 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -30,6 +30,7 @@ #include "hw/misc/npcm7xx_pwm.h" #include "hw/misc/npcm7xx_rng.h" #include "hw/net/npcm7xx_emc.h" +#include "hw/net/npcm_gmac.h" #include "hw/nvram/npcm7xx_otp.h" #include "hw/timer/npcm7xx_timer.h" #include "hw/ssi/npcm7xx_fiu.h" @@ -105,6 +106,8 @@ struct NPCM7xxState { OHCISysBusState ohci; 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Tue, 19 Sep 2023 10:57:54 -0700 (PDT) Date: Tue, 19 Sep 2023 17:57:19 +0000 In-Reply-To: <20230919175725.3413108-1-nabihestefan@google.com> Mime-Version: 1.0 References: <20230919175725.3413108-1-nabihestefan@google.com> X-Mailer: git-send-email 2.42.0.459.ge4e396fd5e-goog Message-ID: <20230919175725.3413108-9-nabihestefan@google.com> Subject: [PATCH 08/14] \tests/qtest: Creating qtest for GMAC Module From: Nabih Estefan To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kfting@nuvoton.com, wuhaotsh@google.com, jasonwang@redhat.com, Avi.Fishman@nuvoton.com, Nabih Estefan Diaz Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1149; envelope-from=3IuEJZQwKCjskXYfebpqbcXkdlldib.Zljnbjr-absbiklkdkr.lod@flex--nabihestefan.bounces.google.com; helo=mail-yw1-x1149.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 19 Sep 2023 16:04:51 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1695153954094100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nabih Estefan Diaz - Created qtest to check initialization of registers in GMAC Module. - Implemented test into Build File. Signed-off-by: Nabih Estefan Diaz --- tests/qtest/meson.build | 11 +- tests/qtest/npcm_gmac-test.c | 209 +++++++++++++++++++++++++++++++++++ 2 files changed, 215 insertions(+), 5 deletions(-) create mode 100644 tests/qtest/npcm_gmac-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 5adf12b45f..4d0e00444d 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -191,6 +191,8 @@ qtests_npcm7xx =3D \ 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] + \ (slirp.found() ? ['npcm7xx_emc-test'] : []) +qtests_npcm8xx =3D \ + ['npcm_gmac-test'] qtests_aspeed =3D \ ['aspeed_hace-test', 'aspeed_smc-test', @@ -205,9 +207,7 @@ qtests_arm =3D \ (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed : []) += \ (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ (config_all_devices.has_key('CONFIG_GENERIC_LOADER') ? ['hexloader-test'= ] : []) + \ - (config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test']= : []) + \ - (config_all_devices.has_key('CONFIG_VEXPRESS') ? ['test-arm-mptimer'] : = []) + \ - (config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : [])= + \ + (config_all_devices.has_key('CONFIG_NPCM8XX') ? qtests_npcm8xx : []) + \ ['arm-cpu-features', 'boot-serial-test'] =20 @@ -219,8 +219,9 @@ qtests_aarch64 =3D \ (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test'= , 'fuzz-xlnx-dp-test'] : []) + \ (config_all_devices.has_key('CONFIG_XLNX_VERSAL') ? ['xlnx-canfd-test'] = : []) + \ (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : [])= + \ - (config_all.has_key('CONFIG_TCG') and = \ - config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test']= : []) + \ + (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed : []) += \ + (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ + (config_all_devices.has_key('CONFIG_NPCM8XX') ? qtests_npcm8xx : []) + \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c new file mode 100644 index 0000000000..30d27e8dcc --- /dev/null +++ b/tests/qtest/npcm_gmac-test.c @@ -0,0 +1,209 @@ +/* + * QTests for Nuvoton NPCM7xx/8xx GMAC Modules. + * + * Copyright 2022 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqos/libqos.h" + +/* Name of the GMAC Device */ +#define TYPE_NPCM_GMAC "npcm-gmac" + +typedef struct GMACModule { + int irq; + uint64_t base_addr; +} GMACModule; + +typedef struct TestData { + const GMACModule *module; +} TestData; + +/* Values extracted from hw/arm/npcm8xx.c */ +static const GMACModule gmac_module_list[] =3D { + { + .irq =3D 14, + .base_addr =3D 0xf0802000 + }, + { + .irq =3D 15, + .base_addr =3D 0xf0804000 + }, + { + .irq =3D 16, + .base_addr =3D 0xf0806000 + }, + { + .irq =3D 17, + .base_addr =3D 0xf0808000 + } +}; + +/* Returns the index of the GMAC module. */ +static int gmac_module_index(const GMACModule *mod) +{ + ptrdiff_t diff =3D mod - gmac_module_list; + + g_assert_true(diff >=3D 0 && diff < ARRAY_SIZE(gmac_module_list)); + + return diff; +} + +/* 32-bit register indices. Taken from npcm_gmac.c */ +typedef enum NPCMRegister { + /* DMA Registers */ + NPCM_DMA_BUS_MODE =3D 0x1000, + NPCM_DMA_XMT_POLL_DEMAND =3D 0x1004, + NPCM_DMA_RCV_POLL_DEMAND =3D 0x1008, + NPCM_DMA_RCV_BASE_ADDR =3D 0x100c, + NPCM_DMA_TX_BASE_ADDR =3D 0x1010, + NPCM_DMA_STATUS =3D 0x1014, + NPCM_DMA_CONTROL =3D 0x1018, + NPCM_DMA_INTR_ENA =3D 0x101c, + NPCM_DMA_MISSED_FRAME_CTR =3D 0x1020, + NPCM_DMA_HOST_TX_DESC =3D 0x1048, + NPCM_DMA_HOST_RX_DESC =3D 0x104c, + NPCM_DMA_CUR_TX_BUF_ADDR =3D 0x1050, + NPCM_DMA_CUR_RX_BUF_ADDR =3D 0x1054, + NPCM_DMA_HW_FEATURE =3D 0x1058, + + /* GMAC Registers */ + NPCM_GMAC_MAC_CONFIG =3D 0x0, + NPCM_GMAC_FRAME_FILTER =3D 0x4, + NPCM_GMAC_HASH_HIGH =3D 0x8, + NPCM_GMAC_HASH_LOW =3D 0xc, + NPCM_GMAC_MII_ADDR =3D 0x10, + NPCM_GMAC_MII_DATA =3D 0x14, + NPCM_GMAC_FLOW_CTRL =3D 0x18, + NPCM_GMAC_VLAN_FLAG =3D 0x1c, + NPCM_GMAC_VERSION =3D 0x20, + NPCM_GMAC_WAKEUP_FILTER =3D 0x28, + NPCM_GMAC_PMT =3D 0x2c, + NPCM_GMAC_LPI_CTRL =3D 0x30, + NPCM_GMAC_TIMER_CTRL =3D 0x34, + NPCM_GMAC_INT_STATUS =3D 0x38, + NPCM_GMAC_INT_MASK =3D 0x3c, + NPCM_GMAC_MAC0_ADDR_HI =3D 0x40, + NPCM_GMAC_MAC0_ADDR_LO =3D 0x44, + NPCM_GMAC_MAC1_ADDR_HI =3D 0x48, + NPCM_GMAC_MAC1_ADDR_LO =3D 0x4c, + NPCM_GMAC_MAC2_ADDR_HI =3D 0x50, + NPCM_GMAC_MAC2_ADDR_LO =3D 0x54, + NPCM_GMAC_MAC3_ADDR_HI =3D 0x58, + NPCM_GMAC_MAC3_ADDR_LO =3D 0x5c, + NPCM_GMAC_RGMII_STATUS =3D 0xd8, + NPCM_GMAC_WATCHDOG =3D 0xdc, + NPCM_GMAC_PTP_TCR =3D 0x700, + NPCM_GMAC_PTP_SSIR =3D 0x704, + NPCM_GMAC_PTP_STSR =3D 0x708, + NPCM_GMAC_PTP_STNSR =3D 0x70c, + NPCM_GMAC_PTP_STSUR =3D 0x710, + NPCM_GMAC_PTP_STNSUR =3D 0x714, + NPCM_GMAC_PTP_TAR =3D 0x718, + NPCM_GMAC_PTP_TTSR =3D 0x71c, +} NPCMRegister; + +static uint32_t gmac_read(QTestState *qts, const GMACModule *mod, + NPCMRegister regno) +{ + return qtest_readl(qts, mod->base_addr + regno); +} + +/* Check that GMAC registers are reset to default value */ +static void test_init(gconstpointer test_data) +{ + const TestData *td =3D test_data; + const GMACModule *mod =3D td->module; + QTestState *qts =3D qtest_init("-machine npcm845-evb"); + +#define CHECK_REG32(regno, value) \ + do { \ + g_assert_cmphex(gmac_read(qts, mod, (regno)), =3D=3D, (value)); \ + } while (0) + + CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100); + CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0); + CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0); + CHECK_REG32(NPCM_DMA_RCV_BASE_ADDR, 0); + CHECK_REG32(NPCM_DMA_TX_BASE_ADDR, 0); + CHECK_REG32(NPCM_DMA_STATUS, 0); + CHECK_REG32(NPCM_DMA_CONTROL, 0); + CHECK_REG32(NPCM_DMA_INTR_ENA, 0); + CHECK_REG32(NPCM_DMA_MISSED_FRAME_CTR, 0); + CHECK_REG32(NPCM_DMA_HOST_TX_DESC, 0); + CHECK_REG32(NPCM_DMA_HOST_RX_DESC, 0); + CHECK_REG32(NPCM_DMA_CUR_TX_BUF_ADDR, 0); + CHECK_REG32(NPCM_DMA_CUR_RX_BUF_ADDR, 0); + CHECK_REG32(NPCM_DMA_HW_FEATURE, 0x100d4f37); + + CHECK_REG32(NPCM_GMAC_MAC_CONFIG, 0); + CHECK_REG32(NPCM_GMAC_FRAME_FILTER, 0); + CHECK_REG32(NPCM_GMAC_HASH_HIGH, 0); + CHECK_REG32(NPCM_GMAC_HASH_LOW, 0); + CHECK_REG32(NPCM_GMAC_MII_ADDR, 0); + CHECK_REG32(NPCM_GMAC_MII_DATA, 0); + CHECK_REG32(NPCM_GMAC_FLOW_CTRL, 0); + CHECK_REG32(NPCM_GMAC_VLAN_FLAG, 0); + CHECK_REG32(NPCM_GMAC_VERSION, 0x00001037); + CHECK_REG32(NPCM_GMAC_WAKEUP_FILTER, 0); + CHECK_REG32(NPCM_GMAC_PMT, 0); + CHECK_REG32(NPCM_GMAC_LPI_CTRL, 0); + CHECK_REG32(NPCM_GMAC_TIMER_CTRL, 0x03e80000); + CHECK_REG32(NPCM_GMAC_INT_STATUS, 0); + CHECK_REG32(NPCM_GMAC_INT_MASK, 0); + CHECK_REG32(NPCM_GMAC_MAC0_ADDR_HI, 0x8000ffff); + CHECK_REG32(NPCM_GMAC_MAC0_ADDR_LO, 0xffffffff); + CHECK_REG32(NPCM_GMAC_MAC1_ADDR_HI, 0x0000ffff); + CHECK_REG32(NPCM_GMAC_MAC1_ADDR_LO, 0xffffffff); + CHECK_REG32(NPCM_GMAC_MAC2_ADDR_HI, 0x0000ffff); + CHECK_REG32(NPCM_GMAC_MAC2_ADDR_LO, 0xffffffff); + CHECK_REG32(NPCM_GMAC_MAC3_ADDR_HI, 0x0000ffff); + CHECK_REG32(NPCM_GMAC_MAC3_ADDR_LO, 0xffffffff); + CHECK_REG32(NPCM_GMAC_RGMII_STATUS, 0); + CHECK_REG32(NPCM_GMAC_WATCHDOG, 0); + CHECK_REG32(NPCM_GMAC_PTP_TCR, 0x00002000); + CHECK_REG32(NPCM_GMAC_PTP_SSIR, 0); + CHECK_REG32(NPCM_GMAC_PTP_STSR, 0); + CHECK_REG32(NPCM_GMAC_PTP_STNSR, 0); + CHECK_REG32(NPCM_GMAC_PTP_STSUR, 0); + CHECK_REG32(NPCM_GMAC_PTP_STNSUR, 0); + CHECK_REG32(NPCM_GMAC_PTP_TAR, 0); + CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0); + + qtest_quit(qts); +} + +static void gmac_add_test(const char *name, const TestData* td, + GTestDataFunc fn) +{ + g_autofree char *full_name =3D g_strdup_printf( + "npcm8xx_gmac/gmac[%d]/%s", gmac_module_index(td->module), nam= e); + qtest_add_data_func(full_name, td, fn); +} + +int main(int argc, char **argv) +{ + TestData test_data_list[ARRAY_SIZE(gmac_module_list)]; + + g_test_init(&argc, &argv, NULL); + + for (int i =3D 0; i < ARRAY_SIZE(gmac_module_list); ++i) { + TestData *td =3D &test_data_list[i]; + + td->module =3D &gmac_module_list[i]; + + gmac_add_test("init", td, test_init); + } + + return g_test_run(); +} --=20 2.42.0.459.ge4e396fd5e-goog From nobody Sat May 18 22:31:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1695153982; cv=none; d=zohomail.com; s=zohoarc; b=YoM0SdTb0PqG3Bwog62l0IYF+NOLNhCs97dtCLkxmsrKwkSJ6zSpJWPDiCEVzDjWinDcIaufTu08P+0ItG4jxKP1FNzuAXSCiiPTXffpc7J9x6/tHaKd0/9GkITWbWq3ZPPiQv5z90/3Qr+3+6Tt73+0qq26PEx0lZn1Yhscgkk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695153982; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Tue, 19 Sep 2023 10:57:56 -0700 (PDT) Date: Tue, 19 Sep 2023 17:57:20 +0000 In-Reply-To: <20230919175725.3413108-1-nabihestefan@google.com> Mime-Version: 1.0 References: <20230919175725.3413108-1-nabihestefan@google.com> X-Mailer: git-send-email 2.42.0.459.ge4e396fd5e-goog Message-ID: <20230919175725.3413108-10-nabihestefan@google.com> Subject: [PATCH 09/14] include/hw/net: Implemented Classes and Masks for GMAC Descriptors From: Nabih Estefan To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kfting@nuvoton.com, wuhaotsh@google.com, jasonwang@redhat.com, Avi.Fishman@nuvoton.com, Nabih Estefan Diaz Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::b49; envelope-from=3JOEJZQwKCj0mZahgdrsdeZmfnnfkd.bnlpdlt-cdudkmnmfmt.nqf@flex--nabihestefan.bounces.google.com; helo=mail-yb1-xb49.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 19 Sep 2023 16:04:51 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1695153982928100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nabih Estefan Diaz - Implemeted classes for GMAC Receive and Transmit Descriptors - Implemented Masks for said descriptors Signed-off-by: Nabih Estefan Diaz --- include/hw/net/npcm_gmac.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/include/hw/net/npcm_gmac.h b/include/hw/net/npcm_gmac.h index 03529db1d6..067928fe0b 100644 --- a/include/hw/net/npcm_gmac.h +++ b/include/hw/net/npcm_gmac.h @@ -38,12 +38,19 @@ struct NPCMGMACRxDesc { /* RDES2 and RDES3 are buffer address pointers */ /* Owner: 0 =3D software, 1 =3D gmac */ #define RX_DESC_RDES0_OWNER_MASK BIT(31) +<<<<<<< HEAD /* Owner*/ #define RX_DESC_RDES0_OWNER_SHIFT 31 /* Destination Address Filter Fail */ #define RX_DESC_RDES0_DEST_ADDR_FILT_FAIL_MASK BIT(30) /* Frame length*/ #define RX_DESC_RDES0_FRAME_LEN_MASK(word) extract32(word, 16, 29) +=3D=3D=3D=3D=3D=3D=3D +/* Destination Address Filter Fail */ +#define RX_DESC_RDES0_DEST_ADDR_FILT_FAIL_MASK BIT(30) +/* Frame length*/ +#define RX_DESC_RDES0_FRAME_LEN_MASK extract32(rdes0, 16, 29) +>>>>>>> f17fd3e311 (include/hw/net: Implemented Classes and Masks for GMAC= Descriptors) /* Error Summary */ #define RX_DESC_RDES0_ERR_SUMM_MASK BIT(15) /* Descriptor Error */ @@ -84,11 +91,17 @@ struct NPCMGMACRxDesc { /* Second Address Chained */ #define RX_DESC_RDES1_SEC_ADDR_CHND_MASK BIT(24) /* Receive Buffer 2 Size */ +<<<<<<< HEAD #define RX_DESC_RDES1_BFFR2_SZ_SHIFT 11 #define RX_DESC_RDES1_BFFR2_SZ_MASK(word) extract32(word, \ RX_DESC_RDES1_BFFR2_SZ_SHIFT, 10 + RX_DESC_RDES1_BFFR2_SZ_SHIFT) /* Receive Buffer 1 Size */ #define RX_DESC_RDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 10) +=3D=3D=3D=3D=3D=3D=3D +#define RX_DESC_RDES1_BFFR2_SZ_MASK extract32(rdes1, 11, 21) +/* Receive Buffer 1 Size */ +#define RX_DESC_RDES1_BFFR1_SZ_MASK extract32(rdes1, 0, 10) +>>>>>>> f17fd3e311 (include/hw/net: Implemented Classes and Masks for GMAC= Descriptors) =20 =20 struct NPCMGMACTxDesc { @@ -125,7 +138,11 @@ struct NPCMGMACTxDesc { /* VLAN Frame */ #define TX_DESC_TDES0_VLAN_FRM_MASK BIT(7) /* Collision Count */ +<<<<<<< HEAD #define TX_DESC_TDES0_COLL_CNT_MASK(word) extract32(word, 3, 6) +=3D=3D=3D=3D=3D=3D=3D +#define TX_DESC_TDES0_COLL_CNT_MASK extract32(tdes0, 3, 6) +>>>>>>> f17fd3e311 (include/hw/net: Implemented Classes and Masks for GMAC= Descriptors) /* Excessive Deferral */ #define TX_DESC_TDES0_EXCS_DEF_MASK BIT(2) /* Underflow Error */ @@ -140,7 +157,11 @@ struct NPCMGMACTxDesc { /* Last Segment */ #define TX_DESC_TDES1_FIRST_SEG_MASK BIT(29) /* Checksum Insertion Control */ +<<<<<<< HEAD #define TX_DESC_TDES1_CHKSM_INS_CTRL_MASK(word) extract32(word, 27, 28) +=3D=3D=3D=3D=3D=3D=3D +#define TX_DESC_TDES1_CHKSM_INS_CTRL_MASK extract32(tdes1, 27, 28) +>>>>>>> f17fd3e311 (include/hw/net: Implemented Classes and Masks for GMAC= Descriptors) /* Disable Cyclic Redundancy Check */ #define TX_DESC_TDES1_DIS_CDC_MASK BIT(26) /* Transmit End of Ring */ @@ -148,9 +169,15 @@ struct NPCMGMACTxDesc { /* Secondary Address Chained */ #define TX_DESC_TDES1_SEC_ADDR_CHND_MASK BIT(24) /* Transmit Buffer 2 Size */ +<<<<<<< HEAD #define TX_DESC_TDES1_BFFR2_SZ_MASK(word) extract32(word, 11, 21) /* Transmit Buffer 1 Size */ #define TX_DESC_TDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 10) +=3D=3D=3D=3D=3D=3D=3D +#define TX_DESC_TDES1_BFFR2_SZ_MASK extract32(tdes1, 11, 21) +/* Transmit Buffer 1 Size */ +#define TX_DESC_TDES1_BFFR1_SZ_MASK extract32(tdes1, 0, 10) +>>>>>>> f17fd3e311 (include/hw/net: Implemented Classes and Masks for GMAC= Descriptors) =20 typedef struct NPCMGMACState { SysBusDevice parent; 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charset="utf-8" From: Nabih Estefan Diaz - General GMAC Register handling - GMAC IRQ Handling - Added traces in some methods for debugging - Lots of declarations for accessing information on GMAC Descriptors (npcm_= gmac.h file) NOTE: With code on this state, the GMAC can boot-up properly and will show = up in the ifconfig command on the BMC Signed-off-by: Nabih Estefan Diaz --- hw/net/npcm_gmac.c | 183 ++++++++++++++++++++------- hw/net/trace-events | 9 ++ include/hw/net/npcm_gmac.h | 233 ++++++++++++++++++++++++++++------- tests/qtest/npcm_gmac-test.c | 2 +- 4 files changed, 338 insertions(+), 89 deletions(-) diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm_gmac.c index 5ce632858d..6f8109e0ee 100644 --- a/hw/net/npcm_gmac.c +++ b/hw/net/npcm_gmac.c @@ -32,7 +32,7 @@ REG32(NPCM_DMA_BUS_MODE, 0x1000) REG32(NPCM_DMA_XMT_POLL_DEMAND, 0x1004) REG32(NPCM_DMA_RCV_POLL_DEMAND, 0x1008) -REG32(NPCM_DMA_RCV_BASE_ADDR, 0x100c) +REG32(NPCM_DMA_RX_BASE_ADDR, 0x100c) REG32(NPCM_DMA_TX_BASE_ADDR, 0x1010) REG32(NPCM_DMA_STATUS, 0x1014) REG32(NPCM_DMA_CONTROL, 0x1018) @@ -91,7 +91,8 @@ REG32(NPCM_GMAC_PTP_TTSR, 0x71c) #define NPCM_DMA_BUS_MODE_SWR BIT(0) =20 static const uint32_t npcm_gmac_cold_reset_values[NPCM_GMAC_NR_REGS] =3D { - [R_NPCM_GMAC_VERSION] =3D 0x00001037, + /* Reduce version to 3.2 so that the kernel can enable interrupt. */ + [R_NPCM_GMAC_VERSION] =3D 0x00001032, [R_NPCM_GMAC_TIMER_CTRL] =3D 0x03e80000, [R_NPCM_GMAC_MAC0_ADDR_HI] =3D 0x8000ffff, [R_NPCM_GMAC_MAC0_ADDR_LO] =3D 0xffffffff, @@ -125,12 +126,12 @@ static const uint16_t phy_reg_init[] =3D { [MII_EXTSTAT] =3D 0x3000, /* 1000BASTE_T full-duplex capable */ }; =20 -static void npcm_gmac_soft_reset(NPCMGMACState *s) +static void npcm_gmac_soft_reset(NPCMGMACState *gmac) { - memcpy(s->regs, npcm_gmac_cold_reset_values, + memcpy(gmac->regs, npcm_gmac_cold_reset_values, NPCM_GMAC_NR_REGS * sizeof(uint32_t)); /* Clear reset bits */ - s->regs[R_NPCM_DMA_BUS_MODE] &=3D ~NPCM_DMA_BUS_MODE_SWR; + gmac->regs[R_NPCM_DMA_BUS_MODE] &=3D ~NPCM_DMA_BUS_MODE_SWR; } =20 static void gmac_phy_set_link(NPCMGMACState *s, bool active) @@ -148,11 +149,53 @@ static bool gmac_can_receive(NetClientState *nc) return true; } =20 -static ssize_t gmac_receive(NetClientState *nc, const uint8_t *buf, size_t= len1) +/* + * Function that updates the GMAC IRQ + * It find the logical OR of the enabled bits for NIS (if enabled) + * It find the logical OR of the enabled bits for AIS (if enabled) + */ +static void gmac_update_irq(NPCMGMACState *gmac) { - return 0; + /* + * Check if the normal interrupts summery is enabled + * if so, add the bits for the summary that are enabled + */ + if (gmac->regs[R_NPCM_DMA_INTR_ENA] & gmac->regs[R_NPCM_DMA_STATUS] & + (NPCM_DMA_INTR_ENAB_NIE_BITS)) + { + gmac->regs[R_NPCM_DMA_STATUS] |=3D NPCM_DMA_STATUS_NIS; + } + /* + * Check if the abnormal interrupts summery is enabled + * if so, add the bits for the summary that are enabled + */ + if (gmac->regs[R_NPCM_DMA_INTR_ENA] & gmac->regs[R_NPCM_DMA_STATUS] & + (NPCM_DMA_INTR_ENAB_AIE_BITS)) + { + gmac->regs[R_NPCM_DMA_STATUS] |=3D NPCM_DMA_STATUS_AIS; + } + + /* Get the logical OR of both normal and abnormal interrupts */ + int level =3D !!((gmac->regs[R_NPCM_DMA_STATUS] & + gmac->regs[R_NPCM_DMA_INTR_ENA] & + NPCM_DMA_STATUS_NIS) | + (gmac->regs[R_NPCM_DMA_STATUS] & + gmac->regs[R_NPCM_DMA_INTR_ENA] & + NPCM_DMA_STATUS_AIS)); + + /* Set the IRQ */ + trace_npcm_gmac_update_irq(DEVICE(gmac)->canonical_path, + gmac->regs[R_NPCM_DMA_STATUS], + gmac->regs[R_NPCM_DMA_INTR_ENA], + level); + qemu_set_irq(gmac->irq, level); } =20 +static ssize_t gmac_receive(NetClientState *nc, const uint8_t *buf, size_t= len) +{ + /* Placeholder */ + return 0; +} static void gmac_cleanup(NetClientState *nc) { /* Nothing to do yet. */ @@ -166,7 +209,7 @@ static void gmac_set_link(NetClientState *nc) gmac_phy_set_link(s, !nc->link_down); } =20 -static void npcm_gmac_mdio_access(NPCMGMACState *s, uint16_t v) +static void npcm_gmac_mdio_access(NPCMGMACState *gmac, uint16_t v) { bool busy =3D v & NPCM_GMAC_MII_ADDR_BUSY; uint8_t is_write; @@ -183,33 +226,38 @@ static void npcm_gmac_mdio_access(NPCMGMACState *s, u= int16_t v) =20 =20 if (v & NPCM_GMAC_MII_ADDR_WRITE) { - data =3D s->regs[R_NPCM_GMAC_MII_DATA]; + data =3D gmac->regs[R_NPCM_GMAC_MII_DATA]; /* Clear reset bit for BMCR register */ switch (gr) { case MII_BMCR: data &=3D ~MII_BMCR_RESET; - /* Complete auto-negotiation immediately and set as comple= te */ - if (data & MII_BMCR_AUTOEN) { + /* Autonegotiation is a W1C bit*/ + if (data & MII_BMCR_ANRESTART) { /* Tells autonegotiation to not restart again */ data &=3D ~MII_BMCR_ANRESTART; + } + if ((data & MII_BMCR_AUTOEN) && + !(gmac->phy_regs[pa][MII_BMSR] & MII_BMSR_AN_COMP)) { /* sets autonegotiation as complete */ - s->phy_regs[pa][MII_BMSR] |=3D MII_BMSR_AN_COMP; + gmac->phy_regs[pa][MII_BMSR] |=3D MII_BMSR_AN_COMP; + /* Resolve AN automatically->need to set this */ + gmac->phy_regs[0][MII_ANLPAR] =3D 0x0000; } } - s->phy_regs[pa][gr] =3D data; + gmac->phy_regs[pa][gr] =3D data; } else { - data =3D s->phy_regs[pa][gr]; - s->regs[R_NPCM_GMAC_MII_DATA] =3D data; + data =3D gmac->phy_regs[pa][gr]; + gmac->regs[R_NPCM_GMAC_MII_DATA] =3D data; } - trace_npcm_gmac_mdio_access(DEVICE(s)->canonical_path, is_write, p= a, - gr, data); + trace_npcm_gmac_mdio_access(DEVICE(gmac)->canonical_path, is_write= , pa, + gr, data); } - s->regs[R_NPCM_GMAC_MII_ADDR] =3D v & ~NPCM_GMAC_MII_ADDR_BUSY; + gmac->regs[R_NPCM_GMAC_MII_ADDR] =3D v & ~NPCM_GMAC_MII_ADDR_BUSY; } =20 static uint64_t npcm_gmac_read(void *opaque, hwaddr offset, unsigned size) { - NPCMGMACState *s =3D opaque; + NPCMGMACState *gmac =3D opaque; uint32_t v =3D 0; =20 switch (offset) { @@ -218,22 +266,25 @@ static uint64_t npcm_gmac_read(void *opaque, hwaddr o= ffset, unsigned size) case A_NPCM_DMA_RCV_POLL_DEMAND: qemu_log_mask(LOG_GUEST_ERROR, "%s: Read of write-only reg: offset: 0x%04" HWADDR_P= RIx - "\n", DEVICE(s)->canonical_path, offset); + "\n", DEVICE(gmac)->canonical_path, offset); break; =20 default: - v =3D s->regs[offset / sizeof(uint32_t)]; + v =3D gmac->regs[offset / sizeof(uint32_t)]; } - trace_npcm_gmac_reg_read(DEVICE(s)->canonical_path, offset, v); + + trace_npcm_gmac_reg_read(DEVICE(gmac)->canonical_path, offset, v); return v; } =20 static void npcm_gmac_write(void *opaque, hwaddr offset, uint64_t v, unsigned size) { - NPCMGMACState *s =3D opaque; + NPCMGMACState *gmac =3D opaque; + uint32_t prev; + + trace_npcm_gmac_reg_write(DEVICE(gmac)->canonical_path, offset, v); =20 - trace_npcm_gmac_reg_write(DEVICE(s)->canonical_path, offset, v); switch (offset) { /* Read only registers */ case A_NPCM_GMAC_VERSION: @@ -250,25 +301,44 @@ static void npcm_gmac_write(void *opaque, hwaddr offs= et, qemu_log_mask(LOG_GUEST_ERROR, "%s: Write of read-only reg: offset: 0x%04" HWADDR_P= RIx ", value: 0x%04" PRIx64 "\n", - DEVICE(s)->canonical_path, offset, v); + DEVICE(gmac)->canonical_path, offset, v); + break; + + case A_NPCM_GMAC_MAC_CONFIG: + prev =3D gmac->regs[offset / sizeof(uint32_t)]; + gmac->regs[offset / sizeof(uint32_t)] =3D v; + + /* If transmit is being enabled for first time, update desc addr */ + if (~(prev & NPCM_GMAC_MAC_CONFIG_TX_EN) & + (v & NPCM_GMAC_MAC_CONFIG_TX_EN)) { + gmac->regs[R_NPCM_DMA_HOST_TX_DESC] =3D + gmac->regs[R_NPCM_DMA_TX_BASE_ADDR]; + } + + /* If receive is being enabled for first time, update desc addr */ + if (~(prev & NPCM_GMAC_MAC_CONFIG_RX_EN) & + (v & NPCM_GMAC_MAC_CONFIG_RX_EN)) { + gmac->regs[R_NPCM_DMA_HOST_RX_DESC] =3D + gmac->regs[R_NPCM_DMA_RX_BASE_ADDR]; + } break; =20 case A_NPCM_GMAC_MII_ADDR: - npcm_gmac_mdio_access(s, v); + npcm_gmac_mdio_access(gmac, v); break; =20 case A_NPCM_GMAC_MAC0_ADDR_HI: - s->regs[offset / sizeof(uint32_t)] =3D v; - s->conf.macaddr.a[0] =3D v >> 8; - s->conf.macaddr.a[1] =3D v >> 0; + gmac->regs[offset / sizeof(uint32_t)] =3D v; + gmac->conf.macaddr.a[0] =3D v >> 8; + gmac->conf.macaddr.a[1] =3D v >> 0; break; =20 case A_NPCM_GMAC_MAC0_ADDR_LO: - s->regs[offset / sizeof(uint32_t)] =3D v; - s->conf.macaddr.a[2] =3D v >> 24; - s->conf.macaddr.a[3] =3D v >> 16; - s->conf.macaddr.a[4] =3D v >> 8; - s->conf.macaddr.a[5] =3D v >> 0; + gmac->regs[offset / sizeof(uint32_t)] =3D v; + gmac->conf.macaddr.a[2] =3D v >> 24; + gmac->conf.macaddr.a[3] =3D v >> 16; + gmac->conf.macaddr.a[4] =3D v >> 8; + gmac->conf.macaddr.a[5] =3D v >> 0; break; =20 case A_NPCM_GMAC_MAC1_ADDR_HI: @@ -277,33 +347,60 @@ static void npcm_gmac_write(void *opaque, hwaddr offs= et, case A_NPCM_GMAC_MAC2_ADDR_LO: case A_NPCM_GMAC_MAC3_ADDR_HI: case A_NPCM_GMAC_MAC3_ADDR_LO: - s->regs[offset / sizeof(uint32_t)] =3D v; + gmac->regs[offset / sizeof(uint32_t)] =3D v; qemu_log_mask(LOG_UNIMP, "%s: Only MAC Address 0 is supported. This request " - "is ignored.\n", DEVICE(s)->canonical_path); + "is ignored.\n", DEVICE(gmac)->canonical_path); break; =20 case A_NPCM_DMA_BUS_MODE: - s->regs[offset / sizeof(uint32_t)] =3D v; + gmac->regs[offset / sizeof(uint32_t)] =3D v; if (v & NPCM_DMA_BUS_MODE_SWR) { - npcm_gmac_soft_reset(s); + npcm_gmac_soft_reset(gmac); + } + break; + + case A_NPCM_DMA_RCV_POLL_DEMAND: + /* We dont actually care about the value */ + break; + + case A_NPCM_DMA_STATUS: + /* Check that RO bits are not written to */ + if (NPCM_DMA_STATUS_RO_MASK(v)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Write of read-only bits of reg: offset: 0x%= 04" + HWADDR_PRIx ", value: 0x%04" PRIx64 "\n", + DEVICE(gmac)->canonical_path, offset, v); + } else { + /* for W1c bits, implement W1C */ + gmac->regs[offset / sizeof(uint32_t)] &=3D + ~NPCM_DMA_STATUS_W1C_MASK(v); + if (v & NPCM_DMA_STATUS_NIS_BITS) { + gmac->regs[offset / sizeof(uint32_t)] &=3D ~NPCM_DMA_STATU= S_NIS; + } + if (v & NPCM_DMA_STATUS_AIS_BITS) { + gmac->regs[offset / sizeof(uint32_t)] &=3D ~NPCM_DMA_STATU= S_AIS; + } } break; =20 default: - s->regs[offset / sizeof(uint32_t)] =3D v; + gmac->regs[offset / sizeof(uint32_t)] =3D v; break; } + + gmac_update_irq(gmac); } =20 static void npcm_gmac_reset(DeviceState *dev) { - NPCMGMACState *s =3D NPCM_GMAC(dev); + NPCMGMACState *gmac =3D NPCM_GMAC(dev); =20 - npcm_gmac_soft_reset(s); - memcpy(s->phy_regs[0], phy_reg_init, sizeof(phy_reg_init)); + npcm_gmac_soft_reset(gmac); + memcpy(gmac->phy_regs[0], phy_reg_init, sizeof(phy_reg_init)); =20 - trace_npcm_gmac_reset(DEVICE(s)->canonical_path, s->phy_regs[0][MII_BM= SR]); + trace_npcm_gmac_reset(DEVICE(gmac)->canonical_path, + gmac->phy_regs[0][MII_BMSR]); } =20 static NetClientInfo net_npcm_gmac_info =3D { diff --git a/hw/net/trace-events b/hw/net/trace-events index 27b006f40a..c133745fa6 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -470,6 +470,15 @@ npcm_gmac_reg_write(const char *name, uint64_t offset,= uint32_t value) "%s: offs npcm_gmac_mdio_access(const char *name, uint8_t is_write, uint8_t pa, uint= 8_t gr, uint16_t val) "%s: is_write: %" PRIu8 " pa: %" PRIu8 " gr: %" PRIu8= " val: 0x%04" PRIx16 npcm_gmac_reset(const char *name, uint16_t value) "%s: phy_regs[0][1]: 0x%= 04" PRIx16 npcm_gmac_set_link(bool active) "Set link: active=3D%u" +npcm_gmac_update_irq(const char *name, uint32_t status, uint32_t intr_en, = int level) "%s: Status Reg: 0x%04" PRIX32 " Interrupt Enable Reg: 0x%04" PR= IX32 " IRQ Set: %d" +npcm_gmac_packet_desc_read(const char* name, uint32_t desc_addr) "%s: atte= mpting to read descriptor @0x%04" PRIX32 +npcm_gmac_packet_receive(const char* name, uint32_t len) "%s: RX packet le= ngth: 0x%04" PRIX32 +npcm_gmac_packet_receiving_buffer(const char* name, uint32_t buf_len, uint= 32_t rx_buf_addr) "%s: Receiving into Buffer size: 0x%04" PRIX32 " at addre= ss 0x%04" PRIX32 +npcm_gmac_packet_received(const char* name, uint32_t len) "%s: Reception f= inished, packet left: 0x%04" PRIX32 +npcm_gmac_packet_transmit(const char* name, uint16_t len) "%s: TX transmis= sion start, packed length 0x%04" PRIX16 +npcm_gmac_packet_sent(const char* name, uint16_t len) "%s: TX packet sent!= , length: 0x%04" PRIX16 +npcm_gmac_debug_desc_data(const char* name, void* addr, uint32_t des0, uin= t32_t des1, uint32_t des2, uint32_t des3)"%s: Address: %p Descriptor 0: 0x%= 04" PRIX32 " Descriptor 1: 0x%04" PRIX32 "Descriptor 2: 0x%04" PRIX32 " Des= criptor 3: 0x%04" PRIX32 +npcm_gmac_packet_tx_desc_data(const char* name, uint32_t tdes0, uint32_t t= des1) "%s: Tdes0: 0x%04" PRIX32 " Tdes1: 0x%04" PRIX32 =20 # npcm_pcs.c npcm_pcs_reg_read(const char *name, uint16_t indirect_access_baes, uint64_= t offset, uint16_t value) "%s: IND: 0x%02" PRIx16 " offset: 0x%04" PRIx64 "= value: 0x%04" PRIx16 diff --git a/include/hw/net/npcm_gmac.h b/include/hw/net/npcm_gmac.h index 067928fe0b..c8ff154868 100644 --- a/include/hw/net/npcm_gmac.h +++ b/include/hw/net/npcm_gmac.h @@ -35,22 +35,15 @@ struct NPCMGMACRxDesc { }; =20 /* NPCMGMACRxDesc.flags values */ -/* RDES2 and RDES3 are buffer address pointers */ -/* Owner: 0 =3D software, 1 =3D gmac */ -#define RX_DESC_RDES0_OWNER_MASK BIT(31) -<<<<<<< HEAD -/* Owner*/ -#define RX_DESC_RDES0_OWNER_SHIFT 31 -/* Destination Address Filter Fail */ -#define RX_DESC_RDES0_DEST_ADDR_FILT_FAIL_MASK BIT(30) -/* Frame length*/ -#define RX_DESC_RDES0_FRAME_LEN_MASK(word) extract32(word, 16, 29) -=3D=3D=3D=3D=3D=3D=3D +/* RDES2 and RDES3 are buffer addresses */ +/* Owner: 0 =3D software, 1 =3D dma */ +#define RX_DESC_RDES0_OWN BIT(31) /* Destination Address Filter Fail */ -#define RX_DESC_RDES0_DEST_ADDR_FILT_FAIL_MASK BIT(30) -/* Frame length*/ -#define RX_DESC_RDES0_FRAME_LEN_MASK extract32(rdes0, 16, 29) ->>>>>>> f17fd3e311 (include/hw/net: Implemented Classes and Masks for GMAC= Descriptors) +#define RX_DESC_RDES0_DEST_ADDR_FILT_FAIL BIT(30) +/* Frame length */ +#define RX_DESC_RDES0_FRAME_LEN_MASK(word) extract32(word, 16, 14) +/* Frame length Shift*/ +#define RX_DESC_RDES0_FRAME_LEN_SHIFT 16 /* Error Summary */ #define RX_DESC_RDES0_ERR_SUMM_MASK BIT(15) /* Descriptor Error */ @@ -91,17 +84,11 @@ struct NPCMGMACRxDesc { /* Second Address Chained */ #define RX_DESC_RDES1_SEC_ADDR_CHND_MASK BIT(24) /* Receive Buffer 2 Size */ -<<<<<<< HEAD #define RX_DESC_RDES1_BFFR2_SZ_SHIFT 11 #define RX_DESC_RDES1_BFFR2_SZ_MASK(word) extract32(word, \ - RX_DESC_RDES1_BFFR2_SZ_SHIFT, 10 + RX_DESC_RDES1_BFFR2_SZ_SHIFT) + RX_DESC_RDES1_BFFR2_SZ_SHIFT, 11) /* Receive Buffer 1 Size */ -#define RX_DESC_RDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 10) -=3D=3D=3D=3D=3D=3D=3D -#define RX_DESC_RDES1_BFFR2_SZ_MASK extract32(rdes1, 11, 21) -/* Receive Buffer 1 Size */ -#define RX_DESC_RDES1_BFFR1_SZ_MASK extract32(rdes1, 0, 10) ->>>>>>> f17fd3e311 (include/hw/net: Implemented Classes and Masks for GMAC= Descriptors) +#define RX_DESC_RDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 11) =20 =20 struct NPCMGMACTxDesc { @@ -112,9 +99,9 @@ struct NPCMGMACTxDesc { }; =20 /* NPCMGMACTxDesc.flags values */ -/* TDES2 and TDES3 are buffer address pointers */ +/* TDES2 and TDES3 are buffer addresses */ /* Owner: 0 =3D software, 1 =3D gmac */ -#define TX_DESC_TDES0_OWNER_MASK BIT(31) +#define TX_DESC_TDES0_OWN BIT(31) /* Tx Time Stamp Status */ #define TX_DESC_TDES0_TTSS_MASK BIT(17) /* IP Header Error */ @@ -138,11 +125,7 @@ struct NPCMGMACTxDesc { /* VLAN Frame */ #define TX_DESC_TDES0_VLAN_FRM_MASK BIT(7) /* Collision Count */ -<<<<<<< HEAD -#define TX_DESC_TDES0_COLL_CNT_MASK(word) extract32(word, 3, 6) -=3D=3D=3D=3D=3D=3D=3D -#define TX_DESC_TDES0_COLL_CNT_MASK extract32(tdes0, 3, 6) ->>>>>>> f17fd3e311 (include/hw/net: Implemented Classes and Masks for GMAC= Descriptors) +#define TX_DESC_TDES0_COLL_CNT_MASK(word) extract32(word, 3, 4) /* Excessive Deferral */ #define TX_DESC_TDES0_EXCS_DEF_MASK BIT(2) /* Underflow Error */ @@ -154,14 +137,10 @@ struct NPCMGMACTxDesc { #define TX_DESC_TDES1_INTERR_COMP_MASK BIT(31) /* Last Segment */ #define TX_DESC_TDES1_LAST_SEG_MASK BIT(30) -/* Last Segment */ +/* First Segment */ #define TX_DESC_TDES1_FIRST_SEG_MASK BIT(29) /* Checksum Insertion Control */ -<<<<<<< HEAD -#define TX_DESC_TDES1_CHKSM_INS_CTRL_MASK(word) extract32(word, 27, 28) -=3D=3D=3D=3D=3D=3D=3D -#define TX_DESC_TDES1_CHKSM_INS_CTRL_MASK extract32(tdes1, 27, 28) ->>>>>>> f17fd3e311 (include/hw/net: Implemented Classes and Masks for GMAC= Descriptors) +#define TX_DESC_TDES1_CHKSM_INS_CTRL_MASK(word) extract32(word, 27, 2) /* Disable Cyclic Redundancy Check */ #define TX_DESC_TDES1_DIS_CDC_MASK BIT(26) /* Transmit End of Ring */ @@ -169,15 +148,9 @@ struct NPCMGMACTxDesc { /* Secondary Address Chained */ #define TX_DESC_TDES1_SEC_ADDR_CHND_MASK BIT(24) /* Transmit Buffer 2 Size */ -<<<<<<< HEAD -#define TX_DESC_TDES1_BFFR2_SZ_MASK(word) extract32(word, 11, 21) +#define TX_DESC_TDES1_BFFR2_SZ_MASK(word) extract32(word, 11, 11) /* Transmit Buffer 1 Size */ -#define TX_DESC_TDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 10) -=3D=3D=3D=3D=3D=3D=3D -#define TX_DESC_TDES1_BFFR2_SZ_MASK extract32(tdes1, 11, 21) -/* Transmit Buffer 1 Size */ -#define TX_DESC_TDES1_BFFR1_SZ_MASK extract32(tdes1, 0, 10) ->>>>>>> f17fd3e311 (include/hw/net: Implemented Classes and Masks for GMAC= Descriptors) +#define TX_DESC_TDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 11) =20 typedef struct NPCMGMACState { SysBusDevice parent; @@ -196,4 +169,174 @@ typedef struct NPCMGMACState { #define TYPE_NPCM_GMAC "npcm-gmac" OBJECT_DECLARE_SIMPLE_TYPE(NPCMGMACState, NPCM_GMAC) =20 -#endif /* NPCM_GMAC_H */ +/* Mask for RO bits in Status */ +#define NPCM_DMA_STATUS_RO_MASK(word) (word & 0xfffe0000) +/* Mask for RO bits in Status */ +#define NPCM_DMA_STATUS_W1C_MASK(word) (word & 0x1e7ff) + +/* Transmit Process State */ +#define NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT 20 +/* Transmit States */ +#define NPCM_DMA_STATUS_TX_STOPPED_STATE \ + (0b000) +#define NPCM_DMA_STATUS_TX_RUNNING_FETCHING_STATE \ + (0b001) +#define NPCM_DMA_STATUS_TX_RUNNING_WAITING_STATE \ + (0b010) +#define NPCM_DMA_STATUS_TX_RUNNING_READ_STATE \ + (0b011) +#define NPCM_DMA_STATUS_TX_SUSPENDED_STATE \ + (0b110) +#define NPCM_DMA_STATUS_TX_RUNNING_CLOSING_STATE \ + (0b111) +/* Transmit Process State */ +#define NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT 17 +/* Receive States */ +#define NPCM_DMA_STATUS_RX_STOPPED_STATE \ + (0b000) +#define NPCM_DMA_STATUS_RX_RUNNING_FETCHING_STATE \ + (0b001) +#define NPCM_DMA_STATUS_RX_RUNNING_WAITING_STATE \ + (0b011) +#define NPCM_DMA_STATUS_RX_SUSPENDED_STATE \ + (0b100) +#define NPCM_DMA_STATUS_RX_RUNNING_CLOSING_STATE \ + (0b101) +#define NPCM_DMA_STATUS_RX_RUNNING_TRANSFERRING_STATE \ + (0b111) + + +/* Early Receive Interrupt */ +#define NPCM_DMA_STATUS_ERI BIT(14) +/* Fatal Bus Error Interrupt */ +#define NPCM_DMA_STATUS_FBI BIT(13) +/* Early transmit Interrupt */ +#define NPCM_DMA_STATUS_ETI BIT(10) +/* Receive Watchdog Timout */ +#define NPCM_DMA_STATUS_RWT BIT(9) +/* Receive Process Stopped */ +#define NPCM_DMA_STATUS_RPS BIT(8) +/* Receive Buffer Unavailable */ +#define NPCM_DMA_STATUS_RU BIT(7) +/* Receive Interrupt */ +#define NPCM_DMA_STATUS_RI BIT(6) +/* Transmit Underflow */ +#define NPCM_DMA_STATUS_UNF BIT(5) +/* Receive Overflow */ +#define NPCM_DMA_STATUS_OVF BIT(4) +/* Transmit Jabber Timeout */ +#define NPCM_DMA_STATUS_TJT BIT(3) +/* Transmit Buffer Unavailable */ +#define NPCM_DMA_STATUS_TU BIT(2) +/* Transmit Process Stopped */ +#define NPCM_DMA_STATUS_TPS BIT(1) +/* Transmit Interrupt */ +#define NPCM_DMA_STATUS_TI BIT(0) + +/* Normal Interrupt Summary */ +#define NPCM_DMA_STATUS_NIS BIT(16) +/* Interrupts enabled by NIE */ +#define NPCM_DMA_STATUS_NIS_BITS (NPCM_DMA_STATUS_TI | \ + NPCM_DMA_STATUS_TU | \ + NPCM_DMA_STATUS_RI | \ + NPCM_DMA_STATUS_ERI) +/* Abnormal Interrupt Summary */ +#define NPCM_DMA_STATUS_AIS BIT(15) +/* Interrupts enabled by AIE */ +#define NPCM_DMA_STATUS_AIS_BITS (NPCM_DMA_STATUS_TPS | \ + NPCM_DMA_STATUS_TJT | \ + NPCM_DMA_STATUS_OVF | \ + NPCM_DMA_STATUS_UNF | \ + NPCM_DMA_STATUS_RU | \ + NPCM_DMA_STATUS_RPS | \ + NPCM_DMA_STATUS_RWT | \ + NPCM_DMA_STATUS_ETI | \ + NPCM_DMA_STATUS_FBI) + +/* Early Receive Interrupt Enable */ +#define NPCM_DMA_INTR_ENAB_ERE BIT(14) +/* Fatal Bus Error Interrupt Enable */ +#define NPCM_DMA_INTR_ENAB_FBE BIT(13) +/* Early transmit Interrupt Enable */ +#define NPCM_DMA_INTR_ENAB_ETE BIT(10) +/* Receive Watchdog Timout Enable */ +#define NPCM_DMA_INTR_ENAB_RWE BIT(9) +/* Receive Process Stopped Enable */ +#define NPCM_DMA_INTR_ENAB_RSE BIT(8) +/* Receive Buffer Unavailable Enable */ +#define NPCM_DMA_INTR_ENAB_RUE BIT(7) +/* Receive Interrupt Enable */ +#define NPCM_DMA_INTR_ENAB_RIE BIT(6) +/* Transmit Underflow Enable */ +#define NPCM_DMA_INTR_ENAB_UNE BIT(5) +/* Receive Overflow Enable */ +#define NPCM_DMA_INTR_ENAB_OVE BIT(4) +/* Transmit Jabber Timeout Enable */ +#define NPCM_DMA_INTR_ENAB_TJE BIT(3) +/* Transmit Buffer Unavailable Enable */ +#define NPCM_DMA_INTR_ENAB_TUE BIT(2) +/* Transmit Process Stopped Enable */ +#define NPCM_DMA_INTR_ENAB_TSE BIT(1) +/* Transmit Interrupt Enable */ +#define NPCM_DMA_INTR_ENAB_TIE BIT(0) + +/* Normal Interrupt Summary Enable */ +#define NPCM_DMA_INTR_ENAB_NIE BIT(16) +/* Interrupts enabled by NIE Enable */ +#define NPCM_DMA_INTR_ENAB_NIE_BITS (NPCM_DMA_INTR_ENAB_TIE | \ + NPCM_DMA_INTR_ENAB_TUE | \ + NPCM_DMA_INTR_ENAB_RIE | \ + NPCM_DMA_INTR_ENAB_ERE) +/* Abnormal Interrupt Summary Enable */ +#define NPCM_DMA_INTR_ENAB_AIE BIT(15) +/* Interrupts enabled by AIE Enable */ +#define NPCM_DMA_INTR_ENAB_AIE_BITS (NPCM_DMA_INTR_ENAB_TSE | \ + NPCM_DMA_INTR_ENAB_TJE | \ + NPCM_DMA_INTR_ENAB_OVE | \ + NPCM_DMA_INTR_ENAB_UNE | \ + NPCM_DMA_INTR_ENAB_RUE | \ + NPCM_DMA_INTR_ENAB_RSE | \ + NPCM_DMA_INTR_ENAB_RWE | \ + NPCM_DMA_INTR_ENAB_ETE | \ + NPCM_DMA_INTR_ENAB_FBE) + +/* Flushing Disabled */ +#define NPCM_DMA_CONTROL_FLUSH_MASK BIT(24) +/* Start/stop Transmit */ +#define NPCM_DMA_CONTROL_START_STOP_TX BIT(13) +/* Start/stop Receive */ +#define NPCM_DMA_CONTROL_START_STOP_RX BIT(1) +/* Next receive descriptor start address */ +#define NPCM_DMA_HOST_RX_DESC_MASK(word) ((uint32_t) (word) & ~3u) +/* Next transmit descriptor start address */ +#define NPCM_DMA_HOST_TX_DESC_MASK(word) ((uint32_t) (word) & ~3u) + +/* Receive enable */ +#define NPCM_GMAC_MAC_CONFIG_RX_EN BIT(2) +/* Transmit enable */ +#define NPCM_GMAC_MAC_CONFIG_TX_EN BIT(3) + +/* Frame Receive All */ +#define NPCM_GMAC_FRAME_FILTER_REC_ALL_MASK BIT(31) +/* Frame HPF Filter*/ +#define NPCM_GMAC_FRAME_FILTER_HPF_MASK BIT(10) +/* Frame SAF Filter*/ +#define NPCM_GMAC_FRAME_FILTER_SAF_MASK BIT(9) +/* Frame SAIF Filter*/ +#define NPCM_GMAC_FRAME_FILTER_SAIF_MASK BIT(8) +/* Frame PCF Filter*/ +#define NPCM_GMAC_FRAME_FILTER_PCF_MASK BIT(word) extract32((word), 6, 2) +/* Frame DBF Filter*/ +#define NPCM_GMAC_FRAME_FILTER_DBF_MASK BIT(5) +/* Frame PM Filter*/ +#define NPCM_GMAC_FRAME_FILTER_PM_MASK BIT(4) +/* Frame DAIF Filter*/ +#define NPCM_GMAC_FRAME_FILTER_DAIF_MASK BIT(3) +/* Frame HMC Filter*/ +#define NPCM_GMAC_FRAME_FILTER_HMC_MASK BIT(2) +/* Frame HUC Filter*/ +#define NPCM_GMAC_FRAME_FILTER_HUC_MASK BIT(1) +/* Frame PR Filter*/ +#define NPCM_GMAC_FRAME_FILTER_PR_MASK BIT(0) + +#endif /* NPCM_GMAC_H */ \ No newline at end of file diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c index 30d27e8dcc..84511fd915 100644 --- a/tests/qtest/npcm_gmac-test.c +++ b/tests/qtest/npcm_gmac-test.c @@ -154,7 +154,7 @@ static void test_init(gconstpointer test_data) CHECK_REG32(NPCM_GMAC_MII_DATA, 0); CHECK_REG32(NPCM_GMAC_FLOW_CTRL, 0); CHECK_REG32(NPCM_GMAC_VLAN_FLAG, 0); - CHECK_REG32(NPCM_GMAC_VERSION, 0x00001037); + CHECK_REG32(NPCM_GMAC_VERSION, 0x00001032); CHECK_REG32(NPCM_GMAC_WAKEUP_FILTER, 0); CHECK_REG32(NPCM_GMAC_PMT, 0); CHECK_REG32(NPCM_GMAC_LPI_CTRL, 0); --=20 2.42.0.459.ge4e396fd5e-goog From nobody Sat May 18 22:31:25 2024 Delivered-To: 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jasonwang@redhat.com, Avi.Fishman@nuvoton.com, Nabih Estefan Diaz Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::114a; envelope-from=3KOEJZQwKCkEqdelkhvwhidqjrrjoh.frpthpx-ghyhoqrqjqx.ruj@flex--nabihestefan.bounces.google.com; helo=mail-yw1-x114a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 19 Sep 2023 16:04:51 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1695154037701100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nabih Estefan Diaz - Implementation of Receive function for packets - Implementation for reading and writing from and to descriptors in memory for Rx NOTE: At this point in development we believe this function is working as intended, and the kernel supports these findings, but we need the Transmit function to work before we upload Signed-off-by: Nabih Estefan Diaz hw/net: npcm_gmac Flush queued packets when starting RX When RX starts, we need to flush the queued packets so that they can be received by the GMAC device. Without this it won't work with TAP NIC device. Signed-off-by: Hao Wu hw/net: Handle RX desc full in NPCM GMAC When RX descriptor list is full, it returns a DMA_STATUS for software to ha= ndle it. But there's no way to indicate the software ha handled all RX desc= riptors and the whole pipeline stalls. We do something similar to NPCM7XX EMC to handle this case. 1. Return packet size when RX descriptor is full, effectively dropping thes= e packets in such a case. 2. When software clears RX descriptor full bit, continue receiving further = packets by flushing QEMU packet queue. Signed-off-by: Hao Wu hw/net: Receive and drop packets when descriptors are full in GMAC Effectively this allows QEMU to receive and drop incoming packets when RX descriptors are full. Similar to EMC, this lets GMAC to drop packets faster, especially during bootup sequence. Signed-off-by: Hao Wu --- hw/net/npcm_gmac.c | 353 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 324 insertions(+), 29 deletions(-) diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm_gmac.c index 6f8109e0ee..67f123e3c4 100644 --- a/hw/net/npcm_gmac.c +++ b/hw/net/npcm_gmac.c @@ -23,7 +23,11 @@ #include "hw/registerfields.h" #include "hw/net/mii.h" #include "hw/net/npcm_gmac.h" +#include "linux/if_ether.h" #include "migration/vmstate.h" +#include "net/checksum.h" +#include "net/net.h" +#include "qemu/cutils.h" #include "qemu/log.h" #include "qemu/units.h" #include "sysemu/dma.h" @@ -91,7 +95,6 @@ REG32(NPCM_GMAC_PTP_TTSR, 0x71c) #define NPCM_DMA_BUS_MODE_SWR BIT(0) =20 static const uint32_t npcm_gmac_cold_reset_values[NPCM_GMAC_NR_REGS] =3D { - /* Reduce version to 3.2 so that the kernel can enable interrupt. */ [R_NPCM_GMAC_VERSION] =3D 0x00001032, [R_NPCM_GMAC_TIMER_CTRL] =3D 0x03e80000, [R_NPCM_GMAC_MAC0_ADDR_HI] =3D 0x8000ffff, @@ -146,6 +149,17 @@ static void gmac_phy_set_link(NPCMGMACState *s, bool a= ctive) =20 static bool gmac_can_receive(NetClientState *nc) { + NPCMGMACState *gmac =3D NPCM_GMAC(qemu_get_nic_opaque(nc)); + + /* If GMAC receive is disabled. */ + if (!(gmac->regs[R_NPCM_GMAC_MAC_CONFIG] & NPCM_GMAC_MAC_CONFIG_RX_EN)= ) { + return false; + } + + /* If GMAC DMA RX is stopped. */ + if (!(gmac->regs[R_NPCM_DMA_CONTROL] & NPCM_DMA_CONTROL_START_STOP_RX)= ) { + return false; + } return true; } =20 @@ -191,11 +205,285 @@ static void gmac_update_irq(NPCMGMACState *gmac) qemu_set_irq(gmac->irq, level); } =20 -static ssize_t gmac_receive(NetClientState *nc, const uint8_t *buf, size_t= len) +static int gmac_read_rx_desc(dma_addr_t addr, struct NPCMGMACRxDesc *desc) { - /* Placeholder */ + if (dma_memory_read(&address_space_memory, addr, desc, + sizeof(*desc), MEMTXATTRS_UNSPECIFIED)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x= %" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } + desc->rdes0 =3D le32_to_cpu(desc->rdes0); + desc->rdes1 =3D le32_to_cpu(desc->rdes1); + desc->rdes2 =3D le32_to_cpu(desc->rdes2); + desc->rdes3 =3D le32_to_cpu(desc->rdes3); + return 0; +} + +static int gmac_write_rx_desc(dma_addr_t addr, struct NPCMGMACRxDesc *desc) +{ + struct NPCMGMACRxDesc le_desc; + le_desc.rdes0 =3D cpu_to_le32(desc->rdes0); + le_desc.rdes1 =3D cpu_to_le32(desc->rdes1); + le_desc.rdes2 =3D cpu_to_le32(desc->rdes2); + le_desc.rdes3 =3D cpu_to_le32(desc->rdes3); + if (dma_memory_write(&address_space_memory, addr, &le_desc, + sizeof(le_desc), MEMTXATTRS_UNSPECIFIED)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0= x%" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } + return 0; +} + +static int gmac_read_tx_desc(dma_addr_t addr, struct NPCMGMACTxDesc *desc) +{ + if (dma_memory_read(&address_space_memory, addr, desc, + sizeof(*desc), MEMTXATTRS_UNSPECIFIED)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x= %" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } + desc->tdes0 =3D le32_to_cpu(desc->tdes0); + desc->tdes1 =3D le32_to_cpu(desc->tdes1); + desc->tdes2 =3D le32_to_cpu(desc->tdes2); + desc->tdes3 =3D le32_to_cpu(desc->tdes3); + return 0; +} + +static int gmac_write_tx_desc(dma_addr_t addr, struct NPCMGMACTxDesc *desc) +{ + struct NPCMGMACTxDesc le_desc; + le_desc.tdes0 =3D cpu_to_le32(desc->tdes0); + le_desc.tdes1 =3D cpu_to_le32(desc->tdes1); + le_desc.tdes2 =3D cpu_to_le32(desc->tdes2); + le_desc.tdes3 =3D cpu_to_le32(desc->tdes3); + if (dma_memory_write(&address_space_memory, addr, &le_desc, + sizeof(le_desc), MEMTXATTRS_UNSPECIFIED)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0= x%" + HWADDR_PRIx "\n", __func__, addr); + return -1; + } return 0; } +static int gmac_rx_transfer_frame_to_buffer(uint32_t rx_buf_len, + uint32_t *left_frame, + uint32_t rx_buf_addr, + bool *eof_transferred, + const uint8_t *frame_ptr, + uint16_t *transferred) +{ + uint32_t to_transfer; + /* + * Check that buffer is bigger than the frame being transfered + * If bigger then transfer only whats left of frame + * Else, fill frame with all the content possible + */ + if (rx_buf_len >=3D *left_frame) { + to_transfer =3D *left_frame; + *eof_transferred =3D true; + } else { + to_transfer =3D rx_buf_len; + } + + /* write frame part to memory */ + if (dma_memory_write(&address_space_memory, (uint64_t) rx_buf_addr, + frame_ptr, to_transfer, MEMTXATTRS_UNSPECIFIED)) + { + return -1; + } + + /* update frame pointer and size of whats left of frame */ + frame_ptr +=3D to_transfer; + *left_frame -=3D to_transfer; + *transferred +=3D to_transfer; + + return 0; +} + +static void gmac_dma_set_state(NPCMGMACState *gmac, int shift, uint32_t st= ate) +{ + gmac->regs[R_NPCM_DMA_STATUS] =3D deposit32(gmac->regs[R_NPCM_DMA_STAT= US], + shift, 3, state); +} + +static ssize_t gmac_receive(NetClientState *nc, const uint8_t *buf, size_t= len) +{ + /* + * Comments have steps that relate to the + * receiving process steps in pg 386 + */ + NPCMGMACState *gmac =3D NPCM_GMAC(qemu_get_nic_opaque(nc)); + uint32_t left_frame =3D len; + const uint8_t *frame_ptr =3D buf; + uint32_t desc_addr; + uint32_t rx_buf_len, rx_buf_addr; + struct NPCMGMACRxDesc rx_desc; + uint16_t transferred =3D 0; + bool eof_transferred =3D false; + + trace_npcm_gmac_packet_receive(DEVICE(gmac)->canonical_path, len); + if (!gmac_can_receive(nc)) { + qemu_log_mask(LOG_GUEST_ERROR, "GMAC Currently is not able for Rx"= ); + return -1; + } + if (!gmac->regs[R_NPCM_DMA_HOST_RX_DESC]) { + gmac->regs[R_NPCM_DMA_HOST_RX_DESC] =3D + NPCM_DMA_HOST_RX_DESC_MASK(gmac->regs[R_NPCM_DMA_RX_BASE_ADDR]= ); + } + desc_addr =3D NPCM_DMA_HOST_RX_DESC_MASK(gmac->regs[R_NPCM_DMA_HOST_RX= _DESC]); + + /* step 1 */ + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT, + NPCM_DMA_STATUS_RX_RUNNING_FETCHING_STATE); + trace_npcm_gmac_packet_desc_read(DEVICE(gmac)->canonical_path, desc_ad= dr); + if (gmac_read_rx_desc(desc_addr, &rx_desc)) { + qemu_log_mask(LOG_GUEST_ERROR, "RX Descriptor @ 0x%x cant be read\= n", + desc_addr); + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT, + NPCM_DMA_STATUS_RX_SUSPENDED_STATE); + return -1; + } + + /* step 2 */ + if (!(rx_desc.rdes0 & RX_DESC_RDES0_OWN)) { + qemu_log_mask(LOG_GUEST_ERROR, + "RX Descriptor @ 0x%x is owned by software\n", + desc_addr); + gmac->regs[R_NPCM_DMA_STATUS] |=3D NPCM_DMA_STATUS_RU; + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT, + NPCM_DMA_STATUS_RX_SUSPENDED_STATE); + gmac_update_irq(gmac); + return len; + } + /* step 3 */ + /* + * TODO -- + * Implement all frame filtering and processing (with its own interrup= ts) + */ + trace_npcm_gmac_debug_desc_data(DEVICE(gmac)->canonical_path, &rx_desc, + rx_desc.rdes0, rx_desc.rdes1, rx_desc.= rdes2, + rx_desc.rdes3); + /* Set FS in first descriptor */ + rx_desc.rdes0 |=3D RX_DESC_RDES0_FIRST_DESC_MASK; + + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT, + NPCM_DMA_STATUS_RX_RUNNING_TRANSFERRING_STATE); + + /* Pad the frame with FCS as the kernel driver will strip it away. */ + left_frame +=3D ETH_FCS_LEN; + + /* repeat while we still have frame to transfer to memory */ + while (!eof_transferred) { + /* Return descriptor no matter what happens */ + rx_desc.rdes0 &=3D ~RX_DESC_RDES0_OWN; + /* Set the frame to be an IPv4/IPv6 frame. */ + rx_desc.rdes0 |=3D RX_DESC_RDES0_FRM_TYPE_MASK; + + /* step 4 */ + rx_buf_len =3D RX_DESC_RDES1_BFFR1_SZ_MASK(rx_desc.rdes1); + rx_buf_addr =3D rx_desc.rdes2; + gmac->regs[R_NPCM_DMA_CUR_RX_BUF_ADDR] =3D rx_buf_addr; + gmac_rx_transfer_frame_to_buffer(rx_buf_len, &left_frame, rx_buf_a= ddr, + &eof_transferred, frame_ptr, + &transferred); + + trace_npcm_gmac_packet_receiving_buffer(DEVICE(gmac)->canonical_pa= th, + rx_buf_len, rx_buf_addr); + /* if we still have frame left and the second buffer is not chaine= d */ + if (!(rx_desc.rdes1 & RX_DESC_RDES1_SEC_ADDR_CHND_MASK) && \ + !eof_transferred) { + /* repeat process from above on buffer 2 */ + rx_buf_len =3D RX_DESC_RDES1_BFFR2_SZ_MASK(rx_desc.rdes1); + rx_buf_addr =3D rx_desc.rdes3; + gmac->regs[R_NPCM_DMA_CUR_RX_BUF_ADDR] =3D rx_buf_addr; + gmac_rx_transfer_frame_to_buffer(rx_buf_len, &left_frame, + rx_buf_addr, &eof_transferred, + frame_ptr, &transferred); + trace_npcm_gmac_packet_receiving_buffer( \ + DEVICE(gmac)->canonical_pa= th, + rx_buf_len, rx_buf_addr); + } + /* update address for descriptor */ + gmac->regs[R_NPCM_DMA_HOST_RX_DESC] =3D rx_buf_addr; + /* Return descriptor */ + rx_desc.rdes0 &=3D ~RX_DESC_RDES0_OWN; + /* Update frame length transferred */ + rx_desc.rdes0 |=3D ((uint32_t)transferred) + << RX_DESC_RDES0_FRAME_LEN_SHIFT; + trace_npcm_gmac_debug_desc_data(DEVICE(gmac)->canonical_path, &rx_= desc, + rx_desc.rdes0, rx_desc.rdes1, + rx_desc.rdes2, rx_desc.rdes3); + + /* step 5 */ + gmac_write_rx_desc(desc_addr, &rx_desc); + trace_npcm_gmac_debug_desc_data(DEVICE(gmac)->canonical_path, + &rx_desc, rx_desc.rdes0, + rx_desc.rdes1, rx_desc.rdes2, + rx_desc.rdes3); + /* read new descriptor into rx_desc if needed*/ + if (!eof_transferred) { + /* Get next descriptor address (chained or sequential) */ + if (rx_desc.rdes1 & RX_DESC_RDES1_RC_END_RING_MASK) { + desc_addr =3D gmac->regs[R_NPCM_DMA_RX_BASE_ADDR]; + } else if (rx_desc.rdes1 & RX_DESC_RDES1_SEC_ADDR_CHND_MASK) { + desc_addr =3D rx_desc.rdes3; + } else { + desc_addr +=3D sizeof(rx_desc); + } + trace_npcm_gmac_packet_desc_read(DEVICE(gmac)->canonical_path, + desc_addr); + if (gmac_read_rx_desc(desc_addr, &rx_desc)) { + qemu_log_mask(LOG_GUEST_ERROR, + "RX Descriptor @ 0x%x cant be read\n", + desc_addr); + gmac->regs[R_NPCM_DMA_STATUS] |=3D NPCM_DMA_STATUS_RU; + gmac_update_irq(gmac); + return len; + } + + /* step 6 */ + if (rx_desc.rdes0 & RX_DESC_RDES0_OWN) { + if (!(gmac->regs[R_NPCM_DMA_CONTROL] & \ + NPCM_DMA_CONTROL_FLUSH_MASK)) { + rx_desc.rdes0 |=3D RX_DESC_RDES0_DESC_ERR_MASK; + } + eof_transferred =3D true; + } + } + } + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT, + NPCM_DMA_STATUS_RX_RUNNING_CLOSING_STATE); + + rx_desc.rdes0 |=3D RX_DESC_RDES0_LAST_DESC_MASK; + if (!(rx_desc.rdes1 & RX_DESC_RDES1_DIS_INTR_COMP_MASK)) { + gmac->regs[R_NPCM_DMA_STATUS] |=3D NPCM_DMA_STATUS_RI; + gmac_update_irq(gmac); + } + trace_npcm_gmac_debug_desc_data(DEVICE(gmac)->canonical_path, &rx_desc, + rx_desc.rdes0, rx_desc.rdes1, rx_desc.= rdes2, + rx_desc.rdes3); + + /* step 8 */ + gmac->regs[R_NPCM_DMA_CONTROL] |=3D NPCM_DMA_CONTROL_FLUSH_MASK; + + /* step 9 */ + trace_npcm_gmac_packet_received(DEVICE(gmac)->canonical_path, left_fra= me); + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT, + NPCM_DMA_STATUS_RX_RUNNING_WAITING_STATE); + gmac_write_rx_desc(desc_addr, &rx_desc); + + /* Get next descriptor address (chained or sequential) */ + if (rx_desc.rdes1 & RX_DESC_RDES1_RC_END_RING_MASK) { + desc_addr =3D gmac->regs[R_NPCM_DMA_RX_BASE_ADDR]; + } else if (rx_desc.rdes1 & RX_DESC_RDES1_SEC_ADDR_CHND_MASK) { + desc_addr =3D rx_desc.rdes3; + } else { + desc_addr +=3D sizeof(rx_desc); + } + gmac->regs[R_NPCM_DMA_HOST_RX_DESC] =3D desc_addr; + return len; +} static void gmac_cleanup(NetClientState *nc) { /* Nothing to do yet. */ @@ -281,7 +569,6 @@ static void npcm_gmac_write(void *opaque, hwaddr offset, uint64_t v, unsigned size) { NPCMGMACState *gmac =3D opaque; - uint32_t prev; =20 trace_npcm_gmac_reg_write(DEVICE(gmac)->canonical_path, offset, v); =20 @@ -305,22 +592,7 @@ static void npcm_gmac_write(void *opaque, hwaddr offse= t, break; =20 case A_NPCM_GMAC_MAC_CONFIG: - prev =3D gmac->regs[offset / sizeof(uint32_t)]; gmac->regs[offset / sizeof(uint32_t)] =3D v; - - /* If transmit is being enabled for first time, update desc addr */ - if (~(prev & NPCM_GMAC_MAC_CONFIG_TX_EN) & - (v & NPCM_GMAC_MAC_CONFIG_TX_EN)) { - gmac->regs[R_NPCM_DMA_HOST_TX_DESC] =3D - gmac->regs[R_NPCM_DMA_TX_BASE_ADDR]; - } - - /* If receive is being enabled for first time, update desc addr */ - if (~(prev & NPCM_GMAC_MAC_CONFIG_RX_EN) & - (v & NPCM_GMAC_MAC_CONFIG_RX_EN)) { - gmac->regs[R_NPCM_DMA_HOST_RX_DESC] =3D - gmac->regs[R_NPCM_DMA_RX_BASE_ADDR]; - } break; =20 case A_NPCM_GMAC_MII_ADDR: @@ -362,6 +634,31 @@ static void npcm_gmac_write(void *opaque, hwaddr offse= t, =20 case A_NPCM_DMA_RCV_POLL_DEMAND: /* We dont actually care about the value */ + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT, + NPCM_DMA_STATUS_RX_RUNNING_WAITING_STATE); + break; + + case A_NPCM_DMA_XMT_POLL_DEMAND: + /* We dont actually care about the value */ + gmac_try_send_next_packet(gmac); + break; + + case A_NPCM_DMA_CONTROL: + gmac->regs[offset / sizeof(uint32_t)] =3D v; + if (v & NPCM_DMA_CONTROL_START_STOP_TX) { + gmac_try_send_next_packet(gmac); + } else { + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIF= T, + NPCM_DMA_STATUS_TX_STOPPED_STATE); + } + if (v & NPCM_DMA_CONTROL_START_STOP_RX) { + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIF= T, + NPCM_DMA_STATUS_RX_RUNNING_WAITING_STATE); + qemu_flush_queued_packets(qemu_get_queue(gmac->nic)); + } else { + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIF= T, + NPCM_DMA_STATUS_RX_STOPPED_STATE); + } break; =20 case A_NPCM_DMA_STATUS: @@ -371,16 +668,14 @@ static void npcm_gmac_write(void *opaque, hwaddr offs= et, "%s: Write of read-only bits of reg: offset: 0x%= 04" HWADDR_PRIx ", value: 0x%04" PRIx64 "\n", DEVICE(gmac)->canonical_path, offset, v); - } else { - /* for W1c bits, implement W1C */ - gmac->regs[offset / sizeof(uint32_t)] &=3D - ~NPCM_DMA_STATUS_W1C_MASK(v); - if (v & NPCM_DMA_STATUS_NIS_BITS) { - gmac->regs[offset / sizeof(uint32_t)] &=3D ~NPCM_DMA_STATU= S_NIS; - } - if (v & NPCM_DMA_STATUS_AIS_BITS) { - gmac->regs[offset / sizeof(uint32_t)] &=3D ~NPCM_DMA_STATU= S_AIS; - } + } + /* for W1C bits, implement W1C */ + gmac->regs[offset / sizeof(uint32_t)] &=3D ~NPCM_DMA_STATUS_W1C_MA= SK(v); + if (v & NPCM_DMA_STATUS_RU) { + /* Clearing RU bit indicates descriptor is owned by DMA again.= */ + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIF= T, + NPCM_DMA_STATUS_RX_RUNNING_WAITING_STATE); + qemu_flush_queued_packets(qemu_get_queue(gmac->nic)); } break; =20 --=20 2.42.0.459.ge4e396fd5e-goog From nobody Sat May 18 22:31:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1695153920; cv=none; d=zohomail.com; s=zohoarc; b=HrHQICxyYh3K88z0gtygTpdvEyYIupG9w+CnVasRN5eRL6YYeveVCh7JPjOIiZ18o88AzdZntdeY55h07QJvaqG8Ltct0VWNO3yPUCAc33y1BxmLy875FispmQKyaLe6X/9p4MsV0RJQdbY6wAUVNz9evtCkTic6gTvaJCNgGuQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695153920; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TR6lgcRTcQaFiEy+trwn4gcpOsjR1yJslZ49WXNdWvA=; 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Tue, 19 Sep 2023 10:58:02 -0700 (PDT) Date: Tue, 19 Sep 2023 17:57:23 +0000 In-Reply-To: <20230919175725.3413108-1-nabihestefan@google.com> Mime-Version: 1.0 References: <20230919175725.3413108-1-nabihestefan@google.com> X-Mailer: git-send-email 2.42.0.459.ge4e396fd5e-goog Message-ID: <20230919175725.3413108-13-nabihestefan@google.com> Subject: [PATCH 12/14] hw/net: GMAC Tx Implementation From: Nabih Estefan To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kfting@nuvoton.com, wuhaotsh@google.com, jasonwang@redhat.com, Avi.Fishman@nuvoton.com, Nabih Estefan Diaz Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::b49; envelope-from=3KuEJZQwKCkMsfgnmjxyjkfslttlqj.htrvjrz-ij0jqstslsz.twl@flex--nabihestefan.bounces.google.com; helo=mail-yb1-xb49.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 19 Sep 2023 16:04:51 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1695153923212100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nabih Estefan Diaz - Implementation of Transmit function for packets - Implementation for reading and writing from and to descriptors in memory for Tx NOTE: This function implements the steps detailed in the datasheet for transmitting messages from the GMAC. Signed-off-by: Nabih Estefan Diaz --- hw/net/npcm_gmac.c | 150 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm_gmac.c index 67f123e3c4..c457b11e4d 100644 --- a/hw/net/npcm_gmac.c +++ b/hw/net/npcm_gmac.c @@ -266,6 +266,7 @@ static int gmac_write_tx_desc(dma_addr_t addr, struct N= PCMGMACTxDesc *desc) } return 0; } + static int gmac_rx_transfer_frame_to_buffer(uint32_t rx_buf_len, uint32_t *left_frame, uint32_t rx_buf_addr, @@ -484,6 +485,155 @@ static ssize_t gmac_receive(NetClientState *nc, const= uint8_t *buf, size_t len) gmac->regs[R_NPCM_DMA_HOST_RX_DESC] =3D desc_addr; return len; } + +static int gmac_tx_get_csum(uint32_t tdes1) +{ + uint32_t mask =3D TX_DESC_TDES1_CHKSM_INS_CTRL_MASK(tdes1); + int csum =3D 0; + + if (likely(mask > 0)) { + csum |=3D CSUM_IP; + } + if (likely(mask > 1)) { + csum |=3D CSUM_TCP | CSUM_UDP; + } + + return csum; +} + +static void gmac_try_send_next_packet(NPCMGMACState *gmac) +{ + /* + * Comments about steps refer to steps for + * transmitting in page 384 of datasheet + */ + uint16_t tx_buffer_size =3D 2048; + g_autofree uint8_t *tx_send_buffer =3D g_malloc(tx_buffer_size); + uint32_t desc_addr; + struct NPCMGMACTxDesc tx_desc; + uint32_t tx_buf_addr, tx_buf_len; + uint16_t length =3D 0; + uint8_t *buf =3D tx_send_buffer; + uint32_t prev_buf_size =3D 0; + int csum =3D 0; + + /* steps 1&2 */ + if (!gmac->regs[R_NPCM_DMA_HOST_TX_DESC]) { + gmac->regs[R_NPCM_DMA_HOST_TX_DESC] =3D + NPCM_DMA_HOST_TX_DESC_MASK(gmac->regs[R_NPCM_DMA_TX_BASE_ADDR]= ); + } + desc_addr =3D gmac->regs[R_NPCM_DMA_HOST_TX_DESC]; + + while (true) { + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT, + NPCM_DMA_STATUS_TX_RUNNING_FETCHING_STATE); + trace_npcm_gmac_packet_transmit(DEVICE(gmac)->canonical_path, leng= th); + if (gmac_read_tx_desc(desc_addr, &tx_desc)) { + qemu_log_mask(LOG_GUEST_ERROR, "TX Descriptor @ 0x%x can't be = read\n", + desc_addr); + return; + } + /* step 3 */ + + trace_npcm_gmac_packet_desc_read(DEVICE(gmac)->canonical_path, des= c_addr); + trace_npcm_gmac_debug_desc_data(DEVICE(gmac)->canonical_path, &tx_= desc, + tx_desc.tdes0, tx_desc.tdes1, tx_desc.tdes2, tx_desc.tdes3); + + /* 1 =3D DMA Owned, 0 =3D Software Owned */ + if (!(tx_desc.tdes0 & TX_DESC_TDES0_OWN)) { + qemu_log_mask(LOG_GUEST_ERROR, + "TX Descriptor @ 0x%x is owned by software\n", + desc_addr); + gmac->regs[R_NPCM_DMA_STATUS] |=3D NPCM_DMA_STATUS_TU; + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIF= T, + NPCM_DMA_STATUS_TX_SUSPENDED_STATE); + gmac_update_irq(gmac); + return; + } + + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT, + NPCM_DMA_STATUS_TX_RUNNING_READ_STATE); + /* Give the descriptor back regardless of what happens. */ + tx_desc.tdes0 &=3D ~TX_DESC_TDES0_OWN; + + if (tx_desc.tdes1 & TX_DESC_TDES1_FIRST_SEG_MASK) { + csum =3D gmac_tx_get_csum(tx_desc.tdes1); + } + + /* step 4 */ + tx_buf_addr =3D tx_desc.tdes2; + gmac->regs[R_NPCM_DMA_CUR_TX_BUF_ADDR] =3D tx_buf_addr; + tx_buf_len =3D TX_DESC_TDES1_BFFR1_SZ_MASK(tx_desc.tdes1); + buf =3D &tx_send_buffer[prev_buf_size]; + + if ((prev_buf_size + tx_buf_len) > sizeof(buf)) { + tx_buffer_size =3D prev_buf_size + tx_buf_len; + tx_send_buffer =3D g_realloc(tx_send_buffer, tx_buffer_size); + buf =3D &tx_send_buffer[prev_buf_size]; + } + + /* step 5 */ + if (dma_memory_read(&address_space_memory, tx_buf_addr, buf, + tx_buf_len, MEMTXATTRS_UNSPECIFIED)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read packet @ 0x= %x\n", + __func__, tx_buf_addr); + return; + } + length +=3D tx_buf_len; + prev_buf_size +=3D tx_buf_len; + + /* If not chained we'll have a second buffer. */ + if (!(tx_desc.tdes1 & TX_DESC_TDES1_SEC_ADDR_CHND_MASK)) { + tx_buf_addr =3D tx_desc.tdes3; + gmac->regs[R_NPCM_DMA_CUR_TX_BUF_ADDR] =3D tx_buf_addr; + tx_buf_len =3D TX_DESC_TDES1_BFFR2_SZ_MASK(tx_desc.tdes1); + buf =3D &tx_send_buffer[prev_buf_size]; + + if ((prev_buf_size + tx_buf_len) > sizeof(buf)) { + tx_buffer_size =3D prev_buf_size + tx_buf_len; + tx_send_buffer =3D g_realloc(tx_send_buffer, tx_buffer_siz= e); + buf =3D &tx_send_buffer[prev_buf_size]; + } + + if (dma_memory_read(&address_space_memory, tx_buf_addr, buf, + tx_buf_len, MEMTXATTRS_UNSPECIFIED)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Failed to read packet @ 0x%x\n", + __func__, tx_buf_addr); + return; + } + length +=3D tx_buf_len; + prev_buf_size +=3D tx_buf_len; + } + if (tx_desc.tdes1 & TX_DESC_TDES1_LAST_SEG_MASK) { + net_checksum_calculate(tx_send_buffer, length, csum); + qemu_send_packet(qemu_get_queue(gmac->nic), tx_send_buffer, le= ngth); + trace_npcm_gmac_packet_sent(DEVICE(gmac)->canonical_path, leng= th); + buf =3D tx_send_buffer; + length =3D 0; + } + + /* step 6 */ + gmac_dma_set_state(gmac, NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT, + NPCM_DMA_STATUS_TX_RUNNING_CLOSING_STATE); + gmac_write_tx_desc(desc_addr, &tx_desc); + if (tx_desc.tdes1 & TX_DESC_TDES1_TX_END_RING_MASK) { + desc_addr =3D gmac->regs[R_NPCM_DMA_TX_BASE_ADDR]; + } else if (tx_desc.tdes1 & TX_DESC_TDES1_SEC_ADDR_CHND_MASK) { + desc_addr =3D tx_desc.tdes3; + } else { + desc_addr +=3D sizeof(tx_desc); + } + gmac->regs[R_NPCM_DMA_HOST_TX_DESC] =3D desc_addr; + + /* step 7 */ + if (tx_desc.tdes1 & TX_DESC_TDES1_INTERR_COMP_MASK) { + gmac->regs[R_NPCM_DMA_STATUS] |=3D NPCM_DMA_STATUS_TI; + gmac_update_irq(gmac); + } + } +} + static void gmac_cleanup(NetClientState *nc) { /* Nothing to do yet. */ --=20 2.42.0.459.ge4e396fd5e-goog From nobody Sat May 18 22:31:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1695153956; cv=none; d=zohomail.com; s=zohoarc; b=oC+vuMcpox14As5R9CR+vrqdjpCrFg2Pg89G3zg9HNxttyJ2EQlCWMY69i70lC9uZp0ag89wLN917p90mQ75nOLfGVHsfnfKtPJ1CTVV7Q9LPCuNViGL1veVvbMrHFONgXL3yPZVkevIZwbKZu6V35xP4I7sx9hjcJzd5jI4NXM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695153956; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WDRWOhh3VW0C6dXpPJT1aSezqw+qmGqchWiEjYKyhCA=; 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Tue, 19 Sep 2023 10:58:03 -0700 (PDT) Date: Tue, 19 Sep 2023 17:57:24 +0000 In-Reply-To: <20230919175725.3413108-1-nabihestefan@google.com> Mime-Version: 1.0 References: <20230919175725.3413108-1-nabihestefan@google.com> X-Mailer: git-send-email 2.42.0.459.ge4e396fd5e-goog Message-ID: <20230919175725.3413108-14-nabihestefan@google.com> Subject: [PATCH 13/14] hw/arm: Connect to chardev backend for NPCM8XX From: Nabih Estefan To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kfting@nuvoton.com, wuhaotsh@google.com, jasonwang@redhat.com, Avi.Fishman@nuvoton.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::b4a; envelope-from=3K-EJZQwKCkQtghonkyzklgtmuumrk.iuswks0-jk1krtutmt0.uxm@flex--nabihestefan.bounces.google.com; helo=mail-yb1-xb4a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 19 Sep 2023 16:04:51 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1695153957189100002 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hao Wu As NPCM8XX SoCs have 2 mailboxes, we can't use -global to connect the mailboxes to their specific chardevs. So we add the search for chardev code here, similar to what we did for the GMAC devices. Signed-off-by: Hao Wu --- hw/arm/npcm8xx.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c index a9eb2b894c..8859cb274d 100644 --- a/hw/arm/npcm8xx.c +++ b/hw/arm/npcm8xx.c @@ -16,6 +16,7 @@ =20 #include "qemu/osdep.h" =20 +#include "chardev/char.h" #include "hw/arm/boot.h" #include "hw/arm/npcm8xx.h" #include "hw/char/serial.h" @@ -25,7 +26,9 @@ #include "hw/qdev-clock.h" #include "hw/qdev-properties.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "qemu/units.h" +#include "qom/object.h" #include "sysemu/sysemu.h" =20 #define ARM_PHYS_TIMER_PPI 30 @@ -762,6 +765,14 @@ static void npcm8xx_realize(DeviceState *dev, Error **= errp) =20 /* PCI Mailbox. Cannot fail */ for (i =3D 0; i < ARRAY_SIZE(s->pci_mbox); i++) { + g_autofree char *char_name =3D g_strdup_printf("pci%d", i); + Chardev *chardev =3D qemu_chr_find(char_name); + + if (chardev) { + qdev_prop_set_chr(DEVICE(&s->pci_mbox[i]), "chardev", chardev); + } else { + warn_report("PCI Mailbox %d does not have a chardev backend.",= i); + } sysbus_realize(SYS_BUS_DEVICE(&s->pci_mbox[i]), &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(&s->pci_mbox[i]), 0, npcm8xx_pci_mbox_addr[i]); --=20 2.42.0.459.ge4e396fd5e-goog From nobody Sat May 18 22:31:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1695154120; cv=none; d=zohomail.com; s=zohoarc; b=l0kwuhKfE+uUCikNll5wKuVCpp6gUtcGbEoCC0QST/A834npUfQA4biRwTdFpMkBoY9V0Bw6dUx3W/JUUPhAdRgzXLEPfa6tiCDeay4A3y1R+nPfPRBFQWTB04dviCY6YUs6PxpdMg4ZwsC3PpT6fB+MhLtb9cQwfH3UQH+U1pY= ARC-Message-Signature: i=1; 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Tue, 19 Sep 2023 10:58:05 -0700 (PDT) Date: Tue, 19 Sep 2023 17:57:25 +0000 In-Reply-To: <20230919175725.3413108-1-nabihestefan@google.com> Mime-Version: 1.0 References: <20230919175725.3413108-1-nabihestefan@google.com> X-Mailer: git-send-email 2.42.0.459.ge4e396fd5e-goog Message-ID: <20230919175725.3413108-15-nabihestefan@google.com> Subject: [PATCH 14/14] tests/qtest: Adding PCS Module test to GMAC Qtest From: Nabih Estefan To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kfting@nuvoton.com, wuhaotsh@google.com, jasonwang@redhat.com, Avi.Fishman@nuvoton.com, Nabih Estefan Diaz Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::b4a; envelope-from=3LeEJZQwKCkYvijqpm01mnivowwotm.kwuymu2-lm3mtvwvov2.wzo@flex--nabihestefan.bounces.google.com; helo=mail-yb1-xb4a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008, USER_IN_DEF_DKIM_WL=-7.5 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 19 Sep 2023 16:04:51 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1695154121709100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nabih Estefan Diaz - Add PCS Register check to npcm_gmac-test Signed-off-by: Nabih Estefan Diaz --- tests/qtest/npcm_gmac-test.c | 135 ++++++++++++++++++++++++++++++++++- 1 file changed, 134 insertions(+), 1 deletion(-) diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c index 84511fd915..99b914f198 100644 --- a/tests/qtest/npcm_gmac-test.c +++ b/tests/qtest/npcm_gmac-test.c @@ -20,6 +20,10 @@ /* Name of the GMAC Device */ #define TYPE_NPCM_GMAC "npcm-gmac" =20 +/* Address of the PCS Module */ +#define PCS_BASE_ADDRESS 0xf0780000 +#define NPCM_PCS_IND_AC_BA 0x1fe + typedef struct GMACModule { int irq; uint64_t base_addr; @@ -111,6 +115,62 @@ typedef enum NPCMRegister { NPCM_GMAC_PTP_STNSUR =3D 0x714, NPCM_GMAC_PTP_TAR =3D 0x718, NPCM_GMAC_PTP_TTSR =3D 0x71c, + + /* PCS Registers */ + NPCM_PCS_SR_CTL_ID1 =3D 0x3c0008, + NPCM_PCS_SR_CTL_ID2 =3D 0x3c000a, + NPCM_PCS_SR_CTL_STS =3D 0x3c0010, + + NPCM_PCS_SR_MII_CTRL =3D 0x3e0000, + NPCM_PCS_SR_MII_STS =3D 0x3e0002, + NPCM_PCS_SR_MII_DEV_ID1 =3D 0x3e0004, + NPCM_PCS_SR_MII_DEV_ID2 =3D 0x3e0006, + NPCM_PCS_SR_MII_AN_ADV =3D 0x3e0008, + NPCM_PCS_SR_MII_LP_BABL =3D 0x3e000a, + NPCM_PCS_SR_MII_AN_EXPN =3D 0x3e000c, + NPCM_PCS_SR_MII_EXT_STS =3D 0x3e001e, + + NPCM_PCS_SR_TIM_SYNC_ABL =3D 0x3e0e10, + NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR =3D 0x3e0e12, + NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR =3D 0x3e0e14, + NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR =3D 0x3e0e16, + NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR =3D 0x3e0e18, + NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR =3D 0x3e0e1a, + NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR =3D 0x3e0e1c, + NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR =3D 0x3e0e1e, + NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR =3D 0x3e0e20, + + NPCM_PCS_VR_MII_MMD_DIG_CTRL1 =3D 0x3f0000, + NPCM_PCS_VR_MII_AN_CTRL =3D 0x3f0002, + NPCM_PCS_VR_MII_AN_INTR_STS =3D 0x3f0004, + NPCM_PCS_VR_MII_TC =3D 0x3f0006, + NPCM_PCS_VR_MII_DBG_CTRL =3D 0x3f000a, + NPCM_PCS_VR_MII_EEE_MCTRL0 =3D 0x3f000c, + NPCM_PCS_VR_MII_EEE_TXTIMER =3D 0x3f0010, + NPCM_PCS_VR_MII_EEE_RXTIMER =3D 0x3f0012, + NPCM_PCS_VR_MII_LINK_TIMER_CTRL =3D 0x3f0014, + NPCM_PCS_VR_MII_EEE_MCTRL1 =3D 0x3f0016, + NPCM_PCS_VR_MII_DIG_STS =3D 0x3f0020, + NPCM_PCS_VR_MII_ICG_ERRCNT1 =3D 0x3f0022, + NPCM_PCS_VR_MII_MISC_STS =3D 0x3f0030, + NPCM_PCS_VR_MII_RX_LSTS =3D 0x3f0040, + NPCM_PCS_VR_MII_MP_TX_BSTCTRL0 =3D 0x3f0070, + NPCM_PCS_VR_MII_MP_TX_LVLCTRL0 =3D 0x3f0074, + NPCM_PCS_VR_MII_MP_TX_GENCTRL0 =3D 0x3f007a, + NPCM_PCS_VR_MII_MP_TX_GENCTRL1 =3D 0x3f007c, + NPCM_PCS_VR_MII_MP_TX_STS =3D 0x3f0090, + NPCM_PCS_VR_MII_MP_RX_GENCTRL0 =3D 0x3f00b0, + NPCM_PCS_VR_MII_MP_RX_GENCTRL1 =3D 0x3f00b2, + NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0 =3D 0x3f00ba, + NPCM_PCS_VR_MII_MP_MPLL_CTRL0 =3D 0x3f00f0, + NPCM_PCS_VR_MII_MP_MPLL_CTRL1 =3D 0x3f00f2, + NPCM_PCS_VR_MII_MP_MPLL_STS =3D 0x3f0110, + NPCM_PCS_VR_MII_MP_MISC_CTRL2 =3D 0x3f0126, + NPCM_PCS_VR_MII_MP_LVL_CTRL =3D 0x3f0130, + NPCM_PCS_VR_MII_MP_MISC_CTRL0 =3D 0x3f0132, + NPCM_PCS_VR_MII_MP_MISC_CTRL1 =3D 0x3f0134, + NPCM_PCS_VR_MII_DIG_CTRL2 =3D 0x3f01c2, + NPCM_PCS_VR_MII_DIG_ERRCNT_SEL =3D 0x3f01c4, } NPCMRegister; =20 static uint32_t gmac_read(QTestState *qts, const GMACModule *mod, @@ -119,6 +179,15 @@ static uint32_t gmac_read(QTestState *qts, const GMACM= odule *mod, return qtest_readl(qts, mod->base_addr + regno); } =20 +static uint16_t pcs_read(QTestState *qts, const GMACModule *mod, + NPCMRegister regno) +{ + uint32_t write_value =3D (regno & 0x3ffe00) >> 9; + qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value); + uint32_t read_offset =3D regno & 0x1ff; + return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset); +} + /* Check that GMAC registers are reset to default value */ static void test_init(gconstpointer test_data) { @@ -129,7 +198,12 @@ static void test_init(gconstpointer test_data) #define CHECK_REG32(regno, value) \ do { \ g_assert_cmphex(gmac_read(qts, mod, (regno)), =3D=3D, (value)); \ - } while (0) + } while (0); + +#define CHECK_REG_PCS(regno, value) \ + do { \ + g_assert_cmphex(pcs_read(qts, mod, (regno)), =3D=3D, (value)); \ + } while (0); =20 CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100); CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0); @@ -180,6 +254,65 @@ static void test_init(gconstpointer test_data) CHECK_REG32(NPCM_GMAC_PTP_TAR, 0); CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0); =20 + /* TODO Add registers PCS */ + if (mod->base_addr =3D=3D 0xf0802000) + { + CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e) + CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0) + CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000) + + CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140) + CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109) + CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e) + CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0) + CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020) + CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0) + CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0) + CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000) + + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0) + + CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400) + CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a) + CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c) + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010) + CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0) + } + qtest_quit(qts); } =20 --=20 2.42.0.459.ge4e396fd5e-goog