From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900570; cv=none; d=zohomail.com; s=zohoarc; b=K4jNAsqKdu4LhXYftawgwiirX3oYQ6BcFea2Zq/0sqN5Lnu0hcNxy7A0NbNBwypDqYe6B/TPs0/iG56886pMErZcLifxKk5ou+8fEHRVJEC2SySKp6mgfF4sbzbeCMJJGciIOI3bq3XkUPmAsPB4TRDVitSnhVJZEjwQQcQi0sM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900570; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hG4FMe9Q2no9qbt6QH7h9ZHwSIMX8Uo4/7YnZ0piG0o=; b=T0P+UExwSft5dKN+RDl3nebvVMivTw7yJkKPgiU7IcDEzGrsLgr8X2RNGzGfmPKTTYZw2YQdwwZvzIY4Ov2mIHV9O0aw2apLb+n3l30QK5Sf12x6cowRRUMIdvDt7FB+rEbQmMipEbVz0epkuUyfcxYGo/tWg09J3X70TtJK13Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900570787142.90029060960774; Sat, 16 Sep 2023 14:42:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd2i-000541-H5; Sat, 16 Sep 2023 17:41:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd2f-00053T-Qn for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:29 -0400 Received: from mail-oa1-x2d.google.com ([2001:4860:4864:20::2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd2d-0000Pf-Nb for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:29 -0400 Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-1c50438636fso1878912fac.1 for ; Sat, 16 Sep 2023 14:41:27 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900486; x=1695505286; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hG4FMe9Q2no9qbt6QH7h9ZHwSIMX8Uo4/7YnZ0piG0o=; b=SnirGEcp4jaTaHpByQ4lgNQN/lH+v1UE2Pn46qIBKo3sgS8PER6cGc62PvPQ1mzMHa KX/aDucSzWd4WWBt1JLmdSBot4N/4s2M8T5T8ZorQEoZF7z3bowhV7nDxKsYN72n7Geb BS7gwqM3ZLL4oBYls+YzCVlQsiq9NlZ75kcpZVGOUxbvPBfEF6kLZ3Be0sSgAeJn9jut NYL38tvIujkPe8+UQ2+ayRPqCqZq4WbRxyZYc2JtYycJPfcZRmy8upkPnu8ocuNufed1 7rePsynx5Kme22rMLZA5CrpwlUpJQcbXWi+mTsG33D9UJLfrikFOHECmC06i2TCC3L1j sYew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900486; x=1695505286; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hG4FMe9Q2no9qbt6QH7h9ZHwSIMX8Uo4/7YnZ0piG0o=; b=VwhfeJdH+jO5UPRIYNaK+im+3UnrbiN6EHPdCPIASptkY9CFcw6hQnDA7DqjAYXKUi S6VTJNLLGtmrLt0yl4uuw0O1JYVag4bjf0v4s+Xqk2X0KXTRBgZ/HRgWhHrlZd/RpNaP Zu8jtrIhhS2pAC7xqgSLLduiWYUrbQuQ7WF/Ctoxo+NziDmrOJz/SXRarKQINyDDg3RA VY6VrQXU0LvoQcvjTvIF9+Q3jRHFUXhw1qx1Ez6a3AwR4aNWC9i8Stbye2i6DOxWjCET Dhzz9w31rKQ9qE8wGc64N3VrlG6m9+uFTAi29sZDdDa7JkibL4itwqeqLiB74ajruq55 X0Dg== X-Gm-Message-State: AOJu0Yw3/Jh1K3id5L7dasQFWJusWU5fugF7s57Tvh8dxiv7cuHeBUfq urkZ7FSpyGuC+NHrZMArRH4fjN1BrIbOixqAYs4= X-Google-Smtp-Source: AGHT+IEWiI9L5FsHIS/EC6tZNN6qDzifruexx0DBitFjXx9Q+dqUUPvfmX2fAX1Zmj3jTom2402gDw== X-Received: by 2002:a05:6870:a706:b0:1c0:f8a7:ec14 with SMTP id g6-20020a056870a70600b001c0f8a7ec14mr5889038oam.57.1694900486121; Sat, 16 Sep 2023 14:41:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 01/39] target/arm: Replace TARGET_PAGE_ENTRY_EXTRA Date: Sat, 16 Sep 2023 14:40:45 -0700 Message-Id: <20230916214123.525796-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900572606100006 Content-Type: text/plain; charset="utf-8" From: Anton Johansson TARGET_PAGE_ENTRY_EXTRA is a macro that allows guests to specify additional fields for caching with the full TLB entry. This macro is replaced with a union in CPUTLBEntryFull, thus making CPUTLB target-agnostic at the cost of slightly inflated CPUTLBEntryFull for non-arm guests. Note, this is needed to ensure that fields in CPUTLB don't vary in offset between various targets. (arm is the only guest actually making use of this feature.) Signed-off-by: Anton Johansson Message-Id: <20230912153428.17816-2-anjo@rev.ng> Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 18 +++++++++++++++--- target/arm/cpu-param.h | 12 ------------ target/arm/ptw.c | 4 ++-- target/arm/tcg/mte_helper.c | 2 +- target/arm/tcg/sve_helper.c | 2 +- target/arm/tcg/tlb_helper.c | 4 ++-- target/arm/tcg/translate-a64.c | 2 +- 7 files changed, 22 insertions(+), 22 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 350287852e..46d2ac570f 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -135,9 +135,21 @@ typedef struct CPUTLBEntryFull { * This may be used to cache items from the guest cpu * page tables for later use by the implementation. */ -#ifdef TARGET_PAGE_ENTRY_EXTRA - TARGET_PAGE_ENTRY_EXTRA -#endif + union { + /* + * Cache the attrs and shareability fields from the page table ent= ry. + * + * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2= ]. + * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. + * For shareability and guarded, as in the SH and GP fields respec= tively + * of the VMSAv8-64 PTEs. + */ + struct { + uint8_t pte_attrs; + uint8_t shareability; + bool guarded; + } arm; + } extra; } CPUTLBEntryFull; #endif /* CONFIG_SOFTMMU */ =20 diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index b3b35f7aa1..f9b462a98f 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -31,18 +31,6 @@ # define TARGET_PAGE_BITS_VARY # define TARGET_PAGE_BITS_MIN 10 =20 -/* - * Cache the attrs and shareability fields from the page table entry. - * - * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2]. - * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. - * For shareability and guarded, as in the SH and GP fields respectively - * of the VMSAv8-64 PTEs. - */ -# define TARGET_PAGE_ENTRY_EXTRA \ - uint8_t pte_attrs; \ - uint8_t shareability; \ - bool guarded; #endif =20 #endif diff --git a/target/arm/ptw.c b/target/arm/ptw.c index bfbab26b9b..95db9ec4c3 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -579,7 +579,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, } ptw->out_phys =3D full->phys_addr | (addr & ~TARGET_PAGE_MASK); ptw->out_rw =3D full->prot & PAGE_WRITE; - pte_attrs =3D full->pte_attrs; + pte_attrs =3D full->extra.arm.pte_attrs; ptw->out_space =3D full->attrs.space; #else g_assert_not_reached(); @@ -2036,7 +2036,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, =20 /* When in aarch64 mode, and BTI is enabled, remember GP in the TL= B. */ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { - result->f.guarded =3D extract64(attrs, 50, 1); /* GP */ + result->f.extra.arm.guarded =3D extract64(attrs, 50, 1); /* GP= */ } } =20 diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index b23d11563a..dba21cc4d6 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -124,7 +124,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, assert(!(flags & TLB_INVALID_MASK)); =20 /* If the virtual page MemAttr !=3D Tagged, access unchecked. */ - if (full->pte_attrs !=3D 0xf0) { + if (full->extra.arm.pte_attrs !=3D 0xf0) { return NULL; } =20 diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 7c103fc9f7..f006d152cc 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -5373,7 +5373,7 @@ bool sve_probe_page(SVEHostPage *info, bool nofault, = CPUARMState *env, info->tagged =3D (flags & PAGE_ANON) && (flags & PAGE_MTE); #else info->attrs =3D full->attrs; - info->tagged =3D full->pte_attrs =3D=3D 0xf0; + info->tagged =3D full->extra.arm.pte_attrs =3D=3D 0xf0; #endif =20 /* Ensure that info->host[] is relative to addr, not addr + mem_off. */ diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index b22b2a4c6e..59bff8b452 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -334,8 +334,8 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, address &=3D TARGET_PAGE_MASK; } =20 - res.f.pte_attrs =3D res.cacheattrs.attrs; - res.f.shareability =3D res.cacheattrs.shareability; + res.f.extra.arm.pte_attrs =3D res.cacheattrs.attrs; + res.f.extra.arm.shareability =3D res.cacheattrs.shareability; =20 tlb_set_page_full(cs, mmu_idx, address, &res.f); return true; diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1b6fbb61e2..07c8f5b53b 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -13775,7 +13775,7 @@ static bool is_guarded_page(CPUARMState *env, Disas= Context *s) false, &host, &full, 0); assert(!(flags & TLB_INVALID_MASK)); =20 - return full->guarded; + return full->extra.arm.guarded; #endif } =20 --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900685; cv=none; d=zohomail.com; s=zohoarc; b=inWfjZpnzbojxRp8lJQVI7EGIoZo+i4pLLQDDsHFt4k7EEuVj0qrLQ0NKf3MwNp16Hqv3sMfz/OBirykgplBCfqGU/SKJcw4BMfY8nQHz4sAT8l42yJw5lARG3mx9B/tOuW+E4lfEoOsU9mzfFDDU6OoHtQXal9UkrnDFg3Fli8= ARC-Message-Signature: i=1; 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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900487; x=1695505287; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x5bXvV8/liLqXA0kcgF71U15Gwa32na7FANcfIedj14=; b=RlE6hjaMBa12ilYELUlynwe6ZJoO/CwSQuCGnsoWySlhtw78SoiEOIZi3HkshKEGJD oyWISg761CXzmzcc/3ek9yWCUy4K8JXdnwZN46hyhVjxV2JGL0r038LdCDCl7u9UGRBQ rf49aPDK7oGMFRffaYgjRp8LHyCTYrq0LAO82dAm5DsmpdmmpTq9hRv1W87XHAeuKLcx Z8/NWpaTFiQW5hhaBLmo4j0sTQMI/VmWVLK4sVT6Bo942cxu9qDpCx1E09oUdbIfllz/ Y2usKltl/8Iojj6NgvC+/WJQvYv2TtS8UZTO8nbvH1ovEpQIo0cQvrYg5kwDk2fEUKmo Iiuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900487; x=1695505287; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x5bXvV8/liLqXA0kcgF71U15Gwa32na7FANcfIedj14=; b=kIwXplzIkIo0mSS0WIDxWc41JJ8MLs8AKvkwihKsn1VyUAoS9icSqDgDg3yAZgyj76 ixiqInNaQ9N2feiU4/p8EWlC8SdbHNcvx8PMfjXnDLuR/uOZylxcpE3+7Sk3ehZVstB9 2XpRL0pRoyaFptxqlwWGpc10GDNviRBVbuewLywfzQtSjMAedmU9fOcJppzOGxu8yz5m C/L4PerFXqfrFQYTuyeOoo5/duvtkfgg8sTBiWTboUxKFuksfdrt77bsUjS8Uq/d2lt4 XKUQwxhpglKKH1y87jkFhQtiKJw4voljv33SyWYwXHGmj6TTBsZyuQxny3BZrns3aQmQ wRfw== X-Gm-Message-State: AOJu0YxbliOXX1lbtwJVhXw1cyuVOpeeCcXdGF3j0rZkW4tiFGqxTxMH yJbjeFqLz9ERH0/PDV/uTccerN1NFkfR5lbWKB0= X-Google-Smtp-Source: AGHT+IFFimQomnL/SL51yhwtVyVRw0I+yq9tmMEv6DZkKuPMOe0ewWeUBvl0wA+/FEDQvNZ+mXDdTg== X-Received: by 2002:a05:6870:58a5:b0:1be:d9cc:d902 with SMTP id be37-20020a05687058a500b001bed9ccd902mr5927049oab.57.1694900487115; Sat, 16 Sep 2023 14:41:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 02/39] accel/tcg: Move CPUTLB definitions from cpu-defs.h Date: Sat, 16 Sep 2023 14:40:46 -0700 Message-Id: <20230916214123.525796-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2d; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900686897100005 Content-Type: text/plain; charset="utf-8" Accept that we will consume space in CPUState for CONFIG_USER_ONLY, since we cannot test CONFIG_SOFTMMU within hw/core/cpu.h. Reviewed-by: Anton Johansson Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 150 ---------------------------------------- include/hw/core/cpu.h | 141 +++++++++++++++++++++++++++++++++++++ 2 files changed, 141 insertions(+), 150 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 46d2ac570f..3915438b83 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -54,18 +54,7 @@ =20 #include "exec/target_long.h" =20 -/* - * Fix the number of mmu modes to 16, which is also the maximum - * supported by the softmmu tlb api. - */ -#define NB_MMU_MODES 16 - #if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG) -#include "exec/tlb-common.h" - -/* use a fully associative victim tlb of 8 entries */ -#define CPU_VTLB_SIZE 8 - #define CPU_TLB_DYN_MIN_BITS 6 #define CPU_TLB_DYN_DEFAULT_BITS 8 =20 @@ -91,143 +80,4 @@ =20 #endif /* CONFIG_SOFTMMU && CONFIG_TCG */ =20 -#if defined(CONFIG_SOFTMMU) -/* - * The full TLB entry, which is not accessed by generated TCG code, - * so the layout is not as critical as that of CPUTLBEntry. This is - * also why we don't want to combine the two structs. - */ -typedef struct CPUTLBEntryFull { - /* - * @xlat_section contains: - * - For ram, an offset which must be added to the virtual address - * to obtain the ram_addr_t of the target RAM - * - For other memory regions, - * + in the lower TARGET_PAGE_BITS, the physical section number - * + with the TARGET_PAGE_BITS masked off, the offset within - * the target MemoryRegion - */ - hwaddr xlat_section; - - /* - * @phys_addr contains the physical address in the address space - * given by cpu_asidx_from_attrs(cpu, @attrs). - */ - hwaddr phys_addr; - - /* @attrs contains the memory transaction attributes for the page. */ - MemTxAttrs attrs; - - /* @prot contains the complete protections for the page. */ - uint8_t prot; - - /* @lg_page_size contains the log2 of the page size. */ - uint8_t lg_page_size; - - /* - * Additional tlb flags for use by the slow path. If non-zero, - * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. - */ - uint8_t slow_flags[MMU_ACCESS_COUNT]; - - /* - * Allow target-specific additions to this structure. - * This may be used to cache items from the guest cpu - * page tables for later use by the implementation. - */ - union { - /* - * Cache the attrs and shareability fields from the page table ent= ry. - * - * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2= ]. - * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. - * For shareability and guarded, as in the SH and GP fields respec= tively - * of the VMSAv8-64 PTEs. - */ - struct { - uint8_t pte_attrs; - uint8_t shareability; - bool guarded; - } arm; - } extra; -} CPUTLBEntryFull; -#endif /* CONFIG_SOFTMMU */ - -#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG) -/* - * Data elements that are per MMU mode, minus the bits accessed by - * the TCG fast path. - */ -typedef struct CPUTLBDesc { - /* - * Describe a region covering all of the large pages allocated - * into the tlb. When any page within this region is flushed, - * we must flush the entire tlb. The region is matched if - * (addr & large_page_mask) =3D=3D large_page_addr. - */ - vaddr large_page_addr; - vaddr large_page_mask; - /* host time (in ns) at the beginning of the time window */ - int64_t window_begin_ns; - /* maximum number of entries observed in the window */ - size_t window_max_entries; - size_t n_used_entries; - /* The next index to use in the tlb victim table. */ - size_t vindex; - /* The tlb victim table, in two parts. */ - CPUTLBEntry vtable[CPU_VTLB_SIZE]; - CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; - CPUTLBEntryFull *fulltlb; -} CPUTLBDesc; - -/* - * Data elements that are shared between all MMU modes. - */ -typedef struct CPUTLBCommon { - /* Serialize updates to f.table and d.vtable, and others as noted. */ - QemuSpin lock; - /* - * Within dirty, for each bit N, modifications have been made to - * mmu_idx N since the last time that mmu_idx was flushed. - * Protected by tlb_c.lock. - */ - uint16_t dirty; - /* - * Statistics. These are not lock protected, but are read and - * written atomically. This allows the monitor to print a snapshot - * of the stats without interfering with the cpu. - */ - size_t full_flush_count; - size_t part_flush_count; - size_t elide_flush_count; -} CPUTLBCommon; - -/* - * The entire softmmu tlb, for all MMU modes. - * The meaning of each of the MMU modes is defined in the target code. - * Since this is placed within CPUNegativeOffsetState, the smallest - * negative offsets are at the end of the struct. - */ - -typedef struct CPUTLB { - CPUTLBCommon c; - CPUTLBDesc d[NB_MMU_MODES]; - CPUTLBDescFast f[NB_MMU_MODES]; -} CPUTLB; - -#else - -typedef struct CPUTLB { } CPUTLB; - -#endif /* CONFIG_SOFTMMU && CONFIG_TCG */ - -/* - * This structure must be placed in ArchCPU immediately - * before CPUArchState, as a field named "neg". - */ -typedef struct CPUNegativeOffsetState { - CPUTLB tlb; - IcountDecr icount_decr; -} CPUNegativeOffsetState; - #endif diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 648b5b3586..04baa5063c 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -25,6 +25,7 @@ #include "exec/cpu-common.h" #include "exec/hwaddr.h" #include "exec/memattrs.h" +#include "exec/tlb-common.h" #include "qapi/qapi-types-run-state.h" #include "qemu/bitmap.h" #include "qemu/rcu_queue.h" @@ -192,6 +193,137 @@ struct CPUClass { bool gdb_stop_before_watchpoint; }; =20 +/* + * Fix the number of mmu modes to 16, which is also the maximum + * supported by the softmmu tlb api. + */ +#define NB_MMU_MODES 16 + +/* Use a fully associative victim tlb of 8 entries. */ +#define CPU_VTLB_SIZE 8 + +/* + * The full TLB entry, which is not accessed by generated TCG code, + * so the layout is not as critical as that of CPUTLBEntry. This is + * also why we don't want to combine the two structs. + */ +typedef struct CPUTLBEntryFull { + /* + * @xlat_section contains: + * - in the lower TARGET_PAGE_BITS, a physical section number + * - with the lower TARGET_PAGE_BITS masked off, an offset which + * must be added to the virtual address to obtain: + * + the ram_addr_t of the target RAM (if the physical section + * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) + * + the offset within the target MemoryRegion (otherwise) + */ + hwaddr xlat_section; + + /* + * @phys_addr contains the physical address in the address space + * given by cpu_asidx_from_attrs(cpu, @attrs). + */ + hwaddr phys_addr; + + /* @attrs contains the memory transaction attributes for the page. */ + MemTxAttrs attrs; + + /* @prot contains the complete protections for the page. */ + uint8_t prot; + + /* @lg_page_size contains the log2 of the page size. */ + uint8_t lg_page_size; + + /* + * Additional tlb flags for use by the slow path. If non-zero, + * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. + */ + uint8_t slow_flags[MMU_ACCESS_COUNT]; + + /* + * Allow target-specific additions to this structure. + * This may be used to cache items from the guest cpu + * page tables for later use by the implementation. + */ + union { + /* + * Cache the attrs and shareability fields from the page table ent= ry. + * + * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2= ]. + * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. + * For shareability and guarded, as in the SH and GP fields respec= tively + * of the VMSAv8-64 PTEs. + */ + struct { + uint8_t pte_attrs; + uint8_t shareability; + bool guarded; + } arm; + } extra; +} CPUTLBEntryFull; + +/* + * Data elements that are per MMU mode, minus the bits accessed by + * the TCG fast path. + */ +typedef struct CPUTLBDesc { + /* + * Describe a region covering all of the large pages allocated + * into the tlb. When any page within this region is flushed, + * we must flush the entire tlb. The region is matched if + * (addr & large_page_mask) =3D=3D large_page_addr. + */ + vaddr large_page_addr; + vaddr large_page_mask; + /* host time (in ns) at the beginning of the time window */ + int64_t window_begin_ns; + /* maximum number of entries observed in the window */ + size_t window_max_entries; + size_t n_used_entries; + /* The next index to use in the tlb victim table. */ + size_t vindex; + /* The tlb victim table, in two parts. */ + CPUTLBEntry vtable[CPU_VTLB_SIZE]; + CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; + CPUTLBEntryFull *fulltlb; +} CPUTLBDesc; + +/* + * Data elements that are shared between all MMU modes. + */ +typedef struct CPUTLBCommon { + /* Serialize updates to f.table and d.vtable, and others as noted. */ + QemuSpin lock; + /* + * Within dirty, for each bit N, modifications have been made to + * mmu_idx N since the last time that mmu_idx was flushed. + * Protected by tlb_c.lock. + */ + uint16_t dirty; + /* + * Statistics. These are not lock protected, but are read and + * written atomically. This allows the monitor to print a snapshot + * of the stats without interfering with the cpu. + */ + size_t full_flush_count; + size_t part_flush_count; + size_t elide_flush_count; +} CPUTLBCommon; + +/* + * The entire softmmu tlb, for all MMU modes. + * The meaning of each of the MMU modes is defined in the target code. + * Since this is placed within CPUNegativeOffsetState, the smallest + * negative offsets are at the end of the struct. + */ +typedef struct CPUTLB { +#ifdef CONFIG_TCG + CPUTLBCommon c; + CPUTLBDesc d[NB_MMU_MODES]; + CPUTLBDescFast f[NB_MMU_MODES]; +#endif +} CPUTLB; + /* * Low 16 bits: number of cycles left, used only in icount mode. * High 16 bits: Set to -1 to force TCG to stop executing linked TBs @@ -212,6 +344,15 @@ typedef union IcountDecr { } u16; } IcountDecr; =20 +/* + * This structure must be placed in ArchCPU immediately + * before CPUArchState, as a field named "neg". + */ +typedef struct CPUNegativeOffsetState { + CPUTLB tlb; + IcountDecr icount_decr; +} CPUNegativeOffsetState; + typedef struct CPUBreakpoint { vaddr pc; int flags; /* BP_* */ --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900750; cv=none; d=zohomail.com; s=zohoarc; b=Cvub2ipZ4S4XurtckeiMAteyObgDOpWZPeMZ3EvoDqb2B15dHGtk8TUorDkSsYUHAWcp7IAwhj2gLzAPJbVDQ3C+/urSCI2JDo/RK9FwKHPjgm6+JaCg9BOqrmqlgUBIqrKCN0oBNod0mchnZJFfSV89gAvWKzZ73opToK+gmYQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900750; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=i3wrIxgr2m5oHMVkH4v8wSAkRBNGt7xc6AFyiVFHwxo=; b=EcQ4oteefwZGiUUDNuDVAqDEgDMdjwOeQ03rjabQW7cPR6OGKK4emVHibyFmaH8OTz/Ez7nPgfPk1VPzNqfOxWvuYZL3vmmN7gvNPimVEQ3kFuwvnhR7YUQ1LQxFKfrwzkThLMAJocHyLTyGQpD5p/ySIS7/qebsocOnkhrBZ7Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900750912794.8435842238794; Sat, 16 Sep 2023 14:45:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd2k-00054Y-5H; Sat, 16 Sep 2023 17:41:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd2g-00053n-PX for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:30 -0400 Received: from mail-oi1-x231.google.com ([2607:f8b0:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd2f-0000Pu-9B for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:30 -0400 Received: by mail-oi1-x231.google.com with SMTP id 5614622812f47-3a88ef953adso2225756b6e.0 for ; Sat, 16 Sep 2023 14:41:28 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900488; x=1695505288; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i3wrIxgr2m5oHMVkH4v8wSAkRBNGt7xc6AFyiVFHwxo=; b=GU7et89vQoNgQXej9+v+sycADnrLUqdz6cEuULq923fa/Suf5HHK3SR0m3Sm58M9AZ ncuDOmsJV3zbGaKYfUlw4G3y3tohWuNywY57Ps5+CNLlOyawCWFp6o8w9No3ZWPCcZaq spwTw7/Z9UIbmtiq2GCs3jB72LldprzUBgI7uT4RxUeNjEGvr957Fkny9HW8jFi3+d6u omuTaSjb4oItUSqXskhtTD46SLFQT/9mQ9ZeQ3YPJJVV0/cqRAwRos2Rrl0AO/Yg031i CFlfE4CkX0+/Vl4GTqN9Sk23DYOivY1FFkhbKYpm1mGY6HS7xmXkn6GYE1F+1u+EFbwi fTiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900488; x=1695505288; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i3wrIxgr2m5oHMVkH4v8wSAkRBNGt7xc6AFyiVFHwxo=; b=NgNgN9azCh/pvYP96xp/QTH98ezXmvW22Fyjc8LT2JVG1shxz/a84GUlyulLAlrqja U+yuRv/KLb6H/3mG6FUjYLlMFeMdpqx7Mv+apq77XDgmGxlZkNP//wwg5mxZNEHyOpXa NCxWC75dOmG50DWIASitvrXLv9ukFjglKcTViCFdU8YMuHDY6x/sRYWPnxZYfJdZa2/h sf4nEAr4nh9JjkScpd5/mC+aVa97HFRnxWNMWfM5wkvZciYVy6XWAbUo4/OXLuGYlUGz yEbjYyUvD9BFs94kM0eYoq2f7NW4TeyTfKHcx5adnMWTwy2Hq6SCSBnCwlix748GJ0aq K9sg== X-Gm-Message-State: AOJu0Yx1voF9TVBHXe8XPDe+x+mHfIZIy53qprotWc+SYx/GSppy6k60 XP3sze1JEtn5pktWa8Hxg/n5mzpjJMnnjh4TlIM= X-Google-Smtp-Source: AGHT+IHpIsUeX0tfLcrOYHX7LdBPICenQ7KnkwDxe3btiFqtI3XPVN465PHmMYQcadyuJ0zt9sRpkQ== X-Received: by 2002:a05:6870:b4a6:b0:1bf:9fa2:bf8e with SMTP id y38-20020a056870b4a600b001bf9fa2bf8emr6918969oap.1.1694900488113; Sat, 16 Sep 2023 14:41:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 03/39] qom: Propagate alignment through type system Date: Sat, 16 Sep 2023 14:40:47 -0700 Message-Id: <20230916214123.525796-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900751541100001 Propagate alignment just like size. This is required in order to get the correct alignment on most cpu subclasses where the size and alignment is only specified for the base cpu type. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- qom/object.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/qom/object.c b/qom/object.c index e25f1e96db..8557fe8e4e 100644 --- a/qom/object.c +++ b/qom/object.c @@ -220,6 +220,19 @@ static size_t type_object_get_size(TypeImpl *ti) return 0; } =20 +static size_t type_object_get_align(TypeImpl *ti) +{ + if (ti->instance_align) { + return ti->instance_align; + } + + if (type_has_parent(ti)) { + return type_object_get_align(type_get_parent(ti)); + } + + return 0; +} + size_t object_type_get_instance_size(const char *typename) { TypeImpl *type =3D type_get_by_name(typename); @@ -293,6 +306,7 @@ static void type_initialize(TypeImpl *ti) =20 ti->class_size =3D type_class_get_size(ti); ti->instance_size =3D type_object_get_size(ti); + ti->instance_align =3D type_object_get_align(ti); /* Any type with zero instance_size is implicitly abstract. * This means interface types are all abstract. */ --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900730; cv=none; d=zohomail.com; s=zohoarc; b=VRftkilFpnnQjWnFJQXGovgyh0Vb0FXf5AOzAhtBSVUlEj0l60HThCkeqCFkz66BTZyVKrxlICuGo3Kd/+sX6+ev2C1igIMCQMpYflDQQJfSP/On43bwYc9bz/dIwTQnz3aPhlHSuijIS75BgcSZ6Cn5sZnumNY6geHcFCIht7w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900730; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PCZUgNuN/cpm5AWhhskU6xG8RA6Qz33ls/52yNT5Lro=; b=fFMtIZEhc2y6A0IuLy6x1qFsUkDh4MekXxqX6ohDSekk+02fJF8iTXrJWa5YssrjbXcb2m+VkfJ+9681ynppMxNreX+tSq40TFMUCM90BCzNrsKN1h2rEPEdi4E4wPchIvuiOgc4QTc8rD8Kshfve42SjUw7Xc5f/EFYZS9eels= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900730891958.2830762049106; Sat, 16 Sep 2023 14:45:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd2o-000562-5D; Sat, 16 Sep 2023 17:41:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd2i-000543-1y for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:32 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd2g-0000Q8-JB for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:31 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-68fb7fb537dso3022530b3a.2 for ; Sat, 16 Sep 2023 14:41:30 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900489; x=1695505289; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PCZUgNuN/cpm5AWhhskU6xG8RA6Qz33ls/52yNT5Lro=; b=N/cAtsL6tpwGoqv9ja2GRcjv/vEIdtbNkM2l5nFhRF4JL6za4Xbu5nt0D+TMShGuDX SjHf2Km8xMN9xYJ6y8gNDpM1G/tJINlbB9AUa/q/ow2OVKAaeLoeqZzSJGSGlThOolhA g4rXmey2a5TZPnIogA/WyTE4jZsd5E3sZvhWxF6+kfG9RmM4YPpAi+8aFEjVw2aVrkk2 Is3PTFPaMvHH2gDeBsZQpFcKwZN6dT09kSEyFaU/WXWGhZinx+A3s9khlx4Ky4wCB6hd K9jBnf4YZ0f6iLrKON80qT+wNX8WXsb8ekf5B7TFFdXD9pNn+suqC76m7/lqlzgZbqh4 0gkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900489; x=1695505289; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PCZUgNuN/cpm5AWhhskU6xG8RA6Qz33ls/52yNT5Lro=; b=dOH6fIMAzSvEgyu6/EwcZTdbrPTqb8UUwHuTjiLSLvPFKGH2MhquLwg+l9cf7mxPgS OirWUIHxcw17HJfo99Qqwh1BxxAnLoKW+J3EhYBT6HE1TZ9AWuBVAprDdjEj+sJvikrg 4t9o5K30zkKTjOFs618WfE203y/Mf5BFM5SBi6YwNE5mSmSxQfgJCjJyygxVL8ARDZ3Y j4tC5Y3tCQ9MAEEXkjBOwqAulj/ONR1l1A0+O6IzHk+rNQGwtfz08Ot4FQZ/Q9TQIk9z yYOCenb2//COOhreIAUx9EPclIIHm3XkWpXgvcm2hpB18tRtoshbJiadAcoYXKER1HGc cf+g== X-Gm-Message-State: AOJu0Yxdwwljh+7uGb4N742WJv4NtEgK1/OGq0fiO+RG0K9iugtesJOv fkb17/x0ybccp5uY6oFk337jRfpxHOPfxZf4c1A= X-Google-Smtp-Source: AGHT+IE5Ok6nbCQcYbdzeE4F531Scfgkae4hICFOdred4LaiI2c/g59BE+2MDTLFzKz1x7l0KhcGwg== X-Received: by 2002:a05:6a00:181b:b0:68e:3def:c3cd with SMTP id y27-20020a056a00181b00b0068e3defc3cdmr5675389pfa.17.1694900489105; Sat, 16 Sep 2023 14:41:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 04/39] target/arm: Remove size and alignment for cpu subclasses Date: Sat, 16 Sep 2023 14:40:48 -0700 Message-Id: <20230916214123.525796-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900731245100005 Inherit the size and alignment from TYPE_ARM_CPU. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/cpu.c | 3 --- target/arm/cpu64.c | 4 ---- 2 files changed, 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b9e09a702d..d48a70c039 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2423,10 +2423,7 @@ void arm_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info =3D { .parent =3D TYPE_ARM_CPU, - .instance_size =3D sizeof(ARMCPU), - .instance_align =3D __alignof__(ARMCPU), .instance_init =3D arm_cpu_instance_init, - .class_size =3D sizeof(ARMCPUClass), .class_init =3D info->class_init ?: cpu_register_class_init, .class_data =3D (void *)info, }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f3d87e001f..811f3b38c2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -822,9 +822,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info =3D { .parent =3D TYPE_AARCH64_CPU, - .instance_size =3D sizeof(ARMCPU), .instance_init =3D aarch64_cpu_instance_init, - .class_size =3D sizeof(ARMCPUClass), .class_init =3D info->class_init ?: cpu_register_class_init, .class_data =3D (void *)info, }; @@ -837,10 +835,8 @@ void aarch64_cpu_register(const ARMCPUInfo *info) static const TypeInfo aarch64_cpu_type_info =3D { .name =3D TYPE_AARCH64_CPU, .parent =3D TYPE_ARM_CPU, - .instance_size =3D sizeof(ARMCPU), .instance_finalize =3D aarch64_cpu_finalizefn, .abstract =3D true, - .class_size =3D sizeof(AArch64CPUClass), .class_init =3D aarch64_cpu_class_init, }; =20 --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900550; cv=none; d=zohomail.com; s=zohoarc; b=KLdRl4hLmczCxaSmx1/XuYZgyIGD0JVZPKa/ADsm3o3qx48KSjBv97a/5CF5CUT/r2ZzXFYLgNkMk18/gjC1JY9epCQg0iVTndxT8cB+nEE/r6v3ZlYSPXI1/AkPtM4weoMSGE23bfvtjPNGJtlOvrscqr8TdEZp1VVUht/zHko= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900550; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CL2g+I/aYKhCYdCOqJipcnPRCNs8rgqlHMh/Z1brbrI=; b=gibUP2hjq85ubO9kBM9gZJzDzW/UN6aWlCf4/wRq8roKZu6WwAraFa4/4OWkeEVjHhwVBFJ+sc8PGhZJFJyGjpvv7gdT1T0OJBZKq55o4SaOIX2fhf5mNnbe5/LDc+7qVzUVTo5/b5G6s4JV/LMnKg9ig69HBVFfra88xy5a+C0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900550094986.7743667616022; Sat, 16 Sep 2023 14:42:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd2m-00055o-Ov; Sat, 16 Sep 2023 17:41:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd2j-00054V-8o for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:34 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd2h-0000QO-9u for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:33 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-690471b5889so1422291b3a.0 for ; Sat, 16 Sep 2023 14:41:30 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900490; x=1695505290; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CL2g+I/aYKhCYdCOqJipcnPRCNs8rgqlHMh/Z1brbrI=; b=PScSqbZ5qOtn45VoD1eVhb6WXLAfcsWephuqLN3xvgP2o8GWjgusVQdLHW1K8d/qy9 PwpATw7S5vwqLDQW3auB5QQPF/n3HIu6Vy7A0VZOf2NUtT5LXBcuky0jBGZaUdLS/uZe O4XkZNVvsyZXmaz6b3HQHDHAdrcQsITIcYynBkGKJi9Wh91ihra45l0vB46aYItr+3k7 iwAp8t0N0WeGN4RAS839ubIcWiilxmZlA1zRC8RCA+sXBzEMjxKkmJ+XIfevaZh6Ijgq XrLAs2GSDIW5N1DAc+pXVk2TIZAS9FFWthD/kA0iH1Uy/t2Iw2cA6VAhyAxLsGTrxdDe 6NAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900490; x=1695505290; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CL2g+I/aYKhCYdCOqJipcnPRCNs8rgqlHMh/Z1brbrI=; b=sPMj19i56aAb91gEzAO8b5obcW8ou67aOTt6Ai3HjccxKOxafVcsW+u7etOZxrAOPq 81GvbbQovZrXD55YdHkzps0bKRniNFk8aTQ4tFK6Xr9XbjeI/5/bqHa8okFujGQF6R7h WHXkeoQzuuZjGufbHrdZUk0JfmOQ2VaAhcC5Ii6oB+d3FQaGS2+sHSZmKWvd12OuzzZd /UyV79appyNDmN/KkHc7BYVjyhBoPePTyyVFsElpXTtkckPOdC444JURnrWIZEMxchFt umbMlZhZZYJbKSGL6OIjb0wLTERY6UlI6aiDbwKp+JQAqwdkEvCSGC3bQICUonmJJHUJ HMpA== X-Gm-Message-State: AOJu0YyxV4SA8gztZHtMvWZHV1L0W8wCWtIujorOY26smpY0dOropOZM B/Nm/kix86km7T339tXjxDcq6W36/HP0FYEcHTg= X-Google-Smtp-Source: AGHT+IHEXUlVrbUyptiqEwM8YkOHuSvH2KZbK27eqslF6NeSbuHc8Rm9AXamuiICn96CTM+bP6NUzg== X-Received: by 2002:a05:6a00:2d04:b0:68f:dfe2:9f03 with SMTP id fa4-20020a056a002d0400b0068fdfe29f03mr4427665pfb.11.1694900489944; Sat, 16 Sep 2023 14:41:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 05/39] target/*: Add instance_align to all cpu base classes Date: Sat, 16 Sep 2023 14:40:49 -0700 Message-Id: <20230916214123.525796-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900550979100001 The omission of alignment has technically been wrong since 269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/alpha/cpu.c | 1 + target/avr/cpu.c | 1 + target/cris/cpu.c | 1 + target/hexagon/cpu.c | 1 + target/hppa/cpu.c | 1 + target/i386/cpu.c | 1 + target/loongarch/cpu.c | 1 + target/m68k/cpu.c | 1 + target/microblaze/cpu.c | 1 + target/mips/cpu.c | 1 + target/nios2/cpu.c | 1 + target/openrisc/cpu.c | 1 + target/riscv/cpu.c | 2 +- target/rx/cpu.c | 1 + target/sh4/cpu.c | 1 + target/sparc/cpu.c | 1 + target/tricore/cpu.c | 1 + target/xtensa/cpu.c | 1 + 18 files changed, 18 insertions(+), 1 deletion(-) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 270ae787b1..e2156fcb41 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -286,6 +286,7 @@ static const TypeInfo alpha_cpu_type_infos[] =3D { .name =3D TYPE_ALPHA_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(AlphaCPU), + .instance_align =3D __alignof(AlphaCPU), .instance_init =3D alpha_cpu_initfn, .abstract =3D true, .class_size =3D sizeof(AlphaCPUClass), diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 8f741f258c..c5a6436336 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -390,6 +390,7 @@ static const TypeInfo avr_cpu_type_info[] =3D { .name =3D TYPE_AVR_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(AVRCPU), + .instance_align =3D __alignof(AVRCPU), .instance_init =3D avr_cpu_initfn, .class_size =3D sizeof(AVRCPUClass), .class_init =3D avr_cpu_class_init, diff --git a/target/cris/cpu.c b/target/cris/cpu.c index a6a93c2359..8ab8a30b8d 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -345,6 +345,7 @@ static const TypeInfo cris_cpu_model_type_infos[] =3D { .name =3D TYPE_CRIS_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(CRISCPU), + .instance_align =3D __alignof(CRISCPU), .instance_init =3D cris_cpu_initfn, .abstract =3D true, .class_size =3D sizeof(CRISCPUClass), diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index f155936289..65f198b956 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -408,6 +408,7 @@ static const TypeInfo hexagon_cpu_type_infos[] =3D { .name =3D TYPE_HEXAGON_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(HexagonCPU), + .instance_align =3D __alignof(HexagonCPU), .instance_init =3D hexagon_cpu_init, .abstract =3D true, .class_size =3D sizeof(HexagonCPUClass), diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 11022f9c99..17fa901f6a 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -212,6 +212,7 @@ static const TypeInfo hppa_cpu_type_info =3D { .name =3D TYPE_HPPA_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(HPPACPU), + .instance_align =3D __alignof(HPPACPU), .instance_init =3D hppa_cpu_initfn, .abstract =3D false, .class_size =3D sizeof(HPPACPUClass), diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b2a20365e1..7f15ea4ec4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8020,6 +8020,7 @@ static const TypeInfo x86_cpu_type_info =3D { .name =3D TYPE_X86_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(X86CPU), + .instance_align =3D __alignof(X86CPU), .instance_init =3D x86_cpu_initfn, .instance_post_init =3D x86_cpu_post_initfn, =20 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 65f9320e34..56e67cea8d 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -804,6 +804,7 @@ static const TypeInfo loongarch_cpu_type_infos[] =3D { .name =3D TYPE_LOONGARCH_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(LoongArchCPU), + .instance_align =3D __alignof(LoongArchCPU), .instance_init =3D loongarch_cpu_init, =20 .abstract =3D true, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 70d58471dc..d34d1b57d0 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -611,6 +611,7 @@ static const TypeInfo m68k_cpus_type_infos[] =3D { .name =3D TYPE_M68K_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(M68kCPU), + .instance_align =3D __alignof(M68kCPU), .instance_init =3D m68k_cpu_initfn, .abstract =3D true, .class_size =3D sizeof(M68kCPUClass), diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 03c2c4db1f..c53711da52 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -439,6 +439,7 @@ static const TypeInfo mb_cpu_type_info =3D { .name =3D TYPE_MICROBLAZE_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(MicroBlazeCPU), + .instance_align =3D __alignof(MicroBlazeCPU), .instance_init =3D mb_cpu_initfn, .class_size =3D sizeof(MicroBlazeCPUClass), .class_init =3D mb_cpu_class_init, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 63da1948fd..fee791aa44 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -600,6 +600,7 @@ static const TypeInfo mips_cpu_type_info =3D { .name =3D TYPE_MIPS_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(MIPSCPU), + .instance_align =3D __alignof(MIPSCPU), .instance_init =3D mips_cpu_initfn, .abstract =3D true, .class_size =3D sizeof(MIPSCPUClass), diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index bc5cbf81c2..598976305f 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -400,6 +400,7 @@ static const TypeInfo nios2_cpu_type_info =3D { .name =3D TYPE_NIOS2_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(Nios2CPU), + .instance_align =3D __alignof(Nios2CPU), .instance_init =3D nios2_cpu_initfn, .class_size =3D sizeof(Nios2CPUClass), .class_init =3D nios2_cpu_class_init, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 61d748cfdc..be067709b8 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -314,6 +314,7 @@ static const TypeInfo openrisc_cpus_type_infos[] =3D { .name =3D TYPE_OPENRISC_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(OpenRISCCPU), + .instance_align =3D __alignof(OpenRISCCPU), .instance_init =3D openrisc_cpu_initfn, .abstract =3D true, .class_size =3D sizeof(OpenRISCCPUClass), diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f227c7664e..8a765d5117 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2314,7 +2314,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .name =3D TYPE_RISCV_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(RISCVCPU), - .instance_align =3D __alignof__(RISCVCPU), + .instance_align =3D __alignof(RISCVCPU), .instance_init =3D riscv_cpu_init, .abstract =3D true, .class_size =3D sizeof(RISCVCPUClass), diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 157e57da0f..51559943fb 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -248,6 +248,7 @@ static const TypeInfo rx_cpu_info =3D { .name =3D TYPE_RX_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(RXCPU), + .instance_align =3D __alignof(RXCPU), .instance_init =3D rx_cpu_init, .abstract =3D true, .class_size =3D sizeof(RXCPUClass), diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 61769ffdfa..a90e41c4ec 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -315,6 +315,7 @@ static const TypeInfo superh_cpu_type_infos[] =3D { .name =3D TYPE_SUPERH_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(SuperHCPU), + .instance_align =3D __alignof(SuperHCPU), .instance_init =3D superh_cpu_initfn, .abstract =3D true, .class_size =3D sizeof(SuperHCPUClass), diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 130ab8f578..d6d3c4b031 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -930,6 +930,7 @@ static const TypeInfo sparc_cpu_type_info =3D { .name =3D TYPE_SPARC_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(SPARCCPU), + .instance_align =3D __alignof(SPARCCPU), .instance_init =3D sparc_cpu_initfn, .abstract =3D true, .class_size =3D sizeof(SPARCCPUClass), diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 133a9ac70e..50aec6cf10 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -230,6 +230,7 @@ static const TypeInfo tricore_cpu_type_infos[] =3D { .name =3D TYPE_TRICORE_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(TriCoreCPU), + .instance_align =3D __alignof(TriCoreCPU), .instance_init =3D tricore_cpu_initfn, .abstract =3D true, .class_size =3D sizeof(TriCoreCPUClass), diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index acaf8c905f..281872d7ca 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -273,6 +273,7 @@ static const TypeInfo xtensa_cpu_type_info =3D { .name =3D TYPE_XTENSA_CPU, .parent =3D TYPE_CPU, .instance_size =3D sizeof(XtensaCPU), + .instance_align =3D __alignof(XtensaCPU), .instance_init =3D xtensa_cpu_initfn, .abstract =3D true, .class_size =3D sizeof(XtensaCPUClass), --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900785; cv=none; d=zohomail.com; s=zohoarc; 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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900491; x=1695505291; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MKFrEK1ybHE5W37yArUxMsWARo+/L2b8HkANYXonYTk=; b=iKtLI0pJWOnJhaEyUwWew9kRhbxPWO6N4W9PaXIa4E7d8j/ZwDKI0qTMCsiiotnzKy UqoW5shN4oFAeEkzpAiyq5Yb8Y41HBKS6QAY5u4zWz1HpVdVFGr26vrKDc+YMcYCqsH1 28bY8NfgGV6vb5OLjPsRgwXu9biqOKzxiMukB3jxOe4T00Fh7vcBqf2npiQzFmfg7SuC 2PTRFzZ/W7P4rpozW/XwBnu3pRJXmx9F3D8/gyC+IcsNeCF1eyeRcepfxiYtMH8YJsjp u5j00Kdi9iK/WQZ1pfq0uwWQJ7MEmFhmXqhsVUyEoxrgX4SS8kuM1pt3+9PwfCbXDUEr /FaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900491; x=1695505291; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MKFrEK1ybHE5W37yArUxMsWARo+/L2b8HkANYXonYTk=; b=Yp1CNEFYopIaui+y7IlOBaHruBtKcDaBmCRoNvFoFeL3WX2jLWeE3lUaIQowvdnSej apoA4dKNlyhb1n3IVsH9kTBPxGaessgP6B6+cLiLQFejn3djsgEYT5ZoCTvO0lzGJov4 jRonKP4dBt6Hh9yxo4fQxyLJITc+lzK9jWUuS7TLa3V6+e6m2FMkhWQKqiCeZlW+INmL FhSLt+f5dXPK4Kst5KK2czfk4eyglRr4MCnZNejiR35TgWXxneCLamDXBIxsotO78tom ekGabcOc6bVu8u8LVBCEvghJChP8f4l8aObeO/XIFqdd+LJzDbZ9k0UeIeyoNqvZyG+m peAQ== X-Gm-Message-State: AOJu0YzJ6fTMlXX5wbFXHT7UOkZIC4flD9qx3RTwBSHbYB5hFdh80g9P rwYbmYB8t5Db61+nYcTJ6UaSZgc5mg7HHbUnzxM= X-Google-Smtp-Source: AGHT+IFLJ2XtP4OcpAUGcc5Pvgl8XSML/oDCb7v+SRb59UwOjW2g0bOfAwFNJRp3G87m4M2ccNT77Q== X-Received: by 2002:a05:6870:462a:b0:1c8:c128:c38e with SMTP id z42-20020a056870462a00b001c8c128c38emr5936710oao.15.1694900490847; Sat, 16 Sep 2023 14:41:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 06/39] accel/tcg: Validate placement of CPUNegativeOffsetState Date: Sat, 16 Sep 2023 14:40:50 -0700 Message-Id: <20230916214123.525796-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900786515100007 Content-Type: text/plain; charset="utf-8" Verify that the distance between CPUNegativeOffsetState and CPUArchState is no greater than any alignment requirements. Reviewed-by: Anton Johansson Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index c2c62160c6..86a7452b0d 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -459,6 +459,12 @@ static inline CPUState *env_cpu(CPUArchState *env) return &env_archcpu(env)->parent_obj; } =20 +/* + * Validate placement of CPUNegativeOffsetState. + */ +QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) - offsetof(ArchCPU, neg) >=3D + sizeof(CPUNegativeOffsetState) + __alignof(CPUArchState)= ); + /** * env_neg(env) * @env: The architecture environment --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900699; cv=none; d=zohomail.com; s=zohoarc; b=k3KfnKa7qf34vsrswlzhNTGLigQF3bOofC+tmjv1e6+CluxTotR0QKsRvQUjckpHW+uwZNfOh+b0Td0szJy6KVnj//D7IFXZ6pn2A8Nv9+6JBN32NxDxKOmmdwY1A7zrYJH9drBtLbeMW8nmiqIRCKCt7F2fIwXp2oiz3pP8E34= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900699; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3Z+/Cc8PVRj+uMG7DhPL8FK/YG6daD+6YPyxU9cEkIs=; b=Ao4Apq6qToYo2MCm2eToT9fw00+Ll8OjBmBjzCyYwv6s62NkmyH7NcQh5xAHzyy4Gpdgu69ztTvwBWHjiIxRXBV9LKrimJC2Byywn7P0IgjG4Yhy9HimmambtiJmoFzy58+JRC4q55jhd5hhTFa05sq0cj/3ODlNFt9ZT/X58gQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900699231821.4798617804336; Sat, 16 Sep 2023 14:44:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd2s-00057X-FW; Sat, 16 Sep 2023 17:41:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd2l-00055W-Kt for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:35 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd2j-0000Qo-04 for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:35 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-68fc9e0e22eso2656626b3a.1 for ; Sat, 16 Sep 2023 14:41:32 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900491; x=1695505291; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3Z+/Cc8PVRj+uMG7DhPL8FK/YG6daD+6YPyxU9cEkIs=; b=Lyd+40AvQHQ2ha06YuLWvGc3qOIcYbF8RPkZu3hWLCleUgulEBZMob+Lu0LNeC8Zfe L2OJsNT1xhCkQwVnxBCc5xjA0AFJDQx10U1h1zCo5C/SPm/hwJ+BgGVPUqvcvB24fCBm dMqKJZcYZt9gbvWlbnHLtH9WT7+heOFLafpDNzfJkqB4P2Gu98DCZZHM3SPVlqvfXTbk KUwFvaVVfdinyhehH+Q9oZ4gZPR5/Ycu0GqhECckaQxIwvkGiSB66tBqShDnojVWi97p RQuZLi43ZDKoZ+Qz4OfFp1zMhnLsSkdO/5K68ygWBi0E/6IoHOyK7fUVSxjKo4HE1X48 XOZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900491; x=1695505291; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3Z+/Cc8PVRj+uMG7DhPL8FK/YG6daD+6YPyxU9cEkIs=; b=CzTiYXsw2aLnr1lykolJiKU2x3qS5o8MGn5vJ6Ufij+H6xvR6OKHefeSFjoamdL7gC 44aXsKfLVC3VeJ/Zo/7LaXWzpsOoP67EsnfFhLFdIvRUh4Ud9zZLWt6KTPVy2EgUg8Fj kYA6bze88NzR6e8WH2agimAs5JmHqGov0GdBgDpia64IA1QFxeLr8hG5mNad0HzpEZ44 5YNAvRtK9OfxnyeSe30JWoNmBR1pMIVoquqd9UlUt2yxW4sxBRibva4ubb9Ep8zoCH+C sX9zFkID96G69a5j10IUUNnUewpHQS74r3DpgGbgAHf4IiZVJJSqafCVA6qfUMUcAoUS EtEw== X-Gm-Message-State: AOJu0YwY/2Xq6dduGlJzG+QCDnEZJFci86UIC/KulGL/n/RnDK0Be+l/ J0H2DWcM+Hkc+6n47lUTWlIscyce3ch+L4KMgx0= X-Google-Smtp-Source: AGHT+IEJpYFqRfIR2Jx6fzMQPnHd+N7jjLgdRFUVCrt9hfAx3Mb6dqhHrg45CECJ2ymiQ3R8Z3GHzg== X-Received: by 2002:a05:6a00:15cc:b0:68e:2af1:b193 with SMTP id o12-20020a056a0015cc00b0068e2af1b193mr5678374pfu.28.1694900491520; Sat, 16 Sep 2023 14:41:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 07/39] accel/tcg: Move CPUNegativeOffsetState into CPUState Date: Sat, 16 Sep 2023 14:40:51 -0700 Message-Id: <20230916214123.525796-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900699736100001 Content-Type: text/plain; charset="utf-8" Retain the separate structure to emphasize its importance. Enforce CPUArchState always follows CPUState without padding. Reviewed-by: Anton Johansson Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 22 +++++++++------------- include/hw/core/cpu.h | 17 +++++++++++++++-- target/alpha/cpu.h | 1 - target/arm/cpu.h | 1 - target/avr/cpu.h | 1 - target/cris/cpu.h | 1 - target/hexagon/cpu.h | 2 +- target/hppa/cpu.h | 1 - target/i386/cpu.h | 1 - target/loongarch/cpu.h | 1 - target/m68k/cpu.h | 1 - target/microblaze/cpu.h | 6 +++--- target/mips/cpu.h | 4 ++-- target/nios2/cpu.h | 1 - target/openrisc/cpu.h | 1 - target/ppc/cpu.h | 1 - target/riscv/cpu.h | 2 +- target/rx/cpu.h | 1 - target/s390x/cpu.h | 1 - target/sh4/cpu.h | 1 - target/sparc/cpu.h | 1 - target/tricore/cpu.h | 1 - target/xtensa/cpu.h | 3 +-- accel/tcg/translate-all.c | 4 ++-- accel/tcg/translator.c | 8 ++++---- 25 files changed, 38 insertions(+), 46 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 86a7452b0d..165a271642 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -434,9 +434,13 @@ void tcg_exec_unrealizefn(CPUState *cpu); static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) { cpu->parent_obj.env_ptr =3D &cpu->env; - cpu->parent_obj.icount_decr_ptr =3D &cpu->neg.icount_decr; + cpu->parent_obj.icount_decr_ptr =3D &cpu->parent_obj.neg.icount_decr; } =20 +/* Validate correct placement of CPUArchState. */ +QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) !=3D 0); +QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) !=3D sizeof(CPUState)); + /** * env_archcpu(env) * @env: The architecture environment @@ -445,7 +449,7 @@ static inline void cpu_set_cpustate_pointers(ArchCPU *c= pu) */ static inline ArchCPU *env_archcpu(CPUArchState *env) { - return container_of(env, ArchCPU, env); + return (void *)env - sizeof(CPUState); } =20 /** @@ -456,15 +460,9 @@ static inline ArchCPU *env_archcpu(CPUArchState *env) */ static inline CPUState *env_cpu(CPUArchState *env) { - return &env_archcpu(env)->parent_obj; + return (void *)env - sizeof(CPUState); } =20 -/* - * Validate placement of CPUNegativeOffsetState. - */ -QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) - offsetof(ArchCPU, neg) >=3D - sizeof(CPUNegativeOffsetState) + __alignof(CPUArchState)= ); - /** * env_neg(env) * @env: The architecture environment @@ -473,8 +471,7 @@ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) - offsetof(Arc= hCPU, neg) >=3D */ static inline CPUNegativeOffsetState *env_neg(CPUArchState *env) { - ArchCPU *arch_cpu =3D container_of(env, ArchCPU, env); - return &arch_cpu->neg; + return &env_cpu(env)->neg; } =20 /** @@ -485,8 +482,7 @@ static inline CPUNegativeOffsetState *env_neg(CPUArchSt= ate *env) */ static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu) { - ArchCPU *arch_cpu =3D container_of(cpu, ArchCPU, parent_obj); - return &arch_cpu->neg; + return &cpu->neg; } =20 /** diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 04baa5063c..ed1bf8dbf1 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -345,8 +345,8 @@ typedef union IcountDecr { } IcountDecr; =20 /* - * This structure must be placed in ArchCPU immediately - * before CPUArchState, as a field named "neg". + * Elements of CPUState most efficiently accessed from CPUArchState, + * via small negative offsets. */ typedef struct CPUNegativeOffsetState { CPUTLB tlb; @@ -453,6 +453,9 @@ struct qemu_work_item; * dirty ring structure. * * State of one CPU core or thread. + * + * Align, in order to match possible alignment required by CPUArchState, + * and eliminate a hole between CPUState and CPUArchState within ArchCPU. */ struct CPUState { /*< private >*/ @@ -571,8 +574,18 @@ struct CPUState { =20 /* track IOMMUs whose translations we've cached in the TCG TLB */ GArray *iommu_notifiers; + + /* + * MUST BE LAST in order to minimize the displacement to CPUArchState. + */ + char neg_align[-sizeof(CPUNegativeOffsetState) % 16] QEMU_ALIGNED(16); + CPUNegativeOffsetState neg; }; =20 +/* Validate placement of CPUNegativeOffsetState. */ +QEMU_BUILD_BUG_ON(sizeof(CPUState) !=3D=20 + offsetof(CPUState, neg) + sizeof(CPUNegativeOffsetState)= ); + typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; extern CPUTailQ cpus; =20 diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 13306665af..e2a467ec17 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -263,7 +263,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 - CPUNegativeOffsetState neg; CPUAlphaState env; =20 /* This alarm doesn't exist in real hardware; we wish it did. */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f2e3dc49a6..51963b6545 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -856,7 +856,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 - CPUNegativeOffsetState neg; CPUARMState env; =20 /* Coprocessor information */ diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 7225174668..4ce22d8e4f 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -148,7 +148,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 - CPUNegativeOffsetState neg; CPUAVRState env; }; =20 diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 8e37c6e50d..676b8e93ca 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -178,7 +178,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 - CPUNegativeOffsetState neg; CPUCRISState env; }; =20 diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index daef5c3f00..10cd1efd57 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -141,7 +141,7 @@ struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ - CPUNegativeOffsetState neg; + CPUHexagonState env; =20 bool lldb_compat; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index fa13694dab..7557f884b5 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -231,7 +231,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 - CPUNegativeOffsetState neg; CPUHPPAState env; QEMUTimer *alarm_timer; }; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index fbb05eace5..e1b41c29f0 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1900,7 +1900,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 - CPUNegativeOffsetState neg; CPUX86State env; VMChangeStateEntry *vmsentry; =20 diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 4d7201995a..3b5ec51928 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -373,7 +373,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 - CPUNegativeOffsetState neg; CPULoongArchState env; QEMUTimer timer; uint32_t phy_id; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index cf70282717..20afb0c94d 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -168,7 +168,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 - CPUNegativeOffsetState neg; CPUM68KState env; }; =20 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index f6cab6ce19..e43c49d4af 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -345,15 +345,15 @@ typedef struct { struct ArchCPU { /*< private >*/ CPUState parent_obj; - /*< public >*/ + + CPUMBState env; + bool ns_axi_dp; bool ns_axi_ip; bool ns_axi_dc; bool ns_axi_ic; =20 - CPUNegativeOffsetState neg; - CPUMBState env; MicroBlazeCPUConfig cfg; }; =20 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 6d6af1f2a8..67f8e8b988 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1213,10 +1213,10 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 + CPUMIPSState env; + Clock *clock; Clock *count_div; /* Divider for CP0_Count clock */ - CPUNegativeOffsetState neg; - CPUMIPSState env; }; =20 =20 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 477a3161fd..70b6377a4f 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -218,7 +218,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 - CPUNegativeOffsetState neg; CPUNios2State env; =20 bool diverr_present; diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index ce4d605eb7..334997e9a1 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -305,7 +305,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 - CPUNegativeOffsetState neg; CPUOpenRISCState env; }; =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 173e4c351a..f5027616fa 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1317,7 +1317,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 - CPUNegativeOffsetState neg; CPUPPCState env; =20 int vcpu_id; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6316cbcc23..ef9cf21c0c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -388,7 +388,7 @@ struct ArchCPU { /* < private > */ CPUState parent_obj; /* < public > */ - CPUNegativeOffsetState neg; + CPURISCVState env; =20 char *dyn_csr_xml; diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 7f03ffcfed..f66754eb8a 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -111,7 +111,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 - CPUNegativeOffsetState neg; CPURXState env; }; =20 diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 304029e57c..7bea7075e1 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -170,7 +170,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 - CPUNegativeOffsetState neg; CPUS390XState env; S390CPUModel *model; /* needed for live migration */ diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 1399d3840f..f75a235973 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -208,7 +208,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 - CPUNegativeOffsetState neg; CPUSH4State env; }; =20 diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 98044572f2..b3a98f1d74 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -561,7 +561,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 - CPUNegativeOffsetState neg; CPUSPARCState env; }; =20 diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 3708405be8..217937bbf6 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -192,7 +192,6 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 - CPUNegativeOffsetState neg; CPUTriCoreState env; }; =20 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 87fe992ba6..c6bbef1e5d 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -560,9 +560,8 @@ struct ArchCPU { CPUState parent_obj; /*< public >*/ =20 - Clock *clock; - CPUNegativeOffsetState neg; CPUXtensaState env; + Clock *clock; }; =20 =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index b2d4e22c17..098d99b5d4 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -344,8 +344,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->page_bits =3D TARGET_PAGE_BITS; tcg_ctx->page_mask =3D TARGET_PAGE_MASK; tcg_ctx->tlb_dyn_max_bits =3D CPU_TLB_DYN_MAX_BITS; - tcg_ctx->tlb_fast_offset =3D - (int)offsetof(ArchCPU, neg.tlb.f) - (int)offsetof(ArchCPU, env); + tcg_ctx->tlb_fast_offset =3D (int)offsetof(ArchCPU, parent_obj.neg.tlb= .f) + - (int)offsetof(ArchCPU, env); #endif tcg_ctx->insn_start_words =3D TARGET_INSN_START_WORDS; #ifdef TCG_GUEST_DEFAULT_MO diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 1a6a5448c8..54190c785b 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -53,8 +53,8 @@ static TCGOp *gen_tb_start(uint32_t cflags) TCGOp *icount_start_insn =3D NULL; =20 tcg_gen_ld_i32(count, cpu_env, - offsetof(ArchCPU, neg.icount_decr.u32) - - offsetof(ArchCPU, env)); + offsetof(ArchCPU, parent_obj.neg.icount_decr.u32) + - offsetof(ArchCPU, env)); =20 if (cflags & CF_USE_ICOUNT) { /* @@ -82,8 +82,8 @@ static TCGOp *gen_tb_start(uint32_t cflags) =20 if (cflags & CF_USE_ICOUNT) { tcg_gen_st16_i32(count, cpu_env, - offsetof(ArchCPU, neg.icount_decr.u16.low) - - offsetof(ArchCPU, env)); + offsetof(ArchCPU, parent_obj.neg.icount_decr.u16.= low) + - offsetof(ArchCPU, env)); /* * cpu->can_do_io is cleared automatically here at the beginning of * each translation block. The cost is minimal and only paid for --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900804; cv=none; d=zohomail.com; s=zohoarc; b=EjAb3V21ZtscaeUS8Rxy3lYQBnWGA08izvNA56yxtzrwobVqahH5ZBOC7AHnnVcd8cMH2r+rmP2coxaKrvNy6/guyoOBVajMA0VzObHgChjdiiGAUzdJwEgyvIxSjOpoOZjTMZ1+lDCtUPmnAn+SzGPH/Vse3xBI6TEQkUrSU/Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900804; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/HEEMFcGWCyxqTgAPUxdG/wjpw2eKp2fOJzvzeuqm9E=; b=OhsTe7Zc/C4pNTkgOCHx9RxBBUuyF45W0GJc0X74v9IPk2gmdyc5cpd997nTq1B0aY2mU+LFKr7qD1agGdX8USLGhdaE+2wFZSKA6DmwKhLNs0FVgvpPERzwwCLUoQc2/NRdWNVzDfb7xU8iWdrhKZ7hnl+MV6LouVFa9R/Ax+A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16949008046342.48952040240772; Sat, 16 Sep 2023 14:46:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd2q-00056A-Je; Sat, 16 Sep 2023 17:41:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd2l-00055V-Kd for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:35 -0400 Received: from mail-oo1-xc2c.google.com ([2607:f8b0:4864:20::c2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd2j-0000Qy-MZ for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:34 -0400 Received: by mail-oo1-xc2c.google.com with SMTP id 006d021491bc7-57325fcd970so1985680eaf.1 for ; Sat, 16 Sep 2023 14:41:33 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900492; x=1695505292; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/HEEMFcGWCyxqTgAPUxdG/wjpw2eKp2fOJzvzeuqm9E=; b=ihi4ZrGwJoUA0KCQtUf7z6VC1n5nkoVp7ugXLmALbBZZvTpJ+rM3le3GEsyZ4+t/ZH UV5kDHYDv+qU153oygWmx1Bm49Mn+UnhW1pnCDqj0oTIkR4C/DNjwPco3oK32AVURFH+ KmJoEy6FcrKW8og3pJuDr0ZeLftBxRoIMWgfXcp8205ytRqnUqjefwofVuT+VS9PDHbw N6B/aw4pJmLWQ465+cOd0VU8hNJQPNRcmT70rgSP2MrYnwpAOvlpbnTcGzFckH613WGv 3Cy2a1fI23oPMA4kWIu8Hz0EGJKiSUnx0lqh9hqq+vnjRcgIh21IsTxMkKFgY5A+9w7x nvbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900492; x=1695505292; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/HEEMFcGWCyxqTgAPUxdG/wjpw2eKp2fOJzvzeuqm9E=; b=qj3NXZeznmjIj2OTaYvFgTTkrYa6Fi1+CqxKeYpucBuaz7WIyLbJOsA0+ft5uy2/Ku xqZbgzDL5/5FrlXbRZVyEya+kBUP93UqUxgCy83Oxuj4eJ+hSOdXeLXFqEzjDKlkzGJY 5se/ej0/F0jIMsRUKToMib5C8aUAgKmkASgmqqa9oYFHRpXaKLGTA2ljaE+/jt8JyJZO O4a4qYM1MAfB1dKj+DPdcDaqjiKtHvtwUaWZr9yOMEkmaGSq67B9B4uZCpqyiTYHKNX/ xEMHWC8Z2PJ0GQrmb5aRSzENrDByigBmqJ9lHpO2MwjWbQAtC3AaMN2LgxJ7eS4mVoAg VrdQ== X-Gm-Message-State: AOJu0YxwANNQApSkTUEx+/NnaIAIIqIwiqCEMq86EgMiI9zfyuhD6w2q ezgkckYqUyujxVmmNiFSdf/m6MXwczKCYWNDy9I= X-Google-Smtp-Source: AGHT+IF7MkPq+iitWogy7NUgfjckz2J//JOxxg6H1fd9Dm4vLtLkwRy8gGk2O/fABggREf9wIHdJtQ== X-Received: by 2002:a05:6358:9389:b0:142:fd2b:d30c with SMTP id h9-20020a056358938900b00142fd2bd30cmr5866353rwb.23.1694900492427; Sat, 16 Sep 2023 14:41:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 08/39] accel/tcg: Remove CPUState.icount_decr_ptr Date: Sat, 16 Sep 2023 14:40:52 -0700 Message-Id: <20230916214123.525796-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2c; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900806098100001 Content-Type: text/plain; charset="utf-8" We can now access icount_decr directly. Reviewed-by: Anton Johansson Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 1 - include/hw/core/cpu.h | 2 -- hw/core/cpu-common.c | 4 ++-- 3 files changed, 2 insertions(+), 5 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 165a271642..94fe80c979 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -434,7 +434,6 @@ void tcg_exec_unrealizefn(CPUState *cpu); static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) { cpu->parent_obj.env_ptr =3D &cpu->env; - cpu->parent_obj.icount_decr_ptr =3D &cpu->parent_obj.neg.icount_decr; } =20 /* Validate correct placement of CPUArchState. */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index ed1bf8dbf1..4609cf1ae0 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -429,7 +429,6 @@ struct qemu_work_item; * @as: Pointer to the first AddressSpace, for the convenience of targets = which * only have a single AddressSpace * @env_ptr: Pointer to subclass-specific CPUArchState field. - * @icount_decr_ptr: Pointer to IcountDecr field within subclass. * @gdb_regs: Additional GDB registers. * @gdb_num_regs: Number of total registers accessible to GDB. * @gdb_num_g_regs: Number of registers in GDB 'g' packets. @@ -504,7 +503,6 @@ struct CPUState { MemoryRegion *memory; =20 CPUArchState *env_ptr; - IcountDecr *icount_decr_ptr; =20 CPUJumpCache *tb_jmp_cache; =20 diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index ced66c2b34..08d5bbc873 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -86,7 +86,7 @@ void cpu_exit(CPUState *cpu) qatomic_set(&cpu->exit_request, 1); /* Ensure cpu_exec will see the exit request after TCG has exited. */ smp_wmb(); - qatomic_set(&cpu->icount_decr_ptr->u16.high, -1); + qatomic_set(&cpu->neg.icount_decr.u16.high, -1); } =20 static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, in= t reg) @@ -130,7 +130,7 @@ static void cpu_common_reset_hold(Object *obj) cpu->halted =3D cpu->start_powered_off; cpu->mem_io_pc =3D 0; cpu->icount_extra =3D 0; - qatomic_set(&cpu->icount_decr_ptr->u32, 0); + qatomic_set(&cpu->neg.icount_decr.u32, 0); cpu->can_do_io =3D 1; cpu->exception_index =3D -1; cpu->crash_occurred =3D false; --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900550; cv=none; d=zohomail.com; s=zohoarc; b=H0IAVtefvkQ2qUuLOjcRUYhTIV2cV4ym3a/bcvChxtHi/ma5yDT8EH/RfiFO6MNp8rT6Cvqulaf6bAG+UnevzqWzzKw4WBsgRY85TAKLntV8nqGfLGe+g7pNZivCl09pC/zhWBhCIP6ZCId5+trwFbKwM6dMMh79y/HlnxQxvx4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900550; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HBhsboT09KyjKosBF/aAd6AnLWjogoV21dS+/Gecdmc=; b=GQ6y+XJpbQh77sqjwT1P5rMZaeSIs4/PI99V3rWmuUe86Ehiru2qwdNdnGDHld86VK8wsF5qOvR1GPjTpN+UC+Mn0oSmwnGUD4iykRzsZoawzDFYDerjfFWzaq3EfaQH8R+1J7kytdzZvFTYRqqyXdt3jPEJU+yPKLx/EKHV6UE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900549944937.1055746114056; Sat, 16 Sep 2023 14:42:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd2t-00057u-6S; Sat, 16 Sep 2023 17:41:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd2n-00055r-48 for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:37 -0400 Received: from mail-ot1-x332.google.com ([2607:f8b0:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd2k-0000RG-Pe for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:36 -0400 Received: by mail-ot1-x332.google.com with SMTP id 46e09a7af769-6bd0a0a6766so2164834a34.2 for ; Sat, 16 Sep 2023 14:41:34 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900493; x=1695505293; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HBhsboT09KyjKosBF/aAd6AnLWjogoV21dS+/Gecdmc=; b=DOKWVkDxeeXQJSFekbcL0jUTihrsKOkUkY0d51TnKEvRzdXVBDotLhX4tdmKUN0jON BylJW+/sD09hW+WpOuCjxCito8o80/fzFAbNGsfdsUaTqC7oGI2/WrsqmwvbedIvfRlo vQFiyflbEX9fNUr0mOYIrsVYCvyaKG8TD9QiAqtTSuU7N9RUORK2HFiPQ78Aa7/0VdMc /e3a6KT7y5cqqmvMs2UkOWysyMn798HU/oiQyxyxU1SYJsVPdK3WYFEsDdlD3znzkvhZ XYXWEW5Xuz+u237Np4yyOsGqVLZWWPE58YKJLjNEnwOCkeAoUeKipgVOllsMxwp8ogZz XEOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900493; x=1695505293; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HBhsboT09KyjKosBF/aAd6AnLWjogoV21dS+/Gecdmc=; b=UMhUlCCrKI8/8RV+F6AzUniq3HDO/vWULODvWc3+FQwfT9fdKhX1yTljRlbjqhF6vi DCuCa9Bjg/dhJcMRVAR3M/JHKjUnWk0RDiCGKlflOHq22Qtnfd6063SwxrvquYVrB9Wa 8Z31xA1XPe8UMWcQ70VPAd9s1XjEZgYuT8/Uy9mRrTyv/5yw0zRlBFU9AeWluz8FlpGi hodq1KAmhPBEdfdov4TJCoSX6Ma82mkgiacf91fDilp2sXRLRSAF0dWuslVXzHBiQugZ sOgTxw8kWgyrX8LRpJoGKd6bJF/NYiQAQHvClNDmDhsxAPVy3YxYAtEOwdedGooIC5ly VVGA== X-Gm-Message-State: AOJu0YxZZS3YfM/tw9Hf/Wbcu16gV9qjpuWzhprNWm0lwqF3+QwqEXCi FLdutcH2QIdckObOcdckQPO73R0k2A5BhP02YOs= X-Google-Smtp-Source: AGHT+IG8xaXM+rnfPN1Jarip+XTlseeZwNv2fFlPFm3lrGWQux9h423eMm/JT3y2V/ndcwvamVi+Uw== X-Received: by 2002:a05:6358:2907:b0:134:cd32:3565 with SMTP id y7-20020a056358290700b00134cd323565mr5087467rwb.31.1694900493346; Sat, 16 Sep 2023 14:41:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 09/39] accel/tcg: Move can_do_io to CPUNegativeOffsetState Date: Sat, 16 Sep 2023 14:40:53 -0700 Message-Id: <20230916214123.525796-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900551524100003 Minimize the displacement to can_do_io, since it may be touched at the start of each TranslationBlock. It fits into other padding within the substructure. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 2 +- accel/dummy-cpus.c | 2 +- accel/kvm/kvm-accel-ops.c | 2 +- accel/tcg/cpu-exec-common.c | 2 +- accel/tcg/cpu-exec.c | 2 +- accel/tcg/cputlb.c | 2 +- accel/tcg/tcg-accel-ops-icount.c | 2 +- accel/tcg/tcg-accel-ops-mttcg.c | 2 +- accel/tcg/tcg-accel-ops-rr.c | 4 ++-- accel/tcg/translator.c | 4 ++-- hw/core/cpu-common.c | 2 +- softmmu/icount.c | 2 +- softmmu/watchpoint.c | 2 +- 13 files changed, 15 insertions(+), 15 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 4609cf1ae0..819ff1ef2e 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -350,6 +350,7 @@ typedef union IcountDecr { */ typedef struct CPUNegativeOffsetState { CPUTLB tlb; + uint32_t can_do_io; IcountDecr icount_decr; } CPUNegativeOffsetState; =20 @@ -547,7 +548,6 @@ struct CPUState { int cluster_index; uint32_t tcg_cflags; uint32_t halted; - uint32_t can_do_io; int32_t exception_index; =20 AccelCPUState *accel; diff --git a/accel/dummy-cpus.c b/accel/dummy-cpus.c index d6a1b8d0a2..af7f90a4da 100644 --- a/accel/dummy-cpus.c +++ b/accel/dummy-cpus.c @@ -27,7 +27,7 @@ static void *dummy_cpu_thread_fn(void *arg) qemu_mutex_lock_iothread(); qemu_thread_get_self(cpu->thread); cpu->thread_id =3D qemu_get_thread_id(); - cpu->can_do_io =3D 1; + cpu->neg.can_do_io =3D 1; current_cpu =3D cpu; =20 #ifndef _WIN32 diff --git a/accel/kvm/kvm-accel-ops.c b/accel/kvm/kvm-accel-ops.c index 457eafa380..b610c0d378 100644 --- a/accel/kvm/kvm-accel-ops.c +++ b/accel/kvm/kvm-accel-ops.c @@ -36,7 +36,7 @@ static void *kvm_vcpu_thread_fn(void *arg) qemu_mutex_lock_iothread(); qemu_thread_get_self(cpu->thread); cpu->thread_id =3D qemu_get_thread_id(); - cpu->can_do_io =3D 1; + cpu->neg.can_do_io =3D 1; current_cpu =3D cpu; =20 r =3D kvm_init_vcpu(cpu, &error_fatal); diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index 7e35d7f4b5..8ac2af4d0c 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -36,7 +36,7 @@ void cpu_loop_exit_noexc(CPUState *cpu) void cpu_loop_exit(CPUState *cpu) { /* Undo the setting in cpu_tb_exec. */ - cpu->can_do_io =3D 1; + cpu->neg.can_do_io =3D 1; /* Undo any setting in generated code. */ qemu_plugin_disable_mem_helpers(cpu); siglongjmp(cpu->jmp_env, 1); diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index e2c494e75e..b01e3e5dc8 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -455,7 +455,7 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *= tb_exit) =20 qemu_thread_jit_execute(); ret =3D tcg_qemu_tb_exec(env, tb_ptr); - cpu->can_do_io =3D 1; + cpu->neg.can_do_io =3D 1; qemu_plugin_disable_mem_helpers(cpu); /* * TODO: Delay swapping back to the read-write region of the TB diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3270f65c20..d69e046b80 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1361,7 +1361,7 @@ io_prepare(hwaddr *out_offset, CPUArchState *env, hwa= ddr xlat, section =3D iotlb_to_section(cpu, xlat, attrs); mr_offset =3D (xlat & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc =3D retaddr; - if (!cpu->can_do_io) { + if (!cpu->neg.can_do_io) { cpu_io_recompile(cpu, retaddr); } =20 diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-ico= unt.c index 3d2cfbbc97..0af643b217 100644 --- a/accel/tcg/tcg-accel-ops-icount.c +++ b/accel/tcg/tcg-accel-ops-icount.c @@ -153,7 +153,7 @@ void icount_handle_interrupt(CPUState *cpu, int mask) =20 tcg_handle_interrupt(cpu, mask); if (qemu_cpu_is_self(cpu) && - !cpu->can_do_io + !cpu->neg.can_do_io && (mask & ~old_mask) !=3D 0) { cpu_abort(cpu, "Raised interrupt while not in I/O function"); } diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttc= g.c index 4b0dfb4be7..785481dea3 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -80,7 +80,7 @@ static void *mttcg_cpu_thread_fn(void *arg) qemu_thread_get_self(cpu->thread); =20 cpu->thread_id =3D qemu_get_thread_id(); - cpu->can_do_io =3D 1; + cpu->neg.can_do_io =3D 1; current_cpu =3D cpu; cpu_thread_signal_created(cpu); qemu_guest_random_seed_thread_part2(cpu->random_seed); diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index 2d523289a8..c0aceb0a04 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -192,7 +192,7 @@ static void *rr_cpu_thread_fn(void *arg) qemu_thread_get_self(cpu->thread); =20 cpu->thread_id =3D qemu_get_thread_id(); - cpu->can_do_io =3D 1; + cpu->neg.can_do_io =3D 1; cpu_thread_signal_created(cpu); qemu_guest_random_seed_thread_part2(cpu->random_seed); =20 @@ -334,7 +334,7 @@ void rr_start_vcpu_thread(CPUState *cpu) cpu->thread =3D single_tcg_cpu_thread; cpu->halt_cond =3D single_tcg_halt_cond; cpu->thread_id =3D first_cpu->thread_id; - cpu->can_do_io =3D 1; + cpu->neg.can_do_io =3D 1; cpu->created =3D true; } } diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 54190c785b..888302160c 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -19,7 +19,7 @@ static void gen_io_start(void) { tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, - offsetof(ArchCPU, parent_obj.can_do_io) - + offsetof(ArchCPU, parent_obj.neg.can_do_io) - offsetof(ArchCPU, env)); } =20 @@ -92,7 +92,7 @@ static TCGOp *gen_tb_start(uint32_t cflags) * go with gen_io_start(). */ tcg_gen_st_i32(tcg_constant_i32(0), cpu_env, - offsetof(ArchCPU, parent_obj.can_do_io) - + offsetof(ArchCPU, parent_obj.neg.can_do_io) - offsetof(ArchCPU, env)); } =20 diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 08d5bbc873..f0e07f3ae7 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -131,7 +131,7 @@ static void cpu_common_reset_hold(Object *obj) cpu->mem_io_pc =3D 0; cpu->icount_extra =3D 0; qatomic_set(&cpu->neg.icount_decr.u32, 0); - cpu->can_do_io =3D 1; + cpu->neg.can_do_io =3D 1; cpu->exception_index =3D -1; cpu->crash_occurred =3D false; cpu->cflags_next_tb =3D -1; diff --git a/softmmu/icount.c b/softmmu/icount.c index 144e24829c..956d15e343 100644 --- a/softmmu/icount.c +++ b/softmmu/icount.c @@ -111,7 +111,7 @@ static int64_t icount_get_raw_locked(void) CPUState *cpu =3D current_cpu; =20 if (cpu && cpu->running) { - if (!cpu->can_do_io) { + if (!cpu->neg.can_do_io) { error_report("Bad icount read"); exit(1); } diff --git a/softmmu/watchpoint.c b/softmmu/watchpoint.c index 5350163385..45d1f12faf 100644 --- a/softmmu/watchpoint.c +++ b/softmmu/watchpoint.c @@ -177,7 +177,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, va= ddr len, * Force recompile to succeed, because icount may * be read only at the end of the block. */ - if (!cpu->can_do_io) { + if (!cpu->neg.can_do_io) { /* Force execution of one insn next time. */ cpu->cflags_next_tb =3D 1 | CF_LAST_IO | CF_NOIRQ | curr_cflags(cpu); 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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900494; x=1695505294; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=En35xg7nXjvXLsrzg+GNnaGBjlT+fgROcZr2z/jSKT4=; b=cE0dfn3ApjeME4mhmJzcYa8+3kZMOUeLJXl/n5Su36/bNftWPqJYkN6nCVy71KCMfZ zbwqPFxl1CmVo8xLtH2s9e3LcluIfsD0smfvgC4DskzCjmtvQkGddTR3F2PQ/4YMnKpH VYU/kVs+GpOkH8zSYFE5Yhy3G0PFvSz8/tnKLy4EbVDHCukayE6QG7D/n2hSB0YsGJwf BxxmMxdwLhQbxPetEAd1OLAM/t28Y4UfH20JOXWnpJLIWtOAP+D0QXE+IxEU5um8hGNY +/A0GmvaIQGwylTp6sn5r/SRDT/0UDu7i5Cp1WDV9jB7c9eTcoCSIVmedOqaHD7LjRBV e5CA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900494; x=1695505294; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=En35xg7nXjvXLsrzg+GNnaGBjlT+fgROcZr2z/jSKT4=; b=uwRDhguAahm322tUPN4ntTi/bCEHH3llH5FodqdaQWaGnYa737t6vXdu2ZMJuijnGN 1493rKUEZ3+i4x2aREgCrF1XqacpDSysMUr2uQ62Sl3b/DLcChdM5k59PYpzcCkJUnY9 vkDEG+fIVPr9PpRtFHmHwoZYhMjlBvDv3Ha41LIxIlmwuvsQ8vmXzuQugbG16Xqwq7v/ qL5VgxFN3Y2eo5+O+waC8Nio2v15vFP7wGWwU0Yqi9SifeJGbIT3bFlnlbDP71sApN4s YTJppk1BfLxMts9af3Kct0oopHrqBprNw7LBtiudu5/7jhceGRAszWoPjg9fQ3hqEaXN mhag== X-Gm-Message-State: AOJu0YzC8yz9vplUNSH/0BWiRC1B2WtRsExSYK5jDx59hQ37U9uECZ/R NUD6NB/Tb+09mjCFYYresHmBUAqkMyqpfI1QG/c= X-Google-Smtp-Source: AGHT+IGXWRBpi7P4yFxqpf883hLaeWGA/3DyFOAk1K8jC6JinQ/Yq28OeaqSEM9ac1cdI2Dkh+WK1A== X-Received: by 2002:aa7:88d4:0:b0:68e:3d83:e501 with SMTP id k20-20020aa788d4000000b0068e3d83e501mr6708724pff.13.1694900494283; Sat, 16 Sep 2023 14:41:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 10/39] accel/tcg: Remove cpu_neg() Date: Sat, 16 Sep 2023 14:40:54 -0700 Message-Id: <20230916214123.525796-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900660211100001 Now that CPUNegativeOffsetState is part of CPUState, we can reference it directly. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 11 ----------- include/exec/exec-all.h | 2 +- accel/tcg/cpu-exec.c | 14 +++++++------- accel/tcg/tcg-accel-ops-icount.c | 6 +++--- accel/tcg/tcg-accel-ops.c | 2 +- accel/tcg/translate-all.c | 6 +++--- softmmu/icount.c | 2 +- 7 files changed, 16 insertions(+), 27 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 94fe80c979..fcd6ddac6a 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -473,17 +473,6 @@ static inline CPUNegativeOffsetState *env_neg(CPUArchS= tate *env) return &env_cpu(env)->neg; } =20 -/** - * cpu_neg(cpu) - * @cpu: The generic CPUState - * - * Return the CPUNegativeOffsetState associated with the cpu. - */ -static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu) -{ - return &cpu->neg; -} - /** * env_tlb(env) * @env: The architecture environment diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index b2f5cd4c2a..2e4d337805 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -71,7 +71,7 @@ G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintp= tr_t pc); */ static inline bool cpu_loop_exit_requested(CPUState *cpu) { - return (int32_t)qatomic_read(&cpu_neg(cpu)->icount_decr.u32) < 0; + return (int32_t)qatomic_read(&cpu->neg.icount_decr.u32) < 0; } =20 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index b01e3e5dc8..4abbd037f3 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -73,7 +73,7 @@ static void align_clocks(SyncClocks *sc, CPUState *cpu) return; } =20 - cpu_icount =3D cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low; + cpu_icount =3D cpu->icount_extra + cpu->neg.icount_decr.u16.low; sc->diff_clk +=3D icount_to_ns(sc->last_cpu_icount - cpu_icount); sc->last_cpu_icount =3D cpu_icount; =20 @@ -124,7 +124,7 @@ static void init_delay_params(SyncClocks *sc, CPUState = *cpu) sc->realtime_clock =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT); sc->diff_clk =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_= clock; sc->last_cpu_icount - =3D cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low; + =3D cpu->icount_extra + cpu->neg.icount_decr.u16.low; if (sc->diff_clk < max_delay) { max_delay =3D sc->diff_clk; } @@ -717,7 +717,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, = int *ret) if (cpu->exception_index < 0) { #ifndef CONFIG_USER_ONLY if (replay_has_exception() - && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra =3D= =3D 0) { + && cpu->neg.icount_decr.u16.low + cpu->icount_extra =3D=3D 0) { /* Execute just one insn to trigger exception pending in the l= og */ cpu->cflags_next_tb =3D (curr_cflags(cpu) & ~CF_USE_ICOUNT) | CF_NOIRQ | 1; @@ -807,7 +807,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, * Ensure zeroing happens before reading cpu->exit_request or * cpu->interrupt_request (see also smp_wmb in cpu_exit()) */ - qatomic_set_mb(&cpu_neg(cpu)->icount_decr.u16.high, 0); + qatomic_set_mb(&cpu->neg.icount_decr.u16.high, 0); =20 if (unlikely(qatomic_read(&cpu->interrupt_request))) { int interrupt_request; @@ -898,7 +898,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, if (unlikely(qatomic_read(&cpu->exit_request)) || (icount_enabled() && (cpu->cflags_next_tb =3D=3D -1 || cpu->cflags_next_tb & CF_= USE_ICOUNT) - && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra =3D= =3D 0)) { + && cpu->neg.icount_decr.u16.low + cpu->icount_extra =3D=3D 0))= { qatomic_set(&cpu->exit_request, 0); if (cpu->exception_index =3D=3D -1) { cpu->exception_index =3D EXCP_INTERRUPT; @@ -923,7 +923,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, Tran= slationBlock *tb, } =20 *last_tb =3D NULL; - insns_left =3D qatomic_read(&cpu_neg(cpu)->icount_decr.u32); + insns_left =3D qatomic_read(&cpu->neg.icount_decr.u32); if (insns_left < 0) { /* Something asked us to stop executing chained TBs; just * continue round the main loop. Whatever requested the exit @@ -942,7 +942,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, Tran= slationBlock *tb, icount_update(cpu); /* Refill decrementer and continue execution. */ insns_left =3D MIN(0xffff, cpu->icount_budget); - cpu_neg(cpu)->icount_decr.u16.low =3D insns_left; + cpu->neg.icount_decr.u16.low =3D insns_left; cpu->icount_extra =3D cpu->icount_budget - insns_left; =20 /* diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-ico= unt.c index 0af643b217..b25685fb71 100644 --- a/accel/tcg/tcg-accel-ops-icount.c +++ b/accel/tcg/tcg-accel-ops-icount.c @@ -111,14 +111,14 @@ void icount_prepare_for_run(CPUState *cpu, int64_t cp= u_budget) * each vCPU execution. However u16.high can be raised * asynchronously by cpu_exit/cpu_interrupt/tcg_handle_interrupt */ - g_assert(cpu_neg(cpu)->icount_decr.u16.low =3D=3D 0); + g_assert(cpu->neg.icount_decr.u16.low =3D=3D 0); g_assert(cpu->icount_extra =3D=3D 0); =20 replay_mutex_lock(); =20 cpu->icount_budget =3D MIN(icount_get_limit(), cpu_budget); insns_left =3D MIN(0xffff, cpu->icount_budget); - cpu_neg(cpu)->icount_decr.u16.low =3D insns_left; + cpu->neg.icount_decr.u16.low =3D insns_left; cpu->icount_extra =3D cpu->icount_budget - insns_left; =20 if (cpu->icount_budget =3D=3D 0) { @@ -138,7 +138,7 @@ void icount_process_data(CPUState *cpu) icount_update(cpu); =20 /* Reset the counters */ - cpu_neg(cpu)->icount_decr.u16.low =3D 0; + cpu->neg.icount_decr.u16.low =3D 0; cpu->icount_extra =3D 0; cpu->icount_budget =3D 0; =20 diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 3973591508..d885cc1d3c 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -91,7 +91,7 @@ void tcg_handle_interrupt(CPUState *cpu, int mask) if (!qemu_cpu_is_self(cpu)) { qemu_cpu_kick(cpu); } else { - qatomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1); + qatomic_set(&cpu->neg.icount_decr.u16.high, -1); } } =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 098d99b5d4..ed0c7ef7ce 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -214,7 +214,7 @@ void cpu_restore_state_from_tb(CPUState *cpu, Translati= onBlock *tb, * Reset the cycle counter to the start of the block and * shift if to the number of actually executed instructions. */ - cpu_neg(cpu)->icount_decr.u16.low +=3D insns_left; + cpu->neg.icount_decr.u16.low +=3D insns_left; } =20 cpu->cc->tcg_ops->restore_state_to_opc(cpu, tb, data); @@ -623,7 +623,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) cc =3D CPU_GET_CLASS(cpu); if (cc->tcg_ops->io_recompile_replay_branch && cc->tcg_ops->io_recompile_replay_branch(cpu, tb)) { - cpu_neg(cpu)->icount_decr.u16.low++; + cpu->neg.icount_decr.u16.low++; n =3D 2; } =20 @@ -779,7 +779,7 @@ void cpu_interrupt(CPUState *cpu, int mask) { g_assert(qemu_mutex_iothread_locked()); cpu->interrupt_request |=3D mask; - qatomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1); + qatomic_set(&cpu->neg.icount_decr.u16.high, -1); } =20 #endif /* CONFIG_USER_ONLY */ diff --git a/softmmu/icount.c b/softmmu/icount.c index 956d15e343..4527bfbd6e 100644 --- a/softmmu/icount.c +++ b/softmmu/icount.c @@ -75,7 +75,7 @@ static void icount_enable_adaptive(void) static int64_t icount_get_executed(CPUState *cpu) { return (cpu->icount_budget - - (cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra)); + (cpu->neg.icount_decr.u16.low + cpu->icount_extra)); } =20 /* --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900673; cv=none; d=zohomail.com; s=zohoarc; b=aSfymE8999TU+Je3qUmED26+Ry+9Lbl6N/jlf6q2az2YDEGKYqk12dFQiSXzwa5i2KOBjg5B0NNidls+zf21eFbHJ9zk05hp2Fxe3mqW0JlKwYmjCNV6zF1ilSaxt88Eb4qOhO3QVb5IofJyQgNnmkb0lFGCGD+8+jzw+pgTBi0= ARC-Message-Signature: i=1; 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 2 +- target/arm/tcg/translate-a32.h | 2 +- target/arm/tcg/translate-a64.h | 4 +- target/arm/tcg/translate.h | 16 +- target/hexagon/gen_tcg.h | 120 +- target/hexagon/gen_tcg_hvx.h | 20 +- target/hexagon/macros.h | 8 +- target/mips/tcg/translate.h | 6 +- accel/tcg/plugin-gen.c | 8 +- accel/tcg/translator.c | 8 +- target/alpha/translate.c | 142 +- target/arm/tcg/translate-a64.c | 374 ++--- target/arm/tcg/translate-m-nocp.c | 24 +- target/arm/tcg/translate-mve.c | 52 +- target/arm/tcg/translate-neon.c | 78 +- target/arm/tcg/translate-sme.c | 8 +- target/arm/tcg/translate-sve.c | 172 +-- target/arm/tcg/translate-vfp.c | 56 +- target/arm/tcg/translate.c | 228 +-- target/avr/translate.c | 64 +- target/cris/translate.c | 68 +- target/hexagon/genptr.c | 36 +- target/hexagon/idef-parser/parser-helpers.c | 2 +- target/hexagon/translate.c | 48 +- target/hppa/translate.c | 144 +- target/i386/tcg/translate.c | 580 ++++---- target/loongarch/translate.c | 18 +- target/m68k/translate.c | 302 ++-- target/microblaze/translate.c | 50 +- target/mips/tcg/lcsr_translate.c | 6 +- target/mips/tcg/msa_translate.c | 34 +- target/mips/tcg/mxu_translate.c | 4 +- target/mips/tcg/translate.c | 1284 ++++++++--------- target/mips/tcg/vr54xx_translate.c | 2 +- target/nios2/translate.c | 48 +- target/openrisc/translate.c | 84 +- target/ppc/translate.c | 362 ++--- target/riscv/translate.c | 50 +- target/rx/translate.c | 56 +- target/s390x/tcg/translate.c | 424 +++--- target/sh4/translate.c | 124 +- target/sparc/translate.c | 328 ++--- target/tricore/translate.c | 220 +-- target/xtensa/translate.c | 188 +-- tcg/tcg-op-gvec.c | 300 ++-- tcg/tcg-op-ldst.c | 22 +- tcg/tcg-op.c | 2 +- tcg/tcg.c | 4 +- target/cris/translate_v10.c.inc | 28 +- target/i386/tcg/decode-new.c.inc | 2 +- target/i386/tcg/emit.c.inc | 262 ++-- .../loongarch/insn_trans/trans_atomic.c.inc | 4 +- .../loongarch/insn_trans/trans_branch.c.inc | 2 +- target/loongarch/insn_trans/trans_extra.c.inc | 10 +- .../loongarch/insn_trans/trans_farith.c.inc | 6 +- target/loongarch/insn_trans/trans_fcmp.c.inc | 8 +- .../loongarch/insn_trans/trans_fmemory.c.inc | 8 +- target/loongarch/insn_trans/trans_fmov.c.inc | 20 +- target/loongarch/insn_trans/trans_lsx.c.inc | 44 +- .../loongarch/insn_trans/trans_memory.c.inc | 8 +- .../insn_trans/trans_privileged.c.inc | 52 +- target/mips/tcg/micromips_translate.c.inc | 12 +- target/mips/tcg/nanomips_translate.c.inc | 200 +-- target/ppc/power8-pmu-regs.c.inc | 8 +- target/ppc/translate/branch-impl.c.inc | 2 +- target/ppc/translate/dfp-impl.c.inc | 22 +- target/ppc/translate/fixedpoint-impl.c.inc | 2 +- target/ppc/translate/fp-impl.c.inc | 50 +- .../ppc/translate/processor-ctrl-impl.c.inc | 8 +- target/ppc/translate/spe-impl.c.inc | 30 +- target/ppc/translate/storage-ctrl-impl.c.inc | 26 +- target/ppc/translate/vmx-impl.c.inc | 34 +- target/ppc/translate/vsx-impl.c.inc | 54 +- .../riscv/insn_trans/trans_privileged.c.inc | 8 +- target/riscv/insn_trans/trans_rvbf16.c.inc | 10 +- target/riscv/insn_trans/trans_rvd.c.inc | 48 +- target/riscv/insn_trans/trans_rvf.c.inc | 46 +- target/riscv/insn_trans/trans_rvh.c.inc | 8 +- target/riscv/insn_trans/trans_rvi.c.inc | 16 +- target/riscv/insn_trans/trans_rvm.c.inc | 16 +- target/riscv/insn_trans/trans_rvv.c.inc | 130 +- target/riscv/insn_trans/trans_rvvk.c.inc | 30 +- target/riscv/insn_trans/trans_rvzce.c.inc | 2 +- target/riscv/insn_trans/trans_rvzfa.c.inc | 38 +- target/riscv/insn_trans/trans_rvzfh.c.inc | 54 +- target/riscv/insn_trans/trans_rvzicbo.c.inc | 8 +- target/riscv/insn_trans/trans_svinval.c.inc | 6 +- target/riscv/insn_trans/trans_xthead.c.inc | 2 +- target/s390x/tcg/translate_vx.c.inc | 104 +- target/hexagon/README | 10 +- target/hexagon/gen_tcg_funcs.py | 16 +- 91 files changed, 3818 insertions(+), 3818 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index c9c6d770d0..3cdbeaf460 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -577,7 +577,7 @@ static inline bool temp_readonly(TCGTemp *ts) extern __thread TCGContext *tcg_ctx; extern const void *tcg_code_gen_epilogue; extern uintptr_t tcg_splitwx_diff; -extern TCGv_env cpu_env; +extern TCGv_env tcg_env; =20 bool in_code_gen_buffer(const void *p); =20 diff --git a/target/arm/tcg/translate-a32.h b/target/arm/tcg/translate-a32.h index 48a15379d2..19de6e0a1a 100644 --- a/target/arm/tcg/translate-a32.h +++ b/target/arm/tcg/translate-a32.h @@ -55,7 +55,7 @@ bool mve_skip_vmov(DisasContext *s, int vn, int index, in= t size); static inline TCGv_i32 load_cpu_offset(int offset) { TCGv_i32 tmp =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp, cpu_env, offset); + tcg_gen_ld_i32(tmp, tcg_env, offset); return tmp; } =20 diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h index b55dc435fc..96ba39b37e 100644 --- a/target/arm/tcg/translate-a64.h +++ b/target/arm/tcg/translate-a64.h @@ -115,7 +115,7 @@ static inline int vec_full_reg_offset(DisasContext *s, = int regno) static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno) { TCGv_ptr ret =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(ret, cpu_env, vec_full_reg_offset(s, regno)); + tcg_gen_addi_ptr(ret, tcg_env, vec_full_reg_offset(s, regno)); return ret; } =20 @@ -179,7 +179,7 @@ static inline int pred_gvec_reg_size(DisasContext *s) static inline TCGv_ptr pred_full_reg_ptr(DisasContext *s, int regno) { TCGv_ptr ret =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(ret, cpu_env, pred_full_reg_offset(s, regno)); + tcg_gen_addi_ptr(ret, tcg_env, pred_full_reg_offset(s, regno)); return ret; } =20 diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index f748ba6f39..e189d87019 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -329,7 +329,7 @@ static inline TCGv_i32 get_ahp_flag(void) { TCGv_i32 ret =3D tcg_temp_new_i32(); =20 - tcg_gen_ld_i32(ret, cpu_env, + tcg_gen_ld_i32(ret, tcg_env, offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR])); tcg_gen_extract_i32(ret, ret, 26, 1); =20 @@ -343,9 +343,9 @@ static inline void set_pstate_bits(uint32_t bits) =20 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); =20 - tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate)); tcg_gen_ori_i32(p, p, bits); - tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate)); } =20 /* Clear bits within PSTATE. */ @@ -355,9 +355,9 @@ static inline void clear_pstate_bits(uint32_t bits) =20 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); =20 - tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate)); tcg_gen_andi_i32(p, p, ~bits); - tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate)); } =20 /* If the singlestep state is Active-not-pending, advance to Active-pendin= g. */ @@ -374,7 +374,7 @@ static inline void gen_swstep_exception(DisasContext *s= , int isv, int ex) { /* Fill in the same_el field of the syndrome in the helper. */ uint32_t syn =3D syn_swstep(false, isv, ex); - gen_helper_exception_swstep(cpu_env, tcg_constant_i32(syn)); + gen_helper_exception_swstep(tcg_env, tcg_constant_i32(syn)); } =20 /* @@ -557,7 +557,7 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour = flavour) default: g_assert_not_reached(); } - tcg_gen_addi_ptr(statusptr, cpu_env, offset); + tcg_gen_addi_ptr(statusptr, tcg_env, offset); return statusptr; } =20 @@ -679,7 +679,7 @@ static inline void set_disas_label(DisasContext *s, Dis= asLabel l) static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key) { TCGv_ptr ret =3D tcg_temp_new_ptr(); - gen_helper_lookup_cp_reg(ret, cpu_env, tcg_constant_i32(key)); + gen_helper_lookup_cp_reg(ret, tcg_env, tcg_constant_i32(key)); return ret; } =20 diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index d78d99d155..d992059fce 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -591,8 +591,8 @@ */ #define fGEN_TCG_A5_ACS(SHORTCODE) \ do { \ - gen_helper_vacsh_pred(PeV, cpu_env, RxxV, RssV, RttV); \ - gen_helper_vacsh_val(RxxV, cpu_env, RxxV, RssV, RttV, \ + gen_helper_vacsh_pred(PeV, tcg_env, RxxV, RssV, RttV); \ + gen_helper_vacsh_val(RxxV, tcg_env, RxxV, RssV, RttV, \ tcg_constant_tl(ctx->need_commit)); \ } while (0) =20 @@ -614,7 +614,7 @@ #define fGEN_TCG_F2_sfrecipa(SHORTCODE) \ do { \ TCGv_i64 tmp =3D tcg_temp_new_i64(); \ - gen_helper_sfrecipa(tmp, cpu_env, RsV, RtV); \ + gen_helper_sfrecipa(tmp, tcg_env, RsV, RtV); \ tcg_gen_extrh_i64_i32(RdV, tmp); \ tcg_gen_extrl_i64_i32(PeV, tmp); \ } while (0) @@ -629,7 +629,7 @@ #define fGEN_TCG_F2_sfinvsqrta(SHORTCODE) \ do { \ TCGv_i64 tmp =3D tcg_temp_new_i64(); \ - gen_helper_sfinvsqrta(tmp, cpu_env, RsV); \ + gen_helper_sfinvsqrta(tmp, tcg_env, RsV); \ tcg_gen_extrh_i64_i32(RdV, tmp); \ tcg_gen_extrl_i64_i32(PeV, tmp); \ } while (0) @@ -1205,122 +1205,122 @@ =20 /* Floating point */ #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \ - gen_helper_conv_sf2df(RddV, cpu_env, RsV) + gen_helper_conv_sf2df(RddV, tcg_env, RsV) #define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \ - gen_helper_conv_df2sf(RdV, cpu_env, RssV) + gen_helper_conv_df2sf(RdV, tcg_env, RssV) #define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \ - gen_helper_conv_uw2sf(RdV, cpu_env, RsV) + gen_helper_conv_uw2sf(RdV, tcg_env, RsV) #define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \ - gen_helper_conv_uw2df(RddV, cpu_env, RsV) + gen_helper_conv_uw2df(RddV, tcg_env, RsV) #define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \ - gen_helper_conv_w2sf(RdV, cpu_env, RsV) + gen_helper_conv_w2sf(RdV, tcg_env, RsV) #define fGEN_TCG_F2_conv_w2df(SHORTCODE) \ - gen_helper_conv_w2df(RddV, cpu_env, RsV) + gen_helper_conv_w2df(RddV, tcg_env, RsV) #define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \ - gen_helper_conv_ud2sf(RdV, cpu_env, RssV) + gen_helper_conv_ud2sf(RdV, tcg_env, RssV) #define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \ - gen_helper_conv_ud2df(RddV, cpu_env, RssV) + gen_helper_conv_ud2df(RddV, tcg_env, RssV) #define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \ - gen_helper_conv_d2sf(RdV, cpu_env, RssV) + gen_helper_conv_d2sf(RdV, tcg_env, RssV) #define fGEN_TCG_F2_conv_d2df(SHORTCODE) \ - gen_helper_conv_d2df(RddV, cpu_env, RssV) + gen_helper_conv_d2df(RddV, tcg_env, RssV) #define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \ - gen_helper_conv_sf2uw(RdV, cpu_env, RsV) + gen_helper_conv_sf2uw(RdV, tcg_env, RsV) #define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \ - gen_helper_conv_sf2w(RdV, cpu_env, RsV) + gen_helper_conv_sf2w(RdV, tcg_env, RsV) #define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \ - gen_helper_conv_sf2ud(RddV, cpu_env, RsV) + gen_helper_conv_sf2ud(RddV, tcg_env, RsV) #define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \ - gen_helper_conv_sf2d(RddV, cpu_env, RsV) + gen_helper_conv_sf2d(RddV, tcg_env, RsV) #define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \ - gen_helper_conv_df2uw(RdV, cpu_env, RssV) + gen_helper_conv_df2uw(RdV, tcg_env, RssV) #define fGEN_TCG_F2_conv_df2w(SHORTCODE) \ - gen_helper_conv_df2w(RdV, cpu_env, RssV) + gen_helper_conv_df2w(RdV, tcg_env, RssV) #define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \ - gen_helper_conv_df2ud(RddV, cpu_env, RssV) + gen_helper_conv_df2ud(RddV, tcg_env, RssV) #define fGEN_TCG_F2_conv_df2d(SHORTCODE) \ - gen_helper_conv_df2d(RddV, cpu_env, RssV) + gen_helper_conv_df2d(RddV, tcg_env, RssV) #define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \ - gen_helper_conv_sf2uw_chop(RdV, cpu_env, RsV) + gen_helper_conv_sf2uw_chop(RdV, tcg_env, RsV) #define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \ - gen_helper_conv_sf2w_chop(RdV, cpu_env, RsV) + gen_helper_conv_sf2w_chop(RdV, tcg_env, RsV) #define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \ - gen_helper_conv_sf2ud_chop(RddV, cpu_env, RsV) + gen_helper_conv_sf2ud_chop(RddV, tcg_env, RsV) #define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \ - gen_helper_conv_sf2d_chop(RddV, cpu_env, RsV) + gen_helper_conv_sf2d_chop(RddV, tcg_env, RsV) #define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \ - gen_helper_conv_df2uw_chop(RdV, cpu_env, RssV) + gen_helper_conv_df2uw_chop(RdV, tcg_env, RssV) #define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \ - gen_helper_conv_df2w_chop(RdV, cpu_env, RssV) + gen_helper_conv_df2w_chop(RdV, tcg_env, RssV) #define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \ - gen_helper_conv_df2ud_chop(RddV, cpu_env, RssV) + gen_helper_conv_df2ud_chop(RddV, tcg_env, RssV) #define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \ - gen_helper_conv_df2d_chop(RddV, cpu_env, RssV) + gen_helper_conv_df2d_chop(RddV, tcg_env, RssV) #define fGEN_TCG_F2_sfadd(SHORTCODE) \ - gen_helper_sfadd(RdV, cpu_env, RsV, RtV) + gen_helper_sfadd(RdV, tcg_env, RsV, RtV) #define fGEN_TCG_F2_sfsub(SHORTCODE) \ - gen_helper_sfsub(RdV, cpu_env, RsV, RtV) + gen_helper_sfsub(RdV, tcg_env, RsV, RtV) #define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \ - gen_helper_sfcmpeq(PdV, cpu_env, RsV, RtV) + gen_helper_sfcmpeq(PdV, tcg_env, RsV, RtV) #define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \ - gen_helper_sfcmpgt(PdV, cpu_env, RsV, RtV) + gen_helper_sfcmpgt(PdV, tcg_env, RsV, RtV) #define fGEN_TCG_F2_sfcmpge(SHORTCODE) \ - gen_helper_sfcmpge(PdV, cpu_env, RsV, RtV) + gen_helper_sfcmpge(PdV, tcg_env, RsV, RtV) #define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \ - gen_helper_sfcmpuo(PdV, cpu_env, RsV, RtV) + gen_helper_sfcmpuo(PdV, tcg_env, RsV, RtV) #define fGEN_TCG_F2_sfmax(SHORTCODE) \ - gen_helper_sfmax(RdV, cpu_env, RsV, RtV) + gen_helper_sfmax(RdV, tcg_env, RsV, RtV) #define fGEN_TCG_F2_sfmin(SHORTCODE) \ - gen_helper_sfmin(RdV, cpu_env, RsV, RtV) + gen_helper_sfmin(RdV, tcg_env, RsV, RtV) #define fGEN_TCG_F2_sfclass(SHORTCODE) \ do { \ TCGv imm =3D tcg_constant_tl(uiV); \ - gen_helper_sfclass(PdV, cpu_env, RsV, imm); \ + gen_helper_sfclass(PdV, tcg_env, RsV, imm); \ } while (0) #define fGEN_TCG_F2_sffixupn(SHORTCODE) \ - gen_helper_sffixupn(RdV, cpu_env, RsV, RtV) + gen_helper_sffixupn(RdV, tcg_env, RsV, RtV) #define fGEN_TCG_F2_sffixupd(SHORTCODE) \ - gen_helper_sffixupd(RdV, cpu_env, RsV, RtV) + gen_helper_sffixupd(RdV, tcg_env, RsV, RtV) #define fGEN_TCG_F2_sffixupr(SHORTCODE) \ - gen_helper_sffixupr(RdV, cpu_env, RsV) + gen_helper_sffixupr(RdV, tcg_env, RsV) #define fGEN_TCG_F2_dfadd(SHORTCODE) \ - gen_helper_dfadd(RddV, cpu_env, RssV, RttV) + gen_helper_dfadd(RddV, tcg_env, RssV, RttV) #define fGEN_TCG_F2_dfsub(SHORTCODE) \ - gen_helper_dfsub(RddV, cpu_env, RssV, RttV) + gen_helper_dfsub(RddV, tcg_env, RssV, RttV) #define fGEN_TCG_F2_dfmax(SHORTCODE) \ - gen_helper_dfmax(RddV, cpu_env, RssV, RttV) + gen_helper_dfmax(RddV, tcg_env, RssV, RttV) #define fGEN_TCG_F2_dfmin(SHORTCODE) \ - gen_helper_dfmin(RddV, cpu_env, RssV, RttV) + gen_helper_dfmin(RddV, tcg_env, RssV, RttV) #define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \ - gen_helper_dfcmpeq(PdV, cpu_env, RssV, RttV) + gen_helper_dfcmpeq(PdV, tcg_env, RssV, RttV) #define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \ - gen_helper_dfcmpgt(PdV, cpu_env, RssV, RttV) + gen_helper_dfcmpgt(PdV, tcg_env, RssV, RttV) #define fGEN_TCG_F2_dfcmpge(SHORTCODE) \ - gen_helper_dfcmpge(PdV, cpu_env, RssV, RttV) + gen_helper_dfcmpge(PdV, tcg_env, RssV, RttV) #define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \ - gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV) + gen_helper_dfcmpuo(PdV, tcg_env, RssV, RttV) #define fGEN_TCG_F2_dfclass(SHORTCODE) \ do { \ TCGv imm =3D tcg_constant_tl(uiV); \ - gen_helper_dfclass(PdV, cpu_env, RssV, imm); \ + gen_helper_dfclass(PdV, tcg_env, RssV, imm); \ } while (0) #define fGEN_TCG_F2_sfmpy(SHORTCODE) \ - gen_helper_sfmpy(RdV, cpu_env, RsV, RtV) + gen_helper_sfmpy(RdV, tcg_env, RsV, RtV) #define fGEN_TCG_F2_sffma(SHORTCODE) \ - gen_helper_sffma(RxV, cpu_env, RxV, RsV, RtV) + gen_helper_sffma(RxV, tcg_env, RxV, RsV, RtV) #define fGEN_TCG_F2_sffma_sc(SHORTCODE) \ - gen_helper_sffma_sc(RxV, cpu_env, RxV, RsV, RtV, PuV) + gen_helper_sffma_sc(RxV, tcg_env, RxV, RsV, RtV, PuV) #define fGEN_TCG_F2_sffms(SHORTCODE) \ - gen_helper_sffms(RxV, cpu_env, RxV, RsV, RtV) + gen_helper_sffms(RxV, tcg_env, RxV, RsV, RtV) #define fGEN_TCG_F2_sffma_lib(SHORTCODE) \ - gen_helper_sffma_lib(RxV, cpu_env, RxV, RsV, RtV) + gen_helper_sffma_lib(RxV, tcg_env, RxV, RsV, RtV) #define fGEN_TCG_F2_sffms_lib(SHORTCODE) \ - gen_helper_sffms_lib(RxV, cpu_env, RxV, RsV, RtV) + gen_helper_sffms_lib(RxV, tcg_env, RxV, RsV, RtV) =20 #define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \ - gen_helper_dfmpyfix(RddV, cpu_env, RssV, RttV) + gen_helper_dfmpyfix(RddV, tcg_env, RssV, RttV) #define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \ - gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV) + gen_helper_dfmpyhh(RxxV, tcg_env, RxxV, RssV, RttV) =20 /* Nothing to do for these in qemu, need to suppress compiler warnings */ #define fGEN_TCG_Y4_l2fetch(SHORTCODE) \ @@ -1367,6 +1367,6 @@ uiV =3D uiV; \ tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \ TCGv excp =3D tcg_constant_tl(HEX_EXCP_TRAP0); \ - gen_helper_raise_exception(cpu_env, excp); \ + gen_helper_raise_exception(tcg_env, excp); \ } while (0) #endif diff --git a/target/hexagon/gen_tcg_hvx.h b/target/hexagon/gen_tcg_hvx.h index 44bae53f8d..0da64d467e 100644 --- a/target/hexagon/gen_tcg_hvx.h +++ b/target/hexagon/gen_tcg_hvx.h @@ -43,7 +43,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) #define fGEN_TCG_V6_vhist(SHORTCODE) \ if (!ctx->pre_commit) { \ assert_vhist_tmp(ctx); \ - gen_helper_vhist(cpu_env); \ + gen_helper_vhist(tcg_env); \ } #define fGEN_TCG_V6_vhistq(SHORTCODE) \ do { \ @@ -53,13 +53,13 @@ static inline void assert_vhist_tmp(DisasContext *ctx) sizeof(MMVector), sizeof(MMVector)); \ } else { \ assert_vhist_tmp(ctx); \ - gen_helper_vhistq(cpu_env); \ + gen_helper_vhistq(tcg_env); \ } \ } while (0) #define fGEN_TCG_V6_vwhist256(SHORTCODE) \ if (!ctx->pre_commit) { \ assert_vhist_tmp(ctx); \ - gen_helper_vwhist256(cpu_env); \ + gen_helper_vwhist256(tcg_env); \ } #define fGEN_TCG_V6_vwhist256q(SHORTCODE) \ do { \ @@ -69,13 +69,13 @@ static inline void assert_vhist_tmp(DisasContext *ctx) sizeof(MMVector), sizeof(MMVector)); \ } else { \ assert_vhist_tmp(ctx); \ - gen_helper_vwhist256q(cpu_env); \ + gen_helper_vwhist256q(tcg_env); \ } \ } while (0) #define fGEN_TCG_V6_vwhist256_sat(SHORTCODE) \ if (!ctx->pre_commit) { \ assert_vhist_tmp(ctx); \ - gen_helper_vwhist256_sat(cpu_env); \ + gen_helper_vwhist256_sat(tcg_env); \ } #define fGEN_TCG_V6_vwhist256q_sat(SHORTCODE) \ do { \ @@ -85,13 +85,13 @@ static inline void assert_vhist_tmp(DisasContext *ctx) sizeof(MMVector), sizeof(MMVector)); \ } else { \ assert_vhist_tmp(ctx); \ - gen_helper_vwhist256q_sat(cpu_env); \ + gen_helper_vwhist256q_sat(tcg_env); \ } \ } while (0) #define fGEN_TCG_V6_vwhist128(SHORTCODE) \ if (!ctx->pre_commit) { \ assert_vhist_tmp(ctx); \ - gen_helper_vwhist128(cpu_env); \ + gen_helper_vwhist128(tcg_env); \ } #define fGEN_TCG_V6_vwhist128q(SHORTCODE) \ do { \ @@ -101,14 +101,14 @@ static inline void assert_vhist_tmp(DisasContext *ctx) sizeof(MMVector), sizeof(MMVector)); \ } else { \ assert_vhist_tmp(ctx); \ - gen_helper_vwhist128q(cpu_env); \ + gen_helper_vwhist128q(tcg_env); \ } \ } while (0) #define fGEN_TCG_V6_vwhist128m(SHORTCODE) \ if (!ctx->pre_commit) { \ TCGv tcgv_uiV =3D tcg_constant_tl(uiV); \ assert_vhist_tmp(ctx); \ - gen_helper_vwhist128m(cpu_env, tcgv_uiV); \ + gen_helper_vwhist128m(tcg_env, tcgv_uiV); \ } #define fGEN_TCG_V6_vwhist128qm(SHORTCODE) \ do { \ @@ -119,7 +119,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx) } else { \ TCGv tcgv_uiV =3D tcg_constant_tl(uiV); \ assert_vhist_tmp(ctx); \ - gen_helper_vwhist128qm(cpu_env, tcgv_uiV); \ + gen_helper_vwhist128qm(tcg_env, tcgv_uiV); \ } \ } while (0) =20 diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 5451b061ee..b356d85792 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -147,7 +147,7 @@ __builtin_choose_expr(TYPE_TCGV(X), \ gen_store1, (void)0)) #define MEM_STORE1(VA, DATA, SLOT) \ - MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, SLOT) + MEM_STORE1_FUNC(DATA)(tcg_env, VA, DATA, SLOT) =20 #define MEM_STORE2_FUNC(X) \ __builtin_choose_expr(TYPE_INT(X), \ @@ -155,7 +155,7 @@ __builtin_choose_expr(TYPE_TCGV(X), \ gen_store2, (void)0)) #define MEM_STORE2(VA, DATA, SLOT) \ - MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, SLOT) + MEM_STORE2_FUNC(DATA)(tcg_env, VA, DATA, SLOT) =20 #define MEM_STORE4_FUNC(X) \ __builtin_choose_expr(TYPE_INT(X), \ @@ -163,7 +163,7 @@ __builtin_choose_expr(TYPE_TCGV(X), \ gen_store4, (void)0)) #define MEM_STORE4(VA, DATA, SLOT) \ - MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, SLOT) + MEM_STORE4_FUNC(DATA)(tcg_env, VA, DATA, SLOT) =20 #define MEM_STORE8_FUNC(X) \ __builtin_choose_expr(TYPE_INT(X), \ @@ -171,7 +171,7 @@ __builtin_choose_expr(TYPE_TCGV_I64(X), \ gen_store8, (void)0)) #define MEM_STORE8(VA, DATA, SLOT) \ - MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, SLOT) + MEM_STORE8_FUNC(DATA)(tcg_env, VA, DATA, SLOT) #else #define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, pkt_has_store_s1, slot, VA)) #define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, pkt_has_store_s1, slot, VA= )) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index db3dc932c7..cffcfeab8c 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -123,15 +123,15 @@ enum { }; =20 #define gen_helper_0e1i(name, arg1, arg2) do { \ - gen_helper_##name(cpu_env, arg1, tcg_constant_i32(arg2)); \ + gen_helper_##name(tcg_env, arg1, tcg_constant_i32(arg2)); \ } while (0) =20 #define gen_helper_1e0i(name, ret, arg1) do { \ - gen_helper_##name(ret, cpu_env, tcg_constant_i32(arg1)); \ + gen_helper_##name(ret, tcg_env, tcg_constant_i32(arg1)); \ } while (0) =20 #define gen_helper_0e2i(name, arg1, arg2, arg3) do { \ - gen_helper_##name(cpu_env, arg1, arg2, tcg_constant_i32(arg3));\ + gen_helper_##name(tcg_env, arg1, arg2, tcg_constant_i32(arg3));\ } while (0) =20 void generate_exception(DisasContext *ctx, int excp); diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 5c13615112..985c980c92 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -104,7 +104,7 @@ static void gen_empty_udata_cb(void) TCGv_ptr udata =3D tcg_temp_ebb_new_ptr(); =20 tcg_gen_movi_ptr(udata, 0); - tcg_gen_ld_i32(cpu_index, cpu_env, + tcg_gen_ld_i32(cpu_index, tcg_env, -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index)= ); gen_helper_plugin_vcpu_udata_cb(cpu_index, udata); =20 @@ -138,7 +138,7 @@ static void gen_empty_mem_cb(TCGv_i64 addr, uint32_t in= fo) =20 tcg_gen_movi_i32(meminfo, info); tcg_gen_movi_ptr(udata, 0); - tcg_gen_ld_i32(cpu_index, cpu_env, + tcg_gen_ld_i32(cpu_index, tcg_env, -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index)= ); =20 gen_helper_plugin_vcpu_mem_cb(cpu_index, meminfo, addr, udata); @@ -157,7 +157,7 @@ static void gen_empty_mem_helper(void) TCGv_ptr ptr =3D tcg_temp_ebb_new_ptr(); =20 tcg_gen_movi_ptr(ptr, 0); - tcg_gen_st_ptr(ptr, cpu_env, offsetof(CPUState, plugin_mem_cbs) - + tcg_gen_st_ptr(ptr, tcg_env, offsetof(CPUState, plugin_mem_cbs) - offsetof(ArchCPU, env)); tcg_temp_free_ptr(ptr); } @@ -581,7 +581,7 @@ void plugin_gen_disable_mem_helpers(void) if (!tcg_ctx->plugin_tb->mem_helper) { return; } - tcg_gen_st_ptr(tcg_constant_ptr(NULL), cpu_env, + tcg_gen_st_ptr(tcg_constant_ptr(NULL), tcg_env, offsetof(CPUState, plugin_mem_cbs) - offsetof(ArchCPU, = env)); } =20 diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 888302160c..d9fcb4cbe8 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -18,7 +18,7 @@ =20 static void gen_io_start(void) { - tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, + tcg_gen_st_i32(tcg_constant_i32(1), tcg_env, offsetof(ArchCPU, parent_obj.neg.can_do_io) - offsetof(ArchCPU, env)); } @@ -52,7 +52,7 @@ static TCGOp *gen_tb_start(uint32_t cflags) TCGv_i32 count =3D tcg_temp_new_i32(); TCGOp *icount_start_insn =3D NULL; =20 - tcg_gen_ld_i32(count, cpu_env, + tcg_gen_ld_i32(count, tcg_env, offsetof(ArchCPU, parent_obj.neg.icount_decr.u32) - offsetof(ArchCPU, env)); =20 @@ -81,7 +81,7 @@ static TCGOp *gen_tb_start(uint32_t cflags) } =20 if (cflags & CF_USE_ICOUNT) { - tcg_gen_st16_i32(count, cpu_env, + tcg_gen_st16_i32(count, tcg_env, offsetof(ArchCPU, parent_obj.neg.icount_decr.u16.= low) - offsetof(ArchCPU, env)); /* @@ -91,7 +91,7 @@ static TCGOp *gen_tb_start(uint32_t cflags) * translator. Doing it here means we don't need a gen_io_end() to * go with gen_io_start(). */ - tcg_gen_st_i32(tcg_constant_i32(0), cpu_env, + tcg_gen_st_i32(tcg_constant_i32(0), tcg_env, offsetof(ArchCPU, parent_obj.neg.can_do_io) - offsetof(ArchCPU, env)); } diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 9be912c50c..46af6574bf 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -131,13 +131,13 @@ void alpha_translate_init(void) int i; =20 for (i =3D 0; i < 31; i++) { - cpu_std_ir[i] =3D tcg_global_mem_new_i64(cpu_env, + cpu_std_ir[i] =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUAlphaState, ir[= i]), greg_names[i]); } =20 for (i =3D 0; i < 31; i++) { - cpu_fir[i] =3D tcg_global_mem_new_i64(cpu_env, + cpu_fir[i] =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUAlphaState, fir[i]= ), freg_names[i]); } @@ -146,7 +146,7 @@ void alpha_translate_init(void) memcpy(cpu_pal_ir, cpu_std_ir, sizeof(cpu_pal_ir)); for (i =3D 0; i < 8; i++) { int r =3D (i =3D=3D 7 ? 25 : i + 8); - cpu_pal_ir[r] =3D tcg_global_mem_new_i64(cpu_env, + cpu_pal_ir[r] =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUAlphaState, shadow[i]), shadow_names[i]); @@ -155,7 +155,7 @@ void alpha_translate_init(void) =20 for (i =3D 0; i < ARRAY_SIZE(vars); ++i) { const GlobalVar *v =3D &vars[i]; - *v->var =3D tcg_global_mem_new_i64(cpu_env, v->ofs, v->name); + *v->var =3D tcg_global_mem_new_i64(tcg_env, v->ofs, v->name); } } =20 @@ -244,12 +244,12 @@ static int get_flag_ofs(unsigned shift) =20 static void ld_flag_byte(TCGv val, unsigned shift) { - tcg_gen_ld8u_i64(val, cpu_env, get_flag_ofs(shift)); + tcg_gen_ld8u_i64(val, tcg_env, get_flag_ofs(shift)); } =20 static void st_flag_byte(TCGv val, unsigned shift) { - tcg_gen_st8_i64(val, cpu_env, get_flag_ofs(shift)); + tcg_gen_st8_i64(val, tcg_env, get_flag_ofs(shift)); } =20 static void gen_excp_1(int exception, int error_code) @@ -258,7 +258,7 @@ static void gen_excp_1(int exception, int error_code) =20 tmp1 =3D tcg_constant_i32(exception); tmp2 =3D tcg_constant_i32(error_code); - gen_helper_excp(cpu_env, tmp1, tmp2); + gen_helper_excp(tcg_env, tmp1, tmp2); } =20 static DisasJumpType gen_excp(DisasContext *ctx, int exception, int error_= code) @@ -582,7 +582,7 @@ static void gen_qual_roundmode(DisasContext *ctx, int f= n11) tcg_gen_movi_i32(tmp, float_round_down); break; case QUAL_RM_D: - tcg_gen_ld8u_i32(tmp, cpu_env, + tcg_gen_ld8u_i32(tmp, tcg_env, offsetof(CPUAlphaState, fpcr_dyn_round)); break; } @@ -591,7 +591,7 @@ static void gen_qual_roundmode(DisasContext *ctx, int f= n11) /* ??? The "fpu/softfloat.h" interface is to call set_float_rounding_m= ode. With CONFIG_SOFTFLOAT that expands to an out-of-line call that just sets the one field. */ - tcg_gen_st8_i32(tmp, cpu_env, + tcg_gen_st8_i32(tmp, tcg_env, offsetof(CPUAlphaState, fp_status.float_rounding_mode)= ); #else gen_helper_setroundmode(tmp); @@ -611,7 +611,7 @@ static void gen_qual_flushzero(DisasContext *ctx, int f= n11) tmp =3D tcg_temp_new_i32(); if (fn11) { /* Underflow is enabled, use the FPCR setting. */ - tcg_gen_ld8u_i32(tmp, cpu_env, + tcg_gen_ld8u_i32(tmp, tcg_env, offsetof(CPUAlphaState, fpcr_flush_to_zero)); } else { /* Underflow is disabled, force flush-to-zero. */ @@ -619,7 +619,7 @@ static void gen_qual_flushzero(DisasContext *ctx, int f= n11) } =20 #if defined(CONFIG_SOFTFLOAT_INLINE) - tcg_gen_st8_i32(tmp, cpu_env, + tcg_gen_st8_i32(tmp, tcg_env, offsetof(CPUAlphaState, fp_status.flush_to_zero)); #else gen_helper_setflushzero(tmp); @@ -636,16 +636,16 @@ static TCGv gen_ieee_input(DisasContext *ctx, int reg= , int fn11, int is_cmp) val =3D cpu_fir[reg]; if ((fn11 & QUAL_S) =3D=3D 0) { if (is_cmp) { - gen_helper_ieee_input_cmp(cpu_env, val); + gen_helper_ieee_input_cmp(tcg_env, val); } else { - gen_helper_ieee_input(cpu_env, val); + gen_helper_ieee_input(tcg_env, val); } } else { #ifndef CONFIG_USER_ONLY /* In system mode, raise exceptions for denormals like real hardware. In user mode, proceed as if the OS completion handler is handling the denormal as per spec. */ - gen_helper_ieee_input_s(cpu_env, val); + gen_helper_ieee_input_s(tcg_env, val); #endif } } @@ -678,9 +678,9 @@ static void gen_fp_exc_raise(int rc, int fn11) or if we were to do something clever with imprecise exceptions. */ reg =3D tcg_constant_i32(rc + 32); if (fn11 & QUAL_S) { - gen_helper_fp_exc_raise_s(cpu_env, ign, reg); + gen_helper_fp_exc_raise_s(tcg_env, ign, reg); } else { - gen_helper_fp_exc_raise(cpu_env, ign, reg); + gen_helper_fp_exc_raise(tcg_env, ign, reg); } } =20 @@ -705,7 +705,7 @@ static void gen_ieee_arith2(DisasContext *ctx, gen_qual_flushzero(ctx, fn11); =20 vb =3D gen_ieee_input(ctx, rb, fn11, 0); - helper(dest_fpr(ctx, rc), cpu_env, vb); + helper(dest_fpr(ctx, rc), tcg_env, vb); =20 gen_fp_exc_raise(rc, fn11); } @@ -732,10 +732,10 @@ static void gen_cvttq(DisasContext *ctx, int rb, int = rc, int fn11) /* Almost all integer conversions use cropped rounding; special case that. */ if ((fn11 & QUAL_RM_MASK) =3D=3D QUAL_RM_C) { - gen_helper_cvttq_c(vc, cpu_env, vb); + gen_helper_cvttq_c(vc, tcg_env, vb); } else { gen_qual_roundmode(ctx, fn11); - gen_helper_cvttq(vc, cpu_env, vb); + gen_helper_cvttq(vc, tcg_env, vb); } gen_fp_exc_raise(rc, fn11); } @@ -754,10 +754,10 @@ static void gen_ieee_intcvt(DisasContext *ctx, is inexact. Thus we only need to worry about exceptions when inexact handling is requested. */ if (fn11 & QUAL_I) { - helper(vc, cpu_env, vb); + helper(vc, tcg_env, vb); gen_fp_exc_raise(rc, fn11); } else { - helper(vc, cpu_env, vb); + helper(vc, tcg_env, vb); } } =20 @@ -797,7 +797,7 @@ static void gen_ieee_arith3(DisasContext *ctx, va =3D gen_ieee_input(ctx, ra, fn11, 0); vb =3D gen_ieee_input(ctx, rb, fn11, 0); vc =3D dest_fpr(ctx, rc); - helper(vc, cpu_env, va, vb); + helper(vc, tcg_env, va, vb); =20 gen_fp_exc_raise(rc, fn11); } @@ -826,7 +826,7 @@ static void gen_ieee_compare(DisasContext *ctx, va =3D gen_ieee_input(ctx, ra, fn11, 1); vb =3D gen_ieee_input(ctx, rb, fn11, 1); vc =3D dest_fpr(ctx, rc); - helper(vc, cpu_env, va, vb); + helper(vc, tcg_env, va, vb); =20 gen_fp_exc_raise(rc, fn11); } @@ -1059,12 +1059,12 @@ static DisasJumpType gen_call_pal(DisasContext *ctx= , int palcode) break; case 0x9E: /* RDUNIQUE */ - tcg_gen_ld_i64(ctx->ir[IR_V0], cpu_env, + tcg_gen_ld_i64(ctx->ir[IR_V0], tcg_env, offsetof(CPUAlphaState, unique)); break; case 0x9F: /* WRUNIQUE */ - tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env, + tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env, offsetof(CPUAlphaState, unique)); break; default: @@ -1088,17 +1088,17 @@ static DisasJumpType gen_call_pal(DisasContext *ctx= , int palcode) break; case 0x2D: /* WRVPTPTR */ - tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env, + tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env, offsetof(CPUAlphaState, vptptr)); break; case 0x31: /* WRVAL */ - tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env, + tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env, offsetof(CPUAlphaState, sysval)); break; case 0x32: /* RDVAL */ - tcg_gen_ld_i64(ctx->ir[IR_V0], cpu_env, + tcg_gen_ld_i64(ctx->ir[IR_V0], tcg_env, offsetof(CPUAlphaState, sysval)); break; =20 @@ -1126,23 +1126,23 @@ static DisasJumpType gen_call_pal(DisasContext *ctx= , int palcode) =20 case 0x38: /* WRUSP */ - tcg_gen_st_i64(ctx->ir[IR_A0], cpu_env, + tcg_gen_st_i64(ctx->ir[IR_A0], tcg_env, offsetof(CPUAlphaState, usp)); break; case 0x3A: /* RDUSP */ - tcg_gen_ld_i64(ctx->ir[IR_V0], cpu_env, + tcg_gen_ld_i64(ctx->ir[IR_V0], tcg_env, offsetof(CPUAlphaState, usp)); break; case 0x3C: /* WHAMI */ - tcg_gen_ld32s_i64(ctx->ir[IR_V0], cpu_env, + tcg_gen_ld32s_i64(ctx->ir[IR_V0], tcg_env, -offsetof(AlphaCPU, env) + offsetof(CPUState, cpu_index)); break; =20 case 0x3E: /* WTINT */ - tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, + tcg_gen_st_i32(tcg_constant_i32(1), tcg_env, -offsetof(AlphaCPU, env) + offsetof(CPUState, halted)); tcg_gen_movi_i64(ctx->ir[IR_V0], 0); @@ -1174,7 +1174,7 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, = int palcode) } =20 tcg_gen_movi_i64(tmp, exc_addr); - tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc_addr)); + tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUAlphaState, exc_addr)); =20 entry +=3D (palcode & 0x80 ? 0x2000 + (palcode - 0x80) * 64 @@ -1254,9 +1254,9 @@ static DisasJumpType gen_mfpr(DisasContext *ctx, TCGv= va, int regno) if (data =3D=3D 0) { tcg_gen_movi_i64(va, 0); } else if (data & PR_LONG) { - tcg_gen_ld32s_i64(va, cpu_env, data & ~PR_LONG); + tcg_gen_ld32s_i64(va, tcg_env, data & ~PR_LONG); } else { - tcg_gen_ld_i64(va, cpu_env, data); + tcg_gen_ld_i64(va, tcg_env, data); } break; } @@ -1272,17 +1272,17 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TC= Gv vb, int regno) switch (regno) { case 255: /* TBIA */ - gen_helper_tbia(cpu_env); + gen_helper_tbia(tcg_env); break; =20 case 254: /* TBIS */ - gen_helper_tbis(cpu_env, vb); + gen_helper_tbis(tcg_env, vb); break; =20 case 253: /* WAIT */ - tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, + tcg_gen_st_i32(tcg_constant_i32(1), tcg_env, -offsetof(AlphaCPU, env) + offsetof(CPUState, halte= d)); return gen_excp(ctx, EXCP_HALTED, 0); =20 @@ -1296,16 +1296,16 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TC= Gv vb, int regno) if (translator_io_start(&ctx->base)) { ret =3D DISAS_PC_STALE; } - gen_helper_set_alarm(cpu_env, vb); + gen_helper_set_alarm(tcg_env, vb); break; =20 case 7: /* PALBR */ - tcg_gen_st_i64(vb, cpu_env, offsetof(CPUAlphaState, palbr)); + tcg_gen_st_i64(vb, tcg_env, offsetof(CPUAlphaState, palbr)); /* Changing the PAL base register implies un-chaining all of the T= Bs that ended with a CALL_PAL. Since the base register usually on= ly changes during boot, flushing everything works well. */ - gen_helper_tb_flush(cpu_env); + gen_helper_tb_flush(tcg_env); return DISAS_PC_STALE; =20 case 32 ... 39: @@ -1327,9 +1327,9 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv= vb, int regno) data =3D cpu_pr_data(regno); if (data !=3D 0) { if (data & PR_LONG) { - tcg_gen_st32_i64(vb, cpu_env, data & ~PR_LONG); + tcg_gen_st32_i64(vb, tcg_env, data & ~PR_LONG); } else { - tcg_gen_st_i64(vb, cpu_env, data); + tcg_gen_st_i64(vb, tcg_env, data); } } break; @@ -1594,7 +1594,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_ext32s_i64(vc, vb); tcg_gen_add_i64(tmp, tmp, vc); tcg_gen_ext32s_i64(vc, tmp); - gen_helper_check_overflow(cpu_env, vc, tmp); + gen_helper_check_overflow(tcg_env, vc, tmp); break; case 0x49: /* SUBL/V */ @@ -1603,7 +1603,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_ext32s_i64(vc, vb); tcg_gen_sub_i64(tmp, tmp, vc); tcg_gen_ext32s_i64(vc, tmp); - gen_helper_check_overflow(cpu_env, vc, tmp); + gen_helper_check_overflow(tcg_env, vc, tmp); break; case 0x4D: /* CMPLT */ @@ -1620,7 +1620,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_and_i64(tmp, tmp, tmp2); tcg_gen_shri_i64(tmp, tmp, 63); tcg_gen_movi_i64(tmp2, 0); - gen_helper_check_overflow(cpu_env, tmp, tmp2); + gen_helper_check_overflow(tcg_env, tmp, tmp2); break; case 0x69: /* SUBQ/V */ @@ -1633,7 +1633,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_and_i64(tmp, tmp, tmp2); tcg_gen_shri_i64(tmp, tmp, 63); tcg_gen_movi_i64(tmp2, 0); - gen_helper_check_overflow(cpu_env, tmp, tmp2); + gen_helper_check_overflow(tcg_env, tmp, tmp2); break; case 0x6D: /* CMPLE */ @@ -1924,7 +1924,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tcg_gen_ext32s_i64(vc, vb); tcg_gen_mul_i64(tmp, tmp, vc); tcg_gen_ext32s_i64(vc, tmp); - gen_helper_check_overflow(cpu_env, vc, tmp); + gen_helper_check_overflow(tcg_env, vc, tmp); break; case 0x60: /* MULQ/V */ @@ -1932,7 +1932,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) tmp2 =3D tcg_temp_new(); tcg_gen_muls2_i64(vc, tmp, va, vb); tcg_gen_sari_i64(tmp2, vc, 63); - gen_helper_check_overflow(cpu_env, tmp, tmp2); + gen_helper_check_overflow(tcg_env, tmp, tmp2); break; default: goto invalid_opc; @@ -1957,7 +1957,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) REQUIRE_REG_31(ra); REQUIRE_FEN; vb =3D load_fpr(ctx, rb); - gen_helper_sqrtf(vc, cpu_env, vb); + gen_helper_sqrtf(vc, tcg_env, vb); break; case 0x0B: /* SQRTS */ @@ -1986,7 +1986,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) REQUIRE_REG_31(ra); REQUIRE_FEN; vb =3D load_fpr(ctx, rb); - gen_helper_sqrtg(vc, cpu_env, vb); + gen_helper_sqrtg(vc, tcg_env, vb); break; case 0x02B: /* SQRTT */ @@ -2009,22 +2009,22 @@ static DisasJumpType translate_one(DisasContext *ct= x, uint32_t insn) case 0x00: /* ADDF */ REQUIRE_FEN; - gen_helper_addf(vc, cpu_env, va, vb); + gen_helper_addf(vc, tcg_env, va, vb); break; case 0x01: /* SUBF */ REQUIRE_FEN; - gen_helper_subf(vc, cpu_env, va, vb); + gen_helper_subf(vc, tcg_env, va, vb); break; case 0x02: /* MULF */ REQUIRE_FEN; - gen_helper_mulf(vc, cpu_env, va, vb); + gen_helper_mulf(vc, tcg_env, va, vb); break; case 0x03: /* DIVF */ REQUIRE_FEN; - gen_helper_divf(vc, cpu_env, va, vb); + gen_helper_divf(vc, tcg_env, va, vb); break; case 0x1E: /* CVTDG -- TODO */ @@ -2033,43 +2033,43 @@ static DisasJumpType translate_one(DisasContext *ct= x, uint32_t insn) case 0x20: /* ADDG */ REQUIRE_FEN; - gen_helper_addg(vc, cpu_env, va, vb); + gen_helper_addg(vc, tcg_env, va, vb); break; case 0x21: /* SUBG */ REQUIRE_FEN; - gen_helper_subg(vc, cpu_env, va, vb); + gen_helper_subg(vc, tcg_env, va, vb); break; case 0x22: /* MULG */ REQUIRE_FEN; - gen_helper_mulg(vc, cpu_env, va, vb); + gen_helper_mulg(vc, tcg_env, va, vb); break; case 0x23: /* DIVG */ REQUIRE_FEN; - gen_helper_divg(vc, cpu_env, va, vb); + gen_helper_divg(vc, tcg_env, va, vb); break; case 0x25: /* CMPGEQ */ REQUIRE_FEN; - gen_helper_cmpgeq(vc, cpu_env, va, vb); + gen_helper_cmpgeq(vc, tcg_env, va, vb); break; case 0x26: /* CMPGLT */ REQUIRE_FEN; - gen_helper_cmpglt(vc, cpu_env, va, vb); + gen_helper_cmpglt(vc, tcg_env, va, vb); break; case 0x27: /* CMPGLE */ REQUIRE_FEN; - gen_helper_cmpgle(vc, cpu_env, va, vb); + gen_helper_cmpgle(vc, tcg_env, va, vb); break; case 0x2C: /* CVTGF */ REQUIRE_REG_31(ra); REQUIRE_FEN; - gen_helper_cvtgf(vc, cpu_env, vb); + gen_helper_cvtgf(vc, tcg_env, vb); break; case 0x2D: /* CVTGD -- TODO */ @@ -2079,19 +2079,19 @@ static DisasJumpType translate_one(DisasContext *ct= x, uint32_t insn) /* CVTGQ */ REQUIRE_REG_31(ra); REQUIRE_FEN; - gen_helper_cvtgq(vc, cpu_env, vb); + gen_helper_cvtgq(vc, tcg_env, vb); break; case 0x3C: /* CVTQF */ REQUIRE_REG_31(ra); REQUIRE_FEN; - gen_helper_cvtqf(vc, cpu_env, vb); + gen_helper_cvtqf(vc, tcg_env, vb); break; case 0x3E: /* CVTQG */ REQUIRE_REG_31(ra); REQUIRE_FEN; - gen_helper_cvtqg(vc, cpu_env, vb); + gen_helper_cvtqg(vc, tcg_env, vb); break; default: goto invalid_opc; @@ -2242,7 +2242,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) /* MT_FPCR */ REQUIRE_FEN; va =3D load_fpr(ctx, ra); - gen_helper_store_fpcr(cpu_env, va); + gen_helper_store_fpcr(tcg_env, va); if (ctx->tb_rm =3D=3D QUAL_RM_D) { /* Re-do the copy of the rounding mode to fp_status the next time we use dynamic rounding. */ @@ -2253,7 +2253,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) /* MF_FPCR */ REQUIRE_FEN; va =3D dest_fpr(ctx, ra); - gen_helper_load_fpcr(va, cpu_env); + gen_helper_load_fpcr(va, tcg_env); break; case 0x02A: /* FCMOVEQ */ @@ -2292,7 +2292,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) REQUIRE_FEN; vc =3D dest_fpr(ctx, rc); vb =3D load_fpr(ctx, rb); - gen_helper_cvtql(vc, cpu_env, vb); + gen_helper_cvtql(vc, tcg_env, vb); gen_fp_exc_raise(rc, fn11); break; default: @@ -2332,7 +2332,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) if (translator_io_start(&ctx->base)) { ret =3D DISAS_PC_STALE; } - gen_helper_load_pcc(va, cpu_env); + gen_helper_load_pcc(va, tcg_env); break; case 0xE000: /* RC */ @@ -2628,7 +2628,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) address from EXC_ADDR. This turns out to be useful for our emulation PALcode, so continue to accept it. */ vb =3D dest_sink(ctx); - tcg_gen_ld_i64(vb, cpu_env, offsetof(CPUAlphaState, exc_addr)); + tcg_gen_ld_i64(vb, tcg_env, offsetof(CPUAlphaState, exc_addr)); } else { vb =3D load_gpr(ctx, rb); } diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 07c8f5b53b..cb520efcd0 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -91,16 +91,16 @@ void a64_translate_init(void) { int i; =20 - cpu_pc =3D tcg_global_mem_new_i64(cpu_env, + cpu_pc =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUARMState, pc), "pc"); for (i =3D 0; i < 32; i++) { - cpu_X[i] =3D tcg_global_mem_new_i64(cpu_env, + cpu_X[i] =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUARMState, xregs[i]), regnames[i]); } =20 - cpu_exclusive_high =3D tcg_global_mem_new_i64(cpu_env, + cpu_exclusive_high =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUARMState, exclusive_high), "exclusive_high"); } =20 @@ -139,7 +139,7 @@ static int get_a64_user_mem_index(DisasContext *s) =20 static void set_btype_raw(int val) { - tcg_gen_st_i32(tcg_constant_i32(val), cpu_env, + tcg_gen_st_i32(tcg_constant_i32(val), tcg_env, offsetof(CPUARMState, btype)); } =20 @@ -261,7 +261,7 @@ static void gen_address_with_allocation_tag0(TCGv_i64 d= st, TCGv_i64 src) static void gen_probe_access(DisasContext *s, TCGv_i64 ptr, MMUAccessType acc, int log2_size) { - gen_helper_probe_access(cpu_env, ptr, + gen_helper_probe_access(tcg_env, ptr, tcg_constant_i32(acc), tcg_constant_i32(get_mem_index(s)), tcg_constant_i32(1 << log2_size)); @@ -290,7 +290,7 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, = TCGv_i64 addr, desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, memop_size(memop) - 1); =20 ret =3D tcg_temp_new_i64(); - gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr); + gen_helper_mte_check(ret, tcg_env, tcg_constant_i32(desc), addr); =20 return ret; } @@ -322,7 +322,7 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr,= bool is_write, desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, total_size - 1); =20 ret =3D tcg_temp_new_i64(); - gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr); + gen_helper_mte_check(ret, tcg_env, tcg_constant_i32(desc), addr); =20 return ret; } @@ -358,7 +358,7 @@ static void check_lse2_align(DisasContext *s, int rn, i= nt imm, =20 type =3D is_write ? MMU_DATA_STORE : MMU_DATA_LOAD, mmu_idx =3D get_mem_index(s); - gen_helper_unaligned_access(cpu_env, addr, tcg_constant_i32(type), + gen_helper_unaligned_access(tcg_env, addr, tcg_constant_i32(type), tcg_constant_i32(mmu_idx)); =20 gen_set_label(over_label); @@ -434,13 +434,13 @@ static void a64_test_cc(DisasCompare64 *c64, int cc) =20 static void gen_rebuild_hflags(DisasContext *s) { - gen_helper_rebuild_hflags_a64(cpu_env, tcg_constant_i32(s->current_el)= ); + gen_helper_rebuild_hflags_a64(tcg_env, tcg_constant_i32(s->current_el)= ); } =20 static void gen_exception_internal(int excp) { assert(excp_is_internal(excp)); - gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp)); + gen_helper_exception_internal(tcg_env, tcg_constant_i32(excp)); } =20 static void gen_exception_internal_insn(DisasContext *s, int excp) @@ -453,7 +453,7 @@ static void gen_exception_internal_insn(DisasContext *s= , int excp) static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) { gen_a64_update_pc(s, 0); - gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome)); + gen_helper_exception_bkpt_insn(tcg_env, tcg_constant_i32(syndrome)); s->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -600,7 +600,7 @@ static TCGv_i64 read_fp_dreg(DisasContext *s, int reg) { TCGv_i64 v =3D tcg_temp_new_i64(); =20 - tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64)); + tcg_gen_ld_i64(v, tcg_env, fp_reg_offset(s, reg, MO_64)); return v; } =20 @@ -608,7 +608,7 @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) { TCGv_i32 v =3D tcg_temp_new_i32(); =20 - tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_32)); + tcg_gen_ld_i32(v, tcg_env, fp_reg_offset(s, reg, MO_32)); return v; } =20 @@ -616,7 +616,7 @@ static TCGv_i32 read_fp_hreg(DisasContext *s, int reg) { TCGv_i32 v =3D tcg_temp_new_i32(); =20 - tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16)); + tcg_gen_ld16u_i32(v, tcg_env, fp_reg_offset(s, reg, MO_16)); return v; } =20 @@ -636,7 +636,7 @@ void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) { unsigned ofs =3D fp_reg_offset(s, reg, MO_64); =20 - tcg_gen_st_i64(v, cpu_env, ofs); + tcg_gen_st_i64(v, tcg_env, ofs); clear_vec_high(s, false, reg); } =20 @@ -722,7 +722,7 @@ static void gen_gvec_op3_qc(DisasContext *s, bool is_q,= int rd, int rn, { TCGv_ptr qc_ptr =3D tcg_temp_new_ptr(); =20 - tcg_gen_addi_ptr(qc_ptr, cpu_env, offsetof(CPUARMState, vfp.qc)); + tcg_gen_addi_ptr(qc_ptr, tcg_env, offsetof(CPUARMState, vfp.qc)); tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), vec_full_reg_offset(s, rm), qc_ptr, @@ -1017,7 +1017,7 @@ static void do_fp_st(DisasContext *s, int srcidx, TCG= v_i64 tcg_addr, MemOp mop) /* This writes the bottom N bits of a 128 bit wide vector to memory */ TCGv_i64 tmplo =3D tcg_temp_new_i64(); =20 - tcg_gen_ld_i64(tmplo, cpu_env, fp_reg_offset(s, srcidx, MO_64)); + tcg_gen_ld_i64(tmplo, tcg_env, fp_reg_offset(s, srcidx, MO_64)); =20 if ((mop & MO_SIZE) < MO_128) { tcg_gen_qemu_st_i64(tmplo, tcg_addr, get_mem_index(s), mop); @@ -1025,7 +1025,7 @@ static void do_fp_st(DisasContext *s, int srcidx, TCG= v_i64 tcg_addr, MemOp mop) TCGv_i64 tmphi =3D tcg_temp_new_i64(); TCGv_i128 t16 =3D tcg_temp_new_i128(); =20 - tcg_gen_ld_i64(tmphi, cpu_env, fp_reg_hi_offset(s, srcidx)); + tcg_gen_ld_i64(tmphi, tcg_env, fp_reg_hi_offset(s, srcidx)); tcg_gen_concat_i64_i128(t16, tmplo, tmphi); =20 tcg_gen_qemu_st_i128(t16, tcg_addr, get_mem_index(s), mop); @@ -1052,10 +1052,10 @@ static void do_fp_ld(DisasContext *s, int destidx, = TCGv_i64 tcg_addr, MemOp mop) tcg_gen_extr_i128_i64(tmplo, tmphi, t16); } =20 - tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64)); + tcg_gen_st_i64(tmplo, tcg_env, fp_reg_offset(s, destidx, MO_64)); =20 if (tmphi) { - tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx)); + tcg_gen_st_i64(tmphi, tcg_env, fp_reg_hi_offset(s, destidx)); } clear_vec_high(s, tmphi !=3D NULL, destidx); } @@ -1079,26 +1079,26 @@ static void read_vec_element(DisasContext *s, TCGv_= i64 tcg_dest, int srcidx, int vect_off =3D vec_reg_offset(s, srcidx, element, memop & MO_SIZE); switch ((unsigned)memop) { case MO_8: - tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off); + tcg_gen_ld8u_i64(tcg_dest, tcg_env, vect_off); break; case MO_16: - tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off); + tcg_gen_ld16u_i64(tcg_dest, tcg_env, vect_off); break; case MO_32: - tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off); + tcg_gen_ld32u_i64(tcg_dest, tcg_env, vect_off); break; case MO_8|MO_SIGN: - tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off); + tcg_gen_ld8s_i64(tcg_dest, tcg_env, vect_off); break; case MO_16|MO_SIGN: - tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off); + tcg_gen_ld16s_i64(tcg_dest, tcg_env, vect_off); break; case MO_32|MO_SIGN: - tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off); + tcg_gen_ld32s_i64(tcg_dest, tcg_env, vect_off); break; case MO_64: case MO_64|MO_SIGN: - tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off); + tcg_gen_ld_i64(tcg_dest, tcg_env, vect_off); break; default: g_assert_not_reached(); @@ -1111,20 +1111,20 @@ static void read_vec_element_i32(DisasContext *s, T= CGv_i32 tcg_dest, int srcidx, int vect_off =3D vec_reg_offset(s, srcidx, element, memop & MO_SIZE); switch (memop) { case MO_8: - tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off); + tcg_gen_ld8u_i32(tcg_dest, tcg_env, vect_off); break; case MO_16: - tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off); + tcg_gen_ld16u_i32(tcg_dest, tcg_env, vect_off); break; case MO_8|MO_SIGN: - tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off); + tcg_gen_ld8s_i32(tcg_dest, tcg_env, vect_off); break; case MO_16|MO_SIGN: - tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off); + tcg_gen_ld16s_i32(tcg_dest, tcg_env, vect_off); break; case MO_32: case MO_32|MO_SIGN: - tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off); + tcg_gen_ld_i32(tcg_dest, tcg_env, vect_off); break; default: g_assert_not_reached(); @@ -1138,16 +1138,16 @@ static void write_vec_element(DisasContext *s, TCGv= _i64 tcg_src, int destidx, int vect_off =3D vec_reg_offset(s, destidx, element, memop & MO_SIZE); switch (memop) { case MO_8: - tcg_gen_st8_i64(tcg_src, cpu_env, vect_off); + tcg_gen_st8_i64(tcg_src, tcg_env, vect_off); break; case MO_16: - tcg_gen_st16_i64(tcg_src, cpu_env, vect_off); + tcg_gen_st16_i64(tcg_src, tcg_env, vect_off); break; case MO_32: - tcg_gen_st32_i64(tcg_src, cpu_env, vect_off); + tcg_gen_st32_i64(tcg_src, tcg_env, vect_off); break; case MO_64: - tcg_gen_st_i64(tcg_src, cpu_env, vect_off); + tcg_gen_st_i64(tcg_src, tcg_env, vect_off); break; default: g_assert_not_reached(); @@ -1160,13 +1160,13 @@ static void write_vec_element_i32(DisasContext *s, = TCGv_i32 tcg_src, int vect_off =3D vec_reg_offset(s, destidx, element, memop & MO_SIZE); switch (memop) { case MO_8: - tcg_gen_st8_i32(tcg_src, cpu_env, vect_off); + tcg_gen_st8_i32(tcg_src, tcg_env, vect_off); break; case MO_16: - tcg_gen_st16_i32(tcg_src, cpu_env, vect_off); + tcg_gen_st16_i32(tcg_src, tcg_env, vect_off); break; case MO_32: - tcg_gen_st_i32(tcg_src, cpu_env, vect_off); + tcg_gen_st_i32(tcg_src, tcg_env, vect_off); break; default: g_assert_not_reached(); @@ -1530,9 +1530,9 @@ static TCGv_i64 auth_branch_target(DisasContext *s, T= CGv_i64 dst, =20 truedst =3D tcg_temp_new_i64(); if (use_key_a) { - gen_helper_autia_combined(truedst, cpu_env, dst, modifier); + gen_helper_autia_combined(truedst, tcg_env, dst, modifier); } else { - gen_helper_autib_combined(truedst, cpu_env, dst, modifier); + gen_helper_autib_combined(truedst, tcg_env, dst, modifier); } return truedst; } @@ -1631,12 +1631,12 @@ static bool trans_ERET(DisasContext *s, arg_ERET *a) return true; } dst =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(dst, cpu_env, + tcg_gen_ld_i64(dst, tcg_env, offsetof(CPUARMState, elr_el[s->current_el])); =20 translator_io_start(&s->base); =20 - gen_helper_exception_return(cpu_env, dst); + gen_helper_exception_return(tcg_env, dst); /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; return true; @@ -1658,14 +1658,14 @@ static bool trans_ERETA(DisasContext *s, arg_reta *= a) return true; } dst =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(dst, cpu_env, + tcg_gen_ld_i64(dst, tcg_env, offsetof(CPUARMState, elr_el[s->current_el])); =20 dst =3D auth_branch_target(s, dst, cpu_X[31], !a->m); =20 translator_io_start(&s->base); =20 - gen_helper_exception_return(cpu_env, dst); + gen_helper_exception_return(tcg_env, dst); /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; return true; @@ -1713,7 +1713,7 @@ static bool trans_WFE(DisasContext *s, arg_WFI *a) static bool trans_XPACLRI(DisasContext *s, arg_XPACLRI *a) { if (s->pauth_active) { - gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); + gen_helper_xpaci(cpu_X[30], tcg_env, cpu_X[30]); } return true; } @@ -1721,7 +1721,7 @@ static bool trans_XPACLRI(DisasContext *s, arg_XPACLR= I *a) static bool trans_PACIA1716(DisasContext *s, arg_PACIA1716 *a) { if (s->pauth_active) { - gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + gen_helper_pacia(cpu_X[17], tcg_env, cpu_X[17], cpu_X[16]); } return true; } @@ -1729,7 +1729,7 @@ static bool trans_PACIA1716(DisasContext *s, arg_PACI= A1716 *a) static bool trans_PACIB1716(DisasContext *s, arg_PACIB1716 *a) { if (s->pauth_active) { - gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + gen_helper_pacib(cpu_X[17], tcg_env, cpu_X[17], cpu_X[16]); } return true; } @@ -1737,7 +1737,7 @@ static bool trans_PACIB1716(DisasContext *s, arg_PACI= B1716 *a) static bool trans_AUTIA1716(DisasContext *s, arg_AUTIA1716 *a) { if (s->pauth_active) { - gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + gen_helper_autia(cpu_X[17], tcg_env, cpu_X[17], cpu_X[16]); } return true; } @@ -1745,7 +1745,7 @@ static bool trans_AUTIA1716(DisasContext *s, arg_AUTI= A1716 *a) static bool trans_AUTIB1716(DisasContext *s, arg_AUTIB1716 *a) { if (s->pauth_active) { - gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + gen_helper_autib(cpu_X[17], tcg_env, cpu_X[17], cpu_X[16]); } return true; } @@ -1764,7 +1764,7 @@ static bool trans_ESB(DisasContext *s, arg_ESB *a) * Test for EL2 present, and defer test for SEL2 to runtime. */ if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { - gen_helper_vesb(cpu_env); + gen_helper_vesb(tcg_env); } } return true; @@ -1773,7 +1773,7 @@ static bool trans_ESB(DisasContext *s, arg_ESB *a) static bool trans_PACIAZ(DisasContext *s, arg_PACIAZ *a) { if (s->pauth_active) { - gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0= )); + gen_helper_pacia(cpu_X[30], tcg_env, cpu_X[30], tcg_constant_i64(0= )); } return true; } @@ -1781,7 +1781,7 @@ static bool trans_PACIAZ(DisasContext *s, arg_PACIAZ = *a) static bool trans_PACIASP(DisasContext *s, arg_PACIASP *a) { if (s->pauth_active) { - gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + gen_helper_pacia(cpu_X[30], tcg_env, cpu_X[30], cpu_X[31]); } return true; } @@ -1789,7 +1789,7 @@ static bool trans_PACIASP(DisasContext *s, arg_PACIAS= P *a) static bool trans_PACIBZ(DisasContext *s, arg_PACIBZ *a) { if (s->pauth_active) { - gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0= )); + gen_helper_pacib(cpu_X[30], tcg_env, cpu_X[30], tcg_constant_i64(0= )); } return true; } @@ -1797,7 +1797,7 @@ static bool trans_PACIBZ(DisasContext *s, arg_PACIBZ = *a) static bool trans_PACIBSP(DisasContext *s, arg_PACIBSP *a) { if (s->pauth_active) { - gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + gen_helper_pacib(cpu_X[30], tcg_env, cpu_X[30], cpu_X[31]); } return true; } @@ -1805,7 +1805,7 @@ static bool trans_PACIBSP(DisasContext *s, arg_PACIBS= P *a) static bool trans_AUTIAZ(DisasContext *s, arg_AUTIAZ *a) { if (s->pauth_active) { - gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0= )); + gen_helper_autia(cpu_X[30], tcg_env, cpu_X[30], tcg_constant_i64(0= )); } return true; } @@ -1813,7 +1813,7 @@ static bool trans_AUTIAZ(DisasContext *s, arg_AUTIAZ = *a) static bool trans_AUTIASP(DisasContext *s, arg_AUTIASP *a) { if (s->pauth_active) { - gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + gen_helper_autia(cpu_X[30], tcg_env, cpu_X[30], cpu_X[31]); } return true; } @@ -1821,7 +1821,7 @@ static bool trans_AUTIASP(DisasContext *s, arg_AUTIAS= P *a) static bool trans_AUTIBZ(DisasContext *s, arg_AUTIBZ *a) { if (s->pauth_active) { - gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0= )); + gen_helper_autib(cpu_X[30], tcg_env, cpu_X[30], tcg_constant_i64(0= )); } return true; } @@ -1829,7 +1829,7 @@ static bool trans_AUTIBZ(DisasContext *s, arg_AUTIBZ = *a) static bool trans_AUTIBSP(DisasContext *s, arg_AUTIBSP *a) { if (s->pauth_active) { - gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + gen_helper_autib(cpu_X[30], tcg_env, cpu_X[30], cpu_X[31]); } return true; } @@ -1984,7 +1984,7 @@ static bool trans_MSR_i_SPSEL(DisasContext *s, arg_i = *a) if (s->current_el =3D=3D 0) { return false; } - gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(a->imm & PSTATE_SP)); + gen_helper_msr_i_spsel(tcg_env, tcg_constant_i32(a->imm & PSTATE_SP)); s->base.is_jmp =3D DISAS_TOO_MANY; return true; } @@ -2043,14 +2043,14 @@ static bool trans_MSR_i_TCO(DisasContext *s, arg_i = *a) =20 static bool trans_MSR_i_DAIFSET(DisasContext *s, arg_i *a) { - gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(a->imm)); + gen_helper_msr_i_daifset(tcg_env, tcg_constant_i32(a->imm)); s->base.is_jmp =3D DISAS_TOO_MANY; return true; } =20 static bool trans_MSR_i_DAIFCLEAR(DisasContext *s, arg_i *a) { - gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(a->imm)); + gen_helper_msr_i_daifclear(tcg_env, tcg_constant_i32(a->imm)); /* Exit the cpu loop to re-evaluate pending IRQs. */ s->base.is_jmp =3D DISAS_UPDATE_EXIT; return true; @@ -2067,7 +2067,7 @@ static bool trans_MSR_i_SVCR(DisasContext *s, arg_MSR= _i_SVCR *a) =20 if ((old ^ new) & a->mask) { /* At least one bit changes. */ - gen_helper_set_svcr(cpu_env, tcg_constant_i32(new), + gen_helper_set_svcr(tcg_env, tcg_constant_i32(new), tcg_constant_i32(a->mask)); s->base.is_jmp =3D DISAS_TOO_MANY; } @@ -2165,11 +2165,11 @@ static void handle_sys(DisasContext *s, bool isread, switch (s->current_el) { case 0: if (dc_isar_feature(aa64_tidcp1, s)) { - gen_helper_tidcp_el0(cpu_env, tcg_constant_i32(syndrome)); + gen_helper_tidcp_el0(tcg_env, tcg_constant_i32(syndrome)); } break; case 1: - gen_helper_tidcp_el1(cpu_env, tcg_constant_i32(syndrome)); + gen_helper_tidcp_el1(tcg_env, tcg_constant_i32(syndrome)); break; } } @@ -2198,7 +2198,7 @@ static void handle_sys(DisasContext *s, bool isread, syndrome =3D syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isre= ad); gen_a64_update_pc(s, 0); tcg_ri =3D tcg_temp_new_ptr(); - gen_helper_access_check_cp_reg(tcg_ri, cpu_env, + gen_helper_access_check_cp_reg(tcg_ri, tcg_env, tcg_constant_i32(key), tcg_constant_i32(syndrome), tcg_constant_i32(isread)); @@ -2241,12 +2241,12 @@ static void handle_sys(DisasContext *s, bool isread, desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); =20 tcg_rt =3D tcg_temp_new_i64(); - gen_helper_mte_check_zva(tcg_rt, cpu_env, + gen_helper_mte_check_zva(tcg_rt, tcg_env, tcg_constant_i32(desc), cpu_reg(s, rt= )); } else { tcg_rt =3D clean_data_tbi(s, cpu_reg(s, rt)); } - gen_helper_dc_zva(cpu_env, tcg_rt); + gen_helper_dc_zva(tcg_env, tcg_rt); return; case ARM_CP_DC_GVA: { @@ -2264,7 +2264,7 @@ static void handle_sys(DisasContext *s, bool isread, /* Extract the tag from the register to match STZGM. */ tag =3D tcg_temp_new_i64(); tcg_gen_shri_i64(tag, tcg_rt, 56); - gen_helper_stzgm_tags(cpu_env, clean_addr, tag); + gen_helper_stzgm_tags(tcg_env, clean_addr, tag); } } return; @@ -2275,13 +2275,13 @@ static void handle_sys(DisasContext *s, bool isread, /* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */ tcg_rt =3D cpu_reg(s, rt); clean_addr =3D clean_data_tbi(s, tcg_rt); - gen_helper_dc_zva(cpu_env, clean_addr); + gen_helper_dc_zva(tcg_env, clean_addr); =20 if (s->ata) { /* Extract the tag from the register to match STZGM. */ tag =3D tcg_temp_new_i64(); tcg_gen_shri_i64(tag, tcg_rt, 56); - gen_helper_stzgm_tags(cpu_env, clean_addr, tag); + gen_helper_stzgm_tags(tcg_env, clean_addr, tag); } } return; @@ -2310,9 +2310,9 @@ static void handle_sys(DisasContext *s, bool isread, if (!tcg_ri) { tcg_ri =3D gen_lookup_cp_reg(key); } - gen_helper_get_cp_reg64(tcg_rt, cpu_env, tcg_ri); + gen_helper_get_cp_reg64(tcg_rt, tcg_env, tcg_ri); } else { - tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset); + tcg_gen_ld_i64(tcg_rt, tcg_env, ri->fieldoffset); } } else { if (ri->type & ARM_CP_CONST) { @@ -2322,9 +2322,9 @@ static void handle_sys(DisasContext *s, bool isread, if (!tcg_ri) { tcg_ri =3D gen_lookup_cp_reg(key); } - gen_helper_set_cp_reg64(cpu_env, tcg_ri, tcg_rt); + gen_helper_set_cp_reg64(tcg_env, tcg_ri, tcg_rt); } else { - tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset); + tcg_gen_st_i64(tcg_rt, tcg_env, ri->fieldoffset); } } =20 @@ -2381,7 +2381,7 @@ static bool trans_HVC(DisasContext *s, arg_i *a) * as an undefined insn by runtime configuration. */ gen_a64_update_pc(s, 0); - gen_helper_pre_hvc(cpu_env); + gen_helper_pre_hvc(tcg_env); /* Architecture requires ss advance before we do the actual work */ gen_ss_advance(s); gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), 2); @@ -2395,7 +2395,7 @@ static bool trans_SMC(DisasContext *s, arg_i *a) return true; } gen_a64_update_pc(s, 0); - gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(a->imm))); + gen_helper_pre_smc(tcg_env, tcg_constant_i32(syn_aa64_smc(a->imm))); /* Architecture requires ss advance before we do the actual work */ gen_ss_advance(s); gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(a->imm), 3); @@ -3060,9 +3060,9 @@ static bool trans_STGP(DisasContext *s, arg_ldstpair = *a) /* Perform the tag store, if tag access enabled. */ if (s->ata) { if (tb_cflags(s->base.tb) & CF_PARALLEL) { - gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr); + gen_helper_stg_parallel(tcg_env, dirty_addr, dirty_addr); } else { - gen_helper_stg(cpu_env, dirty_addr, dirty_addr); + gen_helper_stg(tcg_env, dirty_addr, dirty_addr); } } =20 @@ -3358,10 +3358,10 @@ static bool trans_LDRA(DisasContext *s, arg_LDRA *a) =20 if (s->pauth_active) { if (!a->m) { - gen_helper_autda_combined(dirty_addr, cpu_env, dirty_addr, + gen_helper_autda_combined(dirty_addr, tcg_env, dirty_addr, tcg_constant_i64(0)); } else { - gen_helper_autdb_combined(dirty_addr, cpu_env, dirty_addr, + gen_helper_autdb_combined(dirty_addr, tcg_env, dirty_addr, tcg_constant_i64(0)); } } @@ -3757,7 +3757,7 @@ static bool trans_STZGM(DisasContext *s, arg_ldst_tag= *a) tcg_rt =3D cpu_reg(s, a->rt); =20 if (s->ata) { - gen_helper_stzgm_tags(cpu_env, addr, tcg_rt); + gen_helper_stzgm_tags(tcg_env, addr, tcg_rt); } /* * The non-tags portion of STZGM is mostly like DC_ZVA, @@ -3765,7 +3765,7 @@ static bool trans_STZGM(DisasContext *s, arg_ldst_tag= *a) */ clean_addr =3D clean_data_tbi(s, addr); tcg_gen_andi_i64(clean_addr, clean_addr, -size); - gen_helper_dc_zva(cpu_env, clean_addr); + gen_helper_dc_zva(tcg_env, clean_addr); return true; } =20 @@ -3789,7 +3789,7 @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag = *a) tcg_rt =3D cpu_reg(s, a->rt); =20 if (s->ata) { - gen_helper_stgm(cpu_env, addr, tcg_rt); + gen_helper_stgm(tcg_env, addr, tcg_rt); } else { MMUAccessType acc =3D MMU_DATA_STORE; int size =3D 4 << s->gm_blocksize; @@ -3821,7 +3821,7 @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag = *a) tcg_rt =3D cpu_reg(s, a->rt); =20 if (s->ata) { - gen_helper_ldgm(tcg_rt, cpu_env, addr); + gen_helper_ldgm(tcg_rt, tcg_env, addr); } else { MMUAccessType acc =3D MMU_DATA_LOAD; int size =3D 4 << s->gm_blocksize; @@ -3856,7 +3856,7 @@ static bool trans_LDG(DisasContext *s, arg_ldst_tag *= a) tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); tcg_rt =3D cpu_reg(s, a->rt); if (s->ata) { - gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); + gen_helper_ldg(tcg_rt, tcg_env, addr, tcg_rt); } else { /* * Tag access disabled: we must check for aborts on the load @@ -3899,21 +3899,21 @@ static bool do_STG(DisasContext *s, arg_ldst_tag *a= , bool is_zero, bool is_pair) * at least for system mode; user-only won't enforce alignment. */ if (is_pair) { - gen_helper_st2g_stub(cpu_env, addr); + gen_helper_st2g_stub(tcg_env, addr); } else { - gen_helper_stg_stub(cpu_env, addr); + gen_helper_stg_stub(tcg_env, addr); } } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { if (is_pair) { - gen_helper_st2g_parallel(cpu_env, addr, tcg_rt); + gen_helper_st2g_parallel(tcg_env, addr, tcg_rt); } else { - gen_helper_stg_parallel(cpu_env, addr, tcg_rt); + gen_helper_stg_parallel(tcg_env, addr, tcg_rt); } } else { if (is_pair) { - gen_helper_st2g(cpu_env, addr, tcg_rt); + gen_helper_st2g(tcg_env, addr, tcg_rt); } else { - gen_helper_stg(cpu_env, addr, tcg_rt); + gen_helper_stg(tcg_env, addr, tcg_rt); } } =20 @@ -4013,7 +4013,7 @@ static bool gen_add_sub_imm_with_tags(DisasContext *s= , arg_rri_tag *a, tcg_rd =3D cpu_reg_sp(s, a->rd); =20 if (s->ata) { - gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, + gen_helper_addsubg(tcg_rd, tcg_env, tcg_rn, tcg_constant_i32(imm), tcg_constant_i32(a->uimm4)); } else { @@ -5112,7 +5112,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) case MAP(1, 0x01, 0x00): /* PACIA */ if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + gen_helper_pacia(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn)); } else if (!dc_isar_feature(aa64_pauth, s)) { goto do_unallocated; } @@ -5120,7 +5120,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) case MAP(1, 0x01, 0x01): /* PACIB */ if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + gen_helper_pacib(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn)); } else if (!dc_isar_feature(aa64_pauth, s)) { goto do_unallocated; } @@ -5128,7 +5128,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) case MAP(1, 0x01, 0x02): /* PACDA */ if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + gen_helper_pacda(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn)); } else if (!dc_isar_feature(aa64_pauth, s)) { goto do_unallocated; } @@ -5136,7 +5136,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) case MAP(1, 0x01, 0x03): /* PACDB */ if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + gen_helper_pacdb(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn)); } else if (!dc_isar_feature(aa64_pauth, s)) { goto do_unallocated; } @@ -5144,7 +5144,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) case MAP(1, 0x01, 0x04): /* AUTIA */ if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_autia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + gen_helper_autia(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn)); } else if (!dc_isar_feature(aa64_pauth, s)) { goto do_unallocated; } @@ -5152,7 +5152,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) case MAP(1, 0x01, 0x05): /* AUTIB */ if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_autib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + gen_helper_autib(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn)); } else if (!dc_isar_feature(aa64_pauth, s)) { goto do_unallocated; } @@ -5160,7 +5160,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) case MAP(1, 0x01, 0x06): /* AUTDA */ if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_autda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + gen_helper_autda(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn)); } else if (!dc_isar_feature(aa64_pauth, s)) { goto do_unallocated; } @@ -5168,7 +5168,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) case MAP(1, 0x01, 0x07): /* AUTDB */ if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn)); + gen_helper_autdb(tcg_rd, tcg_env, tcg_rd, cpu_reg_sp(s, rn)); } else if (!dc_isar_feature(aa64_pauth, s)) { goto do_unallocated; } @@ -5178,7 +5178,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0)); + gen_helper_pacia(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0)); } break; case MAP(1, 0x01, 0x09): /* PACIZB */ @@ -5186,7 +5186,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0)); + gen_helper_pacib(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0)); } break; case MAP(1, 0x01, 0x0a): /* PACDZA */ @@ -5194,7 +5194,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0)); + gen_helper_pacda(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0)); } break; case MAP(1, 0x01, 0x0b): /* PACDZB */ @@ -5202,7 +5202,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0)); + gen_helper_pacdb(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0)); } break; case MAP(1, 0x01, 0x0c): /* AUTIZA */ @@ -5210,7 +5210,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_autia(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0)); + gen_helper_autia(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0)); } break; case MAP(1, 0x01, 0x0d): /* AUTIZB */ @@ -5218,7 +5218,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_autib(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0)); + gen_helper_autib(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0)); } break; case MAP(1, 0x01, 0x0e): /* AUTDZA */ @@ -5226,7 +5226,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_autda(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0)); + gen_helper_autda(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0)); } break; case MAP(1, 0x01, 0x0f): /* AUTDZB */ @@ -5234,7 +5234,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, tcg_constant_i64(0)); + gen_helper_autdb(tcg_rd, tcg_env, tcg_rd, tcg_constant_i64(0)); } break; case MAP(1, 0x01, 0x10): /* XPACI */ @@ -5242,7 +5242,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_xpaci(tcg_rd, cpu_env, tcg_rd); + gen_helper_xpaci(tcg_rd, tcg_env, tcg_rd); } break; case MAP(1, 0x01, 0x11): /* XPACD */ @@ -5250,7 +5250,7 @@ static void disas_data_proc_1src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } else if (s->pauth_active) { tcg_rd =3D cpu_reg(s, rd); - gen_helper_xpacd(tcg_rd, cpu_env, tcg_rd); + gen_helper_xpacd(tcg_rd, tcg_env, tcg_rd); } break; default: @@ -5400,7 +5400,7 @@ static void disas_data_proc_2src(DisasContext *s, uin= t32_t insn) goto do_unallocated; } if (s->ata) { - gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, + gen_helper_irg(cpu_reg_sp(s, rd), tcg_env, cpu_reg_sp(s, rn), cpu_reg(s, rm)); } else { gen_address_with_allocation_tag0(cpu_reg_sp(s, rd), @@ -5434,7 +5434,7 @@ static void disas_data_proc_2src(DisasContext *s, uin= t32_t insn) if (sf =3D=3D 0 || !dc_isar_feature(aa64_pauth, s)) { goto do_unallocated; } - gen_helper_pacga(cpu_reg(s, rd), cpu_env, + gen_helper_pacga(cpu_reg(s, rd), tcg_env, cpu_reg(s, rn), cpu_reg_sp(s, rm)); break; case 16: @@ -5840,7 +5840,7 @@ static void handle_fp_1src_single(DisasContext *s, in= t opcode, int rd, int rn) gen_helper_vfp_negs(tcg_res, tcg_op); goto done; case 0x3: /* FSQRT */ - gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); + gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_env); goto done; case 0x6: /* BFCVT */ gen_fpst =3D gen_helper_bfcvt; @@ -5915,7 +5915,7 @@ static void handle_fp_1src_double(DisasContext *s, in= t opcode, int rd, int rn) gen_helper_vfp_negd(tcg_res, tcg_op); goto done; case 0x3: /* FSQRT */ - gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env); + gen_helper_vfp_sqrtd(tcg_res, tcg_op, tcg_env); goto done; case 0x8: /* FRINTN */ case 0x9: /* FRINTP */ @@ -5972,7 +5972,7 @@ static void handle_fp_fcvt(DisasContext *s, int opcod= e, if (dtype =3D=3D 1) { /* Single to double */ TCGv_i64 tcg_rd =3D tcg_temp_new_i64(); - gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, cpu_env); + gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, tcg_env); write_fp_dreg(s, rd, tcg_rd); } else { /* Single to half */ @@ -5992,7 +5992,7 @@ static void handle_fp_fcvt(DisasContext *s, int opcod= e, TCGv_i32 tcg_rd =3D tcg_temp_new_i32(); if (dtype =3D=3D 0) { /* Double to single */ - gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env); + gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, tcg_env); } else { TCGv_ptr fpst =3D fpstatus_ptr(FPST_FPCR); TCGv_i32 ahp =3D get_ahp_flag(); @@ -6752,7 +6752,7 @@ static void handle_fmov(DisasContext *s, int rd, int = rn, int type, bool itof) break; case 2: /* 64 bit to top half. */ - tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd)); + tcg_gen_st_i64(tcg_rn, tcg_env, fp_reg_hi_offset(s, rd)); clear_vec_high(s, true, rd); break; case 3: @@ -6770,19 +6770,19 @@ static void handle_fmov(DisasContext *s, int rd, in= t rn, int type, bool itof) switch (type) { case 0: /* 32 bit */ - tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_32)= ); + tcg_gen_ld32u_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_32)= ); break; case 1: /* 64 bit */ - tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_64)); + tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_64)); break; case 2: /* 64 bits from top half */ - tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn)); + tcg_gen_ld_i64(tcg_rd, tcg_env, fp_reg_hi_offset(s, rn)); break; case 3: /* 16 bit */ - tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16)= ); + tcg_gen_ld16u_i64(tcg_rd, tcg_env, fp_reg_offset(s, rn, MO_16)= ); break; default: g_assert_not_reached(); @@ -7066,7 +7066,7 @@ static void disas_simd_tb(DisasContext *s, uint32_t i= nsn) } =20 tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, rd), - vec_full_reg_offset(s, rm), cpu_env, + vec_full_reg_offset(s, rm), tcg_env, is_q ? 16 : 8, vec_full_reg_size(s), (len << 6) | (is_tbx << 5) | rn, gen_helper_simd_tblx); @@ -8120,7 +8120,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, b= ool is_scalar, bool is_q, read_vec_element(s, tcg_rn, rn, i, ldop); handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round, false, is_u_shift, size+1, shift); - narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd); + narrowfn(tcg_rd_narrowed, tcg_env, tcg_rd); tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed); if (i =3D=3D 0) { tcg_gen_mov_i64(tcg_final, tcg_rd); @@ -8192,7 +8192,7 @@ static void handle_simd_qshl(DisasContext *s, bool sc= alar, bool is_q, TCGv_i64 tcg_op =3D tcg_temp_new_i64(); =20 read_vec_element(s, tcg_op, rn, pass, MO_64); - genfn(tcg_op, cpu_env, tcg_op, tcg_shift); + genfn(tcg_op, tcg_env, tcg_op, tcg_shift); write_vec_element(s, tcg_op, rd, pass, MO_64); } clear_vec_high(s, is_q, rd); @@ -8221,7 +8221,7 @@ static void handle_simd_qshl(DisasContext *s, bool sc= alar, bool is_q, TCGv_i32 tcg_op =3D tcg_temp_new_i32(); =20 read_vec_element_i32(s, tcg_op, rn, pass, memop); - genfn(tcg_op, cpu_env, tcg_op, tcg_shift); + genfn(tcg_op, tcg_env, tcg_op, tcg_shift); if (scalar) { switch (size) { case 0: @@ -8604,7 +8604,7 @@ static void disas_simd_scalar_three_reg_diff(DisasCon= text *s, uint32_t insn) read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN); =20 tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2); - gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, tcg_res, tcg_r= es); + gen_helper_neon_addl_saturate_s64(tcg_res, tcg_env, tcg_res, tcg_r= es); =20 switch (opcode) { case 0xd: /* SQDMULL, SQDMULL2 */ @@ -8614,7 +8614,7 @@ static void disas_simd_scalar_three_reg_diff(DisasCon= text *s, uint32_t insn) /* fall through */ case 0x9: /* SQDMLAL, SQDMLAL2 */ read_vec_element(s, tcg_op1, rd, 0, MO_64); - gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, + gen_helper_neon_addl_saturate_s64(tcg_res, tcg_env, tcg_res, tcg_op1); break; default: @@ -8628,7 +8628,7 @@ static void disas_simd_scalar_three_reg_diff(DisasCon= text *s, uint32_t insn) TCGv_i64 tcg_res =3D tcg_temp_new_i64(); =20 gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2); - gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_r= es); + gen_helper_neon_addl_saturate_s32(tcg_res, tcg_env, tcg_res, tcg_r= es); =20 switch (opcode) { case 0xd: /* SQDMULL, SQDMULL2 */ @@ -8640,7 +8640,7 @@ static void disas_simd_scalar_three_reg_diff(DisasCon= text *s, uint32_t insn) { TCGv_i64 tcg_op3 =3D tcg_temp_new_i64(); read_vec_element(s, tcg_op3, rd, 0, MO_32); - gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, + gen_helper_neon_addl_saturate_s32(tcg_res, tcg_env, tcg_res, tcg_op3); break; } @@ -8666,16 +8666,16 @@ static void handle_3same_64(DisasContext *s, int op= code, bool u, switch (opcode) { case 0x1: /* SQADD */ if (u) { - gen_helper_neon_qadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); + gen_helper_neon_qadd_u64(tcg_rd, tcg_env, tcg_rn, tcg_rm); } else { - gen_helper_neon_qadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); + gen_helper_neon_qadd_s64(tcg_rd, tcg_env, tcg_rn, tcg_rm); } break; case 0x5: /* SQSUB */ if (u) { - gen_helper_neon_qsub_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); + gen_helper_neon_qsub_u64(tcg_rd, tcg_env, tcg_rn, tcg_rm); } else { - gen_helper_neon_qsub_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); + gen_helper_neon_qsub_s64(tcg_rd, tcg_env, tcg_rn, tcg_rm); } break; case 0x6: /* CMGT, CMHI */ @@ -8703,9 +8703,9 @@ static void handle_3same_64(DisasContext *s, int opco= de, bool u, break; case 0x9: /* SQSHL, UQSHL */ if (u) { - gen_helper_neon_qshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); + gen_helper_neon_qshl_u64(tcg_rd, tcg_env, tcg_rn, tcg_rm); } else { - gen_helper_neon_qshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); + gen_helper_neon_qshl_s64(tcg_rd, tcg_env, tcg_rn, tcg_rm); } break; case 0xa: /* SRSHL, URSHL */ @@ -8717,9 +8717,9 @@ static void handle_3same_64(DisasContext *s, int opco= de, bool u, break; case 0xb: /* SQRSHL, UQRSHL */ if (u) { - gen_helper_neon_qrshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm); + gen_helper_neon_qrshl_u64(tcg_rd, tcg_env, tcg_rn, tcg_rm); } else { - gen_helper_neon_qrshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm); + gen_helper_neon_qrshl_s64(tcg_rd, tcg_env, tcg_rn, tcg_rm); } break; case 0x10: /* ADD, SUB */ @@ -9063,7 +9063,7 @@ static void disas_simd_scalar_three_reg_same(DisasCon= text *s, uint32_t insn) g_assert_not_reached(); } =20 - genenvfn(tcg_rd32, cpu_env, tcg_rn, tcg_rm); + genenvfn(tcg_rd32, tcg_env, tcg_rn, tcg_rm); tcg_gen_extu_i32_i64(tcg_rd, tcg_rd32); } =20 @@ -9216,16 +9216,16 @@ static void disas_simd_scalar_three_reg_same_extra(= DisasContext *s, switch (opcode) { case 0x0: /* SQRDMLAH */ if (size =3D=3D 1) { - gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3); + gen_helper_neon_qrdmlah_s16(ele3, tcg_env, ele1, ele2, ele3); } else { - gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3); + gen_helper_neon_qrdmlah_s32(ele3, tcg_env, ele1, ele2, ele3); } break; case 0x1: /* SQRDMLSH */ if (size =3D=3D 1) { - gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3); + gen_helper_neon_qrdmlsh_s16(ele3, tcg_env, ele1, ele2, ele3); } else { - gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3); + gen_helper_neon_qrdmlsh_s32(ele3, tcg_env, ele1, ele2, ele3); } break; default: @@ -9265,9 +9265,9 @@ static void handle_2misc_64(DisasContext *s, int opco= de, bool u, break; case 0x7: /* SQABS, SQNEG */ if (u) { - gen_helper_neon_qneg_s64(tcg_rd, cpu_env, tcg_rn); + gen_helper_neon_qneg_s64(tcg_rd, tcg_env, tcg_rn); } else { - gen_helper_neon_qabs_s64(tcg_rd, cpu_env, tcg_rn); + gen_helper_neon_qabs_s64(tcg_rd, tcg_env, tcg_rn); } break; case 0xa: /* CMLT */ @@ -9296,7 +9296,7 @@ static void handle_2misc_64(DisasContext *s, int opco= de, bool u, gen_helper_vfp_negd(tcg_rd, tcg_rn); break; case 0x7f: /* FSQRT */ - gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env); + gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, tcg_env); break; case 0x1a: /* FCVTNS */ case 0x1b: /* FCVTMS */ @@ -9602,7 +9602,7 @@ static void handle_2misc_narrow(DisasContext *s, bool= scalar, case 0x16: /* FCVTN, FCVTN2 */ /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */ if (size =3D=3D 2) { - gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env); + gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, tcg_env); } else { TCGv_i32 tcg_lo =3D tcg_temp_new_i32(); TCGv_i32 tcg_hi =3D tcg_temp_new_i32(); @@ -9626,7 +9626,7 @@ static void handle_2misc_narrow(DisasContext *s, bool= scalar, * with von Neumann rounding (round to odd) */ assert(size =3D=3D 2); - gen_helper_fcvtx_f64_to_f32(tcg_res[pass], tcg_op, cpu_env); + gen_helper_fcvtx_f64_to_f32(tcg_res[pass], tcg_op, tcg_env); break; default: g_assert_not_reached(); @@ -9635,7 +9635,7 @@ static void handle_2misc_narrow(DisasContext *s, bool= scalar, if (genfn) { genfn(tcg_res[pass], tcg_op); } else if (genenvfn) { - genenvfn(tcg_res[pass], cpu_env, tcg_op); + genenvfn(tcg_res[pass], tcg_env, tcg_op); } } =20 @@ -9661,9 +9661,9 @@ static void handle_2misc_satacc(DisasContext *s, bool= is_scalar, bool is_u, read_vec_element(s, tcg_rd, rd, pass, MO_64); =20 if (is_u) { /* USQADD */ - gen_helper_neon_uqadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rd); + gen_helper_neon_uqadd_s64(tcg_rd, tcg_env, tcg_rn, tcg_rd); } else { /* SUQADD */ - gen_helper_neon_sqadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rd); + gen_helper_neon_sqadd_u64(tcg_rd, tcg_env, tcg_rn, tcg_rd); } write_vec_element(s, tcg_rd, rd, pass, MO_64); } @@ -9691,13 +9691,13 @@ static void handle_2misc_satacc(DisasContext *s, bo= ol is_scalar, bool is_u, if (is_u) { /* USQADD */ switch (size) { case 0: - gen_helper_neon_uqadd_s8(tcg_rd, cpu_env, tcg_rn, tcg_= rd); + gen_helper_neon_uqadd_s8(tcg_rd, tcg_env, tcg_rn, tcg_= rd); break; case 1: - gen_helper_neon_uqadd_s16(tcg_rd, cpu_env, tcg_rn, tcg= _rd); + gen_helper_neon_uqadd_s16(tcg_rd, tcg_env, tcg_rn, tcg= _rd); break; case 2: - gen_helper_neon_uqadd_s32(tcg_rd, cpu_env, tcg_rn, tcg= _rd); + gen_helper_neon_uqadd_s32(tcg_rd, tcg_env, tcg_rn, tcg= _rd); break; default: g_assert_not_reached(); @@ -9705,13 +9705,13 @@ static void handle_2misc_satacc(DisasContext *s, bo= ol is_scalar, bool is_u, } else { /* SUQADD */ switch (size) { case 0: - gen_helper_neon_sqadd_u8(tcg_rd, cpu_env, tcg_rn, tcg_= rd); + gen_helper_neon_sqadd_u8(tcg_rd, tcg_env, tcg_rn, tcg_= rd); break; case 1: - gen_helper_neon_sqadd_u16(tcg_rd, cpu_env, tcg_rn, tcg= _rd); + gen_helper_neon_sqadd_u16(tcg_rd, tcg_env, tcg_rn, tcg= _rd); break; case 2: - gen_helper_neon_sqadd_u32(tcg_rd, cpu_env, tcg_rn, tcg= _rd); + gen_helper_neon_sqadd_u32(tcg_rd, tcg_env, tcg_rn, tcg= _rd); break; default: g_assert_not_reached(); @@ -9889,7 +9889,7 @@ static void disas_simd_scalar_two_reg_misc(DisasConte= xt *s, uint32_t insn) { gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 }, }; genfn =3D fns[size][u]; - genfn(tcg_rd, cpu_env, tcg_rn); + genfn(tcg_rd, tcg_env, tcg_rn); break; } case 0x1a: /* FCVTNS */ @@ -10274,7 +10274,7 @@ static void handle_3rd_widening(DisasContext *s, in= t is_q, int is_u, int size, case 11: /* SQDMLSL, SQDMLSL2 */ case 13: /* SQDMULL, SQDMULL2 */ tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2); - gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, + gen_helper_neon_addl_saturate_s64(tcg_passres, tcg_env, tcg_passres, tcg_passres= ); break; default: @@ -10286,7 +10286,7 @@ static void handle_3rd_widening(DisasContext *s, in= t is_q, int is_u, int size, if (accop < 0) { tcg_gen_neg_i64(tcg_passres, tcg_passres); } - gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env, + gen_helper_neon_addl_saturate_s64(tcg_res[pass], tcg_env, tcg_res[pass], tcg_passr= es); } else if (accop > 0) { tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres); @@ -10366,7 +10366,7 @@ static void handle_3rd_widening(DisasContext *s, in= t is_q, int is_u, int size, case 13: /* SQDMULL, SQDMULL2 */ assert(size =3D=3D 1); gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2); - gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, + gen_helper_neon_addl_saturate_s32(tcg_passres, tcg_env, tcg_passres, tcg_passres= ); break; default: @@ -10379,7 +10379,7 @@ static void handle_3rd_widening(DisasContext *s, in= t is_q, int is_u, int size, if (accop < 0) { gen_helper_neon_negl_u32(tcg_passres, tcg_passres); } - gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_e= nv, + gen_helper_neon_addl_saturate_s32(tcg_res[pass], tcg_e= nv, tcg_res[pass], tcg_passres); } else { @@ -10849,7 +10849,7 @@ static void disas_simd_3same_float(DisasContext *s,= uint32_t insn) int data =3D (is_2 << 1) | is_s; tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), - vec_full_reg_offset(s, rm), cpu_env, + vec_full_reg_offset(s, rm), tcg_env, is_q ? 16 : 8, vec_full_reg_size(s), data, gen_helper_gvec_fmlal_a64); } @@ -11104,7 +11104,7 @@ static void disas_simd_3same_int(DisasContext *s, u= int32_t insn) } =20 if (genenvfn) { - genenvfn(tcg_res, cpu_env, tcg_op1, tcg_op2); + genenvfn(tcg_res, tcg_env, tcg_op1, tcg_op2); } else { genfn(tcg_res, tcg_op1, tcg_op2); } @@ -11573,7 +11573,7 @@ static void handle_2misc_widening(DisasContext *s, = int opcode, bool is_q, tcg_res[pass] =3D tcg_temp_new_i64(); =20 read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32); - gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, cpu_env); + gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, tcg_env); } for (pass =3D 0; pass < 2; pass++) { write_vec_element(s, tcg_res[pass], rd, pass, MO_64); @@ -12128,9 +12128,9 @@ static void disas_simd_two_reg_misc(DisasContext *s= , uint32_t insn) break; case 0x7: /* SQABS, SQNEG */ if (u) { - gen_helper_neon_qneg_s32(tcg_res, cpu_env, tcg_op); + gen_helper_neon_qneg_s32(tcg_res, tcg_env, tcg_op); } else { - gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op); + gen_helper_neon_qabs_s32(tcg_res, tcg_env, tcg_op); } break; case 0x2f: /* FABS */ @@ -12140,7 +12140,7 @@ static void disas_simd_two_reg_misc(DisasContext *s= , uint32_t insn) gen_helper_vfp_negs(tcg_res, tcg_op); break; case 0x7f: /* FSQRT */ - gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); + gen_helper_vfp_sqrts(tcg_res, tcg_op, tcg_env); break; case 0x1a: /* FCVTNS */ case 0x1b: /* FCVTMS */ @@ -12204,7 +12204,7 @@ static void disas_simd_two_reg_misc(DisasContext *s= , uint32_t insn) { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s= 16 }, }; genfn =3D fns[size][u]; - genfn(tcg_res, cpu_env, tcg_op); + genfn(tcg_res, tcg_env, tcg_op); break; } case 0x4: /* CLS, CLZ */ @@ -12641,7 +12641,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) return; } size =3D MO_16; - /* is_fp, but we pass cpu_env not fp_status. */ + /* is_fp, but we pass tcg_env not fp_status. */ break; default: unallocated_encoding(s); @@ -12784,7 +12784,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) int data =3D (index << 2) | (is_2 << 1) | is_s; tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), - vec_full_reg_offset(s, rm), cpu_env, + vec_full_reg_offset(s, rm), tcg_env, is_q ? 16 : 8, vec_full_reg_size(s), data, gen_helper_gvec_fmlal_idx_a64); } @@ -13003,19 +13003,19 @@ static void disas_simd_indexed(DisasContext *s, u= int32_t insn) break; case 0x0c: /* SQDMULH */ if (size =3D=3D 1) { - gen_helper_neon_qdmulh_s16(tcg_res, cpu_env, + gen_helper_neon_qdmulh_s16(tcg_res, tcg_env, tcg_op, tcg_idx); } else { - gen_helper_neon_qdmulh_s32(tcg_res, cpu_env, + gen_helper_neon_qdmulh_s32(tcg_res, tcg_env, tcg_op, tcg_idx); } break; case 0x0d: /* SQRDMULH */ if (size =3D=3D 1) { - gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env, + gen_helper_neon_qrdmulh_s16(tcg_res, tcg_env, tcg_op, tcg_idx); } else { - gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env, + gen_helper_neon_qrdmulh_s32(tcg_res, tcg_env, tcg_op, tcg_idx); } break; @@ -13023,10 +13023,10 @@ static void disas_simd_indexed(DisasContext *s, u= int32_t insn) read_vec_element_i32(s, tcg_res, rd, pass, is_scalar ? size : MO_32); if (size =3D=3D 1) { - gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env, + gen_helper_neon_qrdmlah_s16(tcg_res, tcg_env, tcg_op, tcg_idx, tcg_res); } else { - gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env, + gen_helper_neon_qrdmlah_s32(tcg_res, tcg_env, tcg_op, tcg_idx, tcg_res); } break; @@ -13034,10 +13034,10 @@ static void disas_simd_indexed(DisasContext *s, u= int32_t insn) read_vec_element_i32(s, tcg_res, rd, pass, is_scalar ? size : MO_32); if (size =3D=3D 1) { - gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env, + gen_helper_neon_qrdmlsh_s16(tcg_res, tcg_env, tcg_op, tcg_idx, tcg_res); } else { - gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env, + gen_helper_neon_qrdmlsh_s32(tcg_res, tcg_env, tcg_op, tcg_idx, tcg_res); } break; @@ -13095,7 +13095,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) =20 if (satop) { /* saturating, doubling */ - gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env, + gen_helper_neon_addl_saturate_s64(tcg_passres, tcg_env, tcg_passres, tcg_pas= sres); } =20 @@ -13117,7 +13117,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) tcg_gen_neg_i64(tcg_passres, tcg_passres); /* fall through */ case 0x3: /* SQDMLAL, SQDMLAL2 */ - gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_e= nv, + gen_helper_neon_addl_saturate_s64(tcg_res[pass], tcg_e= nv, tcg_res[pass], tcg_passres); break; @@ -13167,7 +13167,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) gen_helper_neon_mull_u16(tcg_passres, tcg_op, tcg_idx); } if (satop) { - gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, + gen_helper_neon_addl_saturate_s32(tcg_passres, tcg_env, tcg_passres, tcg_pas= sres); } =20 @@ -13191,7 +13191,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) gen_helper_neon_negl_u32(tcg_passres, tcg_passres); /* fall through */ case 0x3: /* SQDMLAL, SQDMLAL2 */ - gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_e= nv, + gen_helper_neon_addl_saturate_s32(tcg_res[pass], tcg_e= nv, tcg_res[pass], tcg_passres); break; @@ -13990,7 +13990,7 @@ static void aarch64_tr_translate_insn(DisasContextB= ase *dcbase, CPUState *cpu) * start of the TB. */ assert(s->base.num_insns =3D=3D 1); - gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); + gen_helper_exception_pc_alignment(tcg_env, tcg_constant_tl(pc)); s->base.is_jmp =3D DISAS_NORETURN; s->base.pc_next =3D QEMU_ALIGN_UP(pc, 4); return; @@ -14114,11 +14114,11 @@ static void aarch64_tr_tb_stop(DisasContextBase *= dcbase, CPUState *cpu) break; case DISAS_WFE: gen_a64_update_pc(dc, 4); - gen_helper_wfe(cpu_env); + gen_helper_wfe(tcg_env); break; case DISAS_YIELD: gen_a64_update_pc(dc, 4); - gen_helper_yield(cpu_env); + gen_helper_yield(tcg_env); break; case DISAS_WFI: /* @@ -14126,7 +14126,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) * the CPU if trying to debug across a WFI. */ gen_a64_update_pc(dc, 4); - gen_helper_wfi(cpu_env, tcg_constant_i32(4)); + gen_helper_wfi(tcg_env, tcg_constant_i32(4)); /* * The helper doesn't necessarily throw an exception, but we * must go back to the main loop to check for interrupts anywa= y. diff --git a/target/arm/tcg/translate-m-nocp.c b/target/arm/tcg/translate-m= -nocp.c index 33f6478bb9..8afe1b8bf6 100644 --- a/target/arm/tcg/translate-m-nocp.c +++ b/target/arm/tcg/translate-m-nocp.c @@ -85,9 +85,9 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_= VLSTM *a) =20 fptr =3D load_reg(s, a->rn); if (a->l) { - gen_helper_v7m_vlldm(cpu_env, fptr); + gen_helper_v7m_vlldm(tcg_env, fptr); } else { - gen_helper_v7m_vlstm(cpu_env, fptr); + gen_helper_v7m_vlstm(tcg_env, fptr); } =20 clear_eci_state(s); @@ -322,7 +322,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, switch (regno) { case ARM_VFP_FPSCR: tmp =3D loadfn(s, opaque, true); - gen_helper_vfp_set_fpscr(cpu_env, tmp); + gen_helper_vfp_set_fpscr(tcg_env, tmp); gen_lookup_tb(s); break; case ARM_VFP_FPSCR_NZCVQC: @@ -391,7 +391,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, R_V7M_CONTROL_SFPA_SHIFT, 1); store_cpu_field(control, v7m.control[M_REG_S]); tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); - gen_helper_vfp_set_fpscr(cpu_env, tmp); + gen_helper_vfp_set_fpscr(tcg_env, tmp); s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; break; } @@ -451,12 +451,12 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int= regno, switch (regno) { case ARM_VFP_FPSCR: tmp =3D tcg_temp_new_i32(); - gen_helper_vfp_get_fpscr(tmp, cpu_env); + gen_helper_vfp_get_fpscr(tmp, tcg_env); storefn(s, opaque, tmp, true); break; case ARM_VFP_FPSCR_NZCVQC: tmp =3D tcg_temp_new_i32(); - gen_helper_vfp_get_fpscr(tmp, cpu_env); + gen_helper_vfp_get_fpscr(tmp, tcg_env); tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK); storefn(s, opaque, tmp, true); break; @@ -475,7 +475,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, /* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */ tmp =3D tcg_temp_new_i32(); sfpa =3D tcg_temp_new_i32(); - gen_helper_vfp_get_fpscr(tmp, cpu_env); + gen_helper_vfp_get_fpscr(tmp, tcg_env); tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); control =3D load_cpu_field(v7m.control[M_REG_S]); tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); @@ -493,7 +493,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK); store_cpu_field(control, v7m.control[M_REG_S]); fpscr =3D load_cpu_field(v7m.fpdscr[M_REG_NS]); - gen_helper_vfp_set_fpscr(cpu_env, fpscr); + gen_helper_vfp_set_fpscr(tcg_env, fpscr); lookup_tb =3D true; break; } @@ -528,7 +528,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, tmp =3D tcg_temp_new_i32(); sfpa =3D tcg_temp_new_i32(); fpscr =3D tcg_temp_new_i32(); - gen_helper_vfp_get_fpscr(fpscr, cpu_env); + gen_helper_vfp_get_fpscr(fpscr, tcg_env); tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK); control =3D load_cpu_field(v7m.control[M_REG_S]); tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); @@ -540,7 +540,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, fpdscr =3D load_cpu_field(v7m.fpdscr[M_REG_NS]); tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, tcg_constant_i32(0), fpdscr, fpscr); - gen_helper_vfp_set_fpscr(cpu_env, fpscr); + gen_helper_vfp_set_fpscr(tcg_env, fpscr); break; } case ARM_VFP_VPR: @@ -643,7 +643,7 @@ static void fp_sysreg_to_memory(DisasContext *s, void *= opaque, TCGv_i32 value, } =20 if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { - gen_helper_v8m_stackcheck(cpu_env, addr); + gen_helper_v8m_stackcheck(tcg_env, addr); } =20 if (do_access) { @@ -682,7 +682,7 @@ static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, vo= id *opaque, } =20 if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { - gen_helper_v8m_stackcheck(cpu_env, addr); + gen_helper_v8m_stackcheck(tcg_env, addr); } =20 if (do_access) { diff --git a/target/arm/tcg/translate-mve.c b/target/arm/tcg/translate-mve.c index 17d8e6804e..b1a8d6a65c 100644 --- a/target/arm/tcg/translate-mve.c +++ b/target/arm/tcg/translate-mve.c @@ -56,7 +56,7 @@ static inline long mve_qreg_offset(unsigned reg) static TCGv_ptr mve_qreg_ptr(unsigned reg) { TCGv_ptr ret =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(ret, cpu_env, mve_qreg_offset(reg)); + tcg_gen_addi_ptr(ret, tcg_env, mve_qreg_offset(reg)); return ret; } =20 @@ -173,7 +173,7 @@ static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, = MVEGenLdStFn *fn, } =20 qreg =3D mve_qreg_ptr(a->qd); - fn(cpu_env, qreg, addr); + fn(tcg_env, qreg, addr); =20 /* * Writeback always happens after the last beat of the insn, @@ -234,7 +234,7 @@ static bool do_ldst_sg(DisasContext *s, arg_vldst_sg *a= , MVEGenLdStSGFn fn) =20 qd =3D mve_qreg_ptr(a->qd); qm =3D mve_qreg_ptr(a->qm); - fn(cpu_env, qd, qm, addr); + fn(tcg_env, qd, qm, addr); mve_update_eci(s); return true; } @@ -330,7 +330,7 @@ static bool do_ldst_sg_imm(DisasContext *s, arg_vldst_s= g_imm *a, =20 qd =3D mve_qreg_ptr(a->qd); qm =3D mve_qreg_ptr(a->qm); - fn(cpu_env, qd, qm, tcg_constant_i32(offset)); + fn(tcg_env, qd, qm, tcg_constant_i32(offset)); mve_update_eci(s); return true; } @@ -397,7 +397,7 @@ static bool do_vldst_il(DisasContext *s, arg_vldst_il *= a, MVEGenLdStIlFn *fn, * We pass the index of Qd, not a pointer, because the helper must * access multiple Q registers starting at Qd and working up. */ - fn(cpu_env, tcg_constant_i32(a->qd), rn); + fn(tcg_env, tcg_constant_i32(a->qd), rn); =20 if (a->w) { tcg_gen_addi_i32(rn, rn, addrinc); @@ -491,7 +491,7 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) } else { qd =3D mve_qreg_ptr(a->qd); tcg_gen_dup_i32(a->size, rt, rt); - gen_helper_mve_vdup(cpu_env, qd, rt); + gen_helper_mve_vdup(tcg_env, qd, rt); } mve_update_eci(s); return true; @@ -517,7 +517,7 @@ static bool do_1op_vec(DisasContext *s, arg_1op *a, MVE= GenOneOpFn fn, } else { qd =3D mve_qreg_ptr(a->qd); qm =3D mve_qreg_ptr(a->qm); - fn(cpu_env, qd, qm); + fn(tcg_env, qd, qm); } mve_update_eci(s); return true; @@ -612,7 +612,7 @@ static bool do_vcvt_rmode(DisasContext *s, arg_1op *a, =20 qd =3D mve_qreg_ptr(a->qd); qm =3D mve_qreg_ptr(a->qm); - fn(cpu_env, qd, qm, tcg_constant_i32(arm_rmode_to_sf(rmode))); + fn(tcg_env, qd, qm, tcg_constant_i32(arm_rmode_to_sf(rmode))); mve_update_eci(s); return true; } @@ -800,7 +800,7 @@ static bool do_2op_vec(DisasContext *s, arg_2op *a, MVE= GenTwoOpFn fn, qd =3D mve_qreg_ptr(a->qd); qn =3D mve_qreg_ptr(a->qn); qm =3D mve_qreg_ptr(a->qm); - fn(cpu_env, qd, qn, qm); + fn(tcg_env, qd, qn, qm); } mve_update_eci(s); return true; @@ -1052,7 +1052,7 @@ static bool do_2op_scalar(DisasContext *s, arg_2scala= r *a, qd =3D mve_qreg_ptr(a->qd); qn =3D mve_qreg_ptr(a->qn); rm =3D load_reg(s, a->rm); - fn(cpu_env, qd, qn, rm); + fn(tcg_env, qd, qn, rm); mve_update_eci(s); return true; } @@ -1183,7 +1183,7 @@ static bool do_long_dual_acc(DisasContext *s, arg_vml= aldav *a, rda_i =3D tcg_constant_i64(0); } =20 - fn(rda_o, cpu_env, qn, qm, rda_i); + fn(rda_o, tcg_env, qn, qm, rda_i); =20 rdalo =3D tcg_temp_new_i32(); rdahi =3D tcg_temp_new_i32(); @@ -1281,7 +1281,7 @@ static bool do_dual_acc(DisasContext *s, arg_vmladav = *a, MVEGenDualAccOpFn *fn) rda_o =3D tcg_temp_new_i32(); } =20 - fn(rda_o, cpu_env, qn, qm, rda_i); + fn(rda_o, tcg_env, qn, qm, rda_i); store_reg(s, a->rda, rda_o); =20 mve_update_eci(s); @@ -1377,7 +1377,7 @@ static bool trans_VPNOT(DisasContext *s, arg_VPNOT *a) return true; } =20 - gen_helper_mve_vpnot(cpu_env); + gen_helper_mve_vpnot(tcg_env); /* This insn updates predication bits */ s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; mve_update_eci(s); @@ -1419,7 +1419,7 @@ static bool trans_VADDV(DisasContext *s, arg_VADDV *a) } =20 qm =3D mve_qreg_ptr(a->qm); - fns[a->size][a->u](rda_o, cpu_env, qm, rda_i); + fns[a->size][a->u](rda_o, tcg_env, qm, rda_i); store_reg(s, a->rda, rda_o); =20 mve_update_eci(s); @@ -1471,9 +1471,9 @@ static bool trans_VADDLV(DisasContext *s, arg_VADDLV = *a) =20 qm =3D mve_qreg_ptr(a->qm); if (a->u) { - gen_helper_mve_vaddlv_u(rda_o, cpu_env, qm, rda_i); + gen_helper_mve_vaddlv_u(rda_o, tcg_env, qm, rda_i); } else { - gen_helper_mve_vaddlv_s(rda_o, cpu_env, qm, rda_i); + gen_helper_mve_vaddlv_s(rda_o, tcg_env, qm, rda_i); } =20 rdalo =3D tcg_temp_new_i32(); @@ -1508,7 +1508,7 @@ static bool do_1imm(DisasContext *s, arg_1imm *a, MVE= GenOneOpImmFn *fn, imm, 16, 16); } else { qd =3D mve_qreg_ptr(a->qd); - fn(cpu_env, qd, tcg_constant_i64(imm)); + fn(tcg_env, qd, tcg_constant_i64(imm)); } mve_update_eci(s); return true; @@ -1580,7 +1580,7 @@ static bool do_2shift_vec(DisasContext *s, arg_2shift= *a, MVEGenTwoOpShiftFn fn, } else { qd =3D mve_qreg_ptr(a->qd); qm =3D mve_qreg_ptr(a->qm); - fn(cpu_env, qd, qm, tcg_constant_i32(shift)); + fn(tcg_env, qd, qm, tcg_constant_i32(shift)); } mve_update_eci(s); return true; @@ -1685,7 +1685,7 @@ static bool do_2shift_scalar(DisasContext *s, arg_shl= _scalar *a, =20 qda =3D mve_qreg_ptr(a->qda); rm =3D load_reg(s, a->rm); - fn(cpu_env, qda, qda, rm); + fn(tcg_env, qda, qda, rm); mve_update_eci(s); return true; } @@ -1827,7 +1827,7 @@ static bool trans_VSHLC(DisasContext *s, arg_VSHLC *a) =20 qd =3D mve_qreg_ptr(a->qd); rdm =3D load_reg(s, a->rdm); - gen_helper_mve_vshlc(rdm, cpu_env, qd, rdm, tcg_constant_i32(a->imm)); + gen_helper_mve_vshlc(rdm, tcg_env, qd, rdm, tcg_constant_i32(a->imm)); store_reg(s, a->rdm, rdm); mve_update_eci(s); return true; @@ -1856,7 +1856,7 @@ static bool do_vidup(DisasContext *s, arg_vidup *a, M= VEGenVIDUPFn *fn) =20 qd =3D mve_qreg_ptr(a->qd); rn =3D load_reg(s, a->rn); - fn(rn, cpu_env, qd, rn, tcg_constant_i32(a->imm)); + fn(rn, tcg_env, qd, rn, tcg_constant_i32(a->imm)); store_reg(s, a->rn, rn); mve_update_eci(s); return true; @@ -1891,7 +1891,7 @@ static bool do_viwdup(DisasContext *s, arg_viwdup *a,= MVEGenVIWDUPFn *fn) qd =3D mve_qreg_ptr(a->qd); rn =3D load_reg(s, a->rn); rm =3D load_reg(s, a->rm); - fn(rn, cpu_env, qd, rn, rm, tcg_constant_i32(a->imm)); + fn(rn, tcg_env, qd, rn, rm, tcg_constant_i32(a->imm)); store_reg(s, a->rn, rn); mve_update_eci(s); return true; @@ -1957,7 +1957,7 @@ static bool do_vcmp(DisasContext *s, arg_vcmp *a, MVE= GenCmpFn *fn) =20 qn =3D mve_qreg_ptr(a->qn); qm =3D mve_qreg_ptr(a->qm); - fn(cpu_env, qn, qm); + fn(tcg_env, qn, qm); if (a->mask) { /* VPT */ gen_vpst(s, a->mask); @@ -1988,7 +1988,7 @@ static bool do_vcmp_scalar(DisasContext *s, arg_vcmp_= scalar *a, } else { rm =3D load_reg(s, a->rm); } - fn(cpu_env, qn, rm); + fn(tcg_env, qn, rm); if (a->mask) { /* VPT */ gen_vpst(s, a->mask); @@ -2089,7 +2089,7 @@ static bool do_vmaxv(DisasContext *s, arg_vmaxv *a, M= VEGenVADDVFn fn) =20 qm =3D mve_qreg_ptr(a->qm); rda =3D load_reg(s, a->rda); - fn(rda, cpu_env, qm, rda); + fn(rda, tcg_env, qm, rda); store_reg(s, a->rda, rda); mve_update_eci(s); return true; @@ -2153,7 +2153,7 @@ static bool do_vabav(DisasContext *s, arg_vabav *a, M= VEGenVABAVFn *fn) qm =3D mve_qreg_ptr(a->qm); qn =3D mve_qreg_ptr(a->qn); rda =3D load_reg(s, a->rda); - fn(rda, cpu_env, qn, qm, rda); + fn(rda, tcg_env, qn, qm, rda); store_reg(s, a->rda, rda); mve_update_eci(s); return true; diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neo= n.c index 8de4ceb203..144f18ba22 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -32,7 +32,7 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg) { TCGv_ptr ret =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(ret, cpu_env, vfp_reg_offset(dp, reg)); + tcg_gen_addi_ptr(ret, tcg_env, vfp_reg_offset(dp, reg)); return ret; } =20 @@ -42,13 +42,13 @@ static void neon_load_element(TCGv_i32 var, int reg, in= t ele, MemOp mop) =20 switch (mop) { case MO_UB: - tcg_gen_ld8u_i32(var, cpu_env, offset); + tcg_gen_ld8u_i32(var, tcg_env, offset); break; case MO_UW: - tcg_gen_ld16u_i32(var, cpu_env, offset); + tcg_gen_ld16u_i32(var, tcg_env, offset); break; case MO_UL: - tcg_gen_ld_i32(var, cpu_env, offset); + tcg_gen_ld_i32(var, tcg_env, offset); break; default: g_assert_not_reached(); @@ -61,16 +61,16 @@ static void neon_load_element64(TCGv_i64 var, int reg, = int ele, MemOp mop) =20 switch (mop) { case MO_UB: - tcg_gen_ld8u_i64(var, cpu_env, offset); + tcg_gen_ld8u_i64(var, tcg_env, offset); break; case MO_UW: - tcg_gen_ld16u_i64(var, cpu_env, offset); + tcg_gen_ld16u_i64(var, tcg_env, offset); break; case MO_UL: - tcg_gen_ld32u_i64(var, cpu_env, offset); + tcg_gen_ld32u_i64(var, tcg_env, offset); break; case MO_UQ: - tcg_gen_ld_i64(var, cpu_env, offset); + tcg_gen_ld_i64(var, tcg_env, offset); break; default: g_assert_not_reached(); @@ -83,13 +83,13 @@ static void neon_store_element(int reg, int ele, MemOp = size, TCGv_i32 var) =20 switch (size) { case MO_8: - tcg_gen_st8_i32(var, cpu_env, offset); + tcg_gen_st8_i32(var, tcg_env, offset); break; case MO_16: - tcg_gen_st16_i32(var, cpu_env, offset); + tcg_gen_st16_i32(var, tcg_env, offset); break; case MO_32: - tcg_gen_st_i32(var, cpu_env, offset); + tcg_gen_st_i32(var, tcg_env, offset); break; default: g_assert_not_reached(); @@ -102,16 +102,16 @@ static void neon_store_element64(int reg, int ele, Me= mOp size, TCGv_i64 var) =20 switch (size) { case MO_8: - tcg_gen_st8_i64(var, cpu_env, offset); + tcg_gen_st8_i64(var, tcg_env, offset); break; case MO_16: - tcg_gen_st16_i64(var, cpu_env, offset); + tcg_gen_st16_i64(var, tcg_env, offset); break; case MO_32: - tcg_gen_st32_i64(var, cpu_env, offset); + tcg_gen_st32_i64(var, tcg_env, offset); break; case MO_64: - tcg_gen_st_i64(var, cpu_env, offset); + tcg_gen_st_i64(var, tcg_env, offset); break; default: g_assert_not_reached(); @@ -296,7 +296,7 @@ static bool trans_VFML(DisasContext *s, arg_VFML *a) tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(a->q, a->vn), vfp_reg_offset(a->q, a->vm), - cpu_env, opr_sz, opr_sz, a->s, /* is_2 =3D=3D 0 */ + tcg_env, opr_sz, opr_sz, a->s, /* is_2 =3D=3D 0 */ gen_helper_gvec_fmlal_a32); return true; } @@ -390,7 +390,7 @@ static bool trans_VFML_scalar(DisasContext *s, arg_VFML= _scalar *a) tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(a->q, a->vn), vfp_reg_offset(a->q, a->rm), - cpu_env, opr_sz, opr_sz, + tcg_env, opr_sz, opr_sz, (a->index << 2) | a->s, /* is_2 =3D=3D 0 */ gen_helper_gvec_fmlal_idx_a32); return true; @@ -920,7 +920,7 @@ DO_SHA2(SHA256SU1, gen_helper_crypto_sha256su1) #define DO_3SAME_64_ENV(INSN, FUNC) \ static void gen_##INSN##_elt(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m) \ { \ - FUNC(d, cpu_env, n, m); \ + FUNC(d, tcg_env, n, m); \ } \ DO_3SAME_64(INSN, gen_##INSN##_elt) =20 @@ -953,7 +953,7 @@ DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64) } =20 /* - * Some helper functions need to be passed the cpu_env. In order + * Some helper functions need to be passed the tcg_env. In order * to use those with the gvec APIs like tcg_gen_gvec_3() we need * to create wrapper functions whose prototype is a NeonGenTwoOpFn() * and which call a NeonGenTwoOpEnvFn(). @@ -961,7 +961,7 @@ DO_3SAME_64_ENV(VQRSHL_U64, gen_helper_neon_qrshl_u64) #define WRAP_ENV_FN(WRAPNAME, FUNC) \ static void WRAPNAME(TCGv_i32 d, TCGv_i32 n, TCGv_i32 m) \ { \ - FUNC(d, cpu_env, n, m); \ + FUNC(d, tcg_env, n, m); \ } =20 #define DO_3SAME_32_ENV(INSN, FUNC) \ @@ -1305,7 +1305,7 @@ static bool do_2shift_env_64(DisasContext *s, arg_2re= g_shift *a, { /* * 2-reg-and-shift operations, size =3D=3D 3 case, where the - * function needs to be passed cpu_env. + * function needs to be passed tcg_env. */ TCGv_i64 constimm; int pass; @@ -1338,7 +1338,7 @@ static bool do_2shift_env_64(DisasContext *s, arg_2re= g_shift *a, TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 read_neon_element64(tmp, a->vm, pass, MO_64); - fn(tmp, cpu_env, tmp, constimm); + fn(tmp, tcg_env, tmp, constimm); write_neon_element64(tmp, a->vd, pass, MO_64); } return true; @@ -1349,7 +1349,7 @@ static bool do_2shift_env_32(DisasContext *s, arg_2re= g_shift *a, { /* * 2-reg-and-shift operations, size < 3 case, where the - * helper needs to be passed cpu_env. + * helper needs to be passed tcg_env. */ TCGv_i32 constimm, tmp; int pass; @@ -1381,7 +1381,7 @@ static bool do_2shift_env_32(DisasContext *s, arg_2re= g_shift *a, =20 for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { read_neon_element32(tmp, a->vm, pass, MO_32); - fn(tmp, cpu_env, tmp, constimm); + fn(tmp, tcg_env, tmp, constimm); write_neon_element32(tmp, a->vd, pass, MO_32); } return true; @@ -1447,11 +1447,11 @@ static bool do_2shift_narrow_64(DisasContext *s, ar= g_2reg_shift *a, read_neon_element64(rm2, a->vm, 1, MO_64); =20 shiftfn(rm1, rm1, constimm); - narrowfn(rd, cpu_env, rm1); + narrowfn(rd, tcg_env, rm1); write_neon_element32(rd, a->vd, 0, MO_32); =20 shiftfn(rm2, rm2, constimm); - narrowfn(rd, cpu_env, rm2); + narrowfn(rd, tcg_env, rm2); write_neon_element32(rd, a->vd, 1, MO_32); =20 return true; @@ -1514,7 +1514,7 @@ static bool do_2shift_narrow_32(DisasContext *s, arg_= 2reg_shift *a, =20 tcg_gen_concat_i32_i64(rtmp, rm1, rm2); =20 - narrowfn(rm1, cpu_env, rtmp); + narrowfn(rm1, tcg_env, rtmp); write_neon_element32(rm1, a->vd, 0, MO_32); =20 shiftfn(rm3, rm3, constimm); @@ -1522,7 +1522,7 @@ static bool do_2shift_narrow_32(DisasContext *s, arg_= 2reg_shift *a, =20 tcg_gen_concat_i32_i64(rtmp, rm3, rm4); =20 - narrowfn(rm3, cpu_env, rtmp); + narrowfn(rm3, tcg_env, rtmp); write_neon_element32(rm3, a->vd, 1, MO_32); return true; } @@ -2159,13 +2159,13 @@ DO_VMLAL(VMLSL_U,mull_u,sub) static void gen_VQDMULL_16(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) { gen_helper_neon_mull_s16(rd, rn, rm); - gen_helper_neon_addl_saturate_s32(rd, cpu_env, rd, rd); + gen_helper_neon_addl_saturate_s32(rd, tcg_env, rd, rd); } =20 static void gen_VQDMULL_32(TCGv_i64 rd, TCGv_i32 rn, TCGv_i32 rm) { gen_mull_s32(rd, rn, rm); - gen_helper_neon_addl_saturate_s64(rd, cpu_env, rd, rd); + gen_helper_neon_addl_saturate_s64(rd, tcg_env, rd, rd); } =20 static bool trans_VQDMULL_3d(DisasContext *s, arg_3diff *a) @@ -2182,12 +2182,12 @@ static bool trans_VQDMULL_3d(DisasContext *s, arg_3= diff *a) =20 static void gen_VQDMLAL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) { - gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm); + gen_helper_neon_addl_saturate_s32(rd, tcg_env, rn, rm); } =20 static void gen_VQDMLAL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) { - gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm); + gen_helper_neon_addl_saturate_s64(rd, tcg_env, rn, rm); } =20 static bool trans_VQDMLAL_3d(DisasContext *s, arg_3diff *a) @@ -2211,13 +2211,13 @@ static bool trans_VQDMLAL_3d(DisasContext *s, arg_3= diff *a) static void gen_VQDMLSL_acc_16(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) { gen_helper_neon_negl_u32(rm, rm); - gen_helper_neon_addl_saturate_s32(rd, cpu_env, rn, rm); + gen_helper_neon_addl_saturate_s32(rd, tcg_env, rn, rm); } =20 static void gen_VQDMLSL_acc_32(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm) { tcg_gen_neg_i64(rm, rm); - gen_helper_neon_addl_saturate_s64(rd, cpu_env, rn, rm); + gen_helper_neon_addl_saturate_s64(rd, tcg_env, rn, rm); } =20 static bool trans_VQDMLSL_3d(DisasContext *s, arg_3diff *a) @@ -2550,7 +2550,7 @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2sca= lar *a, for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { read_neon_element32(rn, a->vn, pass, MO_32); read_neon_element32(rd, a->vd, pass, MO_32); - opfn(rd, cpu_env, rn, scalar, rd); + opfn(rd, tcg_env, rn, scalar, rd); write_neon_element32(rd, a->vd, pass, MO_32); } return true; @@ -2837,7 +2837,7 @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) val =3D tcg_temp_new_i64(); read_neon_element64(val, a->vm, 0, MO_64); =20 - gen_helper_neon_tbl(val, cpu_env, desc, val, def); + gen_helper_neon_tbl(val, tcg_env, desc, val, def); write_neon_element64(val, a->vd, 0, MO_64); return true; } @@ -3171,9 +3171,9 @@ static bool do_vmovn(DisasContext *s, arg_2misc *a, rd1 =3D tcg_temp_new_i32(); =20 read_neon_element64(rm, a->vm, 0, MO_64); - narrowfn(rd0, cpu_env, rm); + narrowfn(rd0, tcg_env, rm); read_neon_element64(rm, a->vm, 1, MO_64); - narrowfn(rd1, cpu_env, rm); + narrowfn(rd1, tcg_env, rm); write_neon_element32(rd0, a->vd, 0, MO_32); write_neon_element32(rd1, a->vd, 1, MO_32); return true; @@ -3625,7 +3625,7 @@ static bool trans_VRSQRTE(DisasContext *s, arg_2misc = *a) #define WRAP_1OP_ENV_FN(WRAPNAME, FUNC) \ static void WRAPNAME(TCGv_i32 d, TCGv_i32 m) \ { \ - FUNC(d, cpu_env, m); \ + FUNC(d, tcg_env, m); \ } =20 WRAP_1OP_ENV_FN(gen_VQABS_s8, gen_helper_neon_qabs_s8) diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 6038b0a06f..8f0dfc884e 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -90,7 +90,7 @@ static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz,= int rs, /* Add the byte offset to env to produce the final pointer. */ addr =3D tcg_temp_new_ptr(); tcg_gen_ext_i32_ptr(addr, tmp); - tcg_gen_add_ptr(addr, addr, cpu_env); + tcg_gen_add_ptr(addr, addr, tcg_env); =20 return addr; } @@ -106,7 +106,7 @@ static TCGv_ptr get_tile(DisasContext *s, int esz, int = tile) =20 offset =3D tile * sizeof(ARMVectorReg) + offsetof(CPUARMState, zarray); =20 - tcg_gen_addi_ptr(addr, cpu_env, offset); + tcg_gen_addi_ptr(addr, tcg_env, offset); return addr; } =20 @@ -116,7 +116,7 @@ static bool trans_ZERO(DisasContext *s, arg_ZERO *a) return false; } if (sme_za_enabled_check(s)) { - gen_helper_sme_zero(cpu_env, tcg_constant_i32(a->imm), + gen_helper_sme_zero(tcg_env, tcg_constant_i32(a->imm), tcg_constant_i32(streaming_vec_reg_size(s))); } return true; @@ -237,7 +237,7 @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) svl =3D streaming_vec_reg_size(s); desc =3D simd_desc(svl, svl, desc); =20 - fns[a->esz][be][a->v][mte][a->st](cpu_env, t_za, t_pg, addr, + fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr, tcg_constant_i32(desc)); return true; } diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 2ba5efadfd..7b39962f20 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -497,8 +497,8 @@ static void do_predtest(DisasContext *s, int dofs, int = gofs, int words) TCGv_ptr gptr =3D tcg_temp_new_ptr(); TCGv_i32 t =3D tcg_temp_new_i32(); =20 - tcg_gen_addi_ptr(dptr, cpu_env, dofs); - tcg_gen_addi_ptr(gptr, cpu_env, gofs); + tcg_gen_addi_ptr(dptr, tcg_env, dofs); + tcg_gen_addi_ptr(gptr, tcg_env, gofs); =20 gen_helper_sve_predtest(t, dptr, gptr, tcg_constant_i32(words)); =20 @@ -956,8 +956,8 @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a, t_zn =3D tcg_temp_new_ptr(); t_pg =3D tcg_temp_new_ptr(); =20 - tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); - tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); + tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn)); + tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg)); fn(temp, t_zn, t_pg, desc); =20 write_fp_dreg(s, a->rd, temp); @@ -1209,7 +1209,7 @@ static bool do_index(DisasContext *s, int esz, int rd, desc =3D tcg_constant_i32(simd_desc(vsz, vsz, 0)); t_zd =3D tcg_temp_new_ptr(); =20 - tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd)); + tcg_gen_addi_ptr(t_zd, tcg_env, vec_full_reg_offset(s, rd)); if (esz =3D=3D 3) { gen_helper_sve_index_d(t_zd, start, incr, desc); } else { @@ -1379,12 +1379,12 @@ static bool do_pppp_flags(DisasContext *s, arg_rprr= _s *a, TCGv_i64 pm =3D tcg_temp_new_i64(); TCGv_i64 pg =3D tcg_temp_new_i64(); =20 - tcg_gen_ld_i64(pn, cpu_env, nofs); - tcg_gen_ld_i64(pm, cpu_env, mofs); - tcg_gen_ld_i64(pg, cpu_env, gofs); + tcg_gen_ld_i64(pn, tcg_env, nofs); + tcg_gen_ld_i64(pm, tcg_env, mofs); + tcg_gen_ld_i64(pg, tcg_env, gofs); =20 gvec_op->fni8(pd, pn, pm, pg); - tcg_gen_st_i64(pd, cpu_env, dofs); + tcg_gen_st_i64(pd, tcg_env, dofs); =20 do_predtest1(pd, pg); } else { @@ -1654,8 +1654,8 @@ static bool trans_PTEST(DisasContext *s, arg_PTEST *a) TCGv_i64 pn =3D tcg_temp_new_i64(); TCGv_i64 pg =3D tcg_temp_new_i64(); =20 - tcg_gen_ld_i64(pn, cpu_env, nofs); - tcg_gen_ld_i64(pg, cpu_env, gofs); + tcg_gen_ld_i64(pn, tcg_env, nofs); + tcg_gen_ld_i64(pg, tcg_env, gofs); do_predtest1(pn, pg); } else { do_predtest(s, nofs, gofs, words); @@ -1736,7 +1736,7 @@ static bool do_predset(DisasContext *s, int esz, int = rd, int pat, bool setflag) t =3D tcg_temp_new_i64(); if (fullsz <=3D 64) { tcg_gen_movi_i64(t, lastword); - tcg_gen_st_i64(t, cpu_env, ofs); + tcg_gen_st_i64(t, tcg_env, ofs); goto done; } =20 @@ -1755,17 +1755,17 @@ static bool do_predset(DisasContext *s, int esz, in= t rd, int pat, bool setflag) =20 tcg_gen_movi_i64(t, word); for (i =3D 0; i < QEMU_ALIGN_DOWN(setsz, 8); i +=3D 8) { - tcg_gen_st_i64(t, cpu_env, ofs + i); + tcg_gen_st_i64(t, tcg_env, ofs + i); } if (lastword !=3D word) { tcg_gen_movi_i64(t, lastword); - tcg_gen_st_i64(t, cpu_env, ofs + i); + tcg_gen_st_i64(t, tcg_env, ofs + i); i +=3D 8; } if (i < fullsz) { tcg_gen_movi_i64(t, 0); for (; i < fullsz; i +=3D 8) { - tcg_gen_st_i64(t, cpu_env, ofs + i); + tcg_gen_st_i64(t, tcg_env, ofs + i); } } =20 @@ -1822,8 +1822,8 @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr_e= sz *a, desc =3D FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s)); desc =3D FIELD_DP32(desc, PREDDESC, ESZ, a->esz); =20 - tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd)); - tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn)); + tcg_gen_addi_ptr(t_pd, tcg_env, pred_full_reg_offset(s, a->rd)); + tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->rn)); t =3D tcg_temp_new_i32(); =20 gen_fn(t, t_pd, t_pg, tcg_constant_i32(desc)); @@ -1919,8 +1919,8 @@ static void do_sat_addsub_vec(DisasContext *s, int es= z, int rd, int rn, =20 dptr =3D tcg_temp_new_ptr(); nptr =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(dptr, cpu_env, vec_full_reg_offset(s, rd)); - tcg_gen_addi_ptr(nptr, cpu_env, vec_full_reg_offset(s, rn)); + tcg_gen_addi_ptr(dptr, tcg_env, vec_full_reg_offset(s, rd)); + tcg_gen_addi_ptr(nptr, tcg_env, vec_full_reg_offset(s, rn)); desc =3D tcg_constant_i32(simd_desc(vsz, vsz, 0)); =20 switch (esz) { @@ -2163,9 +2163,9 @@ static void do_cpy_m(DisasContext *s, int esz, int rd= , int rn, int pg, TCGv_ptr t_zn =3D tcg_temp_new_ptr(); TCGv_ptr t_pg =3D tcg_temp_new_ptr(); =20 - tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd)); - tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, rn)); - tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); + tcg_gen_addi_ptr(t_zd, tcg_env, vec_full_reg_offset(s, rd)); + tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, rn)); + tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg)); =20 fns[esz](t_zd, t_zn, t_pg, val, desc); } @@ -2310,8 +2310,8 @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz = *a, TCGv_i64 val) TCGv_ptr t_zd =3D tcg_temp_new_ptr(); TCGv_ptr t_zn =3D tcg_temp_new_ptr(); =20 - tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, a->rd)); - tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); + tcg_gen_addi_ptr(t_zd, tcg_env, vec_full_reg_offset(s, a->rd)); + tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn)); =20 fns[a->esz](t_zd, t_zn, val, desc); } @@ -2323,7 +2323,7 @@ static bool trans_INSR_f(DisasContext *s, arg_rrr_esz= *a) } if (sve_access_check(s)) { TCGv_i64 t =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(t, cpu_env, vec_reg_offset(s, a->rm, 0, MO_64)); + tcg_gen_ld_i64(t, tcg_env, vec_reg_offset(s, a->rm, 0, MO_64)); do_insr_i64(s, a, t); } return true; @@ -2409,9 +2409,9 @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_es= z *a, bool high_odd, desc =3D FIELD_DP32(desc, PREDDESC, ESZ, a->esz); desc =3D FIELD_DP32(desc, PREDDESC, DATA, high_odd); =20 - tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); - tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); - tcg_gen_addi_ptr(t_m, cpu_env, pred_full_reg_offset(s, a->rm)); + tcg_gen_addi_ptr(t_d, tcg_env, pred_full_reg_offset(s, a->rd)); + tcg_gen_addi_ptr(t_n, tcg_env, pred_full_reg_offset(s, a->rn)); + tcg_gen_addi_ptr(t_m, tcg_env, pred_full_reg_offset(s, a->rm)); =20 fn(t_d, t_n, t_m, tcg_constant_i32(desc)); return true; @@ -2429,8 +2429,8 @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz= *a, bool high_odd, TCGv_ptr t_n =3D tcg_temp_new_ptr(); uint32_t desc =3D 0; =20 - tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); - tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); + tcg_gen_addi_ptr(t_d, tcg_env, pred_full_reg_offset(s, a->rd)); + tcg_gen_addi_ptr(t_n, tcg_env, pred_full_reg_offset(s, a->rn)); =20 desc =3D FIELD_DP32(desc, PREDDESC, OPRSZ, vsz); desc =3D FIELD_DP32(desc, PREDDESC, ESZ, a->esz); @@ -2525,7 +2525,7 @@ static void find_last_active(DisasContext *s, TCGv_i3= 2 ret, int esz, int pg) desc =3D FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s)); desc =3D FIELD_DP32(desc, PREDDESC, ESZ, esz); =20 - tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg)); + tcg_gen_addi_ptr(t_p, tcg_env, pred_full_reg_offset(s, pg)); =20 gen_helper_sve_last_active_element(ret, t_p, tcg_constant_i32(desc)); } @@ -2602,7 +2602,7 @@ static TCGv_i64 load_last_active(DisasContext *s, TCG= v_i32 last, } #endif tcg_gen_ext_i32_ptr(p, last); - tcg_gen_add_ptr(p, p, cpu_env); + tcg_gen_add_ptr(p, p, tcg_env); =20 return load_esz(p, vec_full_reg_offset(s, rm), esz); } @@ -2674,7 +2674,7 @@ static void do_clast_scalar(DisasContext *s, int esz,= int pg, int rm, } =20 /* The conceit here is that while last < 0 indicates not found, after - * adjusting for cpu_env->vfp.zregs[rm], it is still a valid address + * adjusting for tcg_env->vfp.zregs[rm], it is still a valid address * from which we can load garbage. We then discard the garbage with * a conditional move. */ @@ -2690,7 +2690,7 @@ static bool do_clast_fp(DisasContext *s, arg_rpr_esz = *a, bool before) if (sve_access_check(s)) { int esz =3D a->esz; int ofs =3D vec_reg_offset(s, a->rd, 0, esz); - TCGv_i64 reg =3D load_esz(cpu_env, ofs, esz); + TCGv_i64 reg =3D load_esz(tcg_env, ofs, esz); =20 do_clast_scalar(s, esz, a->pg, a->rn, before, reg); write_fp_dreg(s, a->rd, reg); @@ -2794,7 +2794,7 @@ static bool trans_CPY_m_v(DisasContext *s, arg_rpr_es= z *a) } if (sve_access_check(s)) { int ofs =3D vec_reg_offset(s, a->rn, 0, a->esz); - TCGv_i64 t =3D load_esz(cpu_env, ofs, a->esz); + TCGv_i64 t =3D load_esz(tcg_env, ofs, a->esz); do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, t); } return true; @@ -2847,10 +2847,10 @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr= _esz *a, zm =3D tcg_temp_new_ptr(); pg =3D tcg_temp_new_ptr(); =20 - tcg_gen_addi_ptr(pd, cpu_env, pred_full_reg_offset(s, a->rd)); - tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn)); - tcg_gen_addi_ptr(zm, cpu_env, vec_full_reg_offset(s, a->rm)); - tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg)); + tcg_gen_addi_ptr(pd, tcg_env, pred_full_reg_offset(s, a->rd)); + tcg_gen_addi_ptr(zn, tcg_env, vec_full_reg_offset(s, a->rn)); + tcg_gen_addi_ptr(zm, tcg_env, vec_full_reg_offset(s, a->rm)); + tcg_gen_addi_ptr(pg, tcg_env, pred_full_reg_offset(s, a->pg)); =20 gen_fn(t, pd, zn, zm, pg, tcg_constant_i32(simd_desc(vsz, vsz, 0))); =20 @@ -2920,9 +2920,9 @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_e= sz *a, zn =3D tcg_temp_new_ptr(); pg =3D tcg_temp_new_ptr(); =20 - tcg_gen_addi_ptr(pd, cpu_env, pred_full_reg_offset(s, a->rd)); - tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn)); - tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg)); + tcg_gen_addi_ptr(pd, tcg_env, pred_full_reg_offset(s, a->rd)); + tcg_gen_addi_ptr(zn, tcg_env, vec_full_reg_offset(s, a->rn)); + tcg_gen_addi_ptr(pg, tcg_env, pred_full_reg_offset(s, a->pg)); =20 gen_fn(t, pd, zn, pg, tcg_constant_i32(simd_desc(vsz, vsz, a->imm))); =20 @@ -2971,10 +2971,10 @@ static bool do_brk3(DisasContext *s, arg_rprr_s *a, TCGv_ptr g =3D tcg_temp_new_ptr(); TCGv_i32 desc =3D tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)= ); =20 - tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd)); - tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn)); - tcg_gen_addi_ptr(m, cpu_env, pred_full_reg_offset(s, a->rm)); - tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg)); + tcg_gen_addi_ptr(d, tcg_env, pred_full_reg_offset(s, a->rd)); + tcg_gen_addi_ptr(n, tcg_env, pred_full_reg_offset(s, a->rn)); + tcg_gen_addi_ptr(m, tcg_env, pred_full_reg_offset(s, a->rm)); + tcg_gen_addi_ptr(g, tcg_env, pred_full_reg_offset(s, a->pg)); =20 if (a->s) { TCGv_i32 t =3D tcg_temp_new_i32(); @@ -3001,9 +3001,9 @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a, TCGv_ptr g =3D tcg_temp_new_ptr(); TCGv_i32 desc =3D tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)= ); =20 - tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd)); - tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn)); - tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg)); + tcg_gen_addi_ptr(d, tcg_env, pred_full_reg_offset(s, a->rd)); + tcg_gen_addi_ptr(n, tcg_env, pred_full_reg_offset(s, a->rn)); + tcg_gen_addi_ptr(g, tcg_env, pred_full_reg_offset(s, a->pg)); =20 if (a->s) { TCGv_i32 t =3D tcg_temp_new_i32(); @@ -3044,10 +3044,10 @@ static void do_cntp(DisasContext *s, TCGv_i64 val, = int esz, int pn, int pg) if (psz <=3D 8) { uint64_t psz_mask; =20 - tcg_gen_ld_i64(val, cpu_env, pred_full_reg_offset(s, pn)); + tcg_gen_ld_i64(val, tcg_env, pred_full_reg_offset(s, pn)); if (pn !=3D pg) { TCGv_i64 g =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(g, cpu_env, pred_full_reg_offset(s, pg)); + tcg_gen_ld_i64(g, tcg_env, pred_full_reg_offset(s, pg)); tcg_gen_and_i64(val, val, g); } =20 @@ -3066,8 +3066,8 @@ static void do_cntp(DisasContext *s, TCGv_i64 val, in= t esz, int pn, int pg) desc =3D FIELD_DP32(desc, PREDDESC, OPRSZ, psz); desc =3D FIELD_DP32(desc, PREDDESC, ESZ, esz); =20 - tcg_gen_addi_ptr(t_pn, cpu_env, pred_full_reg_offset(s, pn)); - tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); + tcg_gen_addi_ptr(t_pn, tcg_env, pred_full_reg_offset(s, pn)); + tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg)); =20 gen_helper_sve_cntp(val, t_pn, t_pg, tcg_constant_i32(desc)); } @@ -3291,7 +3291,7 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a) desc =3D FIELD_DP32(desc, PREDDESC, ESZ, a->esz); =20 ptr =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd)); + tcg_gen_addi_ptr(ptr, tcg_env, pred_full_reg_offset(s, a->rd)); =20 if (a->lt) { gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc)); @@ -3354,7 +3354,7 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHIL= E_ptr *a) desc =3D FIELD_DP32(desc, PREDDESC, ESZ, a->esz); =20 ptr =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd)); + tcg_gen_addi_ptr(ptr, tcg_env, pred_full_reg_offset(s, a->rd)); =20 gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc)); do_pred_flags(t2); @@ -3684,8 +3684,8 @@ static bool do_reduce(DisasContext *s, arg_rpr_esz *a, t_zn =3D tcg_temp_new_ptr(); t_pg =3D tcg_temp_new_ptr(); =20 - tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn)); - tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); + tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, a->rn)); + tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg)); status =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_FPC= R); =20 fn(temp, t_zn, t_pg, status, t_desc); @@ -3802,11 +3802,11 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_e= sz *a) return true; } =20 - t_val =3D load_esz(cpu_env, vec_reg_offset(s, a->rn, 0, a->esz), a->es= z); + t_val =3D load_esz(tcg_env, vec_reg_offset(s, a->rn, 0, a->esz), a->es= z); t_rm =3D tcg_temp_new_ptr(); t_pg =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm)); - tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); + tcg_gen_addi_ptr(t_rm, tcg_env, vec_full_reg_offset(s, a->rm)); + tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, a->pg)); t_fpst =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_FPC= R); t_desc =3D tcg_constant_i32(simd_desc(vsz, vsz, 0)); =20 @@ -3878,9 +3878,9 @@ static void do_fp_scalar(DisasContext *s, int zd, int= zn, int pg, bool is_fp16, t_zd =3D tcg_temp_new_ptr(); t_zn =3D tcg_temp_new_ptr(); t_pg =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, zd)); - tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, zn)); - tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); + tcg_gen_addi_ptr(t_zd, tcg_env, vec_full_reg_offset(s, zd)); + tcg_gen_addi_ptr(t_zn, tcg_env, vec_full_reg_offset(s, zn)); + tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg)); =20 status =3D fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR); desc =3D tcg_constant_i32(simd_desc(vsz, vsz, 0)); @@ -4228,7 +4228,7 @@ void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int = vofs, =20 /* * Predicate register loads can be any multiple of 2. - * Note that we still store the entire 64-bit unit into cpu_env. + * Note that we still store the entire 64-bit unit into tcg_env. */ if (len_remain >=3D 8) { t0 =3D tcg_temp_new_i64(); @@ -4370,7 +4370,7 @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D vec_full_reg_size(s); int off =3D vec_full_reg_offset(s, a->rd); - gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); + gen_sve_ldr(s, tcg_env, off, size, a->rn, a->imm * size); } return true; } @@ -4383,7 +4383,7 @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D pred_full_reg_size(s); int off =3D pred_full_reg_offset(s, a->rd); - gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); + gen_sve_ldr(s, tcg_env, off, size, a->rn, a->imm * size); } return true; } @@ -4396,7 +4396,7 @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D vec_full_reg_size(s); int off =3D vec_full_reg_offset(s, a->rd); - gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size); + gen_sve_str(s, tcg_env, off, size, a->rn, a->imm * size); } return true; } @@ -4409,7 +4409,7 @@ static bool trans_STR_pri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D pred_full_reg_size(s); int off =3D pred_full_reg_offset(s, a->rd); - gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size); + gen_sve_str(s, tcg_env, off, size, a->rn, a->imm * size); } return true; } @@ -4465,8 +4465,8 @@ static void do_mem_zpa(DisasContext *s, int zt, int p= g, TCGv_i64 addr, desc =3D simd_desc(vsz, vsz, zt | desc); t_pg =3D tcg_temp_new_ptr(); =20 - tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); - fn(cpu_env, t_pg, addr, tcg_constant_i32(desc)); + tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg)); + fn(tcg_env, t_pg, addr, tcg_constant_i32(desc)); } =20 /* Indexed by [mte][be][dtype][nreg] */ @@ -4860,18 +4860,18 @@ static void do_ldrq(DisasContext *s, int zt, int pg= , TCGv_i64 addr, int dtype) #if HOST_BIG_ENDIAN poff +=3D 6; #endif - tcg_gen_ld16u_i64(tmp, cpu_env, poff); + tcg_gen_ld16u_i64(tmp, tcg_env, poff); =20 poff =3D offsetof(CPUARMState, vfp.preg_tmp); - tcg_gen_st_i64(tmp, cpu_env, poff); + tcg_gen_st_i64(tmp, tcg_env, poff); } =20 t_pg =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(t_pg, cpu_env, poff); + tcg_gen_addi_ptr(t_pg, tcg_env, poff); =20 gen_helper_gvec_mem *fn =3D ldr_fns[s->mte_active[0]][s->be_data =3D=3D MO_BE][dtype][0]; - fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt))); + fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt))); =20 /* Replicate that first quadword. */ if (vsz > 16) { @@ -4939,18 +4939,18 @@ static void do_ldro(DisasContext *s, int zt, int pg= , TCGv_i64 addr, int dtype) #if HOST_BIG_ENDIAN poff +=3D 4; #endif - tcg_gen_ld32u_i64(tmp, cpu_env, poff); + tcg_gen_ld32u_i64(tmp, tcg_env, poff); =20 poff =3D offsetof(CPUARMState, vfp.preg_tmp); - tcg_gen_st_i64(tmp, cpu_env, poff); + tcg_gen_st_i64(tmp, tcg_env, poff); } =20 t_pg =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(t_pg, cpu_env, poff); + tcg_gen_addi_ptr(t_pg, tcg_env, poff); =20 gen_helper_gvec_mem *fn =3D ldr_fns[s->mte_active[0]][s->be_data =3D=3D MO_BE][dtype][0]; - fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt))); + fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt))); =20 /* * Replicate that first octaword. @@ -5027,7 +5027,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri= _load *a) */ uint64_t psz_mask =3D MAKE_64BIT_MASK(0, psz * 8); temp =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(temp, cpu_env, pred_full_reg_offset(s, a->pg)); + tcg_gen_ld_i64(temp, tcg_env, pred_full_reg_offset(s, a->pg)); tcg_gen_andi_i64(temp, temp, pred_esz_masks[esz] & psz_mask); tcg_gen_brcondi_i64(TCG_COND_EQ, temp, 0, over); } else { @@ -5238,10 +5238,10 @@ static void do_mem_zpz(DisasContext *s, int zt, int= pg, int zm, } desc =3D simd_desc(vsz, vsz, desc | scale); =20 - tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); - tcg_gen_addi_ptr(t_zm, cpu_env, vec_full_reg_offset(s, zm)); - tcg_gen_addi_ptr(t_zt, cpu_env, vec_full_reg_offset(s, zt)); - fn(cpu_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc)); + tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg)); + tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm)); + tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt)); + fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc)); } =20 /* Indexed by [mte][be][ff][xs][u][msz]. */ @@ -7197,7 +7197,7 @@ static bool do_FMLAL_zzzw(DisasContext *s, arg_rrrr_e= sz *a, bool sub, bool sel) { return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzzw_s, a->rd, a->rn, a->rm, a->ra, - (sel << 1) | sub, cpu_env); + (sel << 1) | sub, tcg_env); } =20 TRANS_FEAT(FMLALB_zzzw, aa64_sve2, do_FMLAL_zzzw, a, false, false) @@ -7209,7 +7209,7 @@ static bool do_FMLAL_zzxw(DisasContext *s, arg_rrxr_e= sz *a, bool sub, bool sel) { return gen_gvec_ptr_zzzz(s, gen_helper_sve2_fmlal_zzxw_s, a->rd, a->rn, a->rm, a->ra, - (a->index << 2) | (sel << 1) | sub, cpu_env); + (a->index << 2) | (sel << 1) | sub, tcg_env); } =20 TRANS_FEAT(FMLALB_zzxw, aa64_sve2, do_FMLAL_zzxw, a, false, false) @@ -7289,7 +7289,7 @@ static bool trans_PSEL(DisasContext *s, arg_psel *a) =20 /* Load the predicate word. */ tcg_gen_trunc_i64_ptr(ptr, didx); - tcg_gen_add_ptr(ptr, ptr, cpu_env); + tcg_gen_add_ptr(ptr, ptr, tcg_env); tcg_gen_ld8u_i64(tmp, ptr, pred_full_reg_offset(s, a->pm)); =20 /* Extract the predicate bit and replicate to MO_64. */ diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index d3e89fda91..b9af03b7c3 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -30,22 +30,22 @@ =20 static inline void vfp_load_reg64(TCGv_i64 var, int reg) { - tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg)); + tcg_gen_ld_i64(var, tcg_env, vfp_reg_offset(true, reg)); } =20 static inline void vfp_store_reg64(TCGv_i64 var, int reg) { - tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg)); + tcg_gen_st_i64(var, tcg_env, vfp_reg_offset(true, reg)); } =20 static inline void vfp_load_reg32(TCGv_i32 var, int reg) { - tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg)); + tcg_gen_ld_i32(var, tcg_env, vfp_reg_offset(false, reg)); } =20 static inline void vfp_store_reg32(TCGv_i32 var, int reg) { - tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); + tcg_gen_st_i32(var, tcg_env, vfp_reg_offset(false, reg)); } =20 /* @@ -116,7 +116,7 @@ static void gen_preserve_fp_state(DisasContext *s, bool= skip_context_update) if (translator_io_start(&s->base)) { s->base.is_jmp =3D DISAS_UPDATE_EXIT; } - gen_helper_v7m_preserve_fp_state(cpu_env); + gen_helper_v7m_preserve_fp_state(tcg_env); /* * If the preserve_fp_state helper doesn't throw an exception * then it will clear LSPACT; we don't need to repeat this for @@ -172,7 +172,7 @@ static void gen_update_fp_context(DisasContext *s) uint32_t bits =3D R_V7M_CONTROL_FPCA_MASK; =20 fpscr =3D load_cpu_field(v7m.fpdscr[s->v8m_secure]); - gen_helper_vfp_set_fpscr(cpu_env, fpscr); + gen_helper_vfp_set_fpscr(tcg_env, fpscr); if (dc_isar_feature(aa32_mve, s)) { store_cpu_field(tcg_constant_i32(0), v7m.vpr); } @@ -815,7 +815,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) if (s->current_el =3D=3D 1) { gen_set_condexec(s); gen_update_pc(s, 0); - gen_helper_check_hcr_el2_trap(cpu_env, + gen_helper_check_hcr_el2_trap(tcg_env, tcg_constant_i32(a->rt), tcg_constant_i32(a->reg)); } @@ -831,7 +831,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); } else { tmp =3D tcg_temp_new_i32(); - gen_helper_vfp_get_fpscr(tmp, cpu_env); + gen_helper_vfp_get_fpscr(tmp, tcg_env); } break; default: @@ -855,7 +855,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) break; case ARM_VFP_FPSCR: tmp =3D load_reg(s, a->rt); - gen_helper_vfp_set_fpscr(cpu_env, tmp); + gen_helper_vfp_set_fpscr(tcg_env, tmp); gen_lookup_tb(s); break; case ARM_VFP_FPEXC: @@ -1169,7 +1169,7 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_V= LDM_VSTM_sp *a) * value is above, it is UNKNOWN whether the limit check * triggers; we choose to trigger. */ - gen_helper_v8m_stackcheck(cpu_env, addr); + gen_helper_v8m_stackcheck(tcg_env, addr); } =20 offset =3D 4; @@ -1252,7 +1252,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_V= LDM_VSTM_dp *a) * value is above, it is UNKNOWN whether the limit check * triggers; we choose to trigger. */ - gen_helper_v8m_stackcheck(cpu_env, addr); + gen_helper_v8m_stackcheck(tcg_env, addr); } =20 offset =3D 8; @@ -2419,17 +2419,17 @@ DO_VFP_2OP(VNEG, dp, gen_helper_vfp_negd, aa32_fpdp= _v2) =20 static void gen_VSQRT_hp(TCGv_i32 vd, TCGv_i32 vm) { - gen_helper_vfp_sqrth(vd, vm, cpu_env); + gen_helper_vfp_sqrth(vd, vm, tcg_env); } =20 static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm) { - gen_helper_vfp_sqrts(vd, vm, cpu_env); + gen_helper_vfp_sqrts(vd, vm, tcg_env); } =20 static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm) { - gen_helper_vfp_sqrtd(vd, vm, cpu_env); + gen_helper_vfp_sqrtd(vd, vm, tcg_env); } =20 DO_VFP_2OP(VSQRT, hp, gen_VSQRT_hp, aa32_fp16_arith) @@ -2464,9 +2464,9 @@ static bool trans_VCMP_hp(DisasContext *s, arg_VCMP_s= p *a) } =20 if (a->e) { - gen_helper_vfp_cmpeh(vd, vm, cpu_env); + gen_helper_vfp_cmpeh(vd, vm, tcg_env); } else { - gen_helper_vfp_cmph(vd, vm, cpu_env); + gen_helper_vfp_cmph(vd, vm, tcg_env); } return true; } @@ -2499,9 +2499,9 @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_s= p *a) } =20 if (a->e) { - gen_helper_vfp_cmpes(vd, vm, cpu_env); + gen_helper_vfp_cmpes(vd, vm, tcg_env); } else { - gen_helper_vfp_cmps(vd, vm, cpu_env); + gen_helper_vfp_cmps(vd, vm, tcg_env); } return true; } @@ -2539,9 +2539,9 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_d= p *a) } =20 if (a->e) { - gen_helper_vfp_cmped(vd, vm, cpu_env); + gen_helper_vfp_cmped(vd, vm, tcg_env); } else { - gen_helper_vfp_cmpd(vd, vm, cpu_env); + gen_helper_vfp_cmpd(vd, vm, tcg_env); } return true; } @@ -2564,7 +2564,7 @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_V= CVT_f32_f16 *a) ahp_mode =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); /* The T bit tells us if we want the low or high 16 bits of Vm */ - tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); + tcg_gen_ld16u_i32(tmp, tcg_env, vfp_f16_offset(a->vm, a->t)); gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode); vfp_store_reg32(tmp, a->vd); return true; @@ -2598,7 +2598,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_V= CVT_f64_f16 *a) ahp_mode =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); /* The T bit tells us if we want the low or high 16 bits of Vm */ - tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); + tcg_gen_ld16u_i32(tmp, tcg_env, vfp_f16_offset(a->vm, a->t)); vd =3D tcg_temp_new_i64(); gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode); vfp_store_reg64(vd, a->vd); @@ -2623,7 +2623,7 @@ static bool trans_VCVT_b16_f32(DisasContext *s, arg_V= CVT_b16_f32 *a) =20 vfp_load_reg32(tmp, a->vm); gen_helper_bfcvt(tmp, tmp, fpst); - tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); + tcg_gen_st16_i32(tmp, tcg_env, vfp_f16_offset(a->vd, a->t)); return true; } =20 @@ -2647,7 +2647,7 @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_V= CVT_f16_f32 *a) =20 vfp_load_reg32(tmp, a->vm); gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode); - tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); + tcg_gen_st16_i32(tmp, tcg_env, vfp_f16_offset(a->vd, a->t)); return true; } =20 @@ -2682,7 +2682,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_V= CVT_f16_f64 *a) =20 vfp_load_reg64(vm, a->vm); gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode); - tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); + tcg_gen_st16_i32(tmp, tcg_env, vfp_f16_offset(a->vd, a->t)); return true; } =20 @@ -2932,7 +2932,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_s= p *a) vm =3D tcg_temp_new_i32(); vd =3D tcg_temp_new_i64(); vfp_load_reg32(vm, a->vm); - gen_helper_vfp_fcvtds(vd, vm, cpu_env); + gen_helper_vfp_fcvtds(vd, vm, tcg_env); vfp_store_reg64(vd, a->vd); return true; } @@ -2958,7 +2958,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_d= p *a) vd =3D tcg_temp_new_i32(); vm =3D tcg_temp_new_i64(); vfp_load_reg64(vm, a->vm); - gen_helper_vfp_fcvtsd(vd, vm, cpu_env); + gen_helper_vfp_fcvtsd(vd, vm, tcg_env); vfp_store_reg32(vd, a->vd); return true; } @@ -3076,7 +3076,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) vm =3D tcg_temp_new_i64(); vd =3D tcg_temp_new_i32(); vfp_load_reg64(vm, a->vm); - gen_helper_vjcvt(vd, vm, cpu_env); + gen_helper_vjcvt(vd, vm, tcg_env); vfp_store_reg32(vd, a->vd); return true; } diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index d83a0e772c..2524d8f3fb 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -63,18 +63,18 @@ void arm_translate_init(void) int i; =20 for (i =3D 0; i < 16; i++) { - cpu_R[i] =3D tcg_global_mem_new_i32(cpu_env, + cpu_R[i] =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, regs[i]), regnames[i]); } - cpu_CF =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, CF), = "CF"); - cpu_NF =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, NF), = "NF"); - cpu_VF =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, VF), = "VF"); - cpu_ZF =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUARMState, ZF), = "ZF"); + cpu_CF =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, CF), = "CF"); + cpu_NF =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, NF), = "NF"); + cpu_VF =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, VF), = "VF"); + cpu_ZF =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUARMState, ZF), = "ZF"); =20 - cpu_exclusive_addr =3D tcg_global_mem_new_i64(cpu_env, + cpu_exclusive_addr =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUARMState, exclusive_addr), "exclusive_addr"); - cpu_exclusive_val =3D tcg_global_mem_new_i64(cpu_env, + cpu_exclusive_val =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUARMState, exclusive_val), "exclusive_val"); =20 a64_translate_init(); @@ -179,10 +179,10 @@ void store_cpu_offset(TCGv_i32 var, int offset, int s= ize) { switch (size) { case 1: - tcg_gen_st8_i32(var, cpu_env, offset); + tcg_gen_st8_i32(var, tcg_env, offset); break; case 4: - tcg_gen_st_i32(var, cpu_env, offset); + tcg_gen_st_i32(var, tcg_env, offset); break; default: g_assert_not_reached(); @@ -329,7 +329,7 @@ static void store_sp_checked(DisasContext *s, TCGv_i32 = var) { #ifndef CONFIG_USER_ONLY if (s->v8m_stackcheck) { - gen_helper_v8m_stackcheck(cpu_env, var); + gen_helper_v8m_stackcheck(tcg_env, var); } #endif store_reg(s, 13, var); @@ -346,7 +346,7 @@ static void store_sp_checked(DisasContext *s, TCGv_i32 = var) =20 void gen_set_cpsr(TCGv_i32 var, uint32_t mask) { - gen_helper_cpsr_write(cpu_env, var, tcg_constant_i32(mask)); + gen_helper_cpsr_write(tcg_env, var, tcg_constant_i32(mask)); } =20 static void gen_rebuild_hflags(DisasContext *s, bool new_el) @@ -355,16 +355,16 @@ static void gen_rebuild_hflags(DisasContext *s, bool = new_el) =20 if (new_el) { if (m_profile) { - gen_helper_rebuild_hflags_m32_newel(cpu_env); + gen_helper_rebuild_hflags_m32_newel(tcg_env); } else { - gen_helper_rebuild_hflags_a32_newel(cpu_env); + gen_helper_rebuild_hflags_a32_newel(tcg_env); } } else { TCGv_i32 tcg_el =3D tcg_constant_i32(s->current_el); if (m_profile) { - gen_helper_rebuild_hflags_m32(cpu_env, tcg_el); + gen_helper_rebuild_hflags_m32(tcg_env, tcg_el); } else { - gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + gen_helper_rebuild_hflags_a32(tcg_env, tcg_el); } } } @@ -372,7 +372,7 @@ static void gen_rebuild_hflags(DisasContext *s, bool ne= w_el) static void gen_exception_internal(int excp) { assert(excp_is_internal(excp)); - gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp)); + gen_helper_exception_internal(tcg_env, tcg_constant_i32(excp)); } =20 static void gen_singlestep_exception(DisasContext *s) @@ -617,10 +617,10 @@ static inline void gen_arm_shift_reg(TCGv_i32 var, in= t shiftop, { if (flags) { switch (shiftop) { - case 0: gen_helper_shl_cc(var, cpu_env, var, shift); break; - case 1: gen_helper_shr_cc(var, cpu_env, var, shift); break; - case 2: gen_helper_sar_cc(var, cpu_env, var, shift); break; - case 3: gen_helper_ror_cc(var, cpu_env, var, shift); break; + case 0: gen_helper_shl_cc(var, tcg_env, var, shift); break; + case 1: gen_helper_shr_cc(var, tcg_env, var, shift); break; + case 2: gen_helper_sar_cc(var, tcg_env, var, shift); break; + case 3: gen_helper_ror_cc(var, tcg_env, var, shift); break; } } else { switch (shiftop) { @@ -849,7 +849,7 @@ static inline void gen_bxns(DisasContext *s, int rm) * is correct in the non-UNPREDICTABLE cases, and we can choose * "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise. */ - gen_helper_v7m_bxns(cpu_env, var); + gen_helper_v7m_bxns(tcg_env, var); s->base.is_jmp =3D DISAS_EXIT; } =20 @@ -862,7 +862,7 @@ static inline void gen_blxns(DisasContext *s, int rm) * The blxns helper may throw an exception. */ gen_update_pc(s, curr_insn_len(s)); - gen_helper_v7m_blxns(cpu_env, var); + gen_helper_v7m_blxns(tcg_env, var); s->base.is_jmp =3D DISAS_EXIT; } =20 @@ -1024,7 +1024,7 @@ static inline void gen_hvc(DisasContext *s, int imm16) * the insn really executes). */ gen_update_pc(s, 0); - gen_helper_pre_hvc(cpu_env); + gen_helper_pre_hvc(tcg_env); /* Otherwise we will treat this as a real exception which * happens after execution of the insn. (The distinction matters * for the PC value reported to the exception handler and also @@ -1041,7 +1041,7 @@ static inline void gen_smc(DisasContext *s) * the insn executes. */ gen_update_pc(s, 0); - gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa32_smc())); + gen_helper_pre_smc(tcg_env, tcg_constant_i32(syn_aa32_smc())); gen_update_pc(s, curr_insn_len(s)); s->base.is_jmp =3D DISAS_SMC; } @@ -1056,7 +1056,7 @@ static void gen_exception_internal_insn(DisasContext = *s, int excp) =20 static void gen_exception_el_v(int excp, uint32_t syndrome, TCGv_i32 tcg_e= l) { - gen_helper_exception_with_syndrome_el(cpu_env, tcg_constant_i32(excp), + gen_helper_exception_with_syndrome_el(tcg_env, tcg_constant_i32(excp), tcg_constant_i32(syndrome), tcg_= el); } =20 @@ -1067,7 +1067,7 @@ static void gen_exception_el(int excp, uint32_t syndr= ome, uint32_t target_el) =20 static void gen_exception(int excp, uint32_t syndrome) { - gen_helper_exception_with_syndrome(cpu_env, tcg_constant_i32(excp), + gen_helper_exception_with_syndrome(tcg_env, tcg_constant_i32(excp), tcg_constant_i32(syndrome)); } =20 @@ -1108,7 +1108,7 @@ static void gen_exception_bkpt_insn(DisasContext *s, = uint32_t syn) { gen_set_condexec(s); gen_update_pc(s, 0); - gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syn)); + gen_helper_exception_bkpt_insn(tcg_env, tcg_constant_i32(syn)); s->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -1192,20 +1192,20 @@ void read_neon_element32(TCGv_i32 dest, int reg, in= t ele, MemOp memop) =20 switch (memop) { case MO_SB: - tcg_gen_ld8s_i32(dest, cpu_env, off); + tcg_gen_ld8s_i32(dest, tcg_env, off); break; case MO_UB: - tcg_gen_ld8u_i32(dest, cpu_env, off); + tcg_gen_ld8u_i32(dest, tcg_env, off); break; case MO_SW: - tcg_gen_ld16s_i32(dest, cpu_env, off); + tcg_gen_ld16s_i32(dest, tcg_env, off); break; case MO_UW: - tcg_gen_ld16u_i32(dest, cpu_env, off); + tcg_gen_ld16u_i32(dest, tcg_env, off); break; case MO_UL: case MO_SL: - tcg_gen_ld_i32(dest, cpu_env, off); + tcg_gen_ld_i32(dest, tcg_env, off); break; default: g_assert_not_reached(); @@ -1218,13 +1218,13 @@ void read_neon_element64(TCGv_i64 dest, int reg, in= t ele, MemOp memop) =20 switch (memop) { case MO_SL: - tcg_gen_ld32s_i64(dest, cpu_env, off); + tcg_gen_ld32s_i64(dest, tcg_env, off); break; case MO_UL: - tcg_gen_ld32u_i64(dest, cpu_env, off); + tcg_gen_ld32u_i64(dest, tcg_env, off); break; case MO_UQ: - tcg_gen_ld_i64(dest, cpu_env, off); + tcg_gen_ld_i64(dest, tcg_env, off); break; default: g_assert_not_reached(); @@ -1237,13 +1237,13 @@ void write_neon_element32(TCGv_i32 src, int reg, in= t ele, MemOp memop) =20 switch (memop) { case MO_8: - tcg_gen_st8_i32(src, cpu_env, off); + tcg_gen_st8_i32(src, tcg_env, off); break; case MO_16: - tcg_gen_st16_i32(src, cpu_env, off); + tcg_gen_st16_i32(src, tcg_env, off); break; case MO_32: - tcg_gen_st_i32(src, cpu_env, off); + tcg_gen_st_i32(src, tcg_env, off); break; default: g_assert_not_reached(); @@ -1256,10 +1256,10 @@ void write_neon_element64(TCGv_i64 src, int reg, in= t ele, MemOp memop) =20 switch (memop) { case MO_32: - tcg_gen_st32_i64(src, cpu_env, off); + tcg_gen_st32_i64(src, tcg_env, off); break; case MO_64: - tcg_gen_st_i64(src, cpu_env, off); + tcg_gen_st_i64(src, tcg_env, off); break; default: g_assert_not_reached(); @@ -1270,24 +1270,24 @@ void write_neon_element64(TCGv_i64 src, int reg, in= t ele, MemOp memop) =20 static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) { - tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); + tcg_gen_ld_i64(var, tcg_env, offsetof(CPUARMState, iwmmxt.regs[reg])); } =20 static inline void iwmmxt_store_reg(TCGv_i64 var, int reg) { - tcg_gen_st_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); + tcg_gen_st_i64(var, tcg_env, offsetof(CPUARMState, iwmmxt.regs[reg])); } =20 static inline TCGv_i32 iwmmxt_load_creg(int reg) { TCGv_i32 var =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); + tcg_gen_ld_i32(var, tcg_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); return var; } =20 static inline void iwmmxt_store_creg(int reg, TCGv_i32 var) { - tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); + tcg_gen_st_i32(var, tcg_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); } =20 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn) @@ -1329,7 +1329,7 @@ static inline void gen_op_iwmmxt_##name##_M0_wRn(int = rn) \ static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ { \ iwmmxt_load_reg(cpu_V1, rn); \ - gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \ + gen_helper_iwmmxt_##name(cpu_M0, tcg_env, cpu_M0, cpu_V1); \ } =20 #define IWMMXT_OP_ENV_SIZE(name) \ @@ -1340,7 +1340,7 @@ IWMMXT_OP_ENV(name##l) #define IWMMXT_OP_ENV1(name) \ static inline void gen_op_iwmmxt_##name##_M0(void) \ { \ - gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \ + gen_helper_iwmmxt_##name(cpu_M0, tcg_env, cpu_M0); \ } =20 IWMMXT_OP(maddsq) @@ -2113,13 +2113,13 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) } switch ((insn >> 22) & 3) { case 1: - gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp); + gen_helper_iwmmxt_srlw(cpu_M0, tcg_env, cpu_M0, tmp); break; case 2: - gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp); + gen_helper_iwmmxt_srll(cpu_M0, tcg_env, cpu_M0, tmp); break; case 3: - gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp); + gen_helper_iwmmxt_srlq(cpu_M0, tcg_env, cpu_M0, tmp); break; } gen_op_iwmmxt_movq_wRn_M0(wrd); @@ -2139,13 +2139,13 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) } switch ((insn >> 22) & 3) { case 1: - gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp); + gen_helper_iwmmxt_sraw(cpu_M0, tcg_env, cpu_M0, tmp); break; case 2: - gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp); + gen_helper_iwmmxt_sral(cpu_M0, tcg_env, cpu_M0, tmp); break; case 3: - gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp); + gen_helper_iwmmxt_sraq(cpu_M0, tcg_env, cpu_M0, tmp); break; } gen_op_iwmmxt_movq_wRn_M0(wrd); @@ -2165,13 +2165,13 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) } switch ((insn >> 22) & 3) { case 1: - gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp); + gen_helper_iwmmxt_sllw(cpu_M0, tcg_env, cpu_M0, tmp); break; case 2: - gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp); + gen_helper_iwmmxt_slll(cpu_M0, tcg_env, cpu_M0, tmp); break; case 3: - gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp); + gen_helper_iwmmxt_sllq(cpu_M0, tcg_env, cpu_M0, tmp); break; } gen_op_iwmmxt_movq_wRn_M0(wrd); @@ -2191,19 +2191,19 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) if (gen_iwmmxt_shift(insn, 0xf, tmp)) { return 1; } - gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp); + gen_helper_iwmmxt_rorw(cpu_M0, tcg_env, cpu_M0, tmp); break; case 2: if (gen_iwmmxt_shift(insn, 0x1f, tmp)) { return 1; } - gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp); + gen_helper_iwmmxt_rorl(cpu_M0, tcg_env, cpu_M0, tmp); break; case 3: if (gen_iwmmxt_shift(insn, 0x3f, tmp)) { return 1; } - gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp); + gen_helper_iwmmxt_rorq(cpu_M0, tcg_env, cpu_M0, tmp); break; } gen_op_iwmmxt_movq_wRn_M0(wrd); @@ -2335,7 +2335,7 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) rd0 =3D (insn >> 16) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); tmp =3D tcg_constant_i32(((insn >> 16) & 0xf0) | (insn & 0x0f)); - gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp); + gen_helper_iwmmxt_shufh(cpu_M0, tcg_env, cpu_M0, tmp); gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); gen_op_iwmmxt_set_cup(); @@ -2857,7 +2857,7 @@ static void gen_msr_banked(DisasContext *s, int r, in= t sysm, int rn) gen_set_condexec(s); gen_update_pc(s, 0); tcg_reg =3D load_reg(s, rn); - gen_helper_msr_banked(cpu_env, tcg_reg, + gen_helper_msr_banked(tcg_env, tcg_reg, tcg_constant_i32(tgtmode), tcg_constant_i32(regno)); s->base.is_jmp =3D DISAS_UPDATE_EXIT; @@ -2876,7 +2876,7 @@ static void gen_mrs_banked(DisasContext *s, int r, in= t sysm, int rn) gen_set_condexec(s); gen_update_pc(s, 0); tcg_reg =3D tcg_temp_new_i32(); - gen_helper_mrs_banked(tcg_reg, cpu_env, + gen_helper_mrs_banked(tcg_reg, tcg_env, tcg_constant_i32(tgtmode), tcg_constant_i32(regno)); store_reg(s, rn, tcg_reg); @@ -2901,7 +2901,7 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCG= v_i32 cpsr) * be called after storing the new PC. */ translator_io_start(&s->base); - gen_helper_cpsr_write_eret(cpu_env, cpsr); + gen_helper_cpsr_write_eret(tcg_env, cpsr); /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; } @@ -2918,7 +2918,7 @@ static void gen_gvec_fn3_qc(uint32_t rd_ofs, uint32_t= rn_ofs, uint32_t rm_ofs, { TCGv_ptr qc_ptr =3D tcg_temp_new_ptr(); =20 - tcg_gen_addi_ptr(qc_ptr, cpu_env, offsetof(CPUARMState, vfp.qc)); + tcg_gen_addi_ptr(qc_ptr, tcg_env, offsetof(CPUARMState, vfp.qc)); tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, qc_ptr, opr_sz, max_sz, 0, fn); } @@ -4605,11 +4605,11 @@ static void do_coproc_insn(DisasContext *s, int cpn= um, int is64, case 0: if (arm_dc_feature(s, ARM_FEATURE_AARCH64) && dc_isar_feature(aa64_tidcp1, s)) { - gen_helper_tidcp_el0(cpu_env, tcg_constant_i32(syndrome)); + gen_helper_tidcp_el0(tcg_env, tcg_constant_i32(syndrome)); } break; case 1: - gen_helper_tidcp_el1(cpu_env, tcg_constant_i32(syndrome)); + gen_helper_tidcp_el1(tcg_env, tcg_constant_i32(syndrome)); break; } } @@ -4654,7 +4654,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, gen_set_condexec(s); gen_update_pc(s, 0); tcg_ri =3D tcg_temp_new_ptr(); - gen_helper_access_check_cp_reg(tcg_ri, cpu_env, + gen_helper_access_check_cp_reg(tcg_ri, tcg_env, tcg_constant_i32(key), tcg_constant_i32(syndrome), tcg_constant_i32(isread)); @@ -4702,10 +4702,10 @@ static void do_coproc_insn(DisasContext *s, int cpn= um, int is64, tcg_ri =3D gen_lookup_cp_reg(key); } tmp64 =3D tcg_temp_new_i64(); - gen_helper_get_cp_reg64(tmp64, cpu_env, tcg_ri); + gen_helper_get_cp_reg64(tmp64, tcg_env, tcg_ri); } else { tmp64 =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset); + tcg_gen_ld_i64(tmp64, tcg_env, ri->fieldoffset); } tmp =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(tmp, tmp64); @@ -4722,7 +4722,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, tcg_ri =3D gen_lookup_cp_reg(key); } tmp =3D tcg_temp_new_i32(); - gen_helper_get_cp_reg(tmp, cpu_env, tcg_ri); + gen_helper_get_cp_reg(tmp, tcg_env, tcg_ri); } else { tmp =3D load_cpu_offset(ri->fieldoffset); } @@ -4752,9 +4752,9 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, if (!tcg_ri) { tcg_ri =3D gen_lookup_cp_reg(key); } - gen_helper_set_cp_reg64(cpu_env, tcg_ri, tmp64); + gen_helper_set_cp_reg64(tcg_env, tcg_ri, tmp64); } else { - tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset); + tcg_gen_st_i64(tmp64, tcg_env, ri->fieldoffset); } } else { TCGv_i32 tmp =3D load_reg(s, rt); @@ -4762,7 +4762,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, if (!tcg_ri) { tcg_ri =3D gen_lookup_cp_reg(key); } - gen_helper_set_cp_reg(cpu_env, tcg_ri, tmp); + gen_helper_set_cp_reg(tcg_env, tcg_ri, tmp); } else { store_cpu_offset(tmp, ri->fieldoffset, 4); } @@ -5028,7 +5028,7 @@ static void gen_srs(DisasContext *s, /* get_r13_banked() will raise an exception if called from System mode= */ gen_set_condexec(s); gen_update_pc(s, 0); - gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode)); + gen_helper_get_r13_banked(addr, tcg_env, tcg_constant_i32(mode)); switch (amode) { case 0: /* DA */ offset =3D -4; @@ -5069,7 +5069,7 @@ static void gen_srs(DisasContext *s, g_assert_not_reached(); } tcg_gen_addi_i32(addr, addr, offset); - gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr); + gen_helper_set_r13_banked(tcg_env, tcg_constant_i32(mode), addr); } s->base.is_jmp =3D DISAS_UPDATE_EXIT; } @@ -5618,7 +5618,7 @@ static bool trans_LSRL_ri(DisasContext *s, arg_mve_sh= l_ri *a) =20 static void gen_mve_sqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift) { - gen_helper_mve_sqshll(r, cpu_env, n, tcg_constant_i32(shift)); + gen_helper_mve_sqshll(r, tcg_env, n, tcg_constant_i32(shift)); } =20 static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a) @@ -5628,7 +5628,7 @@ static bool trans_SQSHLL_ri(DisasContext *s, arg_mve_= shl_ri *a) =20 static void gen_mve_uqshll(TCGv_i64 r, TCGv_i64 n, int64_t shift) { - gen_helper_mve_uqshll(r, cpu_env, n, tcg_constant_i32(shift)); + gen_helper_mve_uqshll(r, tcg_env, n, tcg_constant_i32(shift)); } =20 static bool trans_UQSHLL_ri(DisasContext *s, arg_mve_shl_ri *a) @@ -5674,7 +5674,7 @@ static bool do_mve_shl_rr(DisasContext *s, arg_mve_sh= l_rr *a, WideShiftFn *fn) tcg_gen_concat_i32_i64(rda, rdalo, rdahi); =20 /* The helper takes care of the sign-extension of the low 8 bits of Rm= */ - fn(rda, cpu_env, rda, cpu_R[a->rm]); + fn(rda, tcg_env, rda, cpu_R[a->rm]); =20 tcg_gen_extrl_i64_i32(rdalo, rda); tcg_gen_extrh_i64_i32(rdahi, rda); @@ -5748,7 +5748,7 @@ static bool trans_SRSHR_ri(DisasContext *s, arg_mve_s= h_ri *a) =20 static void gen_mve_sqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift) { - gen_helper_mve_sqshl(r, cpu_env, n, tcg_constant_i32(shift)); + gen_helper_mve_sqshl(r, tcg_env, n, tcg_constant_i32(shift)); } =20 static bool trans_SQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) @@ -5758,7 +5758,7 @@ static bool trans_SQSHL_ri(DisasContext *s, arg_mve_s= h_ri *a) =20 static void gen_mve_uqshl(TCGv_i32 r, TCGv_i32 n, int32_t shift) { - gen_helper_mve_uqshl(r, cpu_env, n, tcg_constant_i32(shift)); + gen_helper_mve_uqshl(r, tcg_env, n, tcg_constant_i32(shift)); } =20 static bool trans_UQSHL_ri(DisasContext *s, arg_mve_sh_ri *a) @@ -5782,7 +5782,7 @@ static bool do_mve_sh_rr(DisasContext *s, arg_mve_sh_= rr *a, ShiftFn *fn) } =20 /* The helper takes care of the sign-extension of the low 8 bits of Rm= */ - fn(cpu_R[a->rda], cpu_env, cpu_R[a->rda], cpu_R[a->rm]); + fn(cpu_R[a->rda], tcg_env, cpu_R[a->rda], cpu_R[a->rm]); return true; } =20 @@ -5928,12 +5928,12 @@ static bool op_qaddsub(DisasContext *s, arg_rrr *a,= bool add, bool doub) t0 =3D load_reg(s, a->rm); t1 =3D load_reg(s, a->rn); if (doub) { - gen_helper_add_saturate(t1, cpu_env, t1, t1); + gen_helper_add_saturate(t1, tcg_env, t1, t1); } if (add) { - gen_helper_add_saturate(t0, cpu_env, t0, t1); + gen_helper_add_saturate(t0, tcg_env, t0, t1); } else { - gen_helper_sub_saturate(t0, cpu_env, t0, t1); + gen_helper_sub_saturate(t0, tcg_env, t0, t1); } store_reg(s, a->rd, t0); return true; @@ -5977,7 +5977,7 @@ static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, break; case 1: t1 =3D load_reg(s, a->ra); - gen_helper_add_setq(t0, cpu_env, t0, t1); + gen_helper_add_setq(t0, tcg_env, t0, t1); store_reg(s, a->rd, t0); break; case 2: @@ -6041,7 +6041,7 @@ static bool op_smlawx(DisasContext *s, arg_rrrr *a, b= ool add, bool mt) tcg_gen_muls2_i32(t0, t1, t0, t1); if (add) { t0 =3D load_reg(s, a->ra); - gen_helper_add_setq(t1, cpu_env, t1, t0); + gen_helper_add_setq(t1, tcg_env, t1, t0); } store_reg(s, a->rd, t1); return true; @@ -6120,7 +6120,7 @@ static bool trans_ESB(DisasContext *s, arg_ESB *a) * Test for EL2 present, and defer test for SEL2 to runtime. */ if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { - gen_helper_vesb(cpu_env); + gen_helper_vesb(tcg_env); } } return true; @@ -6228,7 +6228,7 @@ static bool trans_MRS_reg(DisasContext *s, arg_MRS_re= g *a) tmp =3D load_cpu_field(spsr); } else { tmp =3D tcg_temp_new_i32(); - gen_helper_cpsr_read(tmp, cpu_env); + gen_helper_cpsr_read(tmp, tcg_env); } store_reg(s, a->rd, tmp); return true; @@ -6257,7 +6257,7 @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7= m *a) return false; } tmp =3D tcg_temp_new_i32(); - gen_helper_v7m_mrs(tmp, cpu_env, tcg_constant_i32(a->sysm)); + gen_helper_v7m_mrs(tmp, tcg_env, tcg_constant_i32(a->sysm)); store_reg(s, a->rd, tmp); return true; } @@ -6271,7 +6271,7 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7= m *a) } addr =3D tcg_constant_i32((a->mask << 10) | a->sysm); reg =3D load_reg(s, a->rn); - gen_helper_v7m_msr(cpu_env, addr, reg); + gen_helper_v7m_msr(tcg_env, addr, reg); /* If we wrote to CONTROL, the EL might have changed */ gen_rebuild_hflags(s, true); gen_lookup_tb(s); @@ -6302,7 +6302,7 @@ static bool trans_BXJ(DisasContext *s, arg_BXJ *a) if (!arm_dc_feature(s, ARM_FEATURE_V8) && arm_dc_feature(s, ARM_FEATURE_EL2) && s->current_el < 2 && s->ns) { - gen_helper_check_bxj_trap(cpu_env, tcg_constant_i32(a->rm)); + gen_helper_check_bxj_trap(tcg_env, tcg_constant_i32(a->rm)); } /* Trivial implementation equivalent to bx. */ gen_bx(s, load_reg(s, a->rm)); @@ -6480,7 +6480,7 @@ static bool trans_TT(DisasContext *s, arg_TT *a) =20 addr =3D load_reg(s, a->rn); tmp =3D tcg_temp_new_i32(); - gen_helper_v7m_tt(tmp, cpu_env, addr, tcg_constant_i32((a->A << 1) | a= ->T)); + gen_helper_v7m_tt(tmp, tcg_env, addr, tcg_constant_i32((a->A << 1) | a= ->T)); store_reg(s, a->rd, tmp); return true; } @@ -6510,7 +6510,7 @@ static TCGv_i32 op_addr_rr_pre(DisasContext *s, arg_l= dst_rr *a) TCGv_i32 addr =3D load_reg(s, a->rn); =20 if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { - gen_helper_v8m_stackcheck(cpu_env, addr); + gen_helper_v8m_stackcheck(tcg_env, addr); } =20 if (a->p) { @@ -6665,9 +6665,9 @@ static TCGv_i32 op_addr_ri_pre(DisasContext *s, arg_l= dst_ri *a) if (!a->u) { TCGv_i32 newsp =3D tcg_temp_new_i32(); tcg_gen_addi_i32(newsp, cpu_R[13], ofs); - gen_helper_v8m_stackcheck(cpu_env, newsp); + gen_helper_v8m_stackcheck(tcg_env, newsp); } else { - gen_helper_v8m_stackcheck(cpu_env, cpu_R[13]); + gen_helper_v8m_stackcheck(tcg_env, cpu_R[13]); } } =20 @@ -7319,7 +7319,7 @@ static bool op_par_addsub_ge(DisasContext *s, arg_rrr= *a, t1 =3D load_reg(s, a->rm); =20 ge =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(ge, cpu_env, offsetof(CPUARMState, GE)); + tcg_gen_addi_ptr(ge, tcg_env, offsetof(CPUARMState, GE)); gen(t0, t0, t1, ge); =20 store_reg(s, a->rd, t0); @@ -7433,7 +7433,7 @@ static bool op_sat(DisasContext *s, arg_sat *a, tcg_gen_shli_i32(tmp, tmp, shift); } =20 - gen(tmp, cpu_env, tmp, tcg_constant_i32(a->satimm)); + gen(tmp, tcg_env, tmp, tcg_constant_i32(a->satimm)); =20 store_reg(s, a->rd, tmp); return true; @@ -7540,7 +7540,7 @@ static bool trans_SEL(DisasContext *s, arg_rrr *a) t1 =3D load_reg(s, a->rn); t2 =3D load_reg(s, a->rm); t3 =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(t3, cpu_env, offsetof(CPUARMState, GE)); + tcg_gen_ld_i32(t3, tcg_env, offsetof(CPUARMState, GE)); gen_helper_sel_flags(t1, t3, t1, t2); store_reg(s, a->rd, t1); return true; @@ -7618,11 +7618,11 @@ static bool op_smlad(DisasContext *s, arg_rrrr *a, = bool m_swap, bool sub) =20 if (a->ra !=3D 15) { t2 =3D load_reg(s, a->ra); - gen_helper_add_setq(t1, cpu_env, t1, t2); + gen_helper_add_setq(t1, tcg_env, t1, t2); } } else if (a->ra =3D=3D 15) { /* Single saturation-checking addition */ - gen_helper_add_setq(t1, cpu_env, t1, t2); + gen_helper_add_setq(t1, tcg_env, t1, t2); } else { /* * We need to add the products and Ra together and then @@ -7804,9 +7804,9 @@ static bool op_div(DisasContext *s, arg_rrr *a, bool = u) t1 =3D load_reg(s, a->rn); t2 =3D load_reg(s, a->rm); if (u) { - gen_helper_udiv(t1, cpu_env, t1, t2); + gen_helper_udiv(t1, tcg_env, t1, t2); } else { - gen_helper_sdiv(t1, cpu_env, t1, t2); + gen_helper_sdiv(t1, tcg_env, t1, t2); } store_reg(s, a->rd, t1); return true; @@ -7855,7 +7855,7 @@ static TCGv_i32 op_addr_block_pre(DisasContext *s, ar= g_ldst_block *a, int n) * either the original SP (if incrementing) or our * final SP (if decrementing), so that's what we check. */ - gen_helper_v8m_stackcheck(cpu_env, addr); + gen_helper_v8m_stackcheck(tcg_env, addr); } =20 return addr; @@ -7916,7 +7916,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a= , int min_n) =20 if (user && i !=3D 15) { tmp =3D tcg_temp_new_i32(); - gen_helper_get_user_reg(tmp, cpu_env, tcg_constant_i32(i)); + gen_helper_get_user_reg(tmp, tcg_env, tcg_constant_i32(i)); } else { tmp =3D load_reg(s, i); } @@ -7999,7 +7999,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a= , int min_n) tmp =3D tcg_temp_new_i32(); gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); if (user) { - gen_helper_set_user_reg(cpu_env, tcg_constant_i32(i), tmp); + gen_helper_set_user_reg(tcg_env, tcg_constant_i32(i), tmp); } else if (i =3D=3D a->rn) { loaded_var =3D tmp; loaded_base =3D true; @@ -8026,7 +8026,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a= , int min_n) /* Restore CPSR from SPSR. */ tmp =3D load_cpu_field(spsr); translator_io_start(&s->base); - gen_helper_cpsr_write_eret(cpu_env, tmp); + gen_helper_cpsr_write_eret(tcg_env, tmp); /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; } @@ -8100,7 +8100,7 @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a) * Clear APSR (by calling the MSR helper with the same argument * as for "MSR APSR_nzcvqg, Rn": mask =3D 0b1100, SYSM=3D0) */ - gen_helper_v7m_msr(cpu_env, tcg_constant_i32(0xc00), zero); + gen_helper_v7m_msr(tcg_env, tcg_constant_i32(0xc00), zero); } clear_eci_state(s); return true; @@ -8487,7 +8487,7 @@ static bool trans_VCTP(DisasContext *s, arg_VCTP *a) tcg_gen_movcond_i32(TCG_COND_LEU, masklen, masklen, tcg_constant_i32(1 << (4 - a->size)), rn_shifted, tcg_constant_i32(16)); - gen_helper_mve_vctp(cpu_env, masklen); + gen_helper_mve_vctp(tcg_env, masklen); /* This insn updates predication bits */ s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; mve_update_eci(s); @@ -8665,12 +8665,12 @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_= v7m *a) /* FAULTMASK */ if (a->F) { addr =3D tcg_constant_i32(19); - gen_helper_v7m_msr(cpu_env, addr, tmp); + gen_helper_v7m_msr(tcg_env, addr, tmp); } /* PRIMASK */ if (a->I) { addr =3D tcg_constant_i32(16); - gen_helper_v7m_msr(cpu_env, addr, tmp); + gen_helper_v7m_msr(tcg_env, addr, tmp); } gen_rebuild_hflags(s, false); gen_lookup_tb(s); @@ -8740,7 +8740,7 @@ static bool trans_SETEND(DisasContext *s, arg_SETEND = *a) return false; } if (a->E !=3D (s->be_data =3D=3D MO_BE)) { - gen_helper_setend(cpu_env); + gen_helper_setend(tcg_env); s->base.is_jmp =3D DISAS_UPDATE_EXIT; } return true; @@ -9335,7 +9335,7 @@ static void arm_tr_translate_insn(DisasContextBase *d= cbase, CPUState *cpu) * be possible after an indirect branch, at the start of the TB. */ assert(dc->base.num_insns =3D=3D 1); - gen_helper_exception_pc_alignment(cpu_env, tcg_constant_tl(pc)); + gen_helper_exception_pc_alignment(tcg_env, tcg_constant_tl(pc)); dc->base.is_jmp =3D DISAS_NORETURN; dc->base.pc_next =3D QEMU_ALIGN_UP(pc, 4); return; @@ -9615,7 +9615,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) /* nothing more to generate */ break; case DISAS_WFI: - gen_helper_wfi(cpu_env, tcg_constant_i32(curr_insn_len(dc))); + gen_helper_wfi(tcg_env, tcg_constant_i32(curr_insn_len(dc))); /* * The helper doesn't necessarily throw an exception, but we * must go back to the main loop to check for interrupts anywa= y. @@ -9623,10 +9623,10 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cpu) tcg_gen_exit_tb(NULL, 0); break; case DISAS_WFE: - gen_helper_wfe(cpu_env); + gen_helper_wfe(tcg_env); break; case DISAS_YIELD: - gen_helper_yield(cpu_env); + gen_helper_yield(tcg_env); break; case DISAS_SWI: gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb)); diff --git a/target/avr/translate.c b/target/avr/translate.c index ef2edd7415..8d67570d17 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -127,25 +127,25 @@ void avr_cpu_tcg_init(void) int i; =20 #define AVR_REG_OFFS(x) offsetof(CPUAVRState, x) - cpu_pc =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc"); - cpu_Cf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf"); - cpu_Zf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregZ), "Zf"); - cpu_Nf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregN), "Nf"); - cpu_Vf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregV), "Vf"); - cpu_Sf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregS), "Sf"); - cpu_Hf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregH), "Hf"); - cpu_Tf =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregT), "Tf"); - cpu_If =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregI), "If"); - cpu_rampD =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampD), "ra= mpD"); - cpu_rampX =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampX), "ra= mpX"); - cpu_rampY =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampY), "ra= mpY"); - cpu_rampZ =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(rampZ), "ra= mpZ"); - cpu_eind =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(eind), "eind= "); - cpu_sp =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sp), "sp"); - cpu_skip =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(skip), "skip= "); + cpu_pc =3D tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(pc_w), "pc"); + cpu_Cf =3D tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregC), "Cf"); + cpu_Zf =3D tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregZ), "Zf"); + cpu_Nf =3D tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregN), "Nf"); + cpu_Vf =3D tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregV), "Vf"); + cpu_Sf =3D tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregS), "Sf"); + cpu_Hf =3D tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregH), "Hf"); + cpu_Tf =3D tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregT), "Tf"); + cpu_If =3D tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sregI), "If"); + cpu_rampD =3D tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(rampD), "ra= mpD"); + cpu_rampX =3D tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(rampX), "ra= mpX"); + cpu_rampY =3D tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(rampY), "ra= mpY"); + cpu_rampZ =3D tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(rampZ), "ra= mpZ"); + cpu_eind =3D tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(eind), "eind= "); + cpu_sp =3D tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(sp), "sp"); + cpu_skip =3D tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(skip), "skip= "); =20 for (i =3D 0; i < NUMBER_OF_CPU_REGISTERS; i++) { - cpu_r[i] =3D tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(r[i]), + cpu_r[i] =3D tcg_global_mem_new_i32(tcg_env, AVR_REG_OFFS(r[i]), reg_names[i]); } #undef AVR_REG_OFFS @@ -184,7 +184,7 @@ static int append_16(DisasContext *ctx, int x) static bool avr_have_feature(DisasContext *ctx, int feature) { if (!avr_feature(ctx->env, feature)) { - gen_helper_unsupported(cpu_env); + gen_helper_unsupported(tcg_env); ctx->base.is_jmp =3D DISAS_NORETURN; return false; } @@ -1295,7 +1295,7 @@ static bool trans_SBIC(DisasContext *ctx, arg_SBIC *a) TCGv data =3D tcg_temp_new_i32(); TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, cpu_env, port); + gen_helper_inb(data, tcg_env, port); tcg_gen_andi_tl(data, data, 1 << a->bit); ctx->skip_cond =3D TCG_COND_EQ; ctx->skip_var0 =3D data; @@ -1313,7 +1313,7 @@ static bool trans_SBIS(DisasContext *ctx, arg_SBIS *a) TCGv data =3D tcg_temp_new_i32(); TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, cpu_env, port); + gen_helper_inb(data, tcg_env, port); tcg_gen_andi_tl(data, data, 1 << a->bit); ctx->skip_cond =3D TCG_COND_NE; ctx->skip_var0 =3D data; @@ -1494,7 +1494,7 @@ static TCGv gen_get_zaddr(void) static void gen_data_store(DisasContext *ctx, TCGv data, TCGv addr) { if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { - gen_helper_fullwr(cpu_env, data, addr); + gen_helper_fullwr(tcg_env, data, addr); } else { tcg_gen_qemu_st_tl(data, addr, MMU_DATA_IDX, MO_UB); } @@ -1503,7 +1503,7 @@ static void gen_data_store(DisasContext *ctx, TCGv da= ta, TCGv addr) static void gen_data_load(DisasContext *ctx, TCGv data, TCGv addr) { if (ctx->base.tb->flags & TB_FLAGS_FULL_ACCESS) { - gen_helper_fullrd(data, cpu_env, addr); + gen_helper_fullrd(data, tcg_env, addr); } else { tcg_gen_qemu_ld_tl(data, addr, MMU_DATA_IDX, MO_UB); } @@ -2130,7 +2130,7 @@ static bool trans_IN(DisasContext *ctx, arg_IN *a) TCGv Rd =3D cpu_r[a->rd]; TCGv port =3D tcg_constant_i32(a->imm); =20 - gen_helper_inb(Rd, cpu_env, port); + gen_helper_inb(Rd, tcg_env, port); return true; } =20 @@ -2143,7 +2143,7 @@ static bool trans_OUT(DisasContext *ctx, arg_OUT *a) TCGv Rd =3D cpu_r[a->rd]; TCGv port =3D tcg_constant_i32(a->imm); =20 - gen_helper_outb(cpu_env, port, Rd); + gen_helper_outb(tcg_env, port, Rd); return true; } =20 @@ -2411,9 +2411,9 @@ static bool trans_SBI(DisasContext *ctx, arg_SBI *a) TCGv data =3D tcg_temp_new_i32(); TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, cpu_env, port); + gen_helper_inb(data, tcg_env, port); tcg_gen_ori_tl(data, data, 1 << a->bit); - gen_helper_outb(cpu_env, port, data); + gen_helper_outb(tcg_env, port, data); return true; } =20 @@ -2426,9 +2426,9 @@ static bool trans_CBI(DisasContext *ctx, arg_CBI *a) TCGv data =3D tcg_temp_new_i32(); TCGv port =3D tcg_constant_i32(a->reg); =20 - gen_helper_inb(data, cpu_env, port); + gen_helper_inb(data, tcg_env, port); tcg_gen_andi_tl(data, data, ~(1 << a->bit)); - gen_helper_outb(cpu_env, port, data); + gen_helper_outb(tcg_env, port, data); return true; } =20 @@ -2551,7 +2551,7 @@ static bool trans_BREAK(DisasContext *ctx, arg_BREAK = *a) =20 #ifdef BREAKPOINT_ON_BREAK tcg_gen_movi_tl(cpu_pc, ctx->npc - 1); - gen_helper_debug(cpu_env); + gen_helper_debug(tcg_env); ctx->base.is_jmp =3D DISAS_EXIT; #else /* NOP */ @@ -2577,7 +2577,7 @@ static bool trans_NOP(DisasContext *ctx, arg_NOP *a) */ static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP *a) { - gen_helper_sleep(cpu_env); + gen_helper_sleep(tcg_env); ctx->base.is_jmp =3D DISAS_NORETURN; return true; } @@ -2589,7 +2589,7 @@ static bool trans_SLEEP(DisasContext *ctx, arg_SLEEP = *a) */ static bool trans_WDR(DisasContext *ctx, arg_WDR *a) { - gen_helper_wdr(cpu_env); + gen_helper_wdr(tcg_env); =20 return true; } @@ -2608,7 +2608,7 @@ static void translate(DisasContext *ctx) uint32_t opcode =3D next_word(ctx); =20 if (!decode_insn(ctx, opcode)) { - gen_helper_unsupported(cpu_env); + gen_helper_unsupported(tcg_env); ctx->base.is_jmp =3D DISAS_NORETURN; } } diff --git a/target/cris/translate.c b/target/cris/translate.c index 42103b5558..395ba12bea 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -171,9 +171,9 @@ static const int preg_sizes[] =3D { }; =20 #define t_gen_mov_TN_env(tn, member) \ - tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member)) + tcg_gen_ld_tl(tn, tcg_env, offsetof(CPUCRISState, member)) #define t_gen_mov_env_TN(member, tn) \ - tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member)) + tcg_gen_st_tl(tn, tcg_env, offsetof(CPUCRISState, member)) #define t_gen_movi_env_TN(member, c) \ t_gen_mov_env_TN(member, tcg_constant_tl(c)) =20 @@ -197,10 +197,10 @@ static inline void t_gen_mov_preg_TN(DisasContext *dc= , int r, TCGv tn) tcg_gen_andi_tl(cpu_PR[r], tn, 3); } else { if (r =3D=3D PR_PID) { - gen_helper_tlb_flush_pid(cpu_env, tn); + gen_helper_tlb_flush_pid(tcg_env, tn); } if (dc->tb_flags & S_FLAG && r =3D=3D PR_SPC) { - gen_helper_spc_write(cpu_env, tn); + gen_helper_spc_write(tcg_env, tn); } else if (r =3D=3D PR_CCS) { dc->cpustate_changed =3D 1; } @@ -265,7 +265,7 @@ static void cris_lock_irq(DisasContext *dc) =20 static inline void t_gen_raise_exception(uint32_t index) { - gen_helper_raise_exception(cpu_env, tcg_constant_i32(index)); + gen_helper_raise_exception(tcg_env, tcg_constant_i32(index)); } =20 static void t_gen_lsl(TCGv d, TCGv a, TCGv b) @@ -504,17 +504,17 @@ static void cris_evaluate_flags(DisasContext *dc) =20 switch (dc->cc_op) { case CC_OP_MCP: - gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env, + gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], tcg_env, cpu_PR[PR_CCS], cc_src, cc_dest, cc_result); break; case CC_OP_MULS: - gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env, + gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], tcg_env, cpu_PR[PR_CCS], cc_result, cpu_PR[PR_MOF]); break; case CC_OP_MULU: - gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env, + gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], tcg_env, cpu_PR[PR_CCS], cc_result, cpu_PR[PR_MOF]); break; @@ -528,14 +528,14 @@ static void cris_evaluate_flags(DisasContext *dc) switch (dc->cc_size) { case 4: gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS], - cpu_env, cpu_PR[PR_CCS], cc_result); + tcg_env, cpu_PR[PR_CCS], cc_result); break; case 2: gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS], - cpu_env, cpu_PR[PR_CCS], cc_result); + tcg_env, cpu_PR[PR_CCS], cc_result); break; default: - gen_helper_evaluate_flags(cpu_env); + gen_helper_evaluate_flags(tcg_env); break; } break; @@ -545,21 +545,21 @@ static void cris_evaluate_flags(DisasContext *dc) case CC_OP_SUB: case CC_OP_CMP: if (dc->cc_size =3D=3D 4) { - gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env, + gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], tcg_env, cpu_PR[PR_CCS], cc_src, cc_dest, cc_result); } else { - gen_helper_evaluate_flags(cpu_env); + gen_helper_evaluate_flags(tcg_env); } =20 break; default: switch (dc->cc_size) { case 4: - gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env, + gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], tcg_env, cpu_PR[PR_CCS], cc_src, cc_dest, cc_result); break; default: - gen_helper_evaluate_flags(cpu_env); + gen_helper_evaluate_flags(tcg_env); break; } break; @@ -1330,7 +1330,7 @@ static int dec_btstq(CPUCRISState *env, DisasContext = *dc) cris_cc_mask(dc, CC_MASK_NZ); c =3D tcg_constant_tl(dc->op1); cris_evaluate_flags(dc); - gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2], + gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->op2], c, cpu_PR[PR_CCS]); cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); @@ -1744,7 +1744,7 @@ static int dec_btst_r(CPUCRISState *env, DisasContext= *dc) dc->op1, dc->op2); cris_cc_mask(dc, CC_MASK_NZ); cris_evaluate_flags(dc); - gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2], + gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->op2], cpu_R[dc->op1], cpu_PR[PR_CCS]); cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); @@ -1946,7 +1946,7 @@ static int dec_move_rs(CPUCRISState *env, DisasContex= t *dc) c1 =3D tcg_constant_tl(dc->op1); c2 =3D tcg_constant_tl(dc->op2); cris_cc_mask(dc, 0); - gen_helper_movl_sreg_reg(cpu_env, c2, c1); + gen_helper_movl_sreg_reg(tcg_env, c2, c1); return 2; } static int dec_move_sr(CPUCRISState *env, DisasContext *dc) @@ -1956,7 +1956,7 @@ static int dec_move_sr(CPUCRISState *env, DisasContex= t *dc) c1 =3D tcg_constant_tl(dc->op1); c2 =3D tcg_constant_tl(dc->op2); cris_cc_mask(dc, 0); - gen_helper_movl_reg_sreg(cpu_env, c1, c2); + gen_helper_movl_reg_sreg(tcg_env, c1, c2); return 2; } =20 @@ -2693,7 +2693,7 @@ static int dec_rfe_etc(CPUCRISState *env, DisasContex= t *dc) cris_cc_mask(dc, 0); =20 if (dc->op2 =3D=3D 15) { - tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, + tcg_gen_st_i32(tcg_constant_i32(1), tcg_env, -offsetof(CRISCPU, env) + offsetof(CPUState, halted= )); tcg_gen_movi_tl(env_pc, dc->pc + 2); t_gen_raise_exception(EXCP_HLT); @@ -2706,7 +2706,7 @@ static int dec_rfe_etc(CPUCRISState *env, DisasContex= t *dc) /* rfe. */ LOG_DIS("rfe\n"); cris_evaluate_flags(dc); - gen_helper_rfe(cpu_env); + gen_helper_rfe(tcg_env); dc->base.is_jmp =3D DISAS_UPDATE; dc->cpustate_changed =3D true; break; @@ -2714,7 +2714,7 @@ static int dec_rfe_etc(CPUCRISState *env, DisasContex= t *dc) /* rfn. */ LOG_DIS("rfn\n"); cris_evaluate_flags(dc); - gen_helper_rfn(cpu_env); + gen_helper_rfn(tcg_env); dc->base.is_jmp =3D DISAS_UPDATE; dc->cpustate_changed =3D true; break; @@ -3238,41 +3238,41 @@ void cris_initialize_tcg(void) { int i; =20 - cc_x =3D tcg_global_mem_new(cpu_env, + cc_x =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, cc_x), "cc_x"); - cc_src =3D tcg_global_mem_new(cpu_env, + cc_src =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, cc_src), "cc_src"); - cc_dest =3D tcg_global_mem_new(cpu_env, + cc_dest =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, cc_dest), "cc_dest"); - cc_result =3D tcg_global_mem_new(cpu_env, + cc_result =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, cc_result), "cc_result"); - cc_op =3D tcg_global_mem_new(cpu_env, + cc_op =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, cc_op), "cc_op"); - cc_size =3D tcg_global_mem_new(cpu_env, + cc_size =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, cc_size), "cc_size"); - cc_mask =3D tcg_global_mem_new(cpu_env, + cc_mask =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, cc_mask), "cc_mask"); =20 - env_pc =3D tcg_global_mem_new(cpu_env, + env_pc =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, pc), "pc"); - env_btarget =3D tcg_global_mem_new(cpu_env, + env_btarget =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, btarget), "btarget"); - env_btaken =3D tcg_global_mem_new(cpu_env, + env_btaken =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, btaken), "btaken"); for (i =3D 0; i < 16; i++) { - cpu_R[i] =3D tcg_global_mem_new(cpu_env, + cpu_R[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, regs[i]), regnames_v32[i]); } for (i =3D 0; i < 16; i++) { - cpu_PR[i] =3D tcg_global_mem_new(cpu_env, + cpu_PR[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, pregs[i]), pregnames_v32[i]); } diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 217bc7bb5a..dbae6c570a 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -414,50 +414,50 @@ void gen_store32(TCGv vaddr, TCGv src, int width, uin= t32_t slot) tcg_gen_mov_tl(hex_store_val32[slot], src); } =20 -void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot) +void gen_store1(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot) { gen_store32(vaddr, src, 1, slot); } =20 -void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot) +void gen_store1i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot) { TCGv tmp =3D tcg_constant_tl(src); - gen_store1(cpu_env, vaddr, tmp, slot); + gen_store1(tcg_env, vaddr, tmp, slot); } =20 -void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot) +void gen_store2(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot) { gen_store32(vaddr, src, 2, slot); } =20 -void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot) +void gen_store2i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot) { TCGv tmp =3D tcg_constant_tl(src); - gen_store2(cpu_env, vaddr, tmp, slot); + gen_store2(tcg_env, vaddr, tmp, slot); } =20 -void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot) +void gen_store4(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot) { gen_store32(vaddr, src, 4, slot); } =20 -void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot) +void gen_store4i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot) { TCGv tmp =3D tcg_constant_tl(src); - gen_store4(cpu_env, vaddr, tmp, slot); + gen_store4(tcg_env, vaddr, tmp, slot); } =20 -void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot) +void gen_store8(TCGv_env tcg_env, TCGv vaddr, TCGv_i64 src, uint32_t slot) { tcg_gen_mov_tl(hex_store_addr[slot], vaddr); tcg_gen_movi_tl(hex_store_width[slot], 8); tcg_gen_mov_i64(hex_store_val64[slot], src); } =20 -void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot) +void gen_store8i(TCGv_env tcg_env, TCGv vaddr, int64_t src, uint32_t slot) { TCGv_i64 tmp =3D tcg_constant_i64(src); - gen_store8(cpu_env, vaddr, tmp, slot); + gen_store8(tcg_env, vaddr, tmp, slot); } =20 TCGv gen_8bitsof(TCGv result, TCGv value) @@ -783,7 +783,7 @@ static void gen_allocframe(DisasContext *ctx, TCGv r29,= int framesize) TCGv_i64 frame; tcg_gen_addi_tl(r30, r29, -8); frame =3D gen_frame_scramble(); - gen_store8(cpu_env, r30, frame, ctx->insn->slot); + gen_store8(tcg_env, r30, frame, ctx->insn->slot); gen_log_reg_write(ctx, HEX_REG_FP, r30); gen_framecheck(r30, framesize); tcg_gen_subi_tl(r29, r30, framesize); @@ -1239,7 +1239,7 @@ static void gen_vreg_load(DisasContext *ctx, intptr_t= dstoff, TCGv src, for (int i =3D 0; i < sizeof(MMVector) / 8; i++) { tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_TEUQ); tcg_gen_addi_tl(src, src, 8); - tcg_gen_st_i64(tmp, cpu_env, dstoff + i * 8); + tcg_gen_st_i64(tmp, tcg_env, dstoff + i * 8); } } =20 @@ -1251,7 +1251,7 @@ static void gen_vreg_store(DisasContext *ctx, TCGv EA= , intptr_t srcoff, =20 if (is_gather_store_insn(ctx)) { TCGv sl =3D tcg_constant_tl(slot); - gen_helper_gather_store(cpu_env, EA, sl); + gen_helper_gather_store(tcg_env, EA, sl); return; } =20 @@ -1301,7 +1301,7 @@ static void vec_to_qvec(size_t size, intptr_t dstoff,= intptr_t srcoff) TCGv_i64 ones =3D tcg_constant_i64(~0); =20 for (int i =3D 0; i < sizeof(MMVector) / 8; i++) { - tcg_gen_ld_i64(tmp, cpu_env, srcoff + i * 8); + tcg_gen_ld_i64(tmp, tcg_env, srcoff + i * 8); tcg_gen_movi_i64(mask, 0); =20 for (int j =3D 0; j < 8; j +=3D size) { @@ -1310,7 +1310,7 @@ static void vec_to_qvec(size_t size, intptr_t dstoff,= intptr_t srcoff) tcg_gen_deposit_i64(mask, mask, bits, j, size); } =20 - tcg_gen_st8_i64(mask, cpu_env, dstoff + i); + tcg_gen_st8_i64(mask, tcg_env, dstoff + i); } } =20 @@ -1318,7 +1318,7 @@ void probe_noshuf_load(TCGv va, int s, int mi) { TCGv size =3D tcg_constant_tl(s); TCGv mem_idx =3D tcg_constant_tl(mi); - gen_helper_probe_noshuf_load(cpu_env, va, size, mem_idx); + gen_helper_probe_noshuf_load(tcg_env, va, size, mem_idx); } =20 /* diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/i= def-parser/parser-helpers.c index ec43343801..4af020933a 100644 --- a/target/hexagon/idef-parser/parser-helpers.c +++ b/target/hexagon/idef-parser/parser-helpers.c @@ -1773,7 +1773,7 @@ void gen_store(Context *c, YYLTYPE *locp, HexValue *w= idth, HexValue *ea, /* Lookup the effective address EA */ find_variable(c, locp, ea, ea); src_m =3D rvalue_materialize(c, locp, &src_m); - OUT(c, locp, "gen_store", &mem_width, "(cpu_env, ", ea, ", ", &src_m); + OUT(c, locp, "gen_store", &mem_width, "(tcg_env, ", ea, ", ", &src_m); OUT(c, locp, ", insn->slot);\n"); } =20 diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index c00254e4d5..012c3c68ec 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -115,7 +115,7 @@ intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum, =20 static void gen_exception_raw(int excp) { - gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); + gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); } =20 static void gen_exec_counters(DisasContext *ctx) @@ -528,7 +528,7 @@ static void gen_start_packet(DisasContext *ctx) =20 if (HEX_DEBUG) { /* Handy place to set a breakpoint before the packet executes */ - gen_helper_debug_start_packet(cpu_env); + gen_helper_debug_start_packet(tcg_env); } =20 /* Initialize the runtime state for packet semantics */ @@ -701,7 +701,7 @@ static void gen_check_store_width(DisasContext *ctx, in= t slot_num) if (HEX_DEBUG) { TCGv slot =3D tcg_constant_tl(slot_num); TCGv check =3D tcg_constant_tl(ctx->store_width[slot_num]); - gen_helper_debug_check_store_width(cpu_env, slot, check); + gen_helper_debug_check_store_width(tcg_env, slot, check); } } =20 @@ -783,7 +783,7 @@ void process_store(DisasContext *ctx, int slot_num) * avoid branching based on the width at runtime. */ TCGv slot =3D tcg_constant_tl(slot_num); - gen_helper_commit_store(cpu_env, slot); + gen_helper_commit_store(tcg_env, slot); } } } @@ -882,7 +882,7 @@ static void gen_commit_hvx(DisasContext *ctx) } =20 if (pkt_has_hvx_store(ctx->pkt)) { - gen_helper_commit_hvx_stores(cpu_env); + gen_helper_commit_hvx_stores(tcg_env); } } =20 @@ -942,7 +942,7 @@ static void gen_commit_packet(DisasContext *ctx) } else if (has_hvx_store) { if (!has_store_s0 && !has_store_s1) { TCGv mem_idx =3D tcg_constant_tl(ctx->mem_idx); - gen_helper_probe_hvx_stores(cpu_env, mem_idx); + gen_helper_probe_hvx_stores(tcg_env, mem_idx); } else { int mask =3D 0; =20 @@ -971,7 +971,7 @@ static void gen_commit_packet(DisasContext *ctx) } mask =3D FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX, ctx->mem_idx); - gen_helper_probe_pkt_scalar_hvx_stores(cpu_env, + gen_helper_probe_pkt_scalar_hvx_stores(tcg_env, tcg_constant_tl(mask)); } } else if (has_store_s0 && has_store_s1) { @@ -987,7 +987,7 @@ static void gen_commit_packet(DisasContext *ctx) FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED,= 1); } TCGv args_tcgv =3D tcg_constant_tl(args); - gen_helper_probe_pkt_scalar_store_s0(cpu_env, args_tcgv); + gen_helper_probe_pkt_scalar_store_s0(tcg_env, args_tcgv); } =20 process_store_log(ctx); @@ -1005,7 +1005,7 @@ static void gen_commit_packet(DisasContext *ctx) tcg_constant_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa= ); =20 /* Handy place to set a breakpoint at the end of execution */ - gen_helper_debug_commit_end(cpu_env, tcg_constant_tl(ctx->pkt->pc), + gen_helper_debug_commit_end(tcg_env, tcg_constant_tl(ctx->pkt->pc), ctx->pred_written, has_st0, has_st1); } =20 @@ -1179,68 +1179,68 @@ void hexagon_translate_init(void) opcode_init(); =20 for (i =3D 0; i < TOTAL_PER_THREAD_REGS; i++) { - hex_gpr[i] =3D tcg_global_mem_new(cpu_env, + hex_gpr[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, gpr[i]), hexagon_regnames[i]); =20 if (HEX_DEBUG) { snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s", hexagon_regnames[i]); - hex_reg_written[i] =3D tcg_global_mem_new(cpu_env, + hex_reg_written[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, reg_written[i]), reg_written_names[i]); } } - hex_new_value_usr =3D tcg_global_mem_new(cpu_env, + hex_new_value_usr =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, new_value_usr), "new_value_usr"); =20 for (i =3D 0; i < NUM_PREGS; i++) { - hex_pred[i] =3D tcg_global_mem_new(cpu_env, + hex_pred[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, pred[i]), hexagon_prednames[i]); } - hex_slot_cancelled =3D tcg_global_mem_new(cpu_env, + hex_slot_cancelled =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled"); - hex_llsc_addr =3D tcg_global_mem_new(cpu_env, + hex_llsc_addr =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, llsc_addr), "llsc_addr"); - hex_llsc_val =3D tcg_global_mem_new(cpu_env, + hex_llsc_val =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, llsc_val), "llsc_val"); - hex_llsc_val_i64 =3D tcg_global_mem_new_i64(cpu_env, + hex_llsc_val_i64 =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64"); for (i =3D 0; i < STORES_MAX; i++) { snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); - hex_store_addr[i] =3D tcg_global_mem_new(cpu_env, + hex_store_addr[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, mem_log_stores[i].va), store_addr_names[i]); =20 snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i); - hex_store_width[i] =3D tcg_global_mem_new(cpu_env, + hex_store_width[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, mem_log_stores[i].width), store_width_names[i]); =20 snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i); - hex_store_val32[i] =3D tcg_global_mem_new(cpu_env, + hex_store_val32[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, mem_log_stores[i].data32), store_val32_names[i]); =20 snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i); - hex_store_val64[i] =3D tcg_global_mem_new_i64(cpu_env, + hex_store_val64[i] =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUHexagonState, mem_log_stores[i].data64), store_val64_names[i]); } for (int i =3D 0; i < VSTORES_MAX; i++) { snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i); - hex_vstore_addr[i] =3D tcg_global_mem_new(cpu_env, + hex_vstore_addr[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, vstore[i].va), vstore_addr_names[i]); =20 snprintf(vstore_size_names[i], NAME_LEN, "vstore_size_%d", i); - hex_vstore_size[i] =3D tcg_global_mem_new(cpu_env, + hex_vstore_size[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, vstore[i].size), vstore_size_names[i]); =20 snprintf(vstore_pending_names[i], NAME_LEN, "vstore_pending_%d", i= ); - hex_vstore_pending[i] =3D tcg_global_mem_new(cpu_env, + hex_vstore_pending[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, vstore_pending[i]), vstore_pending_names[i]); } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c04dc15228..a1046e4672 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -396,28 +396,28 @@ void hppa_translate_init(void) =20 cpu_gr[0] =3D NULL; for (i =3D 1; i < 32; i++) { - cpu_gr[i] =3D tcg_global_mem_new(cpu_env, + cpu_gr[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUHPPAState, gr[i]), gr_names[i]); } for (i =3D 0; i < 4; i++) { - cpu_sr[i] =3D tcg_global_mem_new_i64(cpu_env, + cpu_sr[i] =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUHPPAState, sr[i]), sr_names[i]); } - cpu_srH =3D tcg_global_mem_new_i64(cpu_env, + cpu_srH =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUHPPAState, sr[4]), sr_names[4]); =20 for (i =3D 0; i < ARRAY_SIZE(vars); ++i) { const GlobalVar *v =3D &vars[i]; - *v->var =3D tcg_global_mem_new(cpu_env, v->ofs, v->name); + *v->var =3D tcg_global_mem_new(tcg_env, v->ofs, v->name); } =20 - cpu_iasq_f =3D tcg_global_mem_new_i64(cpu_env, + cpu_iasq_f =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUHPPAState, iasq_f), "iasq_f"); - cpu_iasq_b =3D tcg_global_mem_new_i64(cpu_env, + cpu_iasq_b =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUHPPAState, iasq_b), "iasq_b"); } @@ -563,7 +563,7 @@ static void save_gpr(DisasContext *ctx, unsigned reg, T= CGv_reg t) static TCGv_i32 load_frw_i32(unsigned rt) { TCGv_i32 ret =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(ret, cpu_env, + tcg_gen_ld_i32(ret, tcg_env, offsetof(CPUHPPAState, fr[rt & 31]) + (rt & 32 ? LO_OFS : HI_OFS)); return ret; @@ -586,7 +586,7 @@ static TCGv_i64 load_frw0_i64(unsigned rt) if (rt =3D=3D 0) { tcg_gen_movi_i64(ret, 0); } else { - tcg_gen_ld32u_i64(ret, cpu_env, + tcg_gen_ld32u_i64(ret, tcg_env, offsetof(CPUHPPAState, fr[rt & 31]) + (rt & 32 ? LO_OFS : HI_OFS)); } @@ -595,7 +595,7 @@ static TCGv_i64 load_frw0_i64(unsigned rt) =20 static void save_frw_i32(unsigned rt, TCGv_i32 val) { - tcg_gen_st_i32(val, cpu_env, + tcg_gen_st_i32(val, tcg_env, offsetof(CPUHPPAState, fr[rt & 31]) + (rt & 32 ? LO_OFS : HI_OFS)); } @@ -606,7 +606,7 @@ static void save_frw_i32(unsigned rt, TCGv_i32 val) static TCGv_i64 load_frd(unsigned rt) { TCGv_i64 ret =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(ret, cpu_env, offsetof(CPUHPPAState, fr[rt])); + tcg_gen_ld_i64(ret, tcg_env, offsetof(CPUHPPAState, fr[rt])); return ret; } =20 @@ -623,7 +623,7 @@ static TCGv_i64 load_frd0(unsigned rt) =20 static void save_frd(unsigned rt, TCGv_i64 val) { - tcg_gen_st_i64(val, cpu_env, offsetof(CPUHPPAState, fr[rt])); + tcg_gen_st_i64(val, tcg_env, offsetof(CPUHPPAState, fr[rt])); } =20 static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg) @@ -636,7 +636,7 @@ static void load_spr(DisasContext *ctx, TCGv_i64 dest, = unsigned reg) } else if (ctx->tb_flags & TB_FLAG_SR_SAME) { tcg_gen_mov_i64(dest, cpu_srH); } else { - tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUHPPAState, sr[reg])); + tcg_gen_ld_i64(dest, tcg_env, offsetof(CPUHPPAState, sr[reg])); } #endif } @@ -752,7 +752,7 @@ static inline target_ureg iaoq_dest(DisasContext *ctx, = target_sreg disp) =20 static void gen_excp_1(int exception) { - gen_helper_excp(cpu_env, tcg_constant_i32(exception)); + gen_helper_excp(tcg_env, tcg_constant_i32(exception)); } =20 static void gen_excp(DisasContext *ctx, int exception) @@ -768,7 +768,7 @@ static bool gen_excp_iir(DisasContext *ctx, int exc) { nullify_over(ctx); tcg_gen_st_reg(tcg_constant_reg(ctx->insn), - cpu_env, offsetof(CPUHPPAState, cr[CR_IIR])); + tcg_env, offsetof(CPUHPPAState, cr[CR_IIR])); gen_excp(ctx, exc); return nullify_end(ctx); } @@ -1138,7 +1138,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, sv =3D do_add_sv(ctx, dest, in1, in2); if (is_tsv) { /* ??? Need to include overflow from shift. */ - gen_helper_tsv(cpu_env, sv); + gen_helper_tsv(tcg_env, sv); } } =20 @@ -1147,7 +1147,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, if (is_tc) { tmp =3D tcg_temp_new(); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); - gen_helper_tcond(cpu_env, tmp); + gen_helper_tcond(tcg_env, tmp); } =20 /* Write back the result. */ @@ -1224,7 +1224,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, if (is_tsv || cond_need_sv(c)) { sv =3D do_sub_sv(ctx, dest, in1, in2); if (is_tsv) { - gen_helper_tsv(cpu_env, sv); + gen_helper_tsv(tcg_env, sv); } } =20 @@ -1239,7 +1239,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, if (is_tc) { tmp =3D tcg_temp_new(); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); - gen_helper_tcond(cpu_env, tmp); + gen_helper_tcond(tcg_env, tmp); } =20 /* Write back the result. */ @@ -1358,7 +1358,7 @@ static void do_unit(DisasContext *ctx, unsigned rt, T= CGv_reg in1, if (is_tc) { TCGv_reg tmp =3D tcg_temp_new(); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); - gen_helper_tcond(cpu_env, tmp); + gen_helper_tcond(tcg_env, tmp); } save_gpr(ctx, rt, dest); =20 @@ -1398,7 +1398,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int s= p, TCGv_reg base) tcg_gen_andi_reg(tmp, tmp, 030); tcg_gen_trunc_reg_ptr(ptr, tmp); =20 - tcg_gen_add_ptr(ptr, ptr, cpu_env); + tcg_gen_add_ptr(ptr, ptr, tcg_env); tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4])); =20 return spc; @@ -1559,7 +1559,7 @@ static bool do_floadw(DisasContext *ctx, unsigned rt,= unsigned rb, save_frw_i32(rt, tmp); =20 if (rt =3D=3D 0) { - gen_helper_loaded_fr0(cpu_env); + gen_helper_loaded_fr0(tcg_env); } =20 return nullify_end(ctx); @@ -1584,7 +1584,7 @@ static bool do_floadd(DisasContext *ctx, unsigned rt,= unsigned rb, save_frd(rt, tmp); =20 if (rt =3D=3D 0) { - gen_helper_loaded_fr0(cpu_env); + gen_helper_loaded_fr0(tcg_env); } =20 return nullify_end(ctx); @@ -1653,7 +1653,7 @@ static bool do_fop_wew(DisasContext *ctx, unsigned rt= , unsigned ra, nullify_over(ctx); tmp =3D load_frw0_i32(ra); =20 - func(tmp, cpu_env, tmp); + func(tmp, tcg_env, tmp); =20 save_frw_i32(rt, tmp); return nullify_end(ctx); @@ -1669,7 +1669,7 @@ static bool do_fop_wed(DisasContext *ctx, unsigned rt= , unsigned ra, src =3D load_frd(ra); dst =3D tcg_temp_new_i32(); =20 - func(dst, cpu_env, src); + func(dst, tcg_env, src); =20 save_frw_i32(rt, dst); return nullify_end(ctx); @@ -1683,7 +1683,7 @@ static bool do_fop_ded(DisasContext *ctx, unsigned rt= , unsigned ra, nullify_over(ctx); tmp =3D load_frd0(ra); =20 - func(tmp, cpu_env, tmp); + func(tmp, tcg_env, tmp); =20 save_frd(rt, tmp); return nullify_end(ctx); @@ -1699,7 +1699,7 @@ static bool do_fop_dew(DisasContext *ctx, unsigned rt= , unsigned ra, src =3D load_frw0_i32(ra); dst =3D tcg_temp_new_i64(); =20 - func(dst, cpu_env, src); + func(dst, tcg_env, src); =20 save_frd(rt, dst); return nullify_end(ctx); @@ -1715,7 +1715,7 @@ static bool do_fop_weww(DisasContext *ctx, unsigned r= t, a =3D load_frw0_i32(ra); b =3D load_frw0_i32(rb); =20 - func(a, cpu_env, a, b); + func(a, tcg_env, a, b); =20 save_frw_i32(rt, a); return nullify_end(ctx); @@ -1731,7 +1731,7 @@ static bool do_fop_dedd(DisasContext *ctx, unsigned r= t, a =3D load_frd0(ra); b =3D load_frd0(rb); =20 - func(a, cpu_env, a, b); + func(a, tcg_env, a, b); =20 save_frd(rt, a); return nullify_end(ctx); @@ -1996,7 +1996,7 @@ static void do_page_zero(DisasContext *ctx) break; =20 case 0xe0: /* SET_THREAD_POINTER */ - tcg_gen_st_reg(cpu_gr[26], cpu_env, offsetof(CPUHPPAState, cr[27])= ); + tcg_gen_st_reg(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])= ); tcg_gen_ori_reg(cpu_iaoq_f, cpu_gr[31], 3); tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); ctx->base.is_jmp =3D DISAS_IAQ_N_UPDATED; @@ -2105,7 +2105,7 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl = *a) } =20 tmp =3D get_temp(ctx); - tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl])); + tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); save_gpr(ctx, rt, tmp); =20 done: @@ -2129,7 +2129,7 @@ static bool trans_mtsp(DisasContext *ctx, arg_mtsp *a) tcg_gen_shli_i64(t64, t64, 32); =20 if (rs >=3D 4) { - tcg_gen_st_i64(t64, cpu_env, offsetof(CPUHPPAState, sr[rs])); + tcg_gen_st_i64(t64, tcg_env, offsetof(CPUHPPAState, sr[rs])); ctx->tb_flags &=3D ~TB_FLAG_SR_SAME; } else { tcg_gen_mov_i64(cpu_sr[rs], t64); @@ -2163,13 +2163,13 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtct= l *a) =20 switch (ctl) { case CR_IT: - gen_helper_write_interval_timer(cpu_env, reg); + gen_helper_write_interval_timer(tcg_env, reg); break; case CR_EIRR: - gen_helper_write_eirr(cpu_env, reg); + gen_helper_write_eirr(tcg_env, reg); break; case CR_EIEM: - gen_helper_write_eiem(cpu_env, reg); + gen_helper_write_eiem(tcg_env, reg); ctx->base.is_jmp =3D DISAS_IAQ_N_STALE_EXIT; break; =20 @@ -2178,10 +2178,10 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtct= l *a) /* FIXME: Respect PSW_Q bit */ /* The write advances the queue and stores to the back element. */ tmp =3D get_temp(ctx); - tcg_gen_ld_reg(tmp, cpu_env, + tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); - tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[ctl])); - tcg_gen_st_reg(reg, cpu_env, + tcg_gen_st_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); + tcg_gen_st_reg(reg, tcg_env, offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); break; =20 @@ -2189,14 +2189,14 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtct= l *a) case CR_PID2: case CR_PID3: case CR_PID4: - tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl])); + tcg_gen_st_reg(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl])); #ifndef CONFIG_USER_ONLY - gen_helper_change_prot_id(cpu_env); + gen_helper_change_prot_id(tcg_env); #endif break; =20 default: - tcg_gen_st_reg(reg, cpu_env, offsetof(CPUHPPAState, cr[ctl])); + tcg_gen_st_reg(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl])); break; } return nullify_end(ctx); @@ -2244,9 +2244,9 @@ static bool trans_rsm(DisasContext *ctx, arg_rsm *a) nullify_over(ctx); =20 tmp =3D get_temp(ctx); - tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); + tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw)); tcg_gen_andi_reg(tmp, tmp, ~a->i); - gen_helper_swap_system_mask(tmp, cpu_env, tmp); + gen_helper_swap_system_mask(tmp, tcg_env, tmp); save_gpr(ctx, a->t, tmp); =20 /* Exit the TB to recognize new interrupts, e.g. PSW_M. */ @@ -2264,9 +2264,9 @@ static bool trans_ssm(DisasContext *ctx, arg_ssm *a) nullify_over(ctx); =20 tmp =3D get_temp(ctx); - tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); + tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw)); tcg_gen_ori_reg(tmp, tmp, a->i); - gen_helper_swap_system_mask(tmp, cpu_env, tmp); + gen_helper_swap_system_mask(tmp, tcg_env, tmp); save_gpr(ctx, a->t, tmp); =20 /* Exit the TB to recognize new interrupts, e.g. PSW_I. */ @@ -2284,7 +2284,7 @@ static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a) =20 reg =3D load_gpr(ctx, a->r); tmp =3D get_temp(ctx); - gen_helper_swap_system_mask(tmp, cpu_env, reg); + gen_helper_swap_system_mask(tmp, tcg_env, reg); =20 /* Exit the TB to recognize new interrupts. */ ctx->base.is_jmp =3D DISAS_IAQ_N_STALE_EXIT; @@ -2299,9 +2299,9 @@ static bool do_rfi(DisasContext *ctx, bool rfi_r) nullify_over(ctx); =20 if (rfi_r) { - gen_helper_rfi_r(cpu_env); + gen_helper_rfi_r(tcg_env); } else { - gen_helper_rfi(cpu_env); + gen_helper_rfi(tcg_env); } /* Exit the TB to recognize new interrupts. */ tcg_gen_exit_tb(NULL, 0); @@ -2326,7 +2326,7 @@ static bool trans_halt(DisasContext *ctx, arg_halt *a) CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY nullify_over(ctx); - gen_helper_halt(cpu_env); + gen_helper_halt(tcg_env); ctx->base.is_jmp =3D DISAS_NORETURN; return nullify_end(ctx); #endif @@ -2337,7 +2337,7 @@ static bool trans_reset(DisasContext *ctx, arg_reset = *a) CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY nullify_over(ctx); - gen_helper_reset(cpu_env); + gen_helper_reset(tcg_env); ctx->base.is_jmp =3D DISAS_NORETURN; return nullify_end(ctx); #endif @@ -2348,7 +2348,7 @@ static bool trans_getshadowregs(DisasContext *ctx, ar= g_getshadowregs *a) CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY nullify_over(ctx); - gen_helper_getshadowregs(cpu_env); + gen_helper_getshadowregs(tcg_env); return nullify_end(ctx); #endif } @@ -2388,7 +2388,7 @@ static bool trans_probe(DisasContext *ctx, arg_probe = *a) } want =3D tcg_constant_i32(a->write ? PAGE_WRITE : PAGE_READ); =20 - gen_helper_probe(dest, cpu_env, addr, level, want); + gen_helper_probe(dest, tcg_env, addr, level, want); =20 save_gpr(ctx, a->t, dest); return nullify_end(ctx); @@ -2406,9 +2406,9 @@ static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlb= x *a) form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); reg =3D load_gpr(ctx, a->r); if (a->addr) { - gen_helper_itlba(cpu_env, addr, reg); + gen_helper_itlba(tcg_env, addr, reg); } else { - gen_helper_itlbp(cpu_env, addr, reg); + gen_helper_itlbp(tcg_env, addr, reg); } =20 /* Exit TB for TLB change if mmu is enabled. */ @@ -2433,9 +2433,9 @@ static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlb= x *a) save_gpr(ctx, a->b, ofs); } if (a->local) { - gen_helper_ptlbe(cpu_env); + gen_helper_ptlbe(tcg_env); } else { - gen_helper_ptlb(cpu_env, addr); + gen_helper_ptlb(tcg_env, addr); } =20 /* Exit TB for TLB change if mmu is enabled. */ @@ -2473,10 +2473,10 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ix= tlbxf *a) stl =3D tcg_temp_new_tl(); addr =3D tcg_temp_new_tl(); =20 - tcg_gen_ld32u_i64(stl, cpu_env, + tcg_gen_ld32u_i64(stl, tcg_env, a->data ? offsetof(CPUHPPAState, cr[CR_ISR]) : offsetof(CPUHPPAState, cr[CR_IIASQ])); - tcg_gen_ld32u_i64(atl, cpu_env, + tcg_gen_ld32u_i64(atl, tcg_env, a->data ? offsetof(CPUHPPAState, cr[CR_IOR]) : offsetof(CPUHPPAState, cr[CR_IIAOQ])); tcg_gen_shli_i64(stl, stl, 32); @@ -2484,9 +2484,9 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtl= bxf *a) =20 reg =3D load_gpr(ctx, a->r); if (a->addr) { - gen_helper_itlba(cpu_env, addr, reg); + gen_helper_itlba(tcg_env, addr, reg); } else { - gen_helper_itlbp(cpu_env, addr, reg); + gen_helper_itlbp(tcg_env, addr, reg); } =20 /* Exit TB for TLB change if mmu is enabled. */ @@ -2509,7 +2509,7 @@ static bool trans_lpa(DisasContext *ctx, arg_ldst *a) form_gva(ctx, &vaddr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); =20 paddr =3D tcg_temp_new(); - gen_helper_lpa(paddr, cpu_env, vaddr); + gen_helper_lpa(paddr, tcg_env, vaddr); =20 /* Note that physical address result overrides base modification. */ if (a->m) { @@ -2640,7 +2640,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf *a) nullify_set(ctx, 0); =20 /* Tell the qemu main loop to halt until this cpu has work. */ - tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, + tcg_gen_st_i32(tcg_constant_i32(1), tcg_env, offsetof(CPUState, halted) - offsetof(HPPACPU, = env)); gen_excp_1(EXCP_HALTED); ctx->base.is_jmp =3D DISAS_NORETURN; @@ -2907,15 +2907,15 @@ static bool trans_stby(DisasContext *ctx, arg_stby = *a) val =3D load_gpr(ctx, a->r); if (a->a) { if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - gen_helper_stby_e_parallel(cpu_env, addr, val); + gen_helper_stby_e_parallel(tcg_env, addr, val); } else { - gen_helper_stby_e(cpu_env, addr, val); + gen_helper_stby_e(tcg_env, addr, val); } } else { if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - gen_helper_stby_b_parallel(cpu_env, addr, val); + gen_helper_stby_b_parallel(tcg_env, addr, val); } else { - gen_helper_stby_b(cpu_env, addr, val); + gen_helper_stby_b(tcg_env, addr, val); } } if (a->m) { @@ -3806,7 +3806,7 @@ static bool trans_fcmp_f(DisasContext *ctx, arg_fclas= s2 *a) ty =3D tcg_constant_i32(a->y); tc =3D tcg_constant_i32(a->c); =20 - gen_helper_fcmp_s(cpu_env, ta, tb, ty, tc); + gen_helper_fcmp_s(tcg_env, ta, tb, ty, tc); =20 return nullify_end(ctx); } @@ -3823,7 +3823,7 @@ static bool trans_fcmp_d(DisasContext *ctx, arg_fclas= s2 *a) ty =3D tcg_constant_i32(a->y); tc =3D tcg_constant_i32(a->c); =20 - gen_helper_fcmp_d(cpu_env, ta, tb, ty, tc); + gen_helper_fcmp_d(tcg_env, ta, tb, ty, tc); =20 return nullify_end(ctx); } @@ -3835,7 +3835,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest = *a) nullify_over(ctx); =20 t =3D get_temp(ctx); - tcg_gen_ld32u_reg(t, cpu_env, offsetof(CPUHPPAState, fr0_shadow)); + tcg_gen_ld32u_reg(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow)); =20 if (a->y =3D=3D 1) { int mask; @@ -4012,9 +4012,9 @@ static bool trans_fmpyfadd_f(DisasContext *ctx, arg_f= mpyfadd_f *a) z =3D load_frw0_i32(a->ra3); =20 if (a->neg) { - gen_helper_fmpynfadd_s(x, cpu_env, x, y, z); + gen_helper_fmpynfadd_s(x, tcg_env, x, y, z); } else { - gen_helper_fmpyfadd_s(x, cpu_env, x, y, z); + gen_helper_fmpyfadd_s(x, tcg_env, x, y, z); } =20 save_frw_i32(a->t, x); @@ -4031,9 +4031,9 @@ static bool trans_fmpyfadd_d(DisasContext *ctx, arg_f= mpyfadd_d *a) z =3D load_frd0(a->ra3); =20 if (a->neg) { - gen_helper_fmpynfadd_d(x, cpu_env, x, y, z); + gen_helper_fmpynfadd_d(x, tcg_env, x, y, z); } else { - gen_helper_fmpyfadd_d(x, cpu_env, x, y, z); + gen_helper_fmpyfadd_d(x, tcg_env, x, y, z); } =20 save_frd(a->t, x); diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index e0a622941c..a8a4687227 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -695,7 +695,7 @@ static inline void gen_string_movl_A0_EDI(DisasContext = *s) =20 static inline void gen_op_movl_T0_Dshift(DisasContext *s, MemOp ot) { - tcg_gen_ld32s_tl(s->T0, cpu_env, offsetof(CPUX86State, df)); + tcg_gen_ld32s_tl(s->T0, tcg_env, offsetof(CPUX86State, df)); tcg_gen_shli_tl(s->T0, s->T0, ot); }; =20 @@ -761,13 +761,13 @@ static void gen_helper_in_func(MemOp ot, TCGv v, TCGv= _i32 n) { switch (ot) { case MO_8: - gen_helper_inb(v, cpu_env, n); + gen_helper_inb(v, tcg_env, n); break; case MO_16: - gen_helper_inw(v, cpu_env, n); + gen_helper_inw(v, tcg_env, n); break; case MO_32: - gen_helper_inl(v, cpu_env, n); + gen_helper_inl(v, tcg_env, n); break; default: g_assert_not_reached(); @@ -778,13 +778,13 @@ static void gen_helper_out_func(MemOp ot, TCGv_i32 v,= TCGv_i32 n) { switch (ot) { case MO_8: - gen_helper_outb(cpu_env, v, n); + gen_helper_outb(tcg_env, v, n); break; case MO_16: - gen_helper_outw(cpu_env, v, n); + gen_helper_outw(tcg_env, v, n); break; case MO_32: - gen_helper_outl(cpu_env, v, n); + gen_helper_outl(tcg_env, v, n); break; default: g_assert_not_reached(); @@ -807,7 +807,7 @@ static bool gen_check_io(DisasContext *s, MemOp ot, TCG= v_i32 port, return false; #else if (PE(s) && (CPL(s) > IOPL(s) || VM86(s))) { - gen_helper_check_io(cpu_env, port, tcg_constant_i32(1 << ot)); + gen_helper_check_io(tcg_env, port, tcg_constant_i32(1 << ot)); } if (GUEST(s)) { gen_update_cc_op(s); @@ -816,7 +816,7 @@ static bool gen_check_io(DisasContext *s, MemOp ot, TCG= v_i32 port, svm_flags |=3D SVM_IOIO_REP_MASK; } svm_flags |=3D 1 << (SVM_IOIO_SIZE_SHIFT + ot); - gen_helper_svm_check_io(cpu_env, port, + gen_helper_svm_check_io(tcg_env, port, tcg_constant_i32(svm_flags), cur_insn_len_i32(s)); } @@ -1298,7 +1298,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_po= rt, int ot) #else TCGv_i32 t_size =3D tcg_constant_i32(1 << ot); TCGv t_next =3D eip_next_tl(s); - gen_helper_bpt_io(cpu_env, t_port, t_size, t_next); + gen_helper_bpt_io(tcg_env, t_port, t_size, t_next); #endif /* CONFIG_USER_ONLY */ } } @@ -1388,28 +1388,28 @@ static void gen_helper_fp_arith_ST0_FT0(int op) { switch (op) { case 0: - gen_helper_fadd_ST0_FT0(cpu_env); + gen_helper_fadd_ST0_FT0(tcg_env); break; case 1: - gen_helper_fmul_ST0_FT0(cpu_env); + gen_helper_fmul_ST0_FT0(tcg_env); break; case 2: - gen_helper_fcom_ST0_FT0(cpu_env); + gen_helper_fcom_ST0_FT0(tcg_env); break; case 3: - gen_helper_fcom_ST0_FT0(cpu_env); + gen_helper_fcom_ST0_FT0(tcg_env); break; case 4: - gen_helper_fsub_ST0_FT0(cpu_env); + gen_helper_fsub_ST0_FT0(tcg_env); break; case 5: - gen_helper_fsubr_ST0_FT0(cpu_env); + gen_helper_fsubr_ST0_FT0(tcg_env); break; case 6: - gen_helper_fdiv_ST0_FT0(cpu_env); + gen_helper_fdiv_ST0_FT0(tcg_env); break; case 7: - gen_helper_fdivr_ST0_FT0(cpu_env); + gen_helper_fdivr_ST0_FT0(tcg_env); break; } } @@ -1420,22 +1420,22 @@ static void gen_helper_fp_arith_STN_ST0(int op, int= opreg) TCGv_i32 tmp =3D tcg_constant_i32(opreg); switch (op) { case 0: - gen_helper_fadd_STN_ST0(cpu_env, tmp); + gen_helper_fadd_STN_ST0(tcg_env, tmp); break; case 1: - gen_helper_fmul_STN_ST0(cpu_env, tmp); + gen_helper_fmul_STN_ST0(tcg_env, tmp); break; case 4: - gen_helper_fsubr_STN_ST0(cpu_env, tmp); + gen_helper_fsubr_STN_ST0(tcg_env, tmp); break; case 5: - gen_helper_fsub_STN_ST0(cpu_env, tmp); + gen_helper_fsub_STN_ST0(tcg_env, tmp); break; case 6: - gen_helper_fdivr_STN_ST0(cpu_env, tmp); + gen_helper_fdivr_STN_ST0(tcg_env, tmp); break; case 7: - gen_helper_fdiv_STN_ST0(cpu_env, tmp); + gen_helper_fdiv_STN_ST0(tcg_env, tmp); break; } } @@ -1444,7 +1444,7 @@ static void gen_exception(DisasContext *s, int trapno) { gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_raise_exception(cpu_env, tcg_constant_i32(trapno)); + gen_helper_raise_exception(tcg_env, tcg_constant_i32(trapno)); s->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -1923,17 +1923,17 @@ static void gen_rotc_rm_T1(DisasContext *s, MemOp o= t, int op1, if (is_right) { switch (ot) { case MO_8: - gen_helper_rcrb(s->T0, cpu_env, s->T0, s->T1); + gen_helper_rcrb(s->T0, tcg_env, s->T0, s->T1); break; case MO_16: - gen_helper_rcrw(s->T0, cpu_env, s->T0, s->T1); + gen_helper_rcrw(s->T0, tcg_env, s->T0, s->T1); break; case MO_32: - gen_helper_rcrl(s->T0, cpu_env, s->T0, s->T1); + gen_helper_rcrl(s->T0, tcg_env, s->T0, s->T1); break; #ifdef TARGET_X86_64 case MO_64: - gen_helper_rcrq(s->T0, cpu_env, s->T0, s->T1); + gen_helper_rcrq(s->T0, tcg_env, s->T0, s->T1); break; #endif default: @@ -1942,17 +1942,17 @@ static void gen_rotc_rm_T1(DisasContext *s, MemOp o= t, int op1, } else { switch (ot) { case MO_8: - gen_helper_rclb(s->T0, cpu_env, s->T0, s->T1); + gen_helper_rclb(s->T0, tcg_env, s->T0, s->T1); break; case MO_16: - gen_helper_rclw(s->T0, cpu_env, s->T0, s->T1); + gen_helper_rclw(s->T0, tcg_env, s->T0, s->T1); break; case MO_32: - gen_helper_rcll(s->T0, cpu_env, s->T0, s->T1); + gen_helper_rcll(s->T0, tcg_env, s->T0, s->T1); break; #ifdef TARGET_X86_64 case MO_64: - gen_helper_rclq(s->T0, cpu_env, s->T0, s->T1); + gen_helper_rclq(s->T0, tcg_env, s->T0, s->T1); break; #endif default: @@ -2354,7 +2354,7 @@ static void gen_bndck(CPUX86State *env, DisasContext = *s, int modrm, } tcg_gen_setcond_i64(cond, s->tmp1_i64, s->tmp1_i64, bndv); tcg_gen_extrl_i64_i32(s->tmp2_i32, s->tmp1_i64); - gen_helper_bndck(cpu_env, s->tmp2_i32); + gen_helper_bndck(tcg_env, s->tmp2_i32); } =20 /* used for LEA and MOV AX, mem */ @@ -2512,14 +2512,14 @@ static void gen_cmovcc1(CPUX86State *env, DisasCont= ext *s, MemOp ot, int b, =20 static inline void gen_op_movl_T0_seg(DisasContext *s, X86Seg seg_reg) { - tcg_gen_ld32u_tl(s->T0, cpu_env, + tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State,segs[seg_reg].selector)); } =20 static inline void gen_op_movl_seg_T0_vm(DisasContext *s, X86Seg seg_reg) { tcg_gen_ext16u_tl(s->T0, s->T0); - tcg_gen_st32_tl(s->T0, cpu_env, + tcg_gen_st32_tl(s->T0, tcg_env, offsetof(CPUX86State,segs[seg_reg].selector)); tcg_gen_shli_tl(cpu_seg_base[seg_reg], s->T0, 4); } @@ -2530,7 +2530,7 @@ static void gen_movl_seg_T0(DisasContext *s, X86Seg s= eg_reg) { if (PE(s) && !VM86(s)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); - gen_helper_load_seg(cpu_env, tcg_constant_i32(seg_reg), s->tmp2_i3= 2); + gen_helper_load_seg(tcg_env, tcg_constant_i32(seg_reg), s->tmp2_i3= 2); /* abort translation because the addseg value may change or because ss32 may change. For R_SS, translation must always stop as a special handling must be done to disable hardware @@ -2554,7 +2554,7 @@ static void gen_svm_check_intercept(DisasContext *s, = uint32_t type) if (likely(!GUEST(s))) { return; } - gen_helper_svm_check_intercept(cpu_env, tcg_constant_i32(type)); + gen_helper_svm_check_intercept(tcg_env, tcg_constant_i32(type)); } =20 static inline void gen_stack_update(DisasContext *s, int addend) @@ -2724,7 +2724,7 @@ static void gen_interrupt(DisasContext *s, int intno) { gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_raise_interrupt(cpu_env, tcg_constant_i32(intno), + gen_helper_raise_interrupt(tcg_env, tcg_constant_i32(intno), cur_insn_len_i32(s)); s->base.is_jmp =3D DISAS_NORETURN; } @@ -2733,9 +2733,9 @@ static void gen_set_hflag(DisasContext *s, uint32_t m= ask) { if ((s->flags & mask) =3D=3D 0) { TCGv_i32 t =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags)); + tcg_gen_ld_i32(t, tcg_env, offsetof(CPUX86State, hflags)); tcg_gen_ori_i32(t, t, mask); - tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags)); + tcg_gen_st_i32(t, tcg_env, offsetof(CPUX86State, hflags)); s->flags |=3D mask; } } @@ -2744,9 +2744,9 @@ static void gen_reset_hflag(DisasContext *s, uint32_t= mask) { if (s->flags & mask) { TCGv_i32 t =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags)); + tcg_gen_ld_i32(t, tcg_env, offsetof(CPUX86State, hflags)); tcg_gen_andi_i32(t, t, ~mask); - tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags)); + tcg_gen_st_i32(t, tcg_env, offsetof(CPUX86State, hflags)); s->flags &=3D ~mask; } } @@ -2755,18 +2755,18 @@ static void gen_set_eflags(DisasContext *s, target_= ulong mask) { TCGv t =3D tcg_temp_new(); =20 - tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, eflags)); + tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, eflags)); tcg_gen_ori_tl(t, t, mask); - tcg_gen_st_tl(t, cpu_env, offsetof(CPUX86State, eflags)); + tcg_gen_st_tl(t, tcg_env, offsetof(CPUX86State, eflags)); } =20 static void gen_reset_eflags(DisasContext *s, target_ulong mask) { TCGv t =3D tcg_temp_new(); =20 - tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, eflags)); + tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, eflags)); tcg_gen_andi_tl(t, t, ~mask); - tcg_gen_st_tl(t, cpu_env, offsetof(CPUX86State, eflags)); + tcg_gen_st_tl(t, tcg_env, offsetof(CPUX86State, eflags)); } =20 /* Clear BND registers during legacy branches. */ @@ -2778,7 +2778,7 @@ static void gen_bnd_jmp(DisasContext *s) if ((s->prefix & PREFIX_REPNZ) =3D=3D 0 && (s->flags & HF_MPX_EN_MASK) !=3D 0 && (s->flags & HF_MPX_IU_MASK) !=3D 0) { - gen_helper_bnd_jmp(cpu_env); + gen_helper_bnd_jmp(tcg_env); } } =20 @@ -2802,10 +2802,10 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bo= ol recheck_tf, bool jr) gen_reset_eflags(s, RF_MASK); } if (recheck_tf) { - gen_helper_rechecking_single_step(cpu_env); + gen_helper_rechecking_single_step(tcg_env); tcg_gen_exit_tb(NULL, 0); } else if (s->flags & HF_TF_MASK) { - gen_helper_single_step(cpu_env); + gen_helper_single_step(tcg_env); } else if (jr) { tcg_gen_lookup_and_goto_ptr(); } else { @@ -2907,12 +2907,12 @@ static void gen_jmp_rel_csize(DisasContext *s, int = diff, int tb_num) static inline void gen_ldq_env_A0(DisasContext *s, int offset) { tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); - tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset); + tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset); } =20 static inline void gen_stq_env_A0(DisasContext *s, int offset) { - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset); + tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset); tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); } =20 @@ -2921,20 +2921,20 @@ static inline void gen_ldo_env_A0(DisasContext *s, = int offset, bool align) int mem_index =3D s->mem_index; tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, mem_index, MO_LEUQ | (align ? MO_ALIGN_16 : 0)); - tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0= ))); + tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(XMMReg, XMM_Q(0= ))); tcg_gen_addi_tl(s->tmp0, s->A0, 8); tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ); - tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1= ))); + tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(XMMReg, XMM_Q(1= ))); } =20 static inline void gen_sto_env_A0(DisasContext *s, int offset, bool align) { int mem_index =3D s->mem_index; - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0= ))); + tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(XMMReg, XMM_Q(0= ))); tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, mem_index, MO_LEUQ | (align ? MO_ALIGN_16 : 0)); tcg_gen_addi_tl(s->tmp0, s->A0, 8); - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1= ))); + tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(XMMReg, XMM_Q(1= ))); tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ); } =20 @@ -2943,33 +2943,33 @@ static void gen_ldy_env_A0(DisasContext *s, int off= set, bool align) int mem_index =3D s->mem_index; tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, mem_index, MO_LEUQ | (align ? MO_ALIGN_32 : 0)); - tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(0= ))); + tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(0= ))); tcg_gen_addi_tl(s->tmp0, s->A0, 8); tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ); - tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(1= ))); + tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(1= ))); =20 tcg_gen_addi_tl(s->tmp0, s->A0, 16); tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ); - tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(2= ))); + tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(2= ))); tcg_gen_addi_tl(s->tmp0, s->A0, 24); tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ); - tcg_gen_st_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(3= ))); + tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(3= ))); } =20 static void gen_sty_env_A0(DisasContext *s, int offset, bool align) { int mem_index =3D s->mem_index; - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(0= ))); + tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(0= ))); tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, mem_index, MO_LEUQ | (align ? MO_ALIGN_32 : 0)); tcg_gen_addi_tl(s->tmp0, s->A0, 8); - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(1= ))); + tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(1= ))); tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ); tcg_gen_addi_tl(s->tmp0, s->A0, 16); - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(2= ))); + tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(2= ))); tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ); tcg_gen_addi_tl(s->tmp0, s->A0, 24); - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, offset + offsetof(YMMReg, YMM_Q(3= ))); + tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(3= ))); tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ); } =20 @@ -3533,18 +3533,18 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) case 6: /* div */ switch(ot) { case MO_8: - gen_helper_divb_AL(cpu_env, s->T0); + gen_helper_divb_AL(tcg_env, s->T0); break; case MO_16: - gen_helper_divw_AX(cpu_env, s->T0); + gen_helper_divw_AX(tcg_env, s->T0); break; default: case MO_32: - gen_helper_divl_EAX(cpu_env, s->T0); + gen_helper_divl_EAX(tcg_env, s->T0); break; #ifdef TARGET_X86_64 case MO_64: - gen_helper_divq_EAX(cpu_env, s->T0); + gen_helper_divq_EAX(tcg_env, s->T0); break; #endif } @@ -3552,18 +3552,18 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) case 7: /* idiv */ switch(ot) { case MO_8: - gen_helper_idivb_AL(cpu_env, s->T0); + gen_helper_idivb_AL(tcg_env, s->T0); break; case MO_16: - gen_helper_idivw_AX(cpu_env, s->T0); + gen_helper_idivw_AX(tcg_env, s->T0); break; default: case MO_32: - gen_helper_idivl_EAX(cpu_env, s->T0); + gen_helper_idivl_EAX(tcg_env, s->T0); break; #ifdef TARGET_X86_64 case MO_64: - gen_helper_idivq_EAX(cpu_env, s->T0); + gen_helper_idivq_EAX(tcg_env, s->T0); break; #endif } @@ -3638,13 +3638,13 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) do_lcall: if (PE(s) && !VM86(s)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); - gen_helper_lcall_protected(cpu_env, s->tmp2_i32, s->T1, + gen_helper_lcall_protected(tcg_env, s->tmp2_i32, s->T1, tcg_constant_i32(dflag - 1), eip_next_tl(s)); } else { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1); - gen_helper_lcall_real(cpu_env, s->tmp2_i32, s->tmp3_i32, + gen_helper_lcall_real(tcg_env, s->tmp2_i32, s->tmp3_i32, tcg_constant_i32(dflag - 1), eip_next_i32(s)); } @@ -3668,7 +3668,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) do_ljmp: if (PE(s) && !VM86(s)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); - gen_helper_ljmp_protected(cpu_env, s->tmp2_i32, s->T1, + gen_helper_ljmp_protected(tcg_env, s->tmp2_i32, s->T1, eip_next_tl(s)); } else { gen_op_movl_seg_T0_vm(s, R_CS); @@ -3935,7 +3935,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (!(s->cpuid_ext_features & CPUID_7_0_ECX_RDPID)) { goto illegal_op; } - gen_helper_rdpid(s->T0, cpu_env); + gen_helper_rdpid(s->T0, tcg_env); rm =3D (modrm & 7) | REX_B(s); gen_op_mov_reg_v(s, dflag, rm, s->T0); break; @@ -3954,7 +3954,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } do_rdrand: translator_io_start(&s->base); - gen_helper_rdrand(s->T0, cpu_env); + gen_helper_rdrand(s->T0, tcg_env); rm =3D (modrm & 7) | REX_B(s); gen_op_mov_reg_v(s, dflag, rm, s->T0); set_cc_op(s, CC_OP_EFLAGS); @@ -4412,30 +4412,30 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) case 0: tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL); - gen_helper_flds_FT0(cpu_env, s->tmp2_i32); + gen_helper_flds_FT0(tcg_env, s->tmp2_i32); break; case 1: tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL); - gen_helper_fildl_FT0(cpu_env, s->tmp2_i32); + gen_helper_fildl_FT0(tcg_env, s->tmp2_i32); break; case 2: tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); - gen_helper_fldl_FT0(cpu_env, s->tmp1_i64); + gen_helper_fldl_FT0(tcg_env, s->tmp1_i64); break; case 3: default: tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LESW); - gen_helper_fildl_FT0(cpu_env, s->tmp2_i32); + gen_helper_fildl_FT0(tcg_env, s->tmp2_i32); break; } =20 gen_helper_fp_arith_ST0_FT0(op1); if (op1 =3D=3D 3) { /* fcomp needs pop */ - gen_helper_fpop(cpu_env); + gen_helper_fpop(tcg_env); } } break; @@ -4451,23 +4451,23 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) case 0: tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL); - gen_helper_flds_ST0(cpu_env, s->tmp2_i32); + gen_helper_flds_ST0(tcg_env, s->tmp2_i32); break; case 1: tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL); - gen_helper_fildl_ST0(cpu_env, s->tmp2_i32); + gen_helper_fildl_ST0(tcg_env, s->tmp2_i32); break; case 2: tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); - gen_helper_fldl_ST0(cpu_env, s->tmp1_i64); + gen_helper_fldl_ST0(tcg_env, s->tmp1_i64); break; case 3: default: tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LESW); - gen_helper_fildl_ST0(cpu_env, s->tmp2_i32); + gen_helper_fildl_ST0(tcg_env, s->tmp2_i32); break; } break; @@ -4475,116 +4475,116 @@ static bool disas_insn(DisasContext *s, CPUState = *cpu) /* XXX: the corresponding CPUID bit must be tested= ! */ switch (op >> 4) { case 1: - gen_helper_fisttl_ST0(s->tmp2_i32, cpu_env); + gen_helper_fisttl_ST0(s->tmp2_i32, tcg_env); tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL); break; case 2: - gen_helper_fisttll_ST0(s->tmp1_i64, cpu_env); + gen_helper_fisttll_ST0(s->tmp1_i64, tcg_env); tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); break; case 3: default: - gen_helper_fistt_ST0(s->tmp2_i32, cpu_env); + gen_helper_fistt_ST0(s->tmp2_i32, tcg_env); tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUW); break; } - gen_helper_fpop(cpu_env); + gen_helper_fpop(tcg_env); break; default: switch (op >> 4) { case 0: - gen_helper_fsts_ST0(s->tmp2_i32, cpu_env); + gen_helper_fsts_ST0(s->tmp2_i32, tcg_env); tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL); break; case 1: - gen_helper_fistl_ST0(s->tmp2_i32, cpu_env); + gen_helper_fistl_ST0(s->tmp2_i32, tcg_env); tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL); break; case 2: - gen_helper_fstl_ST0(s->tmp1_i64, cpu_env); + gen_helper_fstl_ST0(s->tmp1_i64, tcg_env); tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); break; case 3: default: - gen_helper_fist_ST0(s->tmp2_i32, cpu_env); + gen_helper_fist_ST0(s->tmp2_i32, tcg_env); tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUW); break; } if ((op & 7) =3D=3D 3) { - gen_helper_fpop(cpu_env); + gen_helper_fpop(tcg_env); } break; } break; case 0x0c: /* fldenv mem */ - gen_helper_fldenv(cpu_env, s->A0, + gen_helper_fldenv(tcg_env, s->A0, tcg_constant_i32(dflag - 1)); update_fip =3D update_fdp =3D false; break; case 0x0d: /* fldcw mem */ tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUW); - gen_helper_fldcw(cpu_env, s->tmp2_i32); + gen_helper_fldcw(tcg_env, s->tmp2_i32); update_fip =3D update_fdp =3D false; break; case 0x0e: /* fnstenv mem */ - gen_helper_fstenv(cpu_env, s->A0, + gen_helper_fstenv(tcg_env, s->A0, tcg_constant_i32(dflag - 1)); update_fip =3D update_fdp =3D false; break; case 0x0f: /* fnstcw mem */ - gen_helper_fnstcw(s->tmp2_i32, cpu_env); + gen_helper_fnstcw(s->tmp2_i32, tcg_env); tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUW); update_fip =3D update_fdp =3D false; break; case 0x1d: /* fldt mem */ - gen_helper_fldt_ST0(cpu_env, s->A0); + gen_helper_fldt_ST0(tcg_env, s->A0); break; case 0x1f: /* fstpt mem */ - gen_helper_fstt_ST0(cpu_env, s->A0); - gen_helper_fpop(cpu_env); + gen_helper_fstt_ST0(tcg_env, s->A0); + gen_helper_fpop(tcg_env); break; case 0x2c: /* frstor mem */ - gen_helper_frstor(cpu_env, s->A0, + gen_helper_frstor(tcg_env, s->A0, tcg_constant_i32(dflag - 1)); update_fip =3D update_fdp =3D false; break; case 0x2e: /* fnsave mem */ - gen_helper_fsave(cpu_env, s->A0, + gen_helper_fsave(tcg_env, s->A0, tcg_constant_i32(dflag - 1)); update_fip =3D update_fdp =3D false; break; case 0x2f: /* fnstsw mem */ - gen_helper_fnstsw(s->tmp2_i32, cpu_env); + gen_helper_fnstsw(s->tmp2_i32, tcg_env); tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUW); update_fip =3D update_fdp =3D false; break; case 0x3c: /* fbld */ - gen_helper_fbld_ST0(cpu_env, s->A0); + gen_helper_fbld_ST0(tcg_env, s->A0); break; case 0x3e: /* fbstp */ - gen_helper_fbst_ST0(cpu_env, s->A0); - gen_helper_fpop(cpu_env); + gen_helper_fbst_ST0(tcg_env, s->A0); + gen_helper_fpop(tcg_env); break; case 0x3d: /* fildll */ tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); - gen_helper_fildll_ST0(cpu_env, s->tmp1_i64); + gen_helper_fildll_ST0(tcg_env, s->tmp1_i64); break; case 0x3f: /* fistpll */ - gen_helper_fistll_ST0(s->tmp1_i64, cpu_env); + gen_helper_fistll_ST0(s->tmp1_i64, tcg_env); tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); - gen_helper_fpop(cpu_env); + gen_helper_fpop(tcg_env); break; default: goto unknown_op; @@ -4593,12 +4593,12 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) if (update_fdp) { int last_seg =3D s->override >=3D 0 ? s->override : a.= def_seg; =20 - tcg_gen_ld_i32(s->tmp2_i32, cpu_env, + tcg_gen_ld_i32(s->tmp2_i32, tcg_env, offsetof(CPUX86State, segs[last_seg].selector)); - tcg_gen_st16_i32(s->tmp2_i32, cpu_env, + tcg_gen_st16_i32(s->tmp2_i32, tcg_env, offsetof(CPUX86State, fpds)); - tcg_gen_st_tl(last_addr, cpu_env, + tcg_gen_st_tl(last_addr, tcg_env, offsetof(CPUX86State, fpdp)); } } else { @@ -4607,14 +4607,14 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) =20 switch (op) { case 0x08: /* fld sti */ - gen_helper_fpush(cpu_env); - gen_helper_fmov_ST0_STN(cpu_env, + gen_helper_fpush(tcg_env); + gen_helper_fmov_ST0_STN(tcg_env, tcg_constant_i32((opreg + 1) &= 7)); break; case 0x09: /* fxchg sti */ case 0x29: /* fxchg4 sti, undocumented op */ case 0x39: /* fxchg7 sti, undocumented op */ - gen_helper_fxchg_ST0_STN(cpu_env, tcg_constant_i32(opr= eg)); + gen_helper_fxchg_ST0_STN(tcg_env, tcg_constant_i32(opr= eg)); break; case 0x0a: /* grp d9/2 */ switch (rm) { @@ -4624,7 +4624,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) * needs to be treated as I/O because of ferr_irq */ translator_io_start(&s->base); - gen_helper_fwait(cpu_env); + gen_helper_fwait(tcg_env); update_fip =3D false; break; default: @@ -4634,17 +4634,17 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) case 0x0c: /* grp d9/4 */ switch (rm) { case 0: /* fchs */ - gen_helper_fchs_ST0(cpu_env); + gen_helper_fchs_ST0(tcg_env); break; case 1: /* fabs */ - gen_helper_fabs_ST0(cpu_env); + gen_helper_fabs_ST0(tcg_env); break; case 4: /* ftst */ - gen_helper_fldz_FT0(cpu_env); - gen_helper_fcom_ST0_FT0(cpu_env); + gen_helper_fldz_FT0(tcg_env); + gen_helper_fcom_ST0_FT0(tcg_env); break; case 5: /* fxam */ - gen_helper_fxam_ST0(cpu_env); + gen_helper_fxam_ST0(tcg_env); break; default: goto unknown_op; @@ -4654,32 +4654,32 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) { switch (rm) { case 0: - gen_helper_fpush(cpu_env); - gen_helper_fld1_ST0(cpu_env); + gen_helper_fpush(tcg_env); + gen_helper_fld1_ST0(tcg_env); break; case 1: - gen_helper_fpush(cpu_env); - gen_helper_fldl2t_ST0(cpu_env); + gen_helper_fpush(tcg_env); + gen_helper_fldl2t_ST0(tcg_env); break; case 2: - gen_helper_fpush(cpu_env); - gen_helper_fldl2e_ST0(cpu_env); + gen_helper_fpush(tcg_env); + gen_helper_fldl2e_ST0(tcg_env); break; case 3: - gen_helper_fpush(cpu_env); - gen_helper_fldpi_ST0(cpu_env); + gen_helper_fpush(tcg_env); + gen_helper_fldpi_ST0(tcg_env); break; case 4: - gen_helper_fpush(cpu_env); - gen_helper_fldlg2_ST0(cpu_env); + gen_helper_fpush(tcg_env); + gen_helper_fldlg2_ST0(tcg_env); break; case 5: - gen_helper_fpush(cpu_env); - gen_helper_fldln2_ST0(cpu_env); + gen_helper_fpush(tcg_env); + gen_helper_fldln2_ST0(tcg_env); break; case 6: - gen_helper_fpush(cpu_env); - gen_helper_fldz_ST0(cpu_env); + gen_helper_fpush(tcg_env); + gen_helper_fldz_ST0(tcg_env); break; default: goto unknown_op; @@ -4689,58 +4689,58 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) case 0x0e: /* grp d9/6 */ switch (rm) { case 0: /* f2xm1 */ - gen_helper_f2xm1(cpu_env); + gen_helper_f2xm1(tcg_env); break; case 1: /* fyl2x */ - gen_helper_fyl2x(cpu_env); + gen_helper_fyl2x(tcg_env); break; case 2: /* fptan */ - gen_helper_fptan(cpu_env); + gen_helper_fptan(tcg_env); break; case 3: /* fpatan */ - gen_helper_fpatan(cpu_env); + gen_helper_fpatan(tcg_env); break; case 4: /* fxtract */ - gen_helper_fxtract(cpu_env); + gen_helper_fxtract(tcg_env); break; case 5: /* fprem1 */ - gen_helper_fprem1(cpu_env); + gen_helper_fprem1(tcg_env); break; case 6: /* fdecstp */ - gen_helper_fdecstp(cpu_env); + gen_helper_fdecstp(tcg_env); break; default: case 7: /* fincstp */ - gen_helper_fincstp(cpu_env); + gen_helper_fincstp(tcg_env); break; } break; case 0x0f: /* grp d9/7 */ switch (rm) { case 0: /* fprem */ - gen_helper_fprem(cpu_env); + gen_helper_fprem(tcg_env); break; case 1: /* fyl2xp1 */ - gen_helper_fyl2xp1(cpu_env); + gen_helper_fyl2xp1(tcg_env); break; case 2: /* fsqrt */ - gen_helper_fsqrt(cpu_env); + gen_helper_fsqrt(tcg_env); break; case 3: /* fsincos */ - gen_helper_fsincos(cpu_env); + gen_helper_fsincos(tcg_env); break; case 5: /* fscale */ - gen_helper_fscale(cpu_env); + gen_helper_fscale(tcg_env); break; case 4: /* frndint */ - gen_helper_frndint(cpu_env); + gen_helper_frndint(tcg_env); break; case 6: /* fsin */ - gen_helper_fsin(cpu_env); + gen_helper_fsin(tcg_env); break; default: case 7: /* fcos */ - gen_helper_fcos(cpu_env); + gen_helper_fcos(tcg_env); break; } break; @@ -4754,10 +4754,10 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) if (op >=3D 0x20) { gen_helper_fp_arith_STN_ST0(op1, opreg); if (op >=3D 0x30) { - gen_helper_fpop(cpu_env); + gen_helper_fpop(tcg_env); } } else { - gen_helper_fmov_FT0_STN(cpu_env, + gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opreg= )); gen_helper_fp_arith_ST0_FT0(op1); } @@ -4765,23 +4765,23 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) break; case 0x02: /* fcom */ case 0x22: /* fcom2, undocumented op */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opre= g)); - gen_helper_fcom_ST0_FT0(cpu_env); + gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opre= g)); + gen_helper_fcom_ST0_FT0(tcg_env); break; case 0x03: /* fcomp */ case 0x23: /* fcomp3, undocumented op */ case 0x32: /* fcomp5, undocumented op */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opre= g)); - gen_helper_fcom_ST0_FT0(cpu_env); - gen_helper_fpop(cpu_env); + gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opre= g)); + gen_helper_fcom_ST0_FT0(tcg_env); + gen_helper_fpop(tcg_env); break; case 0x15: /* da/5 */ switch (rm) { case 1: /* fucompp */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(= 1)); - gen_helper_fucom_ST0_FT0(cpu_env); - gen_helper_fpop(cpu_env); - gen_helper_fpop(cpu_env); + gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(= 1)); + gen_helper_fucom_ST0_FT0(tcg_env); + gen_helper_fpop(tcg_env); + gen_helper_fpop(tcg_env); break; default: goto unknown_op; @@ -4794,11 +4794,11 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) case 1: /* fdisi (287 only, just do nop here) */ break; case 2: /* fclex */ - gen_helper_fclex(cpu_env); + gen_helper_fclex(tcg_env); update_fip =3D false; break; case 3: /* fninit */ - gen_helper_fninit(cpu_env); + gen_helper_fninit(tcg_env); update_fip =3D false; break; case 4: /* fsetpm (287 only, just do nop here) */ @@ -4812,8 +4812,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_update_cc_op(s); - gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opre= g)); - gen_helper_fucomi_ST0_FT0(cpu_env); + gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opre= g)); + gen_helper_fucomi_ST0_FT0(tcg_env); set_cc_op(s, CC_OP_EFLAGS); break; case 0x1e: /* fcomi */ @@ -4821,52 +4821,52 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) goto illegal_op; } gen_update_cc_op(s); - gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opre= g)); - gen_helper_fcomi_ST0_FT0(cpu_env); + gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opre= g)); + gen_helper_fcomi_ST0_FT0(tcg_env); set_cc_op(s, CC_OP_EFLAGS); break; case 0x28: /* ffree sti */ - gen_helper_ffree_STN(cpu_env, tcg_constant_i32(opreg)); + gen_helper_ffree_STN(tcg_env, tcg_constant_i32(opreg)); break; case 0x2a: /* fst sti */ - gen_helper_fmov_STN_ST0(cpu_env, tcg_constant_i32(opre= g)); + gen_helper_fmov_STN_ST0(tcg_env, tcg_constant_i32(opre= g)); break; case 0x2b: /* fstp sti */ case 0x0b: /* fstp1 sti, undocumented op */ case 0x3a: /* fstp8 sti, undocumented op */ case 0x3b: /* fstp9 sti, undocumented op */ - gen_helper_fmov_STN_ST0(cpu_env, tcg_constant_i32(opre= g)); - gen_helper_fpop(cpu_env); + gen_helper_fmov_STN_ST0(tcg_env, tcg_constant_i32(opre= g)); + gen_helper_fpop(tcg_env); break; case 0x2c: /* fucom st(i) */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opre= g)); - gen_helper_fucom_ST0_FT0(cpu_env); + gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opre= g)); + gen_helper_fucom_ST0_FT0(tcg_env); break; case 0x2d: /* fucomp st(i) */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opre= g)); - gen_helper_fucom_ST0_FT0(cpu_env); - gen_helper_fpop(cpu_env); + gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opre= g)); + gen_helper_fucom_ST0_FT0(tcg_env); + gen_helper_fpop(tcg_env); break; case 0x33: /* de/3 */ switch (rm) { case 1: /* fcompp */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(= 1)); - gen_helper_fcom_ST0_FT0(cpu_env); - gen_helper_fpop(cpu_env); - gen_helper_fpop(cpu_env); + gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(= 1)); + gen_helper_fcom_ST0_FT0(tcg_env); + gen_helper_fpop(tcg_env); + gen_helper_fpop(tcg_env); break; default: goto unknown_op; } break; case 0x38: /* ffreep sti, undocumented op */ - gen_helper_ffree_STN(cpu_env, tcg_constant_i32(opreg)); - gen_helper_fpop(cpu_env); + gen_helper_ffree_STN(tcg_env, tcg_constant_i32(opreg)); + gen_helper_fpop(tcg_env); break; case 0x3c: /* df/4 */ switch (rm) { case 0: - gen_helper_fnstsw(s->tmp2_i32, cpu_env); + gen_helper_fnstsw(s->tmp2_i32, tcg_env); tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32); gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); break; @@ -4879,9 +4879,9 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_update_cc_op(s); - gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opre= g)); - gen_helper_fucomi_ST0_FT0(cpu_env); - gen_helper_fpop(cpu_env); + gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opre= g)); + gen_helper_fucomi_ST0_FT0(tcg_env); + gen_helper_fpop(tcg_env); set_cc_op(s, CC_OP_EFLAGS); break; case 0x3e: /* fcomip */ @@ -4889,9 +4889,9 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_update_cc_op(s); - gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opre= g)); - gen_helper_fcomi_ST0_FT0(cpu_env); - gen_helper_fpop(cpu_env); + gen_helper_fmov_FT0_STN(tcg_env, tcg_constant_i32(opre= g)); + gen_helper_fcomi_ST0_FT0(tcg_env); + gen_helper_fpop(tcg_env); set_cc_op(s, CC_OP_EFLAGS); break; case 0x10 ... 0x13: /* fcmovxx */ @@ -4912,7 +4912,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) op1 =3D fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); l1 =3D gen_new_label(); gen_jcc1_noeob(s, op1, l1); - gen_helper_fmov_ST0_STN(cpu_env, + gen_helper_fmov_ST0_STN(tcg_env, tcg_constant_i32(opreg)); gen_set_label(l1); } @@ -4923,12 +4923,12 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) } =20 if (update_fip) { - tcg_gen_ld_i32(s->tmp2_i32, cpu_env, + tcg_gen_ld_i32(s->tmp2_i32, tcg_env, offsetof(CPUX86State, segs[R_CS].selector)); - tcg_gen_st16_i32(s->tmp2_i32, cpu_env, + tcg_gen_st16_i32(s->tmp2_i32, tcg_env, offsetof(CPUX86State, fpcs)); tcg_gen_st_tl(eip_cur_tl(s), - cpu_env, offsetof(CPUX86State, fpip)); + tcg_env, offsetof(CPUX86State, fpip)); } } break; @@ -5101,7 +5101,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (PE(s) && !VM86(s)) { gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_lret_protected(cpu_env, tcg_constant_i32(dflag - 1), + gen_helper_lret_protected(tcg_env, tcg_constant_i32(dflag - 1), tcg_constant_i32(val)); } else { gen_stack_A0(s); @@ -5129,9 +5129,9 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (!check_vm86_iopl(s)) { break; } - gen_helper_iret_real(cpu_env, tcg_constant_i32(dflag - 1)); + gen_helper_iret_real(tcg_env, tcg_constant_i32(dflag - 1)); } else { - gen_helper_iret_protected(cpu_env, tcg_constant_i32(dflag - 1), + gen_helper_iret_protected(tcg_env, tcg_constant_i32(dflag - 1), eip_next_i32(s)); } set_cc_op(s, CC_OP_EFLAGS); @@ -5228,7 +5228,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_svm_check_intercept(s, SVM_EXIT_PUSHF); if (check_vm86_iopl(s)) { gen_update_cc_op(s); - gen_helper_read_eflags(s->T0, cpu_env); + gen_helper_read_eflags(s->T0, tcg_env); gen_push_v(s, s->T0); } break; @@ -5247,7 +5247,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } =20 ot =3D gen_pop_T0(s); - gen_helper_write_eflags(cpu_env, s->T0, tcg_constant_i32(mask)= ); + gen_helper_write_eflags(tcg_env, s->T0, tcg_constant_i32(mask)= ); gen_pop_update(s, ot); set_cc_op(s, CC_OP_EFLAGS); /* abort translation because TF/AC flag may change */ @@ -5285,11 +5285,11 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) break; case 0xfc: /* cld */ tcg_gen_movi_i32(s->tmp2_i32, 1); - tcg_gen_st_i32(s->tmp2_i32, cpu_env, offsetof(CPUX86State, df)); + tcg_gen_st_i32(s->tmp2_i32, tcg_env, offsetof(CPUX86State, df)); break; case 0xfd: /* std */ tcg_gen_movi_i32(s->tmp2_i32, -1); - tcg_gen_st_i32(s->tmp2_i32, cpu_env, offsetof(CPUX86State, df)); + tcg_gen_st_i32(s->tmp2_i32, tcg_env, offsetof(CPUX86State, df)); break; =20 /************************/ @@ -5487,28 +5487,28 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) if (CODE64(s)) goto illegal_op; gen_update_cc_op(s); - gen_helper_daa(cpu_env); + gen_helper_daa(tcg_env); set_cc_op(s, CC_OP_EFLAGS); break; case 0x2f: /* das */ if (CODE64(s)) goto illegal_op; gen_update_cc_op(s); - gen_helper_das(cpu_env); + gen_helper_das(tcg_env); set_cc_op(s, CC_OP_EFLAGS); break; case 0x37: /* aaa */ if (CODE64(s)) goto illegal_op; gen_update_cc_op(s); - gen_helper_aaa(cpu_env); + gen_helper_aaa(tcg_env); set_cc_op(s, CC_OP_EFLAGS); break; case 0x3f: /* aas */ if (CODE64(s)) goto illegal_op; gen_update_cc_op(s); - gen_helper_aas(cpu_env); + gen_helper_aas(tcg_env); set_cc_op(s, CC_OP_EFLAGS); break; case 0xd4: /* aam */ @@ -5518,7 +5518,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (val =3D=3D 0) { gen_exception(s, EXCP00_DIVZ); } else { - gen_helper_aam(cpu_env, tcg_constant_i32(val)); + gen_helper_aam(tcg_env, tcg_constant_i32(val)); set_cc_op(s, CC_OP_LOGICB); } break; @@ -5526,7 +5526,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (CODE64(s)) goto illegal_op; val =3D x86_ldub_code(env, s); - gen_helper_aad(cpu_env, tcg_constant_i32(val)); + gen_helper_aad(tcg_env, tcg_constant_i32(val)); set_cc_op(s, CC_OP_LOGICB); break; /************************/ @@ -5543,7 +5543,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (prefixes & PREFIX_REPZ) { gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_pause(cpu_env, cur_insn_len_i32(s)); + gen_helper_pause(tcg_env, cur_insn_len_i32(s)); s->base.is_jmp =3D DISAS_NORETURN; } break; @@ -5554,7 +5554,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } else { /* needs to be treated as I/O because of ferr_irq */ translator_io_start(&s->base); - gen_helper_fwait(cpu_env); + gen_helper_fwait(tcg_env); } break; case 0xcc: /* int3 */ @@ -5571,7 +5571,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_into(cpu_env, cur_insn_len_i32(s)); + gen_helper_into(tcg_env, cur_insn_len_i32(s)); break; #ifdef WANT_ICEBP case 0xf1: /* icebp (undocumented, exits to external debugger) */ @@ -5605,9 +5605,9 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_lea_modrm(env, s, modrm); tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); if (ot =3D=3D MO_16) { - gen_helper_boundw(cpu_env, s->A0, s->tmp2_i32); + gen_helper_boundw(tcg_env, s->A0, s->tmp2_i32); } else { - gen_helper_boundl(cpu_env, s->A0, s->tmp2_i32); + gen_helper_boundl(tcg_env, s->A0, s->tmp2_i32); } break; case 0x1c8 ... 0x1cf: /* bswap reg */ @@ -5669,9 +5669,9 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_update_cc_op(s); gen_update_eip_cur(s); if (b & 2) { - gen_helper_rdmsr(cpu_env); + gen_helper_rdmsr(tcg_env); } else { - gen_helper_wrmsr(cpu_env); + gen_helper_wrmsr(tcg_env); s->base.is_jmp =3D DISAS_EOB_NEXT; } } @@ -5680,12 +5680,12 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) gen_update_cc_op(s); gen_update_eip_cur(s); translator_io_start(&s->base); - gen_helper_rdtsc(cpu_env); + gen_helper_rdtsc(tcg_env); break; case 0x133: /* rdpmc */ gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_rdpmc(cpu_env); + gen_helper_rdpmc(tcg_env); s->base.is_jmp =3D DISAS_NORETURN; break; case 0x134: /* sysenter */ @@ -5696,7 +5696,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (!PE(s)) { gen_exception_gpf(s); } else { - gen_helper_sysenter(cpu_env); + gen_helper_sysenter(tcg_env); s->base.is_jmp =3D DISAS_EOB_ONLY; } break; @@ -5708,7 +5708,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (!PE(s) || CPL(s) !=3D 0) { gen_exception_gpf(s); } else { - gen_helper_sysexit(cpu_env, tcg_constant_i32(dflag - 1)); + gen_helper_sysexit(tcg_env, tcg_constant_i32(dflag - 1)); s->base.is_jmp =3D DISAS_EOB_ONLY; } break; @@ -5719,7 +5719,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_syscall(cpu_env, cur_insn_len_i32(s)); + gen_helper_syscall(tcg_env, cur_insn_len_i32(s)); /* TF handling for the syscall insn is different. The TF bit is c= hecked after the syscall insn completes. This allows #DB to not be generated after one has entered CPL0 if TF is set in FMASK. */ @@ -5733,7 +5733,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (!PE(s) || CPL(s) !=3D 0) { gen_exception_gpf(s); } else { - gen_helper_sysret(cpu_env, tcg_constant_i32(dflag - 1)); + gen_helper_sysret(tcg_env, tcg_constant_i32(dflag - 1)); /* condition codes are modified only in long mode */ if (LMA(s)) { set_cc_op(s, CC_OP_EFLAGS); @@ -5748,13 +5748,13 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) case 0x1a2: /* cpuid */ gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_cpuid(cpu_env); + gen_helper_cpuid(tcg_env); break; case 0xf4: /* hlt */ if (check_cpl0(s)) { gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_hlt(cpu_env, cur_insn_len_i32(s)); + gen_helper_hlt(tcg_env, cur_insn_len_i32(s)); s->base.is_jmp =3D DISAS_NORETURN; } break; @@ -5770,7 +5770,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; } gen_svm_check_intercept(s, SVM_EXIT_LDTR_READ); - tcg_gen_ld32u_tl(s->T0, cpu_env, + tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, ldt.selector)); ot =3D mod =3D=3D 3 ? dflag : MO_16; gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); @@ -5782,7 +5782,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_svm_check_intercept(s, SVM_EXIT_LDTR_WRITE); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); - gen_helper_lldt(cpu_env, s->tmp2_i32); + gen_helper_lldt(tcg_env, s->tmp2_i32); } break; case 1: /* str */ @@ -5792,7 +5792,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; } gen_svm_check_intercept(s, SVM_EXIT_TR_READ); - tcg_gen_ld32u_tl(s->T0, cpu_env, + tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, tr.selector)); ot =3D mod =3D=3D 3 ? dflag : MO_16; gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); @@ -5804,7 +5804,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_svm_check_intercept(s, SVM_EXIT_TR_WRITE); gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); - gen_helper_ltr(cpu_env, s->tmp2_i32); + gen_helper_ltr(tcg_env, s->tmp2_i32); } break; case 4: /* verr */ @@ -5814,9 +5814,9 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); gen_update_cc_op(s); if (op =3D=3D 4) { - gen_helper_verr(cpu_env, s->T0); + gen_helper_verr(tcg_env, s->T0); } else { - gen_helper_verw(cpu_env, s->T0); + gen_helper_verw(tcg_env, s->T0); } set_cc_op(s, CC_OP_EFLAGS); break; @@ -5835,10 +5835,10 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) gen_svm_check_intercept(s, SVM_EXIT_GDTR_READ); gen_lea_modrm(env, s, modrm); tcg_gen_ld32u_tl(s->T0, - cpu_env, offsetof(CPUX86State, gdt.limit)); + tcg_env, offsetof(CPUX86State, gdt.limit)); gen_op_st_v(s, MO_16, s->T0, s->A0); gen_add_A0_im(s, 2); - tcg_gen_ld_tl(s->T0, cpu_env, offsetof(CPUX86State, gdt.base)); + tcg_gen_ld_tl(s->T0, tcg_env, offsetof(CPUX86State, gdt.base)); if (dflag =3D=3D MO_16) { tcg_gen_andi_tl(s->T0, s->T0, 0xffffff); } @@ -5854,7 +5854,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) tcg_gen_mov_tl(s->A0, cpu_regs[R_EAX]); gen_extu(s->aflag, s->A0); gen_add_A0_ds_seg(s); - gen_helper_monitor(cpu_env, s->A0); + gen_helper_monitor(tcg_env, s->A0); break; =20 case 0xc9: /* mwait */ @@ -5863,7 +5863,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_mwait(cpu_env, cur_insn_len_i32(s)); + gen_helper_mwait(tcg_env, cur_insn_len_i32(s)); s->base.is_jmp =3D DISAS_NORETURN; break; =20 @@ -5891,10 +5891,10 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) } gen_svm_check_intercept(s, SVM_EXIT_IDTR_READ); gen_lea_modrm(env, s, modrm); - tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, idt.lim= it)); + tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, idt.lim= it)); gen_op_st_v(s, MO_16, s->T0, s->A0); gen_add_A0_im(s, 2); - tcg_gen_ld_tl(s->T0, cpu_env, offsetof(CPUX86State, idt.base)); + tcg_gen_ld_tl(s->T0, tcg_env, offsetof(CPUX86State, idt.base)); if (dflag =3D=3D MO_16) { tcg_gen_andi_tl(s->T0, s->T0, 0xffffff); } @@ -5908,7 +5908,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]); - gen_helper_xgetbv(s->tmp1_i64, cpu_env, s->tmp2_i32); + gen_helper_xgetbv(s->tmp1_i64, tcg_env, s->tmp2_i32); tcg_gen_extr_i64_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], s->tmp1_= i64); break; =20 @@ -5924,7 +5924,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX], cpu_regs[R_EDX]); tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]); - gen_helper_xsetbv(cpu_env, s->tmp2_i32, s->tmp1_i64); + gen_helper_xsetbv(tcg_env, s->tmp2_i32, s->tmp1_i64); /* End TB because translation flags may change. */ s->base.is_jmp =3D DISAS_EOB_NEXT; break; @@ -5938,7 +5938,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_vmrun(cpu_env, tcg_constant_i32(s->aflag - 1), + gen_helper_vmrun(tcg_env, tcg_constant_i32(s->aflag - 1), cur_insn_len_i32(s)); tcg_gen_exit_tb(NULL, 0); s->base.is_jmp =3D DISAS_NORETURN; @@ -5950,7 +5950,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_vmmcall(cpu_env); + gen_helper_vmmcall(tcg_env); break; =20 case 0xda: /* VMLOAD */ @@ -5962,7 +5962,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_vmload(cpu_env, tcg_constant_i32(s->aflag - 1)); + gen_helper_vmload(tcg_env, tcg_constant_i32(s->aflag - 1)); break; =20 case 0xdb: /* VMSAVE */ @@ -5974,7 +5974,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_vmsave(cpu_env, tcg_constant_i32(s->aflag - 1)); + gen_helper_vmsave(tcg_env, tcg_constant_i32(s->aflag - 1)); break; =20 case 0xdc: /* STGI */ @@ -5986,7 +5986,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; } gen_update_cc_op(s); - gen_helper_stgi(cpu_env); + gen_helper_stgi(tcg_env); s->base.is_jmp =3D DISAS_EOB_NEXT; break; =20 @@ -5999,7 +5999,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_clgi(cpu_env); + gen_helper_clgi(tcg_env); break; =20 case 0xde: /* SKINIT */ @@ -6024,7 +6024,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } else { tcg_gen_ext32u_tl(s->A0, cpu_regs[R_EAX]); } - gen_helper_flush_page(cpu_env, s->A0); + gen_helper_flush_page(tcg_env, s->A0); s->base.is_jmp =3D DISAS_EOB_NEXT; break; =20 @@ -6040,8 +6040,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (dflag =3D=3D MO_16) { tcg_gen_andi_tl(s->T0, s->T0, 0xffffff); } - tcg_gen_st_tl(s->T0, cpu_env, offsetof(CPUX86State, gdt.base)); - tcg_gen_st32_tl(s->T1, cpu_env, offsetof(CPUX86State, gdt.limi= t)); + tcg_gen_st_tl(s->T0, tcg_env, offsetof(CPUX86State, gdt.base)); + tcg_gen_st32_tl(s->T1, tcg_env, offsetof(CPUX86State, gdt.limi= t)); break; =20 CASE_MODRM_MEM_OP(3): /* lidt */ @@ -6056,8 +6056,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (dflag =3D=3D MO_16) { tcg_gen_andi_tl(s->T0, s->T0, 0xffffff); } - tcg_gen_st_tl(s->T0, cpu_env, offsetof(CPUX86State, idt.base)); - tcg_gen_st32_tl(s->T1, cpu_env, offsetof(CPUX86State, idt.limi= t)); + tcg_gen_st_tl(s->T0, tcg_env, offsetof(CPUX86State, idt.base)); + tcg_gen_st32_tl(s->T1, tcg_env, offsetof(CPUX86State, idt.limi= t)); break; =20 CASE_MODRM_OP(4): /* smsw */ @@ -6065,7 +6065,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; } gen_svm_check_intercept(s, SVM_EXIT_READ_CR0); - tcg_gen_ld_tl(s->T0, cpu_env, offsetof(CPUX86State, cr[0])); + tcg_gen_ld_tl(s->T0, tcg_env, offsetof(CPUX86State, cr[0])); /* * In 32-bit mode, the higher 16 bits of the destination * register are undefined. In practice CR0[31:0] is stored @@ -6080,7 +6080,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]); - gen_helper_rdpkru(s->tmp1_i64, cpu_env, s->tmp2_i32); + gen_helper_rdpkru(s->tmp1_i64, tcg_env, s->tmp2_i32); tcg_gen_extr_i64_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], s->tmp1_= i64); break; case 0xef: /* wrpkru */ @@ -6090,7 +6090,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX], cpu_regs[R_EDX]); tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]); - gen_helper_wrpkru(cpu_env, s->tmp2_i32, s->tmp1_i64); + gen_helper_wrpkru(tcg_env, s->tmp2_i32, s->tmp1_i64); break; =20 CASE_MODRM_OP(6): /* lmsw */ @@ -6103,11 +6103,11 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) * Only the 4 lower bits of CR0 are modified. * PE cannot be set to zero if already set to one. */ - tcg_gen_ld_tl(s->T1, cpu_env, offsetof(CPUX86State, cr[0])); + tcg_gen_ld_tl(s->T1, tcg_env, offsetof(CPUX86State, cr[0])); tcg_gen_andi_tl(s->T0, s->T0, 0xf); tcg_gen_andi_tl(s->T1, s->T1, ~0xe); tcg_gen_or_tl(s->T0, s->T0, s->T1); - gen_helper_write_crN(cpu_env, tcg_constant_i32(0), s->T0); + gen_helper_write_crN(tcg_env, tcg_constant_i32(0), s->T0); s->base.is_jmp =3D DISAS_EOB_NEXT; break; =20 @@ -6117,7 +6117,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_svm_check_intercept(s, SVM_EXIT_INVLPG); gen_lea_modrm(env, s, modrm); - gen_helper_flush_page(cpu_env, s->A0); + gen_helper_flush_page(tcg_env, s->A0); s->base.is_jmp =3D DISAS_EOB_NEXT; break; =20 @@ -6126,9 +6126,9 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (CODE64(s)) { if (check_cpl0(s)) { tcg_gen_mov_tl(s->T0, cpu_seg_base[R_GS]); - tcg_gen_ld_tl(cpu_seg_base[R_GS], cpu_env, + tcg_gen_ld_tl(cpu_seg_base[R_GS], tcg_env, offsetof(CPUX86State, kernelgsbase)); - tcg_gen_st_tl(s->T0, cpu_env, + tcg_gen_st_tl(s->T0, tcg_env, offsetof(CPUX86State, kernelgsbase)); } break; @@ -6143,8 +6143,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_update_cc_op(s); gen_update_eip_cur(s); translator_io_start(&s->base); - gen_helper_rdtsc(cpu_env); - gen_helper_rdpid(s->T0, cpu_env); + gen_helper_rdtsc(tcg_env); + gen_helper_rdpid(s->T0, tcg_env); gen_op_mov_reg_v(s, dflag, R_ECX, s->T0); break; =20 @@ -6240,9 +6240,9 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) t0 =3D tcg_temp_new(); gen_update_cc_op(s); if (b =3D=3D 0x102) { - gen_helper_lar(t0, cpu_env, s->T0); + gen_helper_lar(t0, tcg_env, s->T0); } else { - gen_helper_lsl(t0, cpu_env, s->T0); + gen_helper_lsl(t0, tcg_env, s->T0); } tcg_gen_andi_tl(s->tmp0, cpu_cc_src, CC_Z); label1 =3D gen_new_label(); @@ -6347,11 +6347,11 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) tcg_gen_movi_tl(s->T0, 0); } if (CODE64(s)) { - gen_helper_bndldx64(cpu_bndl[reg], cpu_env, s->A0, s->= T0); - tcg_gen_ld_i64(cpu_bndu[reg], cpu_env, + gen_helper_bndldx64(cpu_bndl[reg], tcg_env, s->A0, s->= T0); + tcg_gen_ld_i64(cpu_bndu[reg], tcg_env, offsetof(CPUX86State, mmx_t0.MMX_Q(0))); } else { - gen_helper_bndldx32(cpu_bndu[reg], cpu_env, s->A0, s->= T0); + gen_helper_bndldx32(cpu_bndu[reg], tcg_env, s->A0, s->= T0); tcg_gen_ext32u_i64(cpu_bndl[reg], cpu_bndu[reg]); tcg_gen_shri_i64(cpu_bndu[reg], cpu_bndu[reg], 32); } @@ -6452,10 +6452,10 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) tcg_gen_movi_tl(s->T0, 0); } if (CODE64(s)) { - gen_helper_bndstx64(cpu_env, s->A0, s->T0, + gen_helper_bndstx64(tcg_env, s->A0, s->T0, cpu_bndl[reg], cpu_bndu[reg]); } else { - gen_helper_bndstx32(cpu_env, s->A0, s->T0, + gen_helper_bndstx32(tcg_env, s->A0, s->T0, cpu_bndl[reg], cpu_bndu[reg]); } } @@ -6502,11 +6502,11 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) if (b & 2) { gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0 + reg); gen_op_mov_v_reg(s, ot, s->T0, rm); - gen_helper_write_crN(cpu_env, tcg_constant_i32(reg), s->T0); + gen_helper_write_crN(tcg_env, tcg_constant_i32(reg), s->T0); s->base.is_jmp =3D DISAS_EOB_NEXT; } else { gen_svm_check_intercept(s, SVM_EXIT_READ_CR0 + reg); - gen_helper_read_crN(s->T0, cpu_env, tcg_constant_i32(reg)); + gen_helper_read_crN(s->T0, tcg_env, tcg_constant_i32(reg)); gen_op_mov_reg_v(s, ot, rm, s->T0); } break; @@ -6533,12 +6533,12 @@ static bool disas_insn(DisasContext *s, CPUState *c= pu) gen_svm_check_intercept(s, SVM_EXIT_WRITE_DR0 + reg); gen_op_mov_v_reg(s, ot, s->T0, rm); tcg_gen_movi_i32(s->tmp2_i32, reg); - gen_helper_set_dr(cpu_env, s->tmp2_i32, s->T0); + gen_helper_set_dr(tcg_env, s->tmp2_i32, s->T0); s->base.is_jmp =3D DISAS_EOB_NEXT; } else { gen_svm_check_intercept(s, SVM_EXIT_READ_DR0 + reg); tcg_gen_movi_i32(s->tmp2_i32, reg); - gen_helper_get_dr(s->T0, cpu_env, s->tmp2_i32); + gen_helper_get_dr(s->T0, tcg_env, s->tmp2_i32); gen_op_mov_reg_v(s, ot, rm, s->T0); } } @@ -6546,7 +6546,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) case 0x106: /* clts */ if (check_cpl0(s)) { gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0); - gen_helper_clts(cpu_env); + gen_helper_clts(tcg_env); /* abort block because static cpu state changed */ s->base.is_jmp =3D DISAS_EOB_NEXT; } @@ -6577,7 +6577,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; } gen_lea_modrm(env, s, modrm); - gen_helper_fxsave(cpu_env, s->A0); + gen_helper_fxsave(tcg_env, s->A0); break; =20 CASE_MODRM_MEM_OP(1): /* fxrstor */ @@ -6590,7 +6590,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; } gen_lea_modrm(env, s, modrm); - gen_helper_fxrstor(cpu_env, s->A0); + gen_helper_fxrstor(tcg_env, s->A0); break; =20 CASE_MODRM_MEM_OP(2): /* ldmxcsr */ @@ -6603,7 +6603,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_lea_modrm(env, s, modrm); tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUL); - gen_helper_ldmxcsr(cpu_env, s->tmp2_i32); + gen_helper_ldmxcsr(tcg_env, s->tmp2_i32); break; =20 CASE_MODRM_MEM_OP(3): /* stmxcsr */ @@ -6614,9 +6614,9 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_exception(s, EXCP07_PREX); break; } - gen_helper_update_mxcsr(cpu_env); + gen_helper_update_mxcsr(tcg_env); gen_lea_modrm(env, s, modrm); - tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, mxcsr)); + tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, mxcsr)); gen_op_st_v(s, MO_32, s->T0, s->A0); break; =20 @@ -6629,7 +6629,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_lea_modrm(env, s, modrm); tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX], cpu_regs[R_EDX]); - gen_helper_xsave(cpu_env, s->A0, s->tmp1_i64); + gen_helper_xsave(tcg_env, s->A0, s->tmp1_i64); break; =20 CASE_MODRM_MEM_OP(5): /* xrstor */ @@ -6641,7 +6641,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_lea_modrm(env, s, modrm); tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX], cpu_regs[R_EDX]); - gen_helper_xrstor(cpu_env, s->A0, s->tmp1_i64); + gen_helper_xrstor(tcg_env, s->A0, s->tmp1_i64); /* XRSTOR is how MPX is enabled, which changes how we translate. Thus we need to end the TB. */ s->base.is_jmp =3D DISAS_EOB_NEXT; @@ -6667,7 +6667,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_lea_modrm(env, s, modrm); tcg_gen_concat_tl_i64(s->tmp1_i64, cpu_regs[R_EAX], cpu_regs[R_EDX]); - gen_helper_xsaveopt(cpu_env, s->A0, s->tmp1_i64); + gen_helper_xsaveopt(tcg_env, s->A0, s->tmp1_i64); } break; =20 @@ -6702,7 +6702,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) =20 /* Preserve hflags bits by testing CR4 at runtime. */ tcg_gen_movi_i32(s->tmp2_i32, CR4_FSGSBASE_MASK); - gen_helper_cr4_testbit(cpu_env, s->tmp2_i32); + gen_helper_cr4_testbit(tcg_env, s->tmp2_i32); =20 base =3D cpu_seg_base[modrm & 8 ? R_GS : R_FS]; treg =3D cpu_regs[(modrm & 7) | REX_B(s)]; @@ -6778,7 +6778,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) #else gen_update_cc_op(s); gen_update_eip_next(s); - gen_helper_rsm(cpu_env); + gen_helper_rsm(tcg_env); #endif /* CONFIG_USER_ONLY */ s->base.is_jmp =3D DISAS_EOB_ONLY; break; @@ -6882,36 +6882,36 @@ void tcg_x86_init(void) }; int i; =20 - cpu_cc_op =3D tcg_global_mem_new_i32(cpu_env, + cpu_cc_op =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUX86State, cc_op), "cc_o= p"); - cpu_cc_dst =3D tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_ds= t), + cpu_cc_dst =3D tcg_global_mem_new(tcg_env, offsetof(CPUX86State, cc_ds= t), "cc_dst"); - cpu_cc_src =3D tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_sr= c), + cpu_cc_src =3D tcg_global_mem_new(tcg_env, offsetof(CPUX86State, cc_sr= c), "cc_src"); - cpu_cc_src2 =3D tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_s= rc2), + cpu_cc_src2 =3D tcg_global_mem_new(tcg_env, offsetof(CPUX86State, cc_s= rc2), "cc_src2"); - cpu_eip =3D tcg_global_mem_new(cpu_env, offsetof(CPUX86State, eip), ei= p_name); + cpu_eip =3D tcg_global_mem_new(tcg_env, offsetof(CPUX86State, eip), ei= p_name); =20 for (i =3D 0; i < CPU_NB_REGS; ++i) { - cpu_regs[i] =3D tcg_global_mem_new(cpu_env, + cpu_regs[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUX86State, regs[i]), reg_names[i]); } =20 for (i =3D 0; i < 6; ++i) { cpu_seg_base[i] - =3D tcg_global_mem_new(cpu_env, + =3D tcg_global_mem_new(tcg_env, offsetof(CPUX86State, segs[i].base), seg_base_names[i]); } =20 for (i =3D 0; i < 4; ++i) { cpu_bndl[i] - =3D tcg_global_mem_new_i64(cpu_env, + =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUX86State, bnd_regs[i].lb), bnd_regl_names[i]); cpu_bndu[i] - =3D tcg_global_mem_new_i64(cpu_env, + =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUX86State, bnd_regs[i].ub), bnd_regu_names[i]); } diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index fd393ed76d..4a4c022f51 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -38,13 +38,13 @@ static inline int vec_full_offset(int regno) =20 static inline void get_vreg64(TCGv_i64 dest, int regno, int index) { - tcg_gen_ld_i64(dest, cpu_env, + tcg_gen_ld_i64(dest, tcg_env, offsetof(CPULoongArchState, fpr[regno].vreg.D(index))); } =20 static inline void set_vreg64(TCGv_i64 src, int regno, int index) { - tcg_gen_st_i64(src, cpu_env, + tcg_gen_st_i64(src, tcg_env, offsetof(CPULoongArchState, fpr[regno].vreg.D(index))); } =20 @@ -80,7 +80,7 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) void generate_exception(DisasContext *ctx, int excp) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); + gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -204,14 +204,14 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExt= end dst_ext) static TCGv get_fpr(DisasContext *ctx, int reg_num) { TCGv t =3D tcg_temp_new(); - tcg_gen_ld_i64(t, cpu_env, + tcg_gen_ld_i64(t, tcg_env, offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0))); return t; } =20 static void set_fpr(int reg_num, TCGv val) { - tcg_gen_st_i64(val, cpu_env, + tcg_gen_st_i64(val, tcg_env, offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0))); } =20 @@ -340,14 +340,14 @@ void loongarch_translate_init(void) =20 cpu_gpr[0] =3D NULL; for (i =3D 1; i < 32; i++) { - cpu_gpr[i] =3D tcg_global_mem_new(cpu_env, + cpu_gpr[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPULoongArchState, gpr[i]= ), regnames[i]); } =20 - cpu_pc =3D tcg_global_mem_new(cpu_env, offsetof(CPULoongArchState, pc)= , "pc"); - cpu_lladdr =3D tcg_global_mem_new(cpu_env, + cpu_pc =3D tcg_global_mem_new(tcg_env, offsetof(CPULoongArchState, pc)= , "pc"); + cpu_lladdr =3D tcg_global_mem_new(tcg_env, offsetof(CPULoongArchState, lladdr), "lladdr"); - cpu_llval =3D tcg_global_mem_new(cpu_env, + cpu_llval =3D tcg_global_mem_new(tcg_env, offsetof(CPULoongArchState, llval), "llval"); } diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 9e224fe796..0989a5b6bd 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -70,19 +70,19 @@ void m68k_tcg_init(void) int i; =20 #define DEFO32(name, offset) \ - QREG_##name =3D tcg_global_mem_new_i32(cpu_env, \ + QREG_##name =3D tcg_global_mem_new_i32(tcg_env, \ offsetof(CPUM68KState, offset), #name); #define DEFO64(name, offset) \ - QREG_##name =3D tcg_global_mem_new_i64(cpu_env, \ + QREG_##name =3D tcg_global_mem_new_i64(tcg_env, \ offsetof(CPUM68KState, offset), #name); #include "qregs.h.inc" #undef DEFO32 #undef DEFO64 =20 - cpu_halted =3D tcg_global_mem_new_i32(cpu_env, + cpu_halted =3D tcg_global_mem_new_i32(tcg_env, -offsetof(M68kCPU, env) + offsetof(CPUState, halted), "HALTE= D"); - cpu_exception_index =3D tcg_global_mem_new_i32(cpu_env, + cpu_exception_index =3D tcg_global_mem_new_i32(tcg_env, -offsetof(M68kCPU, env) + offsetof(CPUState, except= ion_index), "EXCEPTION"); @@ -90,23 +90,23 @@ void m68k_tcg_init(void) p =3D cpu_reg_names; for (i =3D 0; i < 8; i++) { sprintf(p, "D%d", i); - cpu_dregs[i] =3D tcg_global_mem_new(cpu_env, + cpu_dregs[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUM68KState, dregs[i])= , p); p +=3D 3; sprintf(p, "A%d", i); - cpu_aregs[i] =3D tcg_global_mem_new(cpu_env, + cpu_aregs[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUM68KState, aregs[i])= , p); p +=3D 3; } for (i =3D 0; i < 4; i++) { sprintf(p, "ACC%d", i); - cpu_macc[i] =3D tcg_global_mem_new_i64(cpu_env, + cpu_macc[i] =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUM68KState, macc[i]), = p); p +=3D 5; } =20 - NULL_QREG =3D tcg_global_mem_new(cpu_env, -4, "NULL"); - store_dummy =3D tcg_global_mem_new(cpu_env, -8, "NULL"); + NULL_QREG =3D tcg_global_mem_new(tcg_env, -4, "NULL"); + store_dummy =3D tcg_global_mem_new(tcg_env, -8, "NULL"); } =20 /* internal defines */ @@ -264,7 +264,7 @@ static void gen_jmp(DisasContext *s, TCGv dest) =20 static void gen_raise_exception(int nr) { - gen_helper_raise_exception(cpu_env, tcg_constant_i32(nr)); + gen_helper_raise_exception(tcg_env, tcg_constant_i32(nr)); } =20 static void gen_raise_exception_format2(DisasContext *s, int nr, @@ -276,7 +276,7 @@ static void gen_raise_exception_format2(DisasContext *s= , int nr, * Re-use mmu.ar for the purpose, since that's only valid * after tlb_fill. */ - tcg_gen_st_i32(tcg_constant_i32(this_pc), cpu_env, + tcg_gen_st_i32(tcg_constant_i32(this_pc), tcg_env, offsetof(CPUM68KState, mmu.ar)); gen_raise_exception(nr); s->base.is_jmp =3D DISAS_NORETURN; @@ -602,12 +602,12 @@ static void gen_flush_flags(DisasContext *s) break; =20 case CC_OP_DYNAMIC: - gen_helper_flush_flags(cpu_env, QREG_CC_OP); + gen_helper_flush_flags(tcg_env, QREG_CC_OP); s->cc_op_synced =3D 1; break; =20 default: - gen_helper_flush_flags(cpu_env, tcg_constant_i32(s->cc_op)); + gen_helper_flush_flags(tcg_env, tcg_constant_i32(s->cc_op)); s->cc_op_synced =3D 1; break; } @@ -916,14 +916,14 @@ static TCGv gen_ea(CPUM68KState *env, DisasContext *s= , uint16_t insn, static TCGv_ptr gen_fp_ptr(int freg) { TCGv_ptr fp =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fregs[freg])); + tcg_gen_addi_ptr(fp, tcg_env, offsetof(CPUM68KState, fregs[freg])); return fp; } =20 static TCGv_ptr gen_fp_result_ptr(void) { TCGv_ptr fp =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(fp, cpu_env, offsetof(CPUM68KState, fp_result)); + tcg_gen_addi_ptr(fp, tcg_env, offsetof(CPUM68KState, fp_result)); return fp; } =20 @@ -954,15 +954,15 @@ static void gen_load_fp(DisasContext *s, int opsize, = TCGv addr, TCGv_ptr fp, case OS_WORD: case OS_LONG: tcg_gen_qemu_ld_tl(tmp, addr, index, opsize | MO_SIGN | MO_TE); - gen_helper_exts32(cpu_env, fp, tmp); + gen_helper_exts32(tcg_env, fp, tmp); break; case OS_SINGLE: tcg_gen_qemu_ld_tl(tmp, addr, index, MO_TEUL); - gen_helper_extf32(cpu_env, fp, tmp); + gen_helper_extf32(tcg_env, fp, tmp); break; case OS_DOUBLE: tcg_gen_qemu_ld_i64(t64, addr, index, MO_TEUQ); - gen_helper_extf64(cpu_env, fp, t64); + gen_helper_extf64(tcg_env, fp, t64); break; case OS_EXTENDED: if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) { @@ -1000,15 +1000,15 @@ static void gen_store_fp(DisasContext *s, int opsiz= e, TCGv addr, TCGv_ptr fp, case OS_BYTE: case OS_WORD: case OS_LONG: - gen_helper_reds32(tmp, cpu_env, fp); + gen_helper_reds32(tmp, tcg_env, fp); tcg_gen_qemu_st_tl(tmp, addr, index, opsize | MO_TE); break; case OS_SINGLE: - gen_helper_redf32(tmp, cpu_env, fp); + gen_helper_redf32(tmp, tcg_env, fp); tcg_gen_qemu_st_tl(tmp, addr, index, MO_TEUL); break; case OS_DOUBLE: - gen_helper_redf64(t64, cpu_env, fp); + gen_helper_redf64(t64, tcg_env, fp); tcg_gen_qemu_st_i64(t64, addr, index, MO_TEUQ); break; case OS_EXTENDED: @@ -1060,10 +1060,10 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasC= ontext *s, int mode, case OS_BYTE: case OS_WORD: case OS_LONG: - gen_helper_reds32(reg, cpu_env, fp); + gen_helper_reds32(reg, tcg_env, fp); break; case OS_SINGLE: - gen_helper_redf32(reg, cpu_env, fp); + gen_helper_redf32(reg, tcg_env, fp); break; default: g_assert_not_reached(); @@ -1073,17 +1073,17 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasC= ontext *s, int mode, switch (opsize) { case OS_BYTE: tcg_gen_ext8s_i32(tmp, reg); - gen_helper_exts32(cpu_env, fp, tmp); + gen_helper_exts32(tcg_env, fp, tmp); break; case OS_WORD: tcg_gen_ext16s_i32(tmp, reg); - gen_helper_exts32(cpu_env, fp, tmp); + gen_helper_exts32(tcg_env, fp, tmp); break; case OS_LONG: - gen_helper_exts32(cpu_env, fp, reg); + gen_helper_exts32(tcg_env, fp, reg); break; case OS_SINGLE: - gen_helper_extf32(cpu_env, fp, reg); + gen_helper_extf32(tcg_env, fp, reg); break; default: g_assert_not_reached(); @@ -1132,23 +1132,23 @@ static int gen_ea_mode_fp(CPUM68KState *env, DisasC= ontext *s, int mode, switch (opsize) { case OS_BYTE: tmp =3D tcg_constant_i32((int8_t)read_im8(env, s)); - gen_helper_exts32(cpu_env, fp, tmp); + gen_helper_exts32(tcg_env, fp, tmp); break; case OS_WORD: tmp =3D tcg_constant_i32((int16_t)read_im16(env, s)); - gen_helper_exts32(cpu_env, fp, tmp); + gen_helper_exts32(tcg_env, fp, tmp); break; case OS_LONG: tmp =3D tcg_constant_i32(read_im32(env, s)); - gen_helper_exts32(cpu_env, fp, tmp); + gen_helper_exts32(tcg_env, fp, tmp); break; case OS_SINGLE: tmp =3D tcg_constant_i32(read_im32(env, s)); - gen_helper_extf32(cpu_env, fp, tmp); + gen_helper_extf32(tcg_env, fp, tmp); break; case OS_DOUBLE: t64 =3D tcg_constant_i64(read_im64(env, s)); - gen_helper_extf64(cpu_env, fp, t64); + gen_helper_extf64(tcg_env, fp, t64); break; case OS_EXTENDED: if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) { @@ -1516,9 +1516,9 @@ DISAS_INSN(divw) destr =3D tcg_constant_i32(REG(insn, 9)); ilen =3D tcg_constant_i32(s->pc - s->base.pc_next); if (sign) { - gen_helper_divsw(cpu_env, destr, src, ilen); + gen_helper_divsw(tcg_env, destr, src, ilen); } else { - gen_helper_divuw(cpu_env, destr, src, ilen); + gen_helper_divuw(tcg_env, destr, src, ilen); } =20 set_cc_op(s, CC_OP_FLAGS); @@ -1547,9 +1547,9 @@ DISAS_INSN(divl) reg =3D tcg_constant_i32(REG(ext, 0)); ilen =3D tcg_constant_i32(s->pc - s->base.pc_next); if (sign) { - gen_helper_divsll(cpu_env, num, reg, den, ilen); + gen_helper_divsll(tcg_env, num, reg, den, ilen); } else { - gen_helper_divull(cpu_env, num, reg, den, ilen); + gen_helper_divull(tcg_env, num, reg, den, ilen); } set_cc_op(s, CC_OP_FLAGS); return; @@ -1563,9 +1563,9 @@ DISAS_INSN(divl) reg =3D tcg_constant_i32(REG(ext, 0)); ilen =3D tcg_constant_i32(s->pc - s->base.pc_next); if (sign) { - gen_helper_divsl(cpu_env, num, reg, den, ilen); + gen_helper_divsl(tcg_env, num, reg, den, ilen); } else { - gen_helper_divul(cpu_env, num, reg, den, ilen); + gen_helper_divul(tcg_env, num, reg, den, ilen); } =20 set_cc_op(s, CC_OP_FLAGS); @@ -2126,7 +2126,7 @@ static TCGv gen_get_ccr(DisasContext *s) =20 update_cc_op(s); dest =3D tcg_temp_new(); - gen_helper_get_ccr(dest, cpu_env); + gen_helper_get_ccr(dest, tcg_env); return dest; } =20 @@ -2153,7 +2153,7 @@ static void gen_set_sr_im(DisasContext *s, uint16_t v= al, int ccr_only) } else { /* Must writeback before changing security state. */ do_writebacks(s); - gen_helper_set_sr(cpu_env, tcg_constant_i32(val)); + gen_helper_set_sr(tcg_env, tcg_constant_i32(val)); } set_cc_op(s, CC_OP_FLAGS); } @@ -2161,11 +2161,11 @@ static void gen_set_sr_im(DisasContext *s, uint16_t= val, int ccr_only) static void gen_set_sr(DisasContext *s, TCGv val, int ccr_only) { if (ccr_only) { - gen_helper_set_ccr(cpu_env, val); + gen_helper_set_ccr(tcg_env, val); } else { /* Must writeback before changing security state. */ do_writebacks(s); - gen_helper_set_sr(cpu_env, val); + gen_helper_set_sr(tcg_env, val); } set_cc_op(s, CC_OP_FLAGS); } @@ -2388,13 +2388,13 @@ DISAS_INSN(cas2w) */ =20 if (tb_cflags(s->base.tb) & CF_PARALLEL) { - gen_helper_exit_atomic(cpu_env); + gen_helper_exit_atomic(tcg_env); } else { TCGv regs =3D tcg_constant_i32(REG(ext2, 6) | (REG(ext1, 6) << 3) | (REG(ext2, 0) << 6) | (REG(ext1, 0) << 9)); - gen_helper_cas2w(cpu_env, regs, addr1, addr2); + gen_helper_cas2w(tcg_env, regs, addr1, addr2); } =20 /* Note that cas2w also assigned to env->cc_op. */ @@ -2442,9 +2442,9 @@ DISAS_INSN(cas2l) (REG(ext2, 0) << 6) | (REG(ext1, 0) << 9)); if (tb_cflags(s->base.tb) & CF_PARALLEL) { - gen_helper_cas2l_parallel(cpu_env, regs, addr1, addr2); + gen_helper_cas2l_parallel(tcg_env, regs, addr1, addr2); } else { - gen_helper_cas2l(cpu_env, regs, addr1, addr2); + gen_helper_cas2l(tcg_env, regs, addr1, addr2); } =20 /* Note that cas2l also assigned to env->cc_op. */ @@ -2837,7 +2837,7 @@ DISAS_INSN(reset) return; } =20 - gen_helper_reset(cpu_env); + gen_helper_reset(tcg_env); } #endif =20 @@ -3971,11 +3971,11 @@ DISAS_INSN(bfext_mem) } =20 if (is_sign) { - gen_helper_bfexts_mem(dest, cpu_env, addr, ofs, len); + gen_helper_bfexts_mem(dest, tcg_env, addr, ofs, len); tcg_gen_mov_i32(QREG_CC_N, dest); } else { TCGv_i64 tmp =3D tcg_temp_new_i64(); - gen_helper_bfextu_mem(tmp, cpu_env, addr, ofs, len); + gen_helper_bfextu_mem(tmp, tcg_env, addr, ofs, len); tcg_gen_extr_i64_i32(dest, QREG_CC_N, tmp); } set_cc_op(s, CC_OP_LOGIC); @@ -4093,21 +4093,21 @@ DISAS_INSN(bfop_mem) =20 switch (insn & 0x0f00) { case 0x0a00: /* bfchg */ - gen_helper_bfchg_mem(QREG_CC_N, cpu_env, addr, ofs, len); + gen_helper_bfchg_mem(QREG_CC_N, tcg_env, addr, ofs, len); break; case 0x0c00: /* bfclr */ - gen_helper_bfclr_mem(QREG_CC_N, cpu_env, addr, ofs, len); + gen_helper_bfclr_mem(QREG_CC_N, tcg_env, addr, ofs, len); break; case 0x0d00: /* bfffo */ t64 =3D tcg_temp_new_i64(); - gen_helper_bfffo_mem(t64, cpu_env, addr, ofs, len); + gen_helper_bfffo_mem(t64, tcg_env, addr, ofs, len); tcg_gen_extr_i64_i32(DREG(ext, 12), QREG_CC_N, t64); break; case 0x0e00: /* bfset */ - gen_helper_bfset_mem(QREG_CC_N, cpu_env, addr, ofs, len); + gen_helper_bfset_mem(QREG_CC_N, tcg_env, addr, ofs, len); break; case 0x0800: /* bftst */ - gen_helper_bfexts_mem(QREG_CC_N, cpu_env, addr, ofs, len); + gen_helper_bfexts_mem(QREG_CC_N, tcg_env, addr, ofs, len); break; default: g_assert_not_reached(); @@ -4208,7 +4208,7 @@ DISAS_INSN(bfins_mem) ofs =3D tcg_constant_i32(extract32(ext, 6, 5)); } =20 - gen_helper_bfins_mem(QREG_CC_N, cpu_env, addr, src, ofs, len); + gen_helper_bfins_mem(QREG_CC_N, tcg_env, addr, src, ofs, len); set_cc_op(s, CC_OP_LOGIC); } =20 @@ -4243,7 +4243,7 @@ DISAS_INSN(chk) reg =3D gen_extend(s, DREG(insn, 9), opsize, 1); =20 gen_flush_flags(s); - gen_helper_chk(cpu_env, reg, src); + gen_helper_chk(tcg_env, reg, src); } =20 DISAS_INSN(chk2) @@ -4288,7 +4288,7 @@ DISAS_INSN(chk2) } =20 gen_flush_flags(s); - gen_helper_chk2(cpu_env, reg, bound1, bound2); + gen_helper_chk2(tcg_env, reg, bound1, bound2); } =20 static void m68k_copy_line(TCGv dst, TCGv src, int index) @@ -4462,7 +4462,7 @@ DISAS_INSN(move_from_usp) gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE); return; } - tcg_gen_ld_i32(AREG(insn, 0), cpu_env, + tcg_gen_ld_i32(AREG(insn, 0), tcg_env, offsetof(CPUM68KState, sp[M68K_USP])); } =20 @@ -4472,7 +4472,7 @@ DISAS_INSN(move_to_usp) gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE); return; } - tcg_gen_st_i32(AREG(insn, 0), cpu_env, + tcg_gen_st_i32(AREG(insn, 0), tcg_env, offsetof(CPUM68KState, sp[M68K_USP])); } =20 @@ -4528,7 +4528,7 @@ DISAS_INSN(cf_movec) } else { reg =3D DREG(ext, 12); } - gen_helper_cf_movec_to(cpu_env, tcg_constant_i32(ext & 0xfff), reg); + gen_helper_cf_movec_to(tcg_env, tcg_constant_i32(ext & 0xfff), reg); gen_exit_tb(s); } =20 @@ -4551,9 +4551,9 @@ DISAS_INSN(m68k_movec) } creg =3D tcg_constant_i32(ext & 0xfff); if (insn & 1) { - gen_helper_m68k_movec_to(cpu_env, creg, reg); + gen_helper_m68k_movec_to(tcg_env, creg, reg); } else { - gen_helper_m68k_movec_from(reg, cpu_env, creg); + gen_helper_m68k_movec_from(reg, tcg_env, creg); } gen_exit_tb(s); } @@ -4605,7 +4605,7 @@ DISAS_INSN(pflush) } =20 opmode =3D tcg_constant_i32((insn >> 3) & 3); - gen_helper_pflush(cpu_env, AREG(insn, 0), opmode); + gen_helper_pflush(tcg_env, AREG(insn, 0), opmode); } =20 DISAS_INSN(ptest) @@ -4617,7 +4617,7 @@ DISAS_INSN(ptest) return; } is_read =3D tcg_constant_i32((insn >> 5) & 1); - gen_helper_ptest(cpu_env, AREG(insn, 0), is_read); + gen_helper_ptest(tcg_env, AREG(insn, 0), is_read); } #endif =20 @@ -4703,10 +4703,10 @@ static void gen_load_fcr(DisasContext *s, TCGv res,= int reg) tcg_gen_movi_i32(res, 0); break; case M68K_FPSR: - tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpsr)); + tcg_gen_ld_i32(res, tcg_env, offsetof(CPUM68KState, fpsr)); break; case M68K_FPCR: - tcg_gen_ld_i32(res, cpu_env, offsetof(CPUM68KState, fpcr)); + tcg_gen_ld_i32(res, tcg_env, offsetof(CPUM68KState, fpcr)); break; } } @@ -4717,10 +4717,10 @@ static void gen_store_fcr(DisasContext *s, TCGv val= , int reg) case M68K_FPIAR: break; case M68K_FPSR: - tcg_gen_st_i32(val, cpu_env, offsetof(CPUM68KState, fpsr)); + tcg_gen_st_i32(val, tcg_env, offsetof(CPUM68KState, fpsr)); break; case M68K_FPCR: - gen_helper_set_fpcr(cpu_env, val); + gen_helper_set_fpcr(tcg_env, val); break; } } @@ -4877,23 +4877,23 @@ static void gen_op_fmovem(CPUM68KState *env, DisasC= ontext *s, * only available to store register to memory */ if (opsize =3D=3D OS_EXTENDED) { - gen_helper_fmovemx_st_predec(tmp, cpu_env, addr, tmp); + gen_helper_fmovemx_st_predec(tmp, tcg_env, addr, tmp); } else { - gen_helper_fmovemd_st_predec(tmp, cpu_env, addr, tmp); + gen_helper_fmovemd_st_predec(tmp, tcg_env, addr, tmp); } } else { /* postincrement addressing mode */ if (opsize =3D=3D OS_EXTENDED) { if (is_load) { - gen_helper_fmovemx_ld_postinc(tmp, cpu_env, addr, tmp); + gen_helper_fmovemx_ld_postinc(tmp, tcg_env, addr, tmp); } else { - gen_helper_fmovemx_st_postinc(tmp, cpu_env, addr, tmp); + gen_helper_fmovemx_st_postinc(tmp, tcg_env, addr, tmp); } } else { if (is_load) { - gen_helper_fmovemd_ld_postinc(tmp, cpu_env, addr, tmp); + gen_helper_fmovemd_ld_postinc(tmp, tcg_env, addr, tmp); } else { - gen_helper_fmovemd_st_postinc(tmp, cpu_env, addr, tmp); + gen_helper_fmovemd_st_postinc(tmp, tcg_env, addr, tmp); } } } @@ -4925,7 +4925,7 @@ DISAS_INSN(fpu) /* fmovecr */ TCGv rom_offset =3D tcg_constant_i32(opmode); cpu_dest =3D gen_fp_ptr(REG(ext, 7)); - gen_helper_fconst(cpu_env, cpu_dest, rom_offset); + gen_helper_fconst(tcg_env, cpu_dest, rom_offset); return; } break; @@ -4936,7 +4936,7 @@ DISAS_INSN(fpu) EA_STORE, IS_USER(s)) =3D=3D -1) { gen_addr_fault(s); } - gen_helper_ftst(cpu_env, cpu_src); + gen_helper_ftst(tcg_env, cpu_src); return; case 4: /* fmove to control register. */ case 5: /* fmove from control register. */ @@ -4970,172 +4970,172 @@ DISAS_INSN(fpu) gen_fp_move(cpu_dest, cpu_src); break; case 0x40: /* fsmove */ - gen_helper_fsround(cpu_env, cpu_dest, cpu_src); + gen_helper_fsround(tcg_env, cpu_dest, cpu_src); break; case 0x44: /* fdmove */ - gen_helper_fdround(cpu_env, cpu_dest, cpu_src); + gen_helper_fdround(tcg_env, cpu_dest, cpu_src); break; case 1: /* fint */ - gen_helper_firound(cpu_env, cpu_dest, cpu_src); + gen_helper_firound(tcg_env, cpu_dest, cpu_src); break; case 2: /* fsinh */ - gen_helper_fsinh(cpu_env, cpu_dest, cpu_src); + gen_helper_fsinh(tcg_env, cpu_dest, cpu_src); break; case 3: /* fintrz */ - gen_helper_fitrunc(cpu_env, cpu_dest, cpu_src); + gen_helper_fitrunc(tcg_env, cpu_dest, cpu_src); break; case 4: /* fsqrt */ - gen_helper_fsqrt(cpu_env, cpu_dest, cpu_src); + gen_helper_fsqrt(tcg_env, cpu_dest, cpu_src); break; case 0x41: /* fssqrt */ - gen_helper_fssqrt(cpu_env, cpu_dest, cpu_src); + gen_helper_fssqrt(tcg_env, cpu_dest, cpu_src); break; case 0x45: /* fdsqrt */ - gen_helper_fdsqrt(cpu_env, cpu_dest, cpu_src); + gen_helper_fdsqrt(tcg_env, cpu_dest, cpu_src); break; case 0x06: /* flognp1 */ - gen_helper_flognp1(cpu_env, cpu_dest, cpu_src); + gen_helper_flognp1(tcg_env, cpu_dest, cpu_src); break; case 0x08: /* fetoxm1 */ - gen_helper_fetoxm1(cpu_env, cpu_dest, cpu_src); + gen_helper_fetoxm1(tcg_env, cpu_dest, cpu_src); break; case 0x09: /* ftanh */ - gen_helper_ftanh(cpu_env, cpu_dest, cpu_src); + gen_helper_ftanh(tcg_env, cpu_dest, cpu_src); break; case 0x0a: /* fatan */ - gen_helper_fatan(cpu_env, cpu_dest, cpu_src); + gen_helper_fatan(tcg_env, cpu_dest, cpu_src); break; case 0x0c: /* fasin */ - gen_helper_fasin(cpu_env, cpu_dest, cpu_src); + gen_helper_fasin(tcg_env, cpu_dest, cpu_src); break; case 0x0d: /* fatanh */ - gen_helper_fatanh(cpu_env, cpu_dest, cpu_src); + gen_helper_fatanh(tcg_env, cpu_dest, cpu_src); break; case 0x0e: /* fsin */ - gen_helper_fsin(cpu_env, cpu_dest, cpu_src); + gen_helper_fsin(tcg_env, cpu_dest, cpu_src); break; case 0x0f: /* ftan */ - gen_helper_ftan(cpu_env, cpu_dest, cpu_src); + gen_helper_ftan(tcg_env, cpu_dest, cpu_src); break; case 0x10: /* fetox */ - gen_helper_fetox(cpu_env, cpu_dest, cpu_src); + gen_helper_fetox(tcg_env, cpu_dest, cpu_src); break; case 0x11: /* ftwotox */ - gen_helper_ftwotox(cpu_env, cpu_dest, cpu_src); + gen_helper_ftwotox(tcg_env, cpu_dest, cpu_src); break; case 0x12: /* ftentox */ - gen_helper_ftentox(cpu_env, cpu_dest, cpu_src); + gen_helper_ftentox(tcg_env, cpu_dest, cpu_src); break; case 0x14: /* flogn */ - gen_helper_flogn(cpu_env, cpu_dest, cpu_src); + gen_helper_flogn(tcg_env, cpu_dest, cpu_src); break; case 0x15: /* flog10 */ - gen_helper_flog10(cpu_env, cpu_dest, cpu_src); + gen_helper_flog10(tcg_env, cpu_dest, cpu_src); break; case 0x16: /* flog2 */ - gen_helper_flog2(cpu_env, cpu_dest, cpu_src); + gen_helper_flog2(tcg_env, cpu_dest, cpu_src); break; case 0x18: /* fabs */ - gen_helper_fabs(cpu_env, cpu_dest, cpu_src); + gen_helper_fabs(tcg_env, cpu_dest, cpu_src); break; case 0x58: /* fsabs */ - gen_helper_fsabs(cpu_env, cpu_dest, cpu_src); + gen_helper_fsabs(tcg_env, cpu_dest, cpu_src); break; case 0x5c: /* fdabs */ - gen_helper_fdabs(cpu_env, cpu_dest, cpu_src); + gen_helper_fdabs(tcg_env, cpu_dest, cpu_src); break; case 0x19: /* fcosh */ - gen_helper_fcosh(cpu_env, cpu_dest, cpu_src); + gen_helper_fcosh(tcg_env, cpu_dest, cpu_src); break; case 0x1a: /* fneg */ - gen_helper_fneg(cpu_env, cpu_dest, cpu_src); + gen_helper_fneg(tcg_env, cpu_dest, cpu_src); break; case 0x5a: /* fsneg */ - gen_helper_fsneg(cpu_env, cpu_dest, cpu_src); + gen_helper_fsneg(tcg_env, cpu_dest, cpu_src); break; case 0x5e: /* fdneg */ - gen_helper_fdneg(cpu_env, cpu_dest, cpu_src); + gen_helper_fdneg(tcg_env, cpu_dest, cpu_src); break; case 0x1c: /* facos */ - gen_helper_facos(cpu_env, cpu_dest, cpu_src); + gen_helper_facos(tcg_env, cpu_dest, cpu_src); break; case 0x1d: /* fcos */ - gen_helper_fcos(cpu_env, cpu_dest, cpu_src); + gen_helper_fcos(tcg_env, cpu_dest, cpu_src); break; case 0x1e: /* fgetexp */ - gen_helper_fgetexp(cpu_env, cpu_dest, cpu_src); + gen_helper_fgetexp(tcg_env, cpu_dest, cpu_src); break; case 0x1f: /* fgetman */ - gen_helper_fgetman(cpu_env, cpu_dest, cpu_src); + gen_helper_fgetman(tcg_env, cpu_dest, cpu_src); break; case 0x20: /* fdiv */ - gen_helper_fdiv(cpu_env, cpu_dest, cpu_src, cpu_dest); + gen_helper_fdiv(tcg_env, cpu_dest, cpu_src, cpu_dest); break; case 0x60: /* fsdiv */ - gen_helper_fsdiv(cpu_env, cpu_dest, cpu_src, cpu_dest); + gen_helper_fsdiv(tcg_env, cpu_dest, cpu_src, cpu_dest); break; case 0x64: /* fddiv */ - gen_helper_fddiv(cpu_env, cpu_dest, cpu_src, cpu_dest); + gen_helper_fddiv(tcg_env, cpu_dest, cpu_src, cpu_dest); break; case 0x21: /* fmod */ - gen_helper_fmod(cpu_env, cpu_dest, cpu_src, cpu_dest); + gen_helper_fmod(tcg_env, cpu_dest, cpu_src, cpu_dest); break; case 0x22: /* fadd */ - gen_helper_fadd(cpu_env, cpu_dest, cpu_src, cpu_dest); + gen_helper_fadd(tcg_env, cpu_dest, cpu_src, cpu_dest); break; case 0x62: /* fsadd */ - gen_helper_fsadd(cpu_env, cpu_dest, cpu_src, cpu_dest); + gen_helper_fsadd(tcg_env, cpu_dest, cpu_src, cpu_dest); break; case 0x66: /* fdadd */ - gen_helper_fdadd(cpu_env, cpu_dest, cpu_src, cpu_dest); + gen_helper_fdadd(tcg_env, cpu_dest, cpu_src, cpu_dest); break; case 0x23: /* fmul */ - gen_helper_fmul(cpu_env, cpu_dest, cpu_src, cpu_dest); + gen_helper_fmul(tcg_env, cpu_dest, cpu_src, cpu_dest); break; case 0x63: /* fsmul */ - gen_helper_fsmul(cpu_env, cpu_dest, cpu_src, cpu_dest); + gen_helper_fsmul(tcg_env, cpu_dest, cpu_src, cpu_dest); break; case 0x67: /* fdmul */ - gen_helper_fdmul(cpu_env, cpu_dest, cpu_src, cpu_dest); + gen_helper_fdmul(tcg_env, cpu_dest, cpu_src, cpu_dest); break; case 0x24: /* fsgldiv */ - gen_helper_fsgldiv(cpu_env, cpu_dest, cpu_src, cpu_dest); + gen_helper_fsgldiv(tcg_env, cpu_dest, cpu_src, cpu_dest); break; case 0x25: /* frem */ - gen_helper_frem(cpu_env, cpu_dest, cpu_src, cpu_dest); + gen_helper_frem(tcg_env, cpu_dest, cpu_src, cpu_dest); break; case 0x26: /* fscale */ - gen_helper_fscale(cpu_env, cpu_dest, cpu_src, cpu_dest); + gen_helper_fscale(tcg_env, cpu_dest, cpu_src, cpu_dest); break; case 0x27: /* fsglmul */ - gen_helper_fsglmul(cpu_env, cpu_dest, cpu_src, cpu_dest); + gen_helper_fsglmul(tcg_env, cpu_dest, cpu_src, cpu_dest); break; case 0x28: /* fsub */ - gen_helper_fsub(cpu_env, cpu_dest, cpu_src, cpu_dest); + gen_helper_fsub(tcg_env, cpu_dest, cpu_src, cpu_dest); break; case 0x68: /* fssub */ - gen_helper_fssub(cpu_env, cpu_dest, cpu_src, cpu_dest); + gen_helper_fssub(tcg_env, cpu_dest, cpu_src, cpu_dest); break; case 0x6c: /* fdsub */ - gen_helper_fdsub(cpu_env, cpu_dest, cpu_src, cpu_dest); + gen_helper_fdsub(tcg_env, cpu_dest, cpu_src, cpu_dest); break; case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37: { TCGv_ptr cpu_dest2 =3D gen_fp_ptr(REG(ext, 0)); - gen_helper_fsincos(cpu_env, cpu_dest, cpu_dest2, cpu_src); + gen_helper_fsincos(tcg_env, cpu_dest, cpu_dest2, cpu_src); } break; case 0x38: /* fcmp */ - gen_helper_fcmp(cpu_env, cpu_src, cpu_dest); + gen_helper_fcmp(tcg_env, cpu_src, cpu_dest); return; case 0x3a: /* ftst */ - gen_helper_ftst(cpu_env, cpu_src); + gen_helper_ftst(tcg_env, cpu_src); return; default: goto undef; } - gen_helper_ftst(cpu_env, cpu_dest); + gen_helper_ftst(tcg_env, cpu_dest); return; undef: /* FIXME: Is this right for offset addressing modes? */ @@ -5466,12 +5466,12 @@ DISAS_INSN(mac) ry =3D gen_mac_extract_word(s, ry, (ext & 0x40) !=3D 0); } if (s->env->macsr & MACSR_FI) { - gen_helper_macmulf(s->mactmp, cpu_env, rx, ry); + gen_helper_macmulf(s->mactmp, tcg_env, rx, ry); } else { if (s->env->macsr & MACSR_SU) - gen_helper_macmuls(s->mactmp, cpu_env, rx, ry); + gen_helper_macmuls(s->mactmp, tcg_env, rx, ry); else - gen_helper_macmulu(s->mactmp, cpu_env, rx, ry); + gen_helper_macmulu(s->mactmp, tcg_env, rx, ry); switch ((ext >> 9) & 3) { case 1: tcg_gen_shli_i64(s->mactmp, s->mactmp, 1); @@ -5507,11 +5507,11 @@ DISAS_INSN(mac) tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); =20 if (s->env->macsr & MACSR_FI) - gen_helper_macsatf(cpu_env, tcg_constant_i32(acc)); + gen_helper_macsatf(tcg_env, tcg_constant_i32(acc)); else if (s->env->macsr & MACSR_SU) - gen_helper_macsats(cpu_env, tcg_constant_i32(acc)); + gen_helper_macsats(tcg_env, tcg_constant_i32(acc)); else - gen_helper_macsatu(cpu_env, tcg_constant_i32(acc)); + gen_helper_macsatu(tcg_env, tcg_constant_i32(acc)); =20 #if 0 /* Disabled because conditional branches clobber temporary vars. */ @@ -5539,18 +5539,18 @@ DISAS_INSN(mac) else tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp); if (s->env->macsr & MACSR_FI) - gen_helper_macsatf(cpu_env, tcg_constant_i32(acc)); + gen_helper_macsatf(tcg_env, tcg_constant_i32(acc)); else if (s->env->macsr & MACSR_SU) - gen_helper_macsats(cpu_env, tcg_constant_i32(acc)); + gen_helper_macsats(tcg_env, tcg_constant_i32(acc)); else - gen_helper_macsatu(cpu_env, tcg_constant_i32(acc)); + gen_helper_macsatu(tcg_env, tcg_constant_i32(acc)); #if 0 /* Disabled because conditional branches clobber temporary vars. = */ if (l1 !=3D -1) gen_set_label(l1); #endif } - gen_helper_mac_set_flags(cpu_env, tcg_constant_i32(acc)); + gen_helper_mac_set_flags(tcg_env, tcg_constant_i32(acc)); =20 if (insn & 0x30) { TCGv rw; @@ -5580,7 +5580,7 @@ DISAS_INSN(from_mac) accnum =3D (insn >> 9) & 3; acc =3D MACREG(accnum); if (s->env->macsr & MACSR_FI) { - gen_helper_get_macf(rx, cpu_env, acc); + gen_helper_get_macf(rx, tcg_env, acc); } else if ((s->env->macsr & MACSR_OMC) =3D=3D 0) { tcg_gen_extrl_i64_i32(rx, acc); } else if (s->env->macsr & MACSR_SU) { @@ -5601,9 +5601,9 @@ DISAS_INSN(move_mac) TCGv dest; src =3D insn & 3; dest =3D tcg_constant_i32((insn >> 9) & 3); - gen_helper_mac_move(cpu_env, dest, tcg_constant_i32(src)); + gen_helper_mac_move(tcg_env, dest, tcg_constant_i32(src)); gen_mac_clear_flags(); - gen_helper_mac_set_flags(cpu_env, dest); + gen_helper_mac_set_flags(tcg_env, dest); } =20 DISAS_INSN(from_macsr) @@ -5628,9 +5628,9 @@ DISAS_INSN(from_mext) reg =3D (insn & 8) ? AREG(insn, 0) : DREG(insn, 0); acc =3D tcg_constant_i32((insn & 0x400) ? 2 : 0); if (s->env->macsr & MACSR_FI) - gen_helper_get_mac_extf(reg, cpu_env, acc); + gen_helper_get_mac_extf(reg, tcg_env, acc); else - gen_helper_get_mac_exti(reg, cpu_env, acc); + gen_helper_get_mac_exti(reg, tcg_env, acc); } =20 DISAS_INSN(macsr_to_ccr) @@ -5639,7 +5639,7 @@ DISAS_INSN(macsr_to_ccr) =20 /* Note that X and C are always cleared. */ tcg_gen_andi_i32(tmp, QREG_MACSR, CCF_N | CCF_Z | CCF_V); - gen_helper_set_ccr(cpu_env, tmp); + gen_helper_set_ccr(tcg_env, tmp); set_cc_op(s, CC_OP_FLAGS); } =20 @@ -5661,14 +5661,14 @@ DISAS_INSN(to_mac) } tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum)); gen_mac_clear_flags(); - gen_helper_mac_set_flags(cpu_env, tcg_constant_i32(accnum)); + gen_helper_mac_set_flags(tcg_env, tcg_constant_i32(accnum)); } =20 DISAS_INSN(to_macsr) { TCGv val; SRC_EA(env, val, OS_LONG, 0, NULL); - gen_helper_set_macsr(cpu_env, val); + gen_helper_set_macsr(tcg_env, val); gen_exit_tb(s); } =20 @@ -5686,11 +5686,11 @@ DISAS_INSN(to_mext) SRC_EA(env, val, OS_LONG, 0, NULL); acc =3D tcg_constant_i32((insn & 0x400) ? 2 : 0); if (s->env->macsr & MACSR_FI) - gen_helper_set_mac_extf(cpu_env, val, acc); + gen_helper_set_mac_extf(tcg_env, val, acc); else if (s->env->macsr & MACSR_SU) - gen_helper_set_mac_exts(cpu_env, val, acc); + gen_helper_set_mac_exts(tcg_env, val, acc); else - gen_helper_set_mac_extu(cpu_env, val, acc); + gen_helper_set_mac_extu(tcg_env, val, acc); } =20 static disas_proc opcode_table[65536]; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index d02c16296a..bb178219f1 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -102,7 +102,7 @@ static void t_sync_flags(DisasContext *dc) =20 static void gen_raise_exception(DisasContext *dc, uint32_t index) { - gen_helper_raise_exception(cpu_env, tcg_constant_i32(index)); + gen_helper_raise_exception(tcg_env, tcg_constant_i32(index)); dc->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -116,7 +116,7 @@ static void gen_raise_exception_sync(DisasContext *dc, = uint32_t index) static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec) { TCGv_i32 tmp =3D tcg_constant_i32(esr_ec); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, esr)); + tcg_gen_st_i32(tmp, tcg_env, offsetof(CPUMBState, esr)); =20 gen_raise_exception_sync(dc, EXCP_HW_EXCP); } @@ -295,11 +295,11 @@ static bool do_typeb_val(DisasContext *dc, arg_typeb = *arg, bool side_effects, =20 #define ENV_WRAPPER2(NAME, HELPER) \ static void NAME(TCGv_i32 out, TCGv_i32 ina) \ - { HELPER(out, cpu_env, ina); } + { HELPER(out, tcg_env, ina); } =20 #define ENV_WRAPPER3(NAME, HELPER) \ static void NAME(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) \ - { HELPER(out, cpu_env, ina, inb); } + { HELPER(out, tcg_env, ina, inb); } =20 /* No input carry, but output carry. */ static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) @@ -472,12 +472,12 @@ DO_TYPEA0_CFG(fsqrt, use_fpu >=3D 2, true, gen_fsqrt) /* Does not use ENV_WRAPPER3, because arguments are swapped as well. */ static void gen_idiv(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { - gen_helper_divs(out, cpu_env, inb, ina); + gen_helper_divs(out, tcg_env, inb, ina); } =20 static void gen_idivu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) { - gen_helper_divu(out, cpu_env, inb, ina); + gen_helper_divu(out, tcg_env, inb, ina); } =20 DO_TYPEA_CFG(idiv, use_div, true, gen_idiv) @@ -643,7 +643,7 @@ static TCGv compute_ldst_addr_typea(DisasContext *dc, i= nt ra, int rb) } =20 if ((ra =3D=3D 1 || rb =3D=3D 1) && dc->cfg->stackprot) { - gen_helper_stackprot(cpu_env, ret); + gen_helper_stackprot(tcg_env, ret); } return ret; } @@ -662,7 +662,7 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, i= nt ra, int imm) } =20 if (ra =3D=3D 1 && dc->cfg->stackprot) { - gen_helper_stackprot(cpu_env, ret); + gen_helper_stackprot(tcg_env, ret); } return ret; } @@ -1232,7 +1232,7 @@ static bool trans_mbar(DisasContext *dc, arg_mbar *ar= g) =20 t_sync_flags(dc); =20 - tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, + tcg_gen_st_i32(tcg_constant_i32(1), tcg_env, -offsetof(MicroBlazeCPU, env) +offsetof(CPUState, halted)); =20 @@ -1381,13 +1381,13 @@ static bool trans_mts(DisasContext *dc, arg_mts *ar= g) tcg_gen_andi_i32(cpu_msr, src, ~(MSR_C | MSR_CC | MSR_PVR)); break; case SR_FSR: - tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, fsr)); + tcg_gen_st_i32(src, tcg_env, offsetof(CPUMBState, fsr)); break; case 0x800: - tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, slr)); + tcg_gen_st_i32(src, tcg_env, offsetof(CPUMBState, slr)); break; case 0x802: - tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, shr)); + tcg_gen_st_i32(src, tcg_env, offsetof(CPUMBState, shr)); break; =20 case 0x1000: /* PID */ @@ -1400,7 +1400,7 @@ static bool trans_mts(DisasContext *dc, arg_mts *arg) TCGv_i32 tmp_ext =3D tcg_constant_i32(arg->e); TCGv_i32 tmp_reg =3D tcg_constant_i32(arg->rs & 7); =20 - gen_helper_mmu_write(cpu_env, tmp_ext, tmp_reg, src); + gen_helper_mmu_write(tcg_env, tmp_ext, tmp_reg, src); } break; =20 @@ -1422,7 +1422,7 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *arg) case SR_EAR: { TCGv_i64 t64 =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + tcg_gen_ld_i64(t64, tcg_env, offsetof(CPUMBState, ear)); tcg_gen_extrh_i64_i32(dest, t64); } return true; @@ -1452,27 +1452,27 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *ar= g) case SR_EAR: { TCGv_i64 t64 =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); + tcg_gen_ld_i64(t64, tcg_env, offsetof(CPUMBState, ear)); tcg_gen_extrl_i64_i32(dest, t64); } break; case SR_ESR: - tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, esr)); + tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, esr)); break; case SR_FSR: - tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, fsr)); + tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, fsr)); break; case SR_BTR: - tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, btr)); + tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, btr)); break; case SR_EDR: - tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, edr)); + tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, edr)); break; case 0x800: - tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, slr)); + tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, slr)); break; case 0x802: - tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, shr)); + tcg_gen_ld_i32(dest, tcg_env, offsetof(CPUMBState, shr)); break; =20 #ifndef CONFIG_USER_ONLY @@ -1486,13 +1486,13 @@ static bool trans_mfs(DisasContext *dc, arg_mfs *ar= g) TCGv_i32 tmp_ext =3D tcg_constant_i32(arg->e); TCGv_i32 tmp_reg =3D tcg_constant_i32(arg->rs & 7); =20 - gen_helper_mmu_read(dest, cpu_env, tmp_ext, tmp_reg); + gen_helper_mmu_read(dest, tcg_env, tmp_ext, tmp_reg); } break; #endif =20 case 0x2000 ... 0x200c: - tcg_gen_ld_i32(dest, cpu_env, + tcg_gen_ld_i32(dest, tcg_env, offsetof(MicroBlazeCPU, cfg.pvr_regs[arg->rs - 0x20= 00]) - offsetof(MicroBlazeCPU, env)); break; @@ -1882,9 +1882,9 @@ void mb_tcg_init(void) =20 for (int i =3D 0; i < ARRAY_SIZE(i32s); ++i) { *i32s[i].var =3D - tcg_global_mem_new_i32(cpu_env, i32s[i].ofs, i32s[i].name); + tcg_global_mem_new_i32(tcg_env, i32s[i].ofs, i32s[i].name); } =20 cpu_res_addr =3D - tcg_global_mem_new(cpu_env, offsetof(CPUMBState, res_addr), "res_a= ddr"); + tcg_global_mem_new(tcg_env, offsetof(CPUMBState, res_addr), "res_a= ddr"); } diff --git a/target/mips/tcg/lcsr_translate.c b/target/mips/tcg/lcsr_transl= ate.c index 9f2a5f4a37..352b0f4328 100644 --- a/target/mips/tcg/lcsr_translate.c +++ b/target/mips/tcg/lcsr_translate.c @@ -22,7 +22,7 @@ static bool trans_CPUCFG(DisasContext *ctx, arg_CPUCFG *a) TCGv src1 =3D tcg_temp_new(); =20 gen_load_gpr(src1, a->rs); - gen_helper_lcsr_cpucfg(dest, cpu_env, src1); + gen_helper_lcsr_cpucfg(dest, tcg_env, src1); gen_store_gpr(dest, a->rd); =20 return true; @@ -37,7 +37,7 @@ static bool gen_rdcsr(DisasContext *ctx, arg_r *a, =20 check_cp0_enabled(ctx); gen_load_gpr(src1, a->rs); - func(dest, cpu_env, src1); + func(dest, tcg_env, src1); gen_store_gpr(dest, a->rd); =20 return true; @@ -52,7 +52,7 @@ static bool gen_wrcsr(DisasContext *ctx, arg_r *a, check_cp0_enabled(ctx); gen_load_gpr(addr, a->rs); gen_load_gpr(val, a->rd); - func(cpu_env, addr, val); + func(tcg_env, addr, val); =20 return true; } diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index b5b66fb38a..75cf80a20e 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -140,7 +140,7 @@ void msa_translate_init(void) =20 off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); msa_wr_d[i * 2 + 1] =3D - tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1= ]); + tcg_global_mem_new_i64(tcg_env, off, msaregnames[i * 2 + 1= ]); } } =20 @@ -288,7 +288,7 @@ static bool trans_msa_i8(DisasContext *ctx, arg_msa_i *= a, return true; } =20 - gen_msa_i8(cpu_env, + gen_msa_i8(tcg_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws), tcg_constant_i32(a->sa)); @@ -314,7 +314,7 @@ static bool trans_SHF(DisasContext *ctx, arg_msa_i *a) return true; } =20 - gen_helper_msa_shf_df(cpu_env, + gen_helper_msa_shf_df(tcg_env, tcg_constant_i32(a->df), tcg_constant_i32(a->wd), tcg_constant_i32(a->ws), @@ -330,7 +330,7 @@ static bool trans_msa_i5(DisasContext *ctx, arg_msa_i *= a, return true; } =20 - gen_msa_i5(cpu_env, + gen_msa_i5(tcg_env, tcg_constant_i32(a->df), tcg_constant_i32(a->wd), tcg_constant_i32(a->ws), @@ -357,7 +357,7 @@ static bool trans_LDI(DisasContext *ctx, arg_msa_ldi *a) return true; } =20 - gen_helper_msa_ldi_df(cpu_env, + gen_helper_msa_ldi_df(tcg_env, tcg_constant_i32(a->df), tcg_constant_i32(a->wd), tcg_constant_i32(a->sa)); @@ -376,7 +376,7 @@ static bool trans_msa_bit(DisasContext *ctx, arg_msa_bi= t *a, return true; } =20 - gen_msa_bit(cpu_env, + gen_msa_bit(tcg_env, tcg_constant_i32(a->df), tcg_constant_i32(a->wd), tcg_constant_i32(a->ws), @@ -405,7 +405,7 @@ static bool trans_msa_3rf(DisasContext *ctx, arg_msa_r = *a, return true; } =20 - gen_msa_3rf(cpu_env, + gen_msa_3rf(tcg_env, tcg_constant_i32(a->df), tcg_constant_i32(a->wd), tcg_constant_i32(a->ws), @@ -425,7 +425,7 @@ static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *= a, return true; } =20 - gen_msa_3r(cpu_env, + gen_msa_3r(tcg_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws), tcg_constant_i32(a->wt)); @@ -519,7 +519,7 @@ static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm= *a) return true; } =20 - gen_helper_msa_move_v(cpu_env, + gen_helper_msa_move_v(tcg_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws)); =20 @@ -537,7 +537,7 @@ static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm= *a) telm =3D tcg_temp_new(); =20 gen_load_gpr(telm, a->ws); - gen_helper_msa_ctcmsa(cpu_env, telm, tcg_constant_i32(a->wd)); + gen_helper_msa_ctcmsa(tcg_env, telm, tcg_constant_i32(a->wd)); =20 return true; } @@ -552,7 +552,7 @@ static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm= *a) =20 telm =3D tcg_temp_new(); =20 - gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws)); + gen_helper_msa_cfcmsa(telm, tcg_env, tcg_constant_i32(a->ws)); gen_store_gpr(telm, a->wd); =20 return true; @@ -569,7 +569,7 @@ static bool trans_msa_elm(DisasContext *ctx, arg_msa_el= m_df *a, return true; } =20 - gen_msa_elm_df(cpu_env, + gen_msa_elm_df(tcg_env, tcg_constant_i32(a->df), tcg_constant_i32(a->wd), tcg_constant_i32(a->ws), @@ -593,7 +593,7 @@ static bool trans_msa_elm_fn(DisasContext *ctx, arg_msa= _elm_df *a, return true; } =20 - gen_msa_elm[a->df](cpu_env, + gen_msa_elm[a->df](tcg_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws), tcg_constant_i32(a->n)); @@ -698,7 +698,7 @@ static bool trans_msa_2r(DisasContext *ctx, arg_msa_r *= a, return true; } =20 - gen_msa_2r(cpu_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws)); + gen_msa_2r(tcg_env, tcg_constant_i32(a->wd), tcg_constant_i32(a->ws)); =20 return true; } @@ -718,7 +718,7 @@ static bool trans_FILL(DisasContext *ctx, arg_msa_r *a) return true; } =20 - gen_helper_msa_fill_df(cpu_env, + gen_helper_msa_fill_df(tcg_env, tcg_constant_i32(a->df), tcg_constant_i32(a->wd), tcg_constant_i32(a->ws)); @@ -733,7 +733,7 @@ static bool trans_msa_2rf(DisasContext *ctx, arg_msa_r = *a, return true; } =20 - gen_msa_2rf(cpu_env, + gen_msa_2rf(tcg_env, tcg_constant_i32(a->df), tcg_constant_i32(a->wd), tcg_constant_i32(a->ws)); @@ -770,7 +770,7 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i= *a, taddr =3D tcg_temp_new(); =20 gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df); - gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr); + gen_msa_ldst(tcg_env, tcg_constant_i32(a->wd), taddr); =20 return true; } diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translat= e.c index cfcd8ac9bc..c517258ac5 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -617,12 +617,12 @@ static const char mxuregnames[NUMBER_OF_MXU_REGISTERS= ][4] =3D { void mxu_translate_init(void) { for (unsigned i =3D 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { - mxu_gpr[i] =3D tcg_global_mem_new(cpu_env, + mxu_gpr[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, active_tc.m= xu_gpr[i]), mxuregnames[i]); } =20 - mxu_CR =3D tcg_global_mem_new(cpu_env, + mxu_CR =3D tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, active_tc.mxu_cr), mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); } diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 9bb40f1849..c8183710e5 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1268,12 +1268,12 @@ static inline void gen_load_srsgpr(int from, int to) TCGv_i32 t2 =3D tcg_temp_new_i32(); TCGv_ptr addr =3D tcg_temp_new_ptr(); =20 - tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl)); + tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl)); tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); tcg_gen_andi_i32(t2, t2, 0xf); tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); tcg_gen_ext_i32_ptr(addr, t2); - tcg_gen_add_ptr(addr, cpu_env, addr); + tcg_gen_add_ptr(addr, tcg_env, addr); =20 tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from); } @@ -1288,12 +1288,12 @@ static inline void gen_store_srsgpr(int from, int t= o) TCGv_ptr addr =3D tcg_temp_new_ptr(); =20 gen_load_gpr(t0, from); - tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUMIPSState, CP0_SRSCtl)); + tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl)); tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); tcg_gen_andi_i32(t2, t2, 0xf); tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); tcg_gen_ext_i32_ptr(addr, t2); - tcg_gen_add_ptr(addr, cpu_env, addr); + tcg_gen_add_ptr(addr, tcg_env, addr); =20 tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to); } @@ -1344,14 +1344,14 @@ static inline void restore_cpu_state(CPUMIPSState *= env, DisasContext *ctx) void generate_exception_err(DisasContext *ctx, int excp, int err) { save_cpu_state(ctx, 1); - gen_helper_raise_exception_err(cpu_env, tcg_constant_i32(excp), + gen_helper_raise_exception_err(tcg_env, tcg_constant_i32(excp), tcg_constant_i32(err)); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 void generate_exception(DisasContext *ctx, int excp) { - gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); + gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); } =20 void generate_exception_end(DisasContext *ctx, int excp) @@ -1363,7 +1363,7 @@ void generate_exception_break(DisasContext *ctx, int = code) { #ifdef CONFIG_USER_ONLY /* Pass the break code along to cpu_loop. */ - tcg_gen_st_i32(tcg_constant_i32(code), cpu_env, + tcg_gen_st_i32(tcg_constant_i32(code), tcg_env, offsetof(CPUMIPSState, error_code)); #endif generate_exception_end(ctx, EXCP_BREAK); @@ -1868,70 +1868,70 @@ static inline void gen_r6_cmp_ ## fmt(DisasContext = *ctx, int n, \ gen_ldcmp_fpr ## bits(ctx, fp1, ft); \ switch (n) { \ case 0: \ - gen_helper_r6_cmp_ ## fmt ## _af(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _af(fp0, tcg_env, fp0, fp1); \ break; \ case 1: \ - gen_helper_r6_cmp_ ## fmt ## _un(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _un(fp0, tcg_env, fp0, fp1); \ break; \ case 2: \ - gen_helper_r6_cmp_ ## fmt ## _eq(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _eq(fp0, tcg_env, fp0, fp1); \ break; \ case 3: \ - gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _ueq(fp0, tcg_env, fp0, fp1); \ break; \ case 4: \ - gen_helper_r6_cmp_ ## fmt ## _lt(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _lt(fp0, tcg_env, fp0, fp1); \ break; \ case 5: \ - gen_helper_r6_cmp_ ## fmt ## _ult(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _ult(fp0, tcg_env, fp0, fp1); \ break; \ case 6: \ - gen_helper_r6_cmp_ ## fmt ## _le(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _le(fp0, tcg_env, fp0, fp1); \ break; \ case 7: \ - gen_helper_r6_cmp_ ## fmt ## _ule(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _ule(fp0, tcg_env, fp0, fp1); \ break; \ case 8: \ - gen_helper_r6_cmp_ ## fmt ## _saf(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _saf(fp0, tcg_env, fp0, fp1); \ break; \ case 9: \ - gen_helper_r6_cmp_ ## fmt ## _sun(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _sun(fp0, tcg_env, fp0, fp1); \ break; \ case 10: \ - gen_helper_r6_cmp_ ## fmt ## _seq(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _seq(fp0, tcg_env, fp0, fp1); \ break; \ case 11: \ - gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _sueq(fp0, tcg_env, fp0, fp1); \ break; \ case 12: \ - gen_helper_r6_cmp_ ## fmt ## _slt(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _slt(fp0, tcg_env, fp0, fp1); \ break; \ case 13: \ - gen_helper_r6_cmp_ ## fmt ## _sult(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _sult(fp0, tcg_env, fp0, fp1); \ break; \ case 14: \ - gen_helper_r6_cmp_ ## fmt ## _sle(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _sle(fp0, tcg_env, fp0, fp1); \ break; \ case 15: \ - gen_helper_r6_cmp_ ## fmt ## _sule(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _sule(fp0, tcg_env, fp0, fp1); \ break; \ case 17: \ - gen_helper_r6_cmp_ ## fmt ## _or(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _or(fp0, tcg_env, fp0, fp1); \ break; \ case 18: \ - gen_helper_r6_cmp_ ## fmt ## _une(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _une(fp0, tcg_env, fp0, fp1); \ break; \ case 19: \ - gen_helper_r6_cmp_ ## fmt ## _ne(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _ne(fp0, tcg_env, fp0, fp1); \ break; \ case 25: \ - gen_helper_r6_cmp_ ## fmt ## _sor(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _sor(fp0, tcg_env, fp0, fp1); \ break; \ case 26: \ - gen_helper_r6_cmp_ ## fmt ## _sune(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _sune(fp0, tcg_env, fp0, fp1); \ break; \ case 27: \ - gen_helper_r6_cmp_ ## fmt ## _sne(fp0, cpu_env, fp0, fp1); \ + gen_helper_r6_cmp_ ## fmt ## _sne(fp0, tcg_env, fp0, fp1); \ break; \ default: \ abort(); \ @@ -1954,15 +1954,15 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1= , int mem_idx, \ TCGv t0 =3D tcg_temp_new(); = \ tcg_gen_mov_tl(t0, arg1); = \ tcg_gen_qemu_ld_tl(ret, arg1, ctx->mem_idx, memop); = \ - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); = \ - tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); = \ + tcg_gen_st_tl(t0, tcg_env, offsetof(CPUMIPSState, lladdr)); = \ + tcg_gen_st_tl(ret, tcg_env, offsetof(CPUMIPSState, llval)); = \ } #else #define OP_LD_ATOMIC(insn, fname) = \ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, = \ DisasContext *ctx) = \ { = \ - gen_helper_##insn(ret, cpu_env, arg1, tcg_constant_i32(mem_idx)); = \ + gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); = \ } #endif OP_LD_ATOMIC(ll, MO_TESL); @@ -4499,7 +4499,7 @@ static void gen_trap(DisasContext *ctx, uint32_t opc, /* Always trap */ #ifdef CONFIG_USER_ONLY /* Pass the break code along to cpu_loop. */ - tcg_gen_st_i32(tcg_constant_i32(code), cpu_env, + tcg_gen_st_i32(tcg_constant_i32(code), tcg_env, offsetof(CPUMIPSState, error_code)); #endif generate_exception_end(ctx, EXCP_TRAP); @@ -4544,7 +4544,7 @@ static void gen_trap(DisasContext *ctx, uint32_t opc, } #ifdef CONFIG_USER_ONLY /* Pass the break code along to cpu_loop. */ - tcg_gen_st_i32(tcg_constant_i32(code), cpu_env, + tcg_gen_st_i32(tcg_constant_i32(code), tcg_env, offsetof(CPUMIPSState, error_code)); #endif /* Like save_cpu_state, only don't update saved values. */ @@ -5053,13 +5053,13 @@ static inline void gen_mthc0_entrylo(TCGv arg, targ= et_ulong off) TCGv_i64 t1 =3D tcg_temp_new_i64(); =20 tcg_gen_ext_tl_i64(t0, arg); - tcg_gen_ld_i64(t1, cpu_env, off); + tcg_gen_ld_i64(t1, tcg_env, off); #if defined(TARGET_MIPS64) tcg_gen_deposit_i64(t1, t1, t0, 30, 32); #else tcg_gen_concat32_i64(t1, t1, t0); #endif - tcg_gen_st_i64(t1, cpu_env, off); + tcg_gen_st_i64(t1, tcg_env, off); } =20 static inline void gen_mthc0_store64(TCGv arg, target_ulong off) @@ -5068,16 +5068,16 @@ static inline void gen_mthc0_store64(TCGv arg, targ= et_ulong off) TCGv_i64 t1 =3D tcg_temp_new_i64(); =20 tcg_gen_ext_tl_i64(t0, arg); - tcg_gen_ld_i64(t1, cpu_env, off); + tcg_gen_ld_i64(t1, tcg_env, off); tcg_gen_concat32_i64(t1, t1, t0); - tcg_gen_st_i64(t1, cpu_env, off); + tcg_gen_st_i64(t1, tcg_env, off); } =20 static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off) { TCGv_i64 t0 =3D tcg_temp_new_i64(); =20 - tcg_gen_ld_i64(t0, cpu_env, off); + tcg_gen_ld_i64(t0, tcg_env, off); #if defined(TARGET_MIPS64) tcg_gen_shri_i64(t0, t0, 30); #else @@ -5090,7 +5090,7 @@ static inline void gen_mfhc0_load64(TCGv arg, target_= ulong off, int shift) { TCGv_i64 t0 =3D tcg_temp_new_i64(); =20 - tcg_gen_ld_i64(t0, cpu_env, off); + tcg_gen_ld_i64(t0, tcg_env, off); tcg_gen_shri_i64(t0, t0, 32 + shift); gen_move_low32(arg, t0); } @@ -5099,13 +5099,13 @@ static inline void gen_mfc0_load32(TCGv arg, target= _ulong off) { TCGv_i32 t0 =3D tcg_temp_new_i32(); =20 - tcg_gen_ld_i32(t0, cpu_env, off); + tcg_gen_ld_i32(t0, tcg_env, off); tcg_gen_ext_i32_tl(arg, t0); } =20 static inline void gen_mfc0_load64(TCGv arg, target_ulong off) { - tcg_gen_ld_tl(arg, cpu_env, off); + tcg_gen_ld_tl(arg, tcg_env, off); tcg_gen_ext32s_tl(arg, arg); } =20 @@ -5114,7 +5114,7 @@ static inline void gen_mtc0_store32(TCGv arg, target_= ulong off) TCGv_i32 t0 =3D tcg_temp_new_i32(); =20 tcg_gen_trunc_tl_i32(t0, arg); - tcg_gen_st_i32(t0, cpu_env, off); + tcg_gen_st_i32(t0, tcg_env, off); } =20 #define CP0_CHECK(c) \ @@ -5155,7 +5155,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) switch (sel) { case CP0_REG09__SAAR: CP0_CHECK(ctx->saar); - gen_helper_mfhc0_saar(arg, cpu_env); + gen_helper_mfhc0_saar(arg, tcg_env); register_name =3D "SAAR"; break; default: @@ -5171,7 +5171,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); - gen_helper_mfhc0_maar(arg, cpu_env); + gen_helper_mfhc0_maar(arg, tcg_env); register_name =3D "MAAR"; break; default: @@ -5256,7 +5256,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) switch (sel) { case CP0_REG09__SAAR: CP0_CHECK(ctx->saar); - gen_helper_mthc0_saar(cpu_env, arg); + gen_helper_mthc0_saar(tcg_env, arg); register_name =3D "SAAR"; break; default: @@ -5276,7 +5276,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); - gen_helper_mthc0_maar(cpu_env, arg); + gen_helper_mthc0_maar(tcg_env, arg); register_name =3D "MAAR"; break; default: @@ -5353,17 +5353,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REG00__MVPCONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mfc0_mvpcontrol(arg, cpu_env); + gen_helper_mfc0_mvpcontrol(arg, tcg_env); register_name =3D "MVPControl"; break; case CP0_REG00__MVPCONF0: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mfc0_mvpconf0(arg, cpu_env); + gen_helper_mfc0_mvpconf0(arg, tcg_env); register_name =3D "MVPConf0"; break; case CP0_REG00__MVPCONF1: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mfc0_mvpconf1(arg, cpu_env); + gen_helper_mfc0_mvpconf1(arg, tcg_env); register_name =3D "MVPConf1"; break; case CP0_REG00__VPCONTROL: @@ -5379,7 +5379,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) switch (sel) { case CP0_REG01__RANDOM: CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); - gen_helper_mfc0_random(arg, cpu_env); + gen_helper_mfc0_random(arg, tcg_env); register_name =3D "Random"; break; case CP0_REG01__VPECONTROL: @@ -5426,7 +5426,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REG02__ENTRYLO0: { TCGv_i64 tmp =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(tmp, cpu_env, + tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUMIPSState, CP0_EntryLo0)); #if defined(TARGET_MIPS64) if (ctx->rxi) { @@ -5441,37 +5441,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REG02__TCSTATUS: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mfc0_tcstatus(arg, cpu_env); + gen_helper_mfc0_tcstatus(arg, tcg_env); register_name =3D "TCStatus"; break; case CP0_REG02__TCBIND: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mfc0_tcbind(arg, cpu_env); + gen_helper_mfc0_tcbind(arg, tcg_env); register_name =3D "TCBind"; break; case CP0_REG02__TCRESTART: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mfc0_tcrestart(arg, cpu_env); + gen_helper_mfc0_tcrestart(arg, tcg_env); register_name =3D "TCRestart"; break; case CP0_REG02__TCHALT: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mfc0_tchalt(arg, cpu_env); + gen_helper_mfc0_tchalt(arg, tcg_env); register_name =3D "TCHalt"; break; case CP0_REG02__TCCONTEXT: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mfc0_tccontext(arg, cpu_env); + gen_helper_mfc0_tccontext(arg, tcg_env); register_name =3D "TCContext"; break; case CP0_REG02__TCSCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mfc0_tcschedule(arg, cpu_env); + gen_helper_mfc0_tcschedule(arg, tcg_env); register_name =3D "TCSchedule"; break; case CP0_REG02__TCSCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mfc0_tcschefback(arg, cpu_env); + gen_helper_mfc0_tcschefback(arg, tcg_env); register_name =3D "TCScheFBack"; break; default: @@ -5483,7 +5483,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REG03__ENTRYLO1: { TCGv_i64 tmp =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(tmp, cpu_env, + tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUMIPSState, CP0_EntryLo1)); #if defined(TARGET_MIPS64) if (ctx->rxi) { @@ -5508,7 +5508,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_04: switch (sel) { case CP0_REG04__CONTEXT: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context= )); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_Context= )); tcg_gen_ext32s_tl(arg, arg); register_name =3D "Context"; break; @@ -5519,14 +5519,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) goto cp0_unimplemented; case CP0_REG04__USERLOCAL: CP0_CHECK(ctx->ulri); - tcg_gen_ld_tl(arg, cpu_env, + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); tcg_gen_ext32s_tl(arg, arg); register_name =3D "UserLocal"; break; case CP0_REG04__MMID: CP0_CHECK(ctx->mi); - gen_helper_mtc0_memorymapid(cpu_env, arg); + gen_helper_mtc0_memorymapid(tcg_env, arg); register_name =3D "MMID"; break; default: @@ -5546,19 +5546,19 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REG05__SEGCTL0: CP0_CHECK(ctx->sc); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0= )); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl0= )); tcg_gen_ext32s_tl(arg, arg); register_name =3D "SegCtl0"; break; case CP0_REG05__SEGCTL1: CP0_CHECK(ctx->sc); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1= )); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl1= )); tcg_gen_ext32s_tl(arg, arg); register_name =3D "SegCtl1"; break; case CP0_REG05__SEGCTL2: CP0_CHECK(ctx->sc); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2= )); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl2= )); tcg_gen_ext32s_tl(arg, arg); register_name =3D "SegCtl2"; break; @@ -5635,7 +5635,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_08: switch (sel) { case CP0_REG08__BADVADDR: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAdd= r)); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_BadVAdd= r)); tcg_gen_ext32s_tl(arg, arg); register_name =3D "BadVAddr"; break; @@ -5665,7 +5665,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) /* Mark as an IO operation because we read the time. */ translator_io_start(&ctx->base); =20 - gen_helper_mfc0_count(arg, cpu_env); + gen_helper_mfc0_count(arg, tcg_env); /* * Break the TB to be able to take timer interrupts immediately * after reading count. DISAS_STOP isn't sufficient, we need to @@ -5682,7 +5682,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REG09__SAAR: CP0_CHECK(ctx->saar); - gen_helper_mfc0_saar(arg, cpu_env); + gen_helper_mfc0_saar(arg, tcg_env); register_name =3D "SAAR"; break; default: @@ -5692,7 +5692,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_10: switch (sel) { case CP0_REG10__ENTRYHI: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi= )); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryHi= )); tcg_gen_ext32s_tl(arg, arg); register_name =3D "EntryHi"; break; @@ -5749,7 +5749,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_14: switch (sel) { case CP0_REG14__EPC: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC)); tcg_gen_ext32s_tl(arg, arg); register_name =3D "EPC"; break; @@ -5765,14 +5765,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REG15__EBASE: check_insn(ctx, ISA_MIPS_R2); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EBase)); tcg_gen_ext32s_tl(arg, arg); register_name =3D "EBase"; break; case CP0_REG15__CMGCRBASE: check_insn(ctx, ISA_MIPS_R2); CP0_CHECK(ctx->cmgcr); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBa= se)); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_CMGCRBa= se)); tcg_gen_ext32s_tl(arg, arg); register_name =3D "CMGCRBase"; break; @@ -5822,12 +5822,12 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) case CP0_REGISTER_17: switch (sel) { case CP0_REG17__LLADDR: - gen_helper_mfc0_lladdr(arg, cpu_env); + gen_helper_mfc0_lladdr(arg, tcg_env); register_name =3D "LLAddr"; break; case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); - gen_helper_mfc0_maar(arg, cpu_env); + gen_helper_mfc0_maar(arg, tcg_env); register_name =3D "MAAR"; break; case CP0_REG17__MAARI: @@ -5880,7 +5880,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REG20__XCONTEXT: #if defined(TARGET_MIPS64) check_insn(ctx, ISA_MIPS3); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContex= t)); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_XContex= t)); tcg_gen_ext32s_tl(arg, arg); register_name =3D "XContext"; break; @@ -5908,7 +5908,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_23: switch (sel) { case CP0_REG23__DEBUG: - gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */ + gen_helper_mfc0_debug(arg, tcg_env); /* EJTAG support */ register_name =3D "Debug"; break; case CP0_REG23__TRACECONTROL: @@ -5944,7 +5944,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) switch (sel) { case CP0_REG24__DEPC: /* EJTAG support */ - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC)); tcg_gen_ext32s_tl(arg, arg); register_name =3D "DEPC"; break; @@ -6018,7 +6018,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REG28__TAGLO3: { TCGv_i64 tmp =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_Ta= gLo)); + tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUMIPSState, CP0_Ta= gLo)); gen_move_low32(arg, tmp); } register_name =3D "TagLo"; @@ -6057,7 +6057,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_30: switch (sel) { case CP0_REG30__ERROREPC: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEP= C)); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEP= C)); tcg_gen_ext32s_tl(arg, arg); register_name =3D "ErrorEPC"; break; @@ -6079,7 +6079,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REG31__KSCRATCH5: case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); - tcg_gen_ld_tl(arg, cpu_env, + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); tcg_gen_ext32s_tl(arg, arg); register_name =3D "KScratch"; @@ -6115,12 +6115,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) case CP0_REGISTER_00: switch (sel) { case CP0_REG00__INDEX: - gen_helper_mtc0_index(cpu_env, arg); + gen_helper_mtc0_index(tcg_env, arg); register_name =3D "Index"; break; case CP0_REG00__MVPCONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_mvpcontrol(cpu_env, arg); + gen_helper_mtc0_mvpcontrol(tcg_env, arg); register_name =3D "MVPControl"; break; case CP0_REG00__MVPCONF0: @@ -6150,39 +6150,39 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REG01__VPECONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_vpecontrol(cpu_env, arg); + gen_helper_mtc0_vpecontrol(tcg_env, arg); register_name =3D "VPEControl"; break; case CP0_REG01__VPECONF0: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_vpeconf0(cpu_env, arg); + gen_helper_mtc0_vpeconf0(tcg_env, arg); register_name =3D "VPEConf0"; break; case CP0_REG01__VPECONF1: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_vpeconf1(cpu_env, arg); + gen_helper_mtc0_vpeconf1(tcg_env, arg); register_name =3D "VPEConf1"; break; case CP0_REG01__YQMASK: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_yqmask(cpu_env, arg); + gen_helper_mtc0_yqmask(tcg_env, arg); register_name =3D "YQMask"; break; case CP0_REG01__VPESCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); - tcg_gen_st_tl(arg, cpu_env, + tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_VPESchedule)); register_name =3D "VPESchedule"; break; case CP0_REG01__VPESCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); - tcg_gen_st_tl(arg, cpu_env, + tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_VPEScheFBack)); register_name =3D "VPEScheFBack"; break; case CP0_REG01__VPEOPT: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_vpeopt(cpu_env, arg); + gen_helper_mtc0_vpeopt(tcg_env, arg); register_name =3D "VPEOpt"; break; default: @@ -6192,42 +6192,42 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) case CP0_REGISTER_02: switch (sel) { case CP0_REG02__ENTRYLO0: - gen_helper_mtc0_entrylo0(cpu_env, arg); + gen_helper_mtc0_entrylo0(tcg_env, arg); register_name =3D "EntryLo0"; break; case CP0_REG02__TCSTATUS: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_tcstatus(cpu_env, arg); + gen_helper_mtc0_tcstatus(tcg_env, arg); register_name =3D "TCStatus"; break; case CP0_REG02__TCBIND: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_tcbind(cpu_env, arg); + gen_helper_mtc0_tcbind(tcg_env, arg); register_name =3D "TCBind"; break; case CP0_REG02__TCRESTART: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_tcrestart(cpu_env, arg); + gen_helper_mtc0_tcrestart(tcg_env, arg); register_name =3D "TCRestart"; break; case CP0_REG02__TCHALT: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_tchalt(cpu_env, arg); + gen_helper_mtc0_tchalt(tcg_env, arg); register_name =3D "TCHalt"; break; case CP0_REG02__TCCONTEXT: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_tccontext(cpu_env, arg); + gen_helper_mtc0_tccontext(tcg_env, arg); register_name =3D "TCContext"; break; case CP0_REG02__TCSCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_tcschedule(cpu_env, arg); + gen_helper_mtc0_tcschedule(tcg_env, arg); register_name =3D "TCSchedule"; break; case CP0_REG02__TCSCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_tcschefback(cpu_env, arg); + gen_helper_mtc0_tcschefback(tcg_env, arg); register_name =3D "TCScheFBack"; break; default: @@ -6237,7 +6237,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_03: switch (sel) { case CP0_REG03__ENTRYLO1: - gen_helper_mtc0_entrylo1(cpu_env, arg); + gen_helper_mtc0_entrylo1(tcg_env, arg); register_name =3D "EntryLo1"; break; case CP0_REG03__GLOBALNUM: @@ -6252,7 +6252,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_04: switch (sel) { case CP0_REG04__CONTEXT: - gen_helper_mtc0_context(cpu_env, arg); + gen_helper_mtc0_context(tcg_env, arg); register_name =3D "Context"; break; case CP0_REG04__CONTEXTCONFIG: @@ -6262,7 +6262,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) goto cp0_unimplemented; case CP0_REG04__USERLOCAL: CP0_CHECK(ctx->ulri); - tcg_gen_st_tl(arg, cpu_env, + tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); register_name =3D "UserLocal"; break; @@ -6278,28 +6278,28 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) case CP0_REGISTER_05: switch (sel) { case CP0_REG05__PAGEMASK: - gen_helper_mtc0_pagemask(cpu_env, arg); + gen_helper_mtc0_pagemask(tcg_env, arg); register_name =3D "PageMask"; break; case CP0_REG05__PAGEGRAIN: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_pagegrain(cpu_env, arg); + gen_helper_mtc0_pagegrain(tcg_env, arg); register_name =3D "PageGrain"; ctx->base.is_jmp =3D DISAS_STOP; break; case CP0_REG05__SEGCTL0: CP0_CHECK(ctx->sc); - gen_helper_mtc0_segctl0(cpu_env, arg); + gen_helper_mtc0_segctl0(tcg_env, arg); register_name =3D "SegCtl0"; break; case CP0_REG05__SEGCTL1: CP0_CHECK(ctx->sc); - gen_helper_mtc0_segctl1(cpu_env, arg); + gen_helper_mtc0_segctl1(tcg_env, arg); register_name =3D "SegCtl1"; break; case CP0_REG05__SEGCTL2: CP0_CHECK(ctx->sc); - gen_helper_mtc0_segctl2(cpu_env, arg); + gen_helper_mtc0_segctl2(tcg_env, arg); register_name =3D "SegCtl2"; break; case CP0_REG05__PWBASE: @@ -6309,12 +6309,12 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REG05__PWFIELD: check_pw(ctx); - gen_helper_mtc0_pwfield(cpu_env, arg); + gen_helper_mtc0_pwfield(tcg_env, arg); register_name =3D "PWField"; break; case CP0_REG05__PWSIZE: check_pw(ctx); - gen_helper_mtc0_pwsize(cpu_env, arg); + gen_helper_mtc0_pwsize(tcg_env, arg); register_name =3D "PWSize"; break; default: @@ -6324,37 +6324,37 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) case CP0_REGISTER_06: switch (sel) { case CP0_REG06__WIRED: - gen_helper_mtc0_wired(cpu_env, arg); + gen_helper_mtc0_wired(tcg_env, arg); register_name =3D "Wired"; break; case CP0_REG06__SRSCONF0: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_srsconf0(cpu_env, arg); + gen_helper_mtc0_srsconf0(tcg_env, arg); register_name =3D "SRSConf0"; break; case CP0_REG06__SRSCONF1: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_srsconf1(cpu_env, arg); + gen_helper_mtc0_srsconf1(tcg_env, arg); register_name =3D "SRSConf1"; break; case CP0_REG06__SRSCONF2: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_srsconf2(cpu_env, arg); + gen_helper_mtc0_srsconf2(tcg_env, arg); register_name =3D "SRSConf2"; break; case CP0_REG06__SRSCONF3: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_srsconf3(cpu_env, arg); + gen_helper_mtc0_srsconf3(tcg_env, arg); register_name =3D "SRSConf3"; break; case CP0_REG06__SRSCONF4: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_srsconf4(cpu_env, arg); + gen_helper_mtc0_srsconf4(tcg_env, arg); register_name =3D "SRSConf4"; break; case CP0_REG06__PWCTL: check_pw(ctx); - gen_helper_mtc0_pwctl(cpu_env, arg); + gen_helper_mtc0_pwctl(tcg_env, arg); register_name =3D "PWCtl"; break; default: @@ -6365,7 +6365,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) switch (sel) { case CP0_REG07__HWRENA: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_hwrena(cpu_env, arg); + gen_helper_mtc0_hwrena(tcg_env, arg); ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "HWREna"; break; @@ -6398,17 +6398,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) case CP0_REGISTER_09: switch (sel) { case CP0_REG09__COUNT: - gen_helper_mtc0_count(cpu_env, arg); + gen_helper_mtc0_count(tcg_env, arg); register_name =3D "Count"; break; case CP0_REG09__SAARI: CP0_CHECK(ctx->saar); - gen_helper_mtc0_saari(cpu_env, arg); + gen_helper_mtc0_saari(tcg_env, arg); register_name =3D "SAARI"; break; case CP0_REG09__SAAR: CP0_CHECK(ctx->saar); - gen_helper_mtc0_saar(cpu_env, arg); + gen_helper_mtc0_saar(tcg_env, arg); register_name =3D "SAAR"; break; default: @@ -6418,7 +6418,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_10: switch (sel) { case CP0_REG10__ENTRYHI: - gen_helper_mtc0_entryhi(cpu_env, arg); + gen_helper_mtc0_entryhi(tcg_env, arg); register_name =3D "EntryHi"; break; default: @@ -6428,7 +6428,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_11: switch (sel) { case CP0_REG11__COMPARE: - gen_helper_mtc0_compare(cpu_env, arg); + gen_helper_mtc0_compare(tcg_env, arg); register_name =3D "Compare"; break; /* 6,7 are implementation dependent */ @@ -6440,7 +6440,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) switch (sel) { case CP0_REG12__STATUS: save_cpu_state(ctx, 1); - gen_helper_mtc0_status(cpu_env, arg); + gen_helper_mtc0_status(tcg_env, arg); /* DISAS_STOP isn't good enough here, hflags may have changed.= */ gen_save_pc(ctx->base.pc_next + 4); ctx->base.is_jmp =3D DISAS_EXIT; @@ -6448,14 +6448,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REG12__INTCTL: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_intctl(cpu_env, arg); + gen_helper_mtc0_intctl(tcg_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "IntCtl"; break; case CP0_REG12__SRSCTL: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_srsctl(cpu_env, arg); + gen_helper_mtc0_srsctl(tcg_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "SRSCtl"; @@ -6475,7 +6475,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) switch (sel) { case CP0_REG13__CAUSE: save_cpu_state(ctx, 1); - gen_helper_mtc0_cause(cpu_env, arg); + gen_helper_mtc0_cause(tcg_env, arg); /* * Stop translation as we may have triggered an interrupt. * DISAS_STOP isn't sufficient, we need to ensure we break out= of @@ -6492,7 +6492,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_14: switch (sel) { case CP0_REG14__EPC: - tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); + tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC)); register_name =3D "EPC"; break; default: @@ -6507,7 +6507,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) break; case CP0_REG15__EBASE: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_ebase(cpu_env, arg); + gen_helper_mtc0_ebase(tcg_env, arg); register_name =3D "EBase"; break; default: @@ -6517,7 +6517,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_16: switch (sel) { case CP0_REG16__CONFIG: - gen_helper_mtc0_config0(cpu_env, arg); + gen_helper_mtc0_config0(tcg_env, arg); register_name =3D "Config"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; @@ -6527,24 +6527,24 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) register_name =3D "Config1"; break; case CP0_REG16__CONFIG2: - gen_helper_mtc0_config2(cpu_env, arg); + gen_helper_mtc0_config2(tcg_env, arg); register_name =3D "Config2"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; break; case CP0_REG16__CONFIG3: - gen_helper_mtc0_config3(cpu_env, arg); + gen_helper_mtc0_config3(tcg_env, arg); register_name =3D "Config3"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; break; case CP0_REG16__CONFIG4: - gen_helper_mtc0_config4(cpu_env, arg); + gen_helper_mtc0_config4(tcg_env, arg); register_name =3D "Config4"; ctx->base.is_jmp =3D DISAS_STOP; break; case CP0_REG16__CONFIG5: - gen_helper_mtc0_config5(cpu_env, arg); + gen_helper_mtc0_config5(tcg_env, arg); register_name =3D "Config5"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; @@ -6566,17 +6566,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) case CP0_REGISTER_17: switch (sel) { case CP0_REG17__LLADDR: - gen_helper_mtc0_lladdr(cpu_env, arg); + gen_helper_mtc0_lladdr(tcg_env, arg); register_name =3D "LLAddr"; break; case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); - gen_helper_mtc0_maar(cpu_env, arg); + gen_helper_mtc0_maar(tcg_env, arg); register_name =3D "MAAR"; break; case CP0_REG17__MAARI: CP0_CHECK(ctx->mrp); - gen_helper_mtc0_maari(cpu_env, arg); + gen_helper_mtc0_maari(tcg_env, arg); register_name =3D "MAARI"; break; default: @@ -6624,7 +6624,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REG20__XCONTEXT: #if defined(TARGET_MIPS64) check_insn(ctx, ISA_MIPS3); - gen_helper_mtc0_xcontext(cpu_env, arg); + gen_helper_mtc0_xcontext(tcg_env, arg); register_name =3D "XContext"; break; #endif @@ -6637,7 +6637,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: - gen_helper_mtc0_framemask(cpu_env, arg); + gen_helper_mtc0_framemask(tcg_env, arg); register_name =3D "Framemask"; break; default: @@ -6651,7 +6651,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_23: switch (sel) { case CP0_REG23__DEBUG: - gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */ + gen_helper_mtc0_debug(tcg_env, arg); /* EJTAG support */ /* DISAS_STOP isn't good enough here, hflags may have changed.= */ gen_save_pc(ctx->base.pc_next + 4); ctx->base.is_jmp =3D DISAS_EXIT; @@ -6659,14 +6659,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) break; case CP0_REG23__TRACECONTROL: /* PDtrace support */ - /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */ + /* gen_helper_mtc0_tracecontrol(tcg_env, arg); */ register_name =3D "TraceControl"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; goto cp0_unimplemented; case CP0_REG23__TRACECONTROL2: /* PDtrace support */ - /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */ + /* gen_helper_mtc0_tracecontrol2(tcg_env, arg); */ register_name =3D "TraceControl2"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; @@ -6675,21 +6675,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; /* PDtrace support */ - /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/ + /* gen_helper_mtc0_usertracedata1(tcg_env, arg);*/ register_name =3D "UserTraceData"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; goto cp0_unimplemented; case CP0_REG23__TRACEIBPC: /* PDtrace support */ - /* gen_helper_mtc0_traceibpc(cpu_env, arg); */ + /* gen_helper_mtc0_traceibpc(tcg_env, arg); */ /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "TraceIBPC"; goto cp0_unimplemented; case CP0_REG23__TRACEDBPC: /* PDtrace support */ - /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */ + /* gen_helper_mtc0_tracedbpc(tcg_env, arg); */ /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "TraceDBPC"; @@ -6702,7 +6702,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) switch (sel) { case CP0_REG24__DEPC: /* EJTAG support */ - tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); + tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC)); register_name =3D "DEPC"; break; default: @@ -6712,7 +6712,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_25: switch (sel) { case CP0_REG25__PERFCTL0: - gen_helper_mtc0_performance0(cpu_env, arg); + gen_helper_mtc0_performance0(tcg_env, arg); register_name =3D "Performance0"; break; case CP0_REG25__PERFCNT0: @@ -6750,7 +6750,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_26: switch (sel) { case CP0_REG26__ERRCTL: - gen_helper_mtc0_errctl(cpu_env, arg); + gen_helper_mtc0_errctl(tcg_env, arg); ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "ErrCtl"; break; @@ -6774,14 +6774,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) case CP0_REG28__TAGLO1: case CP0_REG28__TAGLO2: case CP0_REG28__TAGLO3: - gen_helper_mtc0_taglo(cpu_env, arg); + gen_helper_mtc0_taglo(tcg_env, arg); register_name =3D "TagLo"; break; case CP0_REG28__DATALO: case CP0_REG28__DATALO1: case CP0_REG28__DATALO2: case CP0_REG28__DATALO3: - gen_helper_mtc0_datalo(cpu_env, arg); + gen_helper_mtc0_datalo(tcg_env, arg); register_name =3D "DataLo"; break; default: @@ -6794,14 +6794,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) case CP0_REG29__TAGHI1: case CP0_REG29__TAGHI2: case CP0_REG29__TAGHI3: - gen_helper_mtc0_taghi(cpu_env, arg); + gen_helper_mtc0_taghi(tcg_env, arg); register_name =3D "TagHi"; break; case CP0_REG29__DATAHI: case CP0_REG29__DATAHI1: case CP0_REG29__DATAHI2: case CP0_REG29__DATAHI3: - gen_helper_mtc0_datahi(cpu_env, arg); + gen_helper_mtc0_datahi(tcg_env, arg); register_name =3D "DataHi"; break; default: @@ -6812,7 +6812,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REGISTER_30: switch (sel) { case CP0_REG30__ERROREPC: - tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEP= C)); + tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEP= C)); register_name =3D "ErrorEPC"; break; default: @@ -6833,7 +6833,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int= reg, int sel) case CP0_REG31__KSCRATCH5: case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); - tcg_gen_st_tl(arg, cpu_env, + tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); register_name =3D "KScratch"; break; @@ -6880,17 +6880,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REG00__MVPCONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mfc0_mvpcontrol(arg, cpu_env); + gen_helper_mfc0_mvpcontrol(arg, tcg_env); register_name =3D "MVPControl"; break; case CP0_REG00__MVPCONF0: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mfc0_mvpconf0(arg, cpu_env); + gen_helper_mfc0_mvpconf0(arg, tcg_env); register_name =3D "MVPConf0"; break; case CP0_REG00__MVPCONF1: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mfc0_mvpconf1(arg, cpu_env); + gen_helper_mfc0_mvpconf1(arg, tcg_env); register_name =3D "MVPConf1"; break; case CP0_REG00__VPCONTROL: @@ -6906,7 +6906,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) switch (sel) { case CP0_REG01__RANDOM: CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); - gen_helper_mfc0_random(arg, cpu_env); + gen_helper_mfc0_random(arg, tcg_env); register_name =3D "Random"; break; case CP0_REG01__VPECONTROL: @@ -6926,19 +6926,19 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REG01__YQMASK: CP0_CHECK(ctx->insn_flags & ASE_MT); - tcg_gen_ld_tl(arg, cpu_env, + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_YQMask)); register_name =3D "YQMask"; break; case CP0_REG01__VPESCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); - tcg_gen_ld_tl(arg, cpu_env, + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_VPESchedule)); register_name =3D "VPESchedule"; break; case CP0_REG01__VPESCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); - tcg_gen_ld_tl(arg, cpu_env, + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_VPEScheFBack)); register_name =3D "VPEScheFBack"; break; @@ -6954,43 +6954,43 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) case CP0_REGISTER_02: switch (sel) { case CP0_REG02__ENTRYLO0: - tcg_gen_ld_tl(arg, cpu_env, + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryLo0)); register_name =3D "EntryLo0"; break; case CP0_REG02__TCSTATUS: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mfc0_tcstatus(arg, cpu_env); + gen_helper_mfc0_tcstatus(arg, tcg_env); register_name =3D "TCStatus"; break; case CP0_REG02__TCBIND: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mfc0_tcbind(arg, cpu_env); + gen_helper_mfc0_tcbind(arg, tcg_env); register_name =3D "TCBind"; break; case CP0_REG02__TCRESTART: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_dmfc0_tcrestart(arg, cpu_env); + gen_helper_dmfc0_tcrestart(arg, tcg_env); register_name =3D "TCRestart"; break; case CP0_REG02__TCHALT: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_dmfc0_tchalt(arg, cpu_env); + gen_helper_dmfc0_tchalt(arg, tcg_env); register_name =3D "TCHalt"; break; case CP0_REG02__TCCONTEXT: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_dmfc0_tccontext(arg, cpu_env); + gen_helper_dmfc0_tccontext(arg, tcg_env); register_name =3D "TCContext"; break; case CP0_REG02__TCSCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_dmfc0_tcschedule(arg, cpu_env); + gen_helper_dmfc0_tcschedule(arg, tcg_env); register_name =3D "TCSchedule"; break; case CP0_REG02__TCSCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_dmfc0_tcschefback(arg, cpu_env); + gen_helper_dmfc0_tcschefback(arg, tcg_env); register_name =3D "TCScheFBack"; break; default: @@ -7000,7 +7000,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_03: switch (sel) { case CP0_REG03__ENTRYLO1: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo= 1)); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryLo= 1)); register_name =3D "EntryLo1"; break; case CP0_REG03__GLOBALNUM: @@ -7015,7 +7015,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_04: switch (sel) { case CP0_REG04__CONTEXT: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context= )); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_Context= )); register_name =3D "Context"; break; case CP0_REG04__CONTEXTCONFIG: @@ -7025,13 +7025,13 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) goto cp0_unimplemented; case CP0_REG04__USERLOCAL: CP0_CHECK(ctx->ulri); - tcg_gen_ld_tl(arg, cpu_env, + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); register_name =3D "UserLocal"; break; case CP0_REG04__MMID: CP0_CHECK(ctx->mi); - gen_helper_mtc0_memorymapid(cpu_env, arg); + gen_helper_mtc0_memorymapid(tcg_env, arg); register_name =3D "MMID"; break; default: @@ -7051,32 +7051,32 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REG05__SEGCTL0: CP0_CHECK(ctx->sc); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0= )); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl0= )); register_name =3D "SegCtl0"; break; case CP0_REG05__SEGCTL1: CP0_CHECK(ctx->sc); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1= )); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl1= )); register_name =3D "SegCtl1"; break; case CP0_REG05__SEGCTL2: CP0_CHECK(ctx->sc); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2= )); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_SegCtl2= )); register_name =3D "SegCtl2"; break; case CP0_REG05__PWBASE: check_pw(ctx); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)= ); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWBase)= ); register_name =3D "PWBase"; break; case CP0_REG05__PWFIELD: check_pw(ctx); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField= )); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWField= )); register_name =3D "PWField"; break; case CP0_REG05__PWSIZE: check_pw(ctx); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize)= ); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWSize)= ); register_name =3D "PWSize"; break; default: @@ -7137,7 +7137,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_08: switch (sel) { case CP0_REG08__BADVADDR: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAdd= r)); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_BadVAdd= r)); register_name =3D "BadVAddr"; break; case CP0_REG08__BADINSTR: @@ -7165,7 +7165,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REG09__COUNT: /* Mark as an IO operation because we read the time. */ translator_io_start(&ctx->base); - gen_helper_mfc0_count(arg, cpu_env); + gen_helper_mfc0_count(arg, tcg_env); /* * Break the TB to be able to take timer interrupts immediately * after reading count. DISAS_STOP isn't sufficient, we need to @@ -7182,7 +7182,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REG09__SAAR: CP0_CHECK(ctx->saar); - gen_helper_dmfc0_saar(arg, cpu_env); + gen_helper_dmfc0_saar(arg, tcg_env); register_name =3D "SAAR"; break; default: @@ -7192,7 +7192,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_10: switch (sel) { case CP0_REG10__ENTRYHI: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi= )); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EntryHi= )); register_name =3D "EntryHi"; break; default: @@ -7248,7 +7248,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_14: switch (sel) { case CP0_REG14__EPC: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC)); register_name =3D "EPC"; break; default: @@ -7263,13 +7263,13 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REG15__EBASE: check_insn(ctx, ISA_MIPS_R2); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase)); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EBase)); register_name =3D "EBase"; break; case CP0_REG15__CMGCRBASE: check_insn(ctx, ISA_MIPS_R2); CP0_CHECK(ctx->cmgcr); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBa= se)); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_CMGCRBa= se)); register_name =3D "CMGCRBase"; break; default: @@ -7318,12 +7318,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) case CP0_REGISTER_17: switch (sel) { case CP0_REG17__LLADDR: - gen_helper_dmfc0_lladdr(arg, cpu_env); + gen_helper_dmfc0_lladdr(arg, tcg_env); register_name =3D "LLAddr"; break; case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); - gen_helper_dmfc0_maar(arg, cpu_env); + gen_helper_dmfc0_maar(arg, tcg_env); register_name =3D "MAAR"; break; case CP0_REG17__MAARI: @@ -7375,7 +7375,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) switch (sel) { case CP0_REG20__XCONTEXT: check_insn(ctx, ISA_MIPS3); - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContex= t)); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_XContex= t)); register_name =3D "XContext"; break; default: @@ -7401,32 +7401,32 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) case CP0_REGISTER_23: switch (sel) { case CP0_REG23__DEBUG: - gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */ + gen_helper_mfc0_debug(arg, tcg_env); /* EJTAG support */ register_name =3D "Debug"; break; case CP0_REG23__TRACECONTROL: /* PDtrace support */ - /* gen_helper_dmfc0_tracecontrol(arg, cpu_env); */ + /* gen_helper_dmfc0_tracecontrol(arg, tcg_env); */ register_name =3D "TraceControl"; goto cp0_unimplemented; case CP0_REG23__TRACECONTROL2: /* PDtrace support */ - /* gen_helper_dmfc0_tracecontrol2(arg, cpu_env); */ + /* gen_helper_dmfc0_tracecontrol2(arg, tcg_env); */ register_name =3D "TraceControl2"; goto cp0_unimplemented; case CP0_REG23__USERTRACEDATA1: /* PDtrace support */ - /* gen_helper_dmfc0_usertracedata1(arg, cpu_env);*/ + /* gen_helper_dmfc0_usertracedata1(arg, tcg_env);*/ register_name =3D "UserTraceData1"; goto cp0_unimplemented; case CP0_REG23__TRACEIBPC: /* PDtrace support */ - /* gen_helper_dmfc0_traceibpc(arg, cpu_env); */ + /* gen_helper_dmfc0_traceibpc(arg, tcg_env); */ register_name =3D "TraceIBPC"; goto cp0_unimplemented; case CP0_REG23__TRACEDBPC: /* PDtrace support */ - /* gen_helper_dmfc0_tracedbpc(arg, cpu_env); */ + /* gen_helper_dmfc0_tracedbpc(arg, tcg_env); */ register_name =3D "TraceDBPC"; goto cp0_unimplemented; default: @@ -7437,7 +7437,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) switch (sel) { case CP0_REG24__DEPC: /* EJTAG support */ - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC)); register_name =3D "DEPC"; break; default: @@ -7546,7 +7546,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_30: switch (sel) { case CP0_REG30__ERROREPC: - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEP= C)); + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEP= C)); register_name =3D "ErrorEPC"; break; default: @@ -7567,7 +7567,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REG31__KSCRATCH5: case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); - tcg_gen_ld_tl(arg, cpu_env, + tcg_gen_ld_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); register_name =3D "KScratch"; break; @@ -7602,12 +7602,12 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) case CP0_REGISTER_00: switch (sel) { case CP0_REG00__INDEX: - gen_helper_mtc0_index(cpu_env, arg); + gen_helper_mtc0_index(tcg_env, arg); register_name =3D "Index"; break; case CP0_REG00__MVPCONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_mvpcontrol(cpu_env, arg); + gen_helper_mtc0_mvpcontrol(tcg_env, arg); register_name =3D "MVPControl"; break; case CP0_REG00__MVPCONF0: @@ -7637,39 +7637,39 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REG01__VPECONTROL: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_vpecontrol(cpu_env, arg); + gen_helper_mtc0_vpecontrol(tcg_env, arg); register_name =3D "VPEControl"; break; case CP0_REG01__VPECONF0: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_vpeconf0(cpu_env, arg); + gen_helper_mtc0_vpeconf0(tcg_env, arg); register_name =3D "VPEConf0"; break; case CP0_REG01__VPECONF1: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_vpeconf1(cpu_env, arg); + gen_helper_mtc0_vpeconf1(tcg_env, arg); register_name =3D "VPEConf1"; break; case CP0_REG01__YQMASK: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_yqmask(cpu_env, arg); + gen_helper_mtc0_yqmask(tcg_env, arg); register_name =3D "YQMask"; break; case CP0_REG01__VPESCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); - tcg_gen_st_tl(arg, cpu_env, + tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_VPESchedule)); register_name =3D "VPESchedule"; break; case CP0_REG01__VPESCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); - tcg_gen_st_tl(arg, cpu_env, + tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_VPEScheFBack)); register_name =3D "VPEScheFBack"; break; case CP0_REG01__VPEOPT: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_vpeopt(cpu_env, arg); + gen_helper_mtc0_vpeopt(tcg_env, arg); register_name =3D "VPEOpt"; break; default: @@ -7679,42 +7679,42 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) case CP0_REGISTER_02: switch (sel) { case CP0_REG02__ENTRYLO0: - gen_helper_dmtc0_entrylo0(cpu_env, arg); + gen_helper_dmtc0_entrylo0(tcg_env, arg); register_name =3D "EntryLo0"; break; case CP0_REG02__TCSTATUS: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_tcstatus(cpu_env, arg); + gen_helper_mtc0_tcstatus(tcg_env, arg); register_name =3D "TCStatus"; break; case CP0_REG02__TCBIND: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_tcbind(cpu_env, arg); + gen_helper_mtc0_tcbind(tcg_env, arg); register_name =3D "TCBind"; break; case CP0_REG02__TCRESTART: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_tcrestart(cpu_env, arg); + gen_helper_mtc0_tcrestart(tcg_env, arg); register_name =3D "TCRestart"; break; case CP0_REG02__TCHALT: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_tchalt(cpu_env, arg); + gen_helper_mtc0_tchalt(tcg_env, arg); register_name =3D "TCHalt"; break; case CP0_REG02__TCCONTEXT: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_tccontext(cpu_env, arg); + gen_helper_mtc0_tccontext(tcg_env, arg); register_name =3D "TCContext"; break; case CP0_REG02__TCSCHEDULE: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_tcschedule(cpu_env, arg); + gen_helper_mtc0_tcschedule(tcg_env, arg); register_name =3D "TCSchedule"; break; case CP0_REG02__TCSCHEFBACK: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_helper_mtc0_tcschefback(cpu_env, arg); + gen_helper_mtc0_tcschefback(tcg_env, arg); register_name =3D "TCScheFBack"; break; default: @@ -7724,7 +7724,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_03: switch (sel) { case CP0_REG03__ENTRYLO1: - gen_helper_dmtc0_entrylo1(cpu_env, arg); + gen_helper_dmtc0_entrylo1(tcg_env, arg); register_name =3D "EntryLo1"; break; case CP0_REG03__GLOBALNUM: @@ -7739,7 +7739,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_04: switch (sel) { case CP0_REG04__CONTEXT: - gen_helper_mtc0_context(cpu_env, arg); + gen_helper_mtc0_context(tcg_env, arg); register_name =3D "Context"; break; case CP0_REG04__CONTEXTCONFIG: @@ -7749,7 +7749,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) goto cp0_unimplemented; case CP0_REG04__USERLOCAL: CP0_CHECK(ctx->ulri); - tcg_gen_st_tl(arg, cpu_env, + tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); register_name =3D "UserLocal"; break; @@ -7765,42 +7765,42 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) case CP0_REGISTER_05: switch (sel) { case CP0_REG05__PAGEMASK: - gen_helper_mtc0_pagemask(cpu_env, arg); + gen_helper_mtc0_pagemask(tcg_env, arg); register_name =3D "PageMask"; break; case CP0_REG05__PAGEGRAIN: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_pagegrain(cpu_env, arg); + gen_helper_mtc0_pagegrain(tcg_env, arg); register_name =3D "PageGrain"; break; case CP0_REG05__SEGCTL0: CP0_CHECK(ctx->sc); - gen_helper_mtc0_segctl0(cpu_env, arg); + gen_helper_mtc0_segctl0(tcg_env, arg); register_name =3D "SegCtl0"; break; case CP0_REG05__SEGCTL1: CP0_CHECK(ctx->sc); - gen_helper_mtc0_segctl1(cpu_env, arg); + gen_helper_mtc0_segctl1(tcg_env, arg); register_name =3D "SegCtl1"; break; case CP0_REG05__SEGCTL2: CP0_CHECK(ctx->sc); - gen_helper_mtc0_segctl2(cpu_env, arg); + gen_helper_mtc0_segctl2(tcg_env, arg); register_name =3D "SegCtl2"; break; case CP0_REG05__PWBASE: check_pw(ctx); - tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase)= ); + tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_PWBase)= ); register_name =3D "PWBase"; break; case CP0_REG05__PWFIELD: check_pw(ctx); - gen_helper_mtc0_pwfield(cpu_env, arg); + gen_helper_mtc0_pwfield(tcg_env, arg); register_name =3D "PWField"; break; case CP0_REG05__PWSIZE: check_pw(ctx); - gen_helper_mtc0_pwsize(cpu_env, arg); + gen_helper_mtc0_pwsize(tcg_env, arg); register_name =3D "PWSize"; break; default: @@ -7810,37 +7810,37 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) case CP0_REGISTER_06: switch (sel) { case CP0_REG06__WIRED: - gen_helper_mtc0_wired(cpu_env, arg); + gen_helper_mtc0_wired(tcg_env, arg); register_name =3D "Wired"; break; case CP0_REG06__SRSCONF0: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_srsconf0(cpu_env, arg); + gen_helper_mtc0_srsconf0(tcg_env, arg); register_name =3D "SRSConf0"; break; case CP0_REG06__SRSCONF1: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_srsconf1(cpu_env, arg); + gen_helper_mtc0_srsconf1(tcg_env, arg); register_name =3D "SRSConf1"; break; case CP0_REG06__SRSCONF2: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_srsconf2(cpu_env, arg); + gen_helper_mtc0_srsconf2(tcg_env, arg); register_name =3D "SRSConf2"; break; case CP0_REG06__SRSCONF3: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_srsconf3(cpu_env, arg); + gen_helper_mtc0_srsconf3(tcg_env, arg); register_name =3D "SRSConf3"; break; case CP0_REG06__SRSCONF4: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_srsconf4(cpu_env, arg); + gen_helper_mtc0_srsconf4(tcg_env, arg); register_name =3D "SRSConf4"; break; case CP0_REG06__PWCTL: check_pw(ctx); - gen_helper_mtc0_pwctl(cpu_env, arg); + gen_helper_mtc0_pwctl(tcg_env, arg); register_name =3D "PWCtl"; break; default: @@ -7851,7 +7851,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) switch (sel) { case CP0_REG07__HWRENA: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_hwrena(cpu_env, arg); + gen_helper_mtc0_hwrena(tcg_env, arg); ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "HWREna"; break; @@ -7884,17 +7884,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) case CP0_REGISTER_09: switch (sel) { case CP0_REG09__COUNT: - gen_helper_mtc0_count(cpu_env, arg); + gen_helper_mtc0_count(tcg_env, arg); register_name =3D "Count"; break; case CP0_REG09__SAARI: CP0_CHECK(ctx->saar); - gen_helper_mtc0_saari(cpu_env, arg); + gen_helper_mtc0_saari(tcg_env, arg); register_name =3D "SAARI"; break; case CP0_REG09__SAAR: CP0_CHECK(ctx->saar); - gen_helper_mtc0_saar(cpu_env, arg); + gen_helper_mtc0_saar(tcg_env, arg); register_name =3D "SAAR"; break; default: @@ -7906,7 +7906,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_10: switch (sel) { case CP0_REG10__ENTRYHI: - gen_helper_mtc0_entryhi(cpu_env, arg); + gen_helper_mtc0_entryhi(tcg_env, arg); register_name =3D "EntryHi"; break; default: @@ -7916,7 +7916,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_11: switch (sel) { case CP0_REG11__COMPARE: - gen_helper_mtc0_compare(cpu_env, arg); + gen_helper_mtc0_compare(tcg_env, arg); register_name =3D "Compare"; break; /* 6,7 are implementation dependent */ @@ -7930,7 +7930,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) switch (sel) { case CP0_REG12__STATUS: save_cpu_state(ctx, 1); - gen_helper_mtc0_status(cpu_env, arg); + gen_helper_mtc0_status(tcg_env, arg); /* DISAS_STOP isn't good enough here, hflags may have changed.= */ gen_save_pc(ctx->base.pc_next + 4); ctx->base.is_jmp =3D DISAS_EXIT; @@ -7938,14 +7938,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REG12__INTCTL: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_intctl(cpu_env, arg); + gen_helper_mtc0_intctl(tcg_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "IntCtl"; break; case CP0_REG12__SRSCTL: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_srsctl(cpu_env, arg); + gen_helper_mtc0_srsctl(tcg_env, arg); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "SRSCtl"; @@ -7965,7 +7965,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) switch (sel) { case CP0_REG13__CAUSE: save_cpu_state(ctx, 1); - gen_helper_mtc0_cause(cpu_env, arg); + gen_helper_mtc0_cause(tcg_env, arg); /* * Stop translation as we may have triggered an interrupt. * DISAS_STOP isn't sufficient, we need to ensure we break out= of @@ -7982,7 +7982,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_14: switch (sel) { case CP0_REG14__EPC: - tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); + tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_EPC)); register_name =3D "EPC"; break; default: @@ -7997,7 +7997,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) break; case CP0_REG15__EBASE: check_insn(ctx, ISA_MIPS_R2); - gen_helper_mtc0_ebase(cpu_env, arg); + gen_helper_mtc0_ebase(tcg_env, arg); register_name =3D "EBase"; break; default: @@ -8007,7 +8007,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_16: switch (sel) { case CP0_REG16__CONFIG: - gen_helper_mtc0_config0(cpu_env, arg); + gen_helper_mtc0_config0(tcg_env, arg); register_name =3D "Config"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; @@ -8017,13 +8017,13 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) register_name =3D "Config1"; break; case CP0_REG16__CONFIG2: - gen_helper_mtc0_config2(cpu_env, arg); + gen_helper_mtc0_config2(tcg_env, arg); register_name =3D "Config2"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; break; case CP0_REG16__CONFIG3: - gen_helper_mtc0_config3(cpu_env, arg); + gen_helper_mtc0_config3(tcg_env, arg); register_name =3D "Config3"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; @@ -8033,7 +8033,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) register_name =3D "Config4"; break; case CP0_REG16__CONFIG5: - gen_helper_mtc0_config5(cpu_env, arg); + gen_helper_mtc0_config5(tcg_env, arg); register_name =3D "Config5"; /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; @@ -8047,17 +8047,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) case CP0_REGISTER_17: switch (sel) { case CP0_REG17__LLADDR: - gen_helper_mtc0_lladdr(cpu_env, arg); + gen_helper_mtc0_lladdr(tcg_env, arg); register_name =3D "LLAddr"; break; case CP0_REG17__MAAR: CP0_CHECK(ctx->mrp); - gen_helper_mtc0_maar(cpu_env, arg); + gen_helper_mtc0_maar(tcg_env, arg); register_name =3D "MAAR"; break; case CP0_REG17__MAARI: CP0_CHECK(ctx->mrp); - gen_helper_mtc0_maari(cpu_env, arg); + gen_helper_mtc0_maari(tcg_env, arg); register_name =3D "MAARI"; break; default: @@ -8104,7 +8104,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) switch (sel) { case CP0_REG20__XCONTEXT: check_insn(ctx, ISA_MIPS3); - gen_helper_mtc0_xcontext(cpu_env, arg); + gen_helper_mtc0_xcontext(tcg_env, arg); register_name =3D "XContext"; break; default: @@ -8116,7 +8116,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); switch (sel) { case 0: - gen_helper_mtc0_framemask(cpu_env, arg); + gen_helper_mtc0_framemask(tcg_env, arg); register_name =3D "Framemask"; break; default: @@ -8130,7 +8130,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_23: switch (sel) { case CP0_REG23__DEBUG: - gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */ + gen_helper_mtc0_debug(tcg_env, arg); /* EJTAG support */ /* DISAS_STOP isn't good enough here, hflags may have changed.= */ gen_save_pc(ctx->base.pc_next + 4); ctx->base.is_jmp =3D DISAS_EXIT; @@ -8138,35 +8138,35 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) break; case CP0_REG23__TRACECONTROL: /* PDtrace support */ - /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */ + /* gen_helper_mtc0_tracecontrol(tcg_env, arg); */ /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "TraceControl"; goto cp0_unimplemented; case CP0_REG23__TRACECONTROL2: /* PDtrace support */ - /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */ + /* gen_helper_mtc0_tracecontrol2(tcg_env, arg); */ /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "TraceControl2"; goto cp0_unimplemented; case CP0_REG23__USERTRACEDATA1: /* PDtrace support */ - /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/ + /* gen_helper_mtc0_usertracedata1(tcg_env, arg);*/ /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "UserTraceData1"; goto cp0_unimplemented; case CP0_REG23__TRACEIBPC: /* PDtrace support */ - /* gen_helper_mtc0_traceibpc(cpu_env, arg); */ + /* gen_helper_mtc0_traceibpc(tcg_env, arg); */ /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "TraceIBPC"; goto cp0_unimplemented; case CP0_REG23__TRACEDBPC: /* PDtrace support */ - /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */ + /* gen_helper_mtc0_tracedbpc(tcg_env, arg); */ /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "TraceDBPC"; @@ -8179,7 +8179,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) switch (sel) { case CP0_REG24__DEPC: /* EJTAG support */ - tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); + tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_DEPC)); register_name =3D "DEPC"; break; default: @@ -8189,35 +8189,35 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) case CP0_REGISTER_25: switch (sel) { case CP0_REG25__PERFCTL0: - gen_helper_mtc0_performance0(cpu_env, arg); + gen_helper_mtc0_performance0(tcg_env, arg); register_name =3D "Performance0"; break; case CP0_REG25__PERFCNT0: - /* gen_helper_mtc0_performance1(cpu_env, arg); */ + /* gen_helper_mtc0_performance1(tcg_env, arg); */ register_name =3D "Performance1"; goto cp0_unimplemented; case CP0_REG25__PERFCTL1: - /* gen_helper_mtc0_performance2(cpu_env, arg); */ + /* gen_helper_mtc0_performance2(tcg_env, arg); */ register_name =3D "Performance2"; goto cp0_unimplemented; case CP0_REG25__PERFCNT1: - /* gen_helper_mtc0_performance3(cpu_env, arg); */ + /* gen_helper_mtc0_performance3(tcg_env, arg); */ register_name =3D "Performance3"; goto cp0_unimplemented; case CP0_REG25__PERFCTL2: - /* gen_helper_mtc0_performance4(cpu_env, arg); */ + /* gen_helper_mtc0_performance4(tcg_env, arg); */ register_name =3D "Performance4"; goto cp0_unimplemented; case CP0_REG25__PERFCNT2: - /* gen_helper_mtc0_performance5(cpu_env, arg); */ + /* gen_helper_mtc0_performance5(tcg_env, arg); */ register_name =3D "Performance5"; goto cp0_unimplemented; case CP0_REG25__PERFCTL3: - /* gen_helper_mtc0_performance6(cpu_env, arg); */ + /* gen_helper_mtc0_performance6(tcg_env, arg); */ register_name =3D "Performance6"; goto cp0_unimplemented; case CP0_REG25__PERFCNT3: - /* gen_helper_mtc0_performance7(cpu_env, arg); */ + /* gen_helper_mtc0_performance7(tcg_env, arg); */ register_name =3D "Performance7"; goto cp0_unimplemented; default: @@ -8227,7 +8227,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_26: switch (sel) { case CP0_REG26__ERRCTL: - gen_helper_mtc0_errctl(cpu_env, arg); + gen_helper_mtc0_errctl(tcg_env, arg); ctx->base.is_jmp =3D DISAS_STOP; register_name =3D "ErrCtl"; break; @@ -8251,14 +8251,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) case CP0_REG28__TAGLO1: case CP0_REG28__TAGLO2: case CP0_REG28__TAGLO3: - gen_helper_mtc0_taglo(cpu_env, arg); + gen_helper_mtc0_taglo(tcg_env, arg); register_name =3D "TagLo"; break; case CP0_REG28__DATALO: case CP0_REG28__DATALO1: case CP0_REG28__DATALO2: case CP0_REG28__DATALO3: - gen_helper_mtc0_datalo(cpu_env, arg); + gen_helper_mtc0_datalo(tcg_env, arg); register_name =3D "DataLo"; break; default: @@ -8271,14 +8271,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, = int reg, int sel) case CP0_REG29__TAGHI1: case CP0_REG29__TAGHI2: case CP0_REG29__TAGHI3: - gen_helper_mtc0_taghi(cpu_env, arg); + gen_helper_mtc0_taghi(tcg_env, arg); register_name =3D "TagHi"; break; case CP0_REG29__DATAHI: case CP0_REG29__DATAHI1: case CP0_REG29__DATAHI2: case CP0_REG29__DATAHI3: - gen_helper_mtc0_datahi(cpu_env, arg); + gen_helper_mtc0_datahi(tcg_env, arg); register_name =3D "DataHi"; break; default: @@ -8289,7 +8289,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REGISTER_30: switch (sel) { case CP0_REG30__ERROREPC: - tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEP= C)); + tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_ErrorEP= C)); register_name =3D "ErrorEPC"; break; default: @@ -8310,7 +8310,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, in= t reg, int sel) case CP0_REG31__KSCRATCH5: case CP0_REG31__KSCRATCH6: CP0_CHECK(ctx->kscrexist & (1 << sel)); - tcg_gen_st_tl(arg, cpu_env, + tcg_gen_st_tl(arg, tcg_env, offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); register_name =3D "KScratch"; break; @@ -8358,10 +8358,10 @@ static void gen_mftr(CPUMIPSState *env, DisasContex= t *ctx, int rt, int rd, case 1: switch (sel) { case 1: - gen_helper_mftc0_vpecontrol(t0, cpu_env); + gen_helper_mftc0_vpecontrol(t0, tcg_env); break; case 2: - gen_helper_mftc0_vpeconf0(t0, cpu_env); + gen_helper_mftc0_vpeconf0(t0, tcg_env); break; default: goto die; @@ -8371,25 +8371,25 @@ static void gen_mftr(CPUMIPSState *env, DisasContex= t *ctx, int rt, int rd, case 2: switch (sel) { case 1: - gen_helper_mftc0_tcstatus(t0, cpu_env); + gen_helper_mftc0_tcstatus(t0, tcg_env); break; case 2: - gen_helper_mftc0_tcbind(t0, cpu_env); + gen_helper_mftc0_tcbind(t0, tcg_env); break; case 3: - gen_helper_mftc0_tcrestart(t0, cpu_env); + gen_helper_mftc0_tcrestart(t0, tcg_env); break; case 4: - gen_helper_mftc0_tchalt(t0, cpu_env); + gen_helper_mftc0_tchalt(t0, tcg_env); break; case 5: - gen_helper_mftc0_tccontext(t0, cpu_env); + gen_helper_mftc0_tccontext(t0, tcg_env); break; case 6: - gen_helper_mftc0_tcschedule(t0, cpu_env); + gen_helper_mftc0_tcschedule(t0, tcg_env); break; case 7: - gen_helper_mftc0_tcschefback(t0, cpu_env); + gen_helper_mftc0_tcschefback(t0, tcg_env); break; default: gen_mfc0(ctx, t0, rt, sel); @@ -8399,7 +8399,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext = *ctx, int rt, int rd, case 10: switch (sel) { case 0: - gen_helper_mftc0_entryhi(t0, cpu_env); + gen_helper_mftc0_entryhi(t0, tcg_env); break; default: gen_mfc0(ctx, t0, rt, sel); @@ -8409,7 +8409,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext = *ctx, int rt, int rd, case 12: switch (sel) { case 0: - gen_helper_mftc0_status(t0, cpu_env); + gen_helper_mftc0_status(t0, tcg_env); break; default: gen_mfc0(ctx, t0, rt, sel); @@ -8419,7 +8419,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext = *ctx, int rt, int rd, case 13: switch (sel) { case 0: - gen_helper_mftc0_cause(t0, cpu_env); + gen_helper_mftc0_cause(t0, tcg_env); break; default: goto die; @@ -8429,7 +8429,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext = *ctx, int rt, int rd, case 14: switch (sel) { case 0: - gen_helper_mftc0_epc(t0, cpu_env); + gen_helper_mftc0_epc(t0, tcg_env); break; default: goto die; @@ -8439,7 +8439,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext = *ctx, int rt, int rd, case 15: switch (sel) { case 1: - gen_helper_mftc0_ebase(t0, cpu_env); + gen_helper_mftc0_ebase(t0, tcg_env); break; default: goto die; @@ -8456,7 +8456,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext = *ctx, int rt, int rd, case 5: case 6: case 7: - gen_helper_mftc0_configx(t0, cpu_env, tcg_constant_tl(sel)= ); + gen_helper_mftc0_configx(t0, tcg_env, tcg_constant_tl(sel)= ); break; default: goto die; @@ -8466,7 +8466,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext = *ctx, int rt, int rd, case 23: switch (sel) { case 0: - gen_helper_mftc0_debug(t0, cpu_env); + gen_helper_mftc0_debug(t0, tcg_env); break; default: gen_mfc0(ctx, t0, rt, sel); @@ -8522,7 +8522,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext = *ctx, int rt, int rd, gen_helper_1e0i(mftacx, t0, 3); break; case 16: - gen_helper_mftdsp(t0, cpu_env); + gen_helper_mftdsp(t0, tcg_env); break; default: goto die; @@ -8585,10 +8585,10 @@ static void gen_mttr(CPUMIPSState *env, DisasContex= t *ctx, int rd, int rt, case 1: switch (sel) { case 1: - gen_helper_mttc0_vpecontrol(cpu_env, t0); + gen_helper_mttc0_vpecontrol(tcg_env, t0); break; case 2: - gen_helper_mttc0_vpeconf0(cpu_env, t0); + gen_helper_mttc0_vpeconf0(tcg_env, t0); break; default: goto die; @@ -8598,25 +8598,25 @@ static void gen_mttr(CPUMIPSState *env, DisasContex= t *ctx, int rd, int rt, case 2: switch (sel) { case 1: - gen_helper_mttc0_tcstatus(cpu_env, t0); + gen_helper_mttc0_tcstatus(tcg_env, t0); break; case 2: - gen_helper_mttc0_tcbind(cpu_env, t0); + gen_helper_mttc0_tcbind(tcg_env, t0); break; case 3: - gen_helper_mttc0_tcrestart(cpu_env, t0); + gen_helper_mttc0_tcrestart(tcg_env, t0); break; case 4: - gen_helper_mttc0_tchalt(cpu_env, t0); + gen_helper_mttc0_tchalt(tcg_env, t0); break; case 5: - gen_helper_mttc0_tccontext(cpu_env, t0); + gen_helper_mttc0_tccontext(tcg_env, t0); break; case 6: - gen_helper_mttc0_tcschedule(cpu_env, t0); + gen_helper_mttc0_tcschedule(tcg_env, t0); break; case 7: - gen_helper_mttc0_tcschefback(cpu_env, t0); + gen_helper_mttc0_tcschefback(tcg_env, t0); break; default: gen_mtc0(ctx, t0, rd, sel); @@ -8626,7 +8626,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext = *ctx, int rd, int rt, case 10: switch (sel) { case 0: - gen_helper_mttc0_entryhi(cpu_env, t0); + gen_helper_mttc0_entryhi(tcg_env, t0); break; default: gen_mtc0(ctx, t0, rd, sel); @@ -8636,7 +8636,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext = *ctx, int rd, int rt, case 12: switch (sel) { case 0: - gen_helper_mttc0_status(cpu_env, t0); + gen_helper_mttc0_status(tcg_env, t0); break; default: gen_mtc0(ctx, t0, rd, sel); @@ -8646,7 +8646,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext = *ctx, int rd, int rt, case 13: switch (sel) { case 0: - gen_helper_mttc0_cause(cpu_env, t0); + gen_helper_mttc0_cause(tcg_env, t0); break; default: goto die; @@ -8656,7 +8656,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext = *ctx, int rd, int rt, case 15: switch (sel) { case 1: - gen_helper_mttc0_ebase(cpu_env, t0); + gen_helper_mttc0_ebase(tcg_env, t0); break; default: goto die; @@ -8666,7 +8666,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext = *ctx, int rd, int rt, case 23: switch (sel) { case 0: - gen_helper_mttc0_debug(cpu_env, t0); + gen_helper_mttc0_debug(tcg_env, t0); break; default: gen_mtc0(ctx, t0, rd, sel); @@ -8722,7 +8722,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext = *ctx, int rd, int rt, gen_helper_0e1i(mttacx, t0, 3); break; case 16: - gen_helper_mttdsp(cpu_env, t0); + gen_helper_mttdsp(tcg_env, t0); break; default: goto die; @@ -8849,7 +8849,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *= ctx, uint32_t opc, if (!env->tlb->helper_tlbwi) { goto die; } - gen_helper_tlbwi(cpu_env); + gen_helper_tlbwi(tcg_env); break; case OPC_TLBINV: opn =3D "tlbinv"; @@ -8857,7 +8857,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *= ctx, uint32_t opc, if (!env->tlb->helper_tlbinv) { goto die; } - gen_helper_tlbinv(cpu_env); + gen_helper_tlbinv(tcg_env); } /* treat as nop if TLBINV not supported */ break; case OPC_TLBINVF: @@ -8866,7 +8866,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *= ctx, uint32_t opc, if (!env->tlb->helper_tlbinvf) { goto die; } - gen_helper_tlbinvf(cpu_env); + gen_helper_tlbinvf(tcg_env); } /* treat as nop if TLBINV not supported */ break; case OPC_TLBWR: @@ -8874,21 +8874,21 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, if (!env->tlb->helper_tlbwr) { goto die; } - gen_helper_tlbwr(cpu_env); + gen_helper_tlbwr(tcg_env); break; case OPC_TLBP: opn =3D "tlbp"; if (!env->tlb->helper_tlbp) { goto die; } - gen_helper_tlbp(cpu_env); + gen_helper_tlbp(tcg_env); break; case OPC_TLBR: opn =3D "tlbr"; if (!env->tlb->helper_tlbr) { goto die; } - gen_helper_tlbr(cpu_env); + gen_helper_tlbr(tcg_env); break; case OPC_ERET: /* OPC_ERETNC */ if ((ctx->insn_flags & ISA_MIPS_R6) && @@ -8900,12 +8900,12 @@ static void gen_cp0(CPUMIPSState *env, DisasContext= *ctx, uint32_t opc, /* OPC_ERETNC */ opn =3D "eretnc"; check_insn(ctx, ISA_MIPS_R5); - gen_helper_eretnc(cpu_env); + gen_helper_eretnc(tcg_env); } else { /* OPC_ERET */ opn =3D "eret"; check_insn(ctx, ISA_MIPS2); - gen_helper_eret(cpu_env); + gen_helper_eret(tcg_env); } ctx->base.is_jmp =3D DISAS_EXIT; } @@ -8921,7 +8921,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *= ctx, uint32_t opc, MIPS_INVAL(opn); gen_reserved_instruction(ctx); } else { - gen_helper_deret(cpu_env); + gen_helper_deret(tcg_env); ctx->base.is_jmp =3D DISAS_EXIT; } break; @@ -8936,7 +8936,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *= ctx, uint32_t opc, ctx->base.pc_next +=3D 4; save_cpu_state(ctx, 1); ctx->base.pc_next -=3D 4; - gen_helper_wait(cpu_env); + gen_helper_wait(tcg_env); ctx->base.is_jmp =3D DISAS_NORETURN; break; default: @@ -9557,7 +9557,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); - gen_helper_float_add_s(fp0, cpu_env, fp0, fp1); + gen_helper_float_add_s(fp0, tcg_env, fp0, fp1); gen_store_fpr32(ctx, fp0, fd); } break; @@ -9568,7 +9568,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); - gen_helper_float_sub_s(fp0, cpu_env, fp0, fp1); + gen_helper_float_sub_s(fp0, tcg_env, fp0, fp1); gen_store_fpr32(ctx, fp0, fd); } break; @@ -9579,7 +9579,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); - gen_helper_float_mul_s(fp0, cpu_env, fp0, fp1); + gen_helper_float_mul_s(fp0, tcg_env, fp0, fp1); gen_store_fpr32(ctx, fp0, fd); } break; @@ -9590,7 +9590,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); - gen_helper_float_div_s(fp0, cpu_env, fp0, fp1); + gen_helper_float_div_s(fp0, tcg_env, fp0, fp1); gen_store_fpr32(ctx, fp0, fd); } break; @@ -9599,7 +9599,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, TCGv_i32 fp0 =3D tcg_temp_new_i32(); =20 gen_load_fpr32(ctx, fp0, fs); - gen_helper_float_sqrt_s(fp0, cpu_env, fp0); + gen_helper_float_sqrt_s(fp0, tcg_env, fp0); gen_store_fpr32(ctx, fp0, fd); } break; @@ -9645,9 +9645,9 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp32, fs); if (ctx->nan2008) { - gen_helper_float_round_2008_l_s(fp64, cpu_env, fp32); + gen_helper_float_round_2008_l_s(fp64, tcg_env, fp32); } else { - gen_helper_float_round_l_s(fp64, cpu_env, fp32); + gen_helper_float_round_l_s(fp64, tcg_env, fp32); } gen_store_fpr64(ctx, fp64, fd); } @@ -9660,9 +9660,9 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp32, fs); if (ctx->nan2008) { - gen_helper_float_trunc_2008_l_s(fp64, cpu_env, fp32); + gen_helper_float_trunc_2008_l_s(fp64, tcg_env, fp32); } else { - gen_helper_float_trunc_l_s(fp64, cpu_env, fp32); + gen_helper_float_trunc_l_s(fp64, tcg_env, fp32); } gen_store_fpr64(ctx, fp64, fd); } @@ -9675,9 +9675,9 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp32, fs); if (ctx->nan2008) { - gen_helper_float_ceil_2008_l_s(fp64, cpu_env, fp32); + gen_helper_float_ceil_2008_l_s(fp64, tcg_env, fp32); } else { - gen_helper_float_ceil_l_s(fp64, cpu_env, fp32); + gen_helper_float_ceil_l_s(fp64, tcg_env, fp32); } gen_store_fpr64(ctx, fp64, fd); } @@ -9690,9 +9690,9 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp32, fs); if (ctx->nan2008) { - gen_helper_float_floor_2008_l_s(fp64, cpu_env, fp32); + gen_helper_float_floor_2008_l_s(fp64, tcg_env, fp32); } else { - gen_helper_float_floor_l_s(fp64, cpu_env, fp32); + gen_helper_float_floor_l_s(fp64, tcg_env, fp32); } gen_store_fpr64(ctx, fp64, fd); } @@ -9703,9 +9703,9 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp0, fs); if (ctx->nan2008) { - gen_helper_float_round_2008_w_s(fp0, cpu_env, fp0); + gen_helper_float_round_2008_w_s(fp0, tcg_env, fp0); } else { - gen_helper_float_round_w_s(fp0, cpu_env, fp0); + gen_helper_float_round_w_s(fp0, tcg_env, fp0); } gen_store_fpr32(ctx, fp0, fd); } @@ -9716,9 +9716,9 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp0, fs); if (ctx->nan2008) { - gen_helper_float_trunc_2008_w_s(fp0, cpu_env, fp0); + gen_helper_float_trunc_2008_w_s(fp0, tcg_env, fp0); } else { - gen_helper_float_trunc_w_s(fp0, cpu_env, fp0); + gen_helper_float_trunc_w_s(fp0, tcg_env, fp0); } gen_store_fpr32(ctx, fp0, fd); } @@ -9729,9 +9729,9 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp0, fs); if (ctx->nan2008) { - gen_helper_float_ceil_2008_w_s(fp0, cpu_env, fp0); + gen_helper_float_ceil_2008_w_s(fp0, tcg_env, fp0); } else { - gen_helper_float_ceil_w_s(fp0, cpu_env, fp0); + gen_helper_float_ceil_w_s(fp0, tcg_env, fp0); } gen_store_fpr32(ctx, fp0, fd); } @@ -9742,9 +9742,9 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp0, fs); if (ctx->nan2008) { - gen_helper_float_floor_2008_w_s(fp0, cpu_env, fp0); + gen_helper_float_floor_2008_w_s(fp0, tcg_env, fp0); } else { - gen_helper_float_floor_w_s(fp0, cpu_env, fp0); + gen_helper_float_floor_w_s(fp0, tcg_env, fp0); } gen_store_fpr32(ctx, fp0, fd); } @@ -9800,7 +9800,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, TCGv_i32 fp0 =3D tcg_temp_new_i32(); =20 gen_load_fpr32(ctx, fp0, fs); - gen_helper_float_recip_s(fp0, cpu_env, fp0); + gen_helper_float_recip_s(fp0, tcg_env, fp0); gen_store_fpr32(ctx, fp0, fd); } break; @@ -9809,7 +9809,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, TCGv_i32 fp0 =3D tcg_temp_new_i32(); =20 gen_load_fpr32(ctx, fp0, fs); - gen_helper_float_rsqrt_s(fp0, cpu_env, fp0); + gen_helper_float_rsqrt_s(fp0, tcg_env, fp0); gen_store_fpr32(ctx, fp0, fd); } break; @@ -9822,7 +9822,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fd); - gen_helper_float_maddf_s(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_maddf_s(fp2, tcg_env, fp0, fp1, fp2); gen_store_fpr32(ctx, fp2, fd); } break; @@ -9835,7 +9835,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fd); - gen_helper_float_msubf_s(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_msubf_s(fp2, tcg_env, fp0, fp1, fp2); gen_store_fpr32(ctx, fp2, fd); } break; @@ -9844,7 +9844,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, { TCGv_i32 fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); - gen_helper_float_rint_s(fp0, cpu_env, fp0); + gen_helper_float_rint_s(fp0, tcg_env, fp0); gen_store_fpr32(ctx, fp0, fd); } break; @@ -9853,7 +9853,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, { TCGv_i32 fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); - gen_helper_float_class_s(fp0, cpu_env, fp0); + gen_helper_float_class_s(fp0, tcg_env, fp0); gen_store_fpr32(ctx, fp0, fd); } break; @@ -9865,7 +9865,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, TCGv_i32 fp2 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); - gen_helper_float_min_s(fp2, cpu_env, fp0, fp1); + gen_helper_float_min_s(fp2, tcg_env, fp0, fp1); gen_store_fpr32(ctx, fp2, fd); } else { /* OPC_RECIP2_S */ @@ -9876,7 +9876,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); - gen_helper_float_recip2_s(fp0, cpu_env, fp0, fp1); + gen_helper_float_recip2_s(fp0, tcg_env, fp0, fp1); gen_store_fpr32(ctx, fp0, fd); } } @@ -9889,7 +9889,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, TCGv_i32 fp2 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); - gen_helper_float_mina_s(fp2, cpu_env, fp0, fp1); + gen_helper_float_mina_s(fp2, tcg_env, fp0, fp1); gen_store_fpr32(ctx, fp2, fd); } else { /* OPC_RECIP1_S */ @@ -9898,7 +9898,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, TCGv_i32 fp0 =3D tcg_temp_new_i32(); =20 gen_load_fpr32(ctx, fp0, fs); - gen_helper_float_recip1_s(fp0, cpu_env, fp0); + gen_helper_float_recip1_s(fp0, tcg_env, fp0); gen_store_fpr32(ctx, fp0, fd); } } @@ -9910,7 +9910,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, TCGv_i32 fp1 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); - gen_helper_float_max_s(fp1, cpu_env, fp0, fp1); + gen_helper_float_max_s(fp1, tcg_env, fp0, fp1); gen_store_fpr32(ctx, fp1, fd); } else { /* OPC_RSQRT1_S */ @@ -9919,7 +9919,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, TCGv_i32 fp0 =3D tcg_temp_new_i32(); =20 gen_load_fpr32(ctx, fp0, fs); - gen_helper_float_rsqrt1_s(fp0, cpu_env, fp0); + gen_helper_float_rsqrt1_s(fp0, tcg_env, fp0); gen_store_fpr32(ctx, fp0, fd); } } @@ -9931,7 +9931,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, TCGv_i32 fp1 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); - gen_helper_float_maxa_s(fp1, cpu_env, fp0, fp1); + gen_helper_float_maxa_s(fp1, tcg_env, fp0, fp1); gen_store_fpr32(ctx, fp1, fd); } else { /* OPC_RSQRT2_S */ @@ -9942,7 +9942,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); - gen_helper_float_rsqrt2_s(fp0, cpu_env, fp0, fp1); + gen_helper_float_rsqrt2_s(fp0, tcg_env, fp0, fp1); gen_store_fpr32(ctx, fp0, fd); } } @@ -9954,7 +9954,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, TCGv_i64 fp64 =3D tcg_temp_new_i64(); =20 gen_load_fpr32(ctx, fp32, fs); - gen_helper_float_cvtd_s(fp64, cpu_env, fp32); + gen_helper_float_cvtd_s(fp64, tcg_env, fp32); gen_store_fpr64(ctx, fp64, fd); } break; @@ -9964,9 +9964,9 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp0, fs); if (ctx->nan2008) { - gen_helper_float_cvt_2008_w_s(fp0, cpu_env, fp0); + gen_helper_float_cvt_2008_w_s(fp0, tcg_env, fp0); } else { - gen_helper_float_cvt_w_s(fp0, cpu_env, fp0); + gen_helper_float_cvt_w_s(fp0, tcg_env, fp0); } gen_store_fpr32(ctx, fp0, fd); } @@ -9979,9 +9979,9 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp32, fs); if (ctx->nan2008) { - gen_helper_float_cvt_2008_l_s(fp64, cpu_env, fp32); + gen_helper_float_cvt_2008_l_s(fp64, tcg_env, fp32); } else { - gen_helper_float_cvt_l_s(fp64, cpu_env, fp32); + gen_helper_float_cvt_l_s(fp64, tcg_env, fp32); } gen_store_fpr64(ctx, fp64, fd); } @@ -10030,7 +10030,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_add_d(fp0, cpu_env, fp0, fp1); + gen_helper_float_add_d(fp0, tcg_env, fp0, fp1); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10042,7 +10042,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_sub_d(fp0, cpu_env, fp0, fp1); + gen_helper_float_sub_d(fp0, tcg_env, fp0, fp1); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10054,7 +10054,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_mul_d(fp0, cpu_env, fp0, fp1); + gen_helper_float_mul_d(fp0, tcg_env, fp0, fp1); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10066,7 +10066,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_div_d(fp0, cpu_env, fp0, fp1); + gen_helper_float_div_d(fp0, tcg_env, fp0, fp1); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10076,7 +10076,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i64 fp0 =3D tcg_temp_new_i64(); =20 gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_sqrt_d(fp0, cpu_env, fp0); + gen_helper_float_sqrt_d(fp0, tcg_env, fp0); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10124,9 +10124,9 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); if (ctx->nan2008) { - gen_helper_float_round_2008_l_d(fp0, cpu_env, fp0); + gen_helper_float_round_2008_l_d(fp0, tcg_env, fp0); } else { - gen_helper_float_round_l_d(fp0, cpu_env, fp0); + gen_helper_float_round_l_d(fp0, tcg_env, fp0); } gen_store_fpr64(ctx, fp0, fd); } @@ -10138,9 +10138,9 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); if (ctx->nan2008) { - gen_helper_float_trunc_2008_l_d(fp0, cpu_env, fp0); + gen_helper_float_trunc_2008_l_d(fp0, tcg_env, fp0); } else { - gen_helper_float_trunc_l_d(fp0, cpu_env, fp0); + gen_helper_float_trunc_l_d(fp0, tcg_env, fp0); } gen_store_fpr64(ctx, fp0, fd); } @@ -10152,9 +10152,9 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); if (ctx->nan2008) { - gen_helper_float_ceil_2008_l_d(fp0, cpu_env, fp0); + gen_helper_float_ceil_2008_l_d(fp0, tcg_env, fp0); } else { - gen_helper_float_ceil_l_d(fp0, cpu_env, fp0); + gen_helper_float_ceil_l_d(fp0, tcg_env, fp0); } gen_store_fpr64(ctx, fp0, fd); } @@ -10166,9 +10166,9 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); if (ctx->nan2008) { - gen_helper_float_floor_2008_l_d(fp0, cpu_env, fp0); + gen_helper_float_floor_2008_l_d(fp0, tcg_env, fp0); } else { - gen_helper_float_floor_l_d(fp0, cpu_env, fp0); + gen_helper_float_floor_l_d(fp0, tcg_env, fp0); } gen_store_fpr64(ctx, fp0, fd); } @@ -10181,9 +10181,9 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp64, fs); if (ctx->nan2008) { - gen_helper_float_round_2008_w_d(fp32, cpu_env, fp64); + gen_helper_float_round_2008_w_d(fp32, tcg_env, fp64); } else { - gen_helper_float_round_w_d(fp32, cpu_env, fp64); + gen_helper_float_round_w_d(fp32, tcg_env, fp64); } gen_store_fpr32(ctx, fp32, fd); } @@ -10196,9 +10196,9 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp64, fs); if (ctx->nan2008) { - gen_helper_float_trunc_2008_w_d(fp32, cpu_env, fp64); + gen_helper_float_trunc_2008_w_d(fp32, tcg_env, fp64); } else { - gen_helper_float_trunc_w_d(fp32, cpu_env, fp64); + gen_helper_float_trunc_w_d(fp32, tcg_env, fp64); } gen_store_fpr32(ctx, fp32, fd); } @@ -10211,9 +10211,9 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp64, fs); if (ctx->nan2008) { - gen_helper_float_ceil_2008_w_d(fp32, cpu_env, fp64); + gen_helper_float_ceil_2008_w_d(fp32, tcg_env, fp64); } else { - gen_helper_float_ceil_w_d(fp32, cpu_env, fp64); + gen_helper_float_ceil_w_d(fp32, tcg_env, fp64); } gen_store_fpr32(ctx, fp32, fd); } @@ -10226,9 +10226,9 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp64, fs); if (ctx->nan2008) { - gen_helper_float_floor_2008_w_d(fp32, cpu_env, fp64); + gen_helper_float_floor_2008_w_d(fp32, tcg_env, fp64); } else { - gen_helper_float_floor_w_d(fp32, cpu_env, fp64); + gen_helper_float_floor_w_d(fp32, tcg_env, fp64); } gen_store_fpr32(ctx, fp32, fd); } @@ -10285,7 +10285,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i64 fp0 =3D tcg_temp_new_i64(); =20 gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_recip_d(fp0, cpu_env, fp0); + gen_helper_float_recip_d(fp0, tcg_env, fp0); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10295,7 +10295,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i64 fp0 =3D tcg_temp_new_i64(); =20 gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_rsqrt_d(fp0, cpu_env, fp0); + gen_helper_float_rsqrt_d(fp0, tcg_env, fp0); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10308,7 +10308,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fd); - gen_helper_float_maddf_d(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_maddf_d(fp2, tcg_env, fp0, fp1, fp2); gen_store_fpr64(ctx, fp2, fd); } break; @@ -10321,7 +10321,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fd); - gen_helper_float_msubf_d(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_msubf_d(fp2, tcg_env, fp0, fp1, fp2); gen_store_fpr64(ctx, fp2, fd); } break; @@ -10330,7 +10330,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, { TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_rint_d(fp0, cpu_env, fp0); + gen_helper_float_rint_d(fp0, tcg_env, fp0); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10339,7 +10339,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, { TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_class_d(fp0, cpu_env, fp0); + gen_helper_float_class_d(fp0, tcg_env, fp0); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10350,7 +10350,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i64 fp1 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_min_d(fp1, cpu_env, fp0, fp1); + gen_helper_float_min_d(fp1, tcg_env, fp0, fp1); gen_store_fpr64(ctx, fp1, fd); } else { /* OPC_RECIP2_D */ @@ -10361,7 +10361,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_recip2_d(fp0, cpu_env, fp0, fp1); + gen_helper_float_recip2_d(fp0, tcg_env, fp0, fp1); gen_store_fpr64(ctx, fp0, fd); } } @@ -10373,7 +10373,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i64 fp1 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_mina_d(fp1, cpu_env, fp0, fp1); + gen_helper_float_mina_d(fp1, tcg_env, fp0, fp1); gen_store_fpr64(ctx, fp1, fd); } else { /* OPC_RECIP1_D */ @@ -10382,7 +10382,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i64 fp0 =3D tcg_temp_new_i64(); =20 gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_recip1_d(fp0, cpu_env, fp0); + gen_helper_float_recip1_d(fp0, tcg_env, fp0); gen_store_fpr64(ctx, fp0, fd); } } @@ -10394,7 +10394,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i64 fp1 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_max_d(fp1, cpu_env, fp0, fp1); + gen_helper_float_max_d(fp1, tcg_env, fp0, fp1); gen_store_fpr64(ctx, fp1, fd); } else { /* OPC_RSQRT1_D */ @@ -10403,7 +10403,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i64 fp0 =3D tcg_temp_new_i64(); =20 gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_rsqrt1_d(fp0, cpu_env, fp0); + gen_helper_float_rsqrt1_d(fp0, tcg_env, fp0); gen_store_fpr64(ctx, fp0, fd); } } @@ -10415,7 +10415,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i64 fp1 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_maxa_d(fp1, cpu_env, fp0, fp1); + gen_helper_float_maxa_d(fp1, tcg_env, fp0, fp1); gen_store_fpr64(ctx, fp1, fd); } else { /* OPC_RSQRT2_D */ @@ -10426,7 +10426,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_rsqrt2_d(fp0, cpu_env, fp0, fp1); + gen_helper_float_rsqrt2_d(fp0, tcg_env, fp0, fp1); gen_store_fpr64(ctx, fp0, fd); } } @@ -10461,7 +10461,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i64 fp64 =3D tcg_temp_new_i64(); =20 gen_load_fpr64(ctx, fp64, fs); - gen_helper_float_cvts_d(fp32, cpu_env, fp64); + gen_helper_float_cvts_d(fp32, tcg_env, fp64); gen_store_fpr32(ctx, fp32, fd); } break; @@ -10473,9 +10473,9 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp64, fs); if (ctx->nan2008) { - gen_helper_float_cvt_2008_w_d(fp32, cpu_env, fp64); + gen_helper_float_cvt_2008_w_d(fp32, tcg_env, fp64); } else { - gen_helper_float_cvt_w_d(fp32, cpu_env, fp64); + gen_helper_float_cvt_w_d(fp32, tcg_env, fp64); } gen_store_fpr32(ctx, fp32, fd); } @@ -10487,9 +10487,9 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); if (ctx->nan2008) { - gen_helper_float_cvt_2008_l_d(fp0, cpu_env, fp0); + gen_helper_float_cvt_2008_l_d(fp0, tcg_env, fp0); } else { - gen_helper_float_cvt_l_d(fp0, cpu_env, fp0); + gen_helper_float_cvt_l_d(fp0, tcg_env, fp0); } gen_store_fpr64(ctx, fp0, fd); } @@ -10499,7 +10499,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i32 fp0 =3D tcg_temp_new_i32(); =20 gen_load_fpr32(ctx, fp0, fs); - gen_helper_float_cvts_w(fp0, cpu_env, fp0); + gen_helper_float_cvts_w(fp0, tcg_env, fp0); gen_store_fpr32(ctx, fp0, fd); } break; @@ -10510,7 +10510,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i64 fp64 =3D tcg_temp_new_i64(); =20 gen_load_fpr32(ctx, fp32, fs); - gen_helper_float_cvtd_w(fp64, cpu_env, fp32); + gen_helper_float_cvtd_w(fp64, tcg_env, fp32); gen_store_fpr64(ctx, fp64, fd); } break; @@ -10521,7 +10521,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i64 fp64 =3D tcg_temp_new_i64(); =20 gen_load_fpr64(ctx, fp64, fs); - gen_helper_float_cvts_l(fp32, cpu_env, fp64); + gen_helper_float_cvts_l(fp32, tcg_env, fp64); gen_store_fpr32(ctx, fp32, fd); } break; @@ -10531,7 +10531,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i64 fp0 =3D tcg_temp_new_i64(); =20 gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_cvtd_l(fp0, cpu_env, fp0); + gen_helper_float_cvtd_l(fp0, tcg_env, fp0); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10541,7 +10541,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i64 fp0 =3D tcg_temp_new_i64(); =20 gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_cvtps_pw(fp0, cpu_env, fp0); + gen_helper_float_cvtps_pw(fp0, tcg_env, fp0); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10553,7 +10553,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_add_ps(fp0, cpu_env, fp0, fp1); + gen_helper_float_add_ps(fp0, tcg_env, fp0, fp1); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10565,7 +10565,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_sub_ps(fp0, cpu_env, fp0, fp1); + gen_helper_float_sub_ps(fp0, tcg_env, fp0, fp1); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10577,7 +10577,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_mul_ps(fp0, cpu_env, fp0, fp1); + gen_helper_float_mul_ps(fp0, tcg_env, fp0, fp1); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10652,7 +10652,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, ft); gen_load_fpr64(ctx, fp1, fs); - gen_helper_float_addr_ps(fp0, cpu_env, fp0, fp1); + gen_helper_float_addr_ps(fp0, tcg_env, fp0, fp1); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10664,7 +10664,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, ft); gen_load_fpr64(ctx, fp1, fs); - gen_helper_float_mulr_ps(fp0, cpu_env, fp0, fp1); + gen_helper_float_mulr_ps(fp0, tcg_env, fp0, fp1); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10676,7 +10676,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_recip2_ps(fp0, cpu_env, fp0, fp1); + gen_helper_float_recip2_ps(fp0, tcg_env, fp0, fp1); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10686,7 +10686,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i64 fp0 =3D tcg_temp_new_i64(); =20 gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_recip1_ps(fp0, cpu_env, fp0); + gen_helper_float_recip1_ps(fp0, tcg_env, fp0); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10696,7 +10696,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i64 fp0 =3D tcg_temp_new_i64(); =20 gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_rsqrt1_ps(fp0, cpu_env, fp0); + gen_helper_float_rsqrt1_ps(fp0, tcg_env, fp0); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10708,7 +10708,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); - gen_helper_float_rsqrt2_ps(fp0, cpu_env, fp0, fp1); + gen_helper_float_rsqrt2_ps(fp0, tcg_env, fp0, fp1); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10718,7 +10718,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i32 fp0 =3D tcg_temp_new_i32(); =20 gen_load_fpr32h(ctx, fp0, fs); - gen_helper_float_cvts_pu(fp0, cpu_env, fp0); + gen_helper_float_cvts_pu(fp0, tcg_env, fp0); gen_store_fpr32(ctx, fp0, fd); } break; @@ -10728,7 +10728,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i64 fp0 =3D tcg_temp_new_i64(); =20 gen_load_fpr64(ctx, fp0, fs); - gen_helper_float_cvtpw_ps(fp0, cpu_env, fp0); + gen_helper_float_cvtpw_ps(fp0, tcg_env, fp0); gen_store_fpr64(ctx, fp0, fd); } break; @@ -10738,7 +10738,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, TCGv_i32 fp0 =3D tcg_temp_new_i32(); =20 gen_load_fpr32(ctx, fp0, fs); - gen_helper_float_cvts_pl(fp0, cpu_env, fp0); + gen_helper_float_cvts_pl(fp0, tcg_env, fp0); gen_store_fpr32(ctx, fp0, fd); } break; @@ -10943,7 +10943,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fr); - gen_helper_float_madd_s(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_madd_s(fp2, tcg_env, fp0, fp1, fp2); gen_store_fpr32(ctx, fp2, fd); } break; @@ -10958,7 +10958,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_madd_d(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_madd_d(fp2, tcg_env, fp0, fp1, fp2); gen_store_fpr64(ctx, fp2, fd); } break; @@ -10972,7 +10972,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_madd_ps(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_madd_ps(fp2, tcg_env, fp0, fp1, fp2); gen_store_fpr64(ctx, fp2, fd); } break; @@ -10986,7 +10986,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fr); - gen_helper_float_msub_s(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_msub_s(fp2, tcg_env, fp0, fp1, fp2); gen_store_fpr32(ctx, fp2, fd); } break; @@ -11001,7 +11001,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_msub_d(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_msub_d(fp2, tcg_env, fp0, fp1, fp2); gen_store_fpr64(ctx, fp2, fd); } break; @@ -11015,7 +11015,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_msub_ps(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_msub_ps(fp2, tcg_env, fp0, fp1, fp2); gen_store_fpr64(ctx, fp2, fd); } break; @@ -11029,7 +11029,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fr); - gen_helper_float_nmadd_s(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_nmadd_s(fp2, tcg_env, fp0, fp1, fp2); gen_store_fpr32(ctx, fp2, fd); } break; @@ -11044,7 +11044,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_nmadd_d(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_nmadd_d(fp2, tcg_env, fp0, fp1, fp2); gen_store_fpr64(ctx, fp2, fd); } break; @@ -11058,7 +11058,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_nmadd_ps(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_nmadd_ps(fp2, tcg_env, fp0, fp1, fp2); gen_store_fpr64(ctx, fp2, fd); } break; @@ -11072,7 +11072,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fr); - gen_helper_float_nmsub_s(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_nmsub_s(fp2, tcg_env, fp0, fp1, fp2); gen_store_fpr32(ctx, fp2, fd); } break; @@ -11087,7 +11087,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_nmsub_d(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_nmsub_d(fp2, tcg_env, fp0, fp1, fp2); gen_store_fpr64(ctx, fp2, fd); } break; @@ -11101,7 +11101,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_nmsub_ps(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_nmsub_ps(fp2, tcg_env, fp0, fp1, fp2); gen_store_fpr64(ctx, fp2, fd); } break; @@ -11127,16 +11127,16 @@ void gen_rdhwr(DisasContext *ctx, int rt, int rd,= int sel) =20 switch (rd) { case 0: - gen_helper_rdhwr_cpunum(t0, cpu_env); + gen_helper_rdhwr_cpunum(t0, tcg_env); gen_store_gpr(t0, rt); break; case 1: - gen_helper_rdhwr_synci_step(t0, cpu_env); + gen_helper_rdhwr_synci_step(t0, tcg_env); gen_store_gpr(t0, rt); break; case 2: translator_io_start(&ctx->base); - gen_helper_rdhwr_cc(t0, cpu_env); + gen_helper_rdhwr_cc(t0, tcg_env); gen_store_gpr(t0, rt); /* * Break the TB to be able to take timer interrupts immediately @@ -11147,7 +11147,7 @@ void gen_rdhwr(DisasContext *ctx, int rt, int rd, i= nt sel) ctx->base.is_jmp =3D DISAS_EXIT; break; case 3: - gen_helper_rdhwr_ccres(t0, cpu_env); + gen_helper_rdhwr_ccres(t0, tcg_env); gen_store_gpr(t0, rt); break; case 4: @@ -11159,24 +11159,24 @@ void gen_rdhwr(DisasContext *ctx, int rt, int rd,= int sel) */ generate_exception(ctx, EXCP_RI); } - gen_helper_rdhwr_performance(t0, cpu_env); + gen_helper_rdhwr_performance(t0, tcg_env); gen_store_gpr(t0, rt); break; case 5: check_insn(ctx, ISA_MIPS_R6); - gen_helper_rdhwr_xnp(t0, cpu_env); + gen_helper_rdhwr_xnp(t0, tcg_env); gen_store_gpr(t0, rt); break; case 29: #if defined(CONFIG_USER_ONLY) - tcg_gen_ld_tl(t0, cpu_env, + tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); gen_store_gpr(t0, rt); break; #else if ((ctx->hflags & MIPS_HFLAG_CP0) || (ctx->hflags & MIPS_HFLAG_HWRENA_ULR)) { - tcg_gen_ld_tl(t0, cpu_env, + tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); gen_store_gpr(t0, rt); } else { @@ -11514,7 +11514,7 @@ static void gen_cache_operation(DisasContext *ctx, = uint32_t op, int base, TCGv_i32 t0 =3D tcg_constant_i32(op); TCGv t1 =3D tcg_temp_new(); gen_base_offset_addr(ctx, t1, base, offset); - gen_helper_cache(cpu_env, t1, t0); + gen_helper_cache(tcg_env, t1, t0); } =20 static inline bool is_uhi(DisasContext *ctx, int sdbbp_code) @@ -11711,15 +11711,15 @@ static void gen_mipsdsp_arith(DisasContext *ctx, = uint32_t op1, uint32_t op2, switch (op2) { case OPC_ABSQ_S_QB: check_dsp_r2(ctx); - gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, cpu_env); + gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, tcg_env); break; case OPC_ABSQ_S_PH: check_dsp(ctx); - gen_helper_absq_s_ph(cpu_gpr[ret], v2_t, cpu_env); + gen_helper_absq_s_ph(cpu_gpr[ret], v2_t, tcg_env); break; case OPC_ABSQ_S_W: check_dsp(ctx); - gen_helper_absq_s_w(cpu_gpr[ret], v2_t, cpu_env); + gen_helper_absq_s_w(cpu_gpr[ret], v2_t, tcg_env); break; case OPC_PRECEQ_W_PHL: check_dsp(ctx); @@ -11770,67 +11770,67 @@ static void gen_mipsdsp_arith(DisasContext *ctx, = uint32_t op1, uint32_t op2, switch (op2) { case OPC_ADDQ_PH: check_dsp(ctx); - gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_ADDQ_S_PH: check_dsp(ctx); - gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_ADDQ_S_W: check_dsp(ctx); - gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_ADDU_QB: check_dsp(ctx); - gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_ADDU_S_QB: check_dsp(ctx); - gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_ADDU_PH: check_dsp_r2(ctx); - gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_ADDU_S_PH: check_dsp_r2(ctx); - gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SUBQ_PH: check_dsp(ctx); - gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SUBQ_S_PH: check_dsp(ctx); - gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SUBQ_S_W: check_dsp(ctx); - gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SUBU_QB: check_dsp(ctx); - gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SUBU_S_QB: check_dsp(ctx); - gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SUBU_PH: check_dsp_r2(ctx); - gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SUBU_S_PH: check_dsp_r2(ctx); - gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_ADDSC: check_dsp(ctx); - gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_ADDWC: check_dsp(ctx); - gen_helper_addwc(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_addwc(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_MODSUB: check_dsp(ctx); @@ -11874,11 +11874,11 @@ static void gen_mipsdsp_arith(DisasContext *ctx, = uint32_t op1, uint32_t op2, break; case OPC_PRECRQ_RS_PH_W: check_dsp(ctx); - gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_PRECRQU_S_QB_PH: check_dsp(ctx); - gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; } break; @@ -11943,15 +11943,15 @@ static void gen_mipsdsp_arith(DisasContext *ctx, = uint32_t op1, uint32_t op2, break; case OPC_ABSQ_S_OB: check_dsp_r2(ctx); - gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, cpu_env); + gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, tcg_env); break; case OPC_ABSQ_S_PW: check_dsp(ctx); - gen_helper_absq_s_pw(cpu_gpr[ret], v2_t, cpu_env); + gen_helper_absq_s_pw(cpu_gpr[ret], v2_t, tcg_env); break; case OPC_ABSQ_S_QH: check_dsp(ctx); - gen_helper_absq_s_qh(cpu_gpr[ret], v2_t, cpu_env); + gen_helper_absq_s_qh(cpu_gpr[ret], v2_t, tcg_env); break; } break; @@ -11963,35 +11963,35 @@ static void gen_mipsdsp_arith(DisasContext *ctx, = uint32_t op1, uint32_t op2, break; case OPC_SUBQ_PW: check_dsp(ctx); - gen_helper_subq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_subq_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SUBQ_S_PW: check_dsp(ctx); - gen_helper_subq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_subq_s_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SUBQ_QH: check_dsp(ctx); - gen_helper_subq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_subq_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SUBQ_S_QH: check_dsp(ctx); - gen_helper_subq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_subq_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SUBU_OB: check_dsp(ctx); - gen_helper_subu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_subu_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SUBU_S_OB: check_dsp(ctx); - gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SUBU_QH: check_dsp_r2(ctx); - gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SUBU_S_QH: check_dsp_r2(ctx); - gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SUBUH_OB: check_dsp_r2(ctx); @@ -12003,35 +12003,35 @@ static void gen_mipsdsp_arith(DisasContext *ctx, = uint32_t op1, uint32_t op2, break; case OPC_ADDQ_PW: check_dsp(ctx); - gen_helper_addq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_addq_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_ADDQ_S_PW: check_dsp(ctx); - gen_helper_addq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_addq_s_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_ADDQ_QH: check_dsp(ctx); - gen_helper_addq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_addq_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_ADDQ_S_QH: check_dsp(ctx); - gen_helper_addq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_addq_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_ADDU_OB: check_dsp(ctx); - gen_helper_addu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_addu_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_ADDU_S_OB: check_dsp(ctx); - gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_ADDU_QH: check_dsp_r2(ctx); - gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_ADDU_S_QH: check_dsp_r2(ctx); - gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_ADDUH_OB: check_dsp_r2(ctx); @@ -12077,11 +12077,11 @@ static void gen_mipsdsp_arith(DisasContext *ctx, = uint32_t op1, uint32_t op2, break; case OPC_PRECRQ_RS_QH_PW: check_dsp(ctx); - gen_helper_precrq_rs_qh_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_precrq_rs_qh_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_PRECRQU_S_OB_QH: check_dsp(ctx); - gen_helper_precrqu_s_ob_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_precrqu_s_ob_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; } break; @@ -12117,35 +12117,35 @@ static void gen_mipsdsp_shift(DisasContext *ctx, = uint32_t opc, switch (op2) { case OPC_SHLL_QB: check_dsp(ctx); - gen_helper_shll_qb(cpu_gpr[ret], t0, v2_t, cpu_env); + gen_helper_shll_qb(cpu_gpr[ret], t0, v2_t, tcg_env); break; case OPC_SHLLV_QB: check_dsp(ctx); - gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SHLL_PH: check_dsp(ctx); - gen_helper_shll_ph(cpu_gpr[ret], t0, v2_t, cpu_env); + gen_helper_shll_ph(cpu_gpr[ret], t0, v2_t, tcg_env); break; case OPC_SHLLV_PH: check_dsp(ctx); - gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SHLL_S_PH: check_dsp(ctx); - gen_helper_shll_s_ph(cpu_gpr[ret], t0, v2_t, cpu_env); + gen_helper_shll_s_ph(cpu_gpr[ret], t0, v2_t, tcg_env); break; case OPC_SHLLV_S_PH: check_dsp(ctx); - gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SHLL_S_W: check_dsp(ctx); - gen_helper_shll_s_w(cpu_gpr[ret], t0, v2_t, cpu_env); + gen_helper_shll_s_w(cpu_gpr[ret], t0, v2_t, tcg_env); break; case OPC_SHLLV_S_W: check_dsp(ctx); - gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_SHRL_QB: check_dsp(ctx); @@ -12216,43 +12216,43 @@ static void gen_mipsdsp_shift(DisasContext *ctx, = uint32_t opc, switch (op2) { case OPC_SHLL_PW: check_dsp(ctx); - gen_helper_shll_pw(cpu_gpr[ret], v2_t, t0, cpu_env); + gen_helper_shll_pw(cpu_gpr[ret], v2_t, t0, tcg_env); break; case OPC_SHLLV_PW: check_dsp(ctx); - gen_helper_shll_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env); + gen_helper_shll_pw(cpu_gpr[ret], v2_t, v1_t, tcg_env); break; case OPC_SHLL_S_PW: check_dsp(ctx); - gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, t0, cpu_env); + gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, t0, tcg_env); break; case OPC_SHLLV_S_PW: check_dsp(ctx); - gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env); + gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, v1_t, tcg_env); break; case OPC_SHLL_OB: check_dsp(ctx); - gen_helper_shll_ob(cpu_gpr[ret], v2_t, t0, cpu_env); + gen_helper_shll_ob(cpu_gpr[ret], v2_t, t0, tcg_env); break; case OPC_SHLLV_OB: check_dsp(ctx); - gen_helper_shll_ob(cpu_gpr[ret], v2_t, v1_t, cpu_env); + gen_helper_shll_ob(cpu_gpr[ret], v2_t, v1_t, tcg_env); break; case OPC_SHLL_QH: check_dsp(ctx); - gen_helper_shll_qh(cpu_gpr[ret], v2_t, t0, cpu_env); + gen_helper_shll_qh(cpu_gpr[ret], v2_t, t0, tcg_env); break; case OPC_SHLLV_QH: check_dsp(ctx); - gen_helper_shll_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env); + gen_helper_shll_qh(cpu_gpr[ret], v2_t, v1_t, tcg_env); break; case OPC_SHLL_S_QH: check_dsp(ctx); - gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, t0, cpu_env); + gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, t0, tcg_env); break; case OPC_SHLLV_S_QH: check_dsp(ctx); - gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env); + gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, tcg_env); break; case OPC_SHRA_OB: check_dsp_r2(ctx); @@ -12357,16 +12357,16 @@ static void gen_mipsdsp_multiply(DisasContext *ct= x, uint32_t op1, uint32_t op2, check_dsp_r2(ctx); switch (op2) { case OPC_MUL_PH: - gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_MUL_S_PH: - gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_MULQ_S_W: - gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_MULQ_RS_W: - gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; } break; @@ -12374,91 +12374,91 @@ static void gen_mipsdsp_multiply(DisasContext *ct= x, uint32_t op1, uint32_t op2, switch (op2) { case OPC_DPAU_H_QBL: check_dsp(ctx); - gen_helper_dpau_h_qbl(t0, v1_t, v2_t, cpu_env); + gen_helper_dpau_h_qbl(t0, v1_t, v2_t, tcg_env); break; case OPC_DPAU_H_QBR: check_dsp(ctx); - gen_helper_dpau_h_qbr(t0, v1_t, v2_t, cpu_env); + gen_helper_dpau_h_qbr(t0, v1_t, v2_t, tcg_env); break; case OPC_DPSU_H_QBL: check_dsp(ctx); - gen_helper_dpsu_h_qbl(t0, v1_t, v2_t, cpu_env); + gen_helper_dpsu_h_qbl(t0, v1_t, v2_t, tcg_env); break; case OPC_DPSU_H_QBR: check_dsp(ctx); - gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, cpu_env); + gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, tcg_env); break; case OPC_DPA_W_PH: check_dsp_r2(ctx); - gen_helper_dpa_w_ph(t0, v1_t, v2_t, cpu_env); + gen_helper_dpa_w_ph(t0, v1_t, v2_t, tcg_env); break; case OPC_DPAX_W_PH: check_dsp_r2(ctx); - gen_helper_dpax_w_ph(t0, v1_t, v2_t, cpu_env); + gen_helper_dpax_w_ph(t0, v1_t, v2_t, tcg_env); break; case OPC_DPAQ_S_W_PH: check_dsp(ctx); - gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, cpu_env); + gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, tcg_env); break; case OPC_DPAQX_S_W_PH: check_dsp_r2(ctx); - gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, cpu_env); + gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, tcg_env); break; case OPC_DPAQX_SA_W_PH: check_dsp_r2(ctx); - gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, cpu_env); + gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, tcg_env); break; case OPC_DPS_W_PH: check_dsp_r2(ctx); - gen_helper_dps_w_ph(t0, v1_t, v2_t, cpu_env); + gen_helper_dps_w_ph(t0, v1_t, v2_t, tcg_env); break; case OPC_DPSX_W_PH: check_dsp_r2(ctx); - gen_helper_dpsx_w_ph(t0, v1_t, v2_t, cpu_env); + gen_helper_dpsx_w_ph(t0, v1_t, v2_t, tcg_env); break; case OPC_DPSQ_S_W_PH: check_dsp(ctx); - gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, cpu_env); + gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, tcg_env); break; case OPC_DPSQX_S_W_PH: check_dsp_r2(ctx); - gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, cpu_env); + gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, tcg_env); break; case OPC_DPSQX_SA_W_PH: check_dsp_r2(ctx); - gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, cpu_env); + gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, tcg_env); break; case OPC_MULSAQ_S_W_PH: check_dsp(ctx); - gen_helper_mulsaq_s_w_ph(t0, v1_t, v2_t, cpu_env); + gen_helper_mulsaq_s_w_ph(t0, v1_t, v2_t, tcg_env); break; case OPC_DPAQ_SA_L_W: check_dsp(ctx); - gen_helper_dpaq_sa_l_w(t0, v1_t, v2_t, cpu_env); + gen_helper_dpaq_sa_l_w(t0, v1_t, v2_t, tcg_env); break; case OPC_DPSQ_SA_L_W: check_dsp(ctx); - gen_helper_dpsq_sa_l_w(t0, v1_t, v2_t, cpu_env); + gen_helper_dpsq_sa_l_w(t0, v1_t, v2_t, tcg_env); break; case OPC_MAQ_S_W_PHL: check_dsp(ctx); - gen_helper_maq_s_w_phl(t0, v1_t, v2_t, cpu_env); + gen_helper_maq_s_w_phl(t0, v1_t, v2_t, tcg_env); break; case OPC_MAQ_S_W_PHR: check_dsp(ctx); - gen_helper_maq_s_w_phr(t0, v1_t, v2_t, cpu_env); + gen_helper_maq_s_w_phr(t0, v1_t, v2_t, tcg_env); break; case OPC_MAQ_SA_W_PHL: check_dsp(ctx); - gen_helper_maq_sa_w_phl(t0, v1_t, v2_t, cpu_env); + gen_helper_maq_sa_w_phl(t0, v1_t, v2_t, tcg_env); break; case OPC_MAQ_SA_W_PHR: check_dsp(ctx); - gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, cpu_env); + gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, tcg_env); break; case OPC_MULSA_W_PH: check_dsp_r2(ctx); - gen_helper_mulsa_w_ph(t0, v1_t, v2_t, cpu_env); + gen_helper_mulsa_w_ph(t0, v1_t, v2_t, tcg_env); break; } break; @@ -12471,107 +12471,107 @@ static void gen_mipsdsp_multiply(DisasContext *= ctx, uint32_t op1, uint32_t op2, switch (op2) { case OPC_DMADD: check_dsp(ctx); - gen_helper_dmadd(v1_t, v2_t, t0, cpu_env); + gen_helper_dmadd(v1_t, v2_t, t0, tcg_env); break; case OPC_DMADDU: check_dsp(ctx); - gen_helper_dmaddu(v1_t, v2_t, t0, cpu_env); + gen_helper_dmaddu(v1_t, v2_t, t0, tcg_env); break; case OPC_DMSUB: check_dsp(ctx); - gen_helper_dmsub(v1_t, v2_t, t0, cpu_env); + gen_helper_dmsub(v1_t, v2_t, t0, tcg_env); break; case OPC_DMSUBU: check_dsp(ctx); - gen_helper_dmsubu(v1_t, v2_t, t0, cpu_env); + gen_helper_dmsubu(v1_t, v2_t, t0, tcg_env); break; case OPC_DPA_W_QH: check_dsp_r2(ctx); - gen_helper_dpa_w_qh(v1_t, v2_t, t0, cpu_env); + gen_helper_dpa_w_qh(v1_t, v2_t, t0, tcg_env); break; case OPC_DPAQ_S_W_QH: check_dsp(ctx); - gen_helper_dpaq_s_w_qh(v1_t, v2_t, t0, cpu_env); + gen_helper_dpaq_s_w_qh(v1_t, v2_t, t0, tcg_env); break; case OPC_DPAQ_SA_L_PW: check_dsp(ctx); - gen_helper_dpaq_sa_l_pw(v1_t, v2_t, t0, cpu_env); + gen_helper_dpaq_sa_l_pw(v1_t, v2_t, t0, tcg_env); break; case OPC_DPAU_H_OBL: check_dsp(ctx); - gen_helper_dpau_h_obl(v1_t, v2_t, t0, cpu_env); + gen_helper_dpau_h_obl(v1_t, v2_t, t0, tcg_env); break; case OPC_DPAU_H_OBR: check_dsp(ctx); - gen_helper_dpau_h_obr(v1_t, v2_t, t0, cpu_env); + gen_helper_dpau_h_obr(v1_t, v2_t, t0, tcg_env); break; case OPC_DPS_W_QH: check_dsp_r2(ctx); - gen_helper_dps_w_qh(v1_t, v2_t, t0, cpu_env); + gen_helper_dps_w_qh(v1_t, v2_t, t0, tcg_env); break; case OPC_DPSQ_S_W_QH: check_dsp(ctx); - gen_helper_dpsq_s_w_qh(v1_t, v2_t, t0, cpu_env); + gen_helper_dpsq_s_w_qh(v1_t, v2_t, t0, tcg_env); break; case OPC_DPSQ_SA_L_PW: check_dsp(ctx); - gen_helper_dpsq_sa_l_pw(v1_t, v2_t, t0, cpu_env); + gen_helper_dpsq_sa_l_pw(v1_t, v2_t, t0, tcg_env); break; case OPC_DPSU_H_OBL: check_dsp(ctx); - gen_helper_dpsu_h_obl(v1_t, v2_t, t0, cpu_env); + gen_helper_dpsu_h_obl(v1_t, v2_t, t0, tcg_env); break; case OPC_DPSU_H_OBR: check_dsp(ctx); - gen_helper_dpsu_h_obr(v1_t, v2_t, t0, cpu_env); + gen_helper_dpsu_h_obr(v1_t, v2_t, t0, tcg_env); break; case OPC_MAQ_S_L_PWL: check_dsp(ctx); - gen_helper_maq_s_l_pwl(v1_t, v2_t, t0, cpu_env); + gen_helper_maq_s_l_pwl(v1_t, v2_t, t0, tcg_env); break; case OPC_MAQ_S_L_PWR: check_dsp(ctx); - gen_helper_maq_s_l_pwr(v1_t, v2_t, t0, cpu_env); + gen_helper_maq_s_l_pwr(v1_t, v2_t, t0, tcg_env); break; case OPC_MAQ_S_W_QHLL: check_dsp(ctx); - gen_helper_maq_s_w_qhll(v1_t, v2_t, t0, cpu_env); + gen_helper_maq_s_w_qhll(v1_t, v2_t, t0, tcg_env); break; case OPC_MAQ_SA_W_QHLL: check_dsp(ctx); - gen_helper_maq_sa_w_qhll(v1_t, v2_t, t0, cpu_env); + gen_helper_maq_sa_w_qhll(v1_t, v2_t, t0, tcg_env); break; case OPC_MAQ_S_W_QHLR: check_dsp(ctx); - gen_helper_maq_s_w_qhlr(v1_t, v2_t, t0, cpu_env); + gen_helper_maq_s_w_qhlr(v1_t, v2_t, t0, tcg_env); break; case OPC_MAQ_SA_W_QHLR: check_dsp(ctx); - gen_helper_maq_sa_w_qhlr(v1_t, v2_t, t0, cpu_env); + gen_helper_maq_sa_w_qhlr(v1_t, v2_t, t0, tcg_env); break; case OPC_MAQ_S_W_QHRL: check_dsp(ctx); - gen_helper_maq_s_w_qhrl(v1_t, v2_t, t0, cpu_env); + gen_helper_maq_s_w_qhrl(v1_t, v2_t, t0, tcg_env); break; case OPC_MAQ_SA_W_QHRL: check_dsp(ctx); - gen_helper_maq_sa_w_qhrl(v1_t, v2_t, t0, cpu_env); + gen_helper_maq_sa_w_qhrl(v1_t, v2_t, t0, tcg_env); break; case OPC_MAQ_S_W_QHRR: check_dsp(ctx); - gen_helper_maq_s_w_qhrr(v1_t, v2_t, t0, cpu_env); + gen_helper_maq_s_w_qhrr(v1_t, v2_t, t0, tcg_env); break; case OPC_MAQ_SA_W_QHRR: check_dsp(ctx); - gen_helper_maq_sa_w_qhrr(v1_t, v2_t, t0, cpu_env); + gen_helper_maq_sa_w_qhrr(v1_t, v2_t, t0, tcg_env); break; case OPC_MULSAQ_S_L_PW: check_dsp(ctx); - gen_helper_mulsaq_s_l_pw(v1_t, v2_t, t0, cpu_env); + gen_helper_mulsaq_s_l_pw(v1_t, v2_t, t0, tcg_env); break; case OPC_MULSAQ_S_W_QH: check_dsp(ctx); - gen_helper_mulsaq_s_w_qh(v1_t, v2_t, t0, cpu_env); + gen_helper_mulsaq_s_w_qh(v1_t, v2_t, t0, tcg_env); break; } } @@ -12581,27 +12581,27 @@ static void gen_mipsdsp_multiply(DisasContext *ct= x, uint32_t op1, uint32_t op2, switch (op2) { case OPC_MULEU_S_PH_QBL: check_dsp(ctx); - gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_MULEU_S_PH_QBR: check_dsp(ctx); - gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_MULQ_RS_PH: check_dsp(ctx); - gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_MULEQ_S_W_PHL: check_dsp(ctx); - gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_MULEQ_S_W_PHR: check_dsp(ctx); - gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_MULQ_S_PH: check_dsp_r2(ctx); - gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; } break; @@ -12610,23 +12610,23 @@ static void gen_mipsdsp_multiply(DisasContext *ct= x, uint32_t op1, uint32_t op2, switch (op2) { case OPC_MULEQ_S_PW_QHL: check_dsp(ctx); - gen_helper_muleq_s_pw_qhl(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_muleq_s_pw_qhl(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_MULEQ_S_PW_QHR: check_dsp(ctx); - gen_helper_muleq_s_pw_qhr(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_muleq_s_pw_qhr(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_MULEU_S_QH_OBL: check_dsp(ctx); - gen_helper_muleu_s_qh_obl(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_muleu_s_qh_obl(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_MULEU_S_QH_OBR: check_dsp(ctx); - gen_helper_muleu_s_qh_obr(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_muleu_s_qh_obr(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_MULQ_RS_QH: check_dsp(ctx); - gen_helper_mulq_rs_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_mulq_rs_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; } break; @@ -12795,15 +12795,15 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext= *ctx, switch (op2) { case OPC_CMPU_EQ_QB: check_dsp(ctx); - gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env); + gen_helper_cmpu_eq_qb(v1_t, v2_t, tcg_env); break; case OPC_CMPU_LT_QB: check_dsp(ctx); - gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env); + gen_helper_cmpu_lt_qb(v1_t, v2_t, tcg_env); break; case OPC_CMPU_LE_QB: check_dsp(ctx); - gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env); + gen_helper_cmpu_le_qb(v1_t, v2_t, tcg_env); break; case OPC_CMPGU_EQ_QB: check_dsp(ctx); @@ -12843,23 +12843,23 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext= *ctx, break; case OPC_CMP_EQ_PH: check_dsp(ctx); - gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env); + gen_helper_cmp_eq_ph(v1_t, v2_t, tcg_env); break; case OPC_CMP_LT_PH: check_dsp(ctx); - gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env); + gen_helper_cmp_lt_ph(v1_t, v2_t, tcg_env); break; case OPC_CMP_LE_PH: check_dsp(ctx); - gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env); + gen_helper_cmp_le_ph(v1_t, v2_t, tcg_env); break; case OPC_PICK_QB: check_dsp(ctx); - gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_PICK_PH: check_dsp(ctx); - gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_PACKRL_PH: check_dsp(ctx); @@ -12872,39 +12872,39 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext= *ctx, switch (op2) { case OPC_CMP_EQ_PW: check_dsp(ctx); - gen_helper_cmp_eq_pw(v1_t, v2_t, cpu_env); + gen_helper_cmp_eq_pw(v1_t, v2_t, tcg_env); break; case OPC_CMP_LT_PW: check_dsp(ctx); - gen_helper_cmp_lt_pw(v1_t, v2_t, cpu_env); + gen_helper_cmp_lt_pw(v1_t, v2_t, tcg_env); break; case OPC_CMP_LE_PW: check_dsp(ctx); - gen_helper_cmp_le_pw(v1_t, v2_t, cpu_env); + gen_helper_cmp_le_pw(v1_t, v2_t, tcg_env); break; case OPC_CMP_EQ_QH: check_dsp(ctx); - gen_helper_cmp_eq_qh(v1_t, v2_t, cpu_env); + gen_helper_cmp_eq_qh(v1_t, v2_t, tcg_env); break; case OPC_CMP_LT_QH: check_dsp(ctx); - gen_helper_cmp_lt_qh(v1_t, v2_t, cpu_env); + gen_helper_cmp_lt_qh(v1_t, v2_t, tcg_env); break; case OPC_CMP_LE_QH: check_dsp(ctx); - gen_helper_cmp_le_qh(v1_t, v2_t, cpu_env); + gen_helper_cmp_le_qh(v1_t, v2_t, tcg_env); break; case OPC_CMPGDU_EQ_OB: check_dsp_r2(ctx); - gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_CMPGDU_LT_OB: check_dsp_r2(ctx); - gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_CMPGDU_LE_OB: check_dsp_r2(ctx); - gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_CMPGU_EQ_OB: check_dsp(ctx); @@ -12920,15 +12920,15 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext= *ctx, break; case OPC_CMPU_EQ_OB: check_dsp(ctx); - gen_helper_cmpu_eq_ob(v1_t, v2_t, cpu_env); + gen_helper_cmpu_eq_ob(v1_t, v2_t, tcg_env); break; case OPC_CMPU_LT_OB: check_dsp(ctx); - gen_helper_cmpu_lt_ob(v1_t, v2_t, cpu_env); + gen_helper_cmpu_lt_ob(v1_t, v2_t, tcg_env); break; case OPC_CMPU_LE_OB: check_dsp(ctx); - gen_helper_cmpu_le_ob(v1_t, v2_t, cpu_env); + gen_helper_cmpu_le_ob(v1_t, v2_t, tcg_env); break; case OPC_PACKRL_PW: check_dsp(ctx); @@ -12936,15 +12936,15 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext= *ctx, break; case OPC_PICK_OB: check_dsp(ctx); - gen_helper_pick_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_pick_ob(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_PICK_PW: check_dsp(ctx); - gen_helper_pick_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_pick_pw(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; case OPC_PICK_QH: check_dsp(ctx); - gen_helper_pick_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + gen_helper_pick_qh(cpu_gpr[ret], v1_t, v2_t, tcg_env); break; } break; @@ -13066,80 +13066,80 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx= , uint32_t op1, uint32_t op2, case OPC_EXTR_W: tcg_gen_movi_tl(t0, v2); tcg_gen_movi_tl(t1, v1); - gen_helper_extr_w(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_extr_w(cpu_gpr[ret], t0, t1, tcg_env); break; case OPC_EXTR_R_W: tcg_gen_movi_tl(t0, v2); tcg_gen_movi_tl(t1, v1); - gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, tcg_env); break; case OPC_EXTR_RS_W: tcg_gen_movi_tl(t0, v2); tcg_gen_movi_tl(t1, v1); - gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, tcg_env); break; case OPC_EXTR_S_H: tcg_gen_movi_tl(t0, v2); tcg_gen_movi_tl(t1, v1); - gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, tcg_env); break; case OPC_EXTRV_S_H: tcg_gen_movi_tl(t0, v2); - gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env); + gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, tcg_env); break; case OPC_EXTRV_W: tcg_gen_movi_tl(t0, v2); - gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, cpu_env); + gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, tcg_env); break; case OPC_EXTRV_R_W: tcg_gen_movi_tl(t0, v2); - gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env); + gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, tcg_env); break; case OPC_EXTRV_RS_W: tcg_gen_movi_tl(t0, v2); - gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env); + gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, tcg_env); break; case OPC_EXTP: tcg_gen_movi_tl(t0, v2); tcg_gen_movi_tl(t1, v1); - gen_helper_extp(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_extp(cpu_gpr[ret], t0, t1, tcg_env); break; case OPC_EXTPV: tcg_gen_movi_tl(t0, v2); - gen_helper_extp(cpu_gpr[ret], t0, v1_t, cpu_env); + gen_helper_extp(cpu_gpr[ret], t0, v1_t, tcg_env); break; case OPC_EXTPDP: tcg_gen_movi_tl(t0, v2); tcg_gen_movi_tl(t1, v1); - gen_helper_extpdp(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_extpdp(cpu_gpr[ret], t0, t1, tcg_env); break; case OPC_EXTPDPV: tcg_gen_movi_tl(t0, v2); - gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, cpu_env); + gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, tcg_env); break; case OPC_SHILO: imm =3D (ctx->opcode >> 20) & 0x3F; tcg_gen_movi_tl(t0, ret); tcg_gen_movi_tl(t1, imm); - gen_helper_shilo(t0, t1, cpu_env); + gen_helper_shilo(t0, t1, tcg_env); break; case OPC_SHILOV: tcg_gen_movi_tl(t0, ret); - gen_helper_shilo(t0, v1_t, cpu_env); + gen_helper_shilo(t0, v1_t, tcg_env); break; case OPC_MTHLIP: tcg_gen_movi_tl(t0, ret); - gen_helper_mthlip(t0, v1_t, cpu_env); + gen_helper_mthlip(t0, v1_t, tcg_env); break; case OPC_WRDSP: imm =3D (ctx->opcode >> 11) & 0x3FF; tcg_gen_movi_tl(t0, imm); - gen_helper_wrdsp(v1_t, t0, cpu_env); + gen_helper_wrdsp(v1_t, t0, tcg_env); break; case OPC_RDDSP: imm =3D (ctx->opcode >> 16) & 0x03FF; tcg_gen_movi_tl(t0, imm); - gen_helper_rddsp(cpu_gpr[ret], t0, cpu_env); + gen_helper_rddsp(cpu_gpr[ret], t0, tcg_env); break; } break; @@ -13149,7 +13149,7 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, = uint32_t op1, uint32_t op2, switch (op2) { case OPC_DMTHLIP: tcg_gen_movi_tl(t0, ret); - gen_helper_dmthlip(v1_t, t0, cpu_env); + gen_helper_dmthlip(v1_t, t0, tcg_env); break; case OPC_DSHILO: { @@ -13157,97 +13157,97 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx= , uint32_t op1, uint32_t op2, int ac =3D (ctx->opcode >> 11) & 0x03; tcg_gen_movi_tl(t0, shift); tcg_gen_movi_tl(t1, ac); - gen_helper_dshilo(t0, t1, cpu_env); + gen_helper_dshilo(t0, t1, tcg_env); break; } case OPC_DSHILOV: { int ac =3D (ctx->opcode >> 11) & 0x03; tcg_gen_movi_tl(t0, ac); - gen_helper_dshilo(v1_t, t0, cpu_env); + gen_helper_dshilo(v1_t, t0, tcg_env); break; } case OPC_DEXTP: tcg_gen_movi_tl(t0, v2); tcg_gen_movi_tl(t1, v1); =20 - gen_helper_dextp(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_dextp(cpu_gpr[ret], t0, t1, tcg_env); break; case OPC_DEXTPV: tcg_gen_movi_tl(t0, v2); - gen_helper_dextp(cpu_gpr[ret], t0, v1_t, cpu_env); + gen_helper_dextp(cpu_gpr[ret], t0, v1_t, tcg_env); break; case OPC_DEXTPDP: tcg_gen_movi_tl(t0, v2); tcg_gen_movi_tl(t1, v1); - gen_helper_dextpdp(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_dextpdp(cpu_gpr[ret], t0, t1, tcg_env); break; case OPC_DEXTPDPV: tcg_gen_movi_tl(t0, v2); - gen_helper_dextpdp(cpu_gpr[ret], t0, v1_t, cpu_env); + gen_helper_dextpdp(cpu_gpr[ret], t0, v1_t, tcg_env); break; case OPC_DEXTR_L: tcg_gen_movi_tl(t0, v2); tcg_gen_movi_tl(t1, v1); - gen_helper_dextr_l(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_dextr_l(cpu_gpr[ret], t0, t1, tcg_env); break; case OPC_DEXTR_R_L: tcg_gen_movi_tl(t0, v2); tcg_gen_movi_tl(t1, v1); - gen_helper_dextr_r_l(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_dextr_r_l(cpu_gpr[ret], t0, t1, tcg_env); break; case OPC_DEXTR_RS_L: tcg_gen_movi_tl(t0, v2); tcg_gen_movi_tl(t1, v1); - gen_helper_dextr_rs_l(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_dextr_rs_l(cpu_gpr[ret], t0, t1, tcg_env); break; case OPC_DEXTR_W: tcg_gen_movi_tl(t0, v2); tcg_gen_movi_tl(t1, v1); - gen_helper_dextr_w(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_dextr_w(cpu_gpr[ret], t0, t1, tcg_env); break; case OPC_DEXTR_R_W: tcg_gen_movi_tl(t0, v2); tcg_gen_movi_tl(t1, v1); - gen_helper_dextr_r_w(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_dextr_r_w(cpu_gpr[ret], t0, t1, tcg_env); break; case OPC_DEXTR_RS_W: tcg_gen_movi_tl(t0, v2); tcg_gen_movi_tl(t1, v1); - gen_helper_dextr_rs_w(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_dextr_rs_w(cpu_gpr[ret], t0, t1, tcg_env); break; case OPC_DEXTR_S_H: tcg_gen_movi_tl(t0, v2); tcg_gen_movi_tl(t1, v1); - gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, tcg_env); break; case OPC_DEXTRV_S_H: tcg_gen_movi_tl(t0, v2); - gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env); + gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, tcg_env); break; case OPC_DEXTRV_L: tcg_gen_movi_tl(t0, v2); - gen_helper_dextr_l(cpu_gpr[ret], t0, v1_t, cpu_env); + gen_helper_dextr_l(cpu_gpr[ret], t0, v1_t, tcg_env); break; case OPC_DEXTRV_R_L: tcg_gen_movi_tl(t0, v2); - gen_helper_dextr_r_l(cpu_gpr[ret], t0, v1_t, cpu_env); + gen_helper_dextr_r_l(cpu_gpr[ret], t0, v1_t, tcg_env); break; case OPC_DEXTRV_RS_L: tcg_gen_movi_tl(t0, v2); - gen_helper_dextr_rs_l(cpu_gpr[ret], t0, v1_t, cpu_env); + gen_helper_dextr_rs_l(cpu_gpr[ret], t0, v1_t, tcg_env); break; case OPC_DEXTRV_W: tcg_gen_movi_tl(t0, v2); - gen_helper_dextr_w(cpu_gpr[ret], t0, v1_t, cpu_env); + gen_helper_dextr_w(cpu_gpr[ret], t0, v1_t, tcg_env); break; case OPC_DEXTRV_R_W: tcg_gen_movi_tl(t0, v2); - gen_helper_dextr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env); + gen_helper_dextr_r_w(cpu_gpr[ret], t0, v1_t, tcg_env); break; case OPC_DEXTRV_RS_W: tcg_gen_movi_tl(t0, v2); - gen_helper_dextr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env); + gen_helper_dextr_rs_w(cpu_gpr[ret], t0, v1_t, tcg_env); break; } break; @@ -13579,7 +13579,7 @@ static void decode_opc_special(CPUMIPSState *env, D= isasContext *ctx) MIPS_INVAL("PMON / selsl"); gen_reserved_instruction(ctx); #else - gen_helper_pmon(cpu_env, tcg_constant_i32(sa)); + gen_helper_pmon(tcg_env, tcg_constant_i32(sa)); #endif break; case OPC_SYSCALL: @@ -14102,7 +14102,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) gen_load_gpr(t0, rt); gen_load_gpr(t1, rs); =20 - gen_helper_insv(cpu_gpr[rt], cpu_env, t1, t0); + gen_helper_insv(cpu_gpr[rt], tcg_env, t1, t0); break; } default: /* Invalid */ @@ -14371,7 +14371,7 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) gen_load_gpr(t0, rt); gen_load_gpr(t1, rs); =20 - gen_helper_dinsv(cpu_gpr[rt], cpu_env, t1, t0); + gen_helper_dinsv(cpu_gpr[rt], tcg_env, t1, t0); break; } default: /* Invalid */ @@ -14606,7 +14606,7 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) TCGv t0 =3D tcg_temp_new(); =20 gen_load_gpr(t0, rs); - gen_helper_yield(t0, cpu_env, t0); + gen_helper_yield(t0, tcg_env, t0); gen_store_gpr(t0, rd); } break; @@ -14797,32 +14797,32 @@ static bool decode_opc_legacy(CPUMIPSState *env, = DisasContext *ctx) break; case OPC_DVPE: check_cp0_mt(ctx); - gen_helper_dvpe(t0, cpu_env); + gen_helper_dvpe(t0, tcg_env); gen_store_gpr(t0, rt); break; case OPC_EVPE: check_cp0_mt(ctx); - gen_helper_evpe(t0, cpu_env); + gen_helper_evpe(t0, tcg_env); gen_store_gpr(t0, rt); break; case OPC_DVP: check_insn(ctx, ISA_MIPS_R6); if (ctx->vp) { - gen_helper_dvp(t0, cpu_env); + gen_helper_dvp(t0, tcg_env); gen_store_gpr(t0, rt); } break; case OPC_EVP: check_insn(ctx, ISA_MIPS_R6); if (ctx->vp) { - gen_helper_evp(t0, cpu_env); + gen_helper_evp(t0, tcg_env); gen_store_gpr(t0, rt); } break; case OPC_DI: check_insn(ctx, ISA_MIPS_R2); save_cpu_state(ctx, 1); - gen_helper_di(t0, cpu_env); + gen_helper_di(t0, tcg_env); gen_store_gpr(t0, rt); /* * Stop translation as we may have switched @@ -14833,7 +14833,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) case OPC_EI: check_insn(ctx, ISA_MIPS_R2); save_cpu_state(ctx, 1); - gen_helper_ei(t0, cpu_env); + gen_helper_ei(t0, tcg_env); gen_store_gpr(t0, rt); /* * DISAS_STOP isn't sufficient, we need to ensure we b= reak @@ -15568,7 +15568,7 @@ void mips_tcg_init(void) =20 cpu_gpr[0] =3D NULL; for (i =3D 1; i < 32; i++) - cpu_gpr[i] =3D tcg_global_mem_new(cpu_env, + cpu_gpr[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, active_tc.gpr[i]), regnames[i]); @@ -15578,7 +15578,7 @@ void mips_tcg_init(void) for (unsigned i =3D 1; i < 32; i++) { g_autofree char *rname =3D g_strdup_printf("%s[hi]", regnames[i]); =20 - cpu_gpr_hi[i] =3D tcg_global_mem_new_i64(cpu_env, + cpu_gpr_hi[i] =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUMIPSState, active_tc.gpr_hi[i= ]), rname); @@ -15587,39 +15587,39 @@ void mips_tcg_init(void) for (i =3D 0; i < 32; i++) { int off =3D offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); =20 - fpu_f64[i] =3D tcg_global_mem_new_i64(cpu_env, off, fregnames[i]); + fpu_f64[i] =3D tcg_global_mem_new_i64(tcg_env, off, fregnames[i]); } msa_translate_init(); - cpu_PC =3D tcg_global_mem_new(cpu_env, + cpu_PC =3D tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, active_tc.PC), "PC"= ); for (i =3D 0; i < MIPS_DSP_ACC; i++) { - cpu_HI[i] =3D tcg_global_mem_new(cpu_env, + cpu_HI[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, active_tc.HI= [i]), regnames_HI[i]); - cpu_LO[i] =3D tcg_global_mem_new(cpu_env, + cpu_LO[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, active_tc.LO= [i]), regnames_LO[i]); } - cpu_dspctrl =3D tcg_global_mem_new(cpu_env, + cpu_dspctrl =3D tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, active_tc.DSPControl), "DSPControl"); - bcond =3D tcg_global_mem_new(cpu_env, + bcond =3D tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, bcond), "bcond"); - btarget =3D tcg_global_mem_new(cpu_env, + btarget =3D tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, btarget), "btarget= "); - hflags =3D tcg_global_mem_new_i32(cpu_env, + hflags =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUMIPSState, hflags), "hflag= s"); =20 - fpu_fcr0 =3D tcg_global_mem_new_i32(cpu_env, + fpu_fcr0 =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUMIPSState, active_fpu.fc= r0), "fcr0"); - fpu_fcr31 =3D tcg_global_mem_new_i32(cpu_env, + fpu_fcr31 =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUMIPSState, active_fpu.f= cr31), "fcr31"); - cpu_lladdr =3D tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llad= dr), + cpu_lladdr =3D tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, llad= dr), "lladdr"); - cpu_llval =3D tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval= ), + cpu_llval =3D tcg_global_mem_new(tcg_env, offsetof(CPUMIPSState, llval= ), "llval"); =20 if (TARGET_LONG_BITS =3D=3D 32) { diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_tr= anslate.c index 2c1f6cc527..c877ede76e 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -43,7 +43,7 @@ static bool trans_mult_acc(DisasContext *ctx, arg_r *a, gen_load_gpr(t0, a->rs); gen_load_gpr(t1, a->rt); =20 - gen_helper_mult_acc(t0, cpu_env, t0, t1); + gen_helper_mult_acc(t0, tcg_env, t0, t1); =20 gen_store_gpr(t0, a->rd); return true; diff --git a/target/nios2/translate.c b/target/nios2/translate.c index dfc546d3bb..93ded65f9a 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -209,7 +209,7 @@ static void t_gen_helper_raise_exception(DisasContext *= dc, uint32_t index) { /* Note that PC is advanced for all hardware exceptions. */ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); - gen_helper_raise_exception(cpu_env, tcg_constant_i32(index)); + gen_helper_raise_exception(tcg_env, tcg_constant_i32(index)); dc->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -244,7 +244,7 @@ static void gen_jumpr(DisasContext *dc, int regno, bool= is_call) tcg_gen_lookup_and_goto_ptr(); =20 gen_set_label(l); - tcg_gen_st_tl(dest, cpu_env, offsetof(CPUNios2State, ctrl[CR_BADADDR])= ); + tcg_gen_st_tl(dest, tcg_env, offsetof(CPUNios2State, ctrl[CR_BADADDR])= ); t_gen_helper_raise_exception(dc, EXCP_UNALIGND); =20 dc->base.is_jmp =3D DISAS_NORETURN; @@ -414,7 +414,7 @@ static void rdprs(DisasContext *dc, uint32_t code, uint= 32_t flags) #else I_TYPE(instr, code); TCGv dest =3D dest_gpr(dc, instr.b); - gen_helper_rdprs(dest, cpu_env, tcg_constant_i32(instr.a)); + gen_helper_rdprs(dest, tcg_env, tcg_constant_i32(instr.a)); tcg_gen_addi_tl(dest, dest, instr.imm16.s); #endif } @@ -508,10 +508,10 @@ static void eret(DisasContext *dc, uint32_t code, uin= t32_t flags) #else if (FIELD_EX32(dc->tb_flags, TBFLAGS, CRS0)) { TCGv tmp =3D tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATU= S])); - gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA)); + tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPUNios2State, ctrl[CR_ESTATU= S])); + gen_helper_eret(tcg_env, tmp, load_gpr(dc, R_EA)); } else { - gen_helper_eret(cpu_env, load_gpr(dc, R_SSTATUS), load_gpr(dc, R_E= A)); + gen_helper_eret(tcg_env, load_gpr(dc, R_SSTATUS), load_gpr(dc, R_E= A)); } dc->base.is_jmp =3D DISAS_NORETURN; #endif @@ -537,8 +537,8 @@ static void bret(DisasContext *dc, uint32_t code, uint3= 2_t flags) g_assert_not_reached(); #else TCGv tmp =3D tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS])); - gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_BA)); + tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS])); + gen_helper_eret(tcg_env, tmp, load_gpr(dc, R_BA)); =20 dc->base.is_jmp =3D DISAS_NORETURN; #endif @@ -602,12 +602,12 @@ static void rdctl(DisasContext *dc, uint32_t code, ui= nt32_t flags) */ t1 =3D tcg_temp_new(); t2 =3D tcg_temp_new(); - tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ctrl[CR_IPENDIN= G])); - tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ctrl[CR_IENABLE= ])); + tcg_gen_ld_tl(t1, tcg_env, offsetof(CPUNios2State, ctrl[CR_IPENDIN= G])); + tcg_gen_ld_tl(t2, tcg_env, offsetof(CPUNios2State, ctrl[CR_IENABLE= ])); tcg_gen_and_tl(dest, t1, t2); break; default: - tcg_gen_ld_tl(dest, cpu_env, + tcg_gen_ld_tl(dest, tcg_env, offsetof(CPUNios2State, ctrl[instr.imm5])); break; } @@ -637,13 +637,13 @@ static void wrctl(DisasContext *dc, uint32_t code, ui= nt32_t flags) =20 switch (instr.imm5) { case CR_PTEADDR: - gen_helper_mmu_write_pteaddr(cpu_env, v); + gen_helper_mmu_write_pteaddr(tcg_env, v); break; case CR_TLBACC: - gen_helper_mmu_write_tlbacc(cpu_env, v); + gen_helper_mmu_write_tlbacc(tcg_env, v); break; case CR_TLBMISC: - gen_helper_mmu_write_tlbmisc(cpu_env, v); + gen_helper_mmu_write_tlbmisc(tcg_env, v); break; case CR_STATUS: case CR_IENABLE: @@ -653,7 +653,7 @@ static void wrctl(DisasContext *dc, uint32_t code, uint= 32_t flags) default: if (wr =3D=3D -1) { /* The register is entirely writable. */ - tcg_gen_st_tl(v, cpu_env, ofs); + tcg_gen_st_tl(v, tcg_env, ofs); } else { /* * The register is partially read-only or reserved: @@ -665,12 +665,12 @@ static void wrctl(DisasContext *dc, uint32_t code, ui= nt32_t flags) =20 if (ro !=3D 0) { TCGv o =3D tcg_temp_new(); - tcg_gen_ld_tl(o, cpu_env, ofs); + tcg_gen_ld_tl(o, tcg_env, ofs); tcg_gen_andi_tl(o, o, ro); tcg_gen_or_tl(n, n, o); } =20 - tcg_gen_st_tl(n, cpu_env, ofs); + tcg_gen_st_tl(n, tcg_env, ofs); } break; } @@ -692,7 +692,7 @@ static void wrprs(DisasContext *dc, uint32_t code, uint= 32_t flags) g_assert_not_reached(); #else R_TYPE(instr, code); - gen_helper_wrprs(cpu_env, tcg_constant_i32(instr.c), + gen_helper_wrprs(tcg_env, tcg_constant_i32(instr.c), load_gpr(dc, instr.a)); /* * The expected write to PRS[r0] is 0, from CRS[r0]. @@ -789,14 +789,14 @@ gen_rr_shift(ror, rotr) static void divs(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, (code)); - gen_helper_divs(dest_gpr(dc, instr.c), cpu_env, + gen_helper_divs(dest_gpr(dc, instr.c), tcg_env, load_gpr(dc, instr.a), load_gpr(dc, instr.b)); } =20 static void divu(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, (code)); - gen_helper_divu(dest_gpr(dc, instr.c), cpu_env, + gen_helper_divu(dest_gpr(dc, instr.c), tcg_env, load_gpr(dc, instr.a), load_gpr(dc, instr.b)); } =20 @@ -809,7 +809,7 @@ static void trap(DisasContext *dc, uint32_t code, uint3= 2_t flags) * things easier for cpu_loop if we pop this into env->error_code. */ R_TYPE(instr, code); - tcg_gen_st_i32(tcg_constant_i32(instr.imm5), cpu_env, + tcg_gen_st_i32(tcg_constant_i32(instr.imm5), tcg_env, offsetof(CPUNios2State, error_code)); #endif t_gen_helper_raise_exception(dc, EXCP_TRAP); @@ -1084,7 +1084,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int = flags) void nios2_tcg_init(void) { #ifndef CONFIG_USER_ONLY - TCGv_ptr crs =3D tcg_global_mem_new_ptr(cpu_env, + TCGv_ptr crs =3D tcg_global_mem_new_ptr(tcg_env, offsetof(CPUNios2State, regs), "= crs"); =20 for (int i =3D 0; i < NUM_GP_REGS; i++) { @@ -1097,12 +1097,12 @@ void nios2_tcg_init(void) #endif =20 for (int i =3D 0; i < NUM_GP_REGS; i++) { - cpu_R[i] =3D tcg_global_mem_new(cpu_env, offsetof_regs0(i), + cpu_R[i] =3D tcg_global_mem_new(tcg_env, offsetof_regs0(i), gr_regnames[i]); } =20 #undef offsetof_regs0 =20 - cpu_pc =3D tcg_global_mem_new(cpu_env, + cpu_pc =3D tcg_global_mem_new(tcg_env, offsetof(CPUNios2State, pc), "pc"); } diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index d65758449f..1b4df1c214 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -95,37 +95,37 @@ void openrisc_translate_init(void) }; int i; =20 - cpu_sr =3D tcg_global_mem_new(cpu_env, + cpu_sr =3D tcg_global_mem_new(tcg_env, offsetof(CPUOpenRISCState, sr), "sr"); - cpu_dflag =3D tcg_global_mem_new_i32(cpu_env, + cpu_dflag =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUOpenRISCState, dflag), "dflag"); - cpu_pc =3D tcg_global_mem_new(cpu_env, + cpu_pc =3D tcg_global_mem_new(tcg_env, offsetof(CPUOpenRISCState, pc), "pc"); - cpu_ppc =3D tcg_global_mem_new(cpu_env, + cpu_ppc =3D tcg_global_mem_new(tcg_env, offsetof(CPUOpenRISCState, ppc), "ppc"); - jmp_pc =3D tcg_global_mem_new(cpu_env, + jmp_pc =3D tcg_global_mem_new(tcg_env, offsetof(CPUOpenRISCState, jmp_pc), "jmp_p= c"); - cpu_sr_f =3D tcg_global_mem_new(cpu_env, + cpu_sr_f =3D tcg_global_mem_new(tcg_env, offsetof(CPUOpenRISCState, sr_f), "sr_f"= ); - cpu_sr_cy =3D tcg_global_mem_new(cpu_env, + cpu_sr_cy =3D tcg_global_mem_new(tcg_env, offsetof(CPUOpenRISCState, sr_cy), "sr_= cy"); - cpu_sr_ov =3D tcg_global_mem_new(cpu_env, + cpu_sr_ov =3D tcg_global_mem_new(tcg_env, offsetof(CPUOpenRISCState, sr_ov), "sr_= ov"); - cpu_lock_addr =3D tcg_global_mem_new(cpu_env, + cpu_lock_addr =3D tcg_global_mem_new(tcg_env, offsetof(CPUOpenRISCState, lock_add= r), "lock_addr"); - cpu_lock_value =3D tcg_global_mem_new(cpu_env, + cpu_lock_value =3D tcg_global_mem_new(tcg_env, offsetof(CPUOpenRISCState, lock_va= lue), "lock_value"); - fpcsr =3D tcg_global_mem_new_i32(cpu_env, + fpcsr =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUOpenRISCState, fpcsr), "fpcsr"); - cpu_mac =3D tcg_global_mem_new_i64(cpu_env, + cpu_mac =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUOpenRISCState, mac), "mac"); for (i =3D 0; i < 32; i++) { - cpu_regs[i] =3D tcg_global_mem_new(cpu_env, + cpu_regs[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUOpenRISCState, shadow_gpr[0][i]), regnames[i]); @@ -134,7 +134,7 @@ void openrisc_translate_init(void) =20 static void gen_exception(DisasContext *dc, unsigned int excp) { - gen_helper_exception(cpu_env, tcg_constant_i32(excp)); + gen_helper_exception(tcg_env, tcg_constant_i32(excp)); } =20 static void gen_illegal_exception(DisasContext *dc) @@ -182,21 +182,21 @@ static void check_r0_write(DisasContext *dc, int reg) static void gen_ove_cy(DisasContext *dc) { if (dc->tb_flags & SR_OVE) { - gen_helper_ove_cy(cpu_env); + gen_helper_ove_cy(tcg_env); } } =20 static void gen_ove_ov(DisasContext *dc) { if (dc->tb_flags & SR_OVE) { - gen_helper_ove_ov(cpu_env); + gen_helper_ove_ov(tcg_env); } } =20 static void gen_ove_cyov(DisasContext *dc) { if (dc->tb_flags & SR_OVE) { - gen_helper_ove_cyov(cpu_env); + gen_helper_ove_cyov(tcg_env); } } =20 @@ -835,7 +835,7 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr= *a) } =20 tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); - gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr); + gen_helper_mfspr(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->d), spr); return true; } =20 @@ -860,7 +860,7 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr= *a) dc->base.is_jmp =3D DISAS_EXIT; =20 tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); - gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b)); + gen_helper_mtspr(tcg_env, spr, cpu_R(dc, a->b)); return true; } =20 @@ -1102,7 +1102,7 @@ static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *= a) if (is_user(dc)) { gen_illegal_exception(dc); } else { - gen_helper_rfe(cpu_env); + gen_helper_rfe(tcg_env); dc->base.is_jmp =3D DISAS_EXIT; } return true; @@ -1115,8 +1115,8 @@ static bool do_fp2(DisasContext *dc, arg_da *a, return false; } check_r0_write(dc, a->d); - fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a)); - gen_helper_update_fpcsr(cpu_env); + fn(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->a)); + gen_helper_update_fpcsr(tcg_env); return true; } =20 @@ -1127,8 +1127,8 @@ static bool do_fp3(DisasContext *dc, arg_dab *a, return false; } check_r0_write(dc, a->d); - fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); - gen_helper_update_fpcsr(cpu_env); + fn(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); + gen_helper_update_fpcsr(tcg_env); return true; } =20 @@ -1140,14 +1140,14 @@ static bool do_fpcmp(DisasContext *dc, arg_ab *a, return false; } if (swap) { - fn(cpu_sr_f, cpu_env, cpu_R(dc, a->b), cpu_R(dc, a->a)); + fn(cpu_sr_f, tcg_env, cpu_R(dc, a->b), cpu_R(dc, a->a)); } else { - fn(cpu_sr_f, cpu_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); + fn(cpu_sr_f, tcg_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); } if (inv) { tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); } - gen_helper_update_fpcsr(cpu_env); + gen_helper_update_fpcsr(tcg_env); return true; } =20 @@ -1193,9 +1193,9 @@ static bool trans_lf_madd_s(DisasContext *dc, arg_dab= *a) return false; } check_r0_write(dc, a->d); - gen_helper_float_madd_s(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), + gen_helper_float_madd_s(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); - gen_helper_update_fpcsr(cpu_env); + gen_helper_update_fpcsr(tcg_env); return true; } =20 @@ -1309,10 +1309,10 @@ static bool do_dp3(DisasContext *dc, arg_dab_pair *= a, t1 =3D tcg_temp_new_i64(); load_pair(dc, t0, a->a, a->ap); load_pair(dc, t1, a->b, a->bp); - fn(t0, cpu_env, t0, t1); + fn(t0, tcg_env, t0, t1); save_pair(dc, t0, a->d, a->dp); =20 - gen_helper_update_fpcsr(cpu_env); + gen_helper_update_fpcsr(tcg_env); return true; } =20 @@ -1330,10 +1330,10 @@ static bool do_dp2(DisasContext *dc, arg_da_pair *a, =20 t0 =3D tcg_temp_new_i64(); load_pair(dc, t0, a->a, a->ap); - fn(t0, cpu_env, t0); + fn(t0, tcg_env, t0); save_pair(dc, t0, a->d, a->dp); =20 - gen_helper_update_fpcsr(cpu_env); + gen_helper_update_fpcsr(tcg_env); return true; } =20 @@ -1354,15 +1354,15 @@ static bool do_dpcmp(DisasContext *dc, arg_ab_pair = *a, load_pair(dc, t0, a->a, a->ap); load_pair(dc, t1, a->b, a->bp); if (swap) { - fn(cpu_sr_f, cpu_env, t1, t0); + fn(cpu_sr_f, tcg_env, t1, t0); } else { - fn(cpu_sr_f, cpu_env, t0, t1); + fn(cpu_sr_f, tcg_env, t0, t1); } =20 if (inv) { tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); } - gen_helper_update_fpcsr(cpu_env); + gen_helper_update_fpcsr(tcg_env); return true; } =20 @@ -1412,10 +1412,10 @@ static bool trans_lf_stod_d(DisasContext *dc, arg_l= f_stod_d *a) check_r0_write(dc, a->d); =20 t0 =3D tcg_temp_new_i64(); - gen_helper_stod(t0, cpu_env, cpu_R(dc, a->a)); + gen_helper_stod(t0, tcg_env, cpu_R(dc, a->a)); save_pair(dc, t0, a->d, a->dp); =20 - gen_helper_update_fpcsr(cpu_env); + gen_helper_update_fpcsr(tcg_env); return true; } =20 @@ -1431,9 +1431,9 @@ static bool trans_lf_dtos_d(DisasContext *dc, arg_lf_= dtos_d *a) =20 t0 =3D tcg_temp_new_i64(); load_pair(dc, t0, a->a, a->ap); - gen_helper_dtos(cpu_R(dc, a->d), cpu_env, t0); + gen_helper_dtos(cpu_R(dc, a->d), tcg_env, t0); =20 - gen_helper_update_fpcsr(cpu_env); + gen_helper_update_fpcsr(tcg_env); return true; } =20 @@ -1455,10 +1455,10 @@ static bool trans_lf_madd_d(DisasContext *dc, arg_d= ab_pair *a) load_pair(dc, t0, a->d, a->dp); load_pair(dc, t1, a->a, a->ap); load_pair(dc, t2, a->b, a->bp); - gen_helper_float_madd_d(t0, cpu_env, t0, t1, t2); + gen_helper_float_madd_d(t0, tcg_env, t0, t1, t2); save_pair(dc, t0, a->d, a->dp); =20 - gen_helper_update_fpcsr(cpu_env); + gen_helper_update_fpcsr(tcg_env); return true; } =20 diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 5c28afbbb8..e20a1bea62 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -92,7 +92,7 @@ void ppc_translate_init(void) =20 for (i =3D 0; i < 8; i++) { snprintf(p, cpu_reg_names_size, "crf%d", i); - cpu_crf[i] =3D tcg_global_mem_new_i32(cpu_env, + cpu_crf[i] =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUPPCState, crf[i]),= p); p +=3D 5; cpu_reg_names_size -=3D 5; @@ -100,67 +100,67 @@ void ppc_translate_init(void) =20 for (i =3D 0; i < 32; i++) { snprintf(p, cpu_reg_names_size, "r%d", i); - cpu_gpr[i] =3D tcg_global_mem_new(cpu_env, + cpu_gpr[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, gpr[i]), p); p +=3D (i < 10) ? 3 : 4; cpu_reg_names_size -=3D (i < 10) ? 3 : 4; snprintf(p, cpu_reg_names_size, "r%dH", i); - cpu_gprh[i] =3D tcg_global_mem_new(cpu_env, + cpu_gprh[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, gprh[i]), p= ); p +=3D (i < 10) ? 4 : 5; cpu_reg_names_size -=3D (i < 10) ? 4 : 5; } =20 - cpu_nip =3D tcg_global_mem_new(cpu_env, + cpu_nip =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, nip), "nip"); =20 - cpu_msr =3D tcg_global_mem_new(cpu_env, + cpu_msr =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, msr), "msr"); =20 - cpu_ctr =3D tcg_global_mem_new(cpu_env, + cpu_ctr =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, ctr), "ctr"); =20 - cpu_lr =3D tcg_global_mem_new(cpu_env, + cpu_lr =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, lr), "lr"); =20 #if defined(TARGET_PPC64) - cpu_cfar =3D tcg_global_mem_new(cpu_env, + cpu_cfar =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, cfar), "cfar"); #endif =20 - cpu_xer =3D tcg_global_mem_new(cpu_env, + cpu_xer =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, xer), "xer"); - cpu_so =3D tcg_global_mem_new(cpu_env, + cpu_so =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, so), "SO"); - cpu_ov =3D tcg_global_mem_new(cpu_env, + cpu_ov =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, ov), "OV"); - cpu_ca =3D tcg_global_mem_new(cpu_env, + cpu_ca =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, ca), "CA"); - cpu_ov32 =3D tcg_global_mem_new(cpu_env, + cpu_ov32 =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, ov32), "OV32"); - cpu_ca32 =3D tcg_global_mem_new(cpu_env, + cpu_ca32 =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, ca32), "CA32"); =20 - cpu_reserve =3D tcg_global_mem_new(cpu_env, + cpu_reserve =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, reserve_addr), "reserve_addr"); - cpu_reserve_length =3D tcg_global_mem_new(cpu_env, + cpu_reserve_length =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, reserve_length), "reserve_length"); - cpu_reserve_val =3D tcg_global_mem_new(cpu_env, + cpu_reserve_val =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, reserve_val= ), "reserve_val"); #if defined(TARGET_PPC64) - cpu_reserve_val2 =3D tcg_global_mem_new(cpu_env, + cpu_reserve_val2 =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, reserve_va= l2), "reserve_val2"); #endif =20 - cpu_fpscr =3D tcg_global_mem_new(cpu_env, + cpu_fpscr =3D tcg_global_mem_new(tcg_env, offsetof(CPUPPCState, fpscr), "fpscr"); =20 - cpu_access_type =3D tcg_global_mem_new_i32(cpu_env, + cpu_access_type =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUPPCState, access_= type), "access_type"); } @@ -240,7 +240,7 @@ static inline bool gen_serialize(DisasContext *ctx) { if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { /* Restart with exclusive lock. */ - gen_helper_exit_atomic(cpu_env); + gen_helper_exit_atomic(tcg_env); ctx->base.is_jmp =3D DISAS_NORETURN; return false; } @@ -261,12 +261,12 @@ static inline bool gen_serialize_core_lpar(DisasConte= xt *ctx) /* SPR load/store helpers */ static inline void gen_load_spr(TCGv t, int reg) { - tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); + tcg_gen_ld_tl(t, tcg_env, offsetof(CPUPPCState, spr[reg])); } =20 static inline void gen_store_spr(int reg, TCGv t) { - tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); + tcg_gen_st_tl(t, tcg_env, offsetof(CPUPPCState, spr[reg])); } =20 static inline void gen_set_access_type(DisasContext *ctx, int access_type) @@ -296,7 +296,7 @@ static void gen_exception_err(DisasContext *ctx, uint32= _t excp, uint32_t error) gen_update_nip(ctx, ctx->cia); t0 =3D tcg_constant_i32(excp); t1 =3D tcg_constant_i32(error); - gen_helper_raise_exception_err(cpu_env, t0, t1); + gen_helper_raise_exception_err(tcg_env, t0, t1); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -310,7 +310,7 @@ static void gen_exception(DisasContext *ctx, uint32_t e= xcp) */ gen_update_nip(ctx, ctx->cia); t0 =3D tcg_constant_i32(excp); - gen_helper_raise_exception(cpu_env, t0); + gen_helper_raise_exception(tcg_env, t0); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -321,7 +321,7 @@ static void gen_exception_nip(DisasContext *ctx, uint32= _t excp, =20 gen_update_nip(ctx, nip); t0 =3D tcg_constant_i32(excp); - gen_helper_raise_exception(cpu_env, t0); + gen_helper_raise_exception(tcg_env, t0); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -329,7 +329,7 @@ static void gen_exception_nip(DisasContext *ctx, uint32= _t excp, static void gen_ppc_maybe_interrupt(DisasContext *ctx) { translator_io_start(&ctx->base); - gen_helper_ppc_maybe_interrupt(cpu_env); + gen_helper_ppc_maybe_interrupt(tcg_env); } #endif =20 @@ -355,14 +355,14 @@ static void gen_debug_exception(DisasContext *ctx, bo= ol rfi_type) gen_load_spr(t0, SPR_BOOKE_DBSR); tcg_gen_ori_tl(t0, t0, dbsr); gen_store_spr(SPR_BOOKE_DBSR, t0); - gen_helper_raise_exception(cpu_env, + gen_helper_raise_exception(tcg_env, tcg_constant_i32(POWERPC_EXCP_DEBUG)); ctx->base.is_jmp =3D DISAS_NORETURN; } else { if (!rfi_type) { /* BookS does not single step rfi type instructio= ns */ TCGv t0 =3D tcg_temp_new(); tcg_gen_movi_tl(t0, ctx->cia); - gen_helper_book3s_trace(cpu_env, t0); + gen_helper_book3s_trace(tcg_env, t0); ctx->base.is_jmp =3D DISAS_NORETURN; } } @@ -407,7 +407,7 @@ static void spr_load_dump_spr(int sprn) { #ifdef PPC_DUMP_SPR_ACCESSES TCGv_i32 t0 =3D tcg_constant_i32(sprn); - gen_helper_load_dump_spr(cpu_env, t0); + gen_helper_load_dump_spr(tcg_env, t0); #endif } =20 @@ -421,7 +421,7 @@ static void spr_store_dump_spr(int sprn) { #ifdef PPC_DUMP_SPR_ACCESSES TCGv_i32 t0 =3D tcg_constant_i32(sprn); - gen_helper_store_dump_spr(cpu_env, t0); + gen_helper_store_dump_spr(tcg_env, t0); #endif } =20 @@ -454,7 +454,7 @@ void spr_core_write_generic(DisasContext *ctx, int sprn= , int gprn) return; } =20 - gen_helper_spr_core_write_generic(cpu_env, tcg_constant_i32(sprn), + gen_helper_spr_core_write_generic(tcg_env, tcg_constant_i32(sprn), cpu_gpr[gprn]); spr_store_dump_spr(sprn); } @@ -482,7 +482,7 @@ void spr_write_CTRL(DisasContext *ctx, int sprn, int gp= rn) return; } =20 - gen_helper_spr_write_CTRL(cpu_env, tcg_constant_i32(sprn), + gen_helper_spr_write_CTRL(tcg_env, tcg_constant_i32(sprn), cpu_gpr[gprn]); out: spr_store_dump_spr(sprn); @@ -578,20 +578,20 @@ void spr_write_cfar(DisasContext *ctx, int sprn, int = gprn) void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_ciabr(cpu_env, cpu_gpr[gprn]); + gen_helper_store_ciabr(tcg_env, cpu_gpr[gprn]); } =20 /* Watchpoint */ void spr_write_dawr0(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_dawr0(cpu_env, cpu_gpr[gprn]); + gen_helper_store_dawr0(tcg_env, cpu_gpr[gprn]); } =20 void spr_write_dawrx0(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_dawrx0(cpu_env, cpu_gpr[gprn]); + gen_helper_store_dawrx0(tcg_env, cpu_gpr[gprn]); } #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ =20 @@ -630,13 +630,13 @@ void spr_write_ureg(DisasContext *ctx, int sprn, int = gprn) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) { translator_io_start(&ctx->base); - gen_helper_load_decr(cpu_gpr[gprn], cpu_env); + gen_helper_load_decr(cpu_gpr[gprn], tcg_env); } =20 void spr_write_decr(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); + gen_helper_store_decr(tcg_env, cpu_gpr[gprn]); } #endif =20 @@ -645,90 +645,90 @@ void spr_write_decr(DisasContext *ctx, int sprn, int = gprn) void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) { translator_io_start(&ctx->base); - gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); + gen_helper_load_tbl(cpu_gpr[gprn], tcg_env); } =20 void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) { translator_io_start(&ctx->base); - gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); + gen_helper_load_tbu(cpu_gpr[gprn], tcg_env); } =20 void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) { - gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); + gen_helper_load_atbl(cpu_gpr[gprn], tcg_env); } =20 void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) { - gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); + gen_helper_load_atbu(cpu_gpr[gprn], tcg_env); } =20 #if !defined(CONFIG_USER_ONLY) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); + gen_helper_store_tbl(tcg_env, cpu_gpr[gprn]); } =20 void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); + gen_helper_store_tbu(tcg_env, cpu_gpr[gprn]); } =20 void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) { - gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); + gen_helper_store_atbl(tcg_env, cpu_gpr[gprn]); } =20 void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) { - gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); + gen_helper_store_atbu(tcg_env, cpu_gpr[gprn]); } =20 #if defined(TARGET_PPC64) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) { translator_io_start(&ctx->base); - gen_helper_load_purr(cpu_gpr[gprn], cpu_env); + gen_helper_load_purr(cpu_gpr[gprn], tcg_env); } =20 void spr_write_purr(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); + gen_helper_store_purr(tcg_env, cpu_gpr[gprn]); } =20 /* HDECR */ void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) { translator_io_start(&ctx->base); - gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); + gen_helper_load_hdecr(cpu_gpr[gprn], tcg_env); } =20 void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); + gen_helper_store_hdecr(tcg_env, cpu_gpr[gprn]); } =20 void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) { translator_io_start(&ctx->base); - gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); + gen_helper_load_vtb(cpu_gpr[gprn], tcg_env); } =20 void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); + gen_helper_store_vtb(tcg_env, cpu_gpr[gprn]); } =20 void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); + gen_helper_store_tbu40(tcg_env, cpu_gpr[gprn]); } =20 #endif @@ -739,14 +739,14 @@ void spr_write_tbu40(DisasContext *ctx, int sprn, int= gprn) /* IBAT0L...IBAT7L */ void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) { - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, + tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); } =20 void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) { - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, + tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, offsetof(CPUPPCState, IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); } @@ -754,39 +754,39 @@ void spr_read_ibat_h(DisasContext *ctx, int gprn, int= sprn) void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 =3D tcg_constant_i32((sprn - SPR_IBAT0U) / 2); - gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); + gen_helper_store_ibatu(tcg_env, t0, cpu_gpr[gprn]); } =20 void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 =3D tcg_constant_i32(((sprn - SPR_IBAT4U) / 2) + 4); - gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); + gen_helper_store_ibatu(tcg_env, t0, cpu_gpr[gprn]); } =20 void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 =3D tcg_constant_i32((sprn - SPR_IBAT0L) / 2); - gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); + gen_helper_store_ibatl(tcg_env, t0, cpu_gpr[gprn]); } =20 void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 =3D tcg_constant_i32(((sprn - SPR_IBAT4L) / 2) + 4); - gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); + gen_helper_store_ibatl(tcg_env, t0, cpu_gpr[gprn]); } =20 /* DBAT0U...DBAT7U */ /* DBAT0L...DBAT7L */ void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) { - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, + tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); } =20 void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) { - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, + tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); } @@ -794,31 +794,31 @@ void spr_read_dbat_h(DisasContext *ctx, int gprn, int= sprn) void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 =3D tcg_constant_i32((sprn - SPR_DBAT0U) / 2); - gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); + gen_helper_store_dbatu(tcg_env, t0, cpu_gpr[gprn]); } =20 void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 =3D tcg_constant_i32(((sprn - SPR_DBAT4U) / 2) + 4); - gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); + gen_helper_store_dbatu(tcg_env, t0, cpu_gpr[gprn]); } =20 void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 =3D tcg_constant_i32((sprn - SPR_DBAT0L) / 2); - gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); + gen_helper_store_dbatl(tcg_env, t0, cpu_gpr[gprn]); } =20 void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 =3D tcg_constant_i32(((sprn - SPR_DBAT4L) / 2) + 4); - gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); + gen_helper_store_dbatl(tcg_env, t0, cpu_gpr[gprn]); } =20 /* SDR1 */ void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) { - gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); + gen_helper_store_sdr1(tcg_env, cpu_gpr[gprn]); } =20 #if defined(TARGET_PPC64) @@ -826,33 +826,33 @@ void spr_write_sdr1(DisasContext *ctx, int sprn, int = gprn) /* PIDR */ void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) { - gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); + gen_helper_store_pidr(tcg_env, cpu_gpr[gprn]); } =20 void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) { - gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); + gen_helper_store_lpidr(tcg_env, cpu_gpr[gprn]); } =20 void spr_read_hior(DisasContext *ctx, int gprn, int sprn) { - tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefi= x)); + tcg_gen_ld_tl(cpu_gpr[gprn], tcg_env, offsetof(CPUPPCState, excp_prefi= x)); } =20 void spr_write_hior(DisasContext *ctx, int sprn, int gprn) { TCGv t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); + tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_prefix)); } void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) { - gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); + gen_helper_store_ptcr(tcg_env, cpu_gpr[gprn]); } =20 void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) { - gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); + gen_helper_store_pcr(tcg_env, cpu_gpr[gprn]); } =20 /* DPDES */ @@ -862,7 +862,7 @@ void spr_read_dpdes(DisasContext *ctx, int gprn, int sp= rn) return; } =20 - gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); + gen_helper_load_dpdes(cpu_gpr[gprn], tcg_env); } =20 void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) @@ -871,7 +871,7 @@ void spr_write_dpdes(DisasContext *ctx, int sprn, int g= prn) return; } =20 - gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); + gen_helper_store_dpdes(tcg_env, cpu_gpr[gprn]); } #endif #endif @@ -881,20 +881,20 @@ void spr_write_dpdes(DisasContext *ctx, int sprn, int= gprn) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) { translator_io_start(&ctx->base); - gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); + gen_helper_load_40x_pit(cpu_gpr[gprn], tcg_env); } =20 void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); + gen_helper_store_40x_pit(tcg_env, cpu_gpr[gprn]); } =20 void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); gen_store_spr(sprn, cpu_gpr[gprn]); - gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); + gen_helper_store_40x_dbcr0(tcg_env, cpu_gpr[gprn]); /* We must stop translation as we may have rebooted */ ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; } @@ -902,38 +902,38 @@ void spr_write_40x_dbcr0(DisasContext *ctx, int sprn,= int gprn) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); + gen_helper_store_40x_sler(tcg_env, cpu_gpr[gprn]); } =20 void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); + gen_helper_store_40x_tcr(tcg_env, cpu_gpr[gprn]); } =20 void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); + gen_helper_store_40x_tsr(tcg_env, cpu_gpr[gprn]); } =20 void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) { TCGv t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xFF); - gen_helper_store_40x_pid(cpu_env, t0); + gen_helper_store_40x_pid(tcg_env, t0); } =20 void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); + gen_helper_store_booke_tcr(tcg_env, cpu_gpr[gprn]); } =20 void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); + gen_helper_store_booke_tsr(tcg_env, cpu_gpr[gprn]); } #endif =20 @@ -951,7 +951,7 @@ void spr_write_pir(DisasContext *ctx, int sprn, int gpr= n) void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) { TCGv_i32 t0 =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); + tcg_gen_ld_i32(t0, tcg_env, offsetof(CPUPPCState, spe_fscr)); tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); } =20 @@ -959,7 +959,7 @@ void spr_write_spefscr(DisasContext *ctx, int sprn, int= gprn) { TCGv_i32 t0 =3D tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); - tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); + tcg_gen_st_i32(t0, tcg_env, offsetof(CPUPPCState, spe_fscr)); } =20 #if !defined(CONFIG_USER_ONLY) @@ -967,9 +967,9 @@ void spr_write_spefscr(DisasContext *ctx, int sprn, int= gprn) void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) { TCGv t0 =3D tcg_temp_new(); - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); + tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUPPCState, ivpr_mask)); tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); + tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_prefix)); gen_store_spr(sprn, t0); } =20 @@ -991,9 +991,9 @@ void spr_write_excp_vector(DisasContext *ctx, int sprn,= int gprn) } =20 TCGv t0 =3D tcg_temp_new(); - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); + tcg_gen_ld_tl(t0, tcg_env, offsetof(CPUPPCState, ivor_mask)); tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); - tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_off= s])); + tcg_gen_st_tl(t0, tcg_env, offsetof(CPUPPCState, excp_vectors[sprn_off= s])); gen_store_spr(sprn, t0); } #endif @@ -1090,7 +1090,7 @@ void spr_write_iamr(DisasContext *ctx, int sprn, int = gprn) #ifndef CONFIG_USER_ONLY void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) { - gen_helper_fixup_thrm(cpu_env); + gen_helper_fixup_thrm(tcg_env); gen_load_spr(cpu_gpr[gprn], sprn); spr_load_dump_spr(sprn); } @@ -1124,23 +1124,23 @@ void spr_write_e500_l2csr0(DisasContext *ctx, int s= prn, int gprn) =20 void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) { - gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); + gen_helper_booke206_tlbflush(tcg_env, cpu_gpr[gprn]); } =20 void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t0 =3D tcg_constant_i32(sprn); - gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); + gen_helper_booke_setpid(tcg_env, t0, cpu_gpr[gprn]); } =20 void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) { - gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); + gen_helper_booke_set_eplc(tcg_env, cpu_gpr[gprn]); } =20 void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) { - gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); + gen_helper_booke_set_epsc(tcg_env, cpu_gpr[gprn]); } =20 #endif @@ -1175,7 +1175,7 @@ static void gen_fscr_facility_check(DisasContext *ctx= , int facility_sprn, TCGv_i32 t2 =3D tcg_constant_i32(sprn); TCGv_i32 t3 =3D tcg_constant_i32(cause); =20 - gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); + gen_helper_fscr_facility_check(tcg_env, t1, t2, t3); } =20 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, @@ -1185,7 +1185,7 @@ static void gen_msr_facility_check(DisasContext *ctx,= int facility_sprn, TCGv_i32 t2 =3D tcg_constant_i32(sprn); TCGv_i32 t3 =3D tcg_constant_i32(cause); =20 - gen_helper_msr_facility_check(cpu_env, t1, t2, t3); + gen_helper_msr_facility_check(tcg_env, t1, t2, t3); } =20 void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) @@ -1220,18 +1220,18 @@ void spr_write_hmer(DisasContext *ctx, int sprn, in= t gprn) =20 void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn) { - gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env); + gen_helper_load_tfmr(cpu_gpr[gprn], tcg_env); } =20 void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn) { - gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]); + gen_helper_store_tfmr(tcg_env, cpu_gpr[gprn]); } =20 void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); + gen_helper_store_lpcr(tcg_env, cpu_gpr[gprn]); } #endif /* !defined(CONFIG_USER_ONLY) */ =20 @@ -1812,7 +1812,7 @@ GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); static void gen_##name(DisasContext *ctx) = \ { = \ TCGv_i32 t0 =3D tcg_constant_i32(compute_ov); = \ - gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, = \ + gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], tcg_env, = \ cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t= 0); \ if (unlikely(Rc(ctx->opcode) !=3D 0)) { = \ gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); = \ @@ -2317,7 +2317,7 @@ GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); static void gen_pause(DisasContext *ctx) { TCGv_i32 t0 =3D tcg_constant_i32(0); - tcg_gen_st_i32(t0, cpu_env, + tcg_gen_st_i32(t0, tcg_env, -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)= ); =20 /* Stop translation, this gives other CPUs a chance to run */ @@ -2912,7 +2912,7 @@ static void gen_slw(DisasContext *ctx) /* sraw & sraw. */ static void gen_sraw(DisasContext *ctx) { - gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, + gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], tcg_env, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); @@ -2995,7 +2995,7 @@ static void gen_sld(DisasContext *ctx) /* srad & srad. */ static void gen_srad(DisasContext *ctx) { - gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, + gen_helper_srad(cpu_gpr[rA(ctx->opcode)], tcg_env, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); if (unlikely(Rc(ctx->opcode) !=3D 0)) { gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); @@ -3360,7 +3360,7 @@ static void gen_lmw(DisasContext *ctx) t0 =3D tcg_temp_new(); t1 =3D tcg_constant_i32(rD(ctx->opcode)); gen_addr_imm_index(ctx, t0, 0); - gen_helper_lmw(cpu_env, t0, t1); + gen_helper_lmw(tcg_env, t0, t1); } =20 /* stmw */ @@ -3377,7 +3377,7 @@ static void gen_stmw(DisasContext *ctx) t0 =3D tcg_temp_new(); t1 =3D tcg_constant_i32(rS(ctx->opcode)); gen_addr_imm_index(ctx, t0, 0); - gen_helper_stmw(cpu_env, t0, t1); + gen_helper_stmw(tcg_env, t0, t1); } =20 /*** Integer load and store strings = ***/ @@ -3415,7 +3415,7 @@ static void gen_lswi(DisasContext *ctx) gen_addr_register(ctx, t0); t1 =3D tcg_constant_i32(nb); t2 =3D tcg_constant_i32(start); - gen_helper_lsw(cpu_env, t0, t1, t2); + gen_helper_lsw(tcg_env, t0, t1, t2); } =20 /* lswx */ @@ -3434,7 +3434,7 @@ static void gen_lswx(DisasContext *ctx) t1 =3D tcg_constant_i32(rD(ctx->opcode)); t2 =3D tcg_constant_i32(rA(ctx->opcode)); t3 =3D tcg_constant_i32(rB(ctx->opcode)); - gen_helper_lswx(cpu_env, t0, t1, t2, t3); + gen_helper_lswx(tcg_env, t0, t1, t2, t3); } =20 /* stswi */ @@ -3456,7 +3456,7 @@ static void gen_stswi(DisasContext *ctx) } t1 =3D tcg_constant_i32(nb); t2 =3D tcg_constant_i32(rS(ctx->opcode)); - gen_helper_stsw(cpu_env, t0, t1, t2); + gen_helper_stsw(tcg_env, t0, t1, t2); } =20 /* stswx */ @@ -3476,7 +3476,7 @@ static void gen_stswx(DisasContext *ctx) tcg_gen_trunc_tl_i32(t1, cpu_xer); tcg_gen_andi_i32(t1, t1, 0x7F); t2 =3D tcg_constant_i32(rS(ctx->opcode)); - gen_helper_stsw(cpu_env, t0, t1, t2); + gen_helper_stsw(tcg_env, t0, t1, t2); } =20 /*** Memory synchronisation = ***/ @@ -3543,12 +3543,12 @@ static inline void gen_check_tlb_flush(DisasContext= *ctx, bool global) } l =3D gen_new_label(); t =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); + tcg_gen_ld_i32(t, tcg_env, offsetof(CPUPPCState, tlb_need_flush)); tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); if (global) { - gen_helper_check_tlb_flush_global(cpu_env); + gen_helper_check_tlb_flush_global(tcg_env); } else { - gen_helper_check_tlb_flush_local(cpu_env); + gen_helper_check_tlb_flush_local(tcg_env); } gen_set_label(l); } @@ -3710,7 +3710,7 @@ static void gen_ld_atomic(DisasContext *ctx, MemOp me= mop) =20 if (need_serial) { /* Restart with exclusive lock. */ - gen_helper_exit_atomic(cpu_env); + gen_helper_exit_atomic(tcg_env); ctx->base.is_jmp =3D DISAS_NORETURN; } } @@ -3766,7 +3766,7 @@ static void gen_st_atomic(DisasContext *ctx, MemOp me= mop) case 24: /* Store twin */ if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { /* Restart with exclusive lock. */ - gen_helper_exit_atomic(cpu_env); + gen_helper_exit_atomic(tcg_env); ctx->base.is_jmp =3D DISAS_NORETURN; } else { TCGv t =3D tcg_temp_new(); @@ -3876,8 +3876,8 @@ static void gen_lqarx(DisasContext *ctx) =20 tcg_gen_mov_tl(cpu_reserve, EA); tcg_gen_movi_tl(cpu_reserve_length, 16); - tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); - tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); + tcg_gen_st_tl(hi, tcg_env, offsetof(CPUPPCState, reserve_val)); + tcg_gen_st_tl(lo, tcg_env, offsetof(CPUPPCState, reserve_val2)); } =20 /* stqcx. */ @@ -4011,7 +4011,7 @@ static void gen_wait(DisasContext *ctx) */ if (wc =3D=3D 0) { TCGv_i32 t0 =3D tcg_constant_i32(1); - tcg_gen_st_i32(t0, cpu_env, + tcg_gen_st_i32(t0, tcg_env, -offsetof(PowerPCCPU, env) + offsetof(CPUState, hal= ted)); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); @@ -4058,7 +4058,7 @@ static void gen_doze(DisasContext *ctx) CHK_HV(ctx); translator_io_start(&ctx->base); t =3D tcg_constant_i32(PPC_PM_DOZE); - gen_helper_pminsn(cpu_env, t); + gen_helper_pminsn(tcg_env, t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); #endif /* defined(CONFIG_USER_ONLY) */ @@ -4074,7 +4074,7 @@ static void gen_nap(DisasContext *ctx) CHK_HV(ctx); translator_io_start(&ctx->base); t =3D tcg_constant_i32(PPC_PM_NAP); - gen_helper_pminsn(cpu_env, t); + gen_helper_pminsn(tcg_env, t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); #endif /* defined(CONFIG_USER_ONLY) */ @@ -4090,7 +4090,7 @@ static void gen_stop(DisasContext *ctx) CHK_HV(ctx); translator_io_start(&ctx->base); t =3D tcg_constant_i32(PPC_PM_STOP); - gen_helper_pminsn(cpu_env, t); + gen_helper_pminsn(tcg_env, t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); #endif /* defined(CONFIG_USER_ONLY) */ @@ -4106,7 +4106,7 @@ static void gen_sleep(DisasContext *ctx) CHK_HV(ctx); translator_io_start(&ctx->base); t =3D tcg_constant_i32(PPC_PM_SLEEP); - gen_helper_pminsn(cpu_env, t); + gen_helper_pminsn(tcg_env, t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); #endif /* defined(CONFIG_USER_ONLY) */ @@ -4122,7 +4122,7 @@ static void gen_rvwinkle(DisasContext *ctx) CHK_HV(ctx); translator_io_start(&ctx->base); t =3D tcg_constant_i32(PPC_PM_RVWINKLE); - gen_helper_pminsn(cpu_env, t); + gen_helper_pminsn(tcg_env, t); /* Stop translation, as the CPU is supposed to sleep from now */ gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); #endif /* defined(CONFIG_USER_ONLY) */ @@ -4172,12 +4172,12 @@ static void pmu_count_insns(DisasContext *ctx) /* Check for overflow, if it's enabled */ if (ctx->mmcr0_pmcjce) { tcg_gen_brcondi_tl(TCG_COND_LT, t0, PMC_COUNTER_NEGATIVE_VAL, = l); - gen_helper_handle_pmc5_overflow(cpu_env); + gen_helper_handle_pmc5_overflow(tcg_env); } =20 gen_set_label(l); } else { - gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns= )); + gen_helper_insns_inc(tcg_env, tcg_constant_i32(ctx->base.num_insns= )); } #else /* @@ -4477,7 +4477,7 @@ static void gen_rfi(DisasContext *ctx) CHK_SV(ctx); translator_io_start(&ctx->base); gen_update_cfar(ctx, ctx->cia); - gen_helper_rfi(cpu_env); + gen_helper_rfi(tcg_env); ctx->base.is_jmp =3D DISAS_EXIT; #endif } @@ -4492,7 +4492,7 @@ static void gen_rfid(DisasContext *ctx) CHK_SV(ctx); translator_io_start(&ctx->base); gen_update_cfar(ctx, ctx->cia); - gen_helper_rfid(cpu_env); + gen_helper_rfid(tcg_env); ctx->base.is_jmp =3D DISAS_EXIT; #endif } @@ -4507,7 +4507,7 @@ static void gen_rfscv(DisasContext *ctx) CHK_SV(ctx); translator_io_start(&ctx->base); gen_update_cfar(ctx, ctx->cia); - gen_helper_rfscv(cpu_env); + gen_helper_rfscv(tcg_env); ctx->base.is_jmp =3D DISAS_EXIT; #endif } @@ -4521,7 +4521,7 @@ static void gen_hrfid(DisasContext *ctx) /* Restore CPU state */ CHK_HV(ctx); translator_io_start(&ctx->base); - gen_helper_hrfid(cpu_env); + gen_helper_hrfid(tcg_env); ctx->base.is_jmp =3D DISAS_EXIT; #endif } @@ -4554,7 +4554,7 @@ static void gen_scv(DisasContext *ctx) =20 /* Set the PC back to the faulting instruction. */ gen_update_nip(ctx, ctx->cia); - gen_helper_scv(cpu_env, tcg_constant_i32(lev)); + gen_helper_scv(tcg_env, tcg_constant_i32(lev)); =20 ctx->base.is_jmp =3D DISAS_NORETURN; } @@ -4587,7 +4587,7 @@ static void gen_tw(DisasContext *ctx) return; } t0 =3D tcg_constant_i32(TO(ctx->opcode)); - gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcod= e)], + gen_helper_tw(tcg_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcod= e)], t0); } =20 @@ -4602,7 +4602,7 @@ static void gen_twi(DisasContext *ctx) } t0 =3D tcg_constant_tl(SIMM(ctx->opcode)); t1 =3D tcg_constant_i32(TO(ctx->opcode)); - gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); + gen_helper_tw(tcg_env, cpu_gpr[rA(ctx->opcode)], t0, t1); } =20 #if defined(TARGET_PPC64) @@ -4615,7 +4615,7 @@ static void gen_td(DisasContext *ctx) return; } t0 =3D tcg_constant_i32(TO(ctx->opcode)); - gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcod= e)], + gen_helper_td(tcg_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcod= e)], t0); } =20 @@ -4630,7 +4630,7 @@ static void gen_tdi(DisasContext *ctx) } t0 =3D tcg_constant_tl(SIMM(ctx->opcode)); t1 =3D tcg_constant_i32(TO(ctx->opcode)); - gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); + gen_helper_td(tcg_env, cpu_gpr[rA(ctx->opcode)], t0, t1); } #endif =20 @@ -4856,7 +4856,7 @@ static void gen_mtmsrd(DisasContext *ctx) tcg_gen_andi_tl(t1, cpu_msr, ~mask); tcg_gen_or_tl(t0, t0, t1); =20 - gen_helper_store_msr(cpu_env, t0); + gen_helper_store_msr(tcg_env, t0); =20 /* Must stop the translation as machine state (may have) changed */ ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; @@ -4895,7 +4895,7 @@ static void gen_mtmsr(DisasContext *ctx) tcg_gen_andi_tl(t1, cpu_msr, ~mask); tcg_gen_or_tl(t0, t0, t1); =20 - gen_helper_store_msr(cpu_env, t0); + gen_helper_store_msr(tcg_env, t0); =20 /* Must stop the translation as machine state (may have) changed */ ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; @@ -5108,7 +5108,7 @@ static void gen_dcbz(DisasContext *ctx) tcgv_addr =3D tcg_temp_new(); tcgv_op =3D tcg_constant_i32(ctx->opcode & 0x03FF000); gen_addr_reg_index(ctx, tcgv_addr); - gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); + gen_helper_dcbz(tcg_env, tcgv_addr, tcgv_op); } =20 /* dcbzep */ @@ -5121,7 +5121,7 @@ static void gen_dcbzep(DisasContext *ctx) tcgv_addr =3D tcg_temp_new(); tcgv_op =3D tcg_constant_i32(ctx->opcode & 0x03FF000); gen_addr_reg_index(ctx, tcgv_addr); - gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); + gen_helper_dcbzep(tcg_env, tcgv_addr, tcgv_op); } =20 /* dst / dstt */ @@ -5158,7 +5158,7 @@ static void gen_icbi(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_CACHE); t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_helper_icbi(cpu_env, t0); + gen_helper_icbi(tcg_env, t0); } =20 /* icbiep */ @@ -5168,7 +5168,7 @@ static void gen_icbiep(DisasContext *ctx) gen_set_access_type(ctx, ACCESS_CACHE); t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_helper_icbiep(cpu_env, t0); + gen_helper_icbiep(tcg_env, t0); } =20 /* Optional: */ @@ -5195,7 +5195,7 @@ static void gen_mfsr(DisasContext *ctx) =20 CHK_SV(ctx); t0 =3D tcg_constant_tl(SR(ctx->opcode)); - gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); + gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5210,7 +5210,7 @@ static void gen_mfsrin(DisasContext *ctx) CHK_SV(ctx); t0 =3D tcg_temp_new(); tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); - gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); + gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5224,7 +5224,7 @@ static void gen_mtsr(DisasContext *ctx) =20 CHK_SV(ctx); t0 =3D tcg_constant_tl(SR(ctx->opcode)); - gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); + gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5239,7 +5239,7 @@ static void gen_mtsrin(DisasContext *ctx) =20 t0 =3D tcg_temp_new(); tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); - gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); + gen_helper_store_sr(tcg_env, t0, cpu_gpr[rD(ctx->opcode)]); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5256,7 +5256,7 @@ static void gen_mfsr_64b(DisasContext *ctx) =20 CHK_SV(ctx); t0 =3D tcg_constant_tl(SR(ctx->opcode)); - gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); + gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5271,7 +5271,7 @@ static void gen_mfsrin_64b(DisasContext *ctx) CHK_SV(ctx); t0 =3D tcg_temp_new(); tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); - gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); + gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5285,7 +5285,7 @@ static void gen_mtsr_64b(DisasContext *ctx) =20 CHK_SV(ctx); t0 =3D tcg_constant_tl(SR(ctx->opcode)); - gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); + gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5300,7 +5300,7 @@ static void gen_mtsrin_64b(DisasContext *ctx) CHK_SV(ctx); t0 =3D tcg_temp_new(); tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); - gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); + gen_helper_store_sr(tcg_env, t0, cpu_gpr[rS(ctx->opcode)]); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5317,7 +5317,7 @@ static void gen_tlbia(DisasContext *ctx) #else CHK_HV(ctx); =20 - gen_helper_tlbia(cpu_env); + gen_helper_tlbia(tcg_env); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5377,7 +5377,7 @@ static void gen_tlbld_6xx(DisasContext *ctx) GEN_PRIV(ctx); #else CHK_SV(ctx); - gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); + gen_helper_6xx_tlbd(tcg_env, cpu_gpr[rB(ctx->opcode)]); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5388,7 +5388,7 @@ static void gen_tlbli_6xx(DisasContext *ctx) GEN_PRIV(ctx); #else CHK_SV(ctx); - gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); + gen_helper_6xx_tlbi(tcg_env, cpu_gpr[rB(ctx->opcode)]); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5412,7 +5412,7 @@ static void gen_tlbiva(DisasContext *ctx) CHK_SV(ctx); t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); + gen_helper_tlbiva(tcg_env, cpu_gpr[rB(ctx->opcode)]); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5639,7 +5639,7 @@ static void gen_mfdcr(DisasContext *ctx) =20 CHK_SV(ctx); dcrn =3D tcg_constant_tl(SPR(ctx->opcode)); - gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); + gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env, dcrn); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5653,7 +5653,7 @@ static void gen_mtdcr(DisasContext *ctx) =20 CHK_SV(ctx); dcrn =3D tcg_constant_tl(SPR(ctx->opcode)); - gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); + gen_helper_store_dcr(tcg_env, dcrn, cpu_gpr[rS(ctx->opcode)]); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5665,7 +5665,7 @@ static void gen_mfdcrx(DisasContext *ctx) GEN_PRIV(ctx); #else CHK_SV(ctx); - gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, + gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], tcg_env, cpu_gpr[rA(ctx->opcode)]); /* Note: Rc update flag set leads to undefined state of Rc0 */ #endif /* defined(CONFIG_USER_ONLY) */ @@ -5679,7 +5679,7 @@ static void gen_mtdcrx(DisasContext *ctx) GEN_PRIV(ctx); #else CHK_SV(ctx); - gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], + gen_helper_store_dcr(tcg_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); /* Note: Rc update flag set leads to undefined state of Rc0 */ #endif /* defined(CONFIG_USER_ONLY) */ @@ -5742,7 +5742,7 @@ static void gen_rfci_40x(DisasContext *ctx) #else CHK_SV(ctx); /* Restore CPU state */ - gen_helper_40x_rfci(cpu_env); + gen_helper_40x_rfci(tcg_env); ctx->base.is_jmp =3D DISAS_EXIT; #endif /* defined(CONFIG_USER_ONLY) */ } @@ -5754,7 +5754,7 @@ static void gen_rfci(DisasContext *ctx) #else CHK_SV(ctx); /* Restore CPU state */ - gen_helper_rfci(cpu_env); + gen_helper_rfci(tcg_env); ctx->base.is_jmp =3D DISAS_EXIT; #endif /* defined(CONFIG_USER_ONLY) */ } @@ -5769,7 +5769,7 @@ static void gen_rfdi(DisasContext *ctx) #else CHK_SV(ctx); /* Restore CPU state */ - gen_helper_rfdi(cpu_env); + gen_helper_rfdi(tcg_env); ctx->base.is_jmp =3D DISAS_EXIT; #endif /* defined(CONFIG_USER_ONLY) */ } @@ -5782,7 +5782,7 @@ static void gen_rfmci(DisasContext *ctx) #else CHK_SV(ctx); /* Restore CPU state */ - gen_helper_rfmci(cpu_env); + gen_helper_rfmci(tcg_env); ctx->base.is_jmp =3D DISAS_EXIT; #endif /* defined(CONFIG_USER_ONLY) */ } @@ -5798,11 +5798,11 @@ static void gen_tlbre_40x(DisasContext *ctx) CHK_SV(ctx); switch (rB(ctx->opcode)) { case 0: - gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, + gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], tcg_env, cpu_gpr[rA(ctx->opcode)]); break; case 1: - gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, + gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], tcg_env, cpu_gpr[rA(ctx->opcode)]); break; default: @@ -5823,7 +5823,7 @@ static void gen_tlbsx_40x(DisasContext *ctx) CHK_SV(ctx); t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); + gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); if (Rc(ctx->opcode)) { TCGLabel *l1 =3D gen_new_label(); tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); @@ -5844,11 +5844,11 @@ static void gen_tlbwe_40x(DisasContext *ctx) =20 switch (rB(ctx->opcode)) { case 0: - gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], + gen_helper_4xx_tlbwe_hi(tcg_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); break; case 1: - gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], + gen_helper_4xx_tlbwe_lo(tcg_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); break; default: @@ -5874,7 +5874,7 @@ static void gen_tlbre_440(DisasContext *ctx) case 2: { TCGv_i32 t0 =3D tcg_constant_i32(rB(ctx->opcode)); - gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, + gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], tcg_env, t0, cpu_gpr[rA(ctx->opcode)]); } break; @@ -5896,7 +5896,7 @@ static void gen_tlbsx_440(DisasContext *ctx) CHK_SV(ctx); t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); + gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], tcg_env, t0); if (Rc(ctx->opcode)) { TCGLabel *l1 =3D gen_new_label(); tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); @@ -5920,7 +5920,7 @@ static void gen_tlbwe_440(DisasContext *ctx) case 2: { TCGv_i32 t0 =3D tcg_constant_i32(rB(ctx->opcode)); - gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], + gen_helper_440_tlbwe(tcg_env, t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); } break; @@ -5940,7 +5940,7 @@ static void gen_tlbre_booke206(DisasContext *ctx) GEN_PRIV(ctx); #else CHK_SV(ctx); - gen_helper_booke206_tlbre(cpu_env); + gen_helper_booke206_tlbre(tcg_env); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5959,7 +5959,7 @@ static void gen_tlbsx_booke206(DisasContext *ctx) } else { t0 =3D cpu_gpr[rB(ctx->opcode)]; } - gen_helper_booke206_tlbsx(cpu_env, t0); + gen_helper_booke206_tlbsx(tcg_env, t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5970,7 +5970,7 @@ static void gen_tlbwe_booke206(DisasContext *ctx) GEN_PRIV(ctx); #else CHK_SV(ctx); - gen_helper_booke206_tlbwe(cpu_env); + gen_helper_booke206_tlbwe(tcg_env); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -5984,7 +5984,7 @@ static void gen_tlbivax_booke206(DisasContext *ctx) CHK_SV(ctx); t0 =3D tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_helper_booke206_tlbivax(cpu_env, t0); + gen_helper_booke206_tlbivax(tcg_env, t0); #endif /* defined(CONFIG_USER_ONLY) */ } =20 @@ -6001,13 +6001,13 @@ static void gen_tlbilx_booke206(DisasContext *ctx) =20 switch ((ctx->opcode >> 21) & 0x3) { case 0: - gen_helper_booke206_tlbilx0(cpu_env, t0); + gen_helper_booke206_tlbilx0(tcg_env, t0); break; case 1: - gen_helper_booke206_tlbilx1(cpu_env, t0); + gen_helper_booke206_tlbilx1(tcg_env, t0); break; case 3: - gen_helper_booke206_tlbilx3(cpu_env, t0); + gen_helper_booke206_tlbilx3(tcg_env, t0); break; default: gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); @@ -6062,7 +6062,7 @@ static void gen_wrteei(DisasContext *ctx) static void gen_dlmzb(DisasContext *ctx) { TCGv_i32 t0 =3D tcg_constant_i32(Rc(ctx->opcode)); - gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, + gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], tcg_env, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t= 0); } =20 @@ -6129,7 +6129,7 @@ static void gen_tbegin(DisasContext *ctx) gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); return; } - gen_helper_tbegin(cpu_env); + gen_helper_tbegin(tcg_env); } =20 #define GEN_TM_NOOP(name) \ @@ -6225,12 +6225,12 @@ GEN_TM_PRIV_NOOP(trechkpt); =20 static inline void get_fpr(TCGv_i64 dst, int regno) { - tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); + tcg_gen_ld_i64(dst, tcg_env, fpr_offset(regno)); } =20 static inline void set_fpr(int regno, TCGv_i64 src) { - tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); + tcg_gen_st_i64(src, tcg_env, fpr_offset(regno)); /* * Before PowerISA v3.1 the result of doubleword 1 of the VSR * corresponding to the target FPR was undefined. However, @@ -6238,17 +6238,17 @@ static inline void set_fpr(int regno, TCGv_i64 src) * Starting at ISA v3.1, the result for doubleword 1 is now defined * to be 0. */ - tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false= )); + tcg_gen_st_i64(tcg_constant_i64(0), tcg_env, vsr64_offset(regno, false= )); } =20 static inline void get_avr64(TCGv_i64 dst, int regno, bool high) { - tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); + tcg_gen_ld_i64(dst, tcg_env, avr64_offset(regno, high)); } =20 static inline void set_avr64(int regno, TCGv_i64 src, bool high) { - tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); + tcg_gen_st_i64(src, tcg_env, avr64_offset(regno, high)); } =20 /* diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 7dbf173adb..2ad5192866 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -238,13 +238,13 @@ static void gen_update_pc(DisasContext *ctx, target_l= ong diff) static void generate_exception(DisasContext *ctx, int excp) { gen_update_pc(ctx, 0); - gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); + gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_exception_illegal(DisasContext *ctx) { - tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, + tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), tcg_env, offsetof(CPURISCVState, bins)); if (ctx->virt_inst_excp) { generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); @@ -255,7 +255,7 @@ static void gen_exception_illegal(DisasContext *ctx) =20 static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target) { - tcg_gen_st_tl(target, cpu_env, offsetof(CPURISCVState, badaddr)); + tcg_gen_st_tl(target, tcg_env, offsetof(CPURISCVState, badaddr)); generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); } =20 @@ -263,7 +263,7 @@ static void lookup_and_goto_ptr(DisasContext *ctx) { #ifndef CONFIG_USER_ONLY if (ctx->itrigger) { - gen_helper_itrigger_match(cpu_env); + gen_helper_itrigger_match(tcg_env); } #endif tcg_gen_lookup_and_goto_ptr(); @@ -273,7 +273,7 @@ static void exit_tb(DisasContext *ctx) { #ifndef CONFIG_USER_ONLY if (ctx->itrigger) { - gen_helper_itrigger_match(cpu_env); + gen_helper_itrigger_match(tcg_env); } #endif tcg_gen_exit_tb(NULL, 0); @@ -630,14 +630,14 @@ static void mark_fs_dirty(DisasContext *ctx) ctx->mstatus_fs =3D EXT_STATUS_DIRTY; =20 tmp =3D tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); - tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); =20 if (ctx->virt_enabled) { - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs= )); + tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs= )); tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); - tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs= )); + tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs= )); } } } @@ -659,14 +659,14 @@ static void mark_vs_dirty(DisasContext *ctx) ctx->mstatus_vs =3D EXT_STATUS_DIRTY; =20 tmp =3D tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); - tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); =20 if (ctx->virt_enabled) { - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs= )); + tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs= )); tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); - tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs= )); + tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs= )); } } } @@ -688,7 +688,7 @@ static void gen_set_rm(DisasContext *ctx, int rm) =20 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ decode_save_opc(ctx); - gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); + gen_helper_set_rounding_mode(tcg_env, tcg_constant_i32(rm)); } =20 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) @@ -701,7 +701,7 @@ static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) =20 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ decode_save_opc(ctx); - gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); + gen_helper_set_rounding_mode_chkfrm(tcg_env, tcg_constant_i32(rm)); } =20 static int ex_plus_1(DisasContext *ctx, int nf) @@ -1306,28 +1306,28 @@ void riscv_translate_init(void) cpu_gprh[0] =3D NULL; =20 for (i =3D 1; i < 32; i++) { - cpu_gpr[i] =3D tcg_global_mem_new(cpu_env, + cpu_gpr[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); - cpu_gprh[i] =3D tcg_global_mem_new(cpu_env, + cpu_gprh[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); } =20 for (i =3D 0; i < 32; i++) { - cpu_fpr[i] =3D tcg_global_mem_new_i64(cpu_env, + cpu_fpr[i] =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); } =20 - cpu_pc =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "p= c"); - cpu_vl =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "v= l"); - cpu_vstart =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vst= art), + cpu_pc =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "p= c"); + cpu_vl =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "v= l"); + cpu_vstart =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vst= art), "vstart"); - load_res =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_= res), + load_res =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_= res), "load_res"); - load_val =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_= val), + load_val =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_= val), "load_val"); /* Assign PM CSRs to tcg globals */ - pm_mask =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pm= mask), + pm_mask =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pm= mask), "pmmask"); - pm_base =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pm= base), + pm_base =3D tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pm= base), "pmbase"); } diff --git a/target/rx/translate.c b/target/rx/translate.c index f552a0319a..9fd4d36b08 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -237,7 +237,7 @@ static int is_privileged(DisasContext *ctx, int is_exce= ption) { if (FIELD_EX32(ctx->tb_flags, PSW, PM)) { if (is_exception) { - gen_helper_raise_privilege_violation(cpu_env); + gen_helper_raise_privilege_violation(tcg_env); } return 0; } else { @@ -318,7 +318,7 @@ static void move_from_cr(DisasContext *ctx, TCGv ret, i= nt cr, uint32_t pc) { switch (cr) { case 0: /* PSW */ - gen_helper_pack_psw(ret, cpu_env); + gen_helper_pack_psw(ret, tcg_env); break; case 1: /* PC */ tcg_gen_movi_i32(ret, pc); @@ -370,7 +370,7 @@ static void move_to_cr(DisasContext *ctx, TCGv val, int= cr) } switch (cr) { case 0: /* PSW */ - gen_helper_set_psw(cpu_env, val); + gen_helper_set_psw(tcg_env, val); if (is_privileged(ctx, 0)) { /* PSW.{I,U} may be updated here. exit TB. */ ctx->base.is_jmp =3D DISAS_UPDATE; @@ -385,7 +385,7 @@ static void move_to_cr(DisasContext *ctx, TCGv val, int= cr) } break; case 3: /* FPSW */ - gen_helper_set_fpsw(cpu_env, val); + gen_helper_set_fpsw(tcg_env, val); break; case 8: /* BPSW */ tcg_gen_mov_i32(cpu_bpsw, val); @@ -1244,12 +1244,12 @@ static bool trans_EMULU_mr(DisasContext *ctx, arg_E= MULU_mr *a) =20 static void rx_div(TCGv ret, TCGv arg1, TCGv arg2) { - gen_helper_div(ret, cpu_env, arg1, arg2); + gen_helper_div(ret, tcg_env, arg1, arg2); } =20 static void rx_divu(TCGv ret, TCGv arg1, TCGv arg2) { - gen_helper_divu(ret, cpu_env, arg1, arg2); + gen_helper_divu(ret, tcg_env, arg1, arg2); } =20 /* div #imm, rd */ @@ -1644,35 +1644,35 @@ static bool trans_NOP(DisasContext *ctx, arg_NOP *a) /* scmpu */ static bool trans_SCMPU(DisasContext *ctx, arg_SCMPU *a) { - gen_helper_scmpu(cpu_env); + gen_helper_scmpu(tcg_env); return true; } =20 /* smovu */ static bool trans_SMOVU(DisasContext *ctx, arg_SMOVU *a) { - gen_helper_smovu(cpu_env); + gen_helper_smovu(tcg_env); return true; } =20 /* smovf */ static bool trans_SMOVF(DisasContext *ctx, arg_SMOVF *a) { - gen_helper_smovf(cpu_env); + gen_helper_smovf(tcg_env); return true; } =20 /* smovb */ static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a) { - gen_helper_smovb(cpu_env); + gen_helper_smovb(tcg_env); return true; } =20 #define STRING(op) \ do { \ TCGv size =3D tcg_constant_i32(a->sz); \ - gen_helper_##op(cpu_env, size); \ + gen_helper_##op(tcg_env, size); \ } while (0) =20 /* suntile. */ @@ -1803,7 +1803,7 @@ static bool trans_MVTACLO(DisasContext *ctx, arg_MVTA= CLO *a) static bool trans_RACW(DisasContext *ctx, arg_RACW *a) { TCGv imm =3D tcg_constant_i32(a->imm + 1); - gen_helper_racw(cpu_env, imm); + gen_helper_racw(tcg_env, imm); return true; } =20 @@ -1825,7 +1825,7 @@ static bool trans_SAT(DisasContext *ctx, arg_SAT *a) /* satr */ static bool trans_SATR(DisasContext *ctx, arg_SATR *a) { - gen_helper_satr(cpu_env); + gen_helper_satr(tcg_env); return true; } =20 @@ -1835,7 +1835,7 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a) cat3(arg_, name, _ir) * a) \ { \ TCGv imm =3D tcg_constant_i32(li(ctx, 0)); \ - gen_helper_##op(cpu_regs[a->rd], cpu_env, \ + gen_helper_##op(cpu_regs[a->rd], tcg_env, \ cpu_regs[a->rd], imm); \ return true; \ } \ @@ -1845,7 +1845,7 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a) TCGv val, mem; \ mem =3D tcg_temp_new(); \ val =3D rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ - gen_helper_##op(cpu_regs[a->rd], cpu_env, \ + gen_helper_##op(cpu_regs[a->rd], tcg_env, \ cpu_regs[a->rd], val); \ return true; \ } @@ -1856,7 +1856,7 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a) TCGv val, mem; \ mem =3D tcg_temp_new(); \ val =3D rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ - gen_helper_##op(cpu_regs[a->rd], cpu_env, val); \ + gen_helper_##op(cpu_regs[a->rd], tcg_env, val); \ return true; \ } =20 @@ -1869,7 +1869,7 @@ FOP(FDIV, fdiv) static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a) { TCGv imm =3D tcg_constant_i32(li(ctx, 0)); - gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm); + gen_helper_fcmp(tcg_env, cpu_regs[a->rd], imm); return true; } =20 @@ -1880,7 +1880,7 @@ static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP= _mr *a) TCGv val, mem; mem =3D tcg_temp_new(); val =3D rx_load_source(ctx, mem, a->ld, MO_32, a->rs); - gen_helper_fcmp(cpu_env, cpu_regs[a->rd], val); + gen_helper_fcmp(tcg_env, cpu_regs[a->rd], val); return true; } =20 @@ -1894,7 +1894,7 @@ static bool trans_ITOF(DisasContext *ctx, arg_ITOF * = a) TCGv val, mem; mem =3D tcg_temp_new(); val =3D rx_load_source(ctx, mem, a->ld, a->mi, a->rs); - gen_helper_itof(cpu_regs[a->rd], cpu_env, val); + gen_helper_itof(cpu_regs[a->rd], tcg_env, val); return true; } =20 @@ -2146,7 +2146,7 @@ static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a) psw =3D tcg_temp_new(); tcg_gen_mov_i32(cpu_pc, cpu_bpc); tcg_gen_mov_i32(psw, cpu_bpsw); - gen_helper_set_psw_rte(cpu_env, psw); + gen_helper_set_psw_rte(tcg_env, psw); ctx->base.is_jmp =3D DISAS_EXIT; } return true; @@ -2160,7 +2160,7 @@ static bool trans_RTE(DisasContext *ctx, arg_RTE *a) psw =3D tcg_temp_new(); pop(cpu_pc); pop(psw); - gen_helper_set_psw_rte(cpu_env, psw); + gen_helper_set_psw_rte(tcg_env, psw); ctx->base.is_jmp =3D DISAS_EXIT; } return true; @@ -2170,7 +2170,7 @@ static bool trans_RTE(DisasContext *ctx, arg_RTE *a) static bool trans_BRK(DisasContext *ctx, arg_BRK *a) { tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); - gen_helper_rxbrk(cpu_env); + gen_helper_rxbrk(tcg_env); ctx->base.is_jmp =3D DISAS_NORETURN; return true; } @@ -2183,7 +2183,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a) tcg_debug_assert(a->imm < 0x100); vec =3D tcg_constant_i32(a->imm); tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); - gen_helper_rxint(cpu_env, vec); + gen_helper_rxint(tcg_env, vec); ctx->base.is_jmp =3D DISAS_NORETURN; return true; } @@ -2193,7 +2193,7 @@ static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) { if (is_privileged(ctx, 1)) { tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); - gen_helper_wait(cpu_env); + gen_helper_wait(tcg_env); } return true; } @@ -2225,7 +2225,7 @@ static void rx_tr_translate_insn(DisasContextBase *dc= base, CPUState *cs) ctx->pc =3D ctx->base.pc_next; insn =3D decode_load(ctx); if (!decode(ctx, insn)) { - gen_helper_raise_illegal_instruction(cpu_env); + gen_helper_raise_illegal_instruction(tcg_env); } } =20 @@ -2279,7 +2279,7 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int *max_insns, } =20 #define ALLOC_REGISTER(sym, name) \ - cpu_##sym =3D tcg_global_mem_new_i32(cpu_env, \ + cpu_##sym =3D tcg_global_mem_new_i32(tcg_env, \ offsetof(CPURXState, sym), name) =20 void rx_translate_init(void) @@ -2291,7 +2291,7 @@ void rx_translate_init(void) int i; =20 for (i =3D 0; i < NUM_REGS; i++) { - cpu_regs[i] =3D tcg_global_mem_new_i32(cpu_env, + cpu_regs[i] =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPURXState, regs[i]= ), regnames[i]); } @@ -2311,6 +2311,6 @@ void rx_translate_init(void) ALLOC_REGISTER(isp, "ISP"); ALLOC_REGISTER(fintv, "FINTV"); ALLOC_REGISTER(intb, "INTB"); - cpu_acc =3D tcg_global_mem_new_i64(cpu_env, + cpu_acc =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPURXState, acc), "ACC"); } diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index dc7041e1d8..22f43974dd 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -199,28 +199,28 @@ void s390x_translate_init(void) { int i; =20 - psw_addr =3D tcg_global_mem_new_i64(cpu_env, + psw_addr =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUS390XState, psw.addr), "psw_addr"); - psw_mask =3D tcg_global_mem_new_i64(cpu_env, + psw_mask =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUS390XState, psw.mask), "psw_mask"); - gbea =3D tcg_global_mem_new_i64(cpu_env, + gbea =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUS390XState, gbea), "gbea"); =20 - cc_op =3D tcg_global_mem_new_i32(cpu_env, offsetof(CPUS390XState, cc_o= p), + cc_op =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUS390XState, cc_o= p), "cc_op"); - cc_src =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUS390XState, cc_= src), + cc_src =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUS390XState, cc_= src), "cc_src"); - cc_dst =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUS390XState, cc_= dst), + cc_dst =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUS390XState, cc_= dst), "cc_dst"); - cc_vr =3D tcg_global_mem_new_i64(cpu_env, offsetof(CPUS390XState, cc_v= r), + cc_vr =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUS390XState, cc_v= r), "cc_vr"); =20 for (i =3D 0; i < 16; i++) { snprintf(cpu_reg_names[i], sizeof(cpu_reg_names[0]), "r%d", i); - regs[i] =3D tcg_global_mem_new(cpu_env, + regs[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUS390XState, regs[i]), cpu_reg_names[i]); } @@ -290,7 +290,7 @@ static TCGv_i64 load_freg(int reg) { TCGv_i64 r =3D tcg_temp_new_i64(); =20 - tcg_gen_ld_i64(r, cpu_env, freg64_offset(reg)); + tcg_gen_ld_i64(r, tcg_env, freg64_offset(reg)); return r; } =20 @@ -298,7 +298,7 @@ static TCGv_i64 load_freg32_i64(int reg) { TCGv_i64 r =3D tcg_temp_new_i64(); =20 - tcg_gen_ld32u_i64(r, cpu_env, freg32_offset(reg)); + tcg_gen_ld32u_i64(r, tcg_env, freg32_offset(reg)); return r; } =20 @@ -319,7 +319,7 @@ static void store_reg(int reg, TCGv_i64 v) =20 static void store_freg(int reg, TCGv_i64 v) { - tcg_gen_st_i64(v, cpu_env, freg64_offset(reg)); + tcg_gen_st_i64(v, tcg_env, freg64_offset(reg)); } =20 static void store_reg32_i64(int reg, TCGv_i64 v) @@ -335,7 +335,7 @@ static void store_reg32h_i64(int reg, TCGv_i64 v) =20 static void store_freg32_i64(int reg, TCGv_i64 v) { - tcg_gen_st32_i64(v, cpu_env, freg32_offset(reg)); + tcg_gen_st32_i64(v, tcg_env, freg32_offset(reg)); } =20 static void update_psw_addr(DisasContext *s) @@ -351,7 +351,7 @@ static void per_branch(DisasContext *s, bool to_next) =20 if (s->base.tb->flags & FLAG_MASK_PER) { TCGv_i64 next_pc =3D to_next ? tcg_constant_i64(s->pc_tmp) : psw_a= ddr; - gen_helper_per_branch(cpu_env, gbea, next_pc); + gen_helper_per_branch(tcg_env, gbea, next_pc); } #endif } @@ -365,7 +365,7 @@ static void per_branch_cond(DisasContext *s, TCGCond co= nd, tcg_gen_brcond_i64(tcg_invert_cond(cond), arg1, arg2, lab); =20 tcg_gen_movi_i64(gbea, s->base.pc_next); - gen_helper_per_branch(cpu_env, gbea, psw_addr); + gen_helper_per_branch(tcg_env, gbea, psw_addr); =20 gen_set_label(lab); } else { @@ -424,16 +424,16 @@ static int get_mem_index(DisasContext *s) =20 static void gen_exception(int excp) { - gen_helper_exception(cpu_env, tcg_constant_i32(excp)); + gen_helper_exception(tcg_env, tcg_constant_i32(excp)); } =20 static void gen_program_exception(DisasContext *s, int code) { /* Remember what pgm exception this was. */ - tcg_gen_st_i32(tcg_constant_i32(code), cpu_env, + tcg_gen_st_i32(tcg_constant_i32(code), tcg_env, offsetof(CPUS390XState, int_pgm_code)); =20 - tcg_gen_st_i32(tcg_constant_i32(s->ilen), cpu_env, + tcg_gen_st_i32(tcg_constant_i32(s->ilen), tcg_env, offsetof(CPUS390XState, int_pgm_ilen)); =20 /* update the psw */ @@ -453,7 +453,7 @@ static inline void gen_illegal_opcode(DisasContext *s) =20 static inline void gen_data_exception(uint8_t dxc) { - gen_helper_data_exception(cpu_env, tcg_constant_i32(dxc)); + gen_helper_data_exception(tcg_env, tcg_constant_i32(dxc)); } =20 static inline void gen_trap(DisasContext *s) @@ -620,7 +620,7 @@ static void gen_op_calc_cc(DisasContext *s) case CC_OP_LCBB: case CC_OP_MULS_32: /* 1 argument */ - gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, dummy, cc_dst, dum= my); + gen_helper_calc_cc(cc_op, tcg_env, local_cc_op, dummy, cc_dst, dum= my); break; case CC_OP_ADDU: case CC_OP_ICM: @@ -636,18 +636,18 @@ static void gen_op_calc_cc(DisasContext *s) case CC_OP_VC: case CC_OP_MULS_64: /* 2 arguments */ - gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, du= mmy); + gen_helper_calc_cc(cc_op, tcg_env, local_cc_op, cc_src, cc_dst, du= mmy); break; case CC_OP_ADD_64: case CC_OP_SUB_64: case CC_OP_ADD_32: case CC_OP_SUB_32: /* 3 arguments */ - gen_helper_calc_cc(cc_op, cpu_env, local_cc_op, cc_src, cc_dst, cc= _vr); + gen_helper_calc_cc(cc_op, tcg_env, local_cc_op, cc_src, cc_dst, cc= _vr); break; case CC_OP_DYNAMIC: /* unknown operation - assume 3 arguments and cc_op in env */ - gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr); + gen_helper_calc_cc(cc_op, tcg_env, cc_op, cc_src, cc_dst, cc_vr); break; default: g_assert_not_reached(); @@ -1398,19 +1398,19 @@ static DisasJumpType op_asiu64(DisasContext *s, Dis= asOps *o) =20 static DisasJumpType op_aeb(DisasContext *s, DisasOps *o) { - gen_helper_aeb(o->out, cpu_env, o->in1, o->in2); + gen_helper_aeb(o->out, tcg_env, o->in1, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_adb(DisasContext *s, DisasOps *o) { - gen_helper_adb(o->out, cpu_env, o->in1, o->in2); + gen_helper_adb(o->out, tcg_env, o->in1, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_axb(DisasContext *s, DisasOps *o) { - gen_helper_axb(o->out_128, cpu_env, o->in1_128, o->in2_128); + gen_helper_axb(o->out_128, tcg_env, o->in1_128, o->in2_128); return DISAS_NEXT; } =20 @@ -1546,7 +1546,7 @@ static DisasJumpType op_bal(DisasContext *s, DisasOps= *o) if (have_field(s, ri)) { = \ if (unlikely(s->ex_value)) { = \ cdest =3D tcg_temp_new_i64(); = \ - tcg_gen_ld_i64(cdest, cpu_env, offsetof(CPUS390XState, ex_targ= et));\ + tcg_gen_ld_i64(cdest, tcg_env, offsetof(CPUS390XState, ex_targ= et));\ tcg_gen_addi_i64(cdest, cdest, (int64_t)get_field(s, ri) * 2);= \ is_imm =3D false; = \ } else { = \ @@ -1734,21 +1734,21 @@ static DisasJumpType op_cj(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_ceb(DisasContext *s, DisasOps *o) { - gen_helper_ceb(cc_op, cpu_env, o->in1, o->in2); + gen_helper_ceb(cc_op, tcg_env, o->in1, o->in2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_cdb(DisasContext *s, DisasOps *o) { - gen_helper_cdb(cc_op, cpu_env, o->in1, o->in2); + gen_helper_cdb(cc_op, tcg_env, o->in1, o->in2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_cxb(DisasContext *s, DisasOps *o) { - gen_helper_cxb(cc_op, cpu_env, o->in1_128, o->in2_128); + gen_helper_cxb(cc_op, tcg_env, o->in1_128, o->in2_128); set_cc_static(s); return DISAS_NEXT; } @@ -1785,7 +1785,7 @@ static DisasJumpType op_cfeb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cfeb(o->out, cpu_env, o->in2, m34); + gen_helper_cfeb(o->out, tcg_env, o->in2, m34); set_cc_static(s); return DISAS_NEXT; } @@ -1797,7 +1797,7 @@ static DisasJumpType op_cfdb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cfdb(o->out, cpu_env, o->in2, m34); + gen_helper_cfdb(o->out, tcg_env, o->in2, m34); set_cc_static(s); return DISAS_NEXT; } @@ -1809,7 +1809,7 @@ static DisasJumpType op_cfxb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cfxb(o->out, cpu_env, o->in2_128, m34); + gen_helper_cfxb(o->out, tcg_env, o->in2_128, m34); set_cc_static(s); return DISAS_NEXT; } @@ -1821,7 +1821,7 @@ static DisasJumpType op_cgeb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cgeb(o->out, cpu_env, o->in2, m34); + gen_helper_cgeb(o->out, tcg_env, o->in2, m34); set_cc_static(s); return DISAS_NEXT; } @@ -1833,7 +1833,7 @@ static DisasJumpType op_cgdb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cgdb(o->out, cpu_env, o->in2, m34); + gen_helper_cgdb(o->out, tcg_env, o->in2, m34); set_cc_static(s); return DISAS_NEXT; } @@ -1845,7 +1845,7 @@ static DisasJumpType op_cgxb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cgxb(o->out, cpu_env, o->in2_128, m34); + gen_helper_cgxb(o->out, tcg_env, o->in2_128, m34); set_cc_static(s); return DISAS_NEXT; } @@ -1857,7 +1857,7 @@ static DisasJumpType op_clfeb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_clfeb(o->out, cpu_env, o->in2, m34); + gen_helper_clfeb(o->out, tcg_env, o->in2, m34); set_cc_static(s); return DISAS_NEXT; } @@ -1869,7 +1869,7 @@ static DisasJumpType op_clfdb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_clfdb(o->out, cpu_env, o->in2, m34); + gen_helper_clfdb(o->out, tcg_env, o->in2, m34); set_cc_static(s); return DISAS_NEXT; } @@ -1881,7 +1881,7 @@ static DisasJumpType op_clfxb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_clfxb(o->out, cpu_env, o->in2_128, m34); + gen_helper_clfxb(o->out, tcg_env, o->in2_128, m34); set_cc_static(s); return DISAS_NEXT; } @@ -1893,7 +1893,7 @@ static DisasJumpType op_clgeb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_clgeb(o->out, cpu_env, o->in2, m34); + gen_helper_clgeb(o->out, tcg_env, o->in2, m34); set_cc_static(s); return DISAS_NEXT; } @@ -1905,7 +1905,7 @@ static DisasJumpType op_clgdb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_clgdb(o->out, cpu_env, o->in2, m34); + gen_helper_clgdb(o->out, tcg_env, o->in2, m34); set_cc_static(s); return DISAS_NEXT; } @@ -1917,7 +1917,7 @@ static DisasJumpType op_clgxb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_clgxb(o->out, cpu_env, o->in2_128, m34); + gen_helper_clgxb(o->out, tcg_env, o->in2_128, m34); set_cc_static(s); return DISAS_NEXT; } @@ -1929,7 +1929,7 @@ static DisasJumpType op_cegb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cegb(o->out, cpu_env, o->in2, m34); + gen_helper_cegb(o->out, tcg_env, o->in2, m34); return DISAS_NEXT; } =20 @@ -1940,7 +1940,7 @@ static DisasJumpType op_cdgb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cdgb(o->out, cpu_env, o->in2, m34); + gen_helper_cdgb(o->out, tcg_env, o->in2, m34); return DISAS_NEXT; } =20 @@ -1951,7 +1951,7 @@ static DisasJumpType op_cxgb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cxgb(o->out_128, cpu_env, o->in2, m34); + gen_helper_cxgb(o->out_128, tcg_env, o->in2, m34); return DISAS_NEXT; } =20 @@ -1962,7 +1962,7 @@ static DisasJumpType op_celgb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_celgb(o->out, cpu_env, o->in2, m34); + gen_helper_celgb(o->out, tcg_env, o->in2, m34); return DISAS_NEXT; } =20 @@ -1973,7 +1973,7 @@ static DisasJumpType op_cdlgb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cdlgb(o->out, cpu_env, o->in2, m34); + gen_helper_cdlgb(o->out, tcg_env, o->in2, m34); return DISAS_NEXT; } =20 @@ -1984,7 +1984,7 @@ static DisasJumpType op_cxlgb(DisasContext *s, DisasO= ps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cxlgb(o->out_128, cpu_env, o->in2, m34); + gen_helper_cxlgb(o->out_128, tcg_env, o->in2, m34); return DISAS_NEXT; } =20 @@ -1994,7 +1994,7 @@ static DisasJumpType op_cksm(DisasContext *s, DisasOp= s *o) TCGv_i128 pair =3D tcg_temp_new_i128(); TCGv_i64 len =3D tcg_temp_new_i64(); =20 - gen_helper_cksm(pair, cpu_env, o->in1, o->in2, regs[r2 + 1]); + gen_helper_cksm(pair, tcg_env, o->in1, o->in2, regs[r2 + 1]); set_cc_static(s); tcg_gen_extr_i128_i64(o->out, len, pair); =20 @@ -2022,7 +2022,7 @@ static DisasJumpType op_clc(DisasContext *s, DisasOps= *o) return DISAS_NEXT; default: vl =3D tcg_constant_i32(l); - gen_helper_clc(cc_op, cpu_env, vl, o->addr1, o->in2); + gen_helper_clc(cc_op, tcg_env, vl, o->addr1, o->in2); set_cc_static(s); return DISAS_NEXT; } @@ -2042,7 +2042,7 @@ static DisasJumpType op_clcl(DisasContext *s, DisasOp= s *o) =20 t1 =3D tcg_constant_i32(r1); t2 =3D tcg_constant_i32(r2); - gen_helper_clcl(cc_op, cpu_env, t1, t2); + gen_helper_clcl(cc_op, tcg_env, t1, t2); set_cc_static(s); return DISAS_NEXT; } @@ -2061,7 +2061,7 @@ static DisasJumpType op_clcle(DisasContext *s, DisasO= ps *o) =20 t1 =3D tcg_constant_i32(r1); t3 =3D tcg_constant_i32(r3); - gen_helper_clcle(cc_op, cpu_env, t1, o->in2, t3); + gen_helper_clcle(cc_op, tcg_env, t1, o->in2, t3); set_cc_static(s); return DISAS_NEXT; } @@ -2080,7 +2080,7 @@ static DisasJumpType op_clclu(DisasContext *s, DisasO= ps *o) =20 t1 =3D tcg_constant_i32(r1); t3 =3D tcg_constant_i32(r3); - gen_helper_clclu(cc_op, cpu_env, t1, o->in2, t3); + gen_helper_clclu(cc_op, tcg_env, t1, o->in2, t3); set_cc_static(s); return DISAS_NEXT; } @@ -2091,7 +2091,7 @@ static DisasJumpType op_clm(DisasContext *s, DisasOps= *o) TCGv_i32 t1 =3D tcg_temp_new_i32(); =20 tcg_gen_extrl_i64_i32(t1, o->in1); - gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2); + gen_helper_clm(cc_op, tcg_env, t1, m3, o->in2); set_cc_static(s); return DISAS_NEXT; } @@ -2100,7 +2100,7 @@ static DisasJumpType op_clst(DisasContext *s, DisasOp= s *o) { TCGv_i128 pair =3D tcg_temp_new_i128(); =20 - gen_helper_clst(pair, cpu_env, regs[0], o->in1, o->in2); + gen_helper_clst(pair, tcg_env, regs[0], o->in1, o->in2); tcg_gen_extr_i128_i64(o->in2, o->in1, pair); =20 set_cc_static(s); @@ -2169,9 +2169,9 @@ static DisasJumpType op_csst(DisasContext *s, DisasOp= s *o) TCGv_i32 t_r3 =3D tcg_constant_i32(r3); =20 if (tb_cflags(s->base.tb) & CF_PARALLEL) { - gen_helper_csst_parallel(cc_op, cpu_env, t_r3, o->addr1, o->in2); + gen_helper_csst_parallel(cc_op, tcg_env, t_r3, o->addr1, o->in2); } else { - gen_helper_csst(cc_op, cpu_env, t_r3, o->addr1, o->in2); + gen_helper_csst(cc_op, tcg_env, t_r3, o->addr1, o->in2); } =20 set_cc_static(s); @@ -2213,7 +2213,7 @@ static DisasJumpType op_csp(DisasContext *s, DisasOps= *o) tcg_gen_and_i64(cc, cc, o->in2); tcg_gen_brcondi_i64(TCG_COND_EQ, cc, 0, lab); =20 - gen_helper_purge(cpu_env); + gen_helper_purge(tcg_env); gen_set_label(lab); =20 return DISAS_NEXT; @@ -2271,22 +2271,22 @@ static DisasJumpType op_cuXX(DisasContext *s, Disas= Ops *o) =20 switch (s->insn->data) { case 12: - gen_helper_cu12(cc_op, cpu_env, tr1, tr2, chk); + gen_helper_cu12(cc_op, tcg_env, tr1, tr2, chk); break; case 14: - gen_helper_cu14(cc_op, cpu_env, tr1, tr2, chk); + gen_helper_cu14(cc_op, tcg_env, tr1, tr2, chk); break; case 21: - gen_helper_cu21(cc_op, cpu_env, tr1, tr2, chk); + gen_helper_cu21(cc_op, tcg_env, tr1, tr2, chk); break; case 24: - gen_helper_cu24(cc_op, cpu_env, tr1, tr2, chk); + gen_helper_cu24(cc_op, tcg_env, tr1, tr2, chk); break; case 41: - gen_helper_cu41(cc_op, cpu_env, tr1, tr2, chk); + gen_helper_cu41(cc_op, tcg_env, tr1, tr2, chk); break; case 42: - gen_helper_cu42(cc_op, cpu_env, tr1, tr2, chk); + gen_helper_cu42(cc_op, tcg_env, tr1, tr2, chk); break; default: g_assert_not_reached(); @@ -2303,21 +2303,21 @@ static DisasJumpType op_diag(DisasContext *s, Disas= Ops *o) TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); TCGv_i32 func_code =3D tcg_constant_i32(get_field(s, i2)); =20 - gen_helper_diag(cpu_env, r1, r3, func_code); + gen_helper_diag(tcg_env, r1, r3, func_code); return DISAS_NEXT; } #endif =20 static DisasJumpType op_divs32(DisasContext *s, DisasOps *o) { - gen_helper_divs32(o->out, cpu_env, o->in1, o->in2); + gen_helper_divs32(o->out, tcg_env, o->in1, o->in2); tcg_gen_extr32_i64(o->out2, o->out, o->out); return DISAS_NEXT; } =20 static DisasJumpType op_divu32(DisasContext *s, DisasOps *o) { - gen_helper_divu32(o->out, cpu_env, o->in1, o->in2); + gen_helper_divu32(o->out, tcg_env, o->in1, o->in2); tcg_gen_extr32_i64(o->out2, o->out, o->out); return DISAS_NEXT; } @@ -2326,7 +2326,7 @@ static DisasJumpType op_divs64(DisasContext *s, Disas= Ops *o) { TCGv_i128 t =3D tcg_temp_new_i128(); =20 - gen_helper_divs64(t, cpu_env, o->in1, o->in2); + gen_helper_divs64(t, tcg_env, o->in1, o->in2); tcg_gen_extr_i128_i64(o->out2, o->out, t); return DISAS_NEXT; } @@ -2335,33 +2335,33 @@ static DisasJumpType op_divu64(DisasContext *s, Dis= asOps *o) { TCGv_i128 t =3D tcg_temp_new_i128(); =20 - gen_helper_divu64(t, cpu_env, o->out, o->out2, o->in2); + gen_helper_divu64(t, tcg_env, o->out, o->out2, o->in2); tcg_gen_extr_i128_i64(o->out2, o->out, t); return DISAS_NEXT; } =20 static DisasJumpType op_deb(DisasContext *s, DisasOps *o) { - gen_helper_deb(o->out, cpu_env, o->in1, o->in2); + gen_helper_deb(o->out, tcg_env, o->in1, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_ddb(DisasContext *s, DisasOps *o) { - gen_helper_ddb(o->out, cpu_env, o->in1, o->in2); + gen_helper_ddb(o->out, tcg_env, o->in1, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_dxb(DisasContext *s, DisasOps *o) { - gen_helper_dxb(o->out_128, cpu_env, o->in1_128, o->in2_128); + gen_helper_dxb(o->out_128, tcg_env, o->in1_128, o->in2_128); return DISAS_NEXT; } =20 static DisasJumpType op_ear(DisasContext *s, DisasOps *o) { int r2 =3D get_field(s, r2); - tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, aregs[r2])); + tcg_gen_ld32u_i64(o->out, tcg_env, offsetof(CPUS390XState, aregs[r2])); return DISAS_NEXT; } =20 @@ -2374,7 +2374,7 @@ static DisasJumpType op_ecag(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_efpc(DisasContext *s, DisasOps *o) { - tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, fpc)); + tcg_gen_ld32u_i64(o->out, tcg_env, offsetof(CPUS390XState, fpc)); return DISAS_NEXT; } =20 @@ -2420,7 +2420,7 @@ static DisasJumpType op_ex(DisasContext *s, DisasOps = *o) } =20 ilen =3D tcg_constant_i32(s->ilen); - gen_helper_ex(cpu_env, ilen, v1, o->in2); + gen_helper_ex(tcg_env, ilen, v1, o->in2); =20 return DISAS_PC_CC_UPDATED; } @@ -2432,7 +2432,7 @@ static DisasJumpType op_fieb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_fieb(o->out, cpu_env, o->in2, m34); + gen_helper_fieb(o->out, tcg_env, o->in2, m34); return DISAS_NEXT; } =20 @@ -2443,7 +2443,7 @@ static DisasJumpType op_fidb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_fidb(o->out, cpu_env, o->in2, m34); + gen_helper_fidb(o->out, tcg_env, o->in2, m34); return DISAS_NEXT; } =20 @@ -2454,7 +2454,7 @@ static DisasJumpType op_fixb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_fixb(o->out_128, cpu_env, o->in2_128, m34); + gen_helper_fixb(o->out_128, tcg_env, o->in2_128, m34); return DISAS_NEXT; } =20 @@ -2575,7 +2575,7 @@ static DisasJumpType op_idte(DisasContext *s, DisasOp= s *o) } else { m4 =3D tcg_constant_i32(0); } - gen_helper_idte(cpu_env, o->in1, o->in2, m4); + gen_helper_idte(tcg_env, o->in1, o->in2, m4); return DISAS_NEXT; } =20 @@ -2588,13 +2588,13 @@ static DisasJumpType op_ipte(DisasContext *s, Disas= Ops *o) } else { m4 =3D tcg_constant_i32(0); } - gen_helper_ipte(cpu_env, o->in1, o->in2, m4); + gen_helper_ipte(tcg_env, o->in1, o->in2, m4); return DISAS_NEXT; } =20 static DisasJumpType op_iske(DisasContext *s, DisasOps *o) { - gen_helper_iske(o->out, cpu_env, o->in2); + gen_helper_iske(o->out, tcg_env, o->in2); return DISAS_NEXT; } #endif @@ -2648,28 +2648,28 @@ static DisasJumpType op_msa(DisasContext *s, DisasO= ps *o) t_r2 =3D tcg_constant_i32(r2); t_r3 =3D tcg_constant_i32(r3); type =3D tcg_constant_i32(s->insn->data); - gen_helper_msa(cc_op, cpu_env, t_r1, t_r2, t_r3, type); + gen_helper_msa(cc_op, tcg_env, t_r1, t_r2, t_r3, type); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_keb(DisasContext *s, DisasOps *o) { - gen_helper_keb(cc_op, cpu_env, o->in1, o->in2); + gen_helper_keb(cc_op, tcg_env, o->in1, o->in2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_kdb(DisasContext *s, DisasOps *o) { - gen_helper_kdb(cc_op, cpu_env, o->in1, o->in2); + gen_helper_kdb(cc_op, tcg_env, o->in1, o->in2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_kxb(DisasContext *s, DisasOps *o) { - gen_helper_kxb(cc_op, cpu_env, o->in1_128, o->in2_128); + gen_helper_kxb(cc_op, tcg_env, o->in1_128, o->in2_128); set_cc_static(s); return DISAS_NEXT; } @@ -2720,7 +2720,7 @@ static DisasJumpType op_lax(DisasContext *s, DisasOps= *o) =20 static DisasJumpType op_ldeb(DisasContext *s, DisasOps *o) { - gen_helper_ldeb(o->out, cpu_env, o->in2); + gen_helper_ldeb(o->out, tcg_env, o->in2); return DISAS_NEXT; } =20 @@ -2731,7 +2731,7 @@ static DisasJumpType op_ledb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_ledb(o->out, cpu_env, o->in2, m34); + gen_helper_ledb(o->out, tcg_env, o->in2, m34); return DISAS_NEXT; } =20 @@ -2742,7 +2742,7 @@ static DisasJumpType op_ldxb(DisasContext *s, DisasOp= s *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_ldxb(o->out, cpu_env, o->in2_128, m34); + gen_helper_ldxb(o->out, tcg_env, o->in2_128, m34); return DISAS_NEXT; } =20 @@ -2753,19 +2753,19 @@ static DisasJumpType op_lexb(DisasContext *s, Disas= Ops *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_lexb(o->out, cpu_env, o->in2_128, m34); + gen_helper_lexb(o->out, tcg_env, o->in2_128, m34); return DISAS_NEXT; } =20 static DisasJumpType op_lxdb(DisasContext *s, DisasOps *o) { - gen_helper_lxdb(o->out_128, cpu_env, o->in2); + gen_helper_lxdb(o->out_128, tcg_env, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_lxeb(DisasContext *s, DisasOps *o) { - gen_helper_lxeb(o->out_128, cpu_env, o->in2); + gen_helper_lxeb(o->out_128, tcg_env, o->in2); return DISAS_NEXT; } =20 @@ -2919,7 +2919,7 @@ static DisasJumpType op_lctl(DisasContext *s, DisasOp= s *o) TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); =20 - gen_helper_lctl(cpu_env, r1, o->in2, r3); + gen_helper_lctl(tcg_env, r1, o->in2, r3); /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */ s->exit_to_mainloop =3D true; return DISAS_TOO_MANY; @@ -2930,7 +2930,7 @@ static DisasJumpType op_lctlg(DisasContext *s, DisasO= ps *o) TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); =20 - gen_helper_lctlg(cpu_env, r1, o->in2, r3); + gen_helper_lctlg(tcg_env, r1, o->in2, r3); /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */ s->exit_to_mainloop =3D true; return DISAS_TOO_MANY; @@ -2938,14 +2938,14 @@ static DisasJumpType op_lctlg(DisasContext *s, Disa= sOps *o) =20 static DisasJumpType op_lra(DisasContext *s, DisasOps *o) { - gen_helper_lra(o->out, cpu_env, o->out, o->in2); + gen_helper_lra(o->out, tcg_env, o->out, o->in2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_lpp(DisasContext *s, DisasOps *o) { - tcg_gen_st_i64(o->in2, cpu_env, offsetof(CPUS390XState, pp)); + tcg_gen_st_i64(o->in2, tcg_env, offsetof(CPUS390XState, pp)); return DISAS_NEXT; } =20 @@ -2965,7 +2965,7 @@ static DisasJumpType op_lpsw(DisasContext *s, DisasOp= s *o) tcg_gen_andi_i64(addr, mask, PSW_MASK_SHORT_ADDR); tcg_gen_andi_i64(mask, mask, PSW_MASK_SHORT_CTRL); tcg_gen_xori_i64(mask, mask, PSW_MASK_SHORTPSW); - gen_helper_load_psw(cpu_env, mask, addr); + gen_helper_load_psw(tcg_env, mask, addr); return DISAS_NORETURN; } =20 @@ -2981,7 +2981,7 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasO= ps *o) MO_TEUQ | MO_ALIGN_8); tcg_gen_addi_i64(o->in2, o->in2, 8); tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_TEUQ); - gen_helper_load_psw(cpu_env, t1, t2); + gen_helper_load_psw(tcg_env, t1, t2); return DISAS_NORETURN; } #endif @@ -2991,7 +2991,7 @@ static DisasJumpType op_lam(DisasContext *s, DisasOps= *o) TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); =20 - gen_helper_lam(cpu_env, r1, o->in2, r3); + gen_helper_lam(tcg_env, r1, o->in2, r3); return DISAS_NEXT; } =20 @@ -3185,7 +3185,7 @@ static DisasJumpType op_mc(DisasContext *s, DisasOps = *o) } =20 #if !defined(CONFIG_USER_ONLY) - gen_helper_monitor_call(cpu_env, o->addr1, + gen_helper_monitor_call(tcg_env, o->addr1, tcg_constant_i32(monitor_class)); #endif /* Defaults to a NOP. */ @@ -3216,7 +3216,7 @@ static DisasJumpType op_mov2e(DisasContext *s, DisasO= ps *o) break; case PSW_ASC_SECONDARY >> FLAG_MASK_PSW_SHIFT: if (b2) { - tcg_gen_ld32u_i64(ar1, cpu_env, offsetof(CPUS390XState, aregs[= b2])); + tcg_gen_ld32u_i64(ar1, tcg_env, offsetof(CPUS390XState, aregs[= b2])); } else { tcg_gen_movi_i64(ar1, 0); } @@ -3226,7 +3226,7 @@ static DisasJumpType op_mov2e(DisasContext *s, DisasO= ps *o) break; } =20 - tcg_gen_st32_i64(ar1, cpu_env, offsetof(CPUS390XState, aregs[1])); + tcg_gen_st32_i64(ar1, tcg_env, offsetof(CPUS390XState, aregs[1])); return DISAS_NEXT; } =20 @@ -3243,13 +3243,13 @@ static DisasJumpType op_mvc(DisasContext *s, DisasO= ps *o) { TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); =20 - gen_helper_mvc(cpu_env, l, o->addr1, o->in2); + gen_helper_mvc(tcg_env, l, o->addr1, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_mvcrl(DisasContext *s, DisasOps *o) { - gen_helper_mvcrl(cpu_env, regs[0], o->addr1, o->in2); + gen_helper_mvcrl(tcg_env, regs[0], o->addr1, o->in2); return DISAS_NEXT; } =20 @@ -3257,7 +3257,7 @@ static DisasJumpType op_mvcin(DisasContext *s, DisasO= ps *o) { TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); =20 - gen_helper_mvcin(cpu_env, l, o->addr1, o->in2); + gen_helper_mvcin(tcg_env, l, o->addr1, o->in2); return DISAS_NEXT; } =20 @@ -3275,7 +3275,7 @@ static DisasJumpType op_mvcl(DisasContext *s, DisasOp= s *o) =20 t1 =3D tcg_constant_i32(r1); t2 =3D tcg_constant_i32(r2); - gen_helper_mvcl(cc_op, cpu_env, t1, t2); + gen_helper_mvcl(cc_op, tcg_env, t1, t2); set_cc_static(s); return DISAS_NEXT; } @@ -3294,7 +3294,7 @@ static DisasJumpType op_mvcle(DisasContext *s, DisasO= ps *o) =20 t1 =3D tcg_constant_i32(r1); t3 =3D tcg_constant_i32(r3); - gen_helper_mvcle(cc_op, cpu_env, t1, o->in2, t3); + gen_helper_mvcle(cc_op, tcg_env, t1, o->in2, t3); set_cc_static(s); return DISAS_NEXT; } @@ -3313,7 +3313,7 @@ static DisasJumpType op_mvclu(DisasContext *s, DisasO= ps *o) =20 t1 =3D tcg_constant_i32(r1); t3 =3D tcg_constant_i32(r3); - gen_helper_mvclu(cc_op, cpu_env, t1, o->in2, t3); + gen_helper_mvclu(cc_op, tcg_env, t1, o->in2, t3); set_cc_static(s); return DISAS_NEXT; } @@ -3321,7 +3321,7 @@ static DisasJumpType op_mvclu(DisasContext *s, DisasO= ps *o) static DisasJumpType op_mvcos(DisasContext *s, DisasOps *o) { int r3 =3D get_field(s, r3); - gen_helper_mvcos(cc_op, cpu_env, o->addr1, o->in2, regs[r3]); + gen_helper_mvcos(cc_op, tcg_env, o->addr1, o->in2, regs[r3]); set_cc_static(s); return DISAS_NEXT; } @@ -3331,7 +3331,7 @@ static DisasJumpType op_mvcp(DisasContext *s, DisasOp= s *o) { int r1 =3D get_field(s, l1); int r3 =3D get_field(s, r3); - gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2, regs[r3]); + gen_helper_mvcp(cc_op, tcg_env, regs[r1], o->addr1, o->in2, regs[r3]); set_cc_static(s); return DISAS_NEXT; } @@ -3340,7 +3340,7 @@ static DisasJumpType op_mvcs(DisasContext *s, DisasOp= s *o) { int r1 =3D get_field(s, l1); int r3 =3D get_field(s, r3); - gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2, regs[r3]); + gen_helper_mvcs(cc_op, tcg_env, regs[r1], o->addr1, o->in2, regs[r3]); set_cc_static(s); return DISAS_NEXT; } @@ -3350,7 +3350,7 @@ static DisasJumpType op_mvn(DisasContext *s, DisasOps= *o) { TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); =20 - gen_helper_mvn(cpu_env, l, o->addr1, o->in2); + gen_helper_mvn(tcg_env, l, o->addr1, o->in2); return DISAS_NEXT; } =20 @@ -3358,7 +3358,7 @@ static DisasJumpType op_mvo(DisasContext *s, DisasOps= *o) { TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); =20 - gen_helper_mvo(cpu_env, l, o->addr1, o->in2); + gen_helper_mvo(tcg_env, l, o->addr1, o->in2); return DISAS_NEXT; } =20 @@ -3367,7 +3367,7 @@ static DisasJumpType op_mvpg(DisasContext *s, DisasOp= s *o) TCGv_i32 t1 =3D tcg_constant_i32(get_field(s, r1)); TCGv_i32 t2 =3D tcg_constant_i32(get_field(s, r2)); =20 - gen_helper_mvpg(cc_op, cpu_env, regs[0], t1, t2); + gen_helper_mvpg(cc_op, tcg_env, regs[0], t1, t2); set_cc_static(s); return DISAS_NEXT; } @@ -3377,7 +3377,7 @@ static DisasJumpType op_mvst(DisasContext *s, DisasOp= s *o) TCGv_i32 t1 =3D tcg_constant_i32(get_field(s, r1)); TCGv_i32 t2 =3D tcg_constant_i32(get_field(s, r2)); =20 - gen_helper_mvst(cc_op, cpu_env, t1, t2); + gen_helper_mvst(cc_op, tcg_env, t1, t2); set_cc_static(s); return DISAS_NEXT; } @@ -3386,7 +3386,7 @@ static DisasJumpType op_mvz(DisasContext *s, DisasOps= *o) { TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); =20 - gen_helper_mvz(cpu_env, l, o->addr1, o->in2); + gen_helper_mvz(tcg_env, l, o->addr1, o->in2); return DISAS_NEXT; } =20 @@ -3410,59 +3410,59 @@ static DisasJumpType op_muls128(DisasContext *s, Di= sasOps *o) =20 static DisasJumpType op_meeb(DisasContext *s, DisasOps *o) { - gen_helper_meeb(o->out, cpu_env, o->in1, o->in2); + gen_helper_meeb(o->out, tcg_env, o->in1, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_mdeb(DisasContext *s, DisasOps *o) { - gen_helper_mdeb(o->out, cpu_env, o->in1, o->in2); + gen_helper_mdeb(o->out, tcg_env, o->in1, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_mdb(DisasContext *s, DisasOps *o) { - gen_helper_mdb(o->out, cpu_env, o->in1, o->in2); + gen_helper_mdb(o->out, tcg_env, o->in1, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_mxb(DisasContext *s, DisasOps *o) { - gen_helper_mxb(o->out_128, cpu_env, o->in1_128, o->in2_128); + gen_helper_mxb(o->out_128, tcg_env, o->in1_128, o->in2_128); return DISAS_NEXT; } =20 static DisasJumpType op_mxdb(DisasContext *s, DisasOps *o) { - gen_helper_mxdb(o->out_128, cpu_env, o->in1, o->in2); + gen_helper_mxdb(o->out_128, tcg_env, o->in1, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_maeb(DisasContext *s, DisasOps *o) { TCGv_i64 r3 =3D load_freg32_i64(get_field(s, r3)); - gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3); + gen_helper_maeb(o->out, tcg_env, o->in1, o->in2, r3); return DISAS_NEXT; } =20 static DisasJumpType op_madb(DisasContext *s, DisasOps *o) { TCGv_i64 r3 =3D load_freg(get_field(s, r3)); - gen_helper_madb(o->out, cpu_env, o->in1, o->in2, r3); + gen_helper_madb(o->out, tcg_env, o->in1, o->in2, r3); return DISAS_NEXT; } =20 static DisasJumpType op_mseb(DisasContext *s, DisasOps *o) { TCGv_i64 r3 =3D load_freg32_i64(get_field(s, r3)); - gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3); + gen_helper_mseb(o->out, tcg_env, o->in1, o->in2, r3); return DISAS_NEXT; } =20 static DisasJumpType op_msdb(DisasContext *s, DisasOps *o) { TCGv_i64 r3 =3D load_freg(get_field(s, r3)); - gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, r3); + gen_helper_msdb(o->out, tcg_env, o->in1, o->in2, r3); return DISAS_NEXT; } =20 @@ -3499,7 +3499,7 @@ static DisasJumpType op_nc(DisasContext *s, DisasOps = *o) { TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); =20 - gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2); + gen_helper_nc(cc_op, tcg_env, l, o->addr1, o->in2); set_cc_static(s); return DISAS_NEXT; } @@ -3533,7 +3533,7 @@ static DisasJumpType op_oc(DisasContext *s, DisasOps = *o) { TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); =20 - gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2); + gen_helper_oc(cc_op, tcg_env, l, o->addr1, o->in2); set_cc_static(s); return DISAS_NEXT; } @@ -3585,7 +3585,7 @@ static DisasJumpType op_pack(DisasContext *s, DisasOp= s *o) { TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); =20 - gen_helper_pack(cpu_env, l, o->addr1, o->in2); + gen_helper_pack(tcg_env, l, o->addr1, o->in2); return DISAS_NEXT; } =20 @@ -3600,7 +3600,7 @@ static DisasJumpType op_pka(DisasContext *s, DisasOps= *o) return DISAS_NORETURN; } l =3D tcg_constant_i32(l2); - gen_helper_pka(cpu_env, o->addr1, o->in2, l); + gen_helper_pka(tcg_env, o->addr1, o->in2, l); return DISAS_NEXT; } =20 @@ -3615,7 +3615,7 @@ static DisasJumpType op_pku(DisasContext *s, DisasOps= *o) return DISAS_NORETURN; } l =3D tcg_constant_i32(l2); - gen_helper_pku(cpu_env, o->addr1, o->in2, l); + gen_helper_pku(tcg_env, o->addr1, o->in2, l); return DISAS_NEXT; } =20 @@ -3634,7 +3634,7 @@ static DisasJumpType op_popcnt(DisasContext *s, Disas= Ops *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_ptlb(DisasContext *s, DisasOps *o) { - gen_helper_ptlb(cpu_env); + gen_helper_ptlb(tcg_env); return DISAS_NEXT; } #endif @@ -3822,14 +3822,14 @@ static DisasJumpType op_rll64(DisasContext *s, Disa= sOps *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_rrbe(DisasContext *s, DisasOps *o) { - gen_helper_rrbe(cc_op, cpu_env, o->in2); + gen_helper_rrbe(cc_op, tcg_env, o->in2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_sacf(DisasContext *s, DisasOps *o) { - gen_helper_sacf(cpu_env, o->in2); + gen_helper_sacf(tcg_env, o->in2); /* Addressing mode has changed, so end the block. */ return DISAS_TOO_MANY; } @@ -3872,50 +3872,50 @@ static DisasJumpType op_sam(DisasContext *s, DisasO= ps *o) static DisasJumpType op_sar(DisasContext *s, DisasOps *o) { int r1 =3D get_field(s, r1); - tcg_gen_st32_i64(o->in2, cpu_env, offsetof(CPUS390XState, aregs[r1])); + tcg_gen_st32_i64(o->in2, tcg_env, offsetof(CPUS390XState, aregs[r1])); return DISAS_NEXT; } =20 static DisasJumpType op_seb(DisasContext *s, DisasOps *o) { - gen_helper_seb(o->out, cpu_env, o->in1, o->in2); + gen_helper_seb(o->out, tcg_env, o->in1, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_sdb(DisasContext *s, DisasOps *o) { - gen_helper_sdb(o->out, cpu_env, o->in1, o->in2); + gen_helper_sdb(o->out, tcg_env, o->in1, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_sxb(DisasContext *s, DisasOps *o) { - gen_helper_sxb(o->out_128, cpu_env, o->in1_128, o->in2_128); + gen_helper_sxb(o->out_128, tcg_env, o->in1_128, o->in2_128); return DISAS_NEXT; } =20 static DisasJumpType op_sqeb(DisasContext *s, DisasOps *o) { - gen_helper_sqeb(o->out, cpu_env, o->in2); + gen_helper_sqeb(o->out, tcg_env, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_sqdb(DisasContext *s, DisasOps *o) { - gen_helper_sqdb(o->out, cpu_env, o->in2); + gen_helper_sqdb(o->out, tcg_env, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_sqxb(DisasContext *s, DisasOps *o) { - gen_helper_sqxb(o->out_128, cpu_env, o->in2_128); + gen_helper_sqxb(o->out_128, tcg_env, o->in2_128); return DISAS_NEXT; } =20 #ifndef CONFIG_USER_ONLY static DisasJumpType op_servc(DisasContext *s, DisasOps *o) { - gen_helper_servc(cc_op, cpu_env, o->in2, o->in1); + gen_helper_servc(cc_op, tcg_env, o->in2, o->in1); set_cc_static(s); return DISAS_NEXT; } @@ -3925,7 +3925,7 @@ static DisasJumpType op_sigp(DisasContext *s, DisasOp= s *o) TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); =20 - gen_helper_sigp(cc_op, cpu_env, o->in2, r1, r3); + gen_helper_sigp(cc_op, tcg_env, o->in2, r1, r3); set_cc_static(s); return DISAS_NEXT; } @@ -4013,13 +4013,13 @@ static DisasJumpType op_srl(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_sfpc(DisasContext *s, DisasOps *o) { - gen_helper_sfpc(cpu_env, o->in2); + gen_helper_sfpc(tcg_env, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_sfas(DisasContext *s, DisasOps *o) { - gen_helper_sfas(cpu_env, o->in2); + gen_helper_sfas(tcg_env, o->in2); return DISAS_NEXT; } =20 @@ -4027,7 +4027,7 @@ static DisasJumpType op_srnm(DisasContext *s, DisasOp= s *o) { /* Bits other than 62 and 63 are ignored. Bit 29 is set to zero. */ tcg_gen_andi_i64(o->addr1, o->addr1, 0x3ull); - gen_helper_srnm(cpu_env, o->addr1); + gen_helper_srnm(tcg_env, o->addr1); return DISAS_NEXT; } =20 @@ -4035,7 +4035,7 @@ static DisasJumpType op_srnmb(DisasContext *s, DisasO= ps *o) { /* Bits 0-55 are are ignored. */ tcg_gen_andi_i64(o->addr1, o->addr1, 0xffull); - gen_helper_srnm(cpu_env, o->addr1); + gen_helper_srnm(tcg_env, o->addr1); return DISAS_NEXT; } =20 @@ -4047,9 +4047,9 @@ static DisasJumpType op_srnmt(DisasContext *s, DisasO= ps *o) tcg_gen_andi_i64(o->addr1, o->addr1, 0x7ull); =20 /* No need to call a helper, we don't implement dfp */ - tcg_gen_ld32u_i64(tmp, cpu_env, offsetof(CPUS390XState, fpc)); + tcg_gen_ld32u_i64(tmp, tcg_env, offsetof(CPUS390XState, fpc)); tcg_gen_deposit_i64(tmp, tmp, o->addr1, 4, 3); - tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUS390XState, fpc)); + tcg_gen_st32_i64(tmp, tcg_env, offsetof(CPUS390XState, fpc)); return DISAS_NEXT; } =20 @@ -4085,7 +4085,7 @@ static DisasJumpType op_ectg(DisasContext *s, DisasOp= s *o) tcg_gen_qemu_ld_i64(regs[r3], o->addr1, get_mem_index(s), MO_TEUQ); =20 /* subtract CPU timer from first operand and store in GR0 */ - gen_helper_stpt(tmp, cpu_env); + gen_helper_stpt(tmp, tcg_env); tcg_gen_sub_i64(regs[0], o->in1, tmp); =20 /* store second operand in GR1 */ @@ -4103,7 +4103,7 @@ static DisasJumpType op_spka(DisasContext *s, DisasOp= s *o) =20 static DisasJumpType op_sske(DisasContext *s, DisasOps *o) { - gen_helper_sske(cpu_env, o->in1, o->in2); + gen_helper_sske(tcg_env, o->in1, o->in2); return DISAS_NEXT; } =20 @@ -4131,14 +4131,14 @@ static DisasJumpType op_ssm(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_stap(DisasContext *s, DisasOps *o) { - tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, core_id)); + tcg_gen_ld32u_i64(o->out, tcg_env, offsetof(CPUS390XState, core_id)); return DISAS_NEXT; } #endif =20 static DisasJumpType op_stck(DisasContext *s, DisasOps *o) { - gen_helper_stck(o->out, cpu_env); + gen_helper_stck(o->out, tcg_env); /* ??? We don't implement clock states. */ gen_op_movi_cc(s, 0); return DISAS_NEXT; @@ -4149,9 +4149,9 @@ static DisasJumpType op_stcke(DisasContext *s, DisasO= ps *o) TCGv_i64 c1 =3D tcg_temp_new_i64(); TCGv_i64 c2 =3D tcg_temp_new_i64(); TCGv_i64 todpr =3D tcg_temp_new_i64(); - gen_helper_stck(c1, cpu_env); + gen_helper_stck(c1, tcg_env); /* 16 bit value store in an uint32_t (only valid bits set) */ - tcg_gen_ld32u_i64(todpr, cpu_env, offsetof(CPUS390XState, todpr)); + tcg_gen_ld32u_i64(todpr, tcg_env, offsetof(CPUS390XState, todpr)); /* Shift the 64-bit value into its place as a zero-extended 104-bit value. Note that "bit positions 64-103 are always non-zero so that they compare differently to STCK"; we set @@ -4171,26 +4171,26 @@ static DisasJumpType op_stcke(DisasContext *s, Disa= sOps *o) #ifndef CONFIG_USER_ONLY static DisasJumpType op_sck(DisasContext *s, DisasOps *o) { - gen_helper_sck(cc_op, cpu_env, o->in2); + gen_helper_sck(cc_op, tcg_env, o->in2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_sckc(DisasContext *s, DisasOps *o) { - gen_helper_sckc(cpu_env, o->in2); + gen_helper_sckc(tcg_env, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_sckpf(DisasContext *s, DisasOps *o) { - gen_helper_sckpf(cpu_env, regs[0]); + gen_helper_sckpf(tcg_env, regs[0]); return DISAS_NEXT; } =20 static DisasJumpType op_stckc(DisasContext *s, DisasOps *o) { - gen_helper_stckc(o->out, cpu_env); + gen_helper_stckc(o->out, tcg_env); return DISAS_NEXT; } =20 @@ -4199,7 +4199,7 @@ static DisasJumpType op_stctg(DisasContext *s, DisasO= ps *o) TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); =20 - gen_helper_stctg(cpu_env, r1, o->in2, r3); + gen_helper_stctg(tcg_env, r1, o->in2, r3); return DISAS_NEXT; } =20 @@ -4208,98 +4208,98 @@ static DisasJumpType op_stctl(DisasContext *s, Disa= sOps *o) TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); =20 - gen_helper_stctl(cpu_env, r1, o->in2, r3); + gen_helper_stctl(tcg_env, r1, o->in2, r3); return DISAS_NEXT; } =20 static DisasJumpType op_stidp(DisasContext *s, DisasOps *o) { - tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, cpuid)); + tcg_gen_ld_i64(o->out, tcg_env, offsetof(CPUS390XState, cpuid)); return DISAS_NEXT; } =20 static DisasJumpType op_spt(DisasContext *s, DisasOps *o) { - gen_helper_spt(cpu_env, o->in2); + gen_helper_spt(tcg_env, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_stfl(DisasContext *s, DisasOps *o) { - gen_helper_stfl(cpu_env); + gen_helper_stfl(tcg_env); return DISAS_NEXT; } =20 static DisasJumpType op_stpt(DisasContext *s, DisasOps *o) { - gen_helper_stpt(o->out, cpu_env); + gen_helper_stpt(o->out, tcg_env); return DISAS_NEXT; } =20 static DisasJumpType op_stsi(DisasContext *s, DisasOps *o) { - gen_helper_stsi(cc_op, cpu_env, o->in2, regs[0], regs[1]); + gen_helper_stsi(cc_op, tcg_env, o->in2, regs[0], regs[1]); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_spx(DisasContext *s, DisasOps *o) { - gen_helper_spx(cpu_env, o->in2); + gen_helper_spx(tcg_env, o->in2); return DISAS_NEXT; } =20 static DisasJumpType op_xsch(DisasContext *s, DisasOps *o) { - gen_helper_xsch(cpu_env, regs[1]); + gen_helper_xsch(tcg_env, regs[1]); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_csch(DisasContext *s, DisasOps *o) { - gen_helper_csch(cpu_env, regs[1]); + gen_helper_csch(tcg_env, regs[1]); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_hsch(DisasContext *s, DisasOps *o) { - gen_helper_hsch(cpu_env, regs[1]); + gen_helper_hsch(tcg_env, regs[1]); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_msch(DisasContext *s, DisasOps *o) { - gen_helper_msch(cpu_env, regs[1], o->in2); + gen_helper_msch(tcg_env, regs[1], o->in2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_rchp(DisasContext *s, DisasOps *o) { - gen_helper_rchp(cpu_env, regs[1]); + gen_helper_rchp(tcg_env, regs[1]); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_rsch(DisasContext *s, DisasOps *o) { - gen_helper_rsch(cpu_env, regs[1]); + gen_helper_rsch(tcg_env, regs[1]); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_sal(DisasContext *s, DisasOps *o) { - gen_helper_sal(cpu_env, regs[1]); + gen_helper_sal(tcg_env, regs[1]); return DISAS_NEXT; } =20 static DisasJumpType op_schm(DisasContext *s, DisasOps *o) { - gen_helper_schm(cpu_env, regs[1], regs[2], o->in2); + gen_helper_schm(tcg_env, regs[1], regs[2], o->in2); return DISAS_NEXT; } =20 @@ -4318,49 +4318,49 @@ static DisasJumpType op_stcps(DisasContext *s, Disa= sOps *o) =20 static DisasJumpType op_ssch(DisasContext *s, DisasOps *o) { - gen_helper_ssch(cpu_env, regs[1], o->in2); + gen_helper_ssch(tcg_env, regs[1], o->in2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_stsch(DisasContext *s, DisasOps *o) { - gen_helper_stsch(cpu_env, regs[1], o->in2); + gen_helper_stsch(tcg_env, regs[1], o->in2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_stcrw(DisasContext *s, DisasOps *o) { - gen_helper_stcrw(cpu_env, o->in2); + gen_helper_stcrw(tcg_env, o->in2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_tpi(DisasContext *s, DisasOps *o) { - gen_helper_tpi(cc_op, cpu_env, o->addr1); + gen_helper_tpi(cc_op, tcg_env, o->addr1); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_tsch(DisasContext *s, DisasOps *o) { - gen_helper_tsch(cpu_env, regs[1], o->in2); + gen_helper_tsch(tcg_env, regs[1], o->in2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_chsc(DisasContext *s, DisasOps *o) { - gen_helper_chsc(cpu_env, o->in2); + gen_helper_chsc(tcg_env, o->in2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_stpx(DisasContext *s, DisasOps *o) { - tcg_gen_ld_i64(o->out, cpu_env, offsetof(CPUS390XState, psa)); + tcg_gen_ld_i64(o->out, tcg_env, offsetof(CPUS390XState, psa)); tcg_gen_andi_i64(o->out, o->out, 0x7fffe000); return DISAS_NEXT; } @@ -4397,7 +4397,7 @@ static DisasJumpType op_stura(DisasContext *s, DisasO= ps *o) =20 if (s->base.tb->flags & FLAG_MASK_PER) { update_psw_addr(s); - gen_helper_per_store_real(cpu_env); + gen_helper_per_store_real(tcg_env); } return DISAS_NEXT; } @@ -4405,7 +4405,7 @@ static DisasJumpType op_stura(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_stfle(DisasContext *s, DisasOps *o) { - gen_helper_stfle(cc_op, cpu_env, o->in2); + gen_helper_stfle(cc_op, tcg_env, o->in2); set_cc_static(s); return DISAS_NEXT; } @@ -4441,7 +4441,7 @@ static DisasJumpType op_stam(DisasContext *s, DisasOp= s *o) TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); =20 - gen_helper_stam(cpu_env, r1, o->in2, r3); + gen_helper_stam(tcg_env, r1, o->in2, r3); return DISAS_NEXT; } =20 @@ -4548,7 +4548,7 @@ static DisasJumpType op_srst(DisasContext *s, DisasOp= s *o) TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); TCGv_i32 r2 =3D tcg_constant_i32(get_field(s, r2)); =20 - gen_helper_srst(cpu_env, r1, r2); + gen_helper_srst(tcg_env, r1, r2); set_cc_static(s); return DISAS_NEXT; } @@ -4558,7 +4558,7 @@ static DisasJumpType op_srstu(DisasContext *s, DisasO= ps *o) TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); TCGv_i32 r2 =3D tcg_constant_i32(get_field(s, r2)); =20 - gen_helper_srstu(cpu_env, r1, r2); + gen_helper_srstu(tcg_env, r1, r2); set_cc_static(s); return DISAS_NEXT; } @@ -4631,10 +4631,10 @@ static DisasJumpType op_svc(DisasContext *s, DisasO= ps *o) update_cc_op(s); =20 t =3D tcg_constant_i32(get_field(s, i1) & 0xff); - tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code)); + tcg_gen_st_i32(t, tcg_env, offsetof(CPUS390XState, int_svc_code)); =20 t =3D tcg_constant_i32(s->ilen); - tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_ilen)); + tcg_gen_st_i32(t, tcg_env, offsetof(CPUS390XState, int_svc_ilen)); =20 gen_exception(EXCP_SVC); return DISAS_NORETURN; @@ -4652,21 +4652,21 @@ static DisasJumpType op_tam(DisasContext *s, DisasO= ps *o) =20 static DisasJumpType op_tceb(DisasContext *s, DisasOps *o) { - gen_helper_tceb(cc_op, cpu_env, o->in1, o->in2); + gen_helper_tceb(cc_op, tcg_env, o->in1, o->in2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_tcdb(DisasContext *s, DisasOps *o) { - gen_helper_tcdb(cc_op, cpu_env, o->in1, o->in2); + gen_helper_tcdb(cc_op, tcg_env, o->in1, o->in2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_tcxb(DisasContext *s, DisasOps *o) { - gen_helper_tcxb(cc_op, cpu_env, o->in1_128, o->in2); + gen_helper_tcxb(cc_op, tcg_env, o->in1_128, o->in2); set_cc_static(s); return DISAS_NEXT; } @@ -4675,14 +4675,14 @@ static DisasJumpType op_tcxb(DisasContext *s, Disas= Ops *o) =20 static DisasJumpType op_testblock(DisasContext *s, DisasOps *o) { - gen_helper_testblock(cc_op, cpu_env, o->in2); + gen_helper_testblock(cc_op, tcg_env, o->in2); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_tprot(DisasContext *s, DisasOps *o) { - gen_helper_tprot(cc_op, cpu_env, o->addr1, o->in2); + gen_helper_tprot(cc_op, tcg_env, o->addr1, o->in2); set_cc_static(s); return DISAS_NEXT; } @@ -4693,7 +4693,7 @@ static DisasJumpType op_tp(DisasContext *s, DisasOps = *o) { TCGv_i32 l1 =3D tcg_constant_i32(get_field(s, l1) + 1); =20 - gen_helper_tp(cc_op, cpu_env, o->addr1, l1); + gen_helper_tp(cc_op, tcg_env, o->addr1, l1); set_cc_static(s); return DISAS_NEXT; } @@ -4702,7 +4702,7 @@ static DisasJumpType op_tr(DisasContext *s, DisasOps = *o) { TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); =20 - gen_helper_tr(cpu_env, l, o->addr1, o->in2); + gen_helper_tr(tcg_env, l, o->addr1, o->in2); set_cc_static(s); return DISAS_NEXT; } @@ -4711,7 +4711,7 @@ static DisasJumpType op_tre(DisasContext *s, DisasOps= *o) { TCGv_i128 pair =3D tcg_temp_new_i128(); =20 - gen_helper_tre(pair, cpu_env, o->out, o->out2, o->in2); + gen_helper_tre(pair, tcg_env, o->out, o->out2, o->in2); tcg_gen_extr_i128_i64(o->out2, o->out, pair); set_cc_static(s); return DISAS_NEXT; @@ -4721,7 +4721,7 @@ static DisasJumpType op_trt(DisasContext *s, DisasOps= *o) { TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); =20 - gen_helper_trt(cc_op, cpu_env, l, o->addr1, o->in2); + gen_helper_trt(cc_op, tcg_env, l, o->addr1, o->in2); set_cc_static(s); return DISAS_NEXT; } @@ -4730,7 +4730,7 @@ static DisasJumpType op_trtr(DisasContext *s, DisasOp= s *o) { TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); =20 - gen_helper_trtr(cc_op, cpu_env, l, o->addr1, o->in2); + gen_helper_trtr(cc_op, tcg_env, l, o->addr1, o->in2); set_cc_static(s); return DISAS_NEXT; } @@ -4756,7 +4756,7 @@ static DisasJumpType op_trXX(DisasContext *s, DisasOp= s *o) tcg_gen_ext16u_i32(tst, tst); } } - gen_helper_trXX(cc_op, cpu_env, r1, r2, tst, sizes); + gen_helper_trXX(cc_op, tcg_env, r1, r2, tst, sizes); =20 set_cc_static(s); return DISAS_NEXT; @@ -4776,7 +4776,7 @@ static DisasJumpType op_unpk(DisasContext *s, DisasOp= s *o) { TCGv_i32 l =3D tcg_constant_i32(get_field(s, l1)); =20 - gen_helper_unpk(cpu_env, l, o->addr1, o->in2); + gen_helper_unpk(tcg_env, l, o->addr1, o->in2); return DISAS_NEXT; } =20 @@ -4791,7 +4791,7 @@ static DisasJumpType op_unpka(DisasContext *s, DisasO= ps *o) return DISAS_NORETURN; } l =3D tcg_constant_i32(l1); - gen_helper_unpka(cc_op, cpu_env, o->addr1, l, o->in2); + gen_helper_unpka(cc_op, tcg_env, o->addr1, l, o->in2); set_cc_static(s); return DISAS_NEXT; } @@ -4807,7 +4807,7 @@ static DisasJumpType op_unpku(DisasContext *s, DisasO= ps *o) return DISAS_NORETURN; } l =3D tcg_constant_i32(l1); - gen_helper_unpku(cc_op, cpu_env, o->addr1, l, o->in2); + gen_helper_unpku(cc_op, tcg_env, o->addr1, l, o->in2); set_cc_static(s); return DISAS_NEXT; } @@ -4860,7 +4860,7 @@ static DisasJumpType op_xc(DisasContext *s, DisasOps = *o) /* But in general we'll defer to a helper. */ o->in2 =3D get_address(s, 0, b2, d2); t32 =3D tcg_constant_i32(l); - gen_helper_xc(cc_op, cpu_env, t32, o->addr1, o->in2); + gen_helper_xc(cc_op, tcg_env, t32, o->addr1, o->in2); set_cc_static(s); return DISAS_NEXT; } @@ -4926,7 +4926,7 @@ static DisasJumpType op_clp(DisasContext *s, DisasOps= *o) { TCGv_i32 r2 =3D tcg_constant_i32(get_field(s, r2)); =20 - gen_helper_clp(cpu_env, r2); + gen_helper_clp(tcg_env, r2); set_cc_static(s); return DISAS_NEXT; } @@ -4936,7 +4936,7 @@ static DisasJumpType op_pcilg(DisasContext *s, DisasO= ps *o) TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); TCGv_i32 r2 =3D tcg_constant_i32(get_field(s, r2)); =20 - gen_helper_pcilg(cpu_env, r1, r2); + gen_helper_pcilg(tcg_env, r1, r2); set_cc_static(s); return DISAS_NEXT; } @@ -4946,7 +4946,7 @@ static DisasJumpType op_pcistg(DisasContext *s, Disas= Ops *o) TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); TCGv_i32 r2 =3D tcg_constant_i32(get_field(s, r2)); =20 - gen_helper_pcistg(cpu_env, r1, r2); + gen_helper_pcistg(tcg_env, r1, r2); set_cc_static(s); return DISAS_NEXT; } @@ -4956,14 +4956,14 @@ static DisasJumpType op_stpcifc(DisasContext *s, Di= sasOps *o) TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); TCGv_i32 ar =3D tcg_constant_i32(get_field(s, b2)); =20 - gen_helper_stpcifc(cpu_env, r1, o->addr1, ar); + gen_helper_stpcifc(tcg_env, r1, o->addr1, ar); set_cc_static(s); return DISAS_NEXT; } =20 static DisasJumpType op_sic(DisasContext *s, DisasOps *o) { - gen_helper_sic(cpu_env, o->in1, o->in2); + gen_helper_sic(tcg_env, o->in1, o->in2); return DISAS_NEXT; } =20 @@ -4972,7 +4972,7 @@ static DisasJumpType op_rpcit(DisasContext *s, DisasO= ps *o) TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); TCGv_i32 r2 =3D tcg_constant_i32(get_field(s, r2)); =20 - gen_helper_rpcit(cpu_env, r1, r2); + gen_helper_rpcit(tcg_env, r1, r2); set_cc_static(s); return DISAS_NEXT; } @@ -4983,7 +4983,7 @@ static DisasJumpType op_pcistb(DisasContext *s, Disas= Ops *o) TCGv_i32 r3 =3D tcg_constant_i32(get_field(s, r3)); TCGv_i32 ar =3D tcg_constant_i32(get_field(s, b2)); =20 - gen_helper_pcistb(cpu_env, r1, r3, o->addr1, ar); + gen_helper_pcistb(tcg_env, r1, r3, o->addr1, ar); set_cc_static(s); return DISAS_NEXT; } @@ -4993,7 +4993,7 @@ static DisasJumpType op_mpcifc(DisasContext *s, Disas= Ops *o) TCGv_i32 r1 =3D tcg_constant_i32(get_field(s, r1)); TCGv_i32 ar =3D tcg_constant_i32(get_field(s, b2)); =20 - gen_helper_mpcifc(cpu_env, r1, o->addr1, ar); + gen_helper_mpcifc(tcg_env, r1, o->addr1, ar); set_cc_static(s); return DISAS_NEXT; } @@ -6176,7 +6176,7 @@ static const DisasInsn *extract_insn(CPUS390XState *e= nv, DisasContext *s) =20 if (unlikely(s->ex_value)) { /* Drop the EX data now, so that it's clear on exception paths. */ - tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, + tcg_gen_st_i64(tcg_constant_i64(0), tcg_env, offsetof(CPUS390XState, ex_value)); =20 /* Extract the values saved by EXECUTE. */ @@ -6310,7 +6310,7 @@ static DisasJumpType translate_one(CPUS390XState *env= , DisasContext *s) #ifndef CONFIG_USER_ONLY if (s->base.tb->flags & FLAG_MASK_PER) { TCGv_i64 addr =3D tcg_constant_i64(s->base.pc_next); - gen_helper_per_ifetch(cpu_env, addr); + gen_helper_per_ifetch(tcg_env, addr); } #endif =20 @@ -6415,7 +6415,7 @@ static DisasJumpType translate_one(CPUS390XState *env= , DisasContext *s) } =20 /* Call the helper to check for a possible PER exception. */ - gen_helper_per_check_exception(cpu_env); + gen_helper_per_check_exception(tcg_env); } #endif =20 diff --git a/target/sh4/translate.c b/target/sh4/translate.c index c1e590feb3..30e3ea509b 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -96,63 +96,63 @@ void sh4_translate_init(void) }; =20 for (i =3D 0; i < 24; i++) { - cpu_gregs[i] =3D tcg_global_mem_new_i32(cpu_env, + cpu_gregs[i] =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, gregs[= i]), gregnames[i]); } memcpy(cpu_gregs + 24, cpu_gregs + 8, 8 * sizeof(TCGv)); =20 - cpu_pc =3D tcg_global_mem_new_i32(cpu_env, + cpu_pc =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, pc), "PC"); - cpu_sr =3D tcg_global_mem_new_i32(cpu_env, + cpu_sr =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, sr), "SR"); - cpu_sr_m =3D tcg_global_mem_new_i32(cpu_env, + cpu_sr_m =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, sr_m), "SR_M"); - cpu_sr_q =3D tcg_global_mem_new_i32(cpu_env, + cpu_sr_q =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, sr_q), "SR_Q"); - cpu_sr_t =3D tcg_global_mem_new_i32(cpu_env, + cpu_sr_t =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, sr_t), "SR_T"); - cpu_ssr =3D tcg_global_mem_new_i32(cpu_env, + cpu_ssr =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, ssr), "SSR"); - cpu_spc =3D tcg_global_mem_new_i32(cpu_env, + cpu_spc =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, spc), "SPC"); - cpu_gbr =3D tcg_global_mem_new_i32(cpu_env, + cpu_gbr =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, gbr), "GBR"); - cpu_vbr =3D tcg_global_mem_new_i32(cpu_env, + cpu_vbr =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, vbr), "VBR"); - cpu_sgr =3D tcg_global_mem_new_i32(cpu_env, + cpu_sgr =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, sgr), "SGR"); - cpu_dbr =3D tcg_global_mem_new_i32(cpu_env, + cpu_dbr =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, dbr), "DBR"); - cpu_mach =3D tcg_global_mem_new_i32(cpu_env, + cpu_mach =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, mach), "MACH"); - cpu_macl =3D tcg_global_mem_new_i32(cpu_env, + cpu_macl =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, macl), "MACL"); - cpu_pr =3D tcg_global_mem_new_i32(cpu_env, + cpu_pr =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, pr), "PR"); - cpu_fpscr =3D tcg_global_mem_new_i32(cpu_env, + cpu_fpscr =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, fpscr), "FPSC= R"); - cpu_fpul =3D tcg_global_mem_new_i32(cpu_env, + cpu_fpul =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, fpul), "FPUL"); =20 - cpu_flags =3D tcg_global_mem_new_i32(cpu_env, + cpu_flags =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, flags), "_flags_"); - cpu_delayed_pc =3D tcg_global_mem_new_i32(cpu_env, + cpu_delayed_pc =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, delayed_pc), "_delayed_pc_"); - cpu_delayed_cond =3D tcg_global_mem_new_i32(cpu_env, + cpu_delayed_cond =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, delayed_cond), "_delayed_cond_"); - cpu_lock_addr =3D tcg_global_mem_new_i32(cpu_env, + cpu_lock_addr =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, lock_addr= ), "_lock_addr_"); - cpu_lock_value =3D tcg_global_mem_new_i32(cpu_env, + cpu_lock_value =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, lock_val= ue), "_lock_value_"); =20 for (i =3D 0; i < 32; i++) - cpu_fregs[i] =3D tcg_global_mem_new_i32(cpu_env, + cpu_fregs[i] =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUSH4State, fregs[= i]), fregnames[i]); } @@ -416,7 +416,7 @@ static void _decode_opc(DisasContext * ctx) if (opcode !=3D 0x0093 /* ocbi */ && opcode !=3D 0x00c3 /* movca.l */) { - gen_helper_discard_movcal_backup(cpu_env); + gen_helper_discard_movcal_backup(tcg_env); ctx->has_movcal =3D 0; } } @@ -449,7 +449,7 @@ static void _decode_opc(DisasContext * ctx) return; case 0x0038: /* ldtlb */ CHECK_PRIVILEGED - gen_helper_ldtlb(cpu_env); + gen_helper_ldtlb(tcg_env); return; case 0x002b: /* rte */ CHECK_PRIVILEGED @@ -486,7 +486,7 @@ static void _decode_opc(DisasContext * ctx) case 0x001b: /* sleep */ CHECK_PRIVILEGED tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next + 2); - gen_helper_sleep(cpu_env); + gen_helper_sleep(tcg_env); return; } =20 @@ -807,7 +807,7 @@ static void _decode_opc(DisasContext * ctx) arg1 =3D tcg_temp_new(); tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, MO_TESL | MO_ALIGN); - gen_helper_macl(cpu_env, arg0, arg1); + gen_helper_macl(tcg_env, arg0, arg1); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); } @@ -821,7 +821,7 @@ static void _decode_opc(DisasContext * ctx) arg1 =3D tcg_temp_new(); tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, MO_TESL | MO_ALIGN); - gen_helper_macw(cpu_env, arg0, arg1); + gen_helper_macw(tcg_env, arg0, arg1); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); } @@ -1069,49 +1069,49 @@ static void _decode_opc(DisasContext * ctx) gen_load_fpr64(ctx, fp1, B7_4); switch (ctx->opcode & 0xf00f) { case 0xf000: /* fadd Rm,Rn */ - gen_helper_fadd_DT(fp0, cpu_env, fp0, fp1); + gen_helper_fadd_DT(fp0, tcg_env, fp0, fp1); break; case 0xf001: /* fsub Rm,Rn */ - gen_helper_fsub_DT(fp0, cpu_env, fp0, fp1); + gen_helper_fsub_DT(fp0, tcg_env, fp0, fp1); break; case 0xf002: /* fmul Rm,Rn */ - gen_helper_fmul_DT(fp0, cpu_env, fp0, fp1); + gen_helper_fmul_DT(fp0, tcg_env, fp0, fp1); break; case 0xf003: /* fdiv Rm,Rn */ - gen_helper_fdiv_DT(fp0, cpu_env, fp0, fp1); + gen_helper_fdiv_DT(fp0, tcg_env, fp0, fp1); break; case 0xf004: /* fcmp/eq Rm,Rn */ - gen_helper_fcmp_eq_DT(cpu_sr_t, cpu_env, fp0, fp1); + gen_helper_fcmp_eq_DT(cpu_sr_t, tcg_env, fp0, fp1); return; case 0xf005: /* fcmp/gt Rm,Rn */ - gen_helper_fcmp_gt_DT(cpu_sr_t, cpu_env, fp0, fp1); + gen_helper_fcmp_gt_DT(cpu_sr_t, tcg_env, fp0, fp1); return; } gen_store_fpr64(ctx, fp0, B11_8); } else { switch (ctx->opcode & 0xf00f) { case 0xf000: /* fadd Rm,Rn */ - gen_helper_fadd_FT(FREG(B11_8), cpu_env, + gen_helper_fadd_FT(FREG(B11_8), tcg_env, FREG(B11_8), FREG(B7_4)); break; case 0xf001: /* fsub Rm,Rn */ - gen_helper_fsub_FT(FREG(B11_8), cpu_env, + gen_helper_fsub_FT(FREG(B11_8), tcg_env, FREG(B11_8), FREG(B7_4)); break; case 0xf002: /* fmul Rm,Rn */ - gen_helper_fmul_FT(FREG(B11_8), cpu_env, + gen_helper_fmul_FT(FREG(B11_8), tcg_env, FREG(B11_8), FREG(B7_4)); break; case 0xf003: /* fdiv Rm,Rn */ - gen_helper_fdiv_FT(FREG(B11_8), cpu_env, + gen_helper_fdiv_FT(FREG(B11_8), tcg_env, FREG(B11_8), FREG(B7_4)); break; case 0xf004: /* fcmp/eq Rm,Rn */ - gen_helper_fcmp_eq_FT(cpu_sr_t, cpu_env, + gen_helper_fcmp_eq_FT(cpu_sr_t, tcg_env, FREG(B11_8), FREG(B7_4)); return; case 0xf005: /* fcmp/gt Rm,Rn */ - gen_helper_fcmp_gt_FT(cpu_sr_t, cpu_env, + gen_helper_fcmp_gt_FT(cpu_sr_t, tcg_env, FREG(B11_8), FREG(B7_4)); return; } @@ -1121,7 +1121,7 @@ static void _decode_opc(DisasContext * ctx) case 0xf00e: /* fmac FR0,RM,Rn */ CHECK_FPU_ENABLED CHECK_FPSCR_PR_0 - gen_helper_fmac_FT(FREG(B11_8), cpu_env, + gen_helper_fmac_FT(FREG(B11_8), tcg_env, FREG(0), FREG(B7_4), FREG(B11_8)); return; } @@ -1260,7 +1260,7 @@ static void _decode_opc(DisasContext * ctx) CHECK_NOT_DELAY_SLOT gen_save_cpu_state(ctx, true); imm =3D tcg_constant_i32(B7_0); - gen_helper_trapa(cpu_env, imm); + gen_helper_trapa(tcg_env, imm); ctx->base.is_jmp =3D DISAS_NORETURN; } return; @@ -1438,7 +1438,7 @@ static void _decode_opc(DisasContext * ctx) LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED}) case 0x406a: /* lds Rm,FPSCR */ CHECK_FPU_ENABLED - gen_helper_ld_fpscr(cpu_env, REG(B11_8)); + gen_helper_ld_fpscr(tcg_env, REG(B11_8)); ctx->base.is_jmp =3D DISAS_STOP; return; case 0x4066: /* lds.l @Rm+,FPSCR */ @@ -1448,7 +1448,7 @@ static void _decode_opc(DisasContext * ctx) tcg_gen_qemu_ld_i32(addr, REG(B11_8), ctx->memidx, MO_TESL | MO_ALIGN); tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); - gen_helper_ld_fpscr(cpu_env, addr); + gen_helper_ld_fpscr(tcg_env, addr); ctx->base.is_jmp =3D DISAS_STOP; } return; @@ -1473,7 +1473,7 @@ static void _decode_opc(DisasContext * ctx) TCGv val =3D tcg_temp_new(); tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, MO_TEUL | MO_ALIGN); - gen_helper_movcal(cpu_env, REG(B11_8), val); + gen_helper_movcal(tcg_env, REG(B11_8), val); tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL | MO_ALIGN); } @@ -1560,7 +1560,7 @@ static void _decode_opc(DisasContext * ctx) return; case 0x0093: /* ocbi @Rn */ { - gen_helper_ocbi(cpu_env, REG(B11_8)); + gen_helper_ocbi(tcg_env, REG(B11_8)); } return; case 0x00a3: /* ocbp @Rn */ @@ -1659,11 +1659,11 @@ static void _decode_opc(DisasContext * ctx) goto do_illegal; } fp =3D tcg_temp_new_i64(); - gen_helper_float_DT(fp, cpu_env, cpu_fpul); + gen_helper_float_DT(fp, tcg_env, cpu_fpul); gen_store_fpr64(ctx, fp, B11_8); } else { - gen_helper_float_FT(FREG(B11_8), cpu_env, cpu_fpul); + gen_helper_float_FT(FREG(B11_8), tcg_env, cpu_fpul); } return; case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag= ] */ @@ -1675,10 +1675,10 @@ static void _decode_opc(DisasContext * ctx) } fp =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp, B11_8); - gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp); + gen_helper_ftrc_DT(cpu_fpul, tcg_env, fp); } else { - gen_helper_ftrc_FT(cpu_fpul, cpu_env, FREG(B11_8)); + gen_helper_ftrc_FT(cpu_fpul, tcg_env, FREG(B11_8)); } return; case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ @@ -1697,16 +1697,16 @@ static void _decode_opc(DisasContext * ctx) } TCGv_i64 fp =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp, B11_8); - gen_helper_fsqrt_DT(fp, cpu_env, fp); + gen_helper_fsqrt_DT(fp, tcg_env, fp); gen_store_fpr64(ctx, fp, B11_8); } else { - gen_helper_fsqrt_FT(FREG(B11_8), cpu_env, FREG(B11_8)); + gen_helper_fsqrt_FT(FREG(B11_8), tcg_env, FREG(B11_8)); } return; case 0xf07d: /* fsrra FRn */ CHECK_FPU_ENABLED CHECK_FPSCR_PR_0 - gen_helper_fsrra_FT(FREG(B11_8), cpu_env, FREG(B11_8)); + gen_helper_fsrra_FT(FREG(B11_8), tcg_env, FREG(B11_8)); break; case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ CHECK_FPU_ENABLED @@ -1722,7 +1722,7 @@ static void _decode_opc(DisasContext * ctx) CHECK_FPU_ENABLED { TCGv_i64 fp =3D tcg_temp_new_i64(); - gen_helper_fcnvsd_FT_DT(fp, cpu_env, cpu_fpul); + gen_helper_fcnvsd_FT_DT(fp, tcg_env, cpu_fpul); gen_store_fpr64(ctx, fp, B11_8); } return; @@ -1731,7 +1731,7 @@ static void _decode_opc(DisasContext * ctx) { TCGv_i64 fp =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp, B11_8); - gen_helper_fcnvds_DT_FT(cpu_fpul, cpu_env, fp); + gen_helper_fcnvds_DT_FT(cpu_fpul, tcg_env, fp); } return; case 0xf0ed: /* fipr FVm,FVn */ @@ -1740,7 +1740,7 @@ static void _decode_opc(DisasContext * ctx) { TCGv m =3D tcg_constant_i32((ctx->opcode >> 8) & 3); TCGv n =3D tcg_constant_i32((ctx->opcode >> 10) & 3); - gen_helper_fipr(cpu_env, m, n); + gen_helper_fipr(tcg_env, m, n); return; } break; @@ -1752,7 +1752,7 @@ static void _decode_opc(DisasContext * ctx) goto do_illegal; } TCGv n =3D tcg_constant_i32((ctx->opcode >> 10) & 3); - gen_helper_ftrv(cpu_env, n); + gen_helper_ftrv(tcg_env, n); return; } break; @@ -1766,10 +1766,10 @@ static void _decode_opc(DisasContext * ctx) if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) { do_illegal_slot: gen_save_cpu_state(ctx, true); - gen_helper_raise_slot_illegal_instruction(cpu_env); + gen_helper_raise_slot_illegal_instruction(tcg_env); } else { gen_save_cpu_state(ctx, true); - gen_helper_raise_illegal_instruction(cpu_env); + gen_helper_raise_illegal_instruction(tcg_env); } ctx->base.is_jmp =3D DISAS_NORETURN; return; @@ -1777,9 +1777,9 @@ static void _decode_opc(DisasContext * ctx) do_fpu_disabled: gen_save_cpu_state(ctx, true); if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) { - gen_helper_raise_slot_fpu_disable(cpu_env); + gen_helper_raise_slot_fpu_disable(tcg_env); } else { - gen_helper_raise_fpu_disable(cpu_env); + gen_helper_raise_fpu_disable(tcg_env); } ctx->base.is_jmp =3D DISAS_NORETURN; return; @@ -2153,7 +2153,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4Stat= e *env) cpu_exec_step_atomic holding the exclusive lock. */ ctx->envflags |=3D TB_FLAG_GUSA_EXCLUSIVE; gen_save_cpu_state(ctx, false); - gen_helper_exclusive(cpu_env); + gen_helper_exclusive(tcg_env); ctx->base.is_jmp =3D DISAS_NORETURN; =20 /* We're not executing an instruction, but we must report one for the diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 3bf0ab8135..71b48cb3b7 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -187,25 +187,25 @@ static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsi= gned int dst) =20 static void gen_op_load_fpr_QT0(unsigned int src) { - tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt0)= + + tcg_gen_st_i64(cpu_fpr[src / 2], tcg_env, offsetof(CPUSPARCState, qt0)= + offsetof(CPU_QuadU, ll.upper)); - tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt= 0) + + tcg_gen_st_i64(cpu_fpr[src/2 + 1], tcg_env, offsetof(CPUSPARCState, qt= 0) + offsetof(CPU_QuadU, ll.lower)); } =20 static void gen_op_load_fpr_QT1(unsigned int src) { - tcg_gen_st_i64(cpu_fpr[src / 2], cpu_env, offsetof(CPUSPARCState, qt1)= + + tcg_gen_st_i64(cpu_fpr[src / 2], tcg_env, offsetof(CPUSPARCState, qt1)= + offsetof(CPU_QuadU, ll.upper)); - tcg_gen_st_i64(cpu_fpr[src/2 + 1], cpu_env, offsetof(CPUSPARCState, qt= 1) + + tcg_gen_st_i64(cpu_fpr[src/2 + 1], tcg_env, offsetof(CPUSPARCState, qt= 1) + offsetof(CPU_QuadU, ll.lower)); } =20 static void gen_op_store_QT0_fpr(unsigned int dst) { - tcg_gen_ld_i64(cpu_fpr[dst / 2], cpu_env, offsetof(CPUSPARCState, qt0)= + + tcg_gen_ld_i64(cpu_fpr[dst / 2], tcg_env, offsetof(CPUSPARCState, qt0)= + offsetof(CPU_QuadU, ll.upper)); - tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], cpu_env, offsetof(CPUSPARCState, qt= 0) + + tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], tcg_env, offsetof(CPUSPARCState, qt= 0) + offsetof(CPU_QuadU, ll.lower)); } =20 @@ -443,7 +443,7 @@ static void gen_op_addx_int(DisasContext *dc, TCGv dst,= TCGv src1, default: /* We need external help to produce the carry. */ carry_32 =3D tcg_temp_new_i32(); - gen_helper_compute_C_icc(carry_32, cpu_env); + gen_helper_compute_C_icc(carry_32, tcg_env); break; } =20 @@ -516,7 +516,7 @@ static void gen_op_subx_int(DisasContext *dc, TCGv dst,= TCGv src1, default: /* We need external help to produce the carry. */ carry_32 =3D tcg_temp_new_i32(); - gen_helper_compute_C_icc(carry_32, cpu_env); + gen_helper_compute_C_icc(carry_32, tcg_env); break; } =20 @@ -967,7 +967,7 @@ static void update_psr(DisasContext *dc) { if (dc->cc_op !=3D CC_OP_FLAGS) { dc->cc_op =3D CC_OP_FLAGS; - gen_helper_compute_psr(cpu_env); + gen_helper_compute_psr(tcg_env); } } =20 @@ -980,13 +980,13 @@ static void save_state(DisasContext *dc) static void gen_exception(DisasContext *dc, int which) { save_state(dc); - gen_helper_raise_exception(cpu_env, tcg_constant_i32(which)); + gen_helper_raise_exception(tcg_env, tcg_constant_i32(which)); dc->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_check_align(TCGv addr, int mask) { - gen_helper_check_align(cpu_env, addr, tcg_constant_i32(mask)); + gen_helper_check_align(tcg_env, addr, tcg_constant_i32(mask)); } =20 static void gen_mov_pc_npc(DisasContext *dc) @@ -1120,7 +1120,7 @@ static void gen_compare(DisasCompare *cmp, bool xcc, = unsigned int cond, =20 default: do_dynamic: - gen_helper_compute_psr(cpu_env); + gen_helper_compute_psr(tcg_env); dc->cc_op =3D CC_OP_FLAGS; /* FALLTHRU */ =20 @@ -1425,16 +1425,16 @@ static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1,= TCGv_i32 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmps_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmps_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmps_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmps_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmps_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmps_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); break; } } @@ -1443,16 +1443,16 @@ static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1,= TCGv_i64 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmpd_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmpd_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmpd_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmpd_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmpd_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmpd_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); break; } } @@ -1461,16 +1461,16 @@ static void gen_op_fcmpq(int fccno) { switch (fccno) { case 0: - gen_helper_fcmpq(cpu_fsr, cpu_env); + gen_helper_fcmpq(cpu_fsr, tcg_env); break; case 1: - gen_helper_fcmpq_fcc1(cpu_fsr, cpu_env); + gen_helper_fcmpq_fcc1(cpu_fsr, tcg_env); break; case 2: - gen_helper_fcmpq_fcc2(cpu_fsr, cpu_env); + gen_helper_fcmpq_fcc2(cpu_fsr, tcg_env); break; case 3: - gen_helper_fcmpq_fcc3(cpu_fsr, cpu_env); + gen_helper_fcmpq_fcc3(cpu_fsr, tcg_env); break; } } @@ -1479,16 +1479,16 @@ static void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1= , TCGv_i32 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmpes_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmpes_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmpes_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmpes_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmpes_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmpes_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); break; } } @@ -1497,16 +1497,16 @@ static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1= , TCGv_i64 r_rs2) { switch (fccno) { case 0: - gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 1: - gen_helper_fcmped_fcc1(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmped_fcc1(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 2: - gen_helper_fcmped_fcc2(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmped_fcc2(cpu_fsr, tcg_env, r_rs1, r_rs2); break; case 3: - gen_helper_fcmped_fcc3(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmped_fcc3(cpu_fsr, tcg_env, r_rs1, r_rs2); break; } } @@ -1515,16 +1515,16 @@ static void gen_op_fcmpeq(int fccno) { switch (fccno) { case 0: - gen_helper_fcmpeq(cpu_fsr, cpu_env); + gen_helper_fcmpeq(cpu_fsr, tcg_env); break; case 1: - gen_helper_fcmpeq_fcc1(cpu_fsr, cpu_env); + gen_helper_fcmpeq_fcc1(cpu_fsr, tcg_env); break; case 2: - gen_helper_fcmpeq_fcc2(cpu_fsr, cpu_env); + gen_helper_fcmpeq_fcc2(cpu_fsr, tcg_env); break; case 3: - gen_helper_fcmpeq_fcc3(cpu_fsr, cpu_env); + gen_helper_fcmpeq_fcc3(cpu_fsr, tcg_env); break; } } @@ -1533,32 +1533,32 @@ static void gen_op_fcmpeq(int fccno) =20 static void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) { - gen_helper_fcmps(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmps(cpu_fsr, tcg_env, r_rs1, r_rs2); } =20 static void gen_op_fcmpd(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) { - gen_helper_fcmpd(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmpd(cpu_fsr, tcg_env, r_rs1, r_rs2); } =20 static void gen_op_fcmpq(int fccno) { - gen_helper_fcmpq(cpu_fsr, cpu_env); + gen_helper_fcmpq(cpu_fsr, tcg_env); } =20 static void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) { - gen_helper_fcmpes(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmpes(cpu_fsr, tcg_env, r_rs1, r_rs2); } =20 static void gen_op_fcmped(int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2) { - gen_helper_fcmped(cpu_fsr, cpu_env, r_rs1, r_rs2); + gen_helper_fcmped(cpu_fsr, tcg_env, r_rs1, r_rs2); } =20 static void gen_op_fcmpeq(int fccno) { - gen_helper_fcmpeq(cpu_fsr, cpu_env); + gen_helper_fcmpeq(cpu_fsr, tcg_env); } #endif =20 @@ -1593,8 +1593,8 @@ static void gen_fop_FF(DisasContext *dc, int rd, int = rs, src =3D gen_load_fpr_F(dc, rs); dst =3D gen_dest_fpr_F(dc); =20 - gen(dst, cpu_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); + gen(dst, tcg_env, src); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); =20 gen_store_fpr_F(dc, rd, dst); } @@ -1621,8 +1621,8 @@ static void gen_fop_FFF(DisasContext *dc, int rd, int= rs1, int rs2, src2 =3D gen_load_fpr_F(dc, rs2); dst =3D gen_dest_fpr_F(dc); =20 - gen(dst, cpu_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); + gen(dst, tcg_env, src1, src2); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); =20 gen_store_fpr_F(dc, rd, dst); } @@ -1651,8 +1651,8 @@ static void gen_fop_DD(DisasContext *dc, int rd, int = rs, src =3D gen_load_fpr_D(dc, rs); dst =3D gen_dest_fpr_D(dc, rd); =20 - gen(dst, cpu_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); + gen(dst, tcg_env, src); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); =20 gen_store_fpr_D(dc, rd, dst); } @@ -1681,8 +1681,8 @@ static void gen_fop_DDD(DisasContext *dc, int rd, int= rs1, int rs2, src2 =3D gen_load_fpr_D(dc, rs2); dst =3D gen_dest_fpr_D(dc, rd); =20 - gen(dst, cpu_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); + gen(dst, tcg_env, src1, src2); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); =20 gen_store_fpr_D(dc, rd, dst); } @@ -1737,8 +1737,8 @@ static void gen_fop_QQ(DisasContext *dc, int rd, int = rs, { gen_op_load_fpr_QT1(QFPREG(rs)); =20 - gen(cpu_env); - gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); + gen(tcg_env); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); =20 gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(dc, QFPREG(rd)); @@ -1750,7 +1750,7 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, i= nt rs, { gen_op_load_fpr_QT1(QFPREG(rs)); =20 - gen(cpu_env); + gen(tcg_env); =20 gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(dc, QFPREG(rd)); @@ -1763,8 +1763,8 @@ static void gen_fop_QQQ(DisasContext *dc, int rd, int= rs1, int rs2, gen_op_load_fpr_QT0(QFPREG(rs1)); gen_op_load_fpr_QT1(QFPREG(rs2)); =20 - gen(cpu_env); - gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); + gen(tcg_env); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); =20 gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(dc, QFPREG(rd)); @@ -1780,8 +1780,8 @@ static void gen_fop_DFF(DisasContext *dc, int rd, int= rs1, int rs2, src2 =3D gen_load_fpr_F(dc, rs2); dst =3D gen_dest_fpr_D(dc, rd); =20 - gen(dst, cpu_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); + gen(dst, tcg_env, src1, src2); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); =20 gen_store_fpr_D(dc, rd, dst); } @@ -1794,8 +1794,8 @@ static void gen_fop_QDD(DisasContext *dc, int rd, int= rs1, int rs2, src1 =3D gen_load_fpr_D(dc, rs1); src2 =3D gen_load_fpr_D(dc, rs2); =20 - gen(cpu_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); + gen(tcg_env, src1, src2); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); =20 gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(dc, QFPREG(rd)); @@ -1811,8 +1811,8 @@ static void gen_fop_DF(DisasContext *dc, int rd, int = rs, src =3D gen_load_fpr_F(dc, rs); dst =3D gen_dest_fpr_D(dc, rd); =20 - gen(dst, cpu_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); + gen(dst, tcg_env, src); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); =20 gen_store_fpr_D(dc, rd, dst); } @@ -1827,7 +1827,7 @@ static void gen_ne_fop_DF(DisasContext *dc, int rd, i= nt rs, src =3D gen_load_fpr_F(dc, rs); dst =3D gen_dest_fpr_D(dc, rd); =20 - gen(dst, cpu_env, src); + gen(dst, tcg_env, src); =20 gen_store_fpr_D(dc, rd, dst); } @@ -1841,8 +1841,8 @@ static void gen_fop_FD(DisasContext *dc, int rd, int = rs, src =3D gen_load_fpr_D(dc, rs); dst =3D gen_dest_fpr_F(dc); =20 - gen(dst, cpu_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); + gen(dst, tcg_env, src); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); =20 gen_store_fpr_F(dc, rd, dst); } @@ -1855,8 +1855,8 @@ static void gen_fop_FQ(DisasContext *dc, int rd, int = rs, gen_op_load_fpr_QT1(QFPREG(rs)); dst =3D gen_dest_fpr_F(dc); =20 - gen(dst, cpu_env); - gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); + gen(dst, tcg_env); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); =20 gen_store_fpr_F(dc, rd, dst); } @@ -1869,8 +1869,8 @@ static void gen_fop_DQ(DisasContext *dc, int rd, int = rs, gen_op_load_fpr_QT1(QFPREG(rs)); dst =3D gen_dest_fpr_D(dc, rd); =20 - gen(dst, cpu_env); - gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env); + gen(dst, tcg_env); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); =20 gen_store_fpr_D(dc, rd, dst); } @@ -1882,7 +1882,7 @@ static void gen_ne_fop_QF(DisasContext *dc, int rd, i= nt rs, =20 src =3D gen_load_fpr_F(dc, rs); =20 - gen(cpu_env, src); + gen(tcg_env, src); =20 gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(dc, QFPREG(rd)); @@ -1895,7 +1895,7 @@ static void gen_ne_fop_QD(DisasContext *dc, int rd, i= nt rs, =20 src =3D gen_load_fpr_D(dc, rs); =20 - gen(cpu_env, src); + gen(tcg_env, src); =20 gen_op_store_QT0_fpr(QFPREG(rd)); gen_update_fprs_dirty(dc, QFPREG(rd)); @@ -2170,11 +2170,11 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, = TCGv addr, =20 save_state(dc); #ifdef TARGET_SPARC64 - gen_helper_ld_asi(dst, cpu_env, addr, r_asi, r_mop); + gen_helper_ld_asi(dst, tcg_env, addr, r_asi, r_mop); #else { TCGv_i64 t64 =3D tcg_temp_new_i64(); - gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop); + gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop); tcg_gen_trunc_i64_tl(dst, t64); } #endif @@ -2243,12 +2243,12 @@ static void gen_st_asi(DisasContext *dc, TCGv src, = TCGv addr, =20 save_state(dc); #ifdef TARGET_SPARC64 - gen_helper_st_asi(cpu_env, addr, src, r_asi, r_mop); + gen_helper_st_asi(tcg_env, addr, src, r_asi, r_mop); #else { TCGv_i64 t64 =3D tcg_temp_new_i64(); tcg_gen_extu_tl_i64(t64, src); - gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop); + gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop); } #endif =20 @@ -2313,7 +2313,7 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst= , TCGv addr, int insn) /* ??? In theory, this should be raise DAE_invalid_asi. But the SS-20 roms do ldstuba [%l0] #ASI_M_CTL, %o1. */ if (tb_cflags(dc->base.tb) & CF_PARALLEL) { - gen_helper_exit_atomic(cpu_env); + gen_helper_exit_atomic(tcg_env); } else { TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); TCGv_i32 r_mop =3D tcg_constant_i32(MO_UB); @@ -2321,10 +2321,10 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv d= st, TCGv addr, int insn) =20 save_state(dc); t64 =3D tcg_temp_new_i64(); - gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop); + gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop); =20 s64 =3D tcg_constant_i64(0xff); - gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_mop); + gen_helper_st_asi(tcg_env, addr, s64, r_asi, r_mop); =20 tcg_gen_trunc_i64_tl(dst, t64); =20 @@ -2423,19 +2423,19 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, switch (size) { case 4: d64 =3D tcg_temp_new_i64(); - gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop); + gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); d32 =3D gen_dest_fpr_F(dc); tcg_gen_extrl_i64_i32(d32, d64); gen_store_fpr_F(dc, rd, d32); break; case 8: - gen_helper_ld_asi(cpu_fpr[rd / 2], cpu_env, addr, r_asi, r= _mop); + gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr, r_asi, r= _mop); break; case 16: d64 =3D tcg_temp_new_i64(); - gen_helper_ld_asi(d64, cpu_env, addr, r_asi, r_mop); + gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); tcg_gen_addi_tl(addr, addr, 8); - gen_helper_ld_asi(cpu_fpr[rd/2+1], cpu_env, addr, r_asi, r= _mop); + gen_helper_ld_asi(cpu_fpr[rd/2+1], tcg_env, addr, r_asi, r= _mop); tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); break; default: @@ -2575,7 +2575,7 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr,= int insn, int rd) TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 save_state(dc); - gen_helper_ld_asi(tmp, cpu_env, addr, r_asi, r_mop); + gen_helper_ld_asi(tmp, tcg_env, addr, r_asi, r_mop); =20 /* See above. */ if ((da.memop & MO_BSWAP) =3D=3D MO_TE) { @@ -2641,7 +2641,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, T= CGv addr, } =20 save_state(dc); - gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop); + gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop); } break; } @@ -2694,7 +2694,7 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr,= int insn, int rd) TCGv_i32 r_mop =3D tcg_constant_i32(MO_UQ); =20 save_state(dc); - gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop); + gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop); } break; } @@ -2744,7 +2744,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, T= CGv addr, TCGv_i32 r_mop =3D tcg_constant_i32(MO_UQ); =20 save_state(dc); - gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop); + gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop); } break; } @@ -2820,19 +2820,19 @@ static void gen_fmovq(DisasContext *dc, DisasCompar= e *cmp, int rd, int rs) } =20 #ifndef CONFIG_USER_ONLY -static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env cpu_env) +static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env tcg_env) { TCGv_i32 r_tl =3D tcg_temp_new_i32(); =20 /* load env->tl into r_tl */ - tcg_gen_ld_i32(r_tl, cpu_env, offsetof(CPUSPARCState, tl)); + tcg_gen_ld_i32(r_tl, tcg_env, offsetof(CPUSPARCState, tl)); =20 /* tl =3D [0 ... MAXTL_MASK] where MAXTL_MASK must be power of 2 */ tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK); =20 /* calculate offset to current trap state from env->ts, reuse r_tl */ tcg_gen_muli_i32(r_tl, r_tl, sizeof (trap_state)); - tcg_gen_addi_ptr(r_tsptr, cpu_env, offsetof(CPUSPARCState, ts)); + tcg_gen_addi_ptr(r_tsptr, tcg_env, offsetof(CPUSPARCState, ts)); =20 /* tsptr =3D env->ts[env->tl & MAXTL_MASK] */ { @@ -3159,7 +3159,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) tcg_gen_addi_i32(trap, trap, TT_TRAP); } =20 - gen_helper_raise_exception(cpu_env, trap); + gen_helper_raise_exception(tcg_env, trap); =20 if (cond =3D=3D 8) { /* An unconditional trap ends the TB. */ @@ -3197,7 +3197,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) #ifdef TARGET_SPARC64 case 0x2: /* V9 rdccr */ update_psr(dc); - gen_helper_rdccr(cpu_dst, cpu_env); + gen_helper_rdccr(cpu_dst, tcg_env); gen_store_gpr(dc, rd, cpu_dst); break; case 0x3: /* V9 rdasi */ @@ -3211,12 +3211,12 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) =20 r_tickptr =3D tcg_temp_new_ptr(); r_const =3D tcg_constant_i32(dc->mem_idx); - tcg_gen_ld_ptr(r_tickptr, cpu_env, + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, tick)); if (translator_io_start(&dc->base)) { dc->base.is_jmp =3D DISAS_EXIT; } - gen_helper_tick_get_count(cpu_dst, cpu_env, r_tick= ptr, + gen_helper_tick_get_count(cpu_dst, tcg_env, r_tick= ptr, r_const); gen_store_gpr(dc, rd, cpu_dst); } @@ -3245,7 +3245,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) gen_store_gpr(dc, rd, cpu_gsr); break; case 0x16: /* Softint */ - tcg_gen_ld32s_tl(cpu_dst, cpu_env, + tcg_gen_ld32s_tl(cpu_dst, tcg_env, offsetof(CPUSPARCState, softint)); gen_store_gpr(dc, rd, cpu_dst); break; @@ -3259,12 +3259,12 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) =20 r_tickptr =3D tcg_temp_new_ptr(); r_const =3D tcg_constant_i32(dc->mem_idx); - tcg_gen_ld_ptr(r_tickptr, cpu_env, + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, stick)); if (translator_io_start(&dc->base)) { dc->base.is_jmp =3D DISAS_EXIT; } - gen_helper_tick_get_count(cpu_dst, cpu_env, r_tick= ptr, + gen_helper_tick_get_count(cpu_dst, tcg_env, r_tick= ptr, r_const); gen_store_gpr(dc, rd, cpu_dst); } @@ -3299,7 +3299,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) goto priv_insn; } update_psr(dc); - gen_helper_rdpsr(cpu_dst, cpu_env); + gen_helper_rdpsr(cpu_dst, tcg_env); #else CHECK_IU_FEATURE(dc, HYPV); if (!hypervisor(dc)) @@ -3307,7 +3307,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) rs1 =3D GET_FIELD(insn, 13, 17); switch (rs1) { case 0: // hpstate - tcg_gen_ld_i64(cpu_dst, cpu_env, + tcg_gen_ld_i64(cpu_dst, tcg_env, offsetof(CPUSPARCState, hpstate)); break; case 1: // htstate @@ -3344,7 +3344,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) TCGv_ptr r_tsptr; =20 r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, cpu_env); + gen_load_trap_state_at_tl(r_tsptr, tcg_env); tcg_gen_ld_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tpc)); } @@ -3354,7 +3354,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) TCGv_ptr r_tsptr; =20 r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, cpu_env); + gen_load_trap_state_at_tl(r_tsptr, tcg_env); tcg_gen_ld_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tnpc)); } @@ -3364,7 +3364,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) TCGv_ptr r_tsptr; =20 r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, cpu_env); + gen_load_trap_state_at_tl(r_tsptr, tcg_env); tcg_gen_ld_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tstate)); } @@ -3373,7 +3373,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) { TCGv_ptr r_tsptr =3D tcg_temp_new_ptr(); =20 - gen_load_trap_state_at_tl(r_tsptr, cpu_env); + gen_load_trap_state_at_tl(r_tsptr, tcg_env); tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tt)); } @@ -3385,12 +3385,12 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) =20 r_tickptr =3D tcg_temp_new_ptr(); r_const =3D tcg_constant_i32(dc->mem_idx); - tcg_gen_ld_ptr(r_tickptr, cpu_env, + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, tick)); if (translator_io_start(&dc->base)) { dc->base.is_jmp =3D DISAS_EXIT; } - gen_helper_tick_get_count(cpu_tmp0, cpu_env, + gen_helper_tick_get_count(cpu_tmp0, tcg_env, r_tickptr, r_const); } break; @@ -3398,43 +3398,43 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) tcg_gen_mov_tl(cpu_tmp0, cpu_tbr); break; case 6: // pstate - tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, + tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, offsetof(CPUSPARCState, pstate)); break; case 7: // tl - tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, + tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, offsetof(CPUSPARCState, tl)); break; case 8: // pil - tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, + tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, offsetof(CPUSPARCState, psrpil)); break; case 9: // cwp - gen_helper_rdcwp(cpu_tmp0, cpu_env); + gen_helper_rdcwp(cpu_tmp0, tcg_env); break; case 10: // cansave - tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, + tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, offsetof(CPUSPARCState, cansave)); break; case 11: // canrestore - tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, + tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, offsetof(CPUSPARCState, canrestore)); break; case 12: // cleanwin - tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, + tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, offsetof(CPUSPARCState, cleanwin)); break; case 13: // otherwin - tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, + tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, offsetof(CPUSPARCState, otherwin)); break; case 14: // wstate - tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, + tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, offsetof(CPUSPARCState, wstate)); break; case 16: // UA2005 gl CHECK_IU_FEATURE(dc, GL); - tcg_gen_ld32s_tl(cpu_tmp0, cpu_env, + tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, offsetof(CPUSPARCState, gl)); break; case 26: // UA2005 strand status @@ -3459,7 +3459,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) #if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) } else if (xop =3D=3D 0x2b) { /* rdtbr / V9 flushw */ #ifdef TARGET_SPARC64 - gen_helper_flushw(cpu_env); + gen_helper_flushw(tcg_env); #else if (!supervisor(dc)) goto priv_insn; @@ -4002,28 +4002,28 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) break; #ifdef TARGET_SPARC64 case 0xd: /* V9 udivx */ - gen_helper_udivx(cpu_dst, cpu_env, cpu_src1, cpu_s= rc2); + gen_helper_udivx(cpu_dst, tcg_env, cpu_src1, cpu_s= rc2); break; #endif case 0xe: /* udiv */ CHECK_IU_FEATURE(dc, DIV); if (xop & 0x10) { - gen_helper_udiv_cc(cpu_dst, cpu_env, cpu_src1, + gen_helper_udiv_cc(cpu_dst, tcg_env, cpu_src1, cpu_src2); dc->cc_op =3D CC_OP_DIV; } else { - gen_helper_udiv(cpu_dst, cpu_env, cpu_src1, + gen_helper_udiv(cpu_dst, tcg_env, cpu_src1, cpu_src2); } break; case 0xf: /* sdiv */ CHECK_IU_FEATURE(dc, DIV); if (xop & 0x10) { - gen_helper_sdiv_cc(cpu_dst, cpu_env, cpu_src1, + gen_helper_sdiv_cc(cpu_dst, tcg_env, cpu_src1, cpu_src2); dc->cc_op =3D CC_OP_DIV; } else { - gen_helper_sdiv(cpu_dst, cpu_env, cpu_src1, + gen_helper_sdiv(cpu_dst, tcg_env, cpu_src1, cpu_src2); } break; @@ -4048,13 +4048,13 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) dc->cc_op =3D CC_OP_TSUB; break; case 0x22: /* taddcctv */ - gen_helper_taddcctv(cpu_dst, cpu_env, + gen_helper_taddcctv(cpu_dst, tcg_env, cpu_src1, cpu_src2); gen_store_gpr(dc, rd, cpu_dst); dc->cc_op =3D CC_OP_TADDTV; break; case 0x23: /* tsubcctv */ - gen_helper_tsubcctv(cpu_dst, cpu_env, + gen_helper_tsubcctv(cpu_dst, tcg_env, cpu_src1, cpu_src2); gen_store_gpr(dc, rd, cpu_dst); dc->cc_op =3D CC_OP_TSUBTV; @@ -4122,20 +4122,20 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) CPU_FEATURE_POWERDOWN= )) { /* LEON3 power-down */ save_state(dc); - gen_helper_power_down(cpu_env); + gen_helper_power_down(tcg_env); } break; #else case 0x2: /* V9 wrccr */ tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src= 2); - gen_helper_wrccr(cpu_env, cpu_tmp0); + gen_helper_wrccr(tcg_env, cpu_tmp0); tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); dc->cc_op =3D CC_OP_FLAGS; break; case 0x3: /* V9 wrasi */ tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src= 2); tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff); - tcg_gen_st32_tl(cpu_tmp0, cpu_env, + tcg_gen_st32_tl(cpu_tmp0, tcg_env, offsetof(CPUSPARCState, as= i)); /* * End TB to notice changed ASI. @@ -4173,19 +4173,19 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) if (!supervisor(dc)) goto illegal_insn; tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src= 2); - gen_helper_set_softint(cpu_env, cpu_tmp0); + gen_helper_set_softint(tcg_env, cpu_tmp0); break; case 0x15: /* Softint clear */ if (!supervisor(dc)) goto illegal_insn; tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src= 2); - gen_helper_clear_softint(cpu_env, cpu_tmp0= ); + gen_helper_clear_softint(tcg_env, cpu_tmp0= ); break; case 0x16: /* Softint write */ if (!supervisor(dc)) goto illegal_insn; tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src= 2); - gen_helper_write_softint(cpu_env, cpu_tmp0= ); + gen_helper_write_softint(tcg_env, cpu_tmp0= ); break; case 0x17: /* Tick compare */ #if !defined(CONFIG_USER_ONLY) @@ -4198,7 +4198,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1, cpu_src2); r_tickptr =3D tcg_temp_new_ptr(); - tcg_gen_ld_ptr(r_tickptr, cpu_env, + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState,= tick)); translator_io_start(&dc->base); gen_helper_tick_set_limit(r_tickptr, @@ -4218,7 +4218,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); r_tickptr =3D tcg_temp_new_ptr(); - tcg_gen_ld_ptr(r_tickptr, cpu_env, + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState,= stick)); translator_io_start(&dc->base); gen_helper_tick_set_count(r_tickptr, @@ -4238,7 +4238,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src= 1, cpu_src2); r_tickptr =3D tcg_temp_new_ptr(); - tcg_gen_ld_ptr(r_tickptr, cpu_env, + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState,= stick)); translator_io_start(&dc->base); gen_helper_tick_set_limit(r_tickptr, @@ -4266,10 +4266,10 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) #ifdef TARGET_SPARC64 switch (rd) { case 0: - gen_helper_saved(cpu_env); + gen_helper_saved(tcg_env); break; case 1: - gen_helper_restored(cpu_env); + gen_helper_restored(tcg_env); break; case 2: /* UA2005 allclean */ case 3: /* UA2005 otherw */ @@ -4282,7 +4282,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) #else cpu_tmp0 =3D tcg_temp_new(); tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); - gen_helper_wrpsr(cpu_env, cpu_tmp0); + gen_helper_wrpsr(tcg_env, cpu_tmp0); tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); dc->cc_op =3D CC_OP_FLAGS; save_state(dc); @@ -4305,7 +4305,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) TCGv_ptr r_tsptr; =20 r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, cpu= _env); + gen_load_trap_state_at_tl(r_tsptr, tcg= _env); tcg_gen_st_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tpc= )); } @@ -4315,7 +4315,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) TCGv_ptr r_tsptr; =20 r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, cpu= _env); + gen_load_trap_state_at_tl(r_tsptr, tcg= _env); tcg_gen_st_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tnp= c)); } @@ -4325,7 +4325,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) TCGv_ptr r_tsptr; =20 r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, cpu= _env); + gen_load_trap_state_at_tl(r_tsptr, tcg= _env); tcg_gen_st_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tstate)); @@ -4336,7 +4336,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) TCGv_ptr r_tsptr; =20 r_tsptr =3D tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, cpu= _env); + gen_load_trap_state_at_tl(r_tsptr, tcg= _env); tcg_gen_st32_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, t= t)); } @@ -4346,7 +4346,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) TCGv_ptr r_tickptr; =20 r_tickptr =3D tcg_temp_new_ptr(); - tcg_gen_ld_ptr(r_tickptr, cpu_env, + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState,= tick)); translator_io_start(&dc->base); gen_helper_tick_set_count(r_tickptr, @@ -4363,12 +4363,12 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) if (translator_io_start(&dc->base)) { dc->base.is_jmp =3D DISAS_EXIT; } - gen_helper_wrpstate(cpu_env, cpu_tmp0); + gen_helper_wrpstate(tcg_env, cpu_tmp0); dc->npc =3D DYNAMIC_PC; break; case 7: // tl save_state(dc); - tcg_gen_st32_tl(cpu_tmp0, cpu_env, + tcg_gen_st32_tl(cpu_tmp0, tcg_env, offsetof(CPUSPARCState, tl)= ); dc->npc =3D DYNAMIC_PC; break; @@ -4376,39 +4376,39 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) if (translator_io_start(&dc->base)) { dc->base.is_jmp =3D DISAS_EXIT; } - gen_helper_wrpil(cpu_env, cpu_tmp0); + gen_helper_wrpil(tcg_env, cpu_tmp0); break; case 9: // cwp - gen_helper_wrcwp(cpu_env, cpu_tmp0); + gen_helper_wrcwp(tcg_env, cpu_tmp0); break; case 10: // cansave - tcg_gen_st32_tl(cpu_tmp0, cpu_env, + tcg_gen_st32_tl(cpu_tmp0, tcg_env, offsetof(CPUSPARCState, cansave)); break; case 11: // canrestore - tcg_gen_st32_tl(cpu_tmp0, cpu_env, + tcg_gen_st32_tl(cpu_tmp0, tcg_env, offsetof(CPUSPARCState, canrestore)); break; case 12: // cleanwin - tcg_gen_st32_tl(cpu_tmp0, cpu_env, + tcg_gen_st32_tl(cpu_tmp0, tcg_env, offsetof(CPUSPARCState, cleanwin)); break; case 13: // otherwin - tcg_gen_st32_tl(cpu_tmp0, cpu_env, + tcg_gen_st32_tl(cpu_tmp0, tcg_env, offsetof(CPUSPARCState, otherwin)); break; case 14: // wstate - tcg_gen_st32_tl(cpu_tmp0, cpu_env, + tcg_gen_st32_tl(cpu_tmp0, tcg_env, offsetof(CPUSPARCState, wstate)); break; case 16: // UA2005 gl CHECK_IU_FEATURE(dc, GL); - gen_helper_wrgl(cpu_env, cpu_tmp0); + gen_helper_wrgl(tcg_env, cpu_tmp0); break; case 26: // UA2005 strand status CHECK_IU_FEATURE(dc, HYPV); @@ -4442,7 +4442,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); switch (rd) { case 0: // hpstate - tcg_gen_st_i64(cpu_tmp0, cpu_env, + tcg_gen_st_i64(cpu_tmp0, tcg_env, offsetof(CPUSPARCState, hpstate)); save_state(dc); @@ -4465,7 +4465,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) =20 tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tm= p0); r_tickptr =3D tcg_temp_new_ptr(); - tcg_gen_ld_ptr(r_tickptr, cpu_env, + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState,= hstick)); translator_io_start(&dc->base); gen_helper_tick_set_limit(r_tickptr, @@ -4518,7 +4518,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) break; } case 0x2d: /* V9 sdivx */ - gen_helper_sdivx(cpu_dst, cpu_env, cpu_src1, cpu_s= rc2); + gen_helper_sdivx(cpu_dst, tcg_env, cpu_src1, cpu_s= rc2); gen_store_gpr(dc, rd, cpu_dst); break; case 0x2e: /* V9 popc */ @@ -5019,7 +5019,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) tcg_gen_mov_tl(cpu_tmp0, cpu_src1); } } - gen_helper_restore(cpu_env); + gen_helper_restore(tcg_env); gen_mov_pc_npc(dc); gen_check_align(cpu_tmp0, 3); tcg_gen_mov_tl(cpu_npc, cpu_tmp0); @@ -5064,7 +5064,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) gen_check_align(cpu_tmp0, 3); tcg_gen_mov_tl(cpu_npc, cpu_tmp0); dc->npc =3D DYNAMIC_PC; - gen_helper_rett(cpu_env); + gen_helper_rett(tcg_env); } goto jmp_insn; #endif @@ -5074,11 +5074,11 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) /* nop */ break; case 0x3c: /* save */ - gen_helper_save(cpu_env); + gen_helper_save(tcg_env); gen_store_gpr(dc, rd, cpu_tmp0); break; case 0x3d: /* restore */ - gen_helper_restore(cpu_env); + gen_helper_restore(tcg_env); gen_store_gpr(dc, rd, cpu_tmp0); break; #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) @@ -5091,7 +5091,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) dc->npc =3D DYNAMIC_PC; dc->pc =3D DYNAMIC_PC; translator_io_start(&dc->base); - gen_helper_done(cpu_env); + gen_helper_done(tcg_env); goto jmp_insn; case 1: if (!supervisor(dc)) @@ -5099,7 +5099,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) dc->npc =3D DYNAMIC_PC; dc->pc =3D DYNAMIC_PC; translator_io_start(&dc->base); - gen_helper_retry(cpu_env); + gen_helper_retry(tcg_env); goto jmp_insn; default: goto illegal_insn; @@ -5302,14 +5302,14 @@ static void disas_sparc_insn(DisasContext * dc, uns= igned int insn) TCGv_i64 t64 =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(t64, cpu_addr, dc->mem_idx, MO_TEUQ | MO_ALIG= N); - gen_helper_ldxfsr(cpu_fsr, cpu_env, cpu_fsr, t64); + gen_helper_ldxfsr(cpu_fsr, tcg_env, cpu_fsr, t64); break; } #endif cpu_dst_32 =3D tcg_temp_new_i32(); tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr, dc->mem_idx, MO_TEUL | MO_ALIGN); - gen_helper_ldfsr(cpu_fsr, cpu_env, cpu_fsr, cpu_dst_32= ); + gen_helper_ldfsr(cpu_fsr, tcg_env, cpu_fsr, cpu_dst_32= ); break; case 0x22: /* ldqf, load quad fpreg */ CHECK_FPU_FEATURE(dc, FLOAT128); @@ -5770,21 +5770,21 @@ void sparc_tcg_init(void) =20 unsigned int i; =20 - cpu_regwptr =3D tcg_global_mem_new_ptr(cpu_env, + cpu_regwptr =3D tcg_global_mem_new_ptr(tcg_env, offsetof(CPUSPARCState, regwptr), "regwptr"); =20 for (i =3D 0; i < ARRAY_SIZE(r32); ++i) { - *r32[i].ptr =3D tcg_global_mem_new_i32(cpu_env, r32[i].off, r32[i]= .name); + *r32[i].ptr =3D tcg_global_mem_new_i32(tcg_env, r32[i].off, r32[i]= .name); } =20 for (i =3D 0; i < ARRAY_SIZE(rtl); ++i) { - *rtl[i].ptr =3D tcg_global_mem_new(cpu_env, rtl[i].off, rtl[i].nam= e); + *rtl[i].ptr =3D tcg_global_mem_new(tcg_env, rtl[i].off, rtl[i].nam= e); } =20 cpu_regs[0] =3D NULL; for (i =3D 1; i < 8; ++i) { - cpu_regs[i] =3D tcg_global_mem_new(cpu_env, + cpu_regs[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUSPARCState, gregs[i]), gregnames[i]); } @@ -5796,7 +5796,7 @@ void sparc_tcg_init(void) } =20 for (i =3D 0; i < TARGET_DPREGS; i++) { - cpu_fpr[i] =3D tcg_global_mem_new_i64(cpu_env, + cpu_fpr[i] =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUSPARCState, fpr[i]= ), fregnames[i]); } diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 6ae5ccbf72..4206728afd 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -132,7 +132,7 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int = flags) =20 #define gen_helper_1arg(name, arg) do { \ TCGv_i32 helper_tmp =3D tcg_constant_i32(arg); \ - gen_helper_##name(cpu_env, helper_tmp); \ + gen_helper_##name(tcg_env, helper_tmp); \ } while (0) =20 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \ @@ -191,7 +191,7 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int = flags) #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \ TCGv_i64 ret =3D tcg_temp_new_i64(); \ \ - gen_helper_##name(ret, cpu_env, arg1, arg2); \ + gen_helper_##name(ret, tcg_env, arg1, arg2); \ tcg_gen_extr_i64_i32(rl, rh, ret); \ } while (0) =20 @@ -341,7 +341,7 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TCG= v ea) #define R(ADDRESS, REG, FEATURE) \ case ADDRESS: \ if (has_feature(ctx, FEATURE)) { \ - tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \ + tcg_gen_ld_tl(ret, tcg_env, offsetof(CPUTriCoreState, REG)); \ } \ break; #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) @@ -350,7 +350,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret= , int32_t offset) { /* since we're caching PSW make this a special case */ if (offset =3D=3D 0xfe04) { - gen_helper_psw_read(ret, cpu_env); + gen_helper_psw_read(ret, tcg_env); } else { switch (offset) { #include "csfr.h.inc" @@ -366,7 +366,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret= , int32_t offset) #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ case ADDRESS: \ if (has_feature(ctx, FEATURE)) { \ - tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \ + tcg_gen_st_tl(r1, tcg_env, offsetof(CPUTriCoreState, REG)); \ } \ break; /* Endinit protected registers @@ -380,7 +380,7 @@ static inline void gen_mtcr(DisasContext *ctx, TCGv r1, if (ctx->priv =3D=3D TRICORE_PRIV_SM) { /* since we're caching PSW make this a special case */ if (offset =3D=3D 0xfe04) { - gen_helper_psw_write(cpu_env, r1); + gen_helper_psw_write(tcg_env, r1); ctx->base.is_jmp =3D DISAS_EXIT_UPDATE; } else { switch (offset) { @@ -788,7 +788,7 @@ gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low= , TCGv r1_high, TCGv r2, tcg_gen_shli_i64(temp64, temp64, 16); tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); =20 - gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); + gen_helper_add64_ssov(temp64, tcg_env, temp64_2, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); } =20 @@ -843,7 +843,7 @@ gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, = TCGv r1_high, TCGv r2, break; } tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); - gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); + gen_helper_add64_ssov(temp64, tcg_env, temp64_2, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); } =20 @@ -867,7 +867,7 @@ gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv= r2, TCGv r3, uint32_t n, GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } - gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high); + gen_helper_addr_h(ret, tcg_env, temp64, r1_low, r1_high); } =20 static inline void @@ -904,7 +904,7 @@ gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, ui= nt32_t n, uint32_t mode) } tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); - gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2); + gen_helper_addsur_h(ret, tcg_env, temp64, temp, temp2); } =20 =20 @@ -928,7 +928,7 @@ gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCG= v r2, TCGv r3, GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } - gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); + gen_helper_addr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high); } =20 static inline void @@ -965,21 +965,21 @@ gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3,= uint32_t n, uint32_t mode) } tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); - gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2); + gen_helper_addsur_h_ssov(ret, tcg_env, temp64, temp, temp2); } =20 static inline void gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) { TCGv t_n =3D tcg_constant_i32(n); - gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, t_n); + gen_helper_maddr_q(ret, tcg_env, r1, r2, r3, t_n); } =20 static inline void gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) { TCGv t_n =3D tcg_constant_i32(n); - gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, t_n); + gen_helper_maddr_q_ssov(ret, tcg_env, r1, r2, r3, t_n); } =20 static inline void @@ -1115,7 +1115,7 @@ gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv= arg1_high, TCGv arg2, tcg_gen_shli_i64(t2, t2, 16); tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); =20 - gen_helper_add64_ssov(t1, cpu_env, t1, t2); + gen_helper_add64_ssov(t1, tcg_env, t1, t2); tcg_gen_extr_i64_i32(rl, rh, t1); } =20 @@ -1182,7 +1182,7 @@ gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv ar= g3, uint32_t n, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_sari_i64(t2, t2, up_shift - n); =20 - gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2); + gen_helper_madd32_q_add_ssov(ret, tcg_env, t1, t2); } =20 static inline void @@ -1193,7 +1193,7 @@ gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv a= rg1_high, TCGv arg2, TCGv t_n =3D tcg_constant_i32(n); =20 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); - gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n); + gen_helper_madd64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n); tcg_gen_extr_i64_i32(rl, rh, r1); } =20 @@ -1638,7 +1638,7 @@ gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low= , TCGv r1_high, TCGv r2, break; } tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); - gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); + gen_helper_sub64_ssov(temp64, tcg_env, temp64_2, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); } =20 @@ -1662,7 +1662,7 @@ gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TC= Gv r2, TCGv r3, uint32_t n, GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } - gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high); + gen_helper_subr_h(ret, tcg_env, temp64, r1_low, r1_high); } =20 static inline void @@ -1696,7 +1696,7 @@ gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, T= CGv r2, TCGv r3, GEN_HELPER_UU(mul_h, temp64, r2, r3, t_n); break; } - gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); + gen_helper_subr_h_ssov(ret, tcg_env, temp64, r1_low, r1_high); } =20 static inline void @@ -1714,14 +1714,14 @@ static inline void gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) { TCGv temp =3D tcg_constant_i32(n); - gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp); + gen_helper_msubr_q(ret, tcg_env, r1, r2, r3, temp); } =20 static inline void gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) { TCGv temp =3D tcg_constant_i32(n); - gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp); + gen_helper_msubr_q_ssov(ret, tcg_env, r1, r2, r3, temp); } =20 static inline void @@ -1848,7 +1848,7 @@ gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv= arg1_high, TCGv arg2, tcg_gen_shli_i64(t2, t2, 16); tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); =20 - gen_helper_sub64_ssov(t1, cpu_env, t1, t2); + gen_helper_sub64_ssov(t1, tcg_env, t1, t2); tcg_gen_extr_i64_i32(rl, rh, t1); } =20 @@ -1920,7 +1920,7 @@ gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv ar= g3, uint32_t n, tcg_gen_sari_i64(t3, t2, up_shift - n); tcg_gen_add_i64(t3, t3, t4); =20 - gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3); + gen_helper_msub32_q_sub_ssov(ret, tcg_env, t1, t3); } =20 static inline void @@ -1931,7 +1931,7 @@ gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv a= rg1_high, TCGv arg2, TCGv t_n =3D tcg_constant_i32(n); =20 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); - gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, t_n); + gen_helper_msub64_q_ssov(r1, tcg_env, r1, arg2, arg3, t_n); tcg_gen_extr_i64_i32(rl, rh, r1); } =20 @@ -2018,7 +2018,7 @@ gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, = uint32_t n, uint32_t mode) } tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); - gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2); + gen_helper_subadr_h(ret, tcg_env, temp64, temp, temp2); } =20 static inline void @@ -2084,7 +2084,7 @@ gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_l= ow, TCGv r1_high, TCGv r2, tcg_gen_shli_i64(temp64, temp64, 16); tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); =20 - gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); + gen_helper_sub64_ssov(temp64, tcg_env, temp64_2, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); } =20 @@ -2111,7 +2111,7 @@ gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3,= uint32_t n, uint32_t mode) } tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); - gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2); + gen_helper_subadr_h_ssov(ret, tcg_env, temp64, temp, temp2); } =20 static inline void gen_abs(TCGv ret, TCGv r1) @@ -2164,7 +2164,7 @@ static inline void gen_absdifi(TCGv ret, TCGv r1, int= 32_t con) static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_constant_i32(con); - gen_helper_absdif_ssov(ret, cpu_env, r1, temp); + gen_helper_absdif_ssov(ret, tcg_env, r1, temp); } =20 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) @@ -2238,26 +2238,26 @@ static inline void gen_muli_i64u(TCGv ret_low, TCGv= ret_high, TCGv r1, static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_constant_i32(con); - gen_helper_mul_ssov(ret, cpu_env, r1, temp); + gen_helper_mul_ssov(ret, tcg_env, r1, temp); } =20 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_constant_i32(con); - gen_helper_mul_suov(ret, cpu_env, r1, temp); + gen_helper_mul_suov(ret, tcg_env, r1, temp); } =20 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */ static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) { TCGv temp =3D tcg_constant_i32(con); - gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp); + gen_helper_madd32_ssov(ret, tcg_env, r1, r2, temp); } =20 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) { TCGv temp =3D tcg_constant_i32(con); - gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp); + gen_helper_madd32_suov(ret, tcg_env, r1, r2, temp); } =20 static void @@ -2371,7 +2371,7 @@ gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TC= Gv r2_low, TCGv r2_high, { TCGv_i64 temp64 =3D tcg_temp_new_i64(); tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); - gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3); + gen_helper_madd64_ssov(temp64, tcg_env, r1, temp64, r3); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); } =20 @@ -2389,7 +2389,7 @@ gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, T= CGv r2_low, TCGv r2_high, { TCGv_i64 temp64 =3D tcg_temp_new_i64(); tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); - gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3); + gen_helper_madd64_suov(temp64, tcg_env, r1, temp64, r3); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); } =20 @@ -2404,13 +2404,13 @@ gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1= , TCGv r2_low, TCGv r2_high, static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) { TCGv temp =3D tcg_constant_i32(con); - gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp); + gen_helper_msub32_ssov(ret, tcg_env, r1, r2, temp); } =20 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) { TCGv temp =3D tcg_constant_i32(con); - gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp); + gen_helper_msub32_suov(ret, tcg_env, r1, r2, temp); } =20 static inline void @@ -2419,7 +2419,7 @@ gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TC= Gv r2_low, TCGv r2_high, { TCGv_i64 temp64 =3D tcg_temp_new_i64(); tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); - gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3); + gen_helper_msub64_ssov(temp64, tcg_env, r1, temp64, r3); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); } =20 @@ -2437,7 +2437,7 @@ gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, T= CGv r2_low, TCGv r2_high, { TCGv_i64 temp64 =3D tcg_temp_new_i64(); tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); - gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3); + gen_helper_msub64_suov(temp64, tcg_env, r1, temp64, r3); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); } =20 @@ -2542,7 +2542,7 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t shif= t_count) =20 static void gen_shas(TCGv ret, TCGv r1, TCGv r2) { - gen_helper_sha_ssov(ret, cpu_env, r1, r2); + gen_helper_sha_ssov(ret, tcg_env, r1, r2); } =20 static void gen_shasi(TCGv ret, TCGv r1, int32_t con) @@ -2595,29 +2595,29 @@ static void gen_sh_condi(int cond, TCGv ret, TCGv r= 1, int32_t con) =20 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) { - gen_helper_add_ssov(ret, cpu_env, r1, r2); + gen_helper_add_ssov(ret, tcg_env, r1, r2); } =20 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_constant_i32(con); - gen_helper_add_ssov(ret, cpu_env, r1, temp); + gen_helper_add_ssov(ret, tcg_env, r1, temp); } =20 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_constant_i32(con); - gen_helper_add_suov(ret, cpu_env, r1, temp); + gen_helper_add_suov(ret, tcg_env, r1, temp); } =20 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2) { - gen_helper_sub_ssov(ret, cpu_env, r1, r2); + gen_helper_sub_ssov(ret, tcg_env, r1, r2); } =20 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2) { - gen_helper_sub_suov(ret, cpu_env, r1, r2); + gen_helper_sub_suov(ret, tcg_env, r1, r2); } =20 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2, @@ -2767,9 +2767,9 @@ gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCG= v r1, TCGv r2) TCGv_i64 ret =3D tcg_temp_new_i64(); =20 if (!has_feature(ctx, TRICORE_FEATURE_131)) { - gen_helper_dvinit_b_13(ret, cpu_env, r1, r2); + gen_helper_dvinit_b_13(ret, tcg_env, r1, r2); } else { - gen_helper_dvinit_b_131(ret, cpu_env, r1, r2); + gen_helper_dvinit_b_131(ret, tcg_env, r1, r2); } tcg_gen_extr_i64_i32(rl, rh, ret); } @@ -2780,9 +2780,9 @@ gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCG= v r1, TCGv r2) TCGv_i64 ret =3D tcg_temp_new_i64(); =20 if (!has_feature(ctx, TRICORE_FEATURE_131)) { - gen_helper_dvinit_h_13(ret, cpu_env, r1, r2); + gen_helper_dvinit_h_13(ret, tcg_env, r1, r2); } else { - gen_helper_dvinit_h_131(ret, cpu_env, r1, r2); + gen_helper_dvinit_h_131(ret, tcg_env, r1, r2); } tcg_gen_extr_i64_i32(rl, rh, ret); } @@ -2841,7 +2841,7 @@ static void generate_trap(DisasContext *ctx, int clas= s, int tin) TCGv_i32 tintemp =3D tcg_constant_i32(tin); =20 gen_save_pc(ctx->base.pc_next); - gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp); + gen_helper_raise_exception_sync(tcg_env, classtemp, tintemp); ctx->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -2996,7 +2996,7 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, int r1, break; case OPC2_32_SYS_RET: case OPC2_16_SR_RET: - gen_helper_ret(cpu_env); + gen_helper_ret(tcg_env); ctx->base.is_jmp =3D DISAS_EXIT; break; /* B-format */ @@ -3493,7 +3493,7 @@ static void decode_sr_system(DisasContext *ctx) gen_compute_branch(ctx, op2, 0, 0, 0, 0); break; case OPC2_16_SR_RFE: - gen_helper_rfe(cpu_env); + gen_helper_rfe(tcg_env); ctx->base.is_jmp =3D DISAS_EXIT; break; case OPC2_16_SR_DEBUG: @@ -4741,7 +4741,7 @@ static void decode_bo_addrmode_stctx_post_pre_base(Di= sasContext *ctx) switch (op2) { case OPC2_32_BO_LDLCX_SHORTOFF: tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); - gen_helper_ldlcx(cpu_env, temp); + gen_helper_ldlcx(tcg_env, temp); break; case OPC2_32_BO_LDMST_SHORTOFF: tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); @@ -4757,18 +4757,18 @@ static void decode_bo_addrmode_stctx_post_pre_base(= DisasContext *ctx) break; case OPC2_32_BO_LDUCX_SHORTOFF: tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); - gen_helper_lducx(cpu_env, temp); + gen_helper_lducx(tcg_env, temp); break; case OPC2_32_BO_LEA_SHORTOFF: tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10); break; case OPC2_32_BO_STLCX_SHORTOFF: tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); - gen_helper_stlcx(cpu_env, temp); + gen_helper_stlcx(tcg_env, temp); break; case OPC2_32_BO_STUCX_SHORTOFF: tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); - gen_helper_stucx(cpu_env, temp); + gen_helper_stucx(tcg_env, temp); break; case OPC2_32_BO_SWAP_W_SHORTOFF: tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); @@ -5590,44 +5590,44 @@ static void decode_rr_accumulator(DisasContext *ctx) gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]); break; case OPC2_32_RR_ABS_B: - gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); + gen_helper_abs_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); break; case OPC2_32_RR_ABS_H: - gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); + gen_helper_abs_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); break; case OPC2_32_RR_ABSDIF: gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_ABSDIF_B: - gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], + gen_helper_absdif_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_ABSDIF_H: - gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], + gen_helper_absdif_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_ABSDIFS: - gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], + gen_helper_absdif_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_ABSDIFS_H: - gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], + gen_helper_absdif_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_ABSS: - gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); + gen_helper_abs_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); break; case OPC2_32_RR_ABSS_H: - gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); + gen_helper_abs_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r2]); break; case OPC2_32_RR_ADD: gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_ADD_B: - gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[= r2]); + gen_helper_add_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[= r2]); break; case OPC2_32_RR_ADD_H: - gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[= r2]); + gen_helper_add_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[= r2]); break; case OPC2_32_RR_ADDC: gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); @@ -5636,15 +5636,15 @@ static void decode_rr_accumulator(DisasContext *ctx) gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_ADDS_H: - gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], + gen_helper_add_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_ADDS_HU: - gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], + gen_helper_add_h_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_ADDS_U: - gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], + gen_helper_add_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_ADDX: @@ -5862,10 +5862,10 @@ static void decode_rr_accumulator(DisasContext *ctx) gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_SUB_B: - gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[= r2]); + gen_helper_sub_b(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[= r2]); break; case OPC2_32_RR_SUB_H: - gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[= r2]); + gen_helper_sub_h(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[= r2]); break; case OPC2_32_RR_SUBC: gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); @@ -5877,11 +5877,11 @@ static void decode_rr_accumulator(DisasContext *ctx) gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_SUBS_H: - gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], + gen_helper_sub_h_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_SUBS_HU: - gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], + gen_helper_sub_h_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_SUBX: @@ -5971,7 +5971,7 @@ static void decode_rr_logical_shift(DisasContext *ctx) gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_SHA: - gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2= ]); + gen_helper_sha(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2= ]); break; case OPC2_32_RR_SHA_H: gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); @@ -6255,34 +6255,34 @@ static void decode_rr_divide(DisasContext *ctx) } break; case OPC2_32_RR_MUL_F: - gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r= 2]); + gen_helper_fmul(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r= 2]); break; case OPC2_32_RR_DIV_F: - gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r= 2]); + gen_helper_fdiv(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r= 2]); break; case OPC2_32_RR_CMP_F: - gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r= 2]); + gen_helper_fcmp(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r= 2]); break; case OPC2_32_RR_FTOI: - gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); + gen_helper_ftoi(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); break; case OPC2_32_RR_ITOF: - gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); + gen_helper_itof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); break; case OPC2_32_RR_FTOUZ: - gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); + gen_helper_ftouz(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); break; case OPC2_32_RR_UPDFL: - gen_helper_updfl(cpu_env, cpu_gpr_d[r1]); + gen_helper_updfl(tcg_env, cpu_gpr_d[r1]); break; case OPC2_32_RR_UTOF: - gen_helper_utof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); + gen_helper_utof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); break; case OPC2_32_RR_FTOIZ: - gen_helper_ftoiz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); + gen_helper_ftoiz(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); break; case OPC2_32_RR_QSEED_F: - gen_helper_qseed(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); + gen_helper_qseed(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]); break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -6483,7 +6483,7 @@ static void decode_rr2_mul(DisasContext *ctx) cpu_gpr_d[r2]); break; case OPC2_32_RR2_MULS_32: - gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], + gen_helper_mul_ssov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR2_MUL_U_64: @@ -6492,7 +6492,7 @@ static void decode_rr2_mul(DisasContext *ctx) cpu_gpr_d[r2]); break; case OPC2_32_RR2_MULS_U_32: - gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], + gen_helper_mul_suov(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); break; default: @@ -6670,17 +6670,17 @@ static void decode_rrr_divide(DisasContext *ctx) cpu_gpr_d[r3+1], cpu_gpr_d[r1]); break; case OPC2_32_RRR_ADD_F: - gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r= 3]); + gen_helper_fadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r= 3]); break; case OPC2_32_RRR_SUB_F: - gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r= 3]); + gen_helper_fsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r= 3]); break; case OPC2_32_RRR_MADD_F: - gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], + gen_helper_fmadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r3]); break; case OPC2_32_RRR_MSUB_F: - gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], + gen_helper_fmsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r3]); break; default: @@ -6711,7 +6711,7 @@ static void decode_rrr2_madd(DisasContext *ctx) cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); break; case OPC2_32_RRR2_MADDS_32: - gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], + gen_helper_madd32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3], cpu_gpr_d[r2]); break; case OPC2_32_RRR2_MADDS_64: @@ -6727,7 +6727,7 @@ static void decode_rrr2_madd(DisasContext *ctx) cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); break; case OPC2_32_RRR2_MADDS_U_32: - gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], + gen_helper_madd32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3], cpu_gpr_d[r2]); break; case OPC2_32_RRR2_MADDS_U_64: @@ -6764,7 +6764,7 @@ static void decode_rrr2_msub(DisasContext *ctx) cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); break; case OPC2_32_RRR2_MSUBS_32: - gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], + gen_helper_msub32_ssov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3], cpu_gpr_d[r2]); break; case OPC2_32_RRR2_MSUBS_64: @@ -6780,7 +6780,7 @@ static void decode_rrr2_msub(DisasContext *ctx) cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); break; case OPC2_32_RRR2_MSUBS_U_32: - gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], + gen_helper_msub32_suov(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3], cpu_gpr_d[r2]); break; case OPC2_32_RRR2_MSUBS_U_64: @@ -7933,7 +7933,7 @@ static void decode_sys_interrupts(DisasContext *ctx) gen_fret(ctx); break; case OPC2_32_SYS_RFE: - gen_helper_rfe(cpu_env); + gen_helper_rfe(tcg_env); ctx->base.is_jmp =3D DISAS_EXIT; break; case OPC2_32_SYS_RFM: @@ -7941,10 +7941,10 @@ static void decode_sys_interrupts(DisasContext *ctx) tmp =3D tcg_temp_new(); l1 =3D gen_new_label(); =20 - tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR= )); + tcg_gen_ld32u_tl(tmp, tcg_env, offsetof(CPUTriCoreState, DBGSR= )); tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE); tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1); - gen_helper_rfm(cpu_env); + gen_helper_rfm(tcg_env); gen_set_label(l1); ctx->base.is_jmp =3D DISAS_EXIT; } else { @@ -7952,10 +7952,10 @@ static void decode_sys_interrupts(DisasContext *ctx) } break; case OPC2_32_SYS_RSLCX: - gen_helper_rslcx(cpu_env); + gen_helper_rslcx(tcg_env); break; case OPC2_32_SYS_SVLCX: - gen_helper_svlcx(cpu_env); + gen_helper_svlcx(tcg_env); break; case OPC2_32_SYS_RESTORE: if (has_feature(ctx, TRICORE_FEATURE_16)) { @@ -8470,13 +8470,13 @@ void cpu_state_reset(CPUTriCoreState *env) =20 static void tricore_tcg_init_csfr(void) { - cpu_PCXI =3D tcg_global_mem_new(cpu_env, + cpu_PCXI =3D tcg_global_mem_new(tcg_env, offsetof(CPUTriCoreState, PCXI), "PCXI"); - cpu_PSW =3D tcg_global_mem_new(cpu_env, + cpu_PSW =3D tcg_global_mem_new(tcg_env, offsetof(CPUTriCoreState, PSW), "PSW"); - cpu_PC =3D tcg_global_mem_new(cpu_env, + cpu_PC =3D tcg_global_mem_new(tcg_env, offsetof(CPUTriCoreState, PC), "PC"); - cpu_ICR =3D tcg_global_mem_new(cpu_env, + cpu_ICR =3D tcg_global_mem_new(tcg_env, offsetof(CPUTriCoreState, ICR), "ICR"); } =20 @@ -8486,30 +8486,30 @@ void tricore_tcg_init(void) =20 /* reg init */ for (i =3D 0 ; i < 16 ; i++) { - cpu_gpr_a[i] =3D tcg_global_mem_new(cpu_env, + cpu_gpr_a[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUTriCoreState, gpr_a[= i]), regnames_a[i]); } for (i =3D 0 ; i < 16 ; i++) { - cpu_gpr_d[i] =3D tcg_global_mem_new(cpu_env, + cpu_gpr_d[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUTriCoreState, gpr_d[i]), regnames_d[i]); } tricore_tcg_init_csfr(); /* init PSW flag cache */ - cpu_PSW_C =3D tcg_global_mem_new(cpu_env, + cpu_PSW_C =3D tcg_global_mem_new(tcg_env, offsetof(CPUTriCoreState, PSW_USB_C), "PSW_C"); - cpu_PSW_V =3D tcg_global_mem_new(cpu_env, + cpu_PSW_V =3D tcg_global_mem_new(tcg_env, offsetof(CPUTriCoreState, PSW_USB_V), "PSW_V"); - cpu_PSW_SV =3D tcg_global_mem_new(cpu_env, + cpu_PSW_SV =3D tcg_global_mem_new(tcg_env, offsetof(CPUTriCoreState, PSW_USB_SV), "PSW_SV"); - cpu_PSW_AV =3D tcg_global_mem_new(cpu_env, + cpu_PSW_AV =3D tcg_global_mem_new(tcg_env, offsetof(CPUTriCoreState, PSW_USB_AV), "PSW_AV"); - cpu_PSW_SAV =3D tcg_global_mem_new(cpu_env, + cpu_PSW_SAV =3D tcg_global_mem_new(tcg_env, offsetof(CPUTriCoreState, PSW_USB_SAV= ), "PSW_SAV"); } diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index b7386ff0f0..fca1b9aba4 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -154,49 +154,49 @@ void xtensa_translate_init(void) }; int i; =20 - cpu_pc =3D tcg_global_mem_new_i32(cpu_env, + cpu_pc =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUXtensaState, pc), "pc"); =20 for (i =3D 0; i < 16; i++) { - cpu_R[i] =3D tcg_global_mem_new_i32(cpu_env, + cpu_R[i] =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUXtensaState, regs[i]= ), regnames[i]); } =20 for (i =3D 0; i < 16; i++) { - cpu_FR[i] =3D tcg_global_mem_new_i32(cpu_env, + cpu_FR[i] =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LO= W]), fregnames[i]); } =20 for (i =3D 0; i < 16; i++) { - cpu_FRD[i] =3D tcg_global_mem_new_i64(cpu_env, + cpu_FRD[i] =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUXtensaState, fregs[i].f64), fregnames[i]); } =20 for (i =3D 0; i < 4; i++) { - cpu_MR[i] =3D tcg_global_mem_new_i32(cpu_env, + cpu_MR[i] =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUXtensaState, sregs[MR + i]), mregnames[i]); } =20 for (i =3D 0; i < 16; i++) { - cpu_BR[i] =3D tcg_global_mem_new_i32(cpu_env, + cpu_BR[i] =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUXtensaState, sregs[BR]), bregnames[i]); if (i % 4 =3D=3D 0) { - cpu_BR4[i / 4] =3D tcg_global_mem_new_i32(cpu_env, + cpu_BR4[i / 4] =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUXtensaStat= e, sregs[BR]), bregnames[i]); } if (i % 8 =3D=3D 0) { - cpu_BR8[i / 8] =3D tcg_global_mem_new_i32(cpu_env, + cpu_BR8[i / 8] =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUXtensaStat= e, sregs[BR]), bregnames[i]); @@ -205,7 +205,7 @@ void xtensa_translate_init(void) =20 for (i =3D 0; i < 256; ++i) { if (sr_name[i]) { - cpu_SR[i] =3D tcg_global_mem_new_i32(cpu_env, + cpu_SR[i] =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUXtensaState, sregs[i]), sr_name[i]); @@ -214,7 +214,7 @@ void xtensa_translate_init(void) =20 for (i =3D 0; i < 256; ++i) { if (ur_name[i]) { - cpu_UR[i] =3D tcg_global_mem_new_i32(cpu_env, + cpu_UR[i] =3D tcg_global_mem_new_i32(tcg_env, offsetof(CPUXtensaState, uregs[i]), ur_name[i]); @@ -222,15 +222,15 @@ void xtensa_translate_init(void) } =20 cpu_windowbase_next =3D - tcg_global_mem_new_i32(cpu_env, + tcg_global_mem_new_i32(tcg_env, offsetof(CPUXtensaState, windowbase_next), "windowbase_next"); cpu_exclusive_addr =3D - tcg_global_mem_new_i32(cpu_env, + tcg_global_mem_new_i32(tcg_env, offsetof(CPUXtensaState, exclusive_addr), "exclusive_addr"); cpu_exclusive_val =3D - tcg_global_mem_new_i32(cpu_env, + tcg_global_mem_new_i32(tcg_env, offsetof(CPUXtensaState, exclusive_val), "exclusive_val"); } @@ -311,13 +311,13 @@ static void gen_left_shift_sar(DisasContext *dc, TCGv= _i32 sa) =20 static void gen_exception(DisasContext *dc, int excp) { - gen_helper_exception(cpu_env, tcg_constant_i32(excp)); + gen_helper_exception(tcg_env, tcg_constant_i32(excp)); } =20 static void gen_exception_cause(DisasContext *dc, uint32_t cause) { TCGv_i32 pc =3D tcg_constant_i32(dc->pc); - gen_helper_exception_cause(cpu_env, pc, tcg_constant_i32(cause)); + gen_helper_exception_cause(tcg_env, pc, tcg_constant_i32(cause)); if (cause =3D=3D ILLEGAL_INSTRUCTION_CAUSE || cause =3D=3D SYSCALL_CAUSE) { dc->base.is_jmp =3D DISAS_NORETURN; @@ -327,7 +327,7 @@ static void gen_exception_cause(DisasContext *dc, uint3= 2_t cause) static void gen_debug_exception(DisasContext *dc, uint32_t cause) { TCGv_i32 pc =3D tcg_constant_i32(dc->pc); - gen_helper_debug_exception(cpu_env, pc, tcg_constant_i32(cause)); + gen_helper_debug_exception(tcg_env, pc, tcg_constant_i32(cause)); if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) { dc->base.is_jmp =3D DISAS_NORETURN; } @@ -536,7 +536,7 @@ static bool gen_window_check(DisasContext *dc, uint32_t= mask) TCGv_i32 pc =3D tcg_constant_i32(dc->pc); TCGv_i32 w =3D tcg_constant_i32(r / 4); =20 - gen_helper_window_check(cpu_env, pc, w); + gen_helper_window_check(tcg_env, pc, w); dc->base.is_jmp =3D DISAS_NORETURN; return false; } @@ -576,11 +576,11 @@ static int gen_postprocess(DisasContext *dc, int slot) #ifndef CONFIG_USER_ONLY if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) { translator_io_start(&dc->base); - gen_helper_check_interrupts(cpu_env); + gen_helper_check_interrupts(tcg_env); } #endif if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) { - gen_helper_sync_windowbase(cpu_env); + gen_helper_sync_windowbase(tcg_env); } if (op_flags & XTENSA_OP_EXIT_TB_M1) { slot =3D -1; @@ -1042,13 +1042,13 @@ static void disas_xtensa_insn(CPUXtensaState *env, = DisasContext *dc) if (op_flags & XTENSA_OP_UNDERFLOW) { TCGv_i32 pc =3D tcg_constant_i32(dc->pc); =20 - gen_helper_test_underflow_retw(cpu_env, pc); + gen_helper_test_underflow_retw(tcg_env, pc); } =20 if (op_flags & XTENSA_OP_ALLOCA) { TCGv_i32 pc =3D tcg_constant_i32(dc->pc); =20 - gen_helper_movsp(cpu_env, pc); + gen_helper_movsp(tcg_env, pc); } =20 if (coprocessor && !gen_check_cpenable(dc, coprocessor)) { @@ -1589,7 +1589,7 @@ static void translate_entry(DisasContext *dc, const O= pcodeArg arg[], TCGv_i32 pc =3D tcg_constant_i32(dc->pc); TCGv_i32 s =3D tcg_constant_i32(arg[0].imm); TCGv_i32 imm =3D tcg_constant_i32(arg[1].imm); - gen_helper_entry(cpu_env, pc, s, imm); + gen_helper_entry(tcg_env, pc, s, imm); } =20 static void translate_extui(DisasContext *dc, const OpcodeArg arg[], @@ -1620,7 +1620,7 @@ static void translate_icache(DisasContext *dc, const = OpcodeArg arg[], =20 tcg_gen_movi_i32(cpu_pc, dc->pc); tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm); - gen_helper_itlb_hit_test(cpu_env, addr); + gen_helper_itlb_hit_test(tcg_env, addr); #endif } =20 @@ -1630,7 +1630,7 @@ static void translate_itlb(DisasContext *dc, const Op= codeArg arg[], #ifndef CONFIG_USER_ONLY TCGv_i32 dtlb =3D tcg_constant_i32(par[0]); =20 - gen_helper_itlb(cpu_env, arg[0].in, dtlb); + gen_helper_itlb(tcg_env, arg[0].in, dtlb); #endif } =20 @@ -1667,7 +1667,7 @@ static void gen_check_exclusive(DisasContext *dc, TCG= v_i32 addr, bool is_write) if (!option_enabled(dc, XTENSA_OPTION_MPU)) { TCGv_i32 pc =3D tcg_constant_i32(dc->pc); =20 - gen_helper_check_exclusive(cpu_env, pc, addr, + gen_helper_check_exclusive(tcg_env, pc, addr, tcg_constant_i32(is_write)); } } @@ -1959,7 +1959,7 @@ static void translate_ptlb(DisasContext *dc, const Op= codeArg arg[], TCGv_i32 dtlb =3D tcg_constant_i32(par[0]); =20 tcg_gen_movi_i32(cpu_pc, dc->pc); - gen_helper_ptlb(arg[0].out, cpu_env, arg[1].in, dtlb); + gen_helper_ptlb(arg[0].out, tcg_env, arg[1].in, dtlb); #endif } =20 @@ -1968,7 +1968,7 @@ static void translate_pptlb(DisasContext *dc, const O= pcodeArg arg[], { #ifndef CONFIG_USER_ONLY tcg_gen_movi_i32(cpu_pc, dc->pc); - gen_helper_pptlb(arg[0].out, cpu_env, arg[1].in); + gen_helper_pptlb(arg[0].out, tcg_env, arg[1].in); #endif } =20 @@ -2020,7 +2020,7 @@ static void translate_remu(DisasContext *dc, const Op= codeArg arg[], static void translate_rer(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_rer(arg[0].out, cpu_env, arg[1].in); + gen_helper_rer(arg[0].out, tcg_env, arg[1].in); } =20 static void translate_ret(DisasContext *dc, const OpcodeArg arg[], @@ -2039,7 +2039,7 @@ static uint32_t test_exceptions_retw(DisasContext *dc= , const OpcodeArg arg[], } else { TCGv_i32 pc =3D tcg_constant_i32(dc->pc); =20 - gen_helper_test_ill_retw(cpu_env, pc); + gen_helper_test_ill_retw(tcg_env, pc); return 0; } } @@ -2053,7 +2053,7 @@ static void translate_retw(DisasContext *dc, const Op= codeArg arg[], cpu_SR[WINDOW_START], tmp); tcg_gen_movi_i32(tmp, dc->pc); tcg_gen_deposit_i32(tmp, tmp, cpu_R[0], 0, 30); - gen_helper_retw(cpu_env, cpu_R[0]); + gen_helper_retw(tcg_env, cpu_R[0]); gen_jump(dc, tmp); } =20 @@ -2093,7 +2093,7 @@ static void translate_rfw(DisasContext *dc, const Opc= odeArg arg[], cpu_SR[WINDOW_START], tmp); } =20 - gen_helper_restore_owb(cpu_env); + gen_helper_restore_owb(tcg_env); gen_jump(dc, cpu_SR[EPC1]); } =20 @@ -2126,7 +2126,7 @@ static void translate_rsr_ccount(DisasContext *dc, co= nst OpcodeArg arg[], { #ifndef CONFIG_USER_ONLY translator_io_start(&dc->base); - gen_helper_update_ccount(cpu_env); + gen_helper_update_ccount(tcg_env); tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); #endif } @@ -2154,7 +2154,7 @@ static void translate_rtlb(DisasContext *dc, const Op= codeArg arg[], }; TCGv_i32 dtlb =3D tcg_constant_i32(par[0]); =20 - helper[par[1]](arg[0].out, cpu_env, arg[1].in, dtlb); + helper[par[1]](arg[0].out, tcg_env, arg[1].in, dtlb); #endif } =20 @@ -2162,7 +2162,7 @@ static void translate_rptlb0(DisasContext *dc, const = OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY - gen_helper_rptlb0(arg[0].out, cpu_env, arg[1].in); + gen_helper_rptlb0(arg[0].out, tcg_env, arg[1].in); #endif } =20 @@ -2170,7 +2170,7 @@ static void translate_rptlb1(DisasContext *dc, const = OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY - gen_helper_rptlb1(arg[0].out, cpu_env, arg[1].in); + gen_helper_rptlb1(arg[0].out, tcg_env, arg[1].in); #endif } =20 @@ -2196,7 +2196,7 @@ static void gen_check_atomctl(DisasContext *dc, TCGv_= i32 addr) { TCGv_i32 pc =3D tcg_constant_i32(dc->pc); =20 - gen_helper_check_atomctl(cpu_env, pc, addr); + gen_helper_check_atomctl(tcg_env, pc, addr); } #endif =20 @@ -2297,7 +2297,7 @@ static void translate_simcall(DisasContext *dc, const= OpcodeArg arg[], { #ifndef CONFIG_USER_ONLY if (semihosting_enabled(dc->cring !=3D 0)) { - gen_helper_simcall(cpu_env); + gen_helper_simcall(tcg_env); } #endif } @@ -2442,7 +2442,7 @@ static void translate_waiti(DisasContext *dc, const O= pcodeArg arg[], TCGv_i32 pc =3D tcg_constant_i32(dc->base.pc_next); =20 translator_io_start(&dc->base); - gen_helper_waiti(cpu_env, pc, tcg_constant_i32(arg[0].imm)); + gen_helper_waiti(tcg_env, pc, tcg_constant_i32(arg[0].imm)); #endif } =20 @@ -2452,7 +2452,7 @@ static void translate_wtlb(DisasContext *dc, const Op= codeArg arg[], #ifndef CONFIG_USER_ONLY TCGv_i32 dtlb =3D tcg_constant_i32(par[0]); =20 - gen_helper_wtlb(cpu_env, arg[0].in, arg[1].in, dtlb); + gen_helper_wtlb(tcg_env, arg[0].in, arg[1].in, dtlb); #endif } =20 @@ -2460,14 +2460,14 @@ static void translate_wptlb(DisasContext *dc, const= OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY - gen_helper_wptlb(cpu_env, arg[0].in, arg[1].in); + gen_helper_wptlb(tcg_env, arg[0].in, arg[1].in); #endif } =20 static void translate_wer(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_wer(cpu_env, arg[0].in, arg[1].in); + gen_helper_wer(tcg_env, arg[0].in, arg[1].in); } =20 static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg= [], @@ -2508,7 +2508,7 @@ static void translate_wsr_ccompare(DisasContext *dc, = const OpcodeArg arg[], assert(id < dc->config->nccompare); translator_io_start(&dc->base); tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in); - gen_helper_update_ccompare(cpu_env, tcg_constant_i32(id)); + gen_helper_update_ccompare(tcg_env, tcg_constant_i32(id)); #endif } =20 @@ -2517,7 +2517,7 @@ static void translate_wsr_ccount(DisasContext *dc, co= nst OpcodeArg arg[], { #ifndef CONFIG_USER_ONLY translator_io_start(&dc->base); - gen_helper_wsr_ccount(cpu_env, arg[0].in); + gen_helper_wsr_ccount(tcg_env, arg[0].in); #endif } =20 @@ -2528,7 +2528,7 @@ static void translate_wsr_dbreaka(DisasContext *dc, c= onst OpcodeArg arg[], unsigned id =3D par[0] - DBREAKA; =20 assert(id < dc->config->ndbreak); - gen_helper_wsr_dbreaka(cpu_env, tcg_constant_i32(id), arg[0].in); + gen_helper_wsr_dbreaka(tcg_env, tcg_constant_i32(id), arg[0].in); #endif } =20 @@ -2539,7 +2539,7 @@ static void translate_wsr_dbreakc(DisasContext *dc, c= onst OpcodeArg arg[], unsigned id =3D par[0] - DBREAKC; =20 assert(id < dc->config->ndbreak); - gen_helper_wsr_dbreakc(cpu_env, tcg_constant_i32(id), arg[0].in); + gen_helper_wsr_dbreakc(tcg_env, tcg_constant_i32(id), arg[0].in); #endif } =20 @@ -2550,7 +2550,7 @@ static void translate_wsr_ibreaka(DisasContext *dc, c= onst OpcodeArg arg[], unsigned id =3D par[0] - IBREAKA; =20 assert(id < dc->config->nibreak); - gen_helper_wsr_ibreaka(cpu_env, tcg_constant_i32(id), arg[0].in); + gen_helper_wsr_ibreaka(tcg_env, tcg_constant_i32(id), arg[0].in); #endif } =20 @@ -2558,7 +2558,7 @@ static void translate_wsr_ibreakenable(DisasContext *= dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY - gen_helper_wsr_ibreakenable(cpu_env, arg[0].in); + gen_helper_wsr_ibreakenable(tcg_env, arg[0].in); #endif } =20 @@ -2578,7 +2578,7 @@ static void translate_wsr_intclear(DisasContext *dc, = const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY - gen_helper_intclear(cpu_env, arg[0].in); + gen_helper_intclear(tcg_env, arg[0].in); #endif } =20 @@ -2586,7 +2586,7 @@ static void translate_wsr_intset(DisasContext *dc, co= nst OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY - gen_helper_intset(cpu_env, arg[0].in); + gen_helper_intset(tcg_env, arg[0].in); #endif } =20 @@ -2594,7 +2594,7 @@ static void translate_wsr_memctl(DisasContext *dc, co= nst OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY - gen_helper_wsr_memctl(cpu_env, arg[0].in); + gen_helper_wsr_memctl(tcg_env, arg[0].in); #endif } =20 @@ -2602,7 +2602,7 @@ static void translate_wsr_mpuenb(DisasContext *dc, co= nst OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY - gen_helper_wsr_mpuenb(cpu_env, arg[0].in); + gen_helper_wsr_mpuenb(tcg_env, arg[0].in); #endif } =20 @@ -2625,7 +2625,7 @@ static void translate_wsr_rasid(DisasContext *dc, con= st OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY - gen_helper_wsr_rasid(cpu_env, arg[0].in); + gen_helper_wsr_rasid(tcg_env, arg[0].in); #endif } =20 @@ -2704,9 +2704,9 @@ static void translate_xsr_ccount(DisasContext *dc, co= nst OpcodeArg arg[], TCGv_i32 tmp =3D tcg_temp_new_i32(); =20 translator_io_start(&dc->base); - gen_helper_update_ccount(cpu_env); + gen_helper_update_ccount(tcg_env); tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); - gen_helper_wsr_ccount(cpu_env, arg[0].in); + gen_helper_wsr_ccount(tcg_env, arg[0].in); tcg_gen_mov_i32(arg[0].out, tmp); =20 #endif @@ -6295,7 +6295,7 @@ static void translate_abs_s(DisasContext *dc, const O= pcodeArg arg[], static void translate_fpu2k_add_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_fpu2k_add_s(arg[0].out, cpu_env, + gen_helper_fpu2k_add_s(arg[0].out, tcg_env, arg[1].in, arg[2].in); } =20 @@ -6330,7 +6330,7 @@ static void translate_compare_d(DisasContext *dc, con= st OpcodeArg arg[], tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm); tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm)); =20 - helper[par[0]](res, cpu_env, arg[1].in, arg[2].in); + helper[par[0]](res, tcg_env, arg[1].in, arg[2].in); tcg_gen_movcond_i32(TCG_COND_NE, arg[0].out, res, zero, set_br, clr_br); @@ -6359,7 +6359,7 @@ static void translate_compare_s(DisasContext *dc, con= st OpcodeArg arg[], tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm)); =20 get_f32_i2(arg, arg32, 1, 2); - helper[par[0]](res, cpu_env, arg32[1].in, arg32[2].in); + helper[par[0]](res, tcg_env, arg32[1].in, arg32[2].in); tcg_gen_movcond_i32(TCG_COND_NE, arg[0].out, res, zero, set_br, clr_br); @@ -6412,9 +6412,9 @@ static void translate_float_d(DisasContext *dc, const= OpcodeArg arg[], TCGv_i32 scale =3D tcg_constant_i32(-arg[2].imm); =20 if (par[0]) { - gen_helper_uitof_d(arg[0].out, cpu_env, arg[1].in, scale); + gen_helper_uitof_d(arg[0].out, tcg_env, arg[1].in, scale); } else { - gen_helper_itof_d(arg[0].out, cpu_env, arg[1].in, scale); + gen_helper_itof_d(arg[0].out, tcg_env, arg[1].in, scale); } } =20 @@ -6426,9 +6426,9 @@ static void translate_float_s(DisasContext *dc, const= OpcodeArg arg[], =20 get_f32_o1(arg, arg32, 0); if (par[0]) { - gen_helper_uitof_s(arg32[0].out, cpu_env, arg[1].in, scale); + gen_helper_uitof_s(arg32[0].out, tcg_env, arg[1].in, scale); } else { - gen_helper_itof_s(arg32[0].out, cpu_env, arg[1].in, scale); + gen_helper_itof_s(arg32[0].out, tcg_env, arg[1].in, scale); } put_f32_o1(arg, arg32, 0); } @@ -6440,10 +6440,10 @@ static void translate_ftoi_d(DisasContext *dc, cons= t OpcodeArg arg[], TCGv_i32 scale =3D tcg_constant_i32(arg[2].imm); =20 if (par[1]) { - gen_helper_ftoui_d(arg[0].out, cpu_env, arg[1].in, + gen_helper_ftoui_d(arg[0].out, tcg_env, arg[1].in, rounding_mode, scale); } else { - gen_helper_ftoi_d(arg[0].out, cpu_env, arg[1].in, + gen_helper_ftoi_d(arg[0].out, tcg_env, arg[1].in, rounding_mode, scale); } } @@ -6457,10 +6457,10 @@ static void translate_ftoi_s(DisasContext *dc, cons= t OpcodeArg arg[], =20 get_f32_i1(arg, arg32, 1); if (par[1]) { - gen_helper_ftoui_s(arg[0].out, cpu_env, arg32[1].in, + gen_helper_ftoui_s(arg[0].out, tcg_env, arg32[1].in, rounding_mode, scale); } else { - gen_helper_ftoi_s(arg[0].out, cpu_env, arg32[1].in, + gen_helper_ftoi_s(arg[0].out, tcg_env, arg32[1].in, rounding_mode, scale); } put_f32_i1(arg, arg32, 1); @@ -6505,7 +6505,7 @@ static void translate_ldstx(DisasContext *dc, const O= pcodeArg arg[], static void translate_fpu2k_madd_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_fpu2k_madd_s(arg[0].out, cpu_env, + gen_helper_fpu2k_madd_s(arg[0].out, tcg_env, arg[0].in, arg[1].in, arg[2].in); } =20 @@ -6584,14 +6584,14 @@ static void translate_movp_s(DisasContext *dc, cons= t OpcodeArg arg[], static void translate_fpu2k_mul_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_fpu2k_mul_s(arg[0].out, cpu_env, + gen_helper_fpu2k_mul_s(arg[0].out, tcg_env, arg[1].in, arg[2].in); } =20 static void translate_fpu2k_msub_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_fpu2k_msub_s(arg[0].out, cpu_env, + gen_helper_fpu2k_msub_s(arg[0].out, tcg_env, arg[0].in, arg[1].in, arg[2].in); } =20 @@ -6630,7 +6630,7 @@ static void translate_rfr_s(DisasContext *dc, const O= pcodeArg arg[], static void translate_fpu2k_sub_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_fpu2k_sub_s(arg[0].out, cpu_env, + gen_helper_fpu2k_sub_s(arg[0].out, tcg_env, arg[1].in, arg[2].in); } =20 @@ -6653,7 +6653,7 @@ static void translate_wfr_s(DisasContext *dc, const O= pcodeArg arg[], static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[= ], const uint32_t par[]) { - gen_helper_wur_fpu2k_fcr(cpu_env, arg[0].in); + gen_helper_wur_fpu2k_fcr(tcg_env, arg[0].in); } =20 static void translate_wur_fpu2k_fsr(DisasContext *dc, const OpcodeArg arg[= ], @@ -6882,20 +6882,20 @@ const XtensaOpcodeTranslators xtensa_fpu2000_opcode= s =3D { static void translate_add_d(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_add_d(arg[0].out, cpu_env, arg[1].in, arg[2].in); + gen_helper_add_d(arg[0].out, tcg_env, arg[1].in, arg[2].in); } =20 static void translate_add_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { - gen_helper_fpu2k_add_s(arg[0].out, cpu_env, + gen_helper_fpu2k_add_s(arg[0].out, tcg_env, arg[1].in, arg[2].in); } else { OpcodeArg arg32[3]; =20 get_f32_o1_i2(arg, arg32, 0, 1, 2); - gen_helper_add_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in); + gen_helper_add_s(arg32[0].out, tcg_env, arg32[1].in, arg32[2].in); put_f32_o1_i2(arg, arg32, 0, 1, 2); } } @@ -6906,7 +6906,7 @@ static void translate_cvtd_s(DisasContext *dc, const = OpcodeArg arg[], TCGv_i32 v =3D tcg_temp_new_i32(); =20 tcg_gen_extrl_i64_i32(v, arg[1].in); - gen_helper_cvtd_s(arg[0].out, cpu_env, v); + gen_helper_cvtd_s(arg[0].out, tcg_env, v); } =20 static void translate_cvts_d(DisasContext *dc, const OpcodeArg arg[], @@ -6914,7 +6914,7 @@ static void translate_cvts_d(DisasContext *dc, const = OpcodeArg arg[], { TCGv_i32 v =3D tcg_temp_new_i32(); =20 - gen_helper_cvts_d(v, cpu_env, arg[1].in); + gen_helper_cvts_d(v, tcg_env, arg[1].in); tcg_gen_extu_i32_i64(arg[0].out, v); } =20 @@ -7039,7 +7039,7 @@ static void translate_ldstx_s(DisasContext *dc, const= OpcodeArg arg[], static void translate_madd_d(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_madd_d(arg[0].out, cpu_env, + gen_helper_madd_d(arg[0].out, tcg_env, arg[0].in, arg[1].in, arg[2].in); } =20 @@ -7047,13 +7047,13 @@ static void translate_madd_s(DisasContext *dc, cons= t OpcodeArg arg[], const uint32_t par[]) { if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { - gen_helper_fpu2k_madd_s(arg[0].out, cpu_env, + gen_helper_fpu2k_madd_s(arg[0].out, tcg_env, arg[0].in, arg[1].in, arg[2].in); } else { OpcodeArg arg32[3]; =20 get_f32_o1_i3(arg, arg32, 0, 0, 1, 2); - gen_helper_madd_s(arg32[0].out, cpu_env, + gen_helper_madd_s(arg32[0].out, tcg_env, arg32[0].in, arg32[1].in, arg32[2].in); put_f32_o1_i3(arg, arg32, 0, 0, 1, 2); } @@ -7062,20 +7062,20 @@ static void translate_madd_s(DisasContext *dc, cons= t OpcodeArg arg[], static void translate_mul_d(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_mul_d(arg[0].out, cpu_env, arg[1].in, arg[2].in); + gen_helper_mul_d(arg[0].out, tcg_env, arg[1].in, arg[2].in); } =20 static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { - gen_helper_fpu2k_mul_s(arg[0].out, cpu_env, + gen_helper_fpu2k_mul_s(arg[0].out, tcg_env, arg[1].in, arg[2].in); } else { OpcodeArg arg32[3]; =20 get_f32_o1_i2(arg, arg32, 0, 1, 2); - gen_helper_mul_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in); + gen_helper_mul_s(arg32[0].out, tcg_env, arg32[1].in, arg32[2].in); put_f32_o1_i2(arg, arg32, 0, 1, 2); } } @@ -7083,7 +7083,7 @@ static void translate_mul_s(DisasContext *dc, const O= pcodeArg arg[], static void translate_msub_d(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_msub_d(arg[0].out, cpu_env, + gen_helper_msub_d(arg[0].out, tcg_env, arg[0].in, arg[1].in, arg[2].in); } =20 @@ -7091,13 +7091,13 @@ static void translate_msub_s(DisasContext *dc, cons= t OpcodeArg arg[], const uint32_t par[]) { if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { - gen_helper_fpu2k_msub_s(arg[0].out, cpu_env, + gen_helper_fpu2k_msub_s(arg[0].out, tcg_env, arg[0].in, arg[1].in, arg[2].in); } else { OpcodeArg arg32[3]; =20 get_f32_o1_i3(arg, arg32, 0, 0, 1, 2); - gen_helper_msub_s(arg32[0].out, cpu_env, + gen_helper_msub_s(arg32[0].out, tcg_env, arg32[0].in, arg32[1].in, arg32[2].in); put_f32_o1_i3(arg, arg32, 0, 0, 1, 2); } @@ -7106,20 +7106,20 @@ static void translate_msub_s(DisasContext *dc, cons= t OpcodeArg arg[], static void translate_sub_d(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_sub_d(arg[0].out, cpu_env, arg[1].in, arg[2].in); + gen_helper_sub_d(arg[0].out, tcg_env, arg[1].in, arg[2].in); } =20 static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { - gen_helper_fpu2k_sub_s(arg[0].out, cpu_env, + gen_helper_fpu2k_sub_s(arg[0].out, tcg_env, arg[1].in, arg[2].in); } else { OpcodeArg arg32[3]; =20 get_f32_o1_i2(arg, arg32, 0, 1, 2); - gen_helper_sub_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in); + gen_helper_sub_s(arg32[0].out, tcg_env, arg32[1].in, arg32[2].in); put_f32_o1_i2(arg, arg32, 0, 1, 2); } } @@ -7127,7 +7127,7 @@ static void translate_sub_s(DisasContext *dc, const O= pcodeArg arg[], static void translate_mkdadj_d(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_mkdadj_d(arg[0].out, cpu_env, arg[0].in, arg[1].in); + gen_helper_mkdadj_d(arg[0].out, tcg_env, arg[0].in, arg[1].in); } =20 static void translate_mkdadj_s(DisasContext *dc, const OpcodeArg arg[], @@ -7136,14 +7136,14 @@ static void translate_mkdadj_s(DisasContext *dc, co= nst OpcodeArg arg[], OpcodeArg arg32[2]; =20 get_f32_o1_i2(arg, arg32, 0, 0, 1); - gen_helper_mkdadj_s(arg32[0].out, cpu_env, arg32[0].in, arg32[1].in); + gen_helper_mkdadj_s(arg32[0].out, tcg_env, arg32[0].in, arg32[1].in); put_f32_o1_i2(arg, arg32, 0, 0, 1); } =20 static void translate_mksadj_d(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_mksadj_d(arg[0].out, cpu_env, arg[1].in); + gen_helper_mksadj_d(arg[0].out, tcg_env, arg[1].in); } =20 static void translate_mksadj_s(DisasContext *dc, const OpcodeArg arg[], @@ -7152,26 +7152,26 @@ static void translate_mksadj_s(DisasContext *dc, co= nst OpcodeArg arg[], OpcodeArg arg32[2]; =20 get_f32_o1_i1(arg, arg32, 0, 1); - gen_helper_mksadj_s(arg32[0].out, cpu_env, arg32[1].in); + gen_helper_mksadj_s(arg32[0].out, tcg_env, arg32[1].in); put_f32_o1_i1(arg, arg32, 0, 1); } =20 static void translate_wur_fpu_fcr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_wur_fpu_fcr(cpu_env, arg[0].in); + gen_helper_wur_fpu_fcr(tcg_env, arg[0].in); } =20 static void translate_rur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_rur_fpu_fsr(arg[0].out, cpu_env); + gen_helper_rur_fpu_fsr(arg[0].out, tcg_env); } =20 static void translate_wur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_wur_fpu_fsr(cpu_env, arg[0].in); + gen_helper_wur_fpu_fsr(tcg_env, arg[0].in); } =20 static const XtensaOpcodeOps fpu_ops[] =3D { diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 41b1ae18e4..feb2d3686b 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -120,8 +120,8 @@ void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs, a0 =3D tcg_temp_ebb_new_ptr(); a1 =3D tcg_temp_ebb_new_ptr(); =20 - tcg_gen_addi_ptr(a0, cpu_env, dofs); - tcg_gen_addi_ptr(a1, cpu_env, aofs); + tcg_gen_addi_ptr(a0, tcg_env, dofs); + tcg_gen_addi_ptr(a1, tcg_env, aofs); =20 fn(a0, a1, desc); =20 @@ -141,8 +141,8 @@ void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, = TCGv_i64 c, a0 =3D tcg_temp_ebb_new_ptr(); a1 =3D tcg_temp_ebb_new_ptr(); =20 - tcg_gen_addi_ptr(a0, cpu_env, dofs); - tcg_gen_addi_ptr(a1, cpu_env, aofs); + tcg_gen_addi_ptr(a0, tcg_env, dofs); + tcg_gen_addi_ptr(a1, tcg_env, aofs); =20 fn(a0, a1, c, desc); =20 @@ -162,9 +162,9 @@ void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, u= int32_t bofs, a1 =3D tcg_temp_ebb_new_ptr(); a2 =3D tcg_temp_ebb_new_ptr(); =20 - tcg_gen_addi_ptr(a0, cpu_env, dofs); - tcg_gen_addi_ptr(a1, cpu_env, aofs); - tcg_gen_addi_ptr(a2, cpu_env, bofs); + tcg_gen_addi_ptr(a0, tcg_env, dofs); + tcg_gen_addi_ptr(a1, tcg_env, aofs); + tcg_gen_addi_ptr(a2, tcg_env, bofs); =20 fn(a0, a1, a2, desc); =20 @@ -186,10 +186,10 @@ void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs,= uint32_t bofs, a2 =3D tcg_temp_ebb_new_ptr(); a3 =3D tcg_temp_ebb_new_ptr(); =20 - tcg_gen_addi_ptr(a0, cpu_env, dofs); - tcg_gen_addi_ptr(a1, cpu_env, aofs); - tcg_gen_addi_ptr(a2, cpu_env, bofs); - tcg_gen_addi_ptr(a3, cpu_env, cofs); + tcg_gen_addi_ptr(a0, tcg_env, dofs); + tcg_gen_addi_ptr(a1, tcg_env, aofs); + tcg_gen_addi_ptr(a2, tcg_env, bofs); + tcg_gen_addi_ptr(a3, tcg_env, cofs); =20 fn(a0, a1, a2, a3, desc); =20 @@ -213,11 +213,11 @@ void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs,= uint32_t bofs, a3 =3D tcg_temp_ebb_new_ptr(); a4 =3D tcg_temp_ebb_new_ptr(); =20 - tcg_gen_addi_ptr(a0, cpu_env, dofs); - tcg_gen_addi_ptr(a1, cpu_env, aofs); - tcg_gen_addi_ptr(a2, cpu_env, bofs); - tcg_gen_addi_ptr(a3, cpu_env, cofs); - tcg_gen_addi_ptr(a4, cpu_env, xofs); + tcg_gen_addi_ptr(a0, tcg_env, dofs); + tcg_gen_addi_ptr(a1, tcg_env, aofs); + tcg_gen_addi_ptr(a2, tcg_env, bofs); + tcg_gen_addi_ptr(a3, tcg_env, cofs); + tcg_gen_addi_ptr(a4, tcg_env, xofs); =20 fn(a0, a1, a2, a3, a4, desc); =20 @@ -240,8 +240,8 @@ void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs, a0 =3D tcg_temp_ebb_new_ptr(); a1 =3D tcg_temp_ebb_new_ptr(); =20 - tcg_gen_addi_ptr(a0, cpu_env, dofs); - tcg_gen_addi_ptr(a1, cpu_env, aofs); + tcg_gen_addi_ptr(a0, tcg_env, dofs); + tcg_gen_addi_ptr(a1, tcg_env, aofs); =20 fn(a0, a1, ptr, desc); =20 @@ -262,9 +262,9 @@ void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, u= int32_t bofs, a1 =3D tcg_temp_ebb_new_ptr(); a2 =3D tcg_temp_ebb_new_ptr(); =20 - tcg_gen_addi_ptr(a0, cpu_env, dofs); - tcg_gen_addi_ptr(a1, cpu_env, aofs); - tcg_gen_addi_ptr(a2, cpu_env, bofs); + tcg_gen_addi_ptr(a0, tcg_env, dofs); + tcg_gen_addi_ptr(a1, tcg_env, aofs); + tcg_gen_addi_ptr(a2, tcg_env, bofs); =20 fn(a0, a1, a2, ptr, desc); =20 @@ -288,10 +288,10 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs,= uint32_t bofs, a2 =3D tcg_temp_ebb_new_ptr(); a3 =3D tcg_temp_ebb_new_ptr(); =20 - tcg_gen_addi_ptr(a0, cpu_env, dofs); - tcg_gen_addi_ptr(a1, cpu_env, aofs); - tcg_gen_addi_ptr(a2, cpu_env, bofs); - tcg_gen_addi_ptr(a3, cpu_env, cofs); + tcg_gen_addi_ptr(a0, tcg_env, dofs); + tcg_gen_addi_ptr(a1, tcg_env, aofs); + tcg_gen_addi_ptr(a2, tcg_env, bofs); + tcg_gen_addi_ptr(a3, tcg_env, cofs); =20 fn(a0, a1, a2, a3, ptr, desc); =20 @@ -317,11 +317,11 @@ void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs,= uint32_t bofs, a3 =3D tcg_temp_ebb_new_ptr(); a4 =3D tcg_temp_ebb_new_ptr(); =20 - tcg_gen_addi_ptr(a0, cpu_env, dofs); - tcg_gen_addi_ptr(a1, cpu_env, aofs); - tcg_gen_addi_ptr(a2, cpu_env, bofs); - tcg_gen_addi_ptr(a3, cpu_env, cofs); - tcg_gen_addi_ptr(a4, cpu_env, eofs); + tcg_gen_addi_ptr(a0, tcg_env, dofs); + tcg_gen_addi_ptr(a1, tcg_env, aofs); + tcg_gen_addi_ptr(a2, tcg_env, bofs); + tcg_gen_addi_ptr(a3, tcg_env, cofs); + tcg_gen_addi_ptr(a4, tcg_env, eofs); =20 fn(a0, a1, a2, a3, a4, ptr, desc); =20 @@ -482,7 +482,7 @@ static void do_dup_store(TCGType type, uint32_t dofs, u= int32_t oprsz, * are misaligned wrt the maximum vector size, so do that first. */ if (dofs & 8) { - tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); + tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V64); i +=3D 8; } =20 @@ -494,17 +494,17 @@ static void do_dup_store(TCGType type, uint32_t dofs,= uint32_t oprsz, * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. */ for (; i + 32 <=3D oprsz; i +=3D 32) { - tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256); + tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V256); } /* fallthru */ case TCG_TYPE_V128: for (; i + 16 <=3D oprsz; i +=3D 16) { - tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128); + tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V128); } break; case TCG_TYPE_V64: for (; i < oprsz; i +=3D 8) { - tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); + tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V64); } break; default: @@ -605,14 +605,14 @@ static void do_dup(unsigned vece, uint32_t dofs, uint= 32_t oprsz, /* Implement inline if we picked an implementation size above. */ if (t_32) { for (i =3D 0; i < oprsz; i +=3D 4) { - tcg_gen_st_i32(t_32, cpu_env, dofs + i); + tcg_gen_st_i32(t_32, tcg_env, dofs + i); } tcg_temp_free_i32(t_32); goto done; } if (t_64) { for (i =3D 0; i < oprsz; i +=3D 8) { - tcg_gen_st_i64(t_64, cpu_env, dofs + i); + tcg_gen_st_i64(t_64, tcg_env, dofs + i); } tcg_temp_free_i64(t_64); goto done; @@ -621,7 +621,7 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32= _t oprsz, =20 /* Otherwise implement out of line. */ t_ptr =3D tcg_temp_ebb_new_ptr(); - tcg_gen_addi_ptr(t_ptr, cpu_env, dofs); + tcg_gen_addi_ptr(t_ptr, tcg_env, dofs); =20 /* * This may be expand_clr for the tail of an operation, e.g. @@ -709,12 +709,12 @@ static void expand_2_i32(uint32_t dofs, uint32_t aofs= , uint32_t oprsz, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 4) { - tcg_gen_ld_i32(t0, cpu_env, aofs + i); + tcg_gen_ld_i32(t0, tcg_env, aofs + i); if (load_dest) { - tcg_gen_ld_i32(t1, cpu_env, dofs + i); + tcg_gen_ld_i32(t1, tcg_env, dofs + i); } fni(t1, t0); - tcg_gen_st_i32(t1, cpu_env, dofs + i); + tcg_gen_st_i32(t1, tcg_env, dofs + i); } tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); @@ -729,12 +729,12 @@ static void expand_2i_i32(uint32_t dofs, uint32_t aof= s, uint32_t oprsz, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 4) { - tcg_gen_ld_i32(t0, cpu_env, aofs + i); + tcg_gen_ld_i32(t0, tcg_env, aofs + i); if (load_dest) { - tcg_gen_ld_i32(t1, cpu_env, dofs + i); + tcg_gen_ld_i32(t1, tcg_env, dofs + i); } fni(t1, t0, c); - tcg_gen_st_i32(t1, cpu_env, dofs + i); + tcg_gen_st_i32(t1, tcg_env, dofs + i); } tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); @@ -749,13 +749,13 @@ static void expand_2s_i32(uint32_t dofs, uint32_t aof= s, uint32_t oprsz, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 4) { - tcg_gen_ld_i32(t0, cpu_env, aofs + i); + tcg_gen_ld_i32(t0, tcg_env, aofs + i); if (scalar_first) { fni(t1, c, t0); } else { fni(t1, t0, c); } - tcg_gen_st_i32(t1, cpu_env, dofs + i); + tcg_gen_st_i32(t1, tcg_env, dofs + i); } tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); @@ -772,13 +772,13 @@ static void expand_3_i32(uint32_t dofs, uint32_t aofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 4) { - tcg_gen_ld_i32(t0, cpu_env, aofs + i); - tcg_gen_ld_i32(t1, cpu_env, bofs + i); + tcg_gen_ld_i32(t0, tcg_env, aofs + i); + tcg_gen_ld_i32(t1, tcg_env, bofs + i); if (load_dest) { - tcg_gen_ld_i32(t2, cpu_env, dofs + i); + tcg_gen_ld_i32(t2, tcg_env, dofs + i); } fni(t2, t0, t1); - tcg_gen_st_i32(t2, cpu_env, dofs + i); + tcg_gen_st_i32(t2, tcg_env, dofs + i); } tcg_temp_free_i32(t2); tcg_temp_free_i32(t1); @@ -795,13 +795,13 @@ static void expand_3i_i32(uint32_t dofs, uint32_t aof= s, uint32_t bofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 4) { - tcg_gen_ld_i32(t0, cpu_env, aofs + i); - tcg_gen_ld_i32(t1, cpu_env, bofs + i); + tcg_gen_ld_i32(t0, tcg_env, aofs + i); + tcg_gen_ld_i32(t1, tcg_env, bofs + i); if (load_dest) { - tcg_gen_ld_i32(t2, cpu_env, dofs + i); + tcg_gen_ld_i32(t2, tcg_env, dofs + i); } fni(t2, t0, t1, c); - tcg_gen_st_i32(t2, cpu_env, dofs + i); + tcg_gen_st_i32(t2, tcg_env, dofs + i); } tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); @@ -820,13 +820,13 @@ static void expand_4_i32(uint32_t dofs, uint32_t aofs= , uint32_t bofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 4) { - tcg_gen_ld_i32(t1, cpu_env, aofs + i); - tcg_gen_ld_i32(t2, cpu_env, bofs + i); - tcg_gen_ld_i32(t3, cpu_env, cofs + i); + tcg_gen_ld_i32(t1, tcg_env, aofs + i); + tcg_gen_ld_i32(t2, tcg_env, bofs + i); + tcg_gen_ld_i32(t3, tcg_env, cofs + i); fni(t0, t1, t2, t3); - tcg_gen_st_i32(t0, cpu_env, dofs + i); + tcg_gen_st_i32(t0, tcg_env, dofs + i); if (write_aofs) { - tcg_gen_st_i32(t1, cpu_env, aofs + i); + tcg_gen_st_i32(t1, tcg_env, aofs + i); } } tcg_temp_free_i32(t3); @@ -847,11 +847,11 @@ static void expand_4i_i32(uint32_t dofs, uint32_t aof= s, uint32_t bofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 4) { - tcg_gen_ld_i32(t1, cpu_env, aofs + i); - tcg_gen_ld_i32(t2, cpu_env, bofs + i); - tcg_gen_ld_i32(t3, cpu_env, cofs + i); + tcg_gen_ld_i32(t1, tcg_env, aofs + i); + tcg_gen_ld_i32(t2, tcg_env, bofs + i); + tcg_gen_ld_i32(t3, tcg_env, cofs + i); fni(t0, t1, t2, t3, c); - tcg_gen_st_i32(t0, cpu_env, dofs + i); + tcg_gen_st_i32(t0, tcg_env, dofs + i); } tcg_temp_free_i32(t3); tcg_temp_free_i32(t2); @@ -868,12 +868,12 @@ static void expand_2_i64(uint32_t dofs, uint32_t aofs= , uint32_t oprsz, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 8) { - tcg_gen_ld_i64(t0, cpu_env, aofs + i); + tcg_gen_ld_i64(t0, tcg_env, aofs + i); if (load_dest) { - tcg_gen_ld_i64(t1, cpu_env, dofs + i); + tcg_gen_ld_i64(t1, tcg_env, dofs + i); } fni(t1, t0); - tcg_gen_st_i64(t1, cpu_env, dofs + i); + tcg_gen_st_i64(t1, tcg_env, dofs + i); } tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); @@ -888,12 +888,12 @@ static void expand_2i_i64(uint32_t dofs, uint32_t aof= s, uint32_t oprsz, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 8) { - tcg_gen_ld_i64(t0, cpu_env, aofs + i); + tcg_gen_ld_i64(t0, tcg_env, aofs + i); if (load_dest) { - tcg_gen_ld_i64(t1, cpu_env, dofs + i); + tcg_gen_ld_i64(t1, tcg_env, dofs + i); } fni(t1, t0, c); - tcg_gen_st_i64(t1, cpu_env, dofs + i); + tcg_gen_st_i64(t1, tcg_env, dofs + i); } tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); @@ -908,13 +908,13 @@ static void expand_2s_i64(uint32_t dofs, uint32_t aof= s, uint32_t oprsz, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 8) { - tcg_gen_ld_i64(t0, cpu_env, aofs + i); + tcg_gen_ld_i64(t0, tcg_env, aofs + i); if (scalar_first) { fni(t1, c, t0); } else { fni(t1, t0, c); } - tcg_gen_st_i64(t1, cpu_env, dofs + i); + tcg_gen_st_i64(t1, tcg_env, dofs + i); } tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); @@ -931,13 +931,13 @@ static void expand_3_i64(uint32_t dofs, uint32_t aofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 8) { - tcg_gen_ld_i64(t0, cpu_env, aofs + i); - tcg_gen_ld_i64(t1, cpu_env, bofs + i); + tcg_gen_ld_i64(t0, tcg_env, aofs + i); + tcg_gen_ld_i64(t1, tcg_env, bofs + i); if (load_dest) { - tcg_gen_ld_i64(t2, cpu_env, dofs + i); + tcg_gen_ld_i64(t2, tcg_env, dofs + i); } fni(t2, t0, t1); - tcg_gen_st_i64(t2, cpu_env, dofs + i); + tcg_gen_st_i64(t2, tcg_env, dofs + i); } tcg_temp_free_i64(t2); tcg_temp_free_i64(t1); @@ -954,13 +954,13 @@ static void expand_3i_i64(uint32_t dofs, uint32_t aof= s, uint32_t bofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 8) { - tcg_gen_ld_i64(t0, cpu_env, aofs + i); - tcg_gen_ld_i64(t1, cpu_env, bofs + i); + tcg_gen_ld_i64(t0, tcg_env, aofs + i); + tcg_gen_ld_i64(t1, tcg_env, bofs + i); if (load_dest) { - tcg_gen_ld_i64(t2, cpu_env, dofs + i); + tcg_gen_ld_i64(t2, tcg_env, dofs + i); } fni(t2, t0, t1, c); - tcg_gen_st_i64(t2, cpu_env, dofs + i); + tcg_gen_st_i64(t2, tcg_env, dofs + i); } tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); @@ -979,13 +979,13 @@ static void expand_4_i64(uint32_t dofs, uint32_t aofs= , uint32_t bofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 8) { - tcg_gen_ld_i64(t1, cpu_env, aofs + i); - tcg_gen_ld_i64(t2, cpu_env, bofs + i); - tcg_gen_ld_i64(t3, cpu_env, cofs + i); + tcg_gen_ld_i64(t1, tcg_env, aofs + i); + tcg_gen_ld_i64(t2, tcg_env, bofs + i); + tcg_gen_ld_i64(t3, tcg_env, cofs + i); fni(t0, t1, t2, t3); - tcg_gen_st_i64(t0, cpu_env, dofs + i); + tcg_gen_st_i64(t0, tcg_env, dofs + i); if (write_aofs) { - tcg_gen_st_i64(t1, cpu_env, aofs + i); + tcg_gen_st_i64(t1, tcg_env, aofs + i); } } tcg_temp_free_i64(t3); @@ -1006,11 +1006,11 @@ static void expand_4i_i64(uint32_t dofs, uint32_t a= ofs, uint32_t bofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 8) { - tcg_gen_ld_i64(t1, cpu_env, aofs + i); - tcg_gen_ld_i64(t2, cpu_env, bofs + i); - tcg_gen_ld_i64(t3, cpu_env, cofs + i); + tcg_gen_ld_i64(t1, tcg_env, aofs + i); + tcg_gen_ld_i64(t2, tcg_env, bofs + i); + tcg_gen_ld_i64(t3, tcg_env, cofs + i); fni(t0, t1, t2, t3, c); - tcg_gen_st_i64(t0, cpu_env, dofs + i); + tcg_gen_st_i64(t0, tcg_env, dofs + i); } tcg_temp_free_i64(t3); tcg_temp_free_i64(t2); @@ -1029,12 +1029,12 @@ static void expand_2_vec(unsigned vece, uint32_t do= fs, uint32_t aofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D tysz) { - tcg_gen_ld_vec(t0, cpu_env, aofs + i); + tcg_gen_ld_vec(t0, tcg_env, aofs + i); if (load_dest) { - tcg_gen_ld_vec(t1, cpu_env, dofs + i); + tcg_gen_ld_vec(t1, tcg_env, dofs + i); } fni(vece, t1, t0); - tcg_gen_st_vec(t1, cpu_env, dofs + i); + tcg_gen_st_vec(t1, tcg_env, dofs + i); } tcg_temp_free_vec(t0); tcg_temp_free_vec(t1); @@ -1052,12 +1052,12 @@ static void expand_2i_vec(unsigned vece, uint32_t d= ofs, uint32_t aofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D tysz) { - tcg_gen_ld_vec(t0, cpu_env, aofs + i); + tcg_gen_ld_vec(t0, tcg_env, aofs + i); if (load_dest) { - tcg_gen_ld_vec(t1, cpu_env, dofs + i); + tcg_gen_ld_vec(t1, tcg_env, dofs + i); } fni(vece, t1, t0, c); - tcg_gen_st_vec(t1, cpu_env, dofs + i); + tcg_gen_st_vec(t1, tcg_env, dofs + i); } tcg_temp_free_vec(t0); tcg_temp_free_vec(t1); @@ -1073,13 +1073,13 @@ static void expand_2s_vec(unsigned vece, uint32_t d= ofs, uint32_t aofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D tysz) { - tcg_gen_ld_vec(t0, cpu_env, aofs + i); + tcg_gen_ld_vec(t0, tcg_env, aofs + i); if (scalar_first) { fni(vece, t1, c, t0); } else { fni(vece, t1, t0, c); } - tcg_gen_st_vec(t1, cpu_env, dofs + i); + tcg_gen_st_vec(t1, tcg_env, dofs + i); } tcg_temp_free_vec(t0); tcg_temp_free_vec(t1); @@ -1097,13 +1097,13 @@ static void expand_3_vec(unsigned vece, uint32_t do= fs, uint32_t aofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D tysz) { - tcg_gen_ld_vec(t0, cpu_env, aofs + i); - tcg_gen_ld_vec(t1, cpu_env, bofs + i); + tcg_gen_ld_vec(t0, tcg_env, aofs + i); + tcg_gen_ld_vec(t1, tcg_env, bofs + i); if (load_dest) { - tcg_gen_ld_vec(t2, cpu_env, dofs + i); + tcg_gen_ld_vec(t2, tcg_env, dofs + i); } fni(vece, t2, t0, t1); - tcg_gen_st_vec(t2, cpu_env, dofs + i); + tcg_gen_st_vec(t2, tcg_env, dofs + i); } tcg_temp_free_vec(t2); tcg_temp_free_vec(t1); @@ -1126,13 +1126,13 @@ static void expand_3i_vec(unsigned vece, uint32_t d= ofs, uint32_t aofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D tysz) { - tcg_gen_ld_vec(t0, cpu_env, aofs + i); - tcg_gen_ld_vec(t1, cpu_env, bofs + i); + tcg_gen_ld_vec(t0, tcg_env, aofs + i); + tcg_gen_ld_vec(t1, tcg_env, bofs + i); if (load_dest) { - tcg_gen_ld_vec(t2, cpu_env, dofs + i); + tcg_gen_ld_vec(t2, tcg_env, dofs + i); } fni(vece, t2, t0, t1, c); - tcg_gen_st_vec(t2, cpu_env, dofs + i); + tcg_gen_st_vec(t2, tcg_env, dofs + i); } tcg_temp_free_vec(t0); tcg_temp_free_vec(t1); @@ -1153,13 +1153,13 @@ static void expand_4_vec(unsigned vece, uint32_t do= fs, uint32_t aofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D tysz) { - tcg_gen_ld_vec(t1, cpu_env, aofs + i); - tcg_gen_ld_vec(t2, cpu_env, bofs + i); - tcg_gen_ld_vec(t3, cpu_env, cofs + i); + tcg_gen_ld_vec(t1, tcg_env, aofs + i); + tcg_gen_ld_vec(t2, tcg_env, bofs + i); + tcg_gen_ld_vec(t3, tcg_env, cofs + i); fni(vece, t0, t1, t2, t3); - tcg_gen_st_vec(t0, cpu_env, dofs + i); + tcg_gen_st_vec(t0, tcg_env, dofs + i); if (write_aofs) { - tcg_gen_st_vec(t1, cpu_env, aofs + i); + tcg_gen_st_vec(t1, tcg_env, aofs + i); } } tcg_temp_free_vec(t3); @@ -1185,11 +1185,11 @@ static void expand_4i_vec(unsigned vece, uint32_t d= ofs, uint32_t aofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D tysz) { - tcg_gen_ld_vec(t1, cpu_env, aofs + i); - tcg_gen_ld_vec(t2, cpu_env, bofs + i); - tcg_gen_ld_vec(t3, cpu_env, cofs + i); + tcg_gen_ld_vec(t1, tcg_env, aofs + i); + tcg_gen_ld_vec(t2, tcg_env, bofs + i); + tcg_gen_ld_vec(t3, tcg_env, cofs + i); fni(vece, t0, t1, t2, t3, c); - tcg_gen_st_vec(t0, cpu_env, dofs + i); + tcg_gen_st_vec(t0, tcg_env, dofs + i); } tcg_temp_free_vec(t3); tcg_temp_free_vec(t2); @@ -1730,27 +1730,27 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t d= ofs, uint32_t aofs, TCGType type =3D choose_vector_type(NULL, vece, oprsz, 0); if (type !=3D 0) { TCGv_vec t_vec =3D tcg_temp_new_vec(type); - tcg_gen_dup_mem_vec(vece, t_vec, cpu_env, aofs); + tcg_gen_dup_mem_vec(vece, t_vec, tcg_env, aofs); do_dup_store(type, dofs, oprsz, maxsz, t_vec); tcg_temp_free_vec(t_vec); } else if (vece <=3D MO_32) { TCGv_i32 in =3D tcg_temp_ebb_new_i32(); switch (vece) { case MO_8: - tcg_gen_ld8u_i32(in, cpu_env, aofs); + tcg_gen_ld8u_i32(in, tcg_env, aofs); break; case MO_16: - tcg_gen_ld16u_i32(in, cpu_env, aofs); + tcg_gen_ld16u_i32(in, tcg_env, aofs); break; default: - tcg_gen_ld_i32(in, cpu_env, aofs); + tcg_gen_ld_i32(in, tcg_env, aofs); break; } do_dup(vece, dofs, oprsz, maxsz, in, NULL, 0); tcg_temp_free_i32(in); } else { TCGv_i64 in =3D tcg_temp_ebb_new_i64(); - tcg_gen_ld_i64(in, cpu_env, aofs); + tcg_gen_ld_i64(in, tcg_env, aofs); do_dup(vece, dofs, oprsz, maxsz, NULL, in, 0); tcg_temp_free_i64(in); } @@ -1762,20 +1762,20 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t d= ofs, uint32_t aofs, if (TCG_TARGET_HAS_v128) { TCGv_vec in =3D tcg_temp_new_vec(TCG_TYPE_V128); =20 - tcg_gen_ld_vec(in, cpu_env, aofs); + tcg_gen_ld_vec(in, tcg_env, aofs); for (i =3D (aofs =3D=3D dofs) * 16; i < oprsz; i +=3D 16) { - tcg_gen_st_vec(in, cpu_env, dofs + i); + tcg_gen_st_vec(in, tcg_env, dofs + i); } tcg_temp_free_vec(in); } else { TCGv_i64 in0 =3D tcg_temp_ebb_new_i64(); TCGv_i64 in1 =3D tcg_temp_ebb_new_i64(); =20 - tcg_gen_ld_i64(in0, cpu_env, aofs); - tcg_gen_ld_i64(in1, cpu_env, aofs + 8); + tcg_gen_ld_i64(in0, tcg_env, aofs); + tcg_gen_ld_i64(in1, tcg_env, aofs + 8); for (i =3D (aofs =3D=3D dofs) * 16; i < oprsz; i +=3D 16) { - tcg_gen_st_i64(in0, cpu_env, dofs + i); - tcg_gen_st_i64(in1, cpu_env, dofs + i + 8); + tcg_gen_st_i64(in0, tcg_env, dofs + i); + tcg_gen_st_i64(in1, tcg_env, dofs + i + 8); } tcg_temp_free_i64(in0); tcg_temp_free_i64(in1); @@ -1792,20 +1792,20 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t d= ofs, uint32_t aofs, if (TCG_TARGET_HAS_v256) { TCGv_vec in =3D tcg_temp_new_vec(TCG_TYPE_V256); =20 - tcg_gen_ld_vec(in, cpu_env, aofs); + tcg_gen_ld_vec(in, tcg_env, aofs); for (i =3D (aofs =3D=3D dofs) * 32; i < oprsz; i +=3D 32) { - tcg_gen_st_vec(in, cpu_env, dofs + i); + tcg_gen_st_vec(in, tcg_env, dofs + i); } tcg_temp_free_vec(in); } else if (TCG_TARGET_HAS_v128) { TCGv_vec in0 =3D tcg_temp_new_vec(TCG_TYPE_V128); TCGv_vec in1 =3D tcg_temp_new_vec(TCG_TYPE_V128); =20 - tcg_gen_ld_vec(in0, cpu_env, aofs); - tcg_gen_ld_vec(in1, cpu_env, aofs + 16); + tcg_gen_ld_vec(in0, tcg_env, aofs); + tcg_gen_ld_vec(in1, tcg_env, aofs + 16); for (i =3D (aofs =3D=3D dofs) * 32; i < oprsz; i +=3D 32) { - tcg_gen_st_vec(in0, cpu_env, dofs + i); - tcg_gen_st_vec(in1, cpu_env, dofs + i + 16); + tcg_gen_st_vec(in0, tcg_env, dofs + i); + tcg_gen_st_vec(in1, tcg_env, dofs + i + 16); } tcg_temp_free_vec(in0); tcg_temp_free_vec(in1); @@ -1815,11 +1815,11 @@ void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t d= ofs, uint32_t aofs, =20 for (j =3D 0; j < 4; ++j) { in[j] =3D tcg_temp_ebb_new_i64(); - tcg_gen_ld_i64(in[j], cpu_env, aofs + j * 8); + tcg_gen_ld_i64(in[j], tcg_env, aofs + j * 8); } for (i =3D (aofs =3D=3D dofs) * 32; i < oprsz; i +=3D 32) { for (j =3D 0; j < 4; ++j) { - tcg_gen_st_i64(in[j], cpu_env, dofs + i + j * 8); + tcg_gen_st_i64(in[j], tcg_env, dofs + i + j * 8); } } for (j =3D 0; j < 4; ++j) { @@ -3140,9 +3140,9 @@ static void expand_2sh_vec(unsigned vece, uint32_t do= fs, uint32_t aofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D tysz) { - tcg_gen_ld_vec(t0, cpu_env, aofs + i); + tcg_gen_ld_vec(t0, tcg_env, aofs + i); fni(vece, t0, t0, shift); - tcg_gen_st_vec(t0, cpu_env, dofs + i); + tcg_gen_st_vec(t0, tcg_env, dofs + i); } tcg_temp_free_vec(t0); } @@ -3248,8 +3248,8 @@ do_gvec_shifts(unsigned vece, uint32_t dofs, uint32_t= aofs, TCGv_i32 shift, =20 tcg_gen_shli_i32(desc, shift, SIMD_DATA_SHIFT); tcg_gen_ori_i32(desc, desc, simd_desc(oprsz, maxsz, 0)); - tcg_gen_addi_ptr(a0, cpu_env, dofs); - tcg_gen_addi_ptr(a1, cpu_env, aofs); + tcg_gen_addi_ptr(a0, tcg_env, dofs); + tcg_gen_addi_ptr(a1, tcg_env, aofs); =20 g->fno[vece](a0, a1, desc); =20 @@ -3690,10 +3690,10 @@ static void expand_cmp_i32(uint32_t dofs, uint32_t = aofs, uint32_t bofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 4) { - tcg_gen_ld_i32(t0, cpu_env, aofs + i); - tcg_gen_ld_i32(t1, cpu_env, bofs + i); + tcg_gen_ld_i32(t0, tcg_env, aofs + i); + tcg_gen_ld_i32(t1, tcg_env, bofs + i); tcg_gen_negsetcond_i32(cond, t0, t0, t1); - tcg_gen_st_i32(t0, cpu_env, dofs + i); + tcg_gen_st_i32(t0, tcg_env, dofs + i); } tcg_temp_free_i32(t1); tcg_temp_free_i32(t0); @@ -3707,10 +3707,10 @@ static void expand_cmp_i64(uint32_t dofs, uint32_t = aofs, uint32_t bofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 8) { - tcg_gen_ld_i64(t0, cpu_env, aofs + i); - tcg_gen_ld_i64(t1, cpu_env, bofs + i); + tcg_gen_ld_i64(t0, tcg_env, aofs + i); + tcg_gen_ld_i64(t1, tcg_env, bofs + i); tcg_gen_negsetcond_i64(cond, t0, t0, t1); - tcg_gen_st_i64(t0, cpu_env, dofs + i); + tcg_gen_st_i64(t0, tcg_env, dofs + i); } tcg_temp_free_i64(t1); tcg_temp_free_i64(t0); @@ -3725,10 +3725,10 @@ static void expand_cmp_vec(unsigned vece, uint32_t = dofs, uint32_t aofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D tysz) { - tcg_gen_ld_vec(t0, cpu_env, aofs + i); - tcg_gen_ld_vec(t1, cpu_env, bofs + i); + tcg_gen_ld_vec(t0, tcg_env, aofs + i); + tcg_gen_ld_vec(t1, tcg_env, bofs + i); tcg_gen_cmp_vec(cond, vece, t0, t0, t1); - tcg_gen_st_vec(t0, cpu_env, dofs + i); + tcg_gen_st_vec(t0, tcg_env, dofs + i); } tcg_temp_free_vec(t1); tcg_temp_free_vec(t0); @@ -3855,9 +3855,9 @@ static void expand_cmps_vec(unsigned vece, uint32_t d= ofs, uint32_t aofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D tysz) { - tcg_gen_ld_vec(t1, cpu_env, aofs + i); + tcg_gen_ld_vec(t1, tcg_env, aofs + i); tcg_gen_cmp_vec(cond, vece, t0, t1, c); - tcg_gen_st_vec(t0, cpu_env, dofs + i); + tcg_gen_st_vec(t0, tcg_env, dofs + i); } } =20 @@ -3950,9 +3950,9 @@ void tcg_gen_gvec_cmps(TCGCond cond, unsigned vece, u= int32_t dofs, uint32_t i; =20 for (i =3D 0; i < oprsz; i +=3D 8) { - tcg_gen_ld_i64(t0, cpu_env, aofs + i); + tcg_gen_ld_i64(t0, tcg_env, aofs + i); tcg_gen_negsetcond_i64(cond, t0, t0, c); - tcg_gen_st_i64(t0, cpu_env, dofs + i); + tcg_gen_st_i64(t0, tcg_env, dofs + i); } tcg_temp_free_i64(t0); } else if (vece =3D=3D MO_32 && check_size_impl(oprsz, 4)) { @@ -3962,9 +3962,9 @@ void tcg_gen_gvec_cmps(TCGCond cond, unsigned vece, u= int32_t dofs, =20 tcg_gen_extrl_i64_i32(t1, c); for (i =3D 0; i < oprsz; i +=3D 8) { - tcg_gen_ld_i32(t0, cpu_env, aofs + i); + tcg_gen_ld_i32(t0, tcg_env, aofs + i); tcg_gen_negsetcond_i32(cond, t0, t0, t1); - tcg_gen_st_i32(t0, cpu_env, dofs + i); + tcg_gen_st_i32(t0, tcg_env, dofs + i); } tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index d54c305598..df4f22c427 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -589,7 +589,7 @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCG= Temp *addr, tcg_gen_extu_i32_i64(ext_addr, temp_tcgv_i32(addr)); addr =3D tcgv_i64_temp(ext_addr); } - gen_helper_ld_i128(val, cpu_env, temp_tcgv_i64(addr), + gen_helper_ld_i128(val, tcg_env, temp_tcgv_i64(addr), tcg_constant_i32(orig_oi)); } =20 @@ -698,7 +698,7 @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCG= Temp *addr, tcg_gen_extu_i32_i64(ext_addr, temp_tcgv_i32(addr)); addr =3D tcgv_i64_temp(ext_addr); } - gen_helper_st_i128(cpu_env, temp_tcgv_i64(addr), val, + gen_helper_st_i128(tcg_env, temp_tcgv_i64(addr), val, tcg_constant_i32(orig_oi)); } =20 @@ -847,7 +847,7 @@ static void tcg_gen_atomic_cmpxchg_i32_int(TCGv_i32 ret= v, TCGTemp *addr, =20 oi =3D make_memop_idx(memop & ~MO_SIGN, idx); a64 =3D maybe_extend_addr64(addr); - gen(retv, cpu_env, a64, cmpv, newv, tcg_constant_i32(oi)); + gen(retv, tcg_env, a64, cmpv, newv, tcg_constant_i32(oi)); maybe_free_addr64(a64); =20 if (memop & MO_SIGN) { @@ -927,12 +927,12 @@ static void tcg_gen_atomic_cmpxchg_i64_int(TCGv_i64 r= etv, TCGTemp *addr, if (gen) { MemOpIdx oi =3D make_memop_idx(memop, idx); TCGv_i64 a64 =3D maybe_extend_addr64(addr); - gen(retv, cpu_env, a64, cmpv, newv, tcg_constant_i32(oi)); + gen(retv, tcg_env, a64, cmpv, newv, tcg_constant_i32(oi)); maybe_free_addr64(a64); return; } =20 - gen_helper_exit_atomic(cpu_env); + gen_helper_exit_atomic(tcg_env); =20 /* * Produce a result for a well-formed opcode stream. This satisfi= es @@ -990,7 +990,7 @@ static void tcg_gen_nonatomic_cmpxchg_i128_int(TCGv_i12= 8 retv, TCGTemp *addr, MemOpIdx oi =3D make_memop_idx(memop, idx); TCGv_i64 a64 =3D maybe_extend_addr64(addr); =20 - gen_helper_nonatomic_cmpxchgo(retv, cpu_env, a64, cmpv, newv, + gen_helper_nonatomic_cmpxchgo(retv, tcg_env, a64, cmpv, newv, tcg_constant_i32(oi)); maybe_free_addr64(a64); } else { @@ -1049,12 +1049,12 @@ static void tcg_gen_atomic_cmpxchg_i128_int(TCGv_i1= 28 retv, TCGTemp *addr, if (gen) { MemOpIdx oi =3D make_memop_idx(memop, idx); TCGv_i64 a64 =3D maybe_extend_addr64(addr); - gen(retv, cpu_env, a64, cmpv, newv, tcg_constant_i32(oi)); + gen(retv, tcg_env, a64, cmpv, newv, tcg_constant_i32(oi)); maybe_free_addr64(a64); return; } =20 - gen_helper_exit_atomic(cpu_env); + gen_helper_exit_atomic(tcg_env); =20 /* * Produce a result for a well-formed opcode stream. This satisfies @@ -1108,7 +1108,7 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGTemp *a= ddr, TCGv_i32 val, =20 oi =3D make_memop_idx(memop & ~MO_SIGN, idx); a64 =3D maybe_extend_addr64(addr); - gen(ret, cpu_env, a64, val, tcg_constant_i32(oi)); + gen(ret, tcg_env, a64, val, tcg_constant_i32(oi)); maybe_free_addr64(a64); =20 if (memop & MO_SIGN) { @@ -1146,12 +1146,12 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGTemp = *addr, TCGv_i64 val, if (gen) { MemOpIdx oi =3D make_memop_idx(memop & ~MO_SIGN, idx); TCGv_i64 a64 =3D maybe_extend_addr64(addr); - gen(ret, cpu_env, a64, val, tcg_constant_i32(oi)); + gen(ret, tcg_env, a64, val, tcg_constant_i32(oi)); maybe_free_addr64(a64); return; } =20 - gen_helper_exit_atomic(cpu_env); + gen_helper_exit_atomic(tcg_env); /* Produce a result, so that we have a well-formed opcode stream with respect to uses of the result in the (dead) code following= . */ tcg_gen_movi_i64(ret, 0); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 02a8cadcc0..393dbcd01c 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2939,7 +2939,7 @@ void tcg_gen_lookup_and_goto_ptr(void) =20 plugin_gen_disable_mem_helpers(); ptr =3D tcg_temp_ebb_new_ptr(); - gen_helper_lookup_tb_ptr(ptr, cpu_env); + gen_helper_lookup_tb_ptr(ptr, tcg_env); tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr)); tcg_temp_free_ptr(ptr); } diff --git a/tcg/tcg.c b/tcg/tcg.c index 604fa9bf3e..72b113ad53 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -231,7 +231,7 @@ __thread TCGContext *tcg_ctx; TCGContext **tcg_ctxs; unsigned int tcg_cur_ctxs; unsigned int tcg_max_ctxs; -TCGv_env cpu_env =3D 0; +TCGv_env tcg_env; const void *tcg_code_gen_epilogue; uintptr_t tcg_splitwx_diff; =20 @@ -1353,7 +1353,7 @@ static void tcg_context_init(unsigned max_cpus) =20 tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0)); ts =3D tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env"); - cpu_env =3D temp_tcgv_ptr(ts); + tcg_env =3D temp_tcgv_ptr(ts); } =20 void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus) diff --git a/target/cris/translate_v10.c.inc b/target/cris/translate_v10.c.= inc index b7b0517982..6df599fdce 100644 --- a/target/cris/translate_v10.c.inc +++ b/target/cris/translate_v10.c.inc @@ -282,7 +282,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc) } else { /* BTST */ cris_update_cc_op(dc, CC_OP_FLAGS, 4); - gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst], + gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->dst], c, cpu_PR[PR_CCS]); } break; @@ -696,7 +696,7 @@ static unsigned int dec10_reg(DisasContext *dc) LOG_DIS("btst $r%d, $r%d sz=3D%d\n", dc->src, dc->dst, siz= e); cris_cc_mask(dc, CC_MASK_NZVC); cris_update_cc_op(dc, CC_OP_FLAGS, 4); - gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst], + gen_helper_btst(cpu_PR[PR_CCS], tcg_env, cpu_R[dc->dst], cpu_R[dc->src], cpu_PR[PR_CCS]); break; case CRISV10_REG_DSTEP: @@ -1235,41 +1235,41 @@ void cris_initialize_crisv10_tcg(void) { int i; =20 - cc_x =3D tcg_global_mem_new(cpu_env, + cc_x =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, cc_x), "cc_x"); - cc_src =3D tcg_global_mem_new(cpu_env, + cc_src =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, cc_src), "cc_src"); - cc_dest =3D tcg_global_mem_new(cpu_env, + cc_dest =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, cc_dest), "cc_dest"); - cc_result =3D tcg_global_mem_new(cpu_env, + cc_result =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, cc_result), "cc_result"); - cc_op =3D tcg_global_mem_new(cpu_env, + cc_op =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, cc_op), "cc_op"); - cc_size =3D tcg_global_mem_new(cpu_env, + cc_size =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, cc_size), "cc_size"); - cc_mask =3D tcg_global_mem_new(cpu_env, + cc_mask =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, cc_mask), "cc_mask"); =20 - env_pc =3D tcg_global_mem_new(cpu_env, + env_pc =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, pc), "pc"); - env_btarget =3D tcg_global_mem_new(cpu_env, + env_btarget =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, btarget), "btarget"); - env_btaken =3D tcg_global_mem_new(cpu_env, + env_btaken =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, btaken), "btaken"); for (i =3D 0; i < 16; i++) { - cpu_R[i] =3D tcg_global_mem_new(cpu_env, + cpu_R[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, regs[i]), regnames_v10[i]); } for (i =3D 0; i < 16; i++) { - cpu_PR[i] =3D tcg_global_mem_new(cpu_env, + cpu_PR[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUCRISState, pregs[i]), pregnames_v10[i]); } diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index 0db19cda3b..af1878c38a 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -1822,7 +1822,7 @@ static void disas_insn_new(DisasContext *s, CPUState = *cpu, int b) } if (decode.e.special =3D=3D X86_SPECIAL_MMX && !(s->prefix & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))) { - gen_helper_enter_mmx(cpu_env); + gen_helper_enter_mmx(tcg_env); } =20 if (decode.op[0].has_ea || decode.op[1].has_ea || decode.op[2].has_ea)= { diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 45a3e55cbf..88793ba988 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -175,15 +175,15 @@ static void gen_load_sse(DisasContext *s, TCGv temp, = MemOp ot, int dest_ofs, boo switch(ot) { case MO_8: gen_op_ld_v(s, MO_8, temp, s->A0); - tcg_gen_st8_tl(temp, cpu_env, dest_ofs); + tcg_gen_st8_tl(temp, tcg_env, dest_ofs); break; case MO_16: gen_op_ld_v(s, MO_16, temp, s->A0); - tcg_gen_st16_tl(temp, cpu_env, dest_ofs); + tcg_gen_st16_tl(temp, tcg_env, dest_ofs); break; case MO_32: gen_op_ld_v(s, MO_32, temp, s->A0); - tcg_gen_st32_tl(temp, cpu_env, dest_ofs); + tcg_gen_st32_tl(temp, tcg_env, dest_ofs); break; case MO_64: gen_ldq_env_A0(s, dest_ofs); @@ -226,14 +226,14 @@ static void gen_load(DisasContext *s, X86DecodedInsn = *decode, int opn, TCGv v) case X86_OP_SKIP: return; case X86_OP_SEG: - tcg_gen_ld32u_tl(v, cpu_env, + tcg_gen_ld32u_tl(v, tcg_env, offsetof(CPUX86State,segs[op->n].selector)); break; case X86_OP_CR: - tcg_gen_ld_tl(v, cpu_env, offsetof(CPUX86State, cr[op->n])); + tcg_gen_ld_tl(v, tcg_env, offsetof(CPUX86State, cr[op->n])); break; case X86_OP_DR: - tcg_gen_ld_tl(v, cpu_env, offsetof(CPUX86State, dr[op->n])); + tcg_gen_ld_tl(v, tcg_env, offsetof(CPUX86State, dr[op->n])); break; case X86_OP_INT: if (op->has_ea) { @@ -273,7 +273,7 @@ static TCGv_ptr op_ptr(X86DecodedInsn *decode, int opn) op->v_ptr =3D tcg_temp_new_ptr(); =20 /* The temporary points to the MMXReg or ZMMReg. */ - tcg_gen_addi_ptr(op->v_ptr, cpu_env, vector_reg_offset(op)); + tcg_gen_addi_ptr(op->v_ptr, tcg_env, vector_reg_offset(op)); return op->v_ptr; } =20 @@ -400,12 +400,12 @@ static void gen_3dnow(DisasContext *s, CPUX86State *e= nv, X86DecodedInsn *decode) return; } =20 - gen_helper_enter_mmx(cpu_env); + gen_helper_enter_mmx(tcg_env); if (fn =3D=3D FN_3DNOW_MOVE) { - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset); - tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset); + tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset); + tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset); } else { - fn(cpu_env, OP_PTR0, OP_PTR1); + fn(tcg_env, OP_PTR0, OP_PTR1); } } =20 @@ -426,7 +426,7 @@ static inline void gen_unary_fp_sse(DisasContext *s, CP= UX86State *env, X86Decode gen_illegal_opcode(s); return; } - fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); + fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); } else { SSEFunc_0_epp ps, pd, fn; ps =3D s->vex_l ? ps_ymm : ps_xmm; @@ -436,7 +436,7 @@ static inline void gen_unary_fp_sse(DisasContext *s, CP= UX86State *env, X86Decode gen_illegal_opcode(s); return; } - fn(cpu_env, OP_PTR0, OP_PTR2); + fn(tcg_env, OP_PTR0, OP_PTR2); } } #define UNARY_FP_SSE(uname, lname) = \ @@ -472,7 +472,7 @@ static inline void gen_fp_sse(DisasContext *s, CPUX86St= ate *env, X86DecodedInsn fn =3D s->prefix & PREFIX_DATA ? pd : ps; } if (fn) { - fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); + fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); } else { gen_illegal_opcode(s); } @@ -503,7 +503,7 @@ static void gen_##uname##Px(DisasContext *s, CPUX86Stat= e *env, X86DecodedInsn *d SSEFunc_0_eppppii ymm =3D s->vex_w ? gen_helper_fma4pd_ymm : gen_helpe= r_fma4ps_ymm; \ SSEFunc_0_eppppii fn =3D s->vex_l ? ymm : xmm; = \ = \ - fn(cpu_env, OP_PTR0, ptr0, ptr1, ptr2, = \ + fn(tcg_env, OP_PTR0, ptr0, ptr1, ptr2, = \ tcg_constant_i32(even), = \ tcg_constant_i32((even) ^ (odd))); = \ } @@ -514,7 +514,7 @@ static void gen_##uname##Sx(DisasContext *s, CPUX86Stat= e *env, X86DecodedInsn *d { = \ SSEFunc_0_eppppi fn =3D s->vex_w ? gen_helper_fma4sd : gen_helper_fma4= ss; \ = \ - fn(cpu_env, OP_PTR0, ptr0, ptr1, ptr2, = \ + fn(tcg_env, OP_PTR0, ptr0, ptr1, ptr2, = \ tcg_constant_i32(flags)); = \ } = \ =20 @@ -571,13 +571,13 @@ static inline void gen_unary_fp32_sse(DisasContext *s= , CPUX86State *env, X86Deco if (!ss) { goto illegal_op; } - ss(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); + ss(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); } else { SSEFunc_0_epp fn =3D s->vex_l ? ps_ymm : ps_xmm; if (!fn) { goto illegal_op; } - fn(cpu_env, OP_PTR0, OP_PTR2); + fn(tcg_env, OP_PTR0, OP_PTR2); } return; =20 @@ -607,7 +607,7 @@ static inline void gen_horizontal_fp_sse(DisasContext *= s, CPUX86State *env, X86D ps =3D s->vex_l ? ps_ymm : ps_xmm; pd =3D s->vex_l ? pd_ymm : pd_xmm; fn =3D s->prefix & PREFIX_DATA ? pd : ps; - fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); + fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); } #define HORIZONTAL_FP_SSE(uname, lname) = \ static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn = *decode) \ @@ -627,8 +627,8 @@ static inline void gen_ternary_sse(DisasContext *s, CPU= X86State *env, X86Decoded TCGv_ptr ptr3 =3D tcg_temp_new_ptr(); =20 /* The format of the fourth input is Lx */ - tcg_gen_addi_ptr(ptr3, cpu_env, ZMM_OFFSET(op3)); - fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, ptr3); + tcg_gen_addi_ptr(ptr3, tcg_env, ZMM_OFFSET(op3)); + fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, ptr3); } #define TERNARY_SSE(uname, uvname, lname) = \ static void gen_##uvname(DisasContext *s, CPUX86State *env, X86DecodedInsn= *decode) \ @@ -650,9 +650,9 @@ static inline void gen_binary_imm_sse(DisasContext *s, = CPUX86State *env, X86Deco { TCGv_i32 imm =3D tcg_constant8u_i32(decode->immediate); if (!s->vex_l) { - xmm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); + xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); } else { - ymm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); + ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); } } =20 @@ -763,11 +763,11 @@ static inline void gen_binary_int_sse(DisasContext *s= , CPUX86State *env, X86Deco return; } if (!(s->prefix & PREFIX_DATA)) { - mmx(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); + mmx(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); } else if (!s->vex_l) { - xmm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); + xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); } else { - ymm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); + ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); } } =20 @@ -850,9 +850,9 @@ BINARY_INT_SSE(VAESENCLAST, aesenclast) static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn = *decode) \ { = \ if (!s->vex_l) { = \ - gen_helper_##lname##_xmm(cpu_env, OP_PTR1, OP_PTR2); = \ + gen_helper_##lname##_xmm(tcg_env, OP_PTR1, OP_PTR2); = \ } else { = \ - gen_helper_##lname##_ymm(cpu_env, OP_PTR1, OP_PTR2); = \ + gen_helper_##lname##_ymm(tcg_env, OP_PTR1, OP_PTR2); = \ } = \ set_cc_op(s, CC_OP_EFLAGS); = \ } @@ -864,9 +864,9 @@ static inline void gen_unary_int_sse(DisasContext *s, C= PUX86State *env, X86Decod SSEFunc_0_epp xmm, SSEFunc_0_epp ymm) { if (!s->vex_l) { - xmm(cpu_env, OP_PTR0, OP_PTR2); + xmm(tcg_env, OP_PTR0, OP_PTR2); } else { - ymm(cpu_env, OP_PTR0, OP_PTR2); + ymm(tcg_env, OP_PTR0, OP_PTR2); } } =20 @@ -937,9 +937,9 @@ static inline void gen_unary_imm_fp_sse(DisasContext *s= , CPUX86State *env, X86De { TCGv_i32 imm =3D tcg_constant8u_i32(decode->immediate); if (!s->vex_l) { - xmm(cpu_env, OP_PTR0, OP_PTR1, imm); + xmm(tcg_env, OP_PTR0, OP_PTR1, imm); } else { - ymm(cpu_env, OP_PTR0, OP_PTR1, imm); + ymm(tcg_env, OP_PTR0, OP_PTR1, imm); } } =20 @@ -961,7 +961,7 @@ static inline void gen_vexw_avx(DisasContext *s, CPUX86= State *env, X86DecodedIns SSEFunc_0_eppp d =3D s->vex_l ? d_ymm : d_xmm; SSEFunc_0_eppp q =3D s->vex_l ? q_ymm : q_xmm; SSEFunc_0_eppp fn =3D s->vex_w ? q : d; - fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); + fn(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); } =20 /* VEX.W affects whether to operate on 32- or 64-bit elements. */ @@ -989,8 +989,8 @@ static inline void gen_vsib_avx(DisasContext *s, CPUX86= State *env, X86DecodedIns TCGv_ptr index =3D tcg_temp_new_ptr(); =20 /* Pass third input as (index, base, scale) */ - tcg_gen_addi_ptr(index, cpu_env, ZMM_OFFSET(decode->mem.index)); - fn(cpu_env, OP_PTR0, OP_PTR1, index, s->A0, scale); + tcg_gen_addi_ptr(index, tcg_env, ZMM_OFFSET(decode->mem.index)); + fn(tcg_env, OP_PTR0, OP_PTR1, index, s->A0, scale); =20 /* * There are two output operands, so zero OP1's high 128 bits @@ -1175,37 +1175,37 @@ static void gen_CRC32(DisasContext *s, CPUX86State = *env, X86DecodedInsn *decode) =20 static void gen_CVTPI2Px(DisasContext *s, CPUX86State *env, X86DecodedInsn= *decode) { - gen_helper_enter_mmx(cpu_env); + gen_helper_enter_mmx(tcg_env); if (s->prefix & PREFIX_DATA) { - gen_helper_cvtpi2pd(cpu_env, OP_PTR0, OP_PTR2); + gen_helper_cvtpi2pd(tcg_env, OP_PTR0, OP_PTR2); } else { - gen_helper_cvtpi2ps(cpu_env, OP_PTR0, OP_PTR2); + gen_helper_cvtpi2ps(tcg_env, OP_PTR0, OP_PTR2); } } =20 static void gen_CVTPx2PI(DisasContext *s, CPUX86State *env, X86DecodedInsn= *decode) { - gen_helper_enter_mmx(cpu_env); + gen_helper_enter_mmx(tcg_env); if (s->prefix & PREFIX_DATA) { - gen_helper_cvtpd2pi(cpu_env, OP_PTR0, OP_PTR2); + gen_helper_cvtpd2pi(tcg_env, OP_PTR0, OP_PTR2); } else { - gen_helper_cvtps2pi(cpu_env, OP_PTR0, OP_PTR2); + gen_helper_cvtps2pi(tcg_env, OP_PTR0, OP_PTR2); } } =20 static void gen_CVTTPx2PI(DisasContext *s, CPUX86State *env, X86DecodedIns= n *decode) { - gen_helper_enter_mmx(cpu_env); + gen_helper_enter_mmx(tcg_env); if (s->prefix & PREFIX_DATA) { - gen_helper_cvttpd2pi(cpu_env, OP_PTR0, OP_PTR2); + gen_helper_cvttpd2pi(tcg_env, OP_PTR0, OP_PTR2); } else { - gen_helper_cvttps2pi(cpu_env, OP_PTR0, OP_PTR2); + gen_helper_cvttps2pi(tcg_env, OP_PTR0, OP_PTR2); } } =20 static void gen_EMMS(DisasContext *s, CPUX86State *env, X86DecodedInsn *de= code) { - gen_helper_emms(cpu_env); + gen_helper_emms(tcg_env); } =20 static void gen_EXTRQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn = *decode) @@ -1213,12 +1213,12 @@ static void gen_EXTRQ_i(DisasContext *s, CPUX86Stat= e *env, X86DecodedInsn *decod TCGv_i32 length =3D tcg_constant_i32(decode->immediate & 63); TCGv_i32 index =3D tcg_constant_i32((decode->immediate >> 8) & 63); =20 - gen_helper_extrq_i(cpu_env, OP_PTR0, index, length); + gen_helper_extrq_i(tcg_env, OP_PTR0, index, length); } =20 static void gen_EXTRQ_r(DisasContext *s, CPUX86State *env, X86DecodedInsn = *decode) { - gen_helper_extrq_r(cpu_env, OP_PTR0, OP_PTR2); + gen_helper_extrq_r(tcg_env, OP_PTR0, OP_PTR2); } =20 static void gen_INSERTQ_i(DisasContext *s, CPUX86State *env, X86DecodedIns= n *decode) @@ -1226,12 +1226,12 @@ static void gen_INSERTQ_i(DisasContext *s, CPUX86St= ate *env, X86DecodedInsn *dec TCGv_i32 length =3D tcg_constant_i32(decode->immediate & 63); TCGv_i32 index =3D tcg_constant_i32((decode->immediate >> 8) & 63); =20 - gen_helper_insertq_i(cpu_env, OP_PTR0, OP_PTR1, index, length); + gen_helper_insertq_i(tcg_env, OP_PTR0, OP_PTR1, index, length); } =20 static void gen_INSERTQ_r(DisasContext *s, CPUX86State *env, X86DecodedIns= n *decode) { - gen_helper_insertq_r(cpu_env, OP_PTR0, OP_PTR2); + gen_helper_insertq_r(tcg_env, OP_PTR0, OP_PTR2); } =20 static void gen_LDMXCSR(DisasContext *s, CPUX86State *env, X86DecodedInsn = *decode) @@ -1241,7 +1241,7 @@ static void gen_LDMXCSR(DisasContext *s, CPUX86State = *env, X86DecodedInsn *decod return; } tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T1); - gen_helper_ldmxcsr(cpu_env, s->tmp2_i32); + gen_helper_ldmxcsr(tcg_env, s->tmp2_i32); } =20 static void gen_MASKMOV(DisasContext *s, CPUX86State *env, X86DecodedInsn = *decode) @@ -1251,9 +1251,9 @@ static void gen_MASKMOV(DisasContext *s, CPUX86State = *env, X86DecodedInsn *decod gen_add_A0_ds_seg(s); =20 if (s->prefix & PREFIX_DATA) { - gen_helper_maskmov_xmm(cpu_env, OP_PTR1, OP_PTR2, s->A0); + gen_helper_maskmov_xmm(tcg_env, OP_PTR1, OP_PTR2, s->A0); } else { - gen_helper_maskmov_mmx(cpu_env, OP_PTR1, OP_PTR2, s->A0); + gen_helper_maskmov_mmx(tcg_env, OP_PTR1, OP_PTR2, s->A0); } } =20 @@ -1276,11 +1276,11 @@ static void gen_MOVD_from(DisasContext *s, CPUX86St= ate *env, X86DecodedInsn *dec switch (ot) { case MO_32: #ifdef TARGET_X86_64 - tcg_gen_ld32u_tl(s->T0, cpu_env, decode->op[2].offset); + tcg_gen_ld32u_tl(s->T0, tcg_env, decode->op[2].offset); break; case MO_64: #endif - tcg_gen_ld_tl(s->T0, cpu_env, decode->op[2].offset); + tcg_gen_ld_tl(s->T0, tcg_env, decode->op[2].offset); break; default: abort(); @@ -1298,11 +1298,11 @@ static void gen_MOVD_to(DisasContext *s, CPUX86Stat= e *env, X86DecodedInsn *decod switch (ot) { case MO_32: #ifdef TARGET_X86_64 - tcg_gen_st32_tl(s->T1, cpu_env, lo_ofs); + tcg_gen_st32_tl(s->T1, tcg_env, lo_ofs); break; case MO_64: #endif - tcg_gen_st_tl(s->T1, cpu_env, lo_ofs); + tcg_gen_st_tl(s->T1, tcg_env, lo_ofs); break; default: g_assert_not_reached(); @@ -1320,7 +1320,7 @@ static void gen_MOVMSK(DisasContext *s, CPUX86State *= env, X86DecodedInsn *decode ps =3D s->vex_l ? gen_helper_movmskps_ymm : gen_helper_movmskps_xmm; pd =3D s->vex_l ? gen_helper_movmskpd_ymm : gen_helper_movmskpd_xmm; fn =3D s->prefix & PREFIX_DATA ? pd : ps; - fn(s->tmp2_i32, cpu_env, OP_PTR2); + fn(s->tmp2_i32, tcg_env, OP_PTR2); tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32); } =20 @@ -1329,7 +1329,7 @@ static void gen_MOVQ(DisasContext *s, CPUX86State *en= v, X86DecodedInsn *decode) int vec_len =3D vector_len(s, decode); int lo_ofs =3D vector_elem_offset(&decode->op[0], MO_64, 0); =20 - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset); + tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset); if (decode->op[0].has_ea) { tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); } else { @@ -1342,13 +1342,13 @@ static void gen_MOVQ(DisasContext *s, CPUX86State *= env, X86DecodedInsn *decode) * it disqualifies using oprsz < maxsz to emulate VEX128. */ tcg_gen_gvec_dup_imm(MO_64, decode->op[0].offset, vec_len, vec_len= , 0); - tcg_gen_st_i64(s->tmp1_i64, cpu_env, lo_ofs); + tcg_gen_st_i64(s->tmp1_i64, tcg_env, lo_ofs); } } =20 static void gen_MOVq_dq(DisasContext *s, CPUX86State *env, X86DecodedInsn = *decode) { - gen_helper_enter_mmx(cpu_env); + gen_helper_enter_mmx(tcg_env); /* Otherwise the same as any other movq. */ return gen_MOVQ(s, env, decode); } @@ -1380,11 +1380,11 @@ static void gen_PALIGNR(DisasContext *s, CPUX86Stat= e *env, X86DecodedInsn *decod { TCGv_i32 imm =3D tcg_constant8u_i32(decode->immediate); if (!(s->prefix & PREFIX_DATA)) { - gen_helper_palignr_mmx(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); + gen_helper_palignr_mmx(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); } else if (!s->vex_l) { - gen_helper_palignr_xmm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); + gen_helper_palignr_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); } else { - gen_helper_palignr_ymm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); + gen_helper_palignr_ymm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); } } =20 @@ -1401,14 +1401,14 @@ static void gen_PANDN(DisasContext *s, CPUX86State = *env, X86DecodedInsn *decode) static void gen_PCMPESTRI(DisasContext *s, CPUX86State *env, X86DecodedIns= n *decode) { TCGv_i32 imm =3D tcg_constant8u_i32(decode->immediate); - gen_helper_pcmpestri_xmm(cpu_env, OP_PTR1, OP_PTR2, imm); + gen_helper_pcmpestri_xmm(tcg_env, OP_PTR1, OP_PTR2, imm); set_cc_op(s, CC_OP_EFLAGS); } =20 static void gen_PCMPESTRM(DisasContext *s, CPUX86State *env, X86DecodedIns= n *decode) { TCGv_i32 imm =3D tcg_constant8u_i32(decode->immediate); - gen_helper_pcmpestrm_xmm(cpu_env, OP_PTR1, OP_PTR2, imm); + gen_helper_pcmpestrm_xmm(tcg_env, OP_PTR1, OP_PTR2, imm); set_cc_op(s, CC_OP_EFLAGS); if ((s->prefix & PREFIX_VEX) && !s->vex_l) { tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_regs[0].ZMM_= X(1)), @@ -1419,14 +1419,14 @@ static void gen_PCMPESTRM(DisasContext *s, CPUX86St= ate *env, X86DecodedInsn *dec static void gen_PCMPISTRI(DisasContext *s, CPUX86State *env, X86DecodedIns= n *decode) { TCGv_i32 imm =3D tcg_constant8u_i32(decode->immediate); - gen_helper_pcmpistri_xmm(cpu_env, OP_PTR1, OP_PTR2, imm); + gen_helper_pcmpistri_xmm(tcg_env, OP_PTR1, OP_PTR2, imm); set_cc_op(s, CC_OP_EFLAGS); } =20 static void gen_PCMPISTRM(DisasContext *s, CPUX86State *env, X86DecodedIns= n *decode) { TCGv_i32 imm =3D tcg_constant8u_i32(decode->immediate); - gen_helper_pcmpistrm_xmm(cpu_env, OP_PTR1, OP_PTR2, imm); + gen_helper_pcmpistrm_xmm(tcg_env, OP_PTR1, OP_PTR2, imm); set_cc_op(s, CC_OP_EFLAGS); if ((s->prefix & PREFIX_VEX) && !s->vex_l) { tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_regs[0].ZMM_= X(1)), @@ -1460,18 +1460,18 @@ static inline void gen_pextr(DisasContext *s, CPUX8= 6State *env, X86DecodedInsn * =20 switch (ot) { case MO_8: - tcg_gen_ld8u_tl(s->T0, cpu_env, vector_elem_offset(&decode->op[1],= ot, val)); + tcg_gen_ld8u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1],= ot, val)); break; case MO_16: - tcg_gen_ld16u_tl(s->T0, cpu_env, vector_elem_offset(&decode->op[1]= , ot, val)); + tcg_gen_ld16u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1]= , ot, val)); break; case MO_32: #ifdef TARGET_X86_64 - tcg_gen_ld32u_tl(s->T0, cpu_env, vector_elem_offset(&decode->op[1]= , ot, val)); + tcg_gen_ld32u_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1]= , ot, val)); break; case MO_64: #endif - tcg_gen_ld_tl(s->T0, cpu_env, vector_elem_offset(&decode->op[1], o= t, val)); + tcg_gen_ld_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], o= t, val)); break; default: abort(); @@ -1507,18 +1507,18 @@ static inline void gen_pinsr(DisasContext *s, CPUX8= 6State *env, X86DecodedInsn * =20 switch (ot) { case MO_8: - tcg_gen_st8_tl(s->T1, cpu_env, vector_elem_offset(&decode->op[0], = ot, val)); + tcg_gen_st8_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], = ot, val)); break; case MO_16: - tcg_gen_st16_tl(s->T1, cpu_env, vector_elem_offset(&decode->op[0],= ot, val)); + tcg_gen_st16_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0],= ot, val)); break; case MO_32: #ifdef TARGET_X86_64 - tcg_gen_st32_tl(s->T1, cpu_env, vector_elem_offset(&decode->op[0],= ot, val)); + tcg_gen_st32_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0],= ot, val)); break; case MO_64: #endif - tcg_gen_st_tl(s->T1, cpu_env, vector_elem_offset(&decode->op[0], o= t, val)); + tcg_gen_st_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], o= t, val)); break; default: abort(); @@ -1599,7 +1599,7 @@ static void gen_PMOVMSKB(DisasContext *s, CPUX86State= *env, X86DecodedInsn *deco =20 tcg_gen_gvec_2(offsetof(CPUX86State, xmm_t0) + xmm_offset(ot), decode-= >op[2].offset, vec_len, vec_len, &g); - tcg_gen_ld8u_tl(s->T0, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec= _len - 1))); + tcg_gen_ld8u_tl(s->T0, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec= _len - 1))); while (vec_len > 8) { vec_len -=3D 8; if (TCG_TARGET_HAS_extract2_tl) { @@ -1609,9 +1609,9 @@ static void gen_PMOVMSKB(DisasContext *s, CPUX86State= *env, X86DecodedInsn *deco * loading the whole word, the shift left is avoided. */ #ifdef TARGET_X86_64 - tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_Q((= vec_len - 1) / 8))); + tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_Q((= vec_len - 1) / 8))); #else - tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_L((= vec_len - 1) / 4))); + tcg_gen_ld_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_L((= vec_len - 1) / 4))); #endif =20 tcg_gen_extract2_tl(s->T0, t, s->T0, TARGET_LONG_BITS - 8); @@ -1621,7 +1621,7 @@ static void gen_PMOVMSKB(DisasContext *s, CPUX86State= *env, X86DecodedInsn *deco * those bits are known to be zero after ld8u, this becomes a = shift+or * if deposit is not available. */ - tcg_gen_ld8u_tl(t, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_B= (vec_len - 1))); + tcg_gen_ld8u_tl(t, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_B= (vec_len - 1))); tcg_gen_deposit_tl(s->T0, t, s->T0, 8, TARGET_LONG_BITS - 8); } } @@ -1744,8 +1744,8 @@ static TCGv_ptr make_imm8u_xmm_vec(uint8_t imm, int v= ec_len) tcg_gen_gvec_dup_imm(MO_64, offsetof(CPUX86State, xmm_t0) + xmm_offset= (ot), vec_len, vec_len, 0); =20 - tcg_gen_addi_ptr(ptr, cpu_env, offsetof(CPUX86State, xmm_t0)); - tcg_gen_st_i32(imm_v, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_L(0))); + tcg_gen_addi_ptr(ptr, tcg_env, offsetof(CPUX86State, xmm_t0)); + tcg_gen_st_i32(imm_v, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_L(0))); return ptr; } =20 @@ -1755,9 +1755,9 @@ static void gen_PSRLDQ_i(DisasContext *s, CPUX86State= *env, X86DecodedInsn *deco TCGv_ptr imm_vec =3D make_imm8u_xmm_vec(decode->immediate, vec_len); =20 if (s->vex_l) { - gen_helper_psrldq_ymm(cpu_env, OP_PTR0, OP_PTR1, imm_vec); + gen_helper_psrldq_ymm(tcg_env, OP_PTR0, OP_PTR1, imm_vec); } else { - gen_helper_psrldq_xmm(cpu_env, OP_PTR0, OP_PTR1, imm_vec); + gen_helper_psrldq_xmm(tcg_env, OP_PTR0, OP_PTR1, imm_vec); } } =20 @@ -1767,9 +1767,9 @@ static void gen_PSLLDQ_i(DisasContext *s, CPUX86State= *env, X86DecodedInsn *deco TCGv_ptr imm_vec =3D make_imm8u_xmm_vec(decode->immediate, vec_len); =20 if (s->vex_l) { - gen_helper_pslldq_ymm(cpu_env, OP_PTR0, OP_PTR1, imm_vec); + gen_helper_pslldq_ymm(tcg_env, OP_PTR0, OP_PTR1, imm_vec); } else { - gen_helper_pslldq_xmm(cpu_env, OP_PTR0, OP_PTR1, imm_vec); + gen_helper_pslldq_xmm(tcg_env, OP_PTR0, OP_PTR1, imm_vec); } } =20 @@ -1827,7 +1827,7 @@ static void gen_VAESKEYGEN(DisasContext *s, CPUX86Sta= te *env, X86DecodedInsn *de { TCGv_i32 imm =3D tcg_constant8u_i32(decode->immediate); assert(!s->vex_l); - gen_helper_aeskeygenassist_xmm(cpu_env, OP_PTR0, OP_PTR1, imm); + gen_helper_aeskeygenassist_xmm(tcg_env, OP_PTR0, OP_PTR1, imm); } =20 static void gen_STMXCSR(DisasContext *s, CPUX86State *env, X86DecodedInsn = *decode) @@ -1836,14 +1836,14 @@ static void gen_STMXCSR(DisasContext *s, CPUX86Stat= e *env, X86DecodedInsn *decod gen_illegal_opcode(s); return; } - gen_helper_update_mxcsr(cpu_env); - tcg_gen_ld32u_tl(s->T0, cpu_env, offsetof(CPUX86State, mxcsr)); + gen_helper_update_mxcsr(tcg_env); + tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, mxcsr)); } =20 static void gen_VAESIMC(DisasContext *s, CPUX86State *env, X86DecodedInsn = *decode) { assert(!s->vex_l); - gen_helper_aesimc_xmm(cpu_env, OP_PTR0, OP_PTR2); + gen_helper_aesimc_xmm(tcg_env, OP_PTR0, OP_PTR2); } =20 /* @@ -1903,32 +1903,32 @@ static void gen_VCMP(DisasContext *s, CPUX86State *= env, X86DecodedInsn *decode) s->prefix & PREFIX_REPNZ ? 3 /* sd */ : !!(s->prefix & PREFIX_DATA) /* pd */ + (s->vex_l << 2); =20 - gen_helper_cmp_funcs[index][b](cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); + gen_helper_cmp_funcs[index][b](tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); } =20 static void gen_VCOMI(DisasContext *s, CPUX86State *env, X86DecodedInsn *d= ecode) { SSEFunc_0_epp fn; fn =3D s->prefix & PREFIX_DATA ? gen_helper_comisd : gen_helper_comiss; - fn(cpu_env, OP_PTR1, OP_PTR2); + fn(tcg_env, OP_PTR1, OP_PTR2); set_cc_op(s, CC_OP_EFLAGS); } =20 static void gen_VCVTPD2PS(DisasContext *s, CPUX86State *env, X86DecodedIns= n *decode) { if (s->vex_l) { - gen_helper_cvtpd2ps_ymm(cpu_env, OP_PTR0, OP_PTR2); + gen_helper_cvtpd2ps_ymm(tcg_env, OP_PTR0, OP_PTR2); } else { - gen_helper_cvtpd2ps_xmm(cpu_env, OP_PTR0, OP_PTR2); + gen_helper_cvtpd2ps_xmm(tcg_env, OP_PTR0, OP_PTR2); } } =20 static void gen_VCVTPS2PD(DisasContext *s, CPUX86State *env, X86DecodedIns= n *decode) { if (s->vex_l) { - gen_helper_cvtps2pd_ymm(cpu_env, OP_PTR0, OP_PTR2); + gen_helper_cvtps2pd_ymm(tcg_env, OP_PTR0, OP_PTR2); } else { - gen_helper_cvtps2pd_xmm(cpu_env, OP_PTR0, OP_PTR2); + gen_helper_cvtps2pd_xmm(tcg_env, OP_PTR0, OP_PTR2); } } =20 @@ -1948,12 +1948,12 @@ static void gen_VCVTPS2PH(DisasContext *s, CPUX86St= ate *env, X86DecodedInsn *dec =20 static void gen_VCVTSD2SS(DisasContext *s, CPUX86State *env, X86DecodedIns= n *decode) { - gen_helper_cvtsd2ss(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); + gen_helper_cvtsd2ss(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); } =20 static void gen_VCVTSS2SD(DisasContext *s, CPUX86State *env, X86DecodedIns= n *decode) { - gen_helper_cvtss2sd(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2); + gen_helper_cvtss2sd(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2); } =20 static void gen_VCVTSI2Sx(DisasContext *s, CPUX86State *env, X86DecodedIns= n *decode) @@ -1967,9 +1967,9 @@ static void gen_VCVTSI2Sx(DisasContext *s, CPUX86Stat= e *env, X86DecodedInsn *dec MemOp ot =3D decode->op[2].ot; if (ot =3D=3D MO_64) { if (s->prefix & PREFIX_REPNZ) { - gen_helper_cvtsq2sd(cpu_env, OP_PTR0, s->T1); + gen_helper_cvtsq2sd(tcg_env, OP_PTR0, s->T1); } else { - gen_helper_cvtsq2ss(cpu_env, OP_PTR0, s->T1); + gen_helper_cvtsq2ss(tcg_env, OP_PTR0, s->T1); } return; } @@ -1980,9 +1980,9 @@ static void gen_VCVTSI2Sx(DisasContext *s, CPUX86Stat= e *env, X86DecodedInsn *dec #endif =20 if (s->prefix & PREFIX_REPNZ) { - gen_helper_cvtsi2sd(cpu_env, OP_PTR0, in); + gen_helper_cvtsi2sd(tcg_env, OP_PTR0, in); } else { - gen_helper_cvtsi2ss(cpu_env, OP_PTR0, in); + gen_helper_cvtsi2ss(tcg_env, OP_PTR0, in); } } =20 @@ -1996,9 +1996,9 @@ static inline void gen_VCVTtSx2SI(DisasContext *s, CP= UX86State *env, X86DecodedI MemOp ot =3D decode->op[0].ot; if (ot =3D=3D MO_64) { if (s->prefix & PREFIX_REPNZ) { - sd2sq(s->T0, cpu_env, OP_PTR2); + sd2sq(s->T0, tcg_env, OP_PTR2); } else { - ss2sq(s->T0, cpu_env, OP_PTR2); + ss2sq(s->T0, tcg_env, OP_PTR2); } return; } @@ -2008,9 +2008,9 @@ static inline void gen_VCVTtSx2SI(DisasContext *s, CP= UX86State *env, X86DecodedI out =3D s->T0; #endif if (s->prefix & PREFIX_REPNZ) { - sd2si(out, cpu_env, OP_PTR2); + sd2si(out, tcg_env, OP_PTR2); } else { - ss2si(out, cpu_env, OP_PTR2); + ss2si(out, tcg_env, OP_PTR2); } #ifdef TARGET_X86_64 tcg_gen_extu_i32_tl(s->T0, out); @@ -2072,7 +2072,7 @@ static void gen_vinsertps(DisasContext *s, CPUX86Stat= e *env, X86DecodedInsn *dec } =20 if (new_mask !=3D (val & 15)) { - tcg_gen_st_i32(s->tmp2_i32, cpu_env, + tcg_gen_st_i32(s->tmp2_i32, tcg_env, vector_elem_offset(&decode->op[0], MO_32, dest_word= )); } =20 @@ -2081,7 +2081,7 @@ static void gen_vinsertps(DisasContext *s, CPUX86Stat= e *env, X86DecodedInsn *dec int i; for (i =3D 0; i < 4; i++) { if ((val >> i) & 1) { - tcg_gen_st_i32(zero, cpu_env, + tcg_gen_st_i32(zero, tcg_env, vector_elem_offset(&decode->op[0], MO_32, i= )); } } @@ -2091,7 +2091,7 @@ static void gen_vinsertps(DisasContext *s, CPUX86Stat= e *env, X86DecodedInsn *dec static void gen_VINSERTPS_r(DisasContext *s, CPUX86State *env, X86DecodedI= nsn *decode) { int val =3D decode->immediate; - tcg_gen_ld_i32(s->tmp2_i32, cpu_env, + tcg_gen_ld_i32(s->tmp2_i32, tcg_env, vector_elem_offset(&decode->op[2], MO_32, (val >> 6) & = 3)); gen_vinsertps(s, env, decode); } @@ -2117,9 +2117,9 @@ static inline void gen_maskmov(DisasContext *s, CPUX8= 6State *env, X86DecodedInsn SSEFunc_0_eppt xmm, SSEFunc_0_eppt ymm) { if (!s->vex_l) { - xmm(cpu_env, OP_PTR2, OP_PTR1, s->A0); + xmm(tcg_env, OP_PTR2, OP_PTR1, s->A0); } else { - ymm(cpu_env, OP_PTR2, OP_PTR1, s->A0); + ymm(tcg_env, OP_PTR2, OP_PTR1, s->A0); } } =20 @@ -2137,8 +2137,8 @@ static void gen_VMOVHPx_ld(DisasContext *s, CPUX86Sta= te *env, X86DecodedInsn *de { gen_ldq_env_A0(s, decode->op[0].offset + offsetof(XMMReg, XMM_Q(1))); if (decode->op[0].offset !=3D decode->op[1].offset) { - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offset= of(XMMReg, XMM_Q(0))); - tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offset= of(XMMReg, XMM_Q(0))); + tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offset= of(XMMReg, XMM_Q(0))); + tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offset= of(XMMReg, XMM_Q(0))); } } =20 @@ -2150,32 +2150,32 @@ static void gen_VMOVHPx_st(DisasContext *s, CPUX86S= tate *env, X86DecodedInsn *de static void gen_VMOVHPx(DisasContext *s, CPUX86State *env, X86DecodedInsn = *decode) { if (decode->op[0].offset !=3D decode->op[2].offset) { - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset + offset= of(XMMReg, XMM_Q(1))); - tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offset= of(XMMReg, XMM_Q(1))); + tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offset= of(XMMReg, XMM_Q(1))); + tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offset= of(XMMReg, XMM_Q(1))); } if (decode->op[0].offset !=3D decode->op[1].offset) { - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offset= of(XMMReg, XMM_Q(0))); - tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offset= of(XMMReg, XMM_Q(0))); + tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offset= of(XMMReg, XMM_Q(0))); + tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offset= of(XMMReg, XMM_Q(0))); } } =20 static void gen_VMOVHLPS(DisasContext *s, CPUX86State *env, X86DecodedInsn= *decode) { - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset + offsetof(X= MMReg, XMM_Q(1))); - tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(X= MMReg, XMM_Q(0))); + tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offsetof(X= MMReg, XMM_Q(1))); + tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(X= MMReg, XMM_Q(0))); if (decode->op[0].offset !=3D decode->op[1].offset) { - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offset= of(XMMReg, XMM_Q(1))); - tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offset= of(XMMReg, XMM_Q(1))); + tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offset= of(XMMReg, XMM_Q(1))); + tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offset= of(XMMReg, XMM_Q(1))); } } =20 static void gen_VMOVLHPS(DisasContext *s, CPUX86State *env, X86DecodedInsn= *decode) { - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset); - tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(X= MMReg, XMM_Q(1))); + tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset); + tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(X= MMReg, XMM_Q(1))); if (decode->op[0].offset !=3D decode->op[1].offset) { - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[1].offset + offset= of(XMMReg, XMM_Q(0))); - tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offset= of(XMMReg, XMM_Q(0))); + tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[1].offset + offset= of(XMMReg, XMM_Q(0))); + tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offset= of(XMMReg, XMM_Q(0))); } } =20 @@ -2188,9 +2188,9 @@ static void gen_VMOVLPx(DisasContext *s, CPUX86State = *env, X86DecodedInsn *decod { int vec_len =3D vector_len(s, decode); =20 - tcg_gen_ld_i64(s->tmp1_i64, cpu_env, decode->op[2].offset + offsetof(X= MMReg, XMM_Q(0))); + tcg_gen_ld_i64(s->tmp1_i64, tcg_env, decode->op[2].offset + offsetof(X= MMReg, XMM_Q(0))); tcg_gen_gvec_mov(MO_64, decode->op[0].offset, decode->op[1].offset, ve= c_len, vec_len); - tcg_gen_st_i64(s->tmp1_i64, cpu_env, decode->op[0].offset + offsetof(X= MMReg, XMM_Q(0))); + tcg_gen_st_i64(s->tmp1_i64, tcg_env, decode->op[0].offset + offsetof(X= MMReg, XMM_Q(0))); } =20 static void gen_VMOVLPx_ld(DisasContext *s, CPUX86State *env, X86DecodedIn= sn *decode) @@ -2266,21 +2266,21 @@ static void gen_VPERM2x128(DisasContext *s, CPUX86S= tate *env, X86DecodedInsn *de static void gen_VPHMINPOSUW(DisasContext *s, CPUX86State *env, X86DecodedI= nsn *decode) { assert(!s->vex_l); - gen_helper_phminposuw_xmm(cpu_env, OP_PTR0, OP_PTR2); + gen_helper_phminposuw_xmm(tcg_env, OP_PTR0, OP_PTR2); } =20 static void gen_VROUNDSD(DisasContext *s, CPUX86State *env, X86DecodedInsn= *decode) { TCGv_i32 imm =3D tcg_constant8u_i32(decode->immediate); assert(!s->vex_l); - gen_helper_roundsd_xmm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); + gen_helper_roundsd_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); } =20 static void gen_VROUNDSS(DisasContext *s, CPUX86State *env, X86DecodedInsn= *decode) { TCGv_i32 imm =3D tcg_constant8u_i32(decode->immediate); assert(!s->vex_l); - gen_helper_roundss_xmm(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); + gen_helper_roundss_xmm(tcg_env, OP_PTR0, OP_PTR1, OP_PTR2, imm); } =20 static void gen_VSHUF(DisasContext *s, CPUX86State *env, X86DecodedInsn *d= ecode) @@ -2297,7 +2297,7 @@ static void gen_VUCOMI(DisasContext *s, CPUX86State *= env, X86DecodedInsn *decode { SSEFunc_0_epp fn; fn =3D s->prefix & PREFIX_DATA ? gen_helper_ucomisd : gen_helper_ucomi= ss; - fn(cpu_env, OP_PTR1, OP_PTR2); + fn(tcg_env, OP_PTR1, OP_PTR2); set_cc_op(s, CC_OP_EFLAGS); } =20 @@ -2305,7 +2305,7 @@ static void gen_VZEROALL(DisasContext *s, CPUX86State= *env, X86DecodedInsn *deco { TCGv_ptr ptr =3D tcg_temp_new_ptr(); =20 - tcg_gen_addi_ptr(ptr, cpu_env, offsetof(CPUX86State, xmm_regs)); + tcg_gen_addi_ptr(ptr, tcg_env, offsetof(CPUX86State, xmm_regs)); gen_helper_memset(ptr, ptr, tcg_constant_i32(0), tcg_constant_ptr(CPU_NB_REGS * sizeof(ZMMReg))); } diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loonga= rch/insn_trans/trans_atomic.c.inc index 40085190f6..80c2e286fd 100644 --- a/target/loongarch/insn_trans/trans_atomic.c.inc +++ b/target/loongarch/insn_trans/trans_atomic.c.inc @@ -10,8 +10,8 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp = mop) TCGv t0 =3D make_address_i(ctx, src1, a->imm); =20 tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, mop); - tcg_gen_st_tl(t0, cpu_env, offsetof(CPULoongArchState, lladdr)); - tcg_gen_st_tl(dest, cpu_env, offsetof(CPULoongArchState, llval)); + tcg_gen_st_tl(t0, tcg_env, offsetof(CPULoongArchState, lladdr)); + tcg_gen_st_tl(dest, tcg_env, offsetof(CPULoongArchState, llval)); gen_set_gpr(a->rd, dest, EXT_NONE); =20 return true; diff --git a/target/loongarch/insn_trans/trans_branch.c.inc b/target/loonga= rch/insn_trans/trans_branch.c.inc index a4fd2092e5..221e5159db 100644 --- a/target/loongarch/insn_trans/trans_branch.c.inc +++ b/target/loongarch/insn_trans/trans_branch.c.inc @@ -66,7 +66,7 @@ static bool gen_cz_bc(DisasContext *ctx, arg_c_offs *a, T= CGCond cond) TCGv src1 =3D tcg_temp_new(); TCGv src2 =3D tcg_constant_tl(0); =20 - tcg_gen_ld8u_tl(src1, cpu_env, + tcg_gen_ld8u_tl(src1, tcg_env, offsetof(CPULoongArchState, cf[a->cj])); gen_bc(ctx, src1, src2, a->offs, cond); return true; diff --git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongar= ch/insn_trans/trans_extra.c.inc index dd5d02e88c..cfa361fecf 100644 --- a/target/loongarch/insn_trans/trans_extra.c.inc +++ b/target/loongarch/insn_trans/trans_extra.c.inc @@ -24,7 +24,7 @@ static bool trans_asrtle_d(DisasContext *ctx, arg_asrtle_= d * a) return false; } =20 - gen_helper_asrtle_d(cpu_env, src1, src2); + gen_helper_asrtle_d(tcg_env, src1, src2); return true; } =20 @@ -37,7 +37,7 @@ static bool trans_asrtgt_d(DisasContext *ctx, arg_asrtgt_= d * a) return false; } =20 - gen_helper_asrtgt_d(cpu_env, src1, src2); + gen_helper_asrtgt_d(tcg_env, src1, src2); return true; } =20 @@ -48,11 +48,11 @@ static bool gen_rdtime(DisasContext *ctx, arg_rr *a, TCGv dst2 =3D gpr_dst(ctx, a->rj, EXT_NONE); =20 translator_io_start(&ctx->base); - gen_helper_rdtime_d(dst1, cpu_env); + gen_helper_rdtime_d(dst1, tcg_env); if (word) { tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32); } - tcg_gen_ld_i64(dst2, cpu_env, offsetof(CPULoongArchState, CSR_TID)); + tcg_gen_ld_i64(dst2, tcg_env, offsetof(CPULoongArchState, CSR_TID)); =20 return true; } @@ -77,7 +77,7 @@ static bool trans_cpucfg(DisasContext *ctx, arg_cpucfg *a) TCGv dest =3D gpr_dst(ctx, a->rd, EXT_NONE); TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); =20 - gen_helper_cpucfg(dest, cpu_env, src1); + gen_helper_cpucfg(dest, tcg_env, src1); gen_set_gpr(a->rd, dest, EXT_NONE); =20 return true; diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loonga= rch/insn_trans/trans_farith.c.inc index a7ced99fd3..f4a0dea727 100644 --- a/target/loongarch/insn_trans/trans_farith.c.inc +++ b/target/loongarch/insn_trans/trans_farith.c.inc @@ -23,7 +23,7 @@ static bool gen_fff(DisasContext *ctx, arg_fff *a, =20 CHECK_FPE; =20 - func(dest, cpu_env, src1, src2); + func(dest, tcg_env, src1, src2); set_fpr(a->fd, dest); =20 return true; @@ -37,7 +37,7 @@ static bool gen_ff(DisasContext *ctx, arg_ff *a, =20 CHECK_FPE; =20 - func(dest, cpu_env, src); + func(dest, tcg_env, src); set_fpr(a->fd, dest); =20 return true; @@ -55,7 +55,7 @@ static bool gen_muladd(DisasContext *ctx, arg_ffff *a, =20 CHECK_FPE; =20 - func(dest, cpu_env, src1, src2, src3, tflag); + func(dest, tcg_env, src1, src2, src3, tflag); set_fpr(a->fd, dest); =20 return true; diff --git a/target/loongarch/insn_trans/trans_fcmp.c.inc b/target/loongarc= h/insn_trans/trans_fcmp.c.inc index 43d5866a67..3babf69e4a 100644 --- a/target/loongarch/insn_trans/trans_fcmp.c.inc +++ b/target/loongarch/insn_trans/trans_fcmp.c.inc @@ -41,9 +41,9 @@ static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp= _cond_s *a) fn =3D (a->fcond & 1 ? gen_helper_fcmp_s_s : gen_helper_fcmp_c_s); flags =3D get_fcmp_flags(a->fcond >> 1); =20 - fn(var, cpu_env, src1, src2, tcg_constant_i32(flags)); + fn(var, tcg_env, src1, src2, tcg_constant_i32(flags)); =20 - tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd])); + tcg_gen_st8_tl(var, tcg_env, offsetof(CPULoongArchState, cf[a->cd])); return true; } =20 @@ -65,8 +65,8 @@ static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp= _cond_d *a) fn =3D (a->fcond & 1 ? gen_helper_fcmp_s_d : gen_helper_fcmp_c_d); flags =3D get_fcmp_flags(a->fcond >> 1); =20 - fn(var, cpu_env, src1, src2, tcg_constant_i32(flags)); + fn(var, tcg_env, src1, src2, tcg_constant_i32(flags)); =20 - tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd])); + tcg_gen_st8_tl(var, tcg_env, offsetof(CPULoongArchState, cf[a->cd])); return true; } diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loong= arch/insn_trans/trans_fmemory.c.inc index 5ddb8a473b..13452bc7e5 100644 --- a/target/loongarch/insn_trans/trans_fmemory.c.inc +++ b/target/loongarch/insn_trans/trans_fmemory.c.inc @@ -81,7 +81,7 @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, M= emOp mop) =20 CHECK_FPE; =20 - gen_helper_asrtgt_d(cpu_env, src1, src2); + gen_helper_asrtgt_d(tcg_env, src1, src2); addr =3D make_address_x(ctx, src1, src2); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); maybe_nanbox_load(dest, mop); @@ -99,7 +99,7 @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a, = MemOp mop) =20 CHECK_FPE; =20 - gen_helper_asrtgt_d(cpu_env, src1, src2); + gen_helper_asrtgt_d(tcg_env, src1, src2); addr =3D make_address_x(ctx, src1, src2); tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop); =20 @@ -115,7 +115,7 @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a,= MemOp mop) =20 CHECK_FPE; =20 - gen_helper_asrtle_d(cpu_env, src1, src2); + gen_helper_asrtle_d(tcg_env, src1, src2); addr =3D make_address_x(ctx, src1, src2); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); maybe_nanbox_load(dest, mop); @@ -133,7 +133,7 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a= , MemOp mop) =20 CHECK_FPE; =20 - gen_helper_asrtle_d(cpu_env, src1, src2); + gen_helper_asrtle_d(tcg_env, src1, src2); addr =3D make_address_x(ctx, src1, src2); tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop); =20 diff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarc= h/insn_trans/trans_fmov.c.inc index 928e127820..5cbd9d3f34 100644 --- a/target/loongarch/insn_trans/trans_fmov.c.inc +++ b/target/loongarch/insn_trans/trans_fmov.c.inc @@ -22,7 +22,7 @@ static bool trans_fsel(DisasContext *ctx, arg_fsel *a) CHECK_FPE; =20 cond =3D tcg_temp_new(); - tcg_gen_ld8u_tl(cond, cpu_env, offsetof(CPULoongArchState, cf[a->ca])); + tcg_gen_ld8u_tl(cond, tcg_env, offsetof(CPULoongArchState, cf[a->ca])); tcg_gen_movcond_tl(TCG_COND_EQ, dest, cond, zero, src1, src2); set_fpr(a->fd, dest); =20 @@ -94,17 +94,17 @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_mov= gr2fcsr *a) CHECK_FPE; =20 if (mask =3D=3D UINT32_MAX) { - tcg_gen_st32_i64(Rj, cpu_env, offsetof(CPULoongArchState, fcsr0)); + tcg_gen_st32_i64(Rj, tcg_env, offsetof(CPULoongArchState, fcsr0)); } else { TCGv_i32 fcsr0 =3D tcg_temp_new_i32(); TCGv_i32 temp =3D tcg_temp_new_i32(); =20 - tcg_gen_ld_i32(fcsr0, cpu_env, offsetof(CPULoongArchState, fcsr0)); + tcg_gen_ld_i32(fcsr0, tcg_env, offsetof(CPULoongArchState, fcsr0)); tcg_gen_extrl_i64_i32(temp, Rj); tcg_gen_andi_i32(temp, temp, mask); tcg_gen_andi_i32(fcsr0, fcsr0, ~mask); tcg_gen_or_i32(fcsr0, fcsr0, temp); - tcg_gen_st_i32(fcsr0, cpu_env, offsetof(CPULoongArchState, fcsr0)); + tcg_gen_st_i32(fcsr0, tcg_env, offsetof(CPULoongArchState, fcsr0)); } =20 /* @@ -112,7 +112,7 @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_mov= gr2fcsr *a) * Note that FCSR3 is exactly the rounding mode field. */ if (mask & FCSR0_M3) { - gen_helper_set_rounding_mode(cpu_env); + gen_helper_set_rounding_mode(tcg_env); } return true; } @@ -127,7 +127,7 @@ static bool trans_movfcsr2gr(DisasContext *ctx, arg_mov= fcsr2gr *a) =20 CHECK_FPE; =20 - tcg_gen_ld32u_i64(dest, cpu_env, offsetof(CPULoongArchState, fcsr0)); + tcg_gen_ld32u_i64(dest, tcg_env, offsetof(CPULoongArchState, fcsr0)); tcg_gen_andi_i64(dest, dest, fcsr_mask[a->fcsrs]); gen_set_gpr(a->rd, dest, EXT_NONE); =20 @@ -162,7 +162,7 @@ static bool trans_movfr2cf(DisasContext *ctx, arg_movfr= 2cf *a) =20 t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, src, 0x1); - tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7= ])); + tcg_gen_st8_tl(t0, tcg_env, offsetof(CPULoongArchState, cf[a->cd & 0x7= ])); =20 return true; } @@ -177,7 +177,7 @@ static bool trans_movcf2fr(DisasContext *ctx, arg_movcf= 2fr *a) =20 CHECK_FPE; =20 - tcg_gen_ld8u_tl(dest, cpu_env, + tcg_gen_ld8u_tl(dest, tcg_env, offsetof(CPULoongArchState, cf[a->cj & 0x7])); set_fpr(a->fd, dest); =20 @@ -196,7 +196,7 @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr= 2cf *a) =20 t0 =3D tcg_temp_new(); tcg_gen_andi_tl(t0, gpr_src(ctx, a->rj, EXT_NONE), 0x1); - tcg_gen_st8_tl(t0, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7= ])); + tcg_gen_st8_tl(t0, tcg_env, offsetof(CPULoongArchState, cf[a->cd & 0x7= ])); =20 return true; } @@ -209,7 +209,7 @@ static bool trans_movcf2gr(DisasContext *ctx, arg_movcf= 2gr *a) =20 CHECK_FPE; =20 - tcg_gen_ld8u_tl(gpr_dst(ctx, a->rd, EXT_NONE), cpu_env, + tcg_gen_ld8u_tl(gpr_dst(ctx, a->rd, EXT_NONE), tcg_env, offsetof(CPULoongArchState, cf[a->cj & 0x7])); return true; } diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch= /insn_trans/trans_lsx.c.inc index 5fbf2718f7..76d30f9c93 100644 --- a/target/loongarch/insn_trans/trans_lsx.c.inc +++ b/target/loongarch/insn_trans/trans_lsx.c.inc @@ -25,7 +25,7 @@ static bool gen_vvvv(DisasContext *ctx, arg_vvvv *a, TCGv_i32 va =3D tcg_constant_i32(a->va); =20 CHECK_SXE; - func(cpu_env, vd, vj, vk, va); + func(tcg_env, vd, vj, vk, va); return true; } =20 @@ -38,7 +38,7 @@ static bool gen_vvv(DisasContext *ctx, arg_vvv *a, =20 CHECK_SXE; =20 - func(cpu_env, vd, vj, vk); + func(tcg_env, vd, vj, vk); return true; } =20 @@ -49,7 +49,7 @@ static bool gen_vv(DisasContext *ctx, arg_vv *a, TCGv_i32 vj =3D tcg_constant_i32(a->vj); =20 CHECK_SXE; - func(cpu_env, vd, vj); + func(tcg_env, vd, vj); return true; } =20 @@ -61,7 +61,7 @@ static bool gen_vv_i(DisasContext *ctx, arg_vv_i *a, TCGv_i32 imm =3D tcg_constant_i32(a->imm); =20 CHECK_SXE; - func(cpu_env, vd, vj, imm); + func(tcg_env, vd, vj, imm); return true; } =20 @@ -72,7 +72,7 @@ static bool gen_cv(DisasContext *ctx, arg_cv *a, TCGv_i32 cd =3D tcg_constant_i32(a->cd); =20 CHECK_SXE; - func(cpu_env, cd, vj); + func(tcg_env, cd, vj); return true; } =20 @@ -3903,7 +3903,7 @@ static bool trans_vfcmp_cond_s(DisasContext *ctx, arg= _vvv_fcond *a) =20 fn =3D (a->fcond & 1 ? gen_helper_vfcmp_s_s : gen_helper_vfcmp_c_s); flags =3D get_fcmp_flags(a->fcond >> 1); - fn(cpu_env, vd, vj, vk, tcg_constant_i32(flags)); + fn(tcg_env, vd, vj, vk, tcg_constant_i32(flags)); =20 return true; } @@ -3924,7 +3924,7 @@ static bool trans_vfcmp_cond_d(DisasContext *ctx, arg= _vvv_fcond *a) =20 fn =3D (a->fcond & 1 ? gen_helper_vfcmp_s_d : gen_helper_vfcmp_c_d); flags =3D get_fcmp_flags(a->fcond >> 1); - fn(cpu_env, vd, vj, vk, tcg_constant_i32(flags)); + fn(tcg_env, vd, vj, vk, tcg_constant_i32(flags)); =20 return true; } @@ -3987,7 +3987,7 @@ static bool trans_## NAME (DisasContext *ctx, arg_cv = *a) \ CHECK_SXE; = \ tcg_gen_or_i64(t1, al, ah); = \ tcg_gen_setcondi_i64(COND, t1, t1, 0); = \ - tcg_gen_st8_tl(t1, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7= ])); \ + tcg_gen_st8_tl(t1, tcg_env, offsetof(CPULoongArchState, cf[a->cd & 0x7= ])); \ = \ return true; = \ } @@ -4013,7 +4013,7 @@ static bool trans_vinsgr2vr_b(DisasContext *ctx, arg_= vr_i *a) } =20 CHECK_SXE; - tcg_gen_st8_i64(src, cpu_env, + tcg_gen_st8_i64(src, tcg_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.B(a->imm))= ); return true; } @@ -4027,7 +4027,7 @@ static bool trans_vinsgr2vr_h(DisasContext *ctx, arg_= vr_i *a) } =20 CHECK_SXE; - tcg_gen_st16_i64(src, cpu_env, + tcg_gen_st16_i64(src, tcg_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.H(a->imm))= ); return true; } @@ -4041,7 +4041,7 @@ static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_= vr_i *a) } =20 CHECK_SXE; - tcg_gen_st32_i64(src, cpu_env, + tcg_gen_st32_i64(src, tcg_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.W(a->imm)= )); return true; } @@ -4055,7 +4055,7 @@ static bool trans_vinsgr2vr_d(DisasContext *ctx, arg_= vr_i *a) } =20 CHECK_SXE; - tcg_gen_st_i64(src, cpu_env, + tcg_gen_st_i64(src, tcg_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.D(a->imm))); return true; } @@ -4069,7 +4069,7 @@ static bool trans_vpickve2gr_b(DisasContext *ctx, arg= _rv_i *a) } =20 CHECK_SXE; - tcg_gen_ld8s_i64(dst, cpu_env, + tcg_gen_ld8s_i64(dst, tcg_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm)= )); return true; } @@ -4083,7 +4083,7 @@ static bool trans_vpickve2gr_h(DisasContext *ctx, arg= _rv_i *a) } =20 CHECK_SXE; - tcg_gen_ld16s_i64(dst, cpu_env, + tcg_gen_ld16s_i64(dst, tcg_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm= ))); return true; } @@ -4097,7 +4097,7 @@ static bool trans_vpickve2gr_w(DisasContext *ctx, arg= _rv_i *a) } =20 CHECK_SXE; - tcg_gen_ld32s_i64(dst, cpu_env, + tcg_gen_ld32s_i64(dst, tcg_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm= ))); return true; } @@ -4111,7 +4111,7 @@ static bool trans_vpickve2gr_d(DisasContext *ctx, arg= _rv_i *a) } =20 CHECK_SXE; - tcg_gen_ld_i64(dst, cpu_env, + tcg_gen_ld_i64(dst, tcg_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm))); return true; } @@ -4125,7 +4125,7 @@ static bool trans_vpickve2gr_bu(DisasContext *ctx, ar= g_rv_i *a) } =20 CHECK_SXE; - tcg_gen_ld8u_i64(dst, cpu_env, + tcg_gen_ld8u_i64(dst, tcg_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm)= )); return true; } @@ -4139,7 +4139,7 @@ static bool trans_vpickve2gr_hu(DisasContext *ctx, ar= g_rv_i *a) } =20 CHECK_SXE; - tcg_gen_ld16u_i64(dst, cpu_env, + tcg_gen_ld16u_i64(dst, tcg_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm= ))); return true; } @@ -4153,7 +4153,7 @@ static bool trans_vpickve2gr_wu(DisasContext *ctx, ar= g_rv_i *a) } =20 CHECK_SXE; - tcg_gen_ld32u_i64(dst, cpu_env, + tcg_gen_ld32u_i64(dst, tcg_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm= ))); return true; } @@ -4167,7 +4167,7 @@ static bool trans_vpickve2gr_du(DisasContext *ctx, ar= g_rv_i *a) } =20 CHECK_SXE; - tcg_gen_ld_i64(dst, cpu_env, + tcg_gen_ld_i64(dst, tcg_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm))); return true; } @@ -4266,7 +4266,7 @@ static bool gen_vreplve(DisasContext *ctx, arg_vvr *a= , int vece, int bit, } =20 tcg_gen_trunc_i64_ptr(t1, t0); - tcg_gen_add_ptr(t1, t1, cpu_env); + tcg_gen_add_ptr(t1, t1, tcg_env); func(t2, t1, vec_full_offset(a->vj)); tcg_gen_gvec_dup_i64(vece, vec_full_offset(a->vd), 16, ctx->vl/8, t2); =20 @@ -4542,7 +4542,7 @@ static bool trans_## NAME (DisasContext *ctx, arg_vr_= ii *a) \ = \ addr =3D make_address_i(ctx, addr, a->imm); = \ = \ - tcg_gen_ld_i64(val, cpu_env, = \ + tcg_gen_ld_i64(val, tcg_env, = \ offsetof(CPULoongArchState, fpr[a->vd].vreg.E(a->imm2))= ); \ tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, MO); = \ = \ diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loonga= rch/insn_trans/trans_memory.c.inc index d9d062235a..c3de1404ea 100644 --- a/target/loongarch/insn_trans/trans_memory.c.inc +++ b/target/loongarch/insn_trans/trans_memory.c.inc @@ -57,7 +57,7 @@ static bool gen_load_gt(DisasContext *ctx, arg_rrr *a, Me= mOp mop) TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); =20 - gen_helper_asrtgt_d(cpu_env, src1, src2); + gen_helper_asrtgt_d(tcg_env, src1, src2); src1 =3D make_address_i(ctx, src1, 0); tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); @@ -71,7 +71,7 @@ static bool gen_load_le(DisasContext *ctx, arg_rrr *a, Me= mOp mop) TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); =20 - gen_helper_asrtle_d(cpu_env, src1, src2); + gen_helper_asrtle_d(tcg_env, src1, src2); src1 =3D make_address_i(ctx, src1, 0); tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); @@ -85,7 +85,7 @@ static bool gen_store_gt(DisasContext *ctx, arg_rrr *a, M= emOp mop) TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); =20 - gen_helper_asrtgt_d(cpu_env, src1, src2); + gen_helper_asrtgt_d(tcg_env, src1, src2); src1 =3D make_address_i(ctx, src1, 0); tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop); =20 @@ -98,7 +98,7 @@ static bool gen_store_le(DisasContext *ctx, arg_rrr *a, M= emOp mop) TCGv src1 =3D gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 =3D gpr_src(ctx, a->rk, EXT_NONE); =20 - gen_helper_asrtle_d(cpu_env, src1, src2); + gen_helper_asrtle_d(tcg_env, src1, src2); src1 =3D make_address_i(ctx, src1, 0); tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop); =20 diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/lo= ongarch/insn_trans/trans_privileged.c.inc index 4cb701b4b5..01d457212b 100644 --- a/target/loongarch/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/insn_trans/trans_privileged.c.inc @@ -203,9 +203,9 @@ static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a) check_csr_flags(ctx, csr, false); dest =3D gpr_dst(ctx, a->rd, EXT_NONE); if (csr->readfn) { - csr->readfn(dest, cpu_env); + csr->readfn(dest, tcg_env); } else { - tcg_gen_ld_tl(dest, cpu_env, csr->offset); + tcg_gen_ld_tl(dest, tcg_env, csr->offset); } } gen_set_gpr(a->rd, dest, EXT_NONE); @@ -233,11 +233,11 @@ static bool trans_csrwr(DisasContext *ctx, arg_csrwr = *a) src1 =3D gpr_src(ctx, a->rd, EXT_NONE); if (csr->writefn) { dest =3D gpr_dst(ctx, a->rd, EXT_NONE); - csr->writefn(dest, cpu_env, src1); + csr->writefn(dest, tcg_env, src1); } else { dest =3D tcg_temp_new(); - tcg_gen_ld_tl(dest, cpu_env, csr->offset); - tcg_gen_st_tl(src1, cpu_env, csr->offset); + tcg_gen_ld_tl(dest, tcg_env, csr->offset); + tcg_gen_st_tl(src1, tcg_env, csr->offset); } gen_set_gpr(a->rd, dest, EXT_NONE); return true; @@ -272,15 +272,15 @@ static bool trans_csrxchg(DisasContext *ctx, arg_csrx= chg *a) newv =3D tcg_temp_new(); temp =3D tcg_temp_new(); =20 - tcg_gen_ld_tl(oldv, cpu_env, csr->offset); + tcg_gen_ld_tl(oldv, tcg_env, csr->offset); tcg_gen_and_tl(newv, src1, mask); tcg_gen_andc_tl(temp, oldv, mask); tcg_gen_or_tl(newv, newv, temp); =20 if (csr->writefn) { - csr->writefn(oldv, cpu_env, newv); + csr->writefn(oldv, tcg_env, newv); } else { - tcg_gen_st_tl(newv, cpu_env, csr->offset); + tcg_gen_st_tl(newv, tcg_env, csr->offset); } gen_set_gpr(a->rd, oldv, EXT_NONE); return true; @@ -295,7 +295,7 @@ static bool gen_iocsrrd(DisasContext *ctx, arg_rr *a, if (check_plv(ctx)) { return false; } - func(dest, cpu_env, src1); + func(dest, tcg_env, src1); return true; } =20 @@ -308,7 +308,7 @@ static bool gen_iocsrwr(DisasContext *ctx, arg_rr *a, if (check_plv(ctx)) { return false; } - func(cpu_env, addr, val); + func(tcg_env, addr, val); return true; } =20 @@ -334,7 +334,7 @@ static bool trans_tlbsrch(DisasContext *ctx, arg_tlbsrc= h *a) if (check_plv(ctx)) { return false; } - gen_helper_tlbsrch(cpu_env); + gen_helper_tlbsrch(tcg_env); return true; } =20 @@ -343,7 +343,7 @@ static bool trans_tlbrd(DisasContext *ctx, arg_tlbrd *a) if (check_plv(ctx)) { return false; } - gen_helper_tlbrd(cpu_env); + gen_helper_tlbrd(tcg_env); return true; } =20 @@ -352,7 +352,7 @@ static bool trans_tlbwr(DisasContext *ctx, arg_tlbwr *a) if (check_plv(ctx)) { return false; } - gen_helper_tlbwr(cpu_env); + gen_helper_tlbwr(tcg_env); check_mmu_idx(ctx); return true; } @@ -362,7 +362,7 @@ static bool trans_tlbfill(DisasContext *ctx, arg_tlbfil= l *a) if (check_plv(ctx)) { return false; } - gen_helper_tlbfill(cpu_env); + gen_helper_tlbfill(tcg_env); check_mmu_idx(ctx); return true; } @@ -372,7 +372,7 @@ static bool trans_tlbclr(DisasContext *ctx, arg_tlbclr = *a) if (check_plv(ctx)) { return false; } - gen_helper_tlbclr(cpu_env); + gen_helper_tlbclr(tcg_env); check_mmu_idx(ctx); return true; } @@ -382,7 +382,7 @@ static bool trans_tlbflush(DisasContext *ctx, arg_tlbfl= ush *a) if (check_plv(ctx)) { return false; } - gen_helper_tlbflush(cpu_env); + gen_helper_tlbflush(tcg_env); check_mmu_idx(ctx); return true; } @@ -399,22 +399,22 @@ static bool trans_invtlb(DisasContext *ctx, arg_invtl= b *a) switch (a->imm) { case 0: case 1: - gen_helper_invtlb_all(cpu_env); + gen_helper_invtlb_all(tcg_env); break; case 2: - gen_helper_invtlb_all_g(cpu_env, tcg_constant_i32(1)); + gen_helper_invtlb_all_g(tcg_env, tcg_constant_i32(1)); break; case 3: - gen_helper_invtlb_all_g(cpu_env, tcg_constant_i32(0)); + gen_helper_invtlb_all_g(tcg_env, tcg_constant_i32(0)); break; case 4: - gen_helper_invtlb_all_asid(cpu_env, rj); + gen_helper_invtlb_all_asid(tcg_env, rj); break; case 5: - gen_helper_invtlb_page_asid(cpu_env, rj, rk); + gen_helper_invtlb_page_asid(tcg_env, rj, rk); break; case 6: - gen_helper_invtlb_page_asid_or_g(cpu_env, rj, rk); + gen_helper_invtlb_page_asid_or_g(tcg_env, rj, rk); break; default: return false; @@ -444,7 +444,7 @@ static bool trans_ldpte(DisasContext *ctx, arg_ldpte *a) if (check_plv(ctx)) { return false; } - gen_helper_ldpte(cpu_env, src1, tcg_constant_tl(a->imm), mem_idx); + gen_helper_ldpte(tcg_env, src1, tcg_constant_tl(a->imm), mem_idx); return true; } =20 @@ -461,7 +461,7 @@ static bool trans_lddir(DisasContext *ctx, arg_lddir *a) if (check_plv(ctx)) { return false; } - gen_helper_lddir(dest, cpu_env, src, tcg_constant_tl(a->imm), mem_idx); + gen_helper_lddir(dest, tcg_env, src, tcg_constant_tl(a->imm), mem_idx); return true; } =20 @@ -470,7 +470,7 @@ static bool trans_ertn(DisasContext *ctx, arg_ertn *a) if (check_plv(ctx)) { return false; } - gen_helper_ertn(cpu_env); + gen_helper_ertn(tcg_env); ctx->base.is_jmp =3D DISAS_EXIT; return true; } @@ -491,7 +491,7 @@ static bool trans_idle(DisasContext *ctx, arg_idle *a) } =20 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4); - gen_helper_idle(cpu_env); + gen_helper_idle(tcg_env); ctx->base.is_jmp =3D DISAS_NORETURN; return true; } diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/mi= cromips_translate.c.inc index 211d102cf6..7510831701 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -710,17 +710,17 @@ static void gen_ldst_multiple(DisasContext *ctx, uint= 32_t opc, int reglist, save_cpu_state(ctx, 1); switch (opc) { case LWM32: - gen_helper_lwm(cpu_env, t0, t1, t2); + gen_helper_lwm(tcg_env, t0, t1, t2); break; case SWM32: - gen_helper_swm(cpu_env, t0, t1, t2); + gen_helper_swm(tcg_env, t0, t1, t2); break; #ifdef TARGET_MIPS64 case LDM: - gen_helper_ldm(cpu_env, t0, t1, t2); + gen_helper_ldm(tcg_env, t0, t1, t2); break; case SDM: - gen_helper_sdm(cpu_env, t0, t1, t2); + gen_helper_sdm(tcg_env, t0, t1, t2); break; #endif } @@ -1271,7 +1271,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasCon= text *ctx, int rt, int rs) TCGv t0 =3D tcg_temp_new(); =20 save_cpu_state(ctx, 1); - gen_helper_di(t0, cpu_env); + gen_helper_di(t0, tcg_env); gen_store_gpr(t0, rs); /* * Stop translation as we may have switched the execution @@ -1286,7 +1286,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasCon= text *ctx, int rt, int rs) TCGv t0 =3D tcg_temp_new(); =20 save_cpu_state(ctx, 1); - gen_helper_ei(t0, cpu_env); + gen_helper_ei(t0, tcg_env); gen_store_gpr(t0, rs); /* * DISAS_STOP isn't sufficient, we need to ensure we break= out diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nan= omips_translate.c.inc index a98dde0d2e..a0f0f35cda 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -1006,8 +1006,8 @@ static void gen_llwp(DisasContext *ctx, uint32_t base= , int16_t offset, } gen_store_gpr(tmp1, reg1); gen_store_gpr(tmp2, reg2); - tcg_gen_st_i64(tval, cpu_env, offsetof(CPUMIPSState, llval_wp)); - tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr)); + tcg_gen_st_i64(tval, tcg_env, offsetof(CPUMIPSState, llval_wp)); + tcg_gen_st_tl(taddr, tcg_env, offsetof(CPUMIPSState, lladdr)); } =20 static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, @@ -1025,7 +1025,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base= , int16_t offset, =20 gen_base_offset_addr(ctx, taddr, base, offset); =20 - tcg_gen_ld_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr)); + tcg_gen_ld_tl(lladdr, tcg_env, offsetof(CPUMIPSState, lladdr)); tcg_gen_brcond_tl(TCG_COND_NE, taddr, lladdr, lab_fail); =20 gen_load_gpr(tmp1, reg1); @@ -1037,7 +1037,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base= , int16_t offset, tcg_gen_concat_tl_i64(tval, tmp1, tmp2); } =20 - tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp)); + tcg_gen_ld_i64(llval, tcg_env, offsetof(CPUMIPSState, llval_wp)); tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval, eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64 | MO_ALIGN); @@ -1053,7 +1053,7 @@ static void gen_scwp(DisasContext *ctx, uint32_t base= , int16_t offset, } gen_set_label(lab_done); tcg_gen_movi_tl(lladdr, -1); - tcg_gen_st_tl(lladdr, cpu_env, offsetof(CPUMIPSState, lladdr)); + tcg_gen_st_tl(lladdr, tcg_env, offsetof(CPUMIPSState, lladdr)); } =20 static void gen_adjust_sp(DisasContext *ctx, int u) @@ -1335,14 +1335,14 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState= *env, DisasContext *ctx) case NM_DVP: if (ctx->vp) { check_cp0_enabled(ctx); - gen_helper_dvp(t0, cpu_env); + gen_helper_dvp(t0, tcg_env); gen_store_gpr(t0, rt); } break; case NM_EVP: if (ctx->vp) { check_cp0_enabled(ctx); - gen_helper_evp(t0, cpu_env); + gen_helper_evp(t0, tcg_env); gen_store_gpr(t0, rt); } break; @@ -1428,7 +1428,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *= env, DisasContext *ctx) } else if (rs =3D=3D 0) { /* DVPE */ check_cp0_mt(ctx); - gen_helper_dvpe(t0, cpu_env); + gen_helper_dvpe(t0, tcg_env); gen_store_gpr(t0, rt); } else { gen_reserved_instruction(ctx); @@ -1443,7 +1443,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *= env, DisasContext *ctx) } else if (rs =3D=3D 0) { /* EVPE */ check_cp0_mt(ctx); - gen_helper_evpe(t0, cpu_env); + gen_helper_evpe(t0, tcg_env); gen_store_gpr(t0, rt); } else { gen_reserved_instruction(ctx); @@ -1485,7 +1485,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *= env, DisasContext *ctx) TCGv t0 =3D tcg_temp_new(); =20 gen_load_gpr(t0, rs); - gen_helper_yield(t0, cpu_env, t0); + gen_helper_yield(t0, tcg_env, t0); gen_store_gpr(t0, rt); } break; @@ -1517,19 +1517,19 @@ static void gen_pool32axf_1_5_nanomips_insn(DisasCo= ntext *ctx, uint32_t opc, switch (opc) { case NM_MAQ_S_W_PHR: check_dsp(ctx); - gen_helper_maq_s_w_phr(t0, v1_t, v0_t, cpu_env); + gen_helper_maq_s_w_phr(t0, v1_t, v0_t, tcg_env); break; case NM_MAQ_S_W_PHL: check_dsp(ctx); - gen_helper_maq_s_w_phl(t0, v1_t, v0_t, cpu_env); + gen_helper_maq_s_w_phl(t0, v1_t, v0_t, tcg_env); break; case NM_MAQ_SA_W_PHR: check_dsp(ctx); - gen_helper_maq_sa_w_phr(t0, v1_t, v0_t, cpu_env); + gen_helper_maq_sa_w_phr(t0, v1_t, v0_t, tcg_env); break; case NM_MAQ_SA_W_PHL: check_dsp(ctx); - gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, cpu_env); + gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, tcg_env); break; default: gen_reserved_instruction(ctx); @@ -1571,11 +1571,11 @@ static void gen_pool32axf_1_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, switch (extract32(ctx->opcode, 12, 2)) { case NM_MTHLIP: tcg_gen_movi_tl(t0, v2 >> 3); - gen_helper_mthlip(t0, v0_t, cpu_env); + gen_helper_mthlip(t0, v0_t, tcg_env); break; case NM_SHILOV: tcg_gen_movi_tl(t0, v2 >> 3); - gen_helper_shilo(t0, v0_t, cpu_env); + gen_helper_shilo(t0, v0_t, tcg_env); break; default: gen_reserved_instruction(ctx); @@ -1588,24 +1588,24 @@ static void gen_pool32axf_1_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, switch (extract32(ctx->opcode, 12, 2)) { case NM_RDDSP: tcg_gen_movi_tl(t0, imm); - gen_helper_rddsp(t0, t0, cpu_env); + gen_helper_rddsp(t0, t0, tcg_env); gen_store_gpr(t0, ret); break; case NM_WRDSP: gen_load_gpr(t0, ret); tcg_gen_movi_tl(t1, imm); - gen_helper_wrdsp(t0, t1, cpu_env); + gen_helper_wrdsp(t0, t1, tcg_env); break; case NM_EXTP: tcg_gen_movi_tl(t0, v2 >> 3); tcg_gen_movi_tl(t1, v1); - gen_helper_extp(t0, t0, t1, cpu_env); + gen_helper_extp(t0, t0, t1, tcg_env); gen_store_gpr(t0, ret); break; case NM_EXTPDP: tcg_gen_movi_tl(t0, v2 >> 3); tcg_gen_movi_tl(t1, v1); - gen_helper_extpdp(t0, t0, t1, cpu_env); + gen_helper_extpdp(t0, t0, t1, tcg_env); gen_store_gpr(t0, ret); break; } @@ -1615,7 +1615,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasContex= t *ctx, uint32_t opc, tcg_gen_movi_tl(t0, v2 >> 2); switch (extract32(ctx->opcode, 12, 1)) { case NM_SHLL_QB: - gen_helper_shll_qb(t0, t0, v0_t, cpu_env); + gen_helper_shll_qb(t0, t0, v0_t, tcg_env); gen_store_gpr(t0, ret); break; case NM_SHRL_QB: @@ -1634,19 +1634,19 @@ static void gen_pool32axf_1_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, tcg_gen_movi_tl(t1, v1); switch (extract32(ctx->opcode, 12, 2)) { case NM_EXTR_W: - gen_helper_extr_w(t0, t0, t1, cpu_env); + gen_helper_extr_w(t0, t0, t1, tcg_env); gen_store_gpr(t0, ret); break; case NM_EXTR_R_W: - gen_helper_extr_r_w(t0, t0, t1, cpu_env); + gen_helper_extr_r_w(t0, t0, t1, tcg_env); gen_store_gpr(t0, ret); break; case NM_EXTR_RS_W: - gen_helper_extr_rs_w(t0, t0, t1, cpu_env); + gen_helper_extr_rs_w(t0, t0, t1, tcg_env); gen_store_gpr(t0, ret); break; case NM_EXTR_S_H: - gen_helper_extr_s_h(t0, t0, t1, cpu_env); + gen_helper_extr_s_h(t0, t0, t1, tcg_env); gen_store_gpr(t0, ret); break; } @@ -1671,19 +1671,19 @@ static void gen_pool32axf_2_multiply(DisasContext *= ctx, uint32_t opc, switch (extract32(ctx->opcode, 9, 3)) { case NM_DPA_W_PH: check_dsp_r2(ctx); - gen_helper_dpa_w_ph(t0, v1, v0, cpu_env); + gen_helper_dpa_w_ph(t0, v1, v0, tcg_env); break; case NM_DPAQ_S_W_PH: check_dsp(ctx); - gen_helper_dpaq_s_w_ph(t0, v1, v0, cpu_env); + gen_helper_dpaq_s_w_ph(t0, v1, v0, tcg_env); break; case NM_DPS_W_PH: check_dsp_r2(ctx); - gen_helper_dps_w_ph(t0, v1, v0, cpu_env); + gen_helper_dps_w_ph(t0, v1, v0, tcg_env); break; case NM_DPSQ_S_W_PH: check_dsp(ctx); - gen_helper_dpsq_s_w_ph(t0, v1, v0, cpu_env); + gen_helper_dpsq_s_w_ph(t0, v1, v0, tcg_env); break; default: gen_reserved_instruction(ctx); @@ -1694,19 +1694,19 @@ static void gen_pool32axf_2_multiply(DisasContext *= ctx, uint32_t opc, switch (extract32(ctx->opcode, 9, 3)) { case NM_DPAX_W_PH: check_dsp_r2(ctx); - gen_helper_dpax_w_ph(t0, v0, v1, cpu_env); + gen_helper_dpax_w_ph(t0, v0, v1, tcg_env); break; case NM_DPAQ_SA_L_W: check_dsp(ctx); - gen_helper_dpaq_sa_l_w(t0, v0, v1, cpu_env); + gen_helper_dpaq_sa_l_w(t0, v0, v1, tcg_env); break; case NM_DPSX_W_PH: check_dsp_r2(ctx); - gen_helper_dpsx_w_ph(t0, v0, v1, cpu_env); + gen_helper_dpsx_w_ph(t0, v0, v1, tcg_env); break; case NM_DPSQ_SA_L_W: check_dsp(ctx); - gen_helper_dpsq_sa_l_w(t0, v0, v1, cpu_env); + gen_helper_dpsq_sa_l_w(t0, v0, v1, tcg_env); break; default: gen_reserved_instruction(ctx); @@ -1717,23 +1717,23 @@ static void gen_pool32axf_2_multiply(DisasContext *= ctx, uint32_t opc, switch (extract32(ctx->opcode, 9, 3)) { case NM_DPAU_H_QBL: check_dsp(ctx); - gen_helper_dpau_h_qbl(t0, v0, v1, cpu_env); + gen_helper_dpau_h_qbl(t0, v0, v1, tcg_env); break; case NM_DPAQX_S_W_PH: check_dsp_r2(ctx); - gen_helper_dpaqx_s_w_ph(t0, v0, v1, cpu_env); + gen_helper_dpaqx_s_w_ph(t0, v0, v1, tcg_env); break; case NM_DPSU_H_QBL: check_dsp(ctx); - gen_helper_dpsu_h_qbl(t0, v0, v1, cpu_env); + gen_helper_dpsu_h_qbl(t0, v0, v1, tcg_env); break; case NM_DPSQX_S_W_PH: check_dsp_r2(ctx); - gen_helper_dpsqx_s_w_ph(t0, v0, v1, cpu_env); + gen_helper_dpsqx_s_w_ph(t0, v0, v1, tcg_env); break; case NM_MULSA_W_PH: check_dsp_r2(ctx); - gen_helper_mulsa_w_ph(t0, v0, v1, cpu_env); + gen_helper_mulsa_w_ph(t0, v0, v1, tcg_env); break; default: gen_reserved_instruction(ctx); @@ -1744,23 +1744,23 @@ static void gen_pool32axf_2_multiply(DisasContext *= ctx, uint32_t opc, switch (extract32(ctx->opcode, 9, 3)) { case NM_DPAU_H_QBR: check_dsp(ctx); - gen_helper_dpau_h_qbr(t0, v1, v0, cpu_env); + gen_helper_dpau_h_qbr(t0, v1, v0, tcg_env); break; case NM_DPAQX_SA_W_PH: check_dsp_r2(ctx); - gen_helper_dpaqx_sa_w_ph(t0, v1, v0, cpu_env); + gen_helper_dpaqx_sa_w_ph(t0, v1, v0, tcg_env); break; case NM_DPSU_H_QBR: check_dsp(ctx); - gen_helper_dpsu_h_qbr(t0, v1, v0, cpu_env); + gen_helper_dpsu_h_qbr(t0, v1, v0, tcg_env); break; case NM_DPSQX_SA_W_PH: check_dsp_r2(ctx); - gen_helper_dpsqx_sa_w_ph(t0, v1, v0, cpu_env); + gen_helper_dpsqx_sa_w_ph(t0, v1, v0, tcg_env); break; case NM_MULSAQ_S_W_PH: check_dsp(ctx); - gen_helper_mulsaq_s_w_ph(t0, v1, v0, cpu_env); + gen_helper_mulsaq_s_w_ph(t0, v1, v0, tcg_env); break; default: gen_reserved_instruction(ctx); @@ -1849,7 +1849,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContex= t *ctx, uint32_t opc, check_dsp(ctx); gen_load_gpr(v1_t, rs); tcg_gen_movi_tl(t0, rd >> 3); - gen_helper_extr_w(t0, t0, v1_t, cpu_env); + gen_helper_extr_w(t0, t0, v1_t, tcg_env); gen_store_gpr(t0, ret); break; } @@ -1904,7 +1904,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContex= t *ctx, uint32_t opc, case NM_EXTRV_R_W: check_dsp(ctx); tcg_gen_movi_tl(t0, rd >> 3); - gen_helper_extr_r_w(t0, t0, v1_t, cpu_env); + gen_helper_extr_r_w(t0, t0, v1_t, tcg_env); gen_store_gpr(t0, ret); break; default: @@ -1924,7 +1924,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContex= t *ctx, uint32_t opc, case NM_EXTPV: check_dsp(ctx); tcg_gen_movi_tl(t0, rd >> 3); - gen_helper_extp(t0, t0, v1_t, cpu_env); + gen_helper_extp(t0, t0, v1_t, tcg_env); gen_store_gpr(t0, ret); break; case NM_MSUB: @@ -1948,7 +1948,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContex= t *ctx, uint32_t opc, case NM_EXTRV_RS_W: check_dsp(ctx); tcg_gen_movi_tl(t0, rd >> 3); - gen_helper_extr_rs_w(t0, t0, v1_t, cpu_env); + gen_helper_extr_rs_w(t0, t0, v1_t, tcg_env); gen_store_gpr(t0, ret); break; } @@ -1965,7 +1965,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContex= t *ctx, uint32_t opc, case NM_EXTPDPV: check_dsp(ctx); tcg_gen_movi_tl(t0, rd >> 3); - gen_helper_extpdp(t0, t0, v1_t, cpu_env); + gen_helper_extpdp(t0, t0, v1_t, tcg_env); gen_store_gpr(t0, ret); break; case NM_MSUBU: @@ -1991,7 +1991,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContex= t *ctx, uint32_t opc, case NM_EXTRV_S_H: check_dsp(ctx); tcg_gen_movi_tl(t0, rd >> 3); - gen_helper_extr_s_h(t0, t0, v1_t, cpu_env); + gen_helper_extr_s_h(t0, t0, v1_t, tcg_env); gen_store_gpr(t0, ret); break; } @@ -2014,17 +2014,17 @@ static void gen_pool32axf_4_nanomips_insn(DisasCont= ext *ctx, uint32_t opc, switch (opc) { case NM_ABSQ_S_QB: check_dsp_r2(ctx); - gen_helper_absq_s_qb(v0_t, v0_t, cpu_env); + gen_helper_absq_s_qb(v0_t, v0_t, tcg_env); gen_store_gpr(v0_t, ret); break; case NM_ABSQ_S_PH: check_dsp(ctx); - gen_helper_absq_s_ph(v0_t, v0_t, cpu_env); + gen_helper_absq_s_ph(v0_t, v0_t, tcg_env); gen_store_gpr(v0_t, ret); break; case NM_ABSQ_S_W: check_dsp(ctx); - gen_helper_absq_s_w(v0_t, v0_t, cpu_env); + gen_helper_absq_s_w(v0_t, v0_t, tcg_env); gen_store_gpr(v0_t, ret); break; case NM_PRECEQ_W_PHL: @@ -2109,7 +2109,7 @@ static void gen_pool32axf_4_nanomips_insn(DisasContex= t *ctx, uint32_t opc, TCGv tv0 =3D tcg_temp_new(); =20 gen_load_gpr(tv0, rt); - gen_helper_insv(v0_t, cpu_env, v0_t, tv0); + gen_helper_insv(v0_t, tcg_env, v0_t, tv0); gen_store_gpr(v0_t, ret); } break; @@ -2243,7 +2243,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState = *env, DisasContext *ctx) TCGv t0 =3D tcg_temp_new(); =20 save_cpu_state(ctx, 1); - gen_helper_di(t0, cpu_env); + gen_helper_di(t0, tcg_env); gen_store_gpr(t0, rt); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; @@ -2255,7 +2255,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState = *env, DisasContext *ctx) TCGv t0 =3D tcg_temp_new(); =20 save_cpu_state(ctx, 1); - gen_helper_ei(t0, cpu_env); + gen_helper_ei(t0, tcg_env); gen_store_gpr(t0, rt); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; @@ -3036,27 +3036,27 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, switch (opc) { case NM_CMP_EQ_PH: check_dsp(ctx); - gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env); + gen_helper_cmp_eq_ph(v1_t, v2_t, tcg_env); break; case NM_CMP_LT_PH: check_dsp(ctx); - gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env); + gen_helper_cmp_lt_ph(v1_t, v2_t, tcg_env); break; case NM_CMP_LE_PH: check_dsp(ctx); - gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env); + gen_helper_cmp_le_ph(v1_t, v2_t, tcg_env); break; case NM_CMPU_EQ_QB: check_dsp(ctx); - gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env); + gen_helper_cmpu_eq_qb(v1_t, v2_t, tcg_env); break; case NM_CMPU_LT_QB: check_dsp(ctx); - gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env); + gen_helper_cmpu_lt_qb(v1_t, v2_t, tcg_env); break; case NM_CMPU_LE_QB: check_dsp(ctx); - gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env); + gen_helper_cmpu_le_qb(v1_t, v2_t, tcg_env); break; case NM_CMPGU_EQ_QB: check_dsp(ctx); @@ -3098,32 +3098,32 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, break; case NM_PICK_QB: check_dsp(ctx); - gen_helper_pick_qb(v1_t, v1_t, v2_t, cpu_env); + gen_helper_pick_qb(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_PICK_PH: check_dsp(ctx); - gen_helper_pick_ph(v1_t, v1_t, v2_t, cpu_env); + gen_helper_pick_ph(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_ADDQ_S_W: check_dsp(ctx); - gen_helper_addq_s_w(v1_t, v1_t, v2_t, cpu_env); + gen_helper_addq_s_w(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_SUBQ_S_W: check_dsp(ctx); - gen_helper_subq_s_w(v1_t, v1_t, v2_t, cpu_env); + gen_helper_subq_s_w(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_ADDSC: check_dsp(ctx); - gen_helper_addsc(v1_t, v1_t, v2_t, cpu_env); + gen_helper_addsc(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_ADDWC: check_dsp(ctx); - gen_helper_addwc(v1_t, v1_t, v2_t, cpu_env); + gen_helper_addwc(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_ADDQ_S_PH: @@ -3131,12 +3131,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, switch (extract32(ctx->opcode, 10, 1)) { case 0: /* ADDQ_PH */ - gen_helper_addq_ph(v1_t, v1_t, v2_t, cpu_env); + gen_helper_addq_ph(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case 1: /* ADDQ_S_PH */ - gen_helper_addq_s_ph(v1_t, v1_t, v2_t, cpu_env); + gen_helper_addq_s_ph(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; } @@ -3176,12 +3176,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, switch (extract32(ctx->opcode, 10, 1)) { case 0: /* ADDU_QB */ - gen_helper_addu_qb(v1_t, v1_t, v2_t, cpu_env); + gen_helper_addu_qb(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case 1: /* ADDU_S_QB */ - gen_helper_addu_s_qb(v1_t, v1_t, v2_t, cpu_env); + gen_helper_addu_s_qb(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; } @@ -3191,12 +3191,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, switch (extract32(ctx->opcode, 10, 1)) { case 0: /* ADDU_PH */ - gen_helper_addu_ph(v1_t, v1_t, v2_t, cpu_env); + gen_helper_addu_ph(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case 1: /* ADDU_S_PH */ - gen_helper_addu_s_ph(v1_t, v1_t, v2_t, cpu_env); + gen_helper_addu_s_ph(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; } @@ -3251,12 +3251,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, switch (extract32(ctx->opcode, 10, 1)) { case 0: /* SUBQ_PH */ - gen_helper_subq_ph(v1_t, v1_t, v2_t, cpu_env); + gen_helper_subq_ph(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case 1: /* SUBQ_S_PH */ - gen_helper_subq_s_ph(v1_t, v1_t, v2_t, cpu_env); + gen_helper_subq_s_ph(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; } @@ -3296,12 +3296,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, switch (extract32(ctx->opcode, 10, 1)) { case 0: /* SUBU_QB */ - gen_helper_subu_qb(v1_t, v1_t, v2_t, cpu_env); + gen_helper_subu_qb(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case 1: /* SUBU_S_QB */ - gen_helper_subu_s_qb(v1_t, v1_t, v2_t, cpu_env); + gen_helper_subu_s_qb(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; } @@ -3311,12 +3311,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, switch (extract32(ctx->opcode, 10, 1)) { case 0: /* SUBU_PH */ - gen_helper_subu_ph(v1_t, v1_t, v2_t, cpu_env); + gen_helper_subu_ph(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case 1: /* SUBU_S_PH */ - gen_helper_subu_s_ph(v1_t, v1_t, v2_t, cpu_env); + gen_helper_subu_s_ph(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; } @@ -3341,12 +3341,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, switch (extract32(ctx->opcode, 10, 1)) { case 0: /* SHLLV_PH */ - gen_helper_shll_ph(v1_t, v1_t, v2_t, cpu_env); + gen_helper_shll_ph(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case 1: /* SHLLV_S_PH */ - gen_helper_shll_s_ph(v1_t, v1_t, v2_t, cpu_env); + gen_helper_shll_s_ph(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; } @@ -3376,32 +3376,32 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, break; case NM_MULEU_S_PH_QBL: check_dsp(ctx); - gen_helper_muleu_s_ph_qbl(v1_t, v1_t, v2_t, cpu_env); + gen_helper_muleu_s_ph_qbl(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_MULEU_S_PH_QBR: check_dsp(ctx); - gen_helper_muleu_s_ph_qbr(v1_t, v1_t, v2_t, cpu_env); + gen_helper_muleu_s_ph_qbr(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_MULQ_RS_PH: check_dsp(ctx); - gen_helper_mulq_rs_ph(v1_t, v1_t, v2_t, cpu_env); + gen_helper_mulq_rs_ph(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_MULQ_S_PH: check_dsp_r2(ctx); - gen_helper_mulq_s_ph(v1_t, v1_t, v2_t, cpu_env); + gen_helper_mulq_s_ph(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_MULQ_RS_W: check_dsp_r2(ctx); - gen_helper_mulq_rs_w(v1_t, v1_t, v2_t, cpu_env); + gen_helper_mulq_rs_w(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_MULQ_S_W: check_dsp_r2(ctx); - gen_helper_mulq_s_w(v1_t, v1_t, v2_t, cpu_env); + gen_helper_mulq_s_w(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_APPEND: @@ -3434,12 +3434,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, break; case NM_SHLLV_QB: check_dsp(ctx); - gen_helper_shll_qb(v1_t, v1_t, v2_t, cpu_env); + gen_helper_shll_qb(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_SHLLV_S_W: check_dsp(ctx); - gen_helper_shll_s_w(v1_t, v1_t, v2_t, cpu_env); + gen_helper_shll_s_w(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_SHILO: @@ -3451,17 +3451,17 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, =20 tcg_gen_movi_tl(tv0, rd >> 3); tcg_gen_movi_tl(tv1, imm); - gen_helper_shilo(tv0, tv1, cpu_env); + gen_helper_shilo(tv0, tv1, tcg_env); } break; case NM_MULEQ_S_W_PHL: check_dsp(ctx); - gen_helper_muleq_s_w_phl(v1_t, v1_t, v2_t, cpu_env); + gen_helper_muleq_s_w_phl(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_MULEQ_S_W_PHR: check_dsp(ctx); - gen_helper_muleq_s_w_phr(v1_t, v1_t, v2_t, cpu_env); + gen_helper_muleq_s_w_phr(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_MUL_S_PH: @@ -3469,12 +3469,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, switch (extract32(ctx->opcode, 10, 1)) { case 0: /* MUL_PH */ - gen_helper_mul_ph(v1_t, v1_t, v2_t, cpu_env); + gen_helper_mul_ph(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case 1: /* MUL_S_PH */ - gen_helper_mul_s_ph(v1_t, v1_t, v2_t, cpu_env); + gen_helper_mul_s_ph(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; } @@ -3496,12 +3496,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, break; case NM_PRECRQ_RS_PH_W: check_dsp(ctx); - gen_helper_precrq_rs_ph_w(v1_t, v1_t, v2_t, cpu_env); + gen_helper_precrq_rs_ph_w(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_PRECRQU_S_QB_PH: check_dsp(ctx); - gen_helper_precrqu_s_qb_ph(v1_t, v1_t, v2_t, cpu_env); + gen_helper_precrqu_s_qb_ph(v1_t, v1_t, v2_t, tcg_env); gen_store_gpr(v1_t, ret); break; case NM_SHRA_R_W: @@ -3532,12 +3532,12 @@ static void gen_pool32a5_nanomips_insn(DisasContext= *ctx, int opc, switch (extract32(ctx->opcode, 10, 2)) { case 0: /* SHLL_PH */ - gen_helper_shll_ph(v1_t, t0, v1_t, cpu_env); + gen_helper_shll_ph(v1_t, t0, v1_t, tcg_env); gen_store_gpr(v1_t, rt); break; case 2: /* SHLL_S_PH */ - gen_helper_shll_s_ph(v1_t, t0, v1_t, cpu_env); + gen_helper_shll_s_ph(v1_t, t0, v1_t, tcg_env); gen_store_gpr(v1_t, rt); break; default: @@ -3548,7 +3548,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *= ctx, int opc, case NM_SHLL_S_W: check_dsp(ctx); tcg_gen_movi_tl(t0, rd); - gen_helper_shll_s_w(v1_t, t0, v1_t, cpu_env); + gen_helper_shll_s_w(v1_t, t0, v1_t, tcg_env); gen_store_gpr(v1_t, rt); break; case NM_REPL_PH: @@ -4503,7 +4503,7 @@ static int decode_isa_nanomips(CPUMIPSState *env, Dis= asContext *ctx) /* make sure instructions are on a halfword boundary */ if (ctx->base.pc_next & 0x1) { TCGv tmp =3D tcg_constant_tl(ctx->base.pc_next); - tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); + tcg_gen_st_tl(tmp, tcg_env, offsetof(CPUMIPSState, CP0_BadVAddr)); generate_exception_end(ctx, EXCP_AdEL); return 2; } diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.= c.inc index c82feedaff..6f796ce511 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -106,7 +106,7 @@ static void write_MMCR0_common(DisasContext *ctx, TCGv = val) * translator_io_start() beforehand. */ translator_io_start(&ctx->base); - gen_helper_store_mmcr0(cpu_env, val); + gen_helper_store_mmcr0(tcg_env, val); =20 /* * End the translation block because MMCR0 writes can change @@ -180,7 +180,7 @@ void spr_read_PMC(DisasContext *ctx, int gprn, int sprn) TCGv_i32 t_sprn =3D tcg_constant_i32(sprn); =20 translator_io_start(&ctx->base); - gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn); + gen_helper_read_pmc(cpu_gpr[gprn], tcg_env, t_sprn); } =20 void spr_read_PMC14_ureg(DisasContext *ctx, int gprn, int sprn) @@ -213,7 +213,7 @@ void spr_write_PMC(DisasContext *ctx, int sprn, int gpr= n) TCGv_i32 t_sprn =3D tcg_constant_i32(sprn); =20 translator_io_start(&ctx->base); - gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]); + gen_helper_store_pmc(tcg_env, t_sprn, cpu_gpr[gprn]); } =20 void spr_write_PMC14_ureg(DisasContext *ctx, int sprn, int gprn) @@ -249,7 +249,7 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int g= prn) void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn) { translator_io_start(&ctx->base); - gen_helper_store_mmcr1(cpu_env, cpu_gpr[gprn]); + gen_helper_store_mmcr1(tcg_env, cpu_gpr[gprn]); } #else void spr_read_MMCR0_ureg(DisasContext *ctx, int gprn, int sprn) diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/= branch-impl.c.inc index f9931b9d73..fb0fcf30cc 100644 --- a/target/ppc/translate/branch-impl.c.inc +++ b/target/ppc/translate/branch-impl.c.inc @@ -18,7 +18,7 @@ static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) =20 translator_io_start(&ctx->base); gen_update_cfar(ctx, ctx->cia); - gen_helper_rfebb(cpu_env, cpu_gpr[arg->s]); + gen_helper_rfebb(tcg_env, cpu_gpr[arg->s]); =20 ctx->base.is_jmp =3D DISAS_CHAIN; =20 diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp= -impl.c.inc index 62911e04c7..371076582b 100644 --- a/target/ppc/translate/dfp-impl.c.inc +++ b/target/ppc/translate/dfp-impl.c.inc @@ -3,7 +3,7 @@ static inline TCGv_ptr gen_fprp_ptr(int reg) { TCGv_ptr r =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[reg].u64[0])); + tcg_gen_addi_ptr(r, tcg_env, offsetof(CPUPPCState, vsr[reg].u64[0])); return r; } =20 @@ -16,7 +16,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a= ) \ rt =3D gen_fprp_ptr(a->rt); \ ra =3D gen_fprp_ptr(a->ra); \ rb =3D gen_fprp_ptr(a->rb); \ - gen_helper_##NAME(cpu_env, rt, ra, rb); \ + gen_helper_##NAME(tcg_env, rt, ra, rb); \ if (unlikely(a->rc)) { \ gen_set_cr1_from_fpscr(ctx); \ } \ @@ -32,7 +32,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a= ) \ ra =3D gen_fprp_ptr(a->ra); \ rb =3D gen_fprp_ptr(a->rb); \ gen_helper_##NAME(cpu_crf[a->bf], \ - cpu_env, ra, rb); \ + tcg_env, ra, rb); \ return true; \ } =20 @@ -44,7 +44,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a= ) \ REQUIRE_FPU(ctx); \ rb =3D gen_fprp_ptr(a->rb); \ gen_helper_##NAME(cpu_crf[a->bf], \ - cpu_env, tcg_constant_i32(a->uim), rb);\ + tcg_env, tcg_constant_i32(a->uim), rb);\ return true; \ } =20 @@ -56,7 +56,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a= ) \ REQUIRE_FPU(ctx); \ ra =3D gen_fprp_ptr(a->fra); \ gen_helper_##NAME(cpu_crf[a->bf], \ - cpu_env, ra, tcg_constant_i32(a->dm)); \ + tcg_env, ra, tcg_constant_i32(a->dm)); \ return true; \ } =20 @@ -68,7 +68,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a= ) \ REQUIRE_FPU(ctx); \ rt =3D gen_fprp_ptr(a->frt); \ rb =3D gen_fprp_ptr(a->frb); \ - gen_helper_##NAME(cpu_env, rt, rb, \ + gen_helper_##NAME(tcg_env, rt, rb, \ tcg_constant_i32(a->U32F1), \ tcg_constant_i32(a->U32F2)); \ if (unlikely(a->rc)) { \ @@ -86,7 +86,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a= ) \ rt =3D gen_fprp_ptr(a->frt); \ ra =3D gen_fprp_ptr(a->fra); \ rb =3D gen_fprp_ptr(a->frb); \ - gen_helper_##NAME(cpu_env, rt, ra, rb, \ + gen_helper_##NAME(tcg_env, rt, ra, rb, \ tcg_constant_i32(a->I32FLD)); \ if (unlikely(a->rc)) { \ gen_set_cr1_from_fpscr(ctx); \ @@ -102,7 +102,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME = *a) \ REQUIRE_FPU(ctx); \ rt =3D gen_fprp_ptr(a->rt); \ rb =3D gen_fprp_ptr(a->rb); \ - gen_helper_##NAME(cpu_env, rt, rb); \ + gen_helper_##NAME(tcg_env, rt, rb); \ if (unlikely(a->rc)) { \ gen_set_cr1_from_fpscr(ctx); \ } \ @@ -117,7 +117,7 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME = *a) \ REQUIRE_FPU(ctx); \ rt =3D gen_fprp_ptr(a->rt); \ rx =3D gen_fprp_ptr(a->FPRFLD); \ - gen_helper_##NAME(cpu_env, rt, rx, \ + gen_helper_##NAME(tcg_env, rt, rx, \ tcg_constant_i32(a->I32FLD)); \ if (unlikely(a->rc)) { \ gen_set_cr1_from_fpscr(ctx); \ @@ -188,7 +188,7 @@ static bool trans_DCFFIXQQ(DisasContext *ctx, arg_DCFFI= XQQ *a) =20 rt =3D gen_fprp_ptr(a->frtp); rb =3D gen_avr_ptr(a->vrb); - gen_helper_DCFFIXQQ(cpu_env, rt, rb); + gen_helper_DCFFIXQQ(tcg_env, rt, rb); =20 return true; } @@ -203,7 +203,7 @@ static bool trans_DCTFIXQQ(DisasContext *ctx, arg_DCTFI= XQQ *a) =20 rt =3D gen_avr_ptr(a->vrt); rb =3D gen_fprp_ptr(a->frbp); - gen_helper_DCTFIXQQ(cpu_env, rt, rb); + gen_helper_DCTFIXQQ(tcg_env, rt, rb); =20 return true; } diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 7ff7e1ec46..51c6fa7330 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -517,7 +517,7 @@ static bool do_hash(DisasContext *ctx, arg_X *a, bool p= riv, } =20 ea =3D do_ea_calc(ctx, a->ra, tcg_constant_tl(a->rt)); - helper(cpu_env, ea, cpu_gpr[a->ra], cpu_gpr[a->rb]); + helper(tcg_env, ea, cpu_gpr[a->ra], cpu_gpr[a->rb]); return true; } =20 diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-i= mpl.c.inc index 874774eade..189cd8c979 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -6,13 +6,13 @@ =20 static inline void gen_reset_fpstatus(void) { - gen_helper_reset_fpstatus(cpu_env); + gen_helper_reset_fpstatus(tcg_env); } =20 static inline void gen_compute_fprf_float64(TCGv_i64 arg) { - gen_helper_compute_fprf_float64(cpu_env, arg); - gen_helper_float_check_status(cpu_env); + gen_helper_compute_fprf_float64(tcg_env, arg); + gen_helper_float_check_status(tcg_env); } =20 #if defined(TARGET_PPC64) @@ -49,7 +49,7 @@ static void gen_f##name(DisasContext *ctx) = \ get_fpr(t0, rA(ctx->opcode)); = \ get_fpr(t1, rC(ctx->opcode)); = \ get_fpr(t2, rB(ctx->opcode)); = \ - gen_helper_f##name(t3, cpu_env, t0, t1, t2); = \ + gen_helper_f##name(t3, tcg_env, t0, t1, t2); = \ set_fpr(rD(ctx->opcode), t3); = \ if (set_fprf) { = \ gen_compute_fprf_float64(t3); = \ @@ -79,7 +79,7 @@ static void gen_f##name(DisasContext *ctx) = \ gen_reset_fpstatus(); = \ get_fpr(t0, rA(ctx->opcode)); = \ get_fpr(t1, rB(ctx->opcode)); = \ - gen_helper_f##name(t2, cpu_env, t0, t1); = \ + gen_helper_f##name(t2, tcg_env, t0, t1); = \ set_fpr(rD(ctx->opcode), t2); = \ if (set_fprf) { = \ gen_compute_fprf_float64(t2); = \ @@ -108,7 +108,7 @@ static void gen_f##name(DisasContext *ctx) = \ gen_reset_fpstatus(); = \ get_fpr(t0, rA(ctx->opcode)); = \ get_fpr(t1, rC(ctx->opcode)); = \ - gen_helper_f##name(t2, cpu_env, t0, t1); = \ + gen_helper_f##name(t2, tcg_env, t0, t1); = \ set_fpr(rD(ctx->opcode), t2); = \ if (set_fprf) { = \ gen_compute_fprf_float64(t2); = \ @@ -134,12 +134,12 @@ static void gen_f##name(DisasContext *ctx) = \ t1 =3D tcg_temp_new_i64(); = \ gen_reset_fpstatus(); = \ get_fpr(t0, rB(ctx->opcode)); = \ - gen_helper_f##name(t1, cpu_env, t0); = \ + gen_helper_f##name(t1, tcg_env, t0); = \ set_fpr(rD(ctx->opcode), t1); = \ if (set_fprf) { = \ - gen_helper_compute_fprf_float64(cpu_env, t1); = \ + gen_helper_compute_fprf_float64(tcg_env, t1); = \ } = \ - gen_helper_float_check_status(cpu_env); = \ + gen_helper_float_check_status(tcg_env); = \ if (unlikely(Rc(ctx->opcode) !=3D 0)) { = \ gen_set_cr1_from_fpscr(ctx); = \ } = \ @@ -158,7 +158,7 @@ static void gen_f##name(DisasContext *ctx) = \ t1 =3D tcg_temp_new_i64(); = \ gen_reset_fpstatus(); = \ get_fpr(t0, rB(ctx->opcode)); = \ - gen_helper_f##name(t1, cpu_env, t0); = \ + gen_helper_f##name(t1, tcg_env, t0); = \ set_fpr(rD(ctx->opcode), t1); = \ if (set_fprf) { = \ gen_compute_fprf_float64(t1); = \ @@ -197,7 +197,7 @@ static void gen_frsqrtes(DisasContext *ctx) t1 =3D tcg_temp_new_i64(); gen_reset_fpstatus(); get_fpr(t0, rB(ctx->opcode)); - gen_helper_frsqrtes(t1, cpu_env, t0); + gen_helper_frsqrtes(t1, tcg_env, t0); set_fpr(rD(ctx->opcode), t1); gen_compute_fprf_float64(t1); if (unlikely(Rc(ctx->opcode) !=3D 0)) { @@ -245,7 +245,7 @@ static bool do_helper_fsqrt(DisasContext *ctx, arg_A_tb= *a, =20 gen_reset_fpstatus(); get_fpr(t0, a->frb); - helper(t1, cpu_env, t0); + helper(t1, tcg_env, t0); set_fpr(a->frt, t1); gen_compute_fprf_float64(t1); if (unlikely(a->rc !=3D 0)) { @@ -351,8 +351,8 @@ static void gen_fcmpo(DisasContext *ctx) crf =3D tcg_constant_i32(crfD(ctx->opcode)); get_fpr(t0, rA(ctx->opcode)); get_fpr(t1, rB(ctx->opcode)); - gen_helper_fcmpo(cpu_env, t0, t1, crf); - gen_helper_float_check_status(cpu_env); + gen_helper_fcmpo(tcg_env, t0, t1, crf); + gen_helper_float_check_status(tcg_env); } =20 /* fcmpu */ @@ -371,8 +371,8 @@ static void gen_fcmpu(DisasContext *ctx) crf =3D tcg_constant_i32(crfD(ctx->opcode)); get_fpr(t0, rA(ctx->opcode)); get_fpr(t1, rB(ctx->opcode)); - gen_helper_fcmpu(cpu_env, t0, t1, crf); - gen_helper_float_check_status(cpu_env); + gen_helper_fcmpu(tcg_env, t0, t1, crf); + gen_helper_float_check_status(tcg_env); } =20 /*** Floating-point move = ***/ @@ -542,7 +542,7 @@ static void gen_mcrfs(DisasContext *ctx) ~((0xF << shift) & FP_EX_CLEAR_BITS)); /* FEX and VX need to be updated, so don't set fpscr directly */ tmask =3D tcg_constant_i32(1 << nibble); - gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask); + gen_helper_store_fpscr(tcg_env, tnew_fpscr, tmask); } =20 static TCGv_i64 place_from_fpscr(int rt, uint64_t mask) @@ -565,7 +565,7 @@ static void store_fpscr_masked(TCGv_i64 fpscr, uint64_t= clear_mask, =20 tcg_gen_andi_i64(fpscr_masked, fpscr, ~clear_mask); tcg_gen_or_i64(fpscr_masked, fpscr_masked, set_mask); - gen_helper_store_fpscr(cpu_env, fpscr_masked, st_mask); + gen_helper_store_fpscr(tcg_env, fpscr_masked, st_mask); } =20 static bool trans_MFFS_ISA207(DisasContext *ctx, arg_X_t_rc *a) @@ -691,7 +691,7 @@ static void gen_mtfsb0(DisasContext *ctx) crb =3D 31 - crbD(ctx->opcode); gen_reset_fpstatus(); if (likely(crb !=3D FPSCR_FEX && crb !=3D FPSCR_VX)) { - gen_helper_fpscr_clrbit(cpu_env, tcg_constant_i32(crb)); + gen_helper_fpscr_clrbit(tcg_env, tcg_constant_i32(crb)); } if (unlikely(Rc(ctx->opcode) !=3D 0)) { tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); @@ -711,14 +711,14 @@ static void gen_mtfsb1(DisasContext *ctx) crb =3D 31 - crbD(ctx->opcode); /* XXX: we pretend we can only do IEEE floating-point computations */ if (likely(crb !=3D FPSCR_FEX && crb !=3D FPSCR_VX && crb !=3D FPSCR_N= I)) { - gen_helper_fpscr_setbit(cpu_env, tcg_constant_i32(crb)); + gen_helper_fpscr_setbit(tcg_env, tcg_constant_i32(crb)); } if (unlikely(Rc(ctx->opcode) !=3D 0)) { tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } /* We can raise a deferred exception */ - gen_helper_fpscr_check_status(cpu_env); + gen_helper_fpscr_check_status(tcg_env); } =20 /* mtfsf */ @@ -748,13 +748,13 @@ static void gen_mtfsf(DisasContext *ctx) } t1 =3D tcg_temp_new_i64(); get_fpr(t1, rB(ctx->opcode)); - gen_helper_store_fpscr(cpu_env, t1, t0); + gen_helper_store_fpscr(tcg_env, t1, t0); if (unlikely(Rc(ctx->opcode) !=3D 0)) { tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } /* We can raise a deferred exception */ - gen_helper_fpscr_check_status(cpu_env); + gen_helper_fpscr_check_status(tcg_env); } =20 /* mtfsfi */ @@ -777,13 +777,13 @@ static void gen_mtfsfi(DisasContext *ctx) sh =3D (8 * w) + 7 - bf; t0 =3D tcg_constant_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh)); t1 =3D tcg_constant_i32(1 << sh); - gen_helper_store_fpscr(cpu_env, t0, t1); + gen_helper_store_fpscr(tcg_env, t0, t1); if (unlikely(Rc(ctx->opcode) !=3D 0)) { tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } /* We can raise a deferred exception */ - gen_helper_fpscr_check_status(cpu_env); + gen_helper_fpscr_check_status(tcg_env); } =20 static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr) diff --git a/target/ppc/translate/processor-ctrl-impl.c.inc b/target/ppc/tr= anslate/processor-ctrl-impl.c.inc index cc7a50d579..0142801985 100644 --- a/target/ppc/translate/processor-ctrl-impl.c.inc +++ b/target/ppc/translate/processor-ctrl-impl.c.inc @@ -35,9 +35,9 @@ static bool trans_MSGCLR(DisasContext *ctx, arg_X_rb *a) =20 #if !defined(CONFIG_USER_ONLY) if (is_book3s_arch2x(ctx)) { - gen_helper_book3s_msgclr(cpu_env, cpu_gpr[a->rb]); + gen_helper_book3s_msgclr(tcg_env, cpu_gpr[a->rb]); } else { - gen_helper_msgclr(cpu_env, cpu_gpr[a->rb]); + gen_helper_msgclr(tcg_env, cpu_gpr[a->rb]); } #else qemu_build_not_reached(); @@ -75,7 +75,7 @@ static bool trans_MSGCLRP(DisasContext *ctx, arg_X_rb *a) REQUIRE_INSNS_FLAGS2(ctx, ISA207S); REQUIRE_SV(ctx); #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) - gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[a->rb]); + gen_helper_book3s_msgclrp(tcg_env, cpu_gpr[a->rb]); #else qemu_build_not_reached(); #endif @@ -88,7 +88,7 @@ static bool trans_MSGSNDP(DisasContext *ctx, arg_X_rb *a) REQUIRE_INSNS_FLAGS2(ctx, ISA207S); REQUIRE_SV(ctx); #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) - gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[a->rb]); + gen_helper_book3s_msgsndp(tcg_env, cpu_gpr[a->rb]); #else qemu_build_not_reached(); #endif diff --git a/target/ppc/translate/spe-impl.c.inc b/target/ppc/translate/spe= -impl.c.inc index f4a858487d..454dac823e 100644 --- a/target/ppc/translate/spe-impl.c.inc +++ b/target/ppc/translate/spe-impl.c.inc @@ -22,7 +22,7 @@ static inline void gen_evmra(DisasContext *ctx) cpu_gprh[rA(ctx->opcode)]); =20 /* spe_acc :=3D tmp */ - tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); + tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUPPCState, spe_acc)); =20 /* rD :=3D rA */ tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); @@ -457,7 +457,7 @@ static inline void gen_evmwumia(DisasContext *ctx) =20 /* acc :=3D rD */ gen_load_gpr64(tmp, rD(ctx->opcode)); - tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); + tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUPPCState, spe_acc)); } =20 static inline void gen_evmwumiaa(DisasContext *ctx) @@ -479,13 +479,13 @@ static inline void gen_evmwumiaa(DisasContext *ctx) gen_load_gpr64(tmp, rD(ctx->opcode)); =20 /* Load acc */ - tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); + tcg_gen_ld_i64(acc, tcg_env, offsetof(CPUPPCState, spe_acc)); =20 /* acc :=3D tmp + acc */ tcg_gen_add_i64(acc, acc, tmp); =20 /* Store acc */ - tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); + tcg_gen_st_i64(acc, tcg_env, offsetof(CPUPPCState, spe_acc)); =20 /* rD :=3D acc */ gen_store_gpr64(rD(ctx->opcode), acc); @@ -529,7 +529,7 @@ static inline void gen_evmwsmia(DisasContext *ctx) =20 /* acc :=3D rD */ gen_load_gpr64(tmp, rD(ctx->opcode)); - tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc)); + tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUPPCState, spe_acc)); } =20 static inline void gen_evmwsmiaa(DisasContext *ctx) @@ -551,13 +551,13 @@ static inline void gen_evmwsmiaa(DisasContext *ctx) gen_load_gpr64(tmp, rD(ctx->opcode)); =20 /* Load acc */ - tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); + tcg_gen_ld_i64(acc, tcg_env, offsetof(CPUPPCState, spe_acc)); =20 /* acc :=3D tmp + acc */ tcg_gen_add_i64(acc, acc, tmp); =20 /* Store acc */ - tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc)); + tcg_gen_st_i64(acc, tcg_env, offsetof(CPUPPCState, spe_acc)); =20 /* rD :=3D acc */ gen_store_gpr64(rD(ctx->opcode), acc); @@ -878,7 +878,7 @@ static inline void gen_##name(DisasContext *ctx) = \ { = \ TCGv_i32 t0 =3D tcg_temp_new_i32(); = \ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); = \ - gen_helper_##name(t0, cpu_env, t0); = \ + gen_helper_##name(t0, tcg_env, t0); = \ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); = \ } #define GEN_SPEFPUOP_CONV_32_64(name) = \ @@ -893,7 +893,7 @@ static inline void gen_##name(DisasContext *ctx) = \ t0 =3D tcg_temp_new_i64(); = \ t1 =3D tcg_temp_new_i32(); = \ gen_load_gpr64(t0, rB(ctx->opcode)); = \ - gen_helper_##name(t1, cpu_env, t0); = \ + gen_helper_##name(t1, tcg_env, t0); = \ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); = \ } #define GEN_SPEFPUOP_CONV_64_32(name) = \ @@ -908,7 +908,7 @@ static inline void gen_##name(DisasContext *ctx) = \ t0 =3D tcg_temp_new_i64(); = \ t1 =3D tcg_temp_new_i32(); = \ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); = \ - gen_helper_##name(t0, cpu_env, t1); = \ + gen_helper_##name(t0, tcg_env, t1); = \ gen_store_gpr64(rD(ctx->opcode), t0); = \ } #define GEN_SPEFPUOP_CONV_64_64(name) = \ @@ -921,7 +921,7 @@ static inline void gen_##name(DisasContext *ctx) = \ } = \ t0 =3D tcg_temp_new_i64(); = \ gen_load_gpr64(t0, rB(ctx->opcode)); = \ - gen_helper_##name(t0, cpu_env, t0); = \ + gen_helper_##name(t0, tcg_env, t0); = \ gen_store_gpr64(rD(ctx->opcode), t0); = \ } #define GEN_SPEFPUOP_ARITH2_32_32(name) = \ @@ -931,7 +931,7 @@ static inline void gen_##name(DisasContext *ctx) = \ TCGv_i32 t1 =3D tcg_temp_new_i32(); = \ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); = \ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); = \ - gen_helper_##name(t0, cpu_env, t0, t1); = \ + gen_helper_##name(t0, tcg_env, t0, t1); = \ tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); = \ } #define GEN_SPEFPUOP_ARITH2_64_64(name) = \ @@ -946,7 +946,7 @@ static inline void gen_##name(DisasContext *ctx) = \ t1 =3D tcg_temp_new_i64(); = \ gen_load_gpr64(t0, rA(ctx->opcode)); = \ gen_load_gpr64(t1, rB(ctx->opcode)); = \ - gen_helper_##name(t0, cpu_env, t0, t1); = \ + gen_helper_##name(t0, tcg_env, t0, t1); = \ gen_store_gpr64(rD(ctx->opcode), t0); = \ } #define GEN_SPEFPUOP_COMP_32(name) = \ @@ -957,7 +957,7 @@ static inline void gen_##name(DisasContext *ctx) = \ = \ tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); = \ tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); = \ - gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); = \ + gen_helper_##name(cpu_crf[crfD(ctx->opcode)], tcg_env, t0, t1); = \ } #define GEN_SPEFPUOP_COMP_64(name) = \ static inline void gen_##name(DisasContext *ctx) = \ @@ -971,7 +971,7 @@ static inline void gen_##name(DisasContext *ctx) = \ t1 =3D tcg_temp_new_i64(); = \ gen_load_gpr64(t0, rA(ctx->opcode)); = \ gen_load_gpr64(t1, rB(ctx->opcode)); = \ - gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); = \ + gen_helper_##name(cpu_crf[crfD(ctx->opcode)], tcg_env, t0, t1); = \ } =20 /* Single precision floating-point vectors operations */ diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/tran= slate/storage-ctrl-impl.c.inc index faa7b04bbc..74c23a4191 100644 --- a/target/ppc/translate/storage-ctrl-impl.c.inc +++ b/target/ppc/translate/storage-ctrl-impl.c.inc @@ -30,7 +30,7 @@ static bool trans_SLBIE(DisasContext *ctx, arg_SLBIE *a) REQUIRE_SV(ctx); =20 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) - gen_helper_SLBIE(cpu_env, cpu_gpr[a->rb]); + gen_helper_SLBIE(tcg_env, cpu_gpr[a->rb]); #else qemu_build_not_reached(); #endif @@ -44,7 +44,7 @@ static bool trans_SLBIEG(DisasContext *ctx, arg_SLBIEG *a) REQUIRE_SV(ctx); =20 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) - gen_helper_SLBIEG(cpu_env, cpu_gpr[a->rb]); + gen_helper_SLBIEG(tcg_env, cpu_gpr[a->rb]); #else qemu_build_not_reached(); #endif @@ -58,7 +58,7 @@ static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a) REQUIRE_SV(ctx); =20 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) - gen_helper_SLBIA(cpu_env, tcg_constant_i32(a->ih)); + gen_helper_SLBIA(tcg_env, tcg_constant_i32(a->ih)); #else qemu_build_not_reached(); #endif @@ -72,7 +72,7 @@ static bool trans_SLBIAG(DisasContext *ctx, arg_SLBIAG *a) REQUIRE_SV(ctx); =20 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) - gen_helper_SLBIAG(cpu_env, cpu_gpr[a->rs], tcg_constant_i32(a->l)); + gen_helper_SLBIAG(tcg_env, cpu_gpr[a->rs], tcg_constant_i32(a->l)); #else qemu_build_not_reached(); #endif @@ -86,7 +86,7 @@ static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a) REQUIRE_SV(ctx); =20 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) - gen_helper_SLBMTE(cpu_env, cpu_gpr[a->rb], cpu_gpr[a->rt]); + gen_helper_SLBMTE(tcg_env, cpu_gpr[a->rb], cpu_gpr[a->rt]); #else qemu_build_not_reached(); #endif @@ -100,7 +100,7 @@ static bool trans_SLBMFEV(DisasContext *ctx, arg_SLBMFE= V *a) REQUIRE_SV(ctx); =20 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) - gen_helper_SLBMFEV(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]); + gen_helper_SLBMFEV(cpu_gpr[a->rt], tcg_env, cpu_gpr[a->rb]); #else qemu_build_not_reached(); #endif @@ -114,7 +114,7 @@ static bool trans_SLBMFEE(DisasContext *ctx, arg_SLBMFE= E *a) REQUIRE_SV(ctx); =20 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) - gen_helper_SLBMFEE(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]); + gen_helper_SLBMFEE(cpu_gpr[a->rt], tcg_env, cpu_gpr[a->rb]); #else qemu_build_not_reached(); #endif @@ -137,7 +137,7 @@ static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE = *a) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); return true; } - gen_helper_SLBFEE(cpu_gpr[a->rt], cpu_env, + gen_helper_SLBFEE(cpu_gpr[a->rt], tcg_env, cpu_gpr[a->rb]); l1 =3D gen_new_label(); l2 =3D gen_new_label(); @@ -211,7 +211,7 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a,= bool local) if (!local && NARROW_MODE(ctx)) { TCGv t0 =3D tcg_temp_new(); tcg_gen_ext32u_tl(t0, cpu_gpr[rb]); - gen_helper_tlbie(cpu_env, t0); + gen_helper_tlbie(tcg_env, t0); =20 #if defined(TARGET_PPC64) /* @@ -219,7 +219,7 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a,= bool local) * otherwise the results are undefined. */ } else if (a->r) { - gen_helper_tlbie_isa300(cpu_env, cpu_gpr[rb], cpu_gpr[a->rs], + gen_helper_tlbie_isa300(tcg_env, cpu_gpr[rb], cpu_gpr[a->rs], tcg_constant_i32(a->ric << TLBIE_F_RIC_SHIFT | a->prs << TLBIE_F_PRS_SHIFT | a->r << TLBIE_F_R_SHIFT | @@ -228,7 +228,7 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a,= bool local) #endif =20 } else { - gen_helper_tlbie(cpu_env, cpu_gpr[rb]); + gen_helper_tlbie(tcg_env, cpu_gpr[rb]); } =20 if (local) { @@ -236,9 +236,9 @@ static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a,= bool local) } =20 t1 =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); + tcg_gen_ld_i32(t1, tcg_env, offsetof(CPUPPCState, tlb_need_flush)); tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); - tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); + tcg_gen_st_i32(t1, tcg_env, offsetof(CPUPPCState, tlb_need_flush)); =20 return true; #endif diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx= -impl.c.inc index 6d7669aabd..5fb49e84fc 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -10,7 +10,7 @@ static inline TCGv_ptr gen_avr_ptr(int reg) { TCGv_ptr r =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg)); + tcg_gen_addi_ptr(r, tcg_env, avr_full_offset(reg)); return r; } =20 @@ -96,7 +96,7 @@ static void gen_lve##name(DisasContext *ctx) = \ tcg_gen_andi_tl(EA, EA, ~(size - 1)); \ } \ rs =3D gen_avr_ptr(rS(ctx->opcode)); \ - gen_helper_lve##name(cpu_env, rs, EA); \ + gen_helper_lve##name(tcg_env, rs, EA); \ } =20 #define GEN_VR_STVE(name, opc2, opc3, size) \ @@ -115,7 +115,7 @@ static void gen_stve##name(DisasContext *ctx) = \ tcg_gen_andi_tl(EA, EA, ~(size - 1)); \ } \ rs =3D gen_avr_ptr(rS(ctx->opcode)); \ - gen_helper_stve##name(cpu_env, rs, EA); \ + gen_helper_stve##name(tcg_env, rs, EA); \ } =20 GEN_VR_LDX(lvx, 0x07, 0x03); @@ -146,7 +146,7 @@ static void gen_mfvscr(DisasContext *ctx) tcg_gen_movi_i64(avr, 0); set_avr64(rD(ctx->opcode), avr, true); t =3D tcg_temp_new_i32(); - gen_helper_mfvscr(t, cpu_env); + gen_helper_mfvscr(t, tcg_env); tcg_gen_extu_i32_i64(avr, t); set_avr64(rD(ctx->opcode), avr, false); } @@ -167,8 +167,8 @@ static void gen_mtvscr(DisasContext *ctx) bofs +=3D 3 * 4; #endif =20 - tcg_gen_ld_i32(val, cpu_env, bofs); - gen_helper_mtvscr(cpu_env, val); + tcg_gen_ld_i32(val, tcg_env, bofs); + gen_helper_mtvscr(tcg_env, val); } =20 static void gen_vx_vmul10(DisasContext *ctx, bool add_cin, bool ret_carry) @@ -287,7 +287,7 @@ static void glue(gen_, name)(DisasContext *ctx) = \ ra =3D gen_avr_ptr(rA(ctx->opcode)); \ rb =3D gen_avr_ptr(rB(ctx->opcode)); \ rd =3D gen_avr_ptr(rD(ctx->opcode)); \ - gen_helper_##name(cpu_env, rd, ra, rb); \ + gen_helper_##name(tcg_env, rd, ra, rb); \ } =20 #define GEN_VXFORM3(name, opc2, opc3) \ @@ -689,10 +689,10 @@ static void trans_vclzw(DisasContext *ctx) =20 /* Perform count for every word element using tcg_gen_clzi_i32. */ for (i =3D 0; i < 4; i++) { - tcg_gen_ld_i32(tmp, cpu_env, + tcg_gen_ld_i32(tmp, tcg_env, offsetof(CPUPPCState, vsr[32 + VB].u64[0]) + i * 4); tcg_gen_clzi_i32(tmp, tmp, 32); - tcg_gen_st_i32(tmp, cpu_env, + tcg_gen_st_i32(tmp, tcg_env, offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4); } } @@ -1174,7 +1174,7 @@ static void glue(gen_, name)(DisasContext *ctx) = \ ra =3D gen_avr_ptr(rA(ctx->opcode)); \ rb =3D gen_avr_ptr(rB(ctx->opcode)); \ rd =3D gen_avr_ptr(rD(ctx->opcode)); \ - gen_helper_##opname(cpu_env, rd, ra, rb); \ + gen_helper_##opname(tcg_env, rd, ra, rb); \ } =20 #define GEN_VXRFORM(name, opc2, opc3) \ @@ -1478,7 +1478,7 @@ static void glue(gen_, name)(DisasContext *ctx) = \ } \ rb =3D gen_avr_ptr(rB(ctx->opcode)); \ rd =3D gen_avr_ptr(rD(ctx->opcode)); \ - gen_helper_##name(cpu_env, rd, rb); \ + gen_helper_##name(tcg_env, rd, rb); \ } =20 #define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \ @@ -1625,7 +1625,7 @@ static void glue(gen_, name)(DisasContext *ctx) = \ uimm =3D tcg_constant_i32(UIMM5(ctx->opcode)); \ rb =3D gen_avr_ptr(rB(ctx->opcode)); \ rd =3D gen_avr_ptr(rD(ctx->opcode)); \ - gen_helper_##name(cpu_env, rd, rb, uimm); \ + gen_helper_##name(tcg_env, rd, rb, uimm); \ } =20 #define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \ @@ -1813,7 +1813,7 @@ static bool do_vextdx(DisasContext *ctx, arg_VA *a, i= nt size, bool right, if (right) { tcg_gen_subfi_tl(rc, 32 - size, rc); } - gen_helper(cpu_env, vrt, vra, vrb, rc); + gen_helper(tcg_env, vrt, vra, vrb, rc); return true; } =20 @@ -1841,7 +1841,7 @@ static bool do_vinsx(DisasContext *ctx, int vrt, int = size, bool right, TCGv ra, tcg_gen_subfi_tl(idx, 16 - size, idx); } =20 - gen_helper(cpu_env, t, rb, idx); + gen_helper(tcg_env, t, rb, idx); return true; } =20 @@ -2349,9 +2349,9 @@ static void glue(gen_, name0##_##name1)(DisasContext = *ctx) \ rc =3D gen_avr_ptr(rC(ctx->opcode)); \ rd =3D gen_avr_ptr(rD(ctx->opcode)); \ if (Rc(ctx->opcode)) { \ - gen_helper_##name1(cpu_env, rd, ra, rb, rc); \ + gen_helper_##name1(tcg_env, rd, ra, rb, rc); \ } else { \ - gen_helper_##name0(cpu_env, rd, ra, rb, rc); \ + gen_helper_##name0(tcg_env, rd, ra, rb, rc); \ } \ } =20 @@ -2437,7 +2437,7 @@ static bool do_va_env_helper(DisasContext *ctx, arg_V= A *a, vra =3D gen_avr_ptr(a->vra); vrb =3D gen_avr_ptr(a->vrb); vrc =3D gen_avr_ptr(a->rc); - gen_helper(cpu_env, vrt, vra, vrb, vrc); + gen_helper(tcg_env, vrt, vra, vrb, vrc); return true; } =20 diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx= -impl.c.inc index 0f5b0056f1..6db87ab336 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -2,25 +2,25 @@ =20 static inline void get_cpu_vsr(TCGv_i64 dst, int n, bool high) { - tcg_gen_ld_i64(dst, cpu_env, vsr64_offset(n, high)); + tcg_gen_ld_i64(dst, tcg_env, vsr64_offset(n, high)); } =20 static inline void set_cpu_vsr(int n, TCGv_i64 src, bool high) { - tcg_gen_st_i64(src, cpu_env, vsr64_offset(n, high)); + tcg_gen_st_i64(src, tcg_env, vsr64_offset(n, high)); } =20 static inline TCGv_ptr gen_vsr_ptr(int reg) { TCGv_ptr r =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(r, cpu_env, vsr_full_offset(reg)); + tcg_gen_addi_ptr(r, tcg_env, vsr_full_offset(reg)); return r; } =20 static inline TCGv_ptr gen_acc_ptr(int reg) { TCGv_ptr r =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(r, cpu_env, acc_full_offset(reg)); + tcg_gen_addi_ptr(r, tcg_env, acc_full_offset(reg)); return r; } =20 @@ -257,7 +257,7 @@ static void gen_##name(DisasContext *ctx) = \ xt =3D gen_vsr_ptr(xT(ctx->opcode)); \ gen_set_access_type(ctx, ACCESS_INT); \ gen_addr_register(ctx, EA); \ - gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \ + gen_helper_##name(tcg_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \ } =20 VSX_VECTOR_LOAD_STORE_LENGTH(lxvl) @@ -801,10 +801,10 @@ static void gen_##name(DisasContext *ctx) = \ xa =3D gen_vsr_ptr(xA(ctx->opcode)); = \ xb =3D gen_vsr_ptr(xB(ctx->opcode)); = \ if ((ctx->opcode >> (31 - 21)) & 1) { = \ - gen_helper_##name(cpu_crf[6], cpu_env, xt, xa, xb); = \ + gen_helper_##name(cpu_crf[6], tcg_env, xt, xa, xb); = \ } else { = \ ignored =3D tcg_temp_new_i32(); = \ - gen_helper_##name(ignored, cpu_env, xt, xa, xb); = \ + gen_helper_##name(ignored, tcg_env, xt, xa, xb); = \ } = \ } =20 @@ -829,7 +829,7 @@ static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_= rc *a) =20 xt =3D gen_avr_ptr(a->rt); xb =3D gen_avr_ptr(a->rb); - gen_helper_XSCVQPDP(cpu_env, ro, xt, xb); + gen_helper_XSCVQPDP(tcg_env, ro, xt, xb); return true; } =20 @@ -843,7 +843,7 @@ static bool do_helper_env_X_tb(DisasContext *ctx, arg_X= _tb *a, =20 xt =3D gen_avr_ptr(a->rt); xb =3D gen_avr_ptr(a->rb); - gen_helper(cpu_env, xt, xb); + gen_helper(tcg_env, xt, xb); return true; } =20 @@ -861,7 +861,7 @@ static void gen_##name(DisasContext *ctx) = \ return; = \ } = \ opc =3D tcg_constant_i32(ctx->opcode); = \ - gen_helper_##name(cpu_env, opc); = \ + gen_helper_##name(tcg_env, opc); = \ } =20 #define GEN_VSX_HELPER_X3(name, op1, op2, inval, type) = \ @@ -875,7 +875,7 @@ static void gen_##name(DisasContext *ctx) = \ xt =3D gen_vsr_ptr(xT(ctx->opcode)); = \ xa =3D gen_vsr_ptr(xA(ctx->opcode)); = \ xb =3D gen_vsr_ptr(xB(ctx->opcode)); = \ - gen_helper_##name(cpu_env, xt, xa, xb); = \ + gen_helper_##name(tcg_env, xt, xa, xb); = \ } =20 #define GEN_VSX_HELPER_X2(name, op1, op2, inval, type) = \ @@ -888,7 +888,7 @@ static void gen_##name(DisasContext *ctx) = \ } = \ xt =3D gen_vsr_ptr(xT(ctx->opcode)); = \ xb =3D gen_vsr_ptr(xB(ctx->opcode)); = \ - gen_helper_##name(cpu_env, xt, xb); = \ + gen_helper_##name(tcg_env, xt, xb); = \ } =20 #define GEN_VSX_HELPER_X2_AB(name, op1, op2, inval, type) = \ @@ -903,7 +903,7 @@ static void gen_##name(DisasContext *ctx) = \ opc =3D tcg_constant_i32(ctx->opcode); = \ xa =3D gen_vsr_ptr(xA(ctx->opcode)); = \ xb =3D gen_vsr_ptr(xB(ctx->opcode)); = \ - gen_helper_##name(cpu_env, opc, xa, xb); = \ + gen_helper_##name(tcg_env, opc, xa, xb); = \ } =20 #define GEN_VSX_HELPER_X1(name, op1, op2, inval, type) = \ @@ -917,7 +917,7 @@ static void gen_##name(DisasContext *ctx) = \ } = \ opc =3D tcg_constant_i32(ctx->opcode); = \ xb =3D gen_vsr_ptr(xB(ctx->opcode)); = \ - gen_helper_##name(cpu_env, opc, xb); = \ + gen_helper_##name(tcg_env, opc, xb); = \ } =20 #define GEN_VSX_HELPER_R3(name, op1, op2, inval, type) = \ @@ -933,7 +933,7 @@ static void gen_##name(DisasContext *ctx) = \ xt =3D gen_vsr_ptr(rD(ctx->opcode) + 32); = \ xa =3D gen_vsr_ptr(rA(ctx->opcode) + 32); = \ xb =3D gen_vsr_ptr(rB(ctx->opcode) + 32); = \ - gen_helper_##name(cpu_env, opc, xt, xa, xb); = \ + gen_helper_##name(tcg_env, opc, xt, xa, xb); = \ } =20 #define GEN_VSX_HELPER_R2(name, op1, op2, inval, type) = \ @@ -948,7 +948,7 @@ static void gen_##name(DisasContext *ctx) = \ opc =3D tcg_constant_i32(ctx->opcode); = \ xt =3D gen_vsr_ptr(rD(ctx->opcode) + 32); = \ xb =3D gen_vsr_ptr(rB(ctx->opcode) + 32); = \ - gen_helper_##name(cpu_env, opc, xt, xb); = \ + gen_helper_##name(tcg_env, opc, xt, xb); = \ } =20 #define GEN_VSX_HELPER_R2_AB(name, op1, op2, inval, type) = \ @@ -963,7 +963,7 @@ static void gen_##name(DisasContext *ctx) = \ opc =3D tcg_constant_i32(ctx->opcode); = \ xa =3D gen_vsr_ptr(rA(ctx->opcode) + 32); = \ xb =3D gen_vsr_ptr(rB(ctx->opcode) + 32); = \ - gen_helper_##name(cpu_env, opc, xa, xb); = \ + gen_helper_##name(tcg_env, opc, xa, xb); = \ } =20 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \ @@ -978,7 +978,7 @@ static void gen_##name(DisasContext *ctx) = \ t0 =3D tcg_temp_new_i64(); \ t1 =3D tcg_temp_new_i64(); \ get_cpu_vsr(t0, xB(ctx->opcode), true); \ - gen_helper_##name(t1, cpu_env, t0); \ + gen_helper_##name(t1, tcg_env, t0); \ set_cpu_vsr(xT(ctx->opcode), t1, true); \ set_cpu_vsr(xT(ctx->opcode), tcg_constant_i64(0), false); \ } @@ -1191,7 +1191,7 @@ static bool do_XX2_bf_uim(DisasContext *ctx, arg_XX2_= bf_uim *a, bool vsr, =20 REQUIRE_VSX(ctx); xb =3D vsr ? gen_vsr_ptr(a->xb) : gen_avr_ptr(a->xb); - gen_helper(cpu_env, tcg_constant_i32(a->bf), tcg_constant_i32(a->uim),= xb); + gen_helper(tcg_env, tcg_constant_i32(a->bf), tcg_constant_i32(a->uim),= xb); return true; } =20 @@ -1420,7 +1420,7 @@ static bool do_xsmadd(DisasContext *ctx, int tgt, int= src1, int src2, int src3, s2 =3D gen_vsr_ptr(src2); s3 =3D gen_vsr_ptr(src3); =20 - gen_helper(cpu_env, t, s1, s2, s3); + gen_helper(tcg_env, t, s1, s2, s3); return true; } =20 @@ -1500,7 +1500,7 @@ static void gen_##name(DisasContext *ctx) = \ s2 =3D gen_vsr_ptr(xT(ctx->opcode)); = \ s3 =3D gen_vsr_ptr(xB(ctx->opcode)); = \ } = \ - gen_helper_##name(cpu_env, xt, s1, s2, s3); = \ + gen_helper_##name(tcg_env, xt, s1, s2, s3); = \ } =20 GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX) @@ -1728,9 +1728,9 @@ static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_= 8RR_D_IX *a) =20 imm =3D tcg_constant_i32(a->si); =20 - tcg_gen_st_i32(imm, cpu_env, + tcg_gen_st_i32(imm, tcg_env, offsetof(CPUPPCState, vsr[a->xt].VsrW(0 + a->ix))); - tcg_gen_st_i32(imm, cpu_env, + tcg_gen_st_i32(imm, tcg_env, offsetof(CPUPPCState, vsr[a->xt].VsrW(2 + a->ix))); =20 return true; @@ -2720,7 +2720,7 @@ static bool do_helper_XX3(DisasContext *ctx, arg_XX3 = *a, xa =3D gen_vsr_ptr(a->xa); xb =3D gen_vsr_ptr(a->xb); =20 - helper(cpu_env, xt, xa, xb); + helper(tcg_env, xt, xa, xb); return true; } =20 @@ -2741,7 +2741,7 @@ static bool do_helper_X(arg_X *a, ra =3D gen_avr_ptr(a->ra); rb =3D gen_avr_ptr(a->rb); =20 - helper(cpu_env, rt, ra, rb); + helper(tcg_env, rt, ra, rb); return true; } =20 @@ -2770,7 +2770,7 @@ static bool trans_XVCVSPBF16(DisasContext *ctx, arg_X= X2 *a) xt =3D gen_vsr_ptr(a->xt); xb =3D gen_vsr_ptr(a->xb); =20 - gen_helper_XVCVSPBF16(cpu_env, xt, xb); + gen_helper_XVCVSPBF16(tcg_env, xt, xb); return true; } =20 @@ -2833,7 +2833,7 @@ static bool do_ger(DisasContext *ctx, arg_MMIRR_XX3 *= a, xb =3D gen_vsr_ptr(a->xb); =20 mask =3D ger_pack_masks(a->pmsk, a->ymsk, a->xmsk); - helper(cpu_env, xa, xb, xt, tcg_constant_i32(mask)); + helper(tcg_env, xa, xb, xt, tcg_constant_i32(mask)); return true; } =20 diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index dc14d7fc7a..620ab54eb0 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -78,7 +78,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) if (has_ext(ctx, RVS)) { decode_save_opc(ctx); translator_io_start(&ctx->base); - gen_helper_sret(cpu_pc, cpu_env); + gen_helper_sret(cpu_pc, tcg_env); exit_tb(ctx); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; } else { @@ -95,7 +95,7 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) #ifndef CONFIG_USER_ONLY decode_save_opc(ctx); translator_io_start(&ctx->base); - gen_helper_mret(cpu_pc, cpu_env); + gen_helper_mret(cpu_pc, tcg_env); exit_tb(ctx); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; return true; @@ -109,7 +109,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a) #ifndef CONFIG_USER_ONLY decode_save_opc(ctx); gen_update_pc(ctx, ctx->cur_insn_len); - gen_helper_wfi(cpu_env); + gen_helper_wfi(tcg_env); return true; #else return false; @@ -120,7 +120,7 @@ static bool trans_sfence_vma(DisasContext *ctx, arg_sfe= nce_vma *a) { #ifndef CONFIG_USER_ONLY decode_save_opc(ctx); - gen_helper_tlb_flush(cpu_env); + gen_helper_tlb_flush(tcg_env); return true; #endif return false; diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn= _trans/trans_rvbf16.c.inc index 911bc29908..4e39c00884 100644 --- a/target/riscv/insn_trans/trans_rvbf16.c.inc +++ b/target/riscv/insn_trans/trans_rvbf16.c.inc @@ -43,7 +43,7 @@ static bool trans_fcvt_bf16_s(DisasContext *ctx, arg_fcvt= _bf16_s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_bf16_s(dest, cpu_env, src1); + gen_helper_fcvt_bf16_s(dest, tcg_env, src1); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -58,7 +58,7 @@ static bool trans_fcvt_s_bf16(DisasContext *ctx, arg_fcvt= _s_bf16 *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_bf16(dest, cpu_env, src1); + gen_helper_fcvt_s_bf16(dest, tcg_env, src1); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -82,7 +82,7 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg= _vfncvtbf16_f_f_w *a) data =3D FIELD_DP32(data, VDATA, VTA, ctx->vta); data =3D FIELD_DP32(data, VDATA, VMA, ctx->vma); tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), - vreg_ofs(ctx, a->rs2), cpu_env, + vreg_ofs(ctx, a->rs2), tcg_env, ctx->cfg_ptr->vlen / 8, ctx->cfg_ptr->vlen / 8, data, gen_helper_vfncvtbf16_f_f_w); @@ -111,7 +111,7 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, a= rg_vfwcvtbf16_f_f_v *a) data =3D FIELD_DP32(data, VDATA, VTA, ctx->vta); data =3D FIELD_DP32(data, VDATA, VMA, ctx->vma); tcg_gen_gvec_3_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), - vreg_ofs(ctx, a->rs2), cpu_env, + vreg_ofs(ctx, a->rs2), tcg_env, ctx->cfg_ptr->vlen / 8, ctx->cfg_ptr->vlen / 8, data, gen_helper_vfwcvtbf16_f_f_v); @@ -142,7 +142,7 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg= _vfwmaccbf16_vv *a) data =3D FIELD_DP32(data, VDATA, VMA, ctx->vma); tcg_gen_gvec_4_ptr(vreg_ofs(ctx, a->rd), vreg_ofs(ctx, 0), vreg_ofs(ctx, a->rs1), - vreg_ofs(ctx, a->rs2), cpu_env, + vreg_ofs(ctx, a->rs2), tcg_env, ctx->cfg_ptr->vlen / 8, ctx->cfg_ptr->vlen / 8, data, gen_helper_vfwmaccbf16_vv); diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 6bdb55ef43..d9ce9e407f 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -91,7 +91,7 @@ static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d = *a) TCGv_i64 src3 =3D get_fpr_d(ctx, a->rs3); =20 gen_set_rm(ctx, a->rm); - gen_helper_fmadd_d(dest, cpu_env, src1, src2, src3); + gen_helper_fmadd_d(dest, tcg_env, src1, src2, src3); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -109,7 +109,7 @@ static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_= d *a) TCGv_i64 src3 =3D get_fpr_d(ctx, a->rs3); =20 gen_set_rm(ctx, a->rm); - gen_helper_fmsub_d(dest, cpu_env, src1, src2, src3); + gen_helper_fmsub_d(dest, tcg_env, src1, src2, src3); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -127,7 +127,7 @@ static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsu= b_d *a) TCGv_i64 src3 =3D get_fpr_d(ctx, a->rs3); =20 gen_set_rm(ctx, a->rm); - gen_helper_fnmsub_d(dest, cpu_env, src1, src2, src3); + gen_helper_fnmsub_d(dest, tcg_env, src1, src2, src3); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -145,7 +145,7 @@ static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmad= d_d *a) TCGv_i64 src3 =3D get_fpr_d(ctx, a->rs3); =20 gen_set_rm(ctx, a->rm); - gen_helper_fnmadd_d(dest, cpu_env, src1, src2, src3); + gen_helper_fnmadd_d(dest, tcg_env, src1, src2, src3); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -162,7 +162,7 @@ static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d = *a) TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fadd_d(dest, cpu_env, src1, src2); + gen_helper_fadd_d(dest, tcg_env, src1, src2); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -179,7 +179,7 @@ static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d = *a) TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsub_d(dest, cpu_env, src1, src2); + gen_helper_fsub_d(dest, tcg_env, src1, src2); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -196,7 +196,7 @@ static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d = *a) TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fmul_d(dest, cpu_env, src1, src2); + gen_helper_fmul_d(dest, tcg_env, src1, src2); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -213,7 +213,7 @@ static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d = *a) TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fdiv_d(dest, cpu_env, src1, src2); + gen_helper_fdiv_d(dest, tcg_env, src1, src2); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -229,7 +229,7 @@ static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_= d *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsqrt_d(dest, cpu_env, src1); + gen_helper_fsqrt_d(dest, tcg_env, src1); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -308,7 +308,7 @@ static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d = *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 - gen_helper_fmin_d(dest, cpu_env, src1, src2); + gen_helper_fmin_d(dest, tcg_env, src1, src2); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -324,7 +324,7 @@ static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d = *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 - gen_helper_fmax_d(dest, cpu_env, src1, src2); + gen_helper_fmax_d(dest, tcg_env, src1, src2); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -340,7 +340,7 @@ static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_= s_d *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_d(dest, cpu_env, src1); + gen_helper_fcvt_s_d(dest, tcg_env, src1); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -356,7 +356,7 @@ static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_= d_s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_s(dest, cpu_env, src1); + gen_helper_fcvt_d_s(dest, tcg_env, src1); gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -372,7 +372,7 @@ static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 - gen_helper_feq_d(dest, cpu_env, src1, src2); + gen_helper_feq_d(dest, tcg_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -387,7 +387,7 @@ static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 - gen_helper_flt_d(dest, cpu_env, src1, src2); + gen_helper_flt_d(dest, tcg_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -402,7 +402,7 @@ static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 - gen_helper_fle_d(dest, cpu_env, src1, src2); + gen_helper_fle_d(dest, tcg_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -431,7 +431,7 @@ static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_= w_d *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_w_d(dest, cpu_env, src1); + gen_helper_fcvt_w_d(dest, tcg_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -446,7 +446,7 @@ static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt= _wu_d *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_wu_d(dest, cpu_env, src1); + gen_helper_fcvt_wu_d(dest, tcg_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -461,7 +461,7 @@ static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_= d_w *a) TCGv src =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_w(dest, cpu_env, src); + gen_helper_fcvt_d_w(dest, tcg_env, src); gen_set_fpr_d(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -478,7 +478,7 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt= _d_wu *a) TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_wu(dest, cpu_env, src); + gen_helper_fcvt_d_wu(dest, tcg_env, src); gen_set_fpr_d(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -496,7 +496,7 @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcvt_= l_d *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_l_d(dest, cpu_env, src1); + gen_helper_fcvt_l_d(dest, tcg_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -512,7 +512,7 @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fcvt= _lu_d *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_lu_d(dest, cpu_env, src1); + gen_helper_fcvt_lu_d(dest, tcg_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -542,7 +542,7 @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcvt_= d_l *a) TCGv src =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_l(dest, cpu_env, src); + gen_helper_fcvt_d_l(dest, tcg_env, src); gen_set_fpr_d(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -560,7 +560,7 @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fcvt= _d_lu *a) TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_lu(dest, cpu_env, src); + gen_helper_fcvt_d_lu(dest, tcg_env, src); gen_set_fpr_d(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index e7ab84cd9a..97a368970b 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -93,7 +93,7 @@ static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s = *a) TCGv_i64 src3 =3D get_fpr_hs(ctx, a->rs3); =20 gen_set_rm(ctx, a->rm); - gen_helper_fmadd_s(dest, cpu_env, src1, src2, src3); + gen_helper_fmadd_s(dest, tcg_env, src1, src2, src3); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -110,7 +110,7 @@ static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_= s *a) TCGv_i64 src3 =3D get_fpr_hs(ctx, a->rs3); =20 gen_set_rm(ctx, a->rm); - gen_helper_fmsub_s(dest, cpu_env, src1, src2, src3); + gen_helper_fmsub_s(dest, tcg_env, src1, src2, src3); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -127,7 +127,7 @@ static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsu= b_s *a) TCGv_i64 src3 =3D get_fpr_hs(ctx, a->rs3); =20 gen_set_rm(ctx, a->rm); - gen_helper_fnmsub_s(dest, cpu_env, src1, src2, src3); + gen_helper_fnmsub_s(dest, tcg_env, src1, src2, src3); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -144,7 +144,7 @@ static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmad= d_s *a) TCGv_i64 src3 =3D get_fpr_hs(ctx, a->rs3); =20 gen_set_rm(ctx, a->rm); - gen_helper_fnmadd_s(dest, cpu_env, src1, src2, src3); + gen_helper_fnmadd_s(dest, tcg_env, src1, src2, src3); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -160,7 +160,7 @@ static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s = *a) TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fadd_s(dest, cpu_env, src1, src2); + gen_helper_fadd_s(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -176,7 +176,7 @@ static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s = *a) TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsub_s(dest, cpu_env, src1, src2); + gen_helper_fsub_s(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -192,7 +192,7 @@ static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s = *a) TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fmul_s(dest, cpu_env, src1, src2); + gen_helper_fmul_s(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -208,7 +208,7 @@ static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s = *a) TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fdiv_s(dest, cpu_env, src1, src2); + gen_helper_fdiv_s(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -223,7 +223,7 @@ static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_= s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsqrt_s(dest, cpu_env, src1); + gen_helper_fsqrt_s(dest, tcg_env, src1); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -363,7 +363,7 @@ static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s = *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fmin_s(dest, cpu_env, src1, src2); + gen_helper_fmin_s(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -378,7 +378,7 @@ static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s = *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fmax_s(dest, cpu_env, src1, src2); + gen_helper_fmax_s(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -393,7 +393,7 @@ static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_= w_s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_w_s(dest, cpu_env, src1); + gen_helper_fcvt_w_s(dest, tcg_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -407,7 +407,7 @@ static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt= _wu_s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_wu_s(dest, cpu_env, src1); + gen_helper_fcvt_wu_s(dest, tcg_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -439,7 +439,7 @@ static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_feq_s(dest, cpu_env, src1, src2); + gen_helper_feq_s(dest, tcg_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -453,7 +453,7 @@ static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_flt_s(dest, cpu_env, src1, src2); + gen_helper_flt_s(dest, tcg_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -467,7 +467,7 @@ static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fle_s(dest, cpu_env, src1, src2); + gen_helper_fle_s(dest, tcg_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -480,7 +480,7 @@ static bool trans_fclass_s(DisasContext *ctx, arg_fclas= s_s *a) TCGv dest =3D dest_gpr(ctx, a->rd); TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 - gen_helper_fclass_s(dest, cpu_env, src1); + gen_helper_fclass_s(dest, tcg_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -494,7 +494,7 @@ static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_= s_w *a) TCGv src =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_w(dest, cpu_env, src); + gen_helper_fcvt_s_w(dest, tcg_env, src); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -509,7 +509,7 @@ static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt= _s_wu *a) TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_wu(dest, cpu_env, src); + gen_helper_fcvt_s_wu(dest, tcg_env, src); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -541,7 +541,7 @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt_= l_s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_l_s(dest, cpu_env, src1); + gen_helper_fcvt_l_s(dest, tcg_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -556,7 +556,7 @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcvt= _lu_s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_lu_s(dest, cpu_env, src1); + gen_helper_fcvt_lu_s(dest, tcg_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -571,7 +571,7 @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcvt_= s_l *a) TCGv src =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_l(dest, cpu_env, src); + gen_helper_fcvt_s_l(dest, tcg_env, src); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -587,7 +587,7 @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcvt= _s_lu *a) TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_lu(dest, cpu_env, src); + gen_helper_fcvt_s_lu(dest, tcg_env, src); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index 3e9322130f..aa9d41c18c 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -45,7 +45,7 @@ static bool do_hlv(DisasContext *ctx, arg_r2 *a, TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); =20 decode_save_opc(ctx); - func(dest, cpu_env, addr); + func(dest, tcg_env, addr); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -57,7 +57,7 @@ static bool do_hsv(DisasContext *ctx, arg_r2_s *a, TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 decode_save_opc(ctx); - func(cpu_env, addr, data); + func(tcg_env, addr, data); return true; } #endif /* CONFIG_USER_ONLY */ @@ -148,7 +148,7 @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sf= ence_vma *a) REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY decode_save_opc(ctx); - gen_helper_hyp_gvma_tlb_flush(cpu_env); + gen_helper_hyp_gvma_tlb_flush(tcg_env); return true; #endif return false; @@ -159,7 +159,7 @@ static bool trans_hfence_vvma(DisasContext *ctx, arg_sf= ence_vma *a) REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY decode_save_opc(ctx); - gen_helper_hyp_tlb_flush(cpu_env); + gen_helper_hyp_tlb_flush(tcg_env); return true; #endif return false; diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 297142208e..25cb60558a 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -830,7 +830,7 @@ static bool do_csrr(DisasContext *ctx, int rd, int rc) TCGv_i32 csr =3D tcg_constant_i32(rc); =20 translator_io_start(&ctx->base); - gen_helper_csrr(dest, cpu_env, csr); + gen_helper_csrr(dest, tcg_env, csr); gen_set_gpr(ctx, rd, dest); return do_csr_post(ctx); } @@ -840,7 +840,7 @@ static bool do_csrw(DisasContext *ctx, int rc, TCGv src) TCGv_i32 csr =3D tcg_constant_i32(rc); =20 translator_io_start(&ctx->base); - gen_helper_csrw(cpu_env, csr, src); + gen_helper_csrw(tcg_env, csr, src); return do_csr_post(ctx); } =20 @@ -850,7 +850,7 @@ static bool do_csrrw(DisasContext *ctx, int rd, int rc,= TCGv src, TCGv mask) TCGv_i32 csr =3D tcg_constant_i32(rc); =20 translator_io_start(&ctx->base); - gen_helper_csrrw(dest, cpu_env, csr, src, mask); + gen_helper_csrrw(dest, tcg_env, csr, src, mask); gen_set_gpr(ctx, rd, dest); return do_csr_post(ctx); } @@ -862,8 +862,8 @@ static bool do_csrr_i128(DisasContext *ctx, int rd, int= rc) TCGv_i32 csr =3D tcg_constant_i32(rc); =20 translator_io_start(&ctx->base); - gen_helper_csrr_i128(destl, cpu_env, csr); - tcg_gen_ld_tl(desth, cpu_env, offsetof(CPURISCVState, retxh)); + gen_helper_csrr_i128(destl, tcg_env, csr); + tcg_gen_ld_tl(desth, tcg_env, offsetof(CPURISCVState, retxh)); gen_set_gpr128(ctx, rd, destl, desth); return do_csr_post(ctx); } @@ -873,7 +873,7 @@ static bool do_csrw_i128(DisasContext *ctx, int rc, TCG= v srcl, TCGv srch) TCGv_i32 csr =3D tcg_constant_i32(rc); =20 translator_io_start(&ctx->base); - gen_helper_csrw_i128(cpu_env, csr, srcl, srch); + gen_helper_csrw_i128(tcg_env, csr, srcl, srch); return do_csr_post(ctx); } =20 @@ -885,8 +885,8 @@ static bool do_csrrw_i128(DisasContext *ctx, int rd, in= t rc, TCGv_i32 csr =3D tcg_constant_i32(rc); =20 translator_io_start(&ctx->base); - gen_helper_csrrw_i128(destl, cpu_env, csr, srcl, srch, maskl, maskh); - tcg_gen_ld_tl(desth, cpu_env, offsetof(CPURISCVState, retxh)); + gen_helper_csrrw_i128(destl, tcg_env, csr, srcl, srch, maskl, maskh); + tcg_gen_ld_tl(desth, tcg_env, offsetof(CPURISCVState, retxh)); gen_set_gpr128(ctx, rd, destl, desth); return do_csr_post(ctx); } diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_tr= ans/trans_rvm.c.inc index 2f0fd1f700..795f0ccf14 100644 --- a/target/riscv/insn_trans/trans_rvm.c.inc +++ b/target/riscv/insn_trans/trans_rvm.c.inc @@ -169,8 +169,8 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a) static void gen_div_i128(TCGv rdl, TCGv rdh, TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) { - gen_helper_divs_i128(rdl, cpu_env, rs1l, rs1h, rs2l, rs2h); - tcg_gen_ld_tl(rdh, cpu_env, offsetof(CPURISCVState, retxh)); + gen_helper_divs_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h); + tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh)); } =20 static void gen_div(TCGv ret, TCGv source1, TCGv source2) @@ -212,8 +212,8 @@ static bool trans_div(DisasContext *ctx, arg_div *a) static void gen_divu_i128(TCGv rdl, TCGv rdh, TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) { - gen_helper_divu_i128(rdl, cpu_env, rs1l, rs1h, rs2l, rs2h); - tcg_gen_ld_tl(rdh, cpu_env, offsetof(CPURISCVState, retxh)); + gen_helper_divu_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h); + tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh)); } =20 static void gen_divu(TCGv ret, TCGv source1, TCGv source2) @@ -244,8 +244,8 @@ static bool trans_divu(DisasContext *ctx, arg_divu *a) static void gen_rem_i128(TCGv rdl, TCGv rdh, TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) { - gen_helper_rems_i128(rdl, cpu_env, rs1l, rs1h, rs2l, rs2h); - tcg_gen_ld_tl(rdh, cpu_env, offsetof(CPURISCVState, retxh)); + gen_helper_rems_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h); + tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh)); } =20 static void gen_rem(TCGv ret, TCGv source1, TCGv source2) @@ -289,8 +289,8 @@ static bool trans_rem(DisasContext *ctx, arg_rem *a) static void gen_remu_i128(TCGv rdl, TCGv rdh, TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h) { - gen_helper_remu_i128(rdl, cpu_env, rs1l, rs1h, rs2l, rs2h); - tcg_gen_ld_tl(rdh, cpu_env, offsetof(CPURISCVState, retxh)); + gen_helper_remu_i128(rdl, tcg_env, rs1l, rs1h, rs2l, rs2h); + tcg_gen_ld_tl(rdh, tcg_env, offsetof(CPURISCVState, retxh)); } =20 static void gen_remu(TCGv ret, TCGv source1, TCGv source2) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 63404f61fc..78bd363310 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -165,7 +165,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1,= TCGv s2) s1 =3D get_gpr(s, rs1, EXT_ZERO); } =20 - gen_helper_vsetvl(dst, cpu_env, s1, s2); + gen_helper_vsetvl(dst, tcg_env, s1, s2); gen_set_gpr(s, rd, dst); mark_vs_dirty(s); =20 @@ -185,7 +185,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s= 1, TCGv s2) =20 dst =3D dest_gpr(s, rd); =20 - gen_helper_vsetvl(dst, cpu_env, s1, s2); + gen_helper_vsetvl(dst, tcg_env, s1, s2); gen_set_gpr(s, rd, dst); mark_vs_dirty(s); gen_update_pc(s, s->cur_insn_len); @@ -633,10 +633,10 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, = uint32_t data, desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); =20 - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd)); + tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0)); =20 - fn(dest, mask, base, cpu_env, desc); + fn(dest, mask, base, tcg_env, desc); =20 if (!is_store) { mark_vs_dirty(s); @@ -794,10 +794,10 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t r= s1, uint32_t rs2, desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); =20 - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd)); + tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0)); =20 - fn(dest, mask, base, stride, cpu_env, desc); + fn(dest, mask, base, stride, tcg_env, desc); =20 if (!is_store) { mark_vs_dirty(s); @@ -900,11 +900,11 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs= 1, uint32_t vs2, desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); =20 - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd)); + tcg_gen_addi_ptr(index, tcg_env, vreg_ofs(s, vs2)); + tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0)); =20 - fn(dest, mask, base, index, cpu_env, desc); + fn(dest, mask, base, index, tcg_env, desc); =20 if (!is_store) { mark_vs_dirty(s); @@ -1039,10 +1039,10 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, u= int32_t data, desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); =20 - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd)); + tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0)); =20 - fn(dest, mask, base, cpu_env, desc); + fn(dest, mask, base, tcg_env, desc); =20 mark_vs_dirty(s); gen_set_label(over); @@ -1100,9 +1100,9 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs= 1, uint32_t nf, s->cfg_ptr->vlen / 8, data)); =20 base =3D get_gpr(s, rs1, EXT_NONE); - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); + tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd)); =20 - fn(dest, base, cpu_env, desc); + fn(dest, base, tcg_env, desc); =20 if (!is_store) { mark_vs_dirty(s); @@ -1199,7 +1199,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3F= n *gvec_fn, data =3D FIELD_DP32(data, VDATA, VMA, s->vma); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, s->cfg_ptr->vlen / 8, + tcg_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fn); } mark_vs_dirty(s); @@ -1251,11 +1251,11 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, = uint32_t vs2, uint32_t vm, desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); =20 - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd)); + tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2)); + tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0)); =20 - fn(dest, mask, src1, src2, cpu_env, desc); + fn(dest, mask, src1, src2, tcg_env, desc); =20 mark_vs_dirty(s); gen_set_label(over); @@ -1413,11 +1413,11 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, = uint32_t vs2, uint32_t vm, desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); =20 - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd)); + tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2)); + tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0)); =20 - fn(dest, mask, src1, src2, cpu_env, desc); + fn(dest, mask, src1, src2, tcg_env, desc); =20 mark_vs_dirty(s); gen_set_label(over); @@ -1492,7 +1492,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr = *a, tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, s->cfg_ptr->vlen / 8, + tcg_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fn); mark_vs_dirty(s); @@ -1568,7 +1568,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr = *a, tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, s->cfg_ptr->vlen / 8, + tcg_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fn); mark_vs_dirty(s); gen_set_label(over); @@ -1639,7 +1639,7 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, ui= nt32_t vs2, uint32_t vm, data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); data =3D FIELD_DP32(data, VDATA, VMA, s->vma); tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1), - vreg_ofs(s, vs2), cpu_env, s->cfg_ptr->vlen / 8, + vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fn); mark_vs_dirty(s); gen_set_label(over); @@ -1830,7 +1830,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ - vreg_ofs(s, a->rs2), cpu_env, \ + vreg_ofs(s, a->rs2), tcg_env, \ s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, data, \ fns[s->sew]); \ @@ -2036,7 +2036,7 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_= v *a) tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), - cpu_env, s->cfg_ptr->vlen / 8, + tcg_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fns[s->sew]); gen_set_label(over); @@ -2084,8 +2084,8 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) tcg_gen_ext_tl_i64(s1_i64, s1); desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); - fns[s->sew](dest, s1_i64, cpu_env, desc); + tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd)); + fns[s->sew](dest, s1_i64, tcg_env, desc); } =20 mark_vs_dirty(s); @@ -2123,8 +2123,8 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) dest =3D tcg_temp_new_ptr(); desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); - fns[s->sew](dest, s1, cpu_env, desc); + tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd)); + fns[s->sew](dest, s1, tcg_env, desc); =20 mark_vs_dirty(s); gen_set_label(over); @@ -2274,7 +2274,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ - vreg_ofs(s, a->rs2), cpu_env, \ + vreg_ofs(s, a->rs2), tcg_env, \ s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ @@ -2306,15 +2306,15 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, = uint32_t vs2, desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); =20 - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); - tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd)); + tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, vs2)); + tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0)); =20 /* NaN-box f[rs1] */ t1 =3D tcg_temp_new_i64(); do_nanbox(s, t1, cpu_fpr[rs1]); =20 - fn(dest, mask, t1, src2, cpu_env, desc); + fn(dest, mask, t1, src2, tcg_env, desc); =20 mark_vs_dirty(s); gen_set_label(over); @@ -2390,7 +2390,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ - vreg_ofs(s, a->rs2), cpu_env, \ + vreg_ofs(s, a->rs2), tcg_env, \ s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ @@ -2464,7 +2464,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ - vreg_ofs(s, a->rs2), cpu_env, \ + vreg_ofs(s, a->rs2), tcg_env, \ s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ @@ -2580,7 +2580,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, data =3D FIELD_DP32(data, VDATA, VTA, s->vta); data =3D FIELD_DP32(data, VDATA, VMA, s->vma); tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), - vreg_ofs(s, a->rs2), cpu_env, + vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fn); mark_vs_dirty(s); @@ -2693,9 +2693,9 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) dest =3D tcg_temp_new_ptr(); desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); + tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd)); =20 - fns[s->sew - 1](dest, t1, cpu_env, desc); + fns[s->sew - 1](dest, t1, tcg_env, desc); =20 mark_vs_dirty(s); gen_set_label(over); @@ -2769,7 +2769,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs2), cpu_env, \ + vreg_ofs(s, a->rs2), tcg_env, \ s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ @@ -2820,7 +2820,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs2), cpu_env, \ + vreg_ofs(s, a->rs2), tcg_env, \ s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, data, \ fns[s->sew]); \ @@ -2887,7 +2887,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs2), cpu_env, \ + vreg_ofs(s, a->rs2), tcg_env, \ s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, data, \ fns[s->sew - 1]); \ @@ -2936,7 +2936,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs2), cpu_env, \ + vreg_ofs(s, a->rs2), tcg_env, \ s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, data, \ fns[s->sew]); \ @@ -3026,7 +3026,7 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) = \ FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ - vreg_ofs(s, a->rs2), cpu_env, \ + vreg_ofs(s, a->rs2), tcg_env, \ s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, data, fn); \ mark_vs_dirty(s); \ @@ -3064,10 +3064,10 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr = *a) desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); =20 - tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2)); + tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0)); =20 - gen_helper_vcpop_m(dst, mask, src2, cpu_env, desc); + gen_helper_vcpop_m(dst, mask, src2, tcg_env, desc); gen_set_gpr(s, a->rd, dst); return true; } @@ -3093,10 +3093,10 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr= *a) desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data)); =20 - tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + tcg_gen_addi_ptr(src2, tcg_env, vreg_ofs(s, a->rs2)); + tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0)); =20 - gen_helper_vfirst_m(dst, mask, src2, cpu_env, desc); + gen_helper_vfirst_m(dst, mask, src2, tcg_env, desc); gen_set_gpr(s, a->rd, dst); return true; } @@ -3128,7 +3128,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \ vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \ - cpu_env, s->cfg_ptr->vlen / 8, \ + tcg_env, s->cfg_ptr->vlen / 8, \ s->cfg_ptr->vlen / 8, \ data, fn); \ mark_vs_dirty(s); \ @@ -3170,7 +3170,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_= m *a) gen_helper_viota_m_w, gen_helper_viota_m_d, }; tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), - vreg_ofs(s, a->rs2), cpu_env, + vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fns[s->sew]); mark_vs_dirty(s); @@ -3200,7 +3200,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) gen_helper_vid_v_w, gen_helper_vid_v_d, }; tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), - cpu_env, s->cfg_ptr->vlen / 8, + tcg_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fns[s->sew]); mark_vs_dirty(s); @@ -3288,7 +3288,7 @@ static void vec_element_loadx(DisasContext *s, TCGv_i= 64 dest, =20 /* Convert the index to a pointer. */ tcg_gen_ext_i32_ptr(base, ofs); - tcg_gen_add_ptr(base, base, cpu_env); + tcg_gen_add_ptr(base, base, tcg_env); =20 /* Perform the load. */ load_element(dest, base, @@ -3306,7 +3306,7 @@ static void vec_element_loadx(DisasContext *s, TCGv_i= 64 dest, static void vec_element_loadi(DisasContext *s, TCGv_i64 dest, int vreg, int idx, bool sign) { - load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign); + load_element(dest, tcg_env, endian_ofs(s, vreg, idx), s->sew, sign); } =20 /* Integer Scalar Move Instruction */ @@ -3340,7 +3340,7 @@ static void store_element(TCGv_i64 val, TCGv_ptr base, static void vec_element_storei(DisasContext *s, int vreg, int idx, TCGv_i64 val) { - store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew); + store_element(val, tcg_env, endian_ofs(s, vreg, idx), s->sew); } =20 /* vmv.x.s rd, vs2 # x[rd] =3D vs2[0] */ @@ -3620,7 +3620,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r= *a) data =3D FIELD_DP32(data, VDATA, VTA, s->vta); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), - cpu_env, s->cfg_ptr->vlen / 8, + tcg_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fns[s->sew]); mark_vs_dirty(s); @@ -3650,7 +3650,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME = * a) \ TCGLabel *over =3D gen_new_label(); \ tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \ tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \ - cpu_env, maxsz, maxsz, 0, gen_helper_vmvr_v= ); \ + tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v= ); \ mark_vs_dirty(s); \ gen_set_label(over); \ } \ @@ -3722,7 +3722,7 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, u= int8_t seq) data =3D FIELD_DP32(data, VDATA, VMA, s->vma); =20 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), - vreg_ofs(s, a->rs2), cpu_env, + vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, fn); =20 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index c00c70dfc6..e691519ed7 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -170,7 +170,7 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvbb_vx_che= ck) data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s= ); \ data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), = \ - vreg_ofs(s, a->rs2), cpu_env, = \ + vreg_ofs(s, a->rs2), tcg_env, = \ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,= \ data, fns[s->sew]); = \ mark_vs_dirty(s); = \ @@ -244,7 +244,7 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll= _vx_check) /* save opcode for unwinding in case we throw an exception= */ \ decode_save_opc(s); = \ egs =3D tcg_constant_i32(EGS); = \ - gen_helper_egs_check(egs, cpu_env); = \ + gen_helper_egs_check(egs, tcg_env); = \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);= \ } = \ = \ @@ -257,9 +257,9 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll= _vx_check) rs2_v =3D tcg_temp_new_ptr(); = \ desc =3D tcg_constant_i32( = \ simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data= )); \ - tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); = \ - tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); = \ - gen_helper_##NAME(rd_v, rs2_v, cpu_env, desc); = \ + tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd)); = \ + tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); = \ + gen_helper_##NAME(rd_v, rs2_v, tcg_env, desc); = \ mark_vs_dirty(s); = \ gen_set_label(over); = \ return true; = \ @@ -320,7 +320,7 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_E= GS) /* save opcode for unwinding in case we throw an exception= */ \ decode_save_opc(s); = \ egs =3D tcg_constant_i32(EGS); = \ - gen_helper_egs_check(egs, cpu_env); = \ + gen_helper_egs_check(egs, tcg_env); = \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);= \ } = \ = \ @@ -335,9 +335,9 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_E= GS) uimm_v =3D tcg_constant_i32(a->rs1); = \ desc =3D tcg_constant_i32( = \ simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data= )); \ - tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); = \ - tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); = \ - gen_helper_##NAME(rd_v, rs2_v, uimm_v, cpu_env, desc); = \ + tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd)); = \ + tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); = \ + gen_helper_##NAME(rd_v, rs2_v, uimm_v, tcg_env, desc); = \ mark_vs_dirty(s); = \ gen_set_label(over); = \ return true; = \ @@ -390,7 +390,7 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED= _EGS) /* save opcode for unwinding in case we throw an exception= */ \ decode_save_opc(s); = \ egs =3D tcg_constant_i32(EGS); = \ - gen_helper_egs_check(egs, cpu_env); = \ + gen_helper_egs_check(egs, tcg_env); = \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);= \ } = \ = \ @@ -401,7 +401,7 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED= _EGS) data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ = \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), = \ - vreg_ofs(s, a->rs2), cpu_env, = \ + vreg_ofs(s, a->rs2), tcg_env, = \ s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,= \ data, gen_helper_##NAME); = \ = \ @@ -444,7 +444,7 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr = *a) /* save opcode for unwinding in case we throw an exception */ decode_save_opc(s); egs =3D tcg_constant_i32(ZVKNH_EGS); - gen_helper_egs_check(egs, cpu_env); + gen_helper_egs_check(egs, tcg_env); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); } =20 @@ -455,7 +455,7 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr = *a) data =3D FIELD_DP32(data, VDATA, VMA, s->vma); =20 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), - vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8, + vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, s->sew =3D=3D MO_32 ? gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv); @@ -478,7 +478,7 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr = *a) /* save opcode for unwinding in case we throw an exception */ decode_save_opc(s); egs =3D tcg_constant_i32(ZVKNH_EGS); - gen_helper_egs_check(egs, cpu_env); + gen_helper_egs_check(egs, tcg_env); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); } =20 @@ -489,7 +489,7 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr = *a) data =3D FIELD_DP32(data, VDATA, VMA, s->vma); =20 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), - vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8, + vreg_ofs(s, a->rs2), tcg_env, s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data, s->sew =3D=3D MO_32 ? gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv); diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_= trans/trans_rvzce.c.inc index 8d8a64f493..2d992e14c4 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -298,7 +298,7 @@ static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jal= t *a) * that might come from cpu_ld*_code() in the helper. */ gen_update_pc(ctx, 0); - gen_helper_cm_jalt(cpu_pc, cpu_env, tcg_constant_i32(a->index)); + gen_helper_cm_jalt(cpu_pc, tcg_env, tcg_constant_i32(a->index)); =20 /* c.jt vs c.jalt depends on the index. */ if (a->index >=3D 32) { diff --git a/target/riscv/insn_trans/trans_rvzfa.c.inc b/target/riscv/insn_= trans/trans_rvzfa.c.inc index 0fdd2698f6..fd7e2daebf 100644 --- a/target/riscv/insn_trans/trans_rvzfa.c.inc +++ b/target/riscv/insn_trans/trans_rvzfa.c.inc @@ -187,7 +187,7 @@ static bool trans_fminm_s(DisasContext *ctx, arg_fminm_= s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fminm_s(dest, cpu_env, src1, src2); + gen_helper_fminm_s(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -204,7 +204,7 @@ static bool trans_fmaxm_s(DisasContext *ctx, arg_fmaxm_= s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fmaxm_s(dest, cpu_env, src1, src2); + gen_helper_fmaxm_s(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -221,7 +221,7 @@ static bool trans_fminm_d(DisasContext *ctx, arg_fminm_= d *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 - gen_helper_fminm_d(dest, cpu_env, src1, src2); + gen_helper_fminm_d(dest, tcg_env, src1, src2); gen_set_fpr_d(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -238,7 +238,7 @@ static bool trans_fmaxm_d(DisasContext *ctx, arg_fmaxm_= d *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 - gen_helper_fmaxm_d(dest, cpu_env, src1, src2); + gen_helper_fmaxm_d(dest, tcg_env, src1, src2); gen_set_fpr_d(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -255,7 +255,7 @@ static bool trans_fminm_h(DisasContext *ctx, arg_fminm_= h *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fminm_h(dest, cpu_env, src1, src2); + gen_helper_fminm_h(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -272,7 +272,7 @@ static bool trans_fmaxm_h(DisasContext *ctx, arg_fmaxm_= h *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fmaxm_h(dest, cpu_env, src1, src2); + gen_helper_fmaxm_h(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -289,7 +289,7 @@ static bool trans_fround_s(DisasContext *ctx, arg_froun= d_s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fround_s(dest, cpu_env, src1); + gen_helper_fround_s(dest, tcg_env, src1); gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -306,7 +306,7 @@ static bool trans_froundnx_s(DisasContext *ctx, arg_fro= undnx_s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_froundnx_s(dest, cpu_env, src1); + gen_helper_froundnx_s(dest, tcg_env, src1); gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -323,7 +323,7 @@ static bool trans_fround_d(DisasContext *ctx, arg_froun= d_d *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fround_d(dest, cpu_env, src1); + gen_helper_fround_d(dest, tcg_env, src1); gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -340,7 +340,7 @@ static bool trans_froundnx_d(DisasContext *ctx, arg_fro= undnx_d *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_froundnx_d(dest, cpu_env, src1); + gen_helper_froundnx_d(dest, tcg_env, src1); gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -357,7 +357,7 @@ static bool trans_fround_h(DisasContext *ctx, arg_froun= d_h *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fround_h(dest, cpu_env, src1); + gen_helper_fround_h(dest, tcg_env, src1); gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -374,7 +374,7 @@ static bool trans_froundnx_h(DisasContext *ctx, arg_fro= undnx_h *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_froundnx_h(dest, cpu_env, src1); + gen_helper_froundnx_h(dest, tcg_env, src1); gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -393,7 +393,7 @@ bool trans_fcvtmod_w_d(DisasContext *ctx, arg_fcvtmod_w= _d *a) =20 /* Rounding mode is RTZ. */ gen_set_rm(ctx, RISCV_FRM_RTZ); - gen_helper_fcvtmod_w_d(t1, cpu_env, src1); + gen_helper_fcvtmod_w_d(t1, tcg_env, src1); tcg_gen_trunc_i64_tl(dst, t1); gen_set_gpr(ctx, a->rd, dst); =20 @@ -440,7 +440,7 @@ bool trans_fleq_s(DisasContext *ctx, arg_fleq_s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fleq_s(dest, cpu_env, src1, src2); + gen_helper_fleq_s(dest, tcg_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -455,7 +455,7 @@ bool trans_fltq_s(DisasContext *ctx, arg_fltq_s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fltq_s(dest, cpu_env, src1, src2); + gen_helper_fltq_s(dest, tcg_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -470,7 +470,7 @@ bool trans_fleq_d(DisasContext *ctx, arg_fleq_d *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fleq_d(dest, cpu_env, src1, src2); + gen_helper_fleq_d(dest, tcg_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -485,7 +485,7 @@ bool trans_fltq_d(DisasContext *ctx, arg_fltq_d *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fltq_d(dest, cpu_env, src1, src2); + gen_helper_fltq_d(dest, tcg_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -500,7 +500,7 @@ bool trans_fleq_h(DisasContext *ctx, arg_fleq_h *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fleq_h(dest, cpu_env, src1, src2); + gen_helper_fleq_h(dest, tcg_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -515,7 +515,7 @@ bool trans_fltq_h(DisasContext *ctx, arg_fltq_h *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fltq_h(dest, cpu_env, src1, src2); + gen_helper_fltq_h(dest, tcg_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_= trans/trans_rvzfh.c.inc index 4b01812fd8..1eb458b491 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -95,7 +95,7 @@ static bool trans_fmadd_h(DisasContext *ctx, arg_fmadd_h = *a) TCGv_i64 src3 =3D get_fpr_hs(ctx, a->rs3); =20 gen_set_rm(ctx, a->rm); - gen_helper_fmadd_h(dest, cpu_env, src1, src2, src3); + gen_helper_fmadd_h(dest, tcg_env, src1, src2, src3); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -112,7 +112,7 @@ static bool trans_fmsub_h(DisasContext *ctx, arg_fmsub_= h *a) TCGv_i64 src3 =3D get_fpr_hs(ctx, a->rs3); =20 gen_set_rm(ctx, a->rm); - gen_helper_fmsub_h(dest, cpu_env, src1, src2, src3); + gen_helper_fmsub_h(dest, tcg_env, src1, src2, src3); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -129,7 +129,7 @@ static bool trans_fnmsub_h(DisasContext *ctx, arg_fnmsu= b_h *a) TCGv_i64 src3 =3D get_fpr_hs(ctx, a->rs3); =20 gen_set_rm(ctx, a->rm); - gen_helper_fnmsub_h(dest, cpu_env, src1, src2, src3); + gen_helper_fnmsub_h(dest, tcg_env, src1, src2, src3); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -146,7 +146,7 @@ static bool trans_fnmadd_h(DisasContext *ctx, arg_fnmad= d_h *a) TCGv_i64 src3 =3D get_fpr_hs(ctx, a->rs3); =20 gen_set_rm(ctx, a->rm); - gen_helper_fnmadd_h(dest, cpu_env, src1, src2, src3); + gen_helper_fnmadd_h(dest, tcg_env, src1, src2, src3); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -162,7 +162,7 @@ static bool trans_fadd_h(DisasContext *ctx, arg_fadd_h = *a) TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fadd_h(dest, cpu_env, src1, src2); + gen_helper_fadd_h(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -178,7 +178,7 @@ static bool trans_fsub_h(DisasContext *ctx, arg_fsub_h = *a) TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsub_h(dest, cpu_env, src1, src2); + gen_helper_fsub_h(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -194,7 +194,7 @@ static bool trans_fmul_h(DisasContext *ctx, arg_fmul_h = *a) TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fmul_h(dest, cpu_env, src1, src2); + gen_helper_fmul_h(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -210,7 +210,7 @@ static bool trans_fdiv_h(DisasContext *ctx, arg_fdiv_h = *a) TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fdiv_h(dest, cpu_env, src1, src2); + gen_helper_fdiv_h(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -225,7 +225,7 @@ static bool trans_fsqrt_h(DisasContext *ctx, arg_fsqrt_= h *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsqrt_h(dest, cpu_env, src1); + gen_helper_fsqrt_h(dest, tcg_env, src1); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -366,7 +366,7 @@ static bool trans_fmin_h(DisasContext *ctx, arg_fmin_h = *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fmin_h(dest, cpu_env, src1, src2); + gen_helper_fmin_h(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -381,7 +381,7 @@ static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h = *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fmax_h(dest, cpu_env, src1, src2); + gen_helper_fmax_h(dest, tcg_env, src1, src2); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; @@ -396,7 +396,7 @@ static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_= s_h *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_h(dest, cpu_env, src1); + gen_helper_fcvt_s_h(dest, tcg_env, src1); gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -414,7 +414,7 @@ static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_= d_h *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_h(dest, cpu_env, src1); + gen_helper_fcvt_d_h(dest, tcg_env, src1); gen_set_fpr_d(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -431,7 +431,7 @@ static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_= h_s *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_h_s(dest, cpu_env, src1); + gen_helper_fcvt_h_s(dest, tcg_env, src1); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); =20 @@ -448,7 +448,7 @@ static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_= h_d *a) TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_h_d(dest, cpu_env, src1); + gen_helper_fcvt_h_d(dest, tcg_env, src1); gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); =20 @@ -464,7 +464,7 @@ static bool trans_feq_h(DisasContext *ctx, arg_feq_h *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_feq_h(dest, cpu_env, src1, src2); + gen_helper_feq_h(dest, tcg_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -478,7 +478,7 @@ static bool trans_flt_h(DisasContext *ctx, arg_flt_h *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_flt_h(dest, cpu_env, src1, src2); + gen_helper_flt_h(dest, tcg_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); =20 return true; @@ -493,7 +493,7 @@ static bool trans_fle_h(DisasContext *ctx, arg_fle_h *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fle_h(dest, cpu_env, src1, src2); + gen_helper_fle_h(dest, tcg_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -506,7 +506,7 @@ static bool trans_fclass_h(DisasContext *ctx, arg_fclas= s_h *a) TCGv dest =3D dest_gpr(ctx, a->rd); TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 - gen_helper_fclass_h(dest, cpu_env, src1); + gen_helper_fclass_h(dest, tcg_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -520,7 +520,7 @@ static bool trans_fcvt_w_h(DisasContext *ctx, arg_fcvt_= w_h *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_w_h(dest, cpu_env, src1); + gen_helper_fcvt_w_h(dest, tcg_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -534,7 +534,7 @@ static bool trans_fcvt_wu_h(DisasContext *ctx, arg_fcvt= _wu_h *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_wu_h(dest, cpu_env, src1); + gen_helper_fcvt_wu_h(dest, tcg_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -548,7 +548,7 @@ static bool trans_fcvt_h_w(DisasContext *ctx, arg_fcvt_= h_w *a) TCGv t0 =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_h_w(dest, cpu_env, t0); + gen_helper_fcvt_h_w(dest, tcg_env, t0); gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -564,7 +564,7 @@ static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt= _h_wu *a) TCGv t0 =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_h_wu(dest, cpu_env, t0); + gen_helper_fcvt_h_wu(dest, tcg_env, t0); gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -615,7 +615,7 @@ static bool trans_fcvt_l_h(DisasContext *ctx, arg_fcvt_= l_h *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_l_h(dest, cpu_env, src1); + gen_helper_fcvt_l_h(dest, tcg_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -630,7 +630,7 @@ static bool trans_fcvt_lu_h(DisasContext *ctx, arg_fcvt= _lu_h *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_lu_h(dest, cpu_env, src1); + gen_helper_fcvt_lu_h(dest, tcg_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -645,7 +645,7 @@ static bool trans_fcvt_h_l(DisasContext *ctx, arg_fcvt_= h_l *a) TCGv t0 =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_h_l(dest, cpu_env, t0); + gen_helper_fcvt_h_l(dest, tcg_env, t0); gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); @@ -662,7 +662,7 @@ static bool trans_fcvt_h_lu(DisasContext *ctx, arg_fcvt= _h_lu *a) TCGv t0 =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_h_lu(dest, cpu_env, t0); + gen_helper_fcvt_h_lu(dest, tcg_env, t0); gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); diff --git a/target/riscv/insn_trans/trans_rvzicbo.c.inc b/target/riscv/ins= n_trans/trans_rvzicbo.c.inc index 7df9c30b58..e5a7704f54 100644 --- a/target/riscv/insn_trans/trans_rvzicbo.c.inc +++ b/target/riscv/insn_trans/trans_rvzicbo.c.inc @@ -31,27 +31,27 @@ static bool trans_cbo_clean(DisasContext *ctx, arg_cbo_clean *a) { REQUIRE_ZICBOM(ctx); - gen_helper_cbo_clean_flush(cpu_env, cpu_gpr[a->rs1]); + gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]); return true; } =20 static bool trans_cbo_flush(DisasContext *ctx, arg_cbo_flush *a) { REQUIRE_ZICBOM(ctx); - gen_helper_cbo_clean_flush(cpu_env, cpu_gpr[a->rs1]); + gen_helper_cbo_clean_flush(tcg_env, cpu_gpr[a->rs1]); return true; } =20 static bool trans_cbo_inval(DisasContext *ctx, arg_cbo_inval *a) { REQUIRE_ZICBOM(ctx); - gen_helper_cbo_inval(cpu_env, cpu_gpr[a->rs1]); + gen_helper_cbo_inval(tcg_env, cpu_gpr[a->rs1]); return true; } =20 static bool trans_cbo_zero(DisasContext *ctx, arg_cbo_zero *a) { REQUIRE_ZICBOZ(ctx); - gen_helper_cbo_zero(cpu_env, cpu_gpr[a->rs1]); + gen_helper_cbo_zero(tcg_env, cpu_gpr[a->rs1]); return true; } diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/ins= n_trans/trans_svinval.c.inc index f3cd7d5c0b..0f692a1088 100644 --- a/target/riscv/insn_trans/trans_svinval.c.inc +++ b/target/riscv/insn_trans/trans_svinval.c.inc @@ -29,7 +29,7 @@ static bool trans_sinval_vma(DisasContext *ctx, arg_sinva= l_vma *a) REQUIRE_EXT(ctx, RVS); #ifndef CONFIG_USER_ONLY decode_save_opc(ctx); - gen_helper_tlb_flush(cpu_env); + gen_helper_tlb_flush(tcg_env); return true; #endif return false; @@ -58,7 +58,7 @@ static bool trans_hinval_vvma(DisasContext *ctx, arg_hinv= al_vvma *a) REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY decode_save_opc(ctx); - gen_helper_hyp_tlb_flush(cpu_env); + gen_helper_hyp_tlb_flush(tcg_env); return true; #endif return false; @@ -71,7 +71,7 @@ static bool trans_hinval_gvma(DisasContext *ctx, arg_hinv= al_gvma *a) REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY decode_save_opc(ctx); - gen_helper_hyp_gvma_tlb_flush(cpu_env); + gen_helper_hyp_gvma_tlb_flush(tcg_env); return true; #endif return false; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn= _trans/trans_xthead.c.inc index da093a4cec..810d76665a 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -985,7 +985,7 @@ static bool trans_th_sfence_vmas(DisasContext *ctx, arg= _th_sfence_vmas *a) =20 #ifndef CONFIG_USER_ONLY REQUIRE_PRIV_MS(ctx); - gen_helper_tlb_flush_all(cpu_env); + gen_helper_tlb_flush_all(tcg_env); return true; #else return false; diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/transla= te_vx.c.inc index ec94d39df0..e073e5ad3a 100644 --- a/target/s390x/tcg/translate_vx.c.inc +++ b/target/s390x/tcg/translate_vx.c.inc @@ -36,7 +36,7 @@ * * CC handling: * As gvec ool-helpers can currently not return values (besides via - * pointers like vectors or cpu_env), whenever we have to set the CC and + * pointers like vectors or tcg_env), whenever we have to set the CC and * can't conclude the value from the result vector, we will directly * set it in "env->cc_op" and mark it as static via set_cc_static()". * Whenever this is done, the helper writes globals (cc_op). @@ -69,26 +69,26 @@ static void read_vec_element_i64(TCGv_i64 dst, uint8_t = reg, uint8_t enr, =20 switch ((unsigned)memop) { case ES_8: - tcg_gen_ld8u_i64(dst, cpu_env, offs); + tcg_gen_ld8u_i64(dst, tcg_env, offs); break; case ES_16: - tcg_gen_ld16u_i64(dst, cpu_env, offs); + tcg_gen_ld16u_i64(dst, tcg_env, offs); break; case ES_32: - tcg_gen_ld32u_i64(dst, cpu_env, offs); + tcg_gen_ld32u_i64(dst, tcg_env, offs); break; case ES_8 | MO_SIGN: - tcg_gen_ld8s_i64(dst, cpu_env, offs); + tcg_gen_ld8s_i64(dst, tcg_env, offs); break; case ES_16 | MO_SIGN: - tcg_gen_ld16s_i64(dst, cpu_env, offs); + tcg_gen_ld16s_i64(dst, tcg_env, offs); break; case ES_32 | MO_SIGN: - tcg_gen_ld32s_i64(dst, cpu_env, offs); + tcg_gen_ld32s_i64(dst, tcg_env, offs); break; case ES_64: case ES_64 | MO_SIGN: - tcg_gen_ld_i64(dst, cpu_env, offs); + tcg_gen_ld_i64(dst, tcg_env, offs); break; default: g_assert_not_reached(); @@ -102,20 +102,20 @@ static void read_vec_element_i32(TCGv_i32 dst, uint8_= t reg, uint8_t enr, =20 switch (memop) { case ES_8: - tcg_gen_ld8u_i32(dst, cpu_env, offs); + tcg_gen_ld8u_i32(dst, tcg_env, offs); break; case ES_16: - tcg_gen_ld16u_i32(dst, cpu_env, offs); + tcg_gen_ld16u_i32(dst, tcg_env, offs); break; case ES_8 | MO_SIGN: - tcg_gen_ld8s_i32(dst, cpu_env, offs); + tcg_gen_ld8s_i32(dst, tcg_env, offs); break; case ES_16 | MO_SIGN: - tcg_gen_ld16s_i32(dst, cpu_env, offs); + tcg_gen_ld16s_i32(dst, tcg_env, offs); break; case ES_32: case ES_32 | MO_SIGN: - tcg_gen_ld_i32(dst, cpu_env, offs); + tcg_gen_ld_i32(dst, tcg_env, offs); break; default: g_assert_not_reached(); @@ -129,16 +129,16 @@ static void write_vec_element_i64(TCGv_i64 src, int r= eg, uint8_t enr, =20 switch (memop) { case ES_8: - tcg_gen_st8_i64(src, cpu_env, offs); + tcg_gen_st8_i64(src, tcg_env, offs); break; case ES_16: - tcg_gen_st16_i64(src, cpu_env, offs); + tcg_gen_st16_i64(src, tcg_env, offs); break; case ES_32: - tcg_gen_st32_i64(src, cpu_env, offs); + tcg_gen_st32_i64(src, tcg_env, offs); break; case ES_64: - tcg_gen_st_i64(src, cpu_env, offs); + tcg_gen_st_i64(src, tcg_env, offs); break; default: g_assert_not_reached(); @@ -152,13 +152,13 @@ static void write_vec_element_i32(TCGv_i32 src, int r= eg, uint8_t enr, =20 switch (memop) { case ES_8: - tcg_gen_st8_i32(src, cpu_env, offs); + tcg_gen_st8_i32(src, tcg_env, offs); break; case ES_16: - tcg_gen_st16_i32(src, cpu_env, offs); + tcg_gen_st16_i32(src, tcg_env, offs); break; case ES_32: - tcg_gen_st_i32(src, cpu_env, offs); + tcg_gen_st_i32(src, tcg_env, offs); break; default: g_assert_not_reached(); @@ -173,16 +173,16 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uin= t8_t reg, TCGv_i64 enr, /* mask off invalid parts from the element nr */ tcg_gen_andi_i64(tmp, enr, NUM_VEC_ELEMENTS(es) - 1); =20 - /* convert it to an element offset relative to cpu_env (vec_reg_offset= () */ + /* convert it to an element offset relative to tcg_env (vec_reg_offset= () */ tcg_gen_shli_i64(tmp, tmp, es); #if !HOST_BIG_ENDIAN tcg_gen_xori_i64(tmp, tmp, 8 - NUM_VEC_ELEMENT_BYTES(es)); #endif tcg_gen_addi_i64(tmp, tmp, vec_full_reg_offset(reg)); =20 - /* generate the final ptr by adding cpu_env */ + /* generate the final ptr by adding tcg_env */ tcg_gen_trunc_i64_ptr(ptr, tmp); - tcg_gen_add_ptr(ptr, ptr, cpu_env); + tcg_gen_add_ptr(ptr, ptr, tcg_env); } =20 #define gen_gvec_2(v1, v2, gen) \ @@ -754,8 +754,8 @@ static DisasJumpType op_vlbb(DisasContext *s, DisasOps = *o) tcg_gen_ori_i64(bytes, o->addr1, -block_size); tcg_gen_neg_i64(bytes, bytes); =20 - tcg_gen_addi_ptr(a0, cpu_env, v1_offs); - gen_helper_vll(cpu_env, a0, o->addr1, bytes); + tcg_gen_addi_ptr(a0, tcg_env, v1_offs); + gen_helper_vll(tcg_env, a0, o->addr1, bytes); return DISAS_NEXT; } =20 @@ -812,8 +812,8 @@ static DisasJumpType op_vll(DisasContext *s, DisasOps *= o) =20 /* convert highest index into an actual length */ tcg_gen_addi_i64(o->in2, o->in2, 1); - tcg_gen_addi_ptr(a0, cpu_env, v1_offs); - gen_helper_vll(cpu_env, a0, o->addr1, o->in2); + tcg_gen_addi_ptr(a0, tcg_env, v1_offs); + gen_helper_vll(tcg_env, a0, o->addr1, o->in2); return DISAS_NEXT; } =20 @@ -898,7 +898,7 @@ static DisasJumpType op_vpk(DisasContext *s, DisasOps *= o) switch (s->fields.op2) { case 0x97: if (get_field(s, m5) & 0x1) { - gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpks_cc[es - 1]); + gen_gvec_3_ptr(v1, v2, v3, tcg_env, 0, vpks_cc[es - 1]); set_cc_static(s); } else { gen_gvec_3_ool(v1, v2, v3, 0, vpks[es - 1]); @@ -906,7 +906,7 @@ static DisasJumpType op_vpk(DisasContext *s, DisasOps *= o) break; case 0x95: if (get_field(s, m5) & 0x1) { - gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpkls_cc[es - 1]); + gen_gvec_3_ptr(v1, v2, v3, tcg_env, 0, vpkls_cc[es - 1]); set_cc_static(s); } else { gen_gvec_3_ool(v1, v2, v3, 0, vpkls[es - 1]); @@ -1058,7 +1058,7 @@ static DisasJumpType op_vst(DisasContext *s, DisasOps= *o) TCGv_i64 tmp; =20 /* Probe write access before actually modifying memory */ - gen_helper_probe_write_access(cpu_env, o->addr1, + gen_helper_probe_write_access(tcg_env, o->addr1, tcg_constant_i64(16)); =20 tmp =3D tcg_temp_new_i64(); @@ -1098,7 +1098,7 @@ static DisasJumpType op_vstbr(DisasContext *s, DisasO= ps *o) } =20 /* Probe write access before actually modifying memory */ - gen_helper_probe_write_access(cpu_env, o->addr1, tcg_constant_i64(16)); + gen_helper_probe_write_access(tcg_env, o->addr1, tcg_constant_i64(16)); =20 t0 =3D tcg_temp_new_i64(); t1 =3D tcg_temp_new_i64(); @@ -1169,7 +1169,7 @@ static DisasJumpType op_vster(DisasContext *s, DisasO= ps *o) } =20 /* Probe write access before actually modifying memory */ - gen_helper_probe_write_access(cpu_env, o->addr1, tcg_constant_i64(16)); + gen_helper_probe_write_access(tcg_env, o->addr1, tcg_constant_i64(16)); =20 /* Begin with the two doublewords swapped... */ t0 =3D tcg_temp_new_i64(); @@ -1211,7 +1211,7 @@ static DisasJumpType op_vstm(DisasContext *s, DisasOp= s *o) } =20 /* Probe write access before actually modifying memory */ - gen_helper_probe_write_access(cpu_env, o->addr1, + gen_helper_probe_write_access(tcg_env, o->addr1, tcg_constant_i64((v3 - v1 + 1) * 16)); =20 tmp =3D tcg_temp_new_i64(); @@ -1236,8 +1236,8 @@ static DisasJumpType op_vstl(DisasContext *s, DisasOp= s *o) =20 /* convert highest index into an actual length */ tcg_gen_addi_i64(o->in2, o->in2, 1); - tcg_gen_addi_ptr(a0, cpu_env, v1_offs); - gen_helper_vstl(cpu_env, a0, o->addr1, o->in2); + tcg_gen_addi_ptr(a0, tcg_env, v1_offs); + gen_helper_vstl(tcg_env, a0, o->addr1, o->in2); return DISAS_NEXT; } =20 @@ -2479,7 +2479,7 @@ static DisasJumpType op_vsum(DisasContext *s, DisasOp= s *o) static DisasJumpType op_vtm(DisasContext *s, DisasOps *o) { gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), - cpu_env, 0, gen_helper_gvec_vtm); + tcg_env, 0, gen_helper_gvec_vtm); set_cc_static(s); return DISAS_NEXT; } @@ -2505,7 +2505,7 @@ static DisasJumpType op_vfae(DisasContext *s, DisasOp= s *o) =20 if (extract32(m5, 0, 1)) { gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), - get_field(s, v3), cpu_env, m5, g_cc[es]); + get_field(s, v3), tcg_env, m5, g_cc[es]); set_cc_static(s); } else { gen_gvec_3_ool(get_field(s, v1), get_field(s, v2), @@ -2536,7 +2536,7 @@ static DisasJumpType op_vfee(DisasContext *s, DisasOp= s *o) =20 if (extract32(m5, 0, 1)) { gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), - get_field(s, v3), cpu_env, m5, g_cc[es]); + get_field(s, v3), tcg_env, m5, g_cc[es]); set_cc_static(s); } else { gen_gvec_3_ool(get_field(s, v1), get_field(s, v2), @@ -2567,7 +2567,7 @@ static DisasJumpType op_vfene(DisasContext *s, DisasO= ps *o) =20 if (extract32(m5, 0, 1)) { gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), - get_field(s, v3), cpu_env, m5, g_cc[es]); + get_field(s, v3), tcg_env, m5, g_cc[es]); set_cc_static(s); } else { gen_gvec_3_ool(get_field(s, v1), get_field(s, v2), @@ -2598,7 +2598,7 @@ static DisasJumpType op_vistr(DisasContext *s, DisasO= ps *o) =20 if (extract32(m5, 0, 1)) { gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), - cpu_env, 0, g_cc[es]); + tcg_env, 0, g_cc[es]); set_cc_static(s); } else { gen_gvec_2_ool(get_field(s, v1), get_field(s, v2), 0, @@ -2641,11 +2641,11 @@ static DisasJumpType op_vstrc(DisasContext *s, Disa= sOps *o) if (extract32(m6, 2, 1)) { gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2), get_field(s, v3), get_field(s, v4), - cpu_env, m6, g_cc_rt[es]); + tcg_env, m6, g_cc_rt[es]); } else { gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2), get_field(s, v3), get_field(s, v4), - cpu_env, m6, g_cc[es]); + tcg_env, m6, g_cc[es]); } set_cc_static(s); } else { @@ -2682,7 +2682,7 @@ static DisasJumpType op_vstrs(DisasContext *s, DisasO= ps *o) =20 gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2), get_field(s, v3), get_field(s, v4), - cpu_env, 0, fns[es][zs]); + tcg_env, 0, fns[es][zs]); set_cc_static(s); return DISAS_NEXT; } @@ -2780,7 +2780,7 @@ static DisasJumpType op_vfa(DisasContext *s, DisasOps= *o) } =20 gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), - get_field(s, v3), cpu_env, m5, fn); + get_field(s, v3), tcg_env, m5, fn); return DISAS_NEXT; } =20 @@ -2822,7 +2822,7 @@ static DisasJumpType op_wfc(DisasContext *s, DisasOps= *o) return DISAS_NORETURN; } =20 - gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, 0, fn); + gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), tcg_env, 0, fn); set_cc_static(s); return DISAS_NEXT; } @@ -2893,7 +2893,7 @@ static DisasJumpType op_vfc(DisasContext *s, DisasOps= *o) } =20 gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), get_field(s, v3), - cpu_env, m5, fn); + tcg_env, m5, fn); if (cs) { set_cc_static(s); } @@ -3007,7 +3007,7 @@ static DisasJumpType op_vcdg(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } =20 - gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, + gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), tcg_env, deposit32(m4, 4, 4, erm), fn); return DISAS_NEXT; } @@ -3036,7 +3036,7 @@ static DisasJumpType op_vfll(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } =20 - gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, m4, fn); + gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), tcg_env, m4, fn); return DISAS_NEXT; } =20 @@ -3080,7 +3080,7 @@ static DisasJumpType op_vfmax(DisasContext *s, DisasO= ps *o) } =20 gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2), get_field(s, v3), - cpu_env, deposit32(m5, 4, 4, m6), fn); + tcg_env, deposit32(m5, 4, 4, m6), fn); return DISAS_NEXT; } =20 @@ -3169,7 +3169,7 @@ static DisasJumpType op_vfma(DisasContext *s, DisasOp= s *o) } =20 gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2), - get_field(s, v3), get_field(s, v4), cpu_env, m5, fn); + get_field(s, v3), get_field(s, v4), tcg_env, m5, fn); return DISAS_NEXT; } =20 @@ -3291,7 +3291,7 @@ static DisasJumpType op_vfsq(DisasContext *s, DisasOp= s *o) return DISAS_NORETURN; } =20 - gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, m4, fn); + gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), tcg_env, m4, fn); return DISAS_NEXT; } =20 @@ -3325,7 +3325,7 @@ static DisasJumpType op_vftci(DisasContext *s, DisasO= ps *o) return DISAS_NORETURN; } =20 - gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, + gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), tcg_env, deposit32(m5, 4, 12, i3), fn); set_cc_static(s); return DISAS_NEXT; diff --git a/target/hexagon/README b/target/hexagon/README index e757bcb64a..69b2ffe9bb 100644 --- a/target/hexagon/README +++ b/target/hexagon/README @@ -86,7 +86,7 @@ tcg_funcs_generated.c.inc const int RdN =3D insn->regno[0]; TCGv RsV =3D hex_gpr[insn->regno[1]]; TCGv RtV =3D hex_gpr[insn->regno[2]]; - gen_helper_A2_add(RdV, cpu_env, RsV, RtV); + gen_helper_A2_add(RdV, tcg_env, RsV, RtV); gen_log_reg_write(ctx, RdN, RdV); } =20 @@ -143,7 +143,7 @@ istruction. const intptr_t VdV_off =3D ctx_future_vreg_off(ctx, VdN, 1, true); TCGv_ptr VdV =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(VdV, cpu_env, VdV_off); + tcg_gen_addi_ptr(VdV, tcg_env, VdV_off); const int VuN =3D insn->regno[1]; const intptr_t VuV_off =3D vreg_src_off(ctx, VuN); @@ -152,9 +152,9 @@ istruction. const intptr_t VvV_off =3D vreg_src_off(ctx, VvN); TCGv_ptr VvV =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(VuV, cpu_env, VuV_off); - tcg_gen_addi_ptr(VvV, cpu_env, VvV_off); - gen_helper_V6_vaddw(cpu_env, VdV, VuV, VvV); + tcg_gen_addi_ptr(VuV, tcg_env, VuV_off); + tcg_gen_addi_ptr(VvV, tcg_env, VvV_off); + gen_helper_V6_vaddw(tcg_env, VdV, VuV, VvV); } =20 Notice that we also generate a variable named _off for each opera= nd of diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index fe29d83d4d..f5246cee6d 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -120,7 +120,7 @@ def genptr_decl(f, tag, regtype, regid, regno): if not hex_common.skip_qemu_helper(tag): f.write(f" TCGv_ptr {regtype}{regid}V =3D " "tcg_temp_n= ew_ptr();\n") f.write( - f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, " + f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, " f"{regtype}{regid}V_off);\n" ) elif regid in {"uu", "vv", "xx"}: @@ -130,7 +130,7 @@ def genptr_decl(f, tag, regtype, regid, regno): if not hex_common.skip_qemu_helper(tag): f.write(f" TCGv_ptr {regtype}{regid}V =3D " "tcg_temp_n= ew_ptr();\n") f.write( - f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, " + f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, " f"{regtype}{regid}V_off);\n" ) elif regid in {"s", "u", "v", "w"}: @@ -155,7 +155,7 @@ def genptr_decl(f, tag, regtype, regid, regno): if not hex_common.skip_qemu_helper(tag): f.write(f" TCGv_ptr {regtype}{regid}V =3D " "tcg_temp_n= ew_ptr();\n") f.write( - f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, " + f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, " f"{regtype}{regid}V_off);\n" ) else: @@ -168,7 +168,7 @@ def genptr_decl(f, tag, regtype, regid, regno): if not hex_common.skip_qemu_helper(tag): f.write(f" TCGv_ptr {regtype}{regid}V =3D " "tcg_temp_n= ew_ptr();\n") f.write( - f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, " + f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, " f"{regtype}{regid}V_off);\n" ) elif regid in {"s", "t", "u", "v"}: @@ -303,7 +303,7 @@ def genptr_src_read(f, tag, regtype, regid): elif regid in {"s", "u", "v", "w"}: if not hex_common.skip_qemu_helper(tag): f.write( - f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, " + f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, " f"{regtype}{regid}V_off);\n" ) elif regid in {"x", "y"}: @@ -316,7 +316,7 @@ def genptr_src_read(f, tag, regtype, regid): if regid in {"s", "t", "u", "v"}: if not hex_common.skip_qemu_helper(tag): f.write( - f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, " + f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, " f"{regtype}{regid}V_off);\n" ) elif regid in {"x"}: @@ -490,7 +490,7 @@ def genptr_dst_write_opn(f, regtype, regid, tag): ## if hex_common.skip_qemu_helper(tag) is True ## is fGEN_TCG_A2_add({ RdV=3DRsV+RtV;}); ## if hex_common.skip_qemu_helper(tag) is False -## is gen_helper_A2_add(RdV, cpu_env, RsV, RtV); +## is gen_helper_A2_add(RdV, tcg_env, RsV, RtV); ## def gen_tcg_func(f, tag, regs, imms): f.write(f"static void generate_{tag}(DisasContext *ctx)\n") @@ -572,7 +572,7 @@ def gen_tcg_func(f, tag, regs, imms): i +=3D 1 if i > 0: f.write(", ") - f.write("cpu_env") + f.write("tcg_env") i =3D 1 ## For conditional instructions, we pass in the destination regist= er if "A_CONDEXEC" in hex_common.attribdict[tag]: --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900751; cv=none; d=zohomail.com; s=zohoarc; b=KCqpIWhPZ76QMNSbJR7tBeKCdraRrvbfOrdX43DLuaXQJbtwjT/bUNIuap64AN1qhHsuRvhROj8zoCpGWSYKnd9WHE2mtJ4RyDETM593hXiVb/lL7NIEuICgUv59hSU5txM1wBhIlaUifO1X5CqDlm0TEXzbqLI1fBREMT1ZXM0= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900753580100007 Content-Type: text/plain; charset="utf-8" Reviewed-by: Anton Johansson Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 1 - include/hw/core/cpu.h | 9 ++++++--- target/arm/common-semi-target.h | 2 +- accel/tcg/cpu-exec.c | 8 ++++---- accel/tcg/cputlb.c | 20 ++++++++++---------- accel/tcg/plugin-gen.c | 2 +- accel/tcg/translate-all.c | 4 ++-- bsd-user/main.c | 2 +- bsd-user/signal.c | 10 +++++----- gdbstub/gdbstub.c | 4 ++-- gdbstub/user-target.c | 2 +- hw/i386/kvm/clock.c | 2 +- hw/intc/mips_gic.c | 2 +- hw/intc/riscv_aclint.c | 12 ++++++------ hw/intc/riscv_imsic.c | 2 +- hw/ppc/e500.c | 4 ++-- hw/ppc/spapr.c | 2 +- linux-user/elfload.c | 4 ++-- linux-user/i386/cpu_loop.c | 2 +- linux-user/main.c | 4 ++-- linux-user/signal.c | 15 +++++++-------- monitor/hmp-cmds-target.c | 2 +- semihosting/arm-compat-semi.c | 6 +++--- semihosting/syscalls.c | 28 ++++++++++++++-------------- target/alpha/translate.c | 4 ++-- target/arm/cpu.c | 8 ++++---- target/arm/helper.c | 2 +- target/arm/tcg/translate-a64.c | 4 ++-- target/arm/tcg/translate.c | 6 +++--- target/avr/translate.c | 2 +- target/cris/translate.c | 4 ++-- target/hexagon/translate.c | 4 ++-- target/hppa/mem_helper.c | 2 +- target/hppa/translate.c | 4 ++-- target/i386/nvmm/nvmm-all.c | 14 +++++++------- target/i386/tcg/sysemu/excp_helper.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/i386/tcg/translate.c | 4 ++-- target/i386/whpx/whpx-all.c | 26 +++++++++++++------------- target/loongarch/translate.c | 4 ++-- target/m68k/translate.c | 4 ++-- target/microblaze/translate.c | 2 +- target/mips/tcg/sysemu/mips-semi.c | 4 ++-- target/mips/tcg/translate.c | 4 ++-- target/nios2/translate.c | 4 ++-- target/openrisc/translate.c | 2 +- target/ppc/excp_helper.c | 10 +++++----- target/ppc/translate.c | 4 ++-- target/riscv/translate.c | 6 +++--- target/rx/cpu.c | 3 --- target/rx/translate.c | 2 +- target/s390x/tcg/translate.c | 2 +- target/sh4/op_helper.c | 2 +- target/sh4/translate.c | 4 ++-- target/sparc/translate.c | 4 ++-- target/tricore/translate.c | 4 ++-- target/xtensa/translate.c | 4 ++-- target/i386/tcg/decode-new.c.inc | 2 +- 58 files changed, 153 insertions(+), 155 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index fcd6ddac6a..bff3867c1e 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -433,7 +433,6 @@ void tcg_exec_unrealizefn(CPUState *cpu); */ static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) { - cpu->parent_obj.env_ptr =3D &cpu->env; } =20 /* Validate correct placement of CPUArchState. */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 819ff1ef2e..f25d53ee90 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -429,7 +429,6 @@ struct qemu_work_item; * @num_ases: number of CPUAddressSpaces in @cpu_ases * @as: Pointer to the first AddressSpace, for the convenience of targets = which * only have a single AddressSpace - * @env_ptr: Pointer to subclass-specific CPUArchState field. * @gdb_regs: Additional GDB registers. * @gdb_num_regs: Number of total registers accessible to GDB. * @gdb_num_g_regs: Number of registers in GDB 'g' packets. @@ -503,8 +502,6 @@ struct CPUState { AddressSpace *as; MemoryRegion *memory; =20 - CPUArchState *env_ptr; - CPUJumpCache *tb_jmp_cache; =20 struct GDBRegisterState *gdb_regs; @@ -584,6 +581,12 @@ struct CPUState { QEMU_BUILD_BUG_ON(sizeof(CPUState) !=3D=20 offsetof(CPUState, neg) + sizeof(CPUNegativeOffsetState)= ); =20 +static inline CPUArchState *cpu_env(CPUState *cpu) +{ + /* We validate that CPUArchState follows CPUState in cpu-all.h. */ + return (CPUArchState *)(cpu + 1); +} + typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; extern CPUTailQ cpus; =20 diff --git a/target/arm/common-semi-target.h b/target/arm/common-semi-targe= t.h index 629d75ca5a..19438ed8cd 100644 --- a/target/arm/common-semi-target.h +++ b/target/arm/common-semi-target.h @@ -38,7 +38,7 @@ static inline void common_semi_set_ret(CPUState *cs, targ= et_ulong ret) =20 static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr) { - return (nr =3D=3D TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr)); + return nr =3D=3D TARGET_SYS_EXIT_EXTENDED || is_a64(cpu_env(cs)); } =20 static inline bool is_64bit_semihosting(CPUArchState *env) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 4abbd037f3..0e7eeef001 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -222,7 +222,7 @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu= , vaddr pc, struct tb_desc desc; uint32_t h; =20 - desc.env =3D cpu->env_ptr; + desc.env =3D cpu_env(cpu); desc.cs_base =3D cs_base; desc.flags =3D flags; desc.cflags =3D cflags; @@ -444,7 +444,7 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) static inline TranslationBlock * QEMU_DISABLE_CFI cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) { - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); uintptr_t ret; TranslationBlock *last_tb; const void *tb_ptr =3D itb->tc.ptr; @@ -565,7 +565,7 @@ static void cpu_exec_longjmp_cleanup(CPUState *cpu) =20 void cpu_exec_step_atomic(CPUState *cpu) { - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); TranslationBlock *tb; vaddr pc; uint64_t cs_base; @@ -976,7 +976,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) uint64_t cs_base; uint32_t flags, cflags; =20 - cpu_get_tb_cpu_state(cpu->env_ptr, &pc, &cs_base, &flags); + cpu_get_tb_cpu_state(cpu_env(cpu), &pc, &cs_base, &flags); =20 /* * When requested, use an exact setting for cflags for the next diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d69e046b80..f790be5b6e 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -274,7 +274,7 @@ static inline void tlb_n_used_entries_dec(CPUArchState = *env, uintptr_t mmu_idx) =20 void tlb_init(CPUState *cpu) { - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); int64_t now =3D get_clock_realtime(); int i; =20 @@ -290,7 +290,7 @@ void tlb_init(CPUState *cpu) =20 void tlb_destroy(CPUState *cpu) { - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); int i; =20 qemu_spin_destroy(&env_tlb(env)->c.lock); @@ -328,7 +328,7 @@ void tlb_flush_counts(size_t *pfull, size_t *ppart, siz= e_t *pelide) size_t full =3D 0, part =3D 0, elide =3D 0; =20 CPU_FOREACH(cpu) { - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); =20 full +=3D qatomic_read(&env_tlb(env)->c.full_flush_count); part +=3D qatomic_read(&env_tlb(env)->c.part_flush_count); @@ -341,7 +341,7 @@ void tlb_flush_counts(size_t *pfull, size_t *ppart, siz= e_t *pelide) =20 static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data = data) { - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); uint16_t asked =3D data.host_int; uint16_t all_dirty, work, to_clean; int64_t now =3D get_clock_realtime(); @@ -523,7 +523,7 @@ static void tlb_flush_page_by_mmuidx_async_0(CPUState *= cpu, vaddr addr, uint16_t idxmap) { - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); int mmu_idx; =20 assert_cpu_is_self(cpu); @@ -769,7 +769,7 @@ typedef struct { static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu, TLBFlushRangeData d) { - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); int mmu_idx; =20 assert_cpu_is_self(cpu); @@ -1032,7 +1032,7 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1= , ram_addr_t length) =20 int mmu_idx; =20 - env =3D cpu->env_ptr; + env =3D cpu_env(cpu); qemu_spin_lock(&env_tlb(env)->c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; @@ -1064,7 +1064,7 @@ static inline void tlb_set_dirty1_locked(CPUTLBEntry = *tlb_entry, so that it is no longer dirty */ void tlb_set_dirty(CPUState *cpu, vaddr addr) { - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); int mmu_idx; =20 assert_cpu_is_self(cpu); @@ -1137,7 +1137,7 @@ static inline void tlb_set_compare(CPUTLBEntryFull *f= ull, CPUTLBEntry *ent, void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, CPUTLBEntryFull *full) { - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); CPUTLB *tlb =3D env_tlb(env); CPUTLBDesc *desc =3D &tlb->d[mmu_idx]; MemoryRegionSection *section; @@ -1662,7 +1662,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState = *env, vaddr addr, bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, int mmu_idx, bool is_store, struct qemu_plugin_hwaddr *data) { - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); CPUTLBEntry *tlbe =3D tlb_entry(env, mmu_idx, addr); uintptr_t index =3D tlb_index(env, mmu_idx, addr); MMUAccessType access_type =3D is_store ? MMU_DATA_STORE : MMU_DATA_LOA= D; diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 985c980c92..d31c9993ea 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -849,7 +849,7 @@ void plugin_gen_insn_start(CPUState *cpu, const DisasCo= ntextBase *db) } else { if (ptb->vaddr2 =3D=3D -1) { ptb->vaddr2 =3D TARGET_PAGE_ALIGN(db->pc_first); - get_page_addr_code_hostp(cpu->env_ptr, ptb->vaddr2, &ptb->hadd= r2); + get_page_addr_code_hostp(cpu_env(cpu), ptb->vaddr2, &ptb->hadd= r2); } pinsn->haddr =3D ptb->haddr2 + pinsn->vaddr - ptb->vaddr2; } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index ed0c7ef7ce..6fac5b7e29 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -288,7 +288,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, vaddr pc, uint64_t cs_base, uint32_t flags, int cflags) { - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); TranslationBlock *tb, *existing_tb; tb_page_addr_t phys_pc, phys_p2; tcg_insn_unit *gen_code_buf; @@ -580,7 +580,7 @@ void tb_check_watchpoint(CPUState *cpu, uintptr_t retad= dr) } else { /* The exception probably happened in a helper. The CPU state sho= uld have been saved before calling it. Fetch the PC from there. */ - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); vaddr pc; uint64_t cs_base; tb_page_addr_t addr; diff --git a/bsd-user/main.c b/bsd-user/main.c index f913cb55a7..6c9addb75a 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -462,7 +462,7 @@ int main(int argc, char **argv) ac->init_machine(NULL); } cpu =3D cpu_create(cpu_type); - env =3D cpu->env_ptr; + env =3D cpu_env(cpu); cpu_reset(cpu); thread_cpu =3D cpu; =20 diff --git a/bsd-user/signal.c b/bsd-user/signal.c index 4db85a3485..b86eeec795 100644 --- a/bsd-user/signal.c +++ b/bsd-user/signal.c @@ -351,8 +351,8 @@ static int core_dump_signal(int sig) static G_NORETURN void dump_core_and_abort(int target_sig) { - CPUArchState *env =3D thread_cpu->env_ptr; - CPUState *cpu =3D env_cpu(env); + CPUState *cpu =3D thread_cpu; + CPUArchState *env =3D cpu_env(cpu); TaskState *ts =3D cpu->opaque; int core_dumped =3D 0; int host_sig; @@ -457,7 +457,7 @@ static int fatal_signal(int sig) void force_sig_fault(int sig, int code, abi_ulong addr) { CPUState *cpu =3D thread_cpu; - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); target_siginfo_t info =3D {}; =20 info.si_signo =3D sig; @@ -469,8 +469,8 @@ void force_sig_fault(int sig, int code, abi_ulong addr) =20 static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) { - CPUArchState *env =3D thread_cpu->env_ptr; - CPUState *cpu =3D env_cpu(env); + CPUState *cpu =3D thread_cpu; + CPUArchState *env =3D cpu_env(cpu); TaskState *ts =3D cpu->opaque; target_siginfo_t tinfo; ucontext_t *uc =3D puc; diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 349d348c7b..8eea21450c 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -423,7 +423,7 @@ static const char *get_feature_xml(const char *p, const= char **newp, static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) { CPUClass *cc =3D CPU_GET_CLASS(cpu); - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); GDBRegisterState *r; =20 if (reg < cc->gdb_num_core_regs) { @@ -441,7 +441,7 @@ static int gdb_read_register(CPUState *cpu, GByteArray = *buf, int reg) static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg) { CPUClass *cc =3D CPU_GET_CLASS(cpu); - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); GDBRegisterState *r; =20 if (reg < cc->gdb_num_core_regs) { diff --git a/gdbstub/user-target.c b/gdbstub/user-target.c index 6e21c3161c..c4bba4c72c 100644 --- a/gdbstub/user-target.c +++ b/gdbstub/user-target.c @@ -310,7 +310,7 @@ void gdb_handle_v_file_open(GArray *params, void *user_= ctx) uint64_t mode =3D get_param(params, 2)->val_ull; =20 #ifdef CONFIG_LINUX - int fd =3D do_guest_openat(gdbserver_state.g_cpu->env_ptr, 0, filename, + int fd =3D do_guest_openat(cpu_env(gdbserver_state.g_cpu), 0, filename, flags, mode, false); #else int fd =3D open(filename, flags, mode); diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c index 34348a3324..f25977d3f6 100644 --- a/hw/i386/kvm/clock.c +++ b/hw/i386/kvm/clock.c @@ -66,7 +66,7 @@ struct pvclock_vcpu_time_info { static uint64_t kvmclock_current_nsec(KVMClockState *s) { CPUState *cpu =3D first_cpu; - CPUX86State *env =3D cpu->env_ptr; + CPUX86State *env =3D cpu_env(cpu); hwaddr kvmclock_struct_pa; uint64_t migration_tsc =3D env->tsc; struct pvclock_vcpu_time_info time; diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c index 4bdc3b1bd1..77ba7348a3 100644 --- a/hw/intc/mips_gic.c +++ b/hw/intc/mips_gic.c @@ -423,7 +423,7 @@ static void mips_gic_realize(DeviceState *dev, Error **= errp) /* Register the env for all VPs with the GIC */ for (i =3D 0; i < s->num_vps; i++) { if (cs !=3D NULL) { - s->vps[i].env =3D cs->env_ptr; + s->vps[i].env =3D cpu_env(cs); cs =3D CPU_NEXT(cs); } else { error_setg(errp, diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 25cf7a5d9d..ab1a0b4b3a 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -131,7 +131,7 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, = hwaddr addr, size_t hartid =3D mtimer->hartid_base + ((addr - mtimer->timecmp_base) >> 3); CPUState *cpu =3D cpu_by_arch_id(hartid); - CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; + CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, "aclint-mtimer: invalid hartid: %zu", hartid); @@ -174,7 +174,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwa= ddr addr, size_t hartid =3D mtimer->hartid_base + ((addr - mtimer->timecmp_base) >> 3); CPUState *cpu =3D cpu_by_arch_id(hartid); - CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; + CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, "aclint-mtimer: invalid hartid: %zu", hartid); @@ -233,7 +233,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwa= ddr addr, /* Check if timer interrupt is triggered for each hart. */ for (i =3D 0; i < mtimer->num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(mtimer->hartid_base + i); - CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; + CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; if (!env) { continue; } @@ -375,7 +375,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hw= addr size, for (i =3D 0; i < num_harts; i++) { CPUState *cpu =3D cpu_by_arch_id(hartid_base + i); RISCVCPU *rvcpu =3D RISCV_CPU(cpu); - CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; + CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; riscv_aclint_mtimer_callback *cb =3D g_new0(riscv_aclint_mtimer_callback, 1); =20 @@ -409,7 +409,7 @@ static uint64_t riscv_aclint_swi_read(void *opaque, hwa= ddr addr, if (addr < (swi->num_harts << 2)) { size_t hartid =3D swi->hartid_base + (addr >> 2); CPUState *cpu =3D cpu_by_arch_id(hartid); - CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; + CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, "aclint-swi: invalid hartid: %zu", hartid); @@ -432,7 +432,7 @@ static void riscv_aclint_swi_write(void *opaque, hwaddr= addr, uint64_t value, if (addr < (swi->num_harts << 2)) { size_t hartid =3D swi->hartid_base + (addr >> 2); CPUState *cpu =3D cpu_by_arch_id(hartid); - CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; + CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; if (!env) { qemu_log_mask(LOG_GUEST_ERROR, "aclint-swi: invalid hartid: %zu", hartid); diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index 760dbddcf7..b31d07980c 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -333,7 +333,7 @@ static void riscv_imsic_realize(DeviceState *dev, Error= **errp) RISCVIMSICState *imsic =3D RISCV_IMSIC(dev); RISCVCPU *rcpu =3D RISCV_CPU(cpu_by_arch_id(imsic->hartid)); CPUState *cpu =3D cpu_by_arch_id(imsic->hartid); - CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; + CPURISCVState *env =3D cpu ? cpu_env(cpu) : NULL; =20 if (!kvm_irqchip_in_kernel()) { imsic->num_eistate =3D imsic->num_pages * imsic->num_irqs; diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index d5b6820d1d..e04114fb3c 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -373,7 +373,7 @@ static int ppce500_load_device_tree(PPCE500MachineState= *pms, MachineState *machine =3D MACHINE(pms); unsigned int smp_cpus =3D machine->smp.cpus; const PPCE500MachineClass *pmc =3D PPCE500_MACHINE_GET_CLASS(pms); - CPUPPCState *env =3D first_cpu->env_ptr; + CPUPPCState *env =3D cpu_env(first_cpu); int ret =3D -1; uint64_t mem_reg_property[] =3D { 0, cpu_to_be64(machine->ram_size) }; int fdt_size; @@ -499,7 +499,7 @@ static int ppce500_load_device_tree(PPCE500MachineState= *pms, if (cpu =3D=3D NULL) { continue; } - env =3D cpu->env_ptr; + env =3D cpu_env(cpu); =20 cpu_name =3D g_strdup_printf("/cpus/PowerPC,8544@%x", i); qemu_fdt_add_subnode(fdt, cpu_name); diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index f7cc6a890f..f919ecd8a3 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1119,7 +1119,7 @@ static void spapr_dt_hypervisor(SpaprMachineState *sp= apr, void *fdt) * Older KVM versions with older guest kernels were broken * with the magic page, don't allow the guest to map it. */ - if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, + if (!kvmppc_get_hypercall(cpu_env(first_cpu), hypercall, sizeof(hypercall))) { _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", hypercall, sizeof(hypercall))); diff --git a/linux-user/elfload.c b/linux-user/elfload.c index a5b28fa3e7..85cff102d1 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -565,7 +565,7 @@ const char *elf_hwcap2_str(uint32_t bit) =20 static const char *get_elf_platform(void) { - CPUARMState *env =3D thread_cpu->env_ptr; + CPUARMState *env =3D cpu_env(thread_cpu); =20 #if TARGET_BIG_ENDIAN # define END "b" @@ -4372,7 +4372,7 @@ static int fill_note_info(struct elf_note_info *info, if (cpu =3D=3D thread_cpu) { continue; } - fill_thread_info(info, cpu->env_ptr); + fill_thread_info(info, cpu_env(cpu)); } } =20 diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c index ef2dcb3d76..42ecb4bf0a 100644 --- a/linux-user/i386/cpu_loop.c +++ b/linux-user/i386/cpu_loop.c @@ -323,7 +323,7 @@ void cpu_loop(CPUX86State *env) =20 static void target_cpu_free(void *obj) { - CPUArchState *env =3D ((CPUState *)obj)->env_ptr; + CPUArchState *env =3D cpu_env(obj); target_munmap(env->gdt.base, sizeof(uint64_t) * TARGET_GDT_ENTRIES); g_free(obj); } diff --git a/linux-user/main.c b/linux-user/main.c index 96be354897..0a62e2be47 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -229,7 +229,7 @@ CPUArchState *cpu_copy(CPUArchState *env) { CPUState *cpu =3D env_cpu(env); CPUState *new_cpu =3D cpu_create(cpu_type); - CPUArchState *new_env =3D new_cpu->env_ptr; + CPUArchState *new_env =3D cpu_env(new_cpu); CPUBreakpoint *bp; =20 /* Reset non arch specific state */ @@ -794,7 +794,7 @@ int main(int argc, char **argv, char **envp) ac->init_machine(NULL); } cpu =3D cpu_create(cpu_type); - env =3D cpu->env_ptr; + env =3D cpu_env(cpu); cpu_reset(cpu); thread_cpu =3D cpu; =20 diff --git a/linux-user/signal.c b/linux-user/signal.c index 748a98f3e5..a7ba2ccaf4 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -618,7 +618,7 @@ void signal_init(void) void force_sig(int sig) { CPUState *cpu =3D thread_cpu; - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); target_siginfo_t info =3D {}; =20 info.si_signo =3D sig; @@ -636,7 +636,7 @@ void force_sig(int sig) void force_sig_fault(int sig, int code, abi_ulong addr) { CPUState *cpu =3D thread_cpu; - CPUArchState *env =3D cpu->env_ptr; + CPUArchState *env =3D cpu_env(cpu); target_siginfo_t info =3D {}; =20 info.si_signo =3D sig; @@ -695,10 +695,9 @@ void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong = addr, =20 /* abort execution with signal */ static G_NORETURN -void dump_core_and_abort(CPUArchState *cpu_env, int target_sig) +void dump_core_and_abort(CPUArchState *env, int target_sig) { - CPUState *cpu =3D thread_cpu; - CPUArchState *env =3D cpu->env_ptr; + CPUState *cpu =3D env_cpu(env); TaskState *ts =3D (TaskState *)cpu->opaque; int host_sig, core_dumped =3D 0; struct sigaction act; @@ -724,7 +723,7 @@ void dump_core_and_abort(CPUArchState *cpu_env, int tar= get_sig) target_sig, strsignal(host_sig), "core dumped" ); } =20 - preexit_cleanup(cpu_env, 128 + target_sig); + preexit_cleanup(env, 128 + target_sig); =20 /* The proper exit code for dying from an uncaught signal is * -. The kernel doesn't allow exit() or _exit() to pass @@ -783,8 +782,8 @@ static inline void rewind_if_in_safe_syscall(void *puc) =20 static void host_signal_handler(int host_sig, siginfo_t *info, void *puc) { - CPUArchState *env =3D thread_cpu->env_ptr; - CPUState *cpu =3D env_cpu(env); + CPUState *cpu =3D thread_cpu; + CPUArchState *env =3D cpu_env(cpu); TaskState *ts =3D cpu->opaque; target_siginfo_t tinfo; host_sigcontext *uc =3D puc; diff --git a/monitor/hmp-cmds-target.c b/monitor/hmp-cmds-target.c index 0d3e84d960..d9fbcac08d 100644 --- a/monitor/hmp-cmds-target.c +++ b/monitor/hmp-cmds-target.c @@ -81,7 +81,7 @@ CPUArchState *mon_get_cpu_env(Monitor *mon) { CPUState *cs =3D mon_get_cpu(mon); =20 - return cs ? cs->env_ptr : NULL; + return cs ? cpu_env(cs) : NULL; } =20 int monitor_get_cpu_index(Monitor *mon) diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index 564fe17f75..29c5670fdf 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -251,7 +251,7 @@ static void common_semi_dead_cb(CPUState *cs, uint64_t = ret, int err) static void common_semi_rw_cb(CPUState *cs, uint64_t ret, int err) { /* Recover the original length from the third argument. */ - CPUArchState *env G_GNUC_UNUSED =3D cs->env_ptr; + CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); target_ulong args =3D common_semi_arg(cs, 1); target_ulong arg2; GET_ARG(2); @@ -322,7 +322,7 @@ static void common_semi_readc_cb(CPUState *cs, uint64_t ret, int err) { if (!err) { - CPUArchState *env G_GNUC_UNUSED =3D cs->env_ptr; + CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); uint8_t ch; =20 if (get_user_u8(ch, common_semi_stack_bottom(cs) - 1)) { @@ -361,7 +361,7 @@ static const uint8_t featurefile_data[] =3D { */ void do_common_semihosting(CPUState *cs) { - CPUArchState *env =3D cs->env_ptr; + CPUArchState *env =3D cpu_env(cs); target_ulong args; target_ulong arg0, arg1, arg2, arg3; target_ulong ul_ret; diff --git a/semihosting/syscalls.c b/semihosting/syscalls.c index d27574a1e2..1ab4809567 100644 --- a/semihosting/syscalls.c +++ b/semihosting/syscalls.c @@ -24,7 +24,7 @@ */ static int validate_strlen(CPUState *cs, target_ulong str, target_ulong tl= en) { - CPUArchState *env G_GNUC_UNUSED =3D cs->env_ptr; + CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); char c; =20 if (tlen =3D=3D 0) { @@ -54,7 +54,7 @@ static int validate_lock_user_string(char **pstr, CPUStat= e *cs, target_ulong tstr, target_ulong tlen) { int ret =3D validate_strlen(cs, tstr, tlen); - CPUArchState *env G_GNUC_UNUSED =3D cs->env_ptr; + CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); char *str =3D NULL; =20 if (ret > 0) { @@ -74,7 +74,7 @@ static int validate_lock_user_string(char **pstr, CPUStat= e *cs, static int copy_stat_to_user(CPUState *cs, target_ulong addr, const struct stat *s) { - CPUArchState *env G_GNUC_UNUSED =3D cs->env_ptr; + CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); struct gdb_stat *p; =20 if (s->st_dev !=3D (uint32_t)s->st_dev || @@ -258,7 +258,7 @@ static void host_open(CPUState *cs, gdb_syscall_complet= e_cb complete, target_ulong fname, target_ulong fname_len, int gdb_flags, int mode) { - CPUArchState *env G_GNUC_UNUSED =3D cs->env_ptr; + CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); char *p; int ret, host_flags =3D O_BINARY; =20 @@ -316,7 +316,7 @@ static void host_close(CPUState *cs, gdb_syscall_comple= te_cb complete, static void host_read(CPUState *cs, gdb_syscall_complete_cb complete, GuestFD *gf, target_ulong buf, target_ulong len) { - CPUArchState *env G_GNUC_UNUSED =3D cs->env_ptr; + CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); void *ptr =3D lock_user(VERIFY_WRITE, buf, len, 0); ssize_t ret; =20 @@ -337,7 +337,7 @@ static void host_read(CPUState *cs, gdb_syscall_complet= e_cb complete, static void host_write(CPUState *cs, gdb_syscall_complete_cb complete, GuestFD *gf, target_ulong buf, target_ulong len) { - CPUArchState *env G_GNUC_UNUSED =3D cs->env_ptr; + CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); void *ptr =3D lock_user(VERIFY_READ, buf, len, 1); ssize_t ret; =20 @@ -411,7 +411,7 @@ static void host_stat(CPUState *cs, gdb_syscall_complet= e_cb complete, target_ulong fname, target_ulong fname_len, target_ulong addr) { - CPUArchState *env G_GNUC_UNUSED =3D cs->env_ptr; + CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); struct stat buf; char *name; int ret, err; @@ -440,7 +440,7 @@ static void host_stat(CPUState *cs, gdb_syscall_complet= e_cb complete, static void host_remove(CPUState *cs, gdb_syscall_complete_cb complete, target_ulong fname, target_ulong fname_len) { - CPUArchState *env G_GNUC_UNUSED =3D cs->env_ptr; + CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); char *p; int ret; =20 @@ -459,7 +459,7 @@ static void host_rename(CPUState *cs, gdb_syscall_compl= ete_cb complete, target_ulong oname, target_ulong oname_len, target_ulong nname, target_ulong nname_len) { - CPUArchState *env G_GNUC_UNUSED =3D cs->env_ptr; + CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); char *ostr, *nstr; int ret; =20 @@ -484,7 +484,7 @@ static void host_rename(CPUState *cs, gdb_syscall_compl= ete_cb complete, static void host_system(CPUState *cs, gdb_syscall_complete_cb complete, target_ulong cmd, target_ulong cmd_len) { - CPUArchState *env G_GNUC_UNUSED =3D cs->env_ptr; + CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); char *p; int ret; =20 @@ -502,7 +502,7 @@ static void host_system(CPUState *cs, gdb_syscall_compl= ete_cb complete, static void host_gettimeofday(CPUState *cs, gdb_syscall_complete_cb comple= te, target_ulong tv_addr, target_ulong tz_addr) { - CPUArchState *env G_GNUC_UNUSED =3D cs->env_ptr; + CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); struct gdb_timeval *p; int64_t rt; =20 @@ -547,7 +547,7 @@ static void host_poll_one(CPUState *cs, gdb_syscall_com= plete_cb complete, static void staticfile_read(CPUState *cs, gdb_syscall_complete_cb complete, GuestFD *gf, target_ulong buf, target_ulong le= n) { - CPUArchState *env G_GNUC_UNUSED =3D cs->env_ptr; + CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); target_ulong rest =3D gf->staticfile.len - gf->staticfile.off; void *ptr; =20 @@ -605,7 +605,7 @@ static void staticfile_flen(CPUState *cs, gdb_syscall_c= omplete_cb complete, static void console_read(CPUState *cs, gdb_syscall_complete_cb complete, GuestFD *gf, target_ulong buf, target_ulong len) { - CPUArchState *env G_GNUC_UNUSED =3D cs->env_ptr; + CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); char *ptr; int ret; =20 @@ -622,7 +622,7 @@ static void console_read(CPUState *cs, gdb_syscall_comp= lete_cb complete, static void console_write(CPUState *cs, gdb_syscall_complete_cb complete, GuestFD *gf, target_ulong buf, target_ulong len) { - CPUArchState *env G_GNUC_UNUSED =3D cs->env_ptr; + CPUArchState *env G_GNUC_UNUSED =3D cpu_env(cs); char *ptr =3D lock_user(VERIFY_READ, buf, len, 1); int ret; =20 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 46af6574bf..32333081d8 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2871,7 +2871,7 @@ static DisasJumpType translate_one(DisasContext *ctx,= uint32_t insn) static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPUAlphaState *env =3D cpu->env_ptr; + CPUAlphaState *env =3D cpu_env(cpu); int64_t bound; =20 ctx->tbflags =3D ctx->base.tb->flags; @@ -2917,7 +2917,7 @@ static void alpha_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPUAlphaState *env =3D cpu->env_ptr; + CPUAlphaState *env =3D cpu_env(cpu); uint32_t insn =3D translator_ldl(env, &ctx->base, ctx->base.pc_next); =20 ctx->base.pc_next +=3D 4; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d48a70c039..36797c2dd3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -80,7 +80,7 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, { /* The program counter is always up to date with CF_PCREL. */ if (!(tb_cflags(tb) & CF_PCREL)) { - CPUARMState *env =3D cs->env_ptr; + CPUARMState *env =3D cpu_env(cs); /* * It's OK to look at env for the current mode here, because it's * never possible for an AArch64 TB to chain to an AArch32 TB. @@ -97,7 +97,7 @@ void arm_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) { - CPUARMState *env =3D cs->env_ptr; + CPUARMState *env =3D cpu_env(cs); =20 if (is_a64(env)) { if (tb_cflags(tb) & CF_PCREL) { @@ -560,7 +560,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, unsigned int cur_el, bool secure, uint64_t hcr_el2) { - CPUARMState *env =3D cs->env_ptr; + CPUARMState *env =3D cpu_env(cs); bool pstate_unmasked; bool unmasked =3D false; =20 @@ -690,7 +690,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsi= gned int excp_idx, static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc =3D CPU_GET_CLASS(cs); - CPUARMState *env =3D cs->env_ptr; + CPUARMState *env =3D cpu_env(cs); uint32_t cur_el =3D arm_current_el(env); bool secure =3D arm_is_secure(env); uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); diff --git a/target/arm/helper.c b/target/arm/helper.c index 3b22596eab..096f1bbe6d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10274,7 +10274,7 @@ static const int8_t target_el_table[2][2][2][2][2][= 4] =3D { uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, uint32_t cur_el, bool secure) { - CPUARMState *env =3D cs->env_ptr; + CPUARMState *env =3D cpu_env(cs); bool rw; bool scr; bool hcr; diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index cb520efcd0..f9aff44dac 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -13853,7 +13853,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUARMState *env =3D cpu->env_ptr; + CPUARMState *env =3D cpu_env(cpu); ARMCPU *arm_cpu =3D env_archcpu(env); CPUARMTBFlags tb_flags =3D arm_tbflags_from_tb(dc->base.tb); int bound, core_mmu_idx; @@ -13959,7 +13959,7 @@ static void aarch64_tr_insn_start(DisasContextBase = *dcbase, CPUState *cpu) static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *= cpu) { DisasContext *s =3D container_of(dcbase, DisasContext, base); - CPUARMState *env =3D cpu->env_ptr; + CPUARMState *env =3D cpu_env(cpu); uint64_t pc =3D s->base.pc_next; uint32_t insn; =20 diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 2524d8f3fb..48927fbb8c 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -9089,7 +9089,7 @@ static bool insn_crosses_page(CPUARMState *env, Disas= Context *s) static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUARMState *env =3D cs->env_ptr; + CPUARMState *env =3D cpu_env(cs); ARMCPU *cpu =3D env_archcpu(env); CPUARMTBFlags tb_flags =3D arm_tbflags_from_tb(dc->base.tb); uint32_t condexec, core_mmu_idx; @@ -9317,7 +9317,7 @@ static void arm_post_translate_insn(DisasContext *dc) static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUARMState *env =3D cpu->env_ptr; + CPUARMState *env =3D cpu_env(cpu); uint32_t pc =3D dc->base.pc_next; unsigned int insn; =20 @@ -9407,7 +9407,7 @@ static bool thumb_insn_is_unconditional(DisasContext = *s, uint32_t insn) static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUARMState *env =3D cpu->env_ptr; + CPUARMState *env =3D cpu_env(cpu); uint32_t pc =3D dc->base.pc_next; uint32_t insn; bool is_16bit; diff --git a/target/avr/translate.c b/target/avr/translate.c index 8d67570d17..cdffa04519 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2657,7 +2657,7 @@ static bool canonicalize_skip(DisasContext *ctx) static void avr_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPUAVRState *env =3D cs->env_ptr; + CPUAVRState *env =3D cpu_env(cs); uint32_t tb_flags =3D ctx->base.tb->flags; =20 ctx->cs =3D cs; diff --git a/target/cris/translate.c b/target/cris/translate.c index 395ba12bea..b3974ba0bb 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -2948,7 +2948,7 @@ static unsigned int crisv32_decoder(CPUCRISState *env= , DisasContext *dc) static void cris_tr_init_disas_context(DisasContextBase *dcbase, CPUState = *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUCRISState *env =3D cs->env_ptr; + CPUCRISState *env =3D cpu_env(cs); uint32_t tb_flags =3D dc->base.tb->flags; uint32_t pc_start; =20 @@ -3006,7 +3006,7 @@ static void cris_tr_insn_start(DisasContextBase *dcba= se, CPUState *cpu) static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUCRISState *env =3D cs->env_ptr; + CPUCRISState *env =3D cpu_env(cs); unsigned int insn_len; =20 /* Pretty disas. */ diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 012c3c68ec..663b7bbc3a 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -1053,7 +1053,7 @@ static void hexagon_tr_init_disas_context(DisasContex= tBase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - HexagonCPU *hex_cpu =3D env_archcpu(cs->env_ptr); + HexagonCPU *hex_cpu =3D env_archcpu(cpu_env(cs)); uint32_t hex_flags =3D dcbase->tb->flags; =20 ctx->mem_idx =3D MMU_USER_IDX; @@ -1094,7 +1094,7 @@ static bool pkt_crosses_page(CPUHexagonState *env, Di= sasContext *ctx) static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState= *cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPUHexagonState *env =3D cpu->env_ptr; + CPUHexagonState *env =3D cpu_env(cpu); =20 decode_and_translate_packet(env, ctx); =20 diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 46c3dcaf15..f28888ccca 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -305,7 +305,7 @@ void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr= , target_ureg reg) synchronous across all processors. */ static void ptlb_work(CPUState *cpu, run_on_cpu_data data) { - CPUHPPAState *env =3D cpu->env_ptr; + CPUHPPAState *env =3D cpu_env(cpu); target_ulong addr =3D (target_ulong) data.target_ptr; hppa_tlb_entry *ent =3D hppa_find_tlb(env, addr); =20 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index a1046e4672..902cd642ae 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3450,7 +3450,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gat= e *a) =20 #ifndef CONFIG_USER_ONLY if (ctx->tb_flags & PSW_C) { - CPUHPPAState *env =3D ctx->cs->env_ptr; + CPUHPPAState *env =3D cpu_env(ctx->cs); int type =3D hppa_artype_for_page(env, ctx->base.pc_next); /* If we could not find a TLB entry, then we need to generate an ITLB miss exception so the kernel will provide it. @@ -4111,7 +4111,7 @@ static void hppa_tr_insn_start(DisasContextBase *dcba= se, CPUState *cs) static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPUHPPAState *env =3D cs->env_ptr; + CPUHPPAState *env =3D cpu_env(cs); DisasJumpType ret; int i, n; =20 diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index 066a173d26..fb769868f2 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -78,7 +78,7 @@ nvmm_set_segment(struct nvmm_x64_state_seg *nseg, const S= egmentCache *qseg) static void nvmm_set_registers(CPUState *cpu) { - CPUX86State *env =3D cpu->env_ptr; + CPUX86State *env =3D cpu_env(cpu); struct nvmm_machine *mach =3D get_nvmm_mach(); AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; @@ -215,7 +215,7 @@ nvmm_get_segment(SegmentCache *qseg, const struct nvmm_= x64_state_seg *nseg) static void nvmm_get_registers(CPUState *cpu) { - CPUX86State *env =3D cpu->env_ptr; + CPUX86State *env =3D cpu_env(cpu); struct nvmm_machine *mach =3D get_nvmm_mach(); AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; @@ -340,7 +340,7 @@ nvmm_get_registers(CPUState *cpu) static bool nvmm_can_take_int(CPUState *cpu) { - CPUX86State *env =3D cpu->env_ptr; + CPUX86State *env =3D cpu_env(cpu); AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_machine *mach =3D get_nvmm_mach(); @@ -387,7 +387,7 @@ nvmm_can_take_nmi(CPUState *cpu) static void nvmm_vcpu_pre_run(CPUState *cpu) { - CPUX86State *env =3D cpu->env_ptr; + CPUX86State *env =3D cpu_env(cpu); struct nvmm_machine *mach =3D get_nvmm_mach(); AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; @@ -473,8 +473,8 @@ static void nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit) { AccelCPUState *qcpu =3D cpu->accel; - CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; uint64_t tpr; =20 env->eflags =3D exit->exitstate.rflags; @@ -645,7 +645,7 @@ static int nvmm_handle_halted(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - CPUX86State *env =3D cpu->env_ptr; + CPUX86State *env =3D cpu_env(cpu); int ret =3D 0; =20 qemu_mutex_lock_iothread(); @@ -678,11 +678,11 @@ nvmm_inject_ud(struct nvmm_machine *mach, struct nvmm= _vcpu *vcpu) static int nvmm_vcpu_loop(CPUState *cpu) { - CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); AccelCPUState *qcpu =3D cpu->accel; struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; struct nvmm_vcpu_exit *exit =3D vcpu->exit; int ret; =20 diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index 226689a4f2..5b86f439ad 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -597,7 +597,7 @@ bool x86_cpu_tlb_fill(CPUState *cs, vaddr addr, int siz= e, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { - CPUX86State *env =3D cs->env_ptr; + CPUX86State *env =3D cpu_env(cs); TranslateResult out; TranslateFault err; =20 diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index b942c306d6..cbde3abe97 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -51,7 +51,7 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, { /* The instruction pointer is always up to date with CF_PCREL. */ if (!(tb_cflags(tb) & CF_PCREL)) { - CPUX86State *env =3D cs->env_ptr; + CPUX86State *env =3D cpu_env(cs); env->eip =3D tb->pc - tb->cs_base; } } diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index a8a4687227..c6894d66b1 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -3079,7 +3079,7 @@ static void gen_cmpxchg16b(DisasContext *s, CPUX86Sta= te *env, int modrm) be stopped. Return the next pc value */ static bool disas_insn(DisasContext *s, CPUState *cpu) { - CPUX86State *env =3D cpu->env_ptr; + CPUX86State *env =3D cpu_env(cpu); int b, prefixes; int shift; MemOp ot, aflag, dflag; @@ -6920,7 +6920,7 @@ void tcg_x86_init(void) static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState = *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUX86State *env =3D cpu->env_ptr; + CPUX86State *env =3D cpu_env(cpu); uint32_t flags =3D dc->base.tb->flags; uint32_t cflags =3D tb_cflags(dc->base.tb); int cpl =3D (flags >> HF_CPL_SHIFT) & 3; diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index 3de0dc1d46..df3aba2642 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -300,7 +300,7 @@ static SegmentCache whpx_seg_h2q(const WHV_X64_SEGMENT_= REGISTER *hs) /* X64 Extended Control Registers */ static void whpx_set_xcrs(CPUState *cpu) { - CPUX86State *env =3D cpu->env_ptr; + CPUX86State *env =3D cpu_env(cpu); HRESULT hr; struct whpx_state *whpx =3D &whpx_global; WHV_REGISTER_VALUE xcr0; @@ -321,7 +321,7 @@ static void whpx_set_xcrs(CPUState *cpu) =20 static int whpx_set_tsc(CPUState *cpu) { - CPUX86State *env =3D cpu->env_ptr; + CPUX86State *env =3D cpu_env(cpu); WHV_REGISTER_NAME tsc_reg =3D WHvX64RegisterTsc; WHV_REGISTER_VALUE tsc_val; HRESULT hr; @@ -382,8 +382,8 @@ static void whpx_set_registers(CPUState *cpu, int level) { struct whpx_state *whpx =3D &whpx_global; AccelCPUState *vcpu =3D cpu->accel; - CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; struct whpx_register_set vcxt; HRESULT hr; int idx; @@ -556,7 +556,7 @@ static void whpx_set_registers(CPUState *cpu, int level) =20 static int whpx_get_tsc(CPUState *cpu) { - CPUX86State *env =3D cpu->env_ptr; + CPUX86State *env =3D cpu_env(cpu); WHV_REGISTER_NAME tsc_reg =3D WHvX64RegisterTsc; WHV_REGISTER_VALUE tsc_val; HRESULT hr; @@ -576,7 +576,7 @@ static int whpx_get_tsc(CPUState *cpu) /* X64 Extended Control Registers */ static void whpx_get_xcrs(CPUState *cpu) { - CPUX86State *env =3D cpu->env_ptr; + CPUX86State *env =3D cpu_env(cpu); HRESULT hr; struct whpx_state *whpx =3D &whpx_global; WHV_REGISTER_VALUE xcr0; @@ -601,8 +601,8 @@ static void whpx_get_registers(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; AccelCPUState *vcpu =3D cpu->accel; - CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; struct whpx_register_set vcxt; uint64_t tpr, apic_base; HRESULT hr; @@ -1400,7 +1400,7 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exi= t_context_valid) { if (cpu->vcpu_dirty) { /* The CPU registers have been modified by other parts of QEMU. */ - CPUArchState *env =3D (CPUArchState *)(cpu->env_ptr); + CPUArchState *env =3D cpu_env(cpu); return env->eip; } else if (exit_context_valid) { /* @@ -1439,7 +1439,7 @@ static vaddr whpx_vcpu_get_pc(CPUState *cpu, bool exi= t_context_valid) =20 static int whpx_handle_halt(CPUState *cpu) { - CPUX86State *env =3D cpu->env_ptr; + CPUX86State *env =3D cpu_env(cpu); int ret =3D 0; =20 qemu_mutex_lock_iothread(); @@ -1460,8 +1460,8 @@ static void whpx_vcpu_pre_run(CPUState *cpu) HRESULT hr; struct whpx_state *whpx =3D &whpx_global; AccelCPUState *vcpu =3D cpu->accel; - CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; int irq; uint8_t tpr; WHV_X64_PENDING_INTERRUPTION_REGISTER new_int; @@ -1582,8 +1582,8 @@ static void whpx_vcpu_pre_run(CPUState *cpu) static void whpx_vcpu_post_run(CPUState *cpu) { AccelCPUState *vcpu =3D cpu->accel; - CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; =20 env->eflags =3D vcpu->exit_ctx.VpContext.Rflags; =20 @@ -1606,8 +1606,8 @@ static void whpx_vcpu_post_run(CPUState *cpu) =20 static void whpx_vcpu_process_async_events(CPUState *cpu) { - CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; AccelCPUState *vcpu =3D cpu->accel; =20 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && @@ -2147,8 +2147,8 @@ int whpx_init_vcpu(CPUState *cpu) struct whpx_state *whpx =3D &whpx_global; AccelCPUState *vcpu =3D NULL; Error *local_error =3D NULL; - CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); + CPUX86State *env =3D &x86_cpu->env; UINT64 freq =3D 0; int ret; =20 @@ -2245,7 +2245,7 @@ int whpx_init_vcpu(CPUState *cpu) cpu->vcpu_dirty =3D true; cpu->accel =3D vcpu; max_vcpu_index =3D max(max_vcpu_index, cpu->cpu_index); - qemu_add_vm_change_state_handler(whpx_cpu_update_state, cpu->env_ptr); + qemu_add_vm_change_state_handler(whpx_cpu_update_state, env); =20 return 0; =20 diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 4a4c022f51..a75fed1d98 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -104,7 +104,7 @@ static void loongarch_tr_init_disas_context(DisasContex= tBase *dcbase, CPUState *cs) { int64_t bound; - CPULoongArchState *env =3D cs->env_ptr; + CPULoongArchState *env =3D cpu_env(cs); DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 ctx->page_start =3D ctx->base.pc_first & TARGET_PAGE_MASK; @@ -265,7 +265,7 @@ static uint64_t make_address_pc(DisasContext *ctx, uint= 64_t addr) =20 static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState= *cs) { - CPULoongArchState *env =3D cs->env_ptr; + CPULoongArchState *env =3D cpu_env(cs); DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 ctx->opcode =3D translator_ldl(env, &ctx->base, ctx->base.pc_next); diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 0989a5b6bd..d22df2a8dc 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5990,7 +5990,7 @@ void register_m68k_insns (CPUM68KState *env) static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState = *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUM68KState *env =3D cpu->env_ptr; + CPUM68KState *env =3D cpu_env(cpu); =20 dc->env =3D env; dc->pc =3D dc->base.pc_first; @@ -6021,7 +6021,7 @@ static void m68k_tr_insn_start(DisasContextBase *dcba= se, CPUState *cpu) static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUM68KState *env =3D cpu->env_ptr; + CPUM68KState *env =3D cpu_env(cpu); uint16_t insn =3D read_im16(env, dc); =20 opcode_table[insn](env, dc, insn); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index bb178219f1..49bfb4a0ea 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1630,7 +1630,7 @@ static void mb_tr_insn_start(DisasContextBase *dcb, C= PUState *cs) static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) { DisasContext *dc =3D container_of(dcb, DisasContext, base); - CPUMBState *env =3D cs->env_ptr; + CPUMBState *env =3D cpu_env(cs); uint32_t ir; =20 /* TODO: This should raise an exception, not terminate qemu. */ diff --git a/target/mips/tcg/sysemu/mips-semi.c b/target/mips/tcg/sysemu/mi= ps-semi.c index f3735df7b9..b3e4e49ff7 100644 --- a/target/mips/tcg/sysemu/mips-semi.c +++ b/target/mips/tcg/sysemu/mips-semi.c @@ -126,7 +126,7 @@ static void report_fault(CPUMIPSState *env) =20 static void uhi_cb(CPUState *cs, uint64_t ret, int err) { - CPUMIPSState *env =3D cs->env_ptr; + CPUMIPSState *env =3D cpu_env(cs); =20 #define E(N) case E##N: err =3D UHI_E##N; break =20 @@ -167,7 +167,7 @@ static void uhi_fstat_cb(CPUState *cs, uint64_t ret, in= t err) QEMU_BUILD_BUG_ON(sizeof(UHIStat) < sizeof(struct gdb_stat)); =20 if (!err) { - CPUMIPSState *env =3D cs->env_ptr; + CPUMIPSState *env =3D cpu_env(cs); target_ulong addr =3D env->active_tc.gpr[5]; UHIStat *dst =3D lock_user(VERIFY_WRITE, addr, sizeof(UHIStat), 1); struct gdb_stat s; diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index c8183710e5..adbdcb1472 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15377,7 +15377,7 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState = *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPUMIPSState *env =3D cs->env_ptr; + CPUMIPSState *env =3D cpu_env(cs); =20 ctx->page_start =3D ctx->base.pc_first & TARGET_PAGE_MASK; ctx->saved_pc =3D -1; @@ -15448,7 +15448,7 @@ static void mips_tr_insn_start(DisasContextBase *dc= base, CPUState *cs) =20 static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { - CPUMIPSState *env =3D cs->env_ptr; + CPUMIPSState *env =3D cpu_env(cs); DisasContext *ctx =3D container_of(dcbase, DisasContext, base); int insn_bytes; int is_slot; diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 93ded65f9a..e806623594 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -944,7 +944,7 @@ static const char * const cr_regnames[NUM_CR_REGS] =3D { static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUNios2State *env =3D cs->env_ptr; + CPUNios2State *env =3D cpu_env(cs); Nios2CPU *cpu =3D env_archcpu(env); int page_insns; =20 @@ -970,7 +970,7 @@ static void nios2_tr_insn_start(DisasContextBase *dcbas= e, CPUState *cs) static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUNios2State *env =3D cs->env_ptr; + CPUNios2State *env =3D cpu_env(cs); const Nios2Instruction *instr; uint32_t code, pc; uint8_t op; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 1b4df1c214..ecff4412b7 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1525,7 +1525,7 @@ static bool trans_lf_sfun_d(DisasContext *dc, arg_ab_= pair *a) static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState= *cs) { DisasContext *dc =3D container_of(dcb, DisasContext, base); - CPUOpenRISCState *env =3D cs->env_ptr; + CPUOpenRISCState *env =3D cpu_env(cs); int bound; =20 dc->mem_idx =3D cpu_mmu_index(env, false); diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 72ec2be92e..437527a47c 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -3189,7 +3189,7 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr = vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - CPUPPCState *env =3D cs->env_ptr; + CPUPPCState *env =3D cpu_env(cs); uint32_t insn; =20 /* Restore state and reload the insn we executed, for filling in DSISR= . */ @@ -3220,7 +3220,7 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr) { - CPUPPCState *env =3D cs->env_ptr; + CPUPPCState *env =3D cpu_env(cs); =20 switch (env->excp_model) { #if defined(TARGET_PPC64) @@ -3264,7 +3264,7 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwad= dr physaddr, void ppc_cpu_debug_excp_handler(CPUState *cs) { #if defined(TARGET_PPC64) - CPUPPCState *env =3D cs->env_ptr; + CPUPPCState *env =3D cpu_env(cs); =20 if (env->insns_flags2 & PPC2_ISA207S) { if (cs->watchpoint_hit) { @@ -3286,7 +3286,7 @@ void ppc_cpu_debug_excp_handler(CPUState *cs) bool ppc_cpu_debug_check_breakpoint(CPUState *cs) { #if defined(TARGET_PPC64) - CPUPPCState *env =3D cs->env_ptr; + CPUPPCState *env =3D cpu_env(cs); =20 if (env->insns_flags2 & PPC2_ISA207S) { target_ulong priv; @@ -3313,7 +3313,7 @@ bool ppc_cpu_debug_check_breakpoint(CPUState *cs) bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) { #if defined(TARGET_PPC64) - CPUPPCState *env =3D cs->env_ptr; + CPUPPCState *env =3D cpu_env(cs); =20 if (env->insns_flags2 & PPC2_ISA207S) { if (wp =3D=3D env->dawr0_watchpoint) { diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e20a1bea62..329da4d518 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7320,7 +7320,7 @@ static bool decode_legacy(PowerPCCPU *cpu, DisasConte= xt *ctx, uint32_t insn) static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPUPPCState *env =3D cs->env_ptr; + CPUPPCState *env =3D cpu_env(cs); uint32_t hflags =3D ctx->base.tb->flags; =20 ctx->spr_cb =3D env->spr_cb; @@ -7384,7 +7384,7 @@ static void ppc_tr_translate_insn(DisasContextBase *d= cbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D cs->env_ptr; + CPUPPCState *env =3D cpu_env(cs); target_ulong pc; uint32_t insn; bool ok; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2ad5192866..f0be79bb16 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1074,7 +1074,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUState *cpu =3D ctx->cs; - CPURISCVState *env =3D cpu->env_ptr; + CPURISCVState *env =3D cpu_env(cpu); =20 return cpu_ldl_code(env, pc); } @@ -1166,7 +1166,7 @@ static void decode_opc(CPURISCVState *env, DisasConte= xt *ctx, uint16_t opcode) static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPURISCVState *env =3D cs->env_ptr; + CPURISCVState *env =3D cpu_env(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); uint32_t tb_flags =3D ctx->base.tb->flags; =20 @@ -1219,7 +1219,7 @@ static void riscv_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPURISCVState *env =3D cpu->env_ptr; + CPURISCVState *env =3D cpu_env(cpu); uint16_t opcode16 =3D translator_lduw(env, &ctx->base, ctx->base.pc_ne= xt); =20 ctx->ol =3D ctx->xl; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 51559943fb..2e7a736590 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -183,12 +183,9 @@ static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, = int size, =20 static void rx_cpu_init(Object *obj) { - CPUState *cs =3D CPU(obj); RXCPU *cpu =3D RX_CPU(obj); - CPURXState *env =3D &cpu->env; =20 cpu_set_cpustate_pointers(cpu); - cs->env_ptr =3D env; qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); } =20 diff --git a/target/rx/translate.c b/target/rx/translate.c index 9fd4d36b08..f8860830ae 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2200,7 +2200,7 @@ static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) =20 static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *c= s) { - CPURXState *env =3D cs->env_ptr; + CPURXState *env =3D cpu_env(cs); DisasContext *ctx =3D container_of(dcbase, DisasContext, base); ctx->env =3D env; ctx->tb_flags =3D ctx->base.tb->flags; diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 22f43974dd..4bae1509f5 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6463,7 +6463,7 @@ static target_ulong get_next_pc(CPUS390XState *env, D= isasContext *s, =20 static void s390x_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { - CPUS390XState *env =3D cs->env_ptr; + CPUS390XState *env =3D cpu_env(cs); DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 dc->base.is_jmp =3D translate_one(env, dc); diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index a663335c39..ada41ba0a2 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -29,7 +29,7 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr a= ddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) { - CPUSH4State *env =3D cs->env_ptr; + CPUSH4State *env =3D cpu_env(cs); =20 env->tea =3D addr; switch (access_type) { diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 30e3ea509b..cbd8dfc02f 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2179,7 +2179,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4Stat= e *env) static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPUSH4State *env =3D cs->env_ptr; + CPUSH4State *env =3D cpu_env(cs); uint32_t tbflags; int bound; =20 @@ -2236,7 +2236,7 @@ static void sh4_tr_insn_start(DisasContextBase *dcbas= e, CPUState *cs) =20 static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { - CPUSH4State *env =3D cs->env_ptr; + CPUSH4State *env =3D cpu_env(cs); DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 #ifdef CONFIG_USER_ONLY diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 71b48cb3b7..f92ff80ac8 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5568,7 +5568,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUSPARCState *env =3D cs->env_ptr; + CPUSPARCState *env =3D cpu_env(cs); int bound; =20 dc->pc =3D dc->base.pc_first; @@ -5625,7 +5625,7 @@ static void sparc_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cs) static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUSPARCState *env =3D cs->env_ptr; + CPUSPARCState *env =3D cpu_env(cs); unsigned int insn; =20 insn =3D translator_ldl(env, &dc->base, dc->pc); diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 4206728afd..1b625629bb 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8331,7 +8331,7 @@ static void tricore_tr_init_disas_context(DisasContex= tBase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPUTriCoreState *env =3D cs->env_ptr; + CPUTriCoreState *env =3D cpu_env(cs); ctx->mem_idx =3D cpu_mmu_index(env, false); =20 uint32_t tb_flags =3D (uint32_t)ctx->base.tb->flags; @@ -8376,7 +8376,7 @@ static bool insn_crosses_page(CPUTriCoreState *env, D= isasContext *ctx) static void tricore_tr_translate_insn(DisasContextBase *dcbase, CPUState *= cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPUTriCoreState *env =3D cpu->env_ptr; + CPUTriCoreState *env =3D cpu_env(cpu); uint16_t insn_lo; bool is_16bit; =20 diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index fca1b9aba4..54bee7ddba 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1140,7 +1140,7 @@ static void xtensa_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUXtensaState *env =3D cpu->env_ptr; + CPUXtensaState *env =3D cpu_env(cpu); uint32_t tb_flags =3D dc->base.tb->flags; =20 dc->config =3D env->config; @@ -1180,7 +1180,7 @@ static void xtensa_tr_insn_start(DisasContextBase *dc= base, CPUState *cpu) static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *c= pu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); - CPUXtensaState *env =3D cpu->env_ptr; + CPUXtensaState *env =3D cpu_env(cpu); target_ulong page_start; =20 /* These two conditions only apply to the first insn in the TB, diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index af1878c38a..7d76f15275 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -1595,7 +1595,7 @@ illegal: */ static void disas_insn_new(DisasContext *s, CPUState *cpu, int b) { - CPUX86State *env =3D cpu->env_ptr; + CPUX86State *env =3D cpu_env(cpu); bool first =3D true; X86DecodedInsn decode; X86DecodeFunc decode_func =3D decode_root; --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900499; x=1695505299; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5yhIAIwYmQRlofGDQOUXCup3FtVZODPpAHGwhbQdmiE=; b=GAmz/2xSdMCQk/gOWxvbfPPKDu4/ohUjGehy0V1LpUUWD/Muuc3uL4MSydXEb/ezhq oegZSqLvf3u7VbKKPpPOegKr8nTpWQAc+zYx5M0gy5VCx6WvBdMT8MrWzq1r6h6vTyqx jlV0CDds4sX58boGDfZpcKMDu+xojyXUVhyEbZBlwA0eZeqG4Sp1/8+tErReWeqKzCk/ Md0A0EZKFvidOxzBVfpI9RHXOemOvjazK7xaPxvM61TVsARwek78uf9F6jY73RFyJ1j/ 51we3R+e2wwqBMtr9PhCbf/l+7sjF1xrrtEk8jUN70C/J8l9/EiZYv1sWkbJZj2a7vP3 A1fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900499; x=1695505299; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5yhIAIwYmQRlofGDQOUXCup3FtVZODPpAHGwhbQdmiE=; b=h3QYd8mDTxdaqpb6tGTmkHQZ0AorW+PV50KJ51vxbxfyUdVdH5yiFoym/LcjvZRbCS jYunENZl5lR/YhGP1213QZeAF4fopgXRZwx4EDI8RZvHee3SRnAU9vqb5thx7x6i37yc sYhHIDecWtVvuvDSOj+mYieOEqRO4qqVzf3KcP7MW+81mrmv6pGgUqkfss4lD9VX6R8L 83y5LOQjhz0HpbCr3vHu0Dsbux/SOPuU67aLe1f5Mjebf7+WXHFSldrWGXEG/8f3lwCT mnAo9gacr5fdpm0Z2ges18ddjfJTfOOOmiXyyI7WWD5SeOZTOLcirnEeDcvfz20p7luW kIkg== X-Gm-Message-State: AOJu0Yweof/gK2FhWQavMVJSK18onNJesAUCrVfZiW+xu93mvrpjEUEG RYS1dLNgbtv7cVdnAGOqSkZ3dbHhOVBe2GmHPmI= X-Google-Smtp-Source: AGHT+IFuRjvQWfCi0FLbX8LX+ykod8+lwr1ju7lbNUjOXfxZyE34x2xVM4Jk9l6DAnHzZB6BCye4LA== X-Received: by 2002:a05:6a20:3942:b0:12e:73bb:cbb6 with SMTP id r2-20020a056a20394200b0012e73bbcbb6mr7051443pzg.14.1694900499170; Sat, 16 Sep 2023 14:41:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 13/39] accel/tcg: Remove cpu_set_cpustate_pointers Date: Sat, 16 Sep 2023 14:40:57 -0700 Message-Id: <20230916214123.525796-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900625118100005 This function is now empty, so remove it. In the case of m68k and tricore, this empties the class instance initfn, so remove those as well. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 10 ---------- target/alpha/cpu.c | 2 -- target/arm/cpu.c | 1 - target/avr/cpu.c | 2 -- target/cris/cpu.c | 2 -- target/hexagon/cpu.c | 3 --- target/hppa/cpu.c | 1 - target/i386/cpu.c | 1 - target/loongarch/cpu.c | 8 +++----- target/m68k/cpu.c | 8 -------- target/microblaze/cpu.c | 1 - target/mips/cpu.c | 1 - target/nios2/cpu.c | 4 +--- target/openrisc/cpu.c | 6 +----- target/ppc/cpu_init.c | 1 - target/riscv/cpu.c | 6 +----- target/rx/cpu.c | 1 - target/s390x/cpu.c | 2 -- target/sh4/cpu.c | 2 -- target/sparc/cpu.c | 2 -- target/tricore/cpu.c | 9 --------- target/xtensa/cpu.c | 1 - 22 files changed, 6 insertions(+), 68 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index bff3867c1e..477e59b4b3 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -425,16 +425,6 @@ int cpu_exec(CPUState *cpu); void tcg_exec_realizefn(CPUState *cpu, Error **errp); void tcg_exec_unrealizefn(CPUState *cpu); =20 -/** - * cpu_set_cpustate_pointers(cpu) - * @cpu: The cpu object - * - * Set the generic pointers in CPUState into the outer object. - */ -static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) -{ -} - /* Validate correct placement of CPUArchState. */ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) !=3D 0); QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) !=3D sizeof(CPUState)); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index e2156fcb41..51b7d8d1bf 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -209,8 +209,6 @@ static void alpha_cpu_initfn(Object *obj) AlphaCPU *cpu =3D ALPHA_CPU(obj); CPUAlphaState *env =3D &cpu->env; =20 - cpu_set_cpustate_pointers(cpu); - env->lock_addr =3D -1; #if defined(CONFIG_USER_ONLY) env->flags =3D ENV_FLAG_PS_USER | ENV_FLAG_FEN; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 36797c2dd3..831295d7cd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1215,7 +1215,6 @@ static void arm_cpu_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); =20 - cpu_set_cpustate_pointers(cpu); cpu->cp_regs =3D g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL, g_free); =20 diff --git a/target/avr/cpu.c b/target/avr/cpu.c index c5a6436336..14d8b9d1f0 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -147,8 +147,6 @@ static void avr_cpu_initfn(Object *obj) { AVRCPU *cpu =3D AVR_CPU(obj); =20 - cpu_set_cpustate_pointers(cpu); - /* Set the number of interrupts supported by the CPU. */ qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int, sizeof(cpu->env.intsrc) * 8); diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 8ab8a30b8d..be4a44c218 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -201,8 +201,6 @@ static void cris_cpu_initfn(Object *obj) CRISCPUClass *ccc =3D CRIS_CPU_GET_CLASS(obj); CPUCRISState *env =3D &cpu->env; =20 - cpu_set_cpustate_pointers(cpu); - env->pregs[PR_VR] =3D ccc->vr; =20 #ifndef CONFIG_USER_ONLY diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 65f198b956..1adc11b713 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -353,9 +353,6 @@ static void hexagon_cpu_realize(DeviceState *dev, Error= **errp) =20 static void hexagon_cpu_init(Object *obj) { - HexagonCPU *cpu =3D HEXAGON_CPU(obj); - - cpu_set_cpustate_pointers(cpu); qdev_property_add_static(DEVICE(obj), &hexagon_lldb_compat_property); qdev_property_add_static(DEVICE(obj), &hexagon_lldb_stack_adjust_prope= rty); qdev_property_add_static(DEVICE(obj), &hexagon_short_circuit_property); diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 17fa901f6a..1644297bf8 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -149,7 +149,6 @@ static void hppa_cpu_initfn(Object *obj) HPPACPU *cpu =3D HPPA_CPU(obj); CPUHPPAState *env =3D &cpu->env; =20 - cpu_set_cpustate_pointers(cpu); cs->exception_index =3D -1; cpu_hppa_loaded_fr0(env); cpu_hppa_put_psw(env, PSW_W); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7f15ea4ec4..66ab092628 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7588,7 +7588,6 @@ static void x86_cpu_initfn(Object *obj) CPUX86State *env =3D &cpu->env; =20 env->nr_dies =3D 1; - cpu_set_cpustate_pointers(cpu); =20 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", x86_cpu_get_feature_words, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 56e67cea8d..e70773c22e 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -614,17 +614,15 @@ static const MemoryRegionOps loongarch_qemu_ops =3D { =20 static void loongarch_cpu_init(Object *obj) { - LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); - - cpu_set_cpustate_pointers(cpu); - #ifndef CONFIG_USER_ONLY + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); CPULoongArchState *env =3D &cpu->env; + qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS); timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL, &loongarch_constant_timer_cb, cpu); memory_region_init_io(&env->system_iocsr, OBJECT(cpu), NULL, - env, "iocsr", UINT64_MAX); + env, "iocsr", UINT64_MAX); address_space_init(&env->address_space_iocsr, &env->system_iocsr, "IOC= SR"); memory_region_init_io(&env->iocsr_mem, OBJECT(cpu), &loongarch_qemu_op= s, NULL, "iocsr_misc", 0x428); diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index d34d1b57d0..538d9473c2 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -327,13 +327,6 @@ static void m68k_cpu_realizefn(DeviceState *dev, Error= **errp) mcc->parent_realize(dev, errp); } =20 -static void m68k_cpu_initfn(Object *obj) -{ - M68kCPU *cpu =3D M68K_CPU(obj); - - cpu_set_cpustate_pointers(cpu); -} - #if !defined(CONFIG_USER_ONLY) static bool fpu_needed(void *opaque) { @@ -612,7 +605,6 @@ static const TypeInfo m68k_cpus_type_infos[] =3D { .parent =3D TYPE_CPU, .instance_size =3D sizeof(M68kCPU), .instance_align =3D __alignof(M68kCPU), - .instance_init =3D m68k_cpu_initfn, .abstract =3D true, .class_size =3D sizeof(M68kCPUClass), .class_init =3D m68k_cpu_class_init, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index c53711da52..bbb3335cad 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -296,7 +296,6 @@ static void mb_cpu_initfn(Object *obj) MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(obj); CPUMBState *env =3D &cpu->env; =20 - cpu_set_cpustate_pointers(cpu); gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect, mb_cpu_gdb_write_stack_protect, 2, "microblaze-stack-protect.xml", 0); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index fee791aa44..a0023edd43 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -504,7 +504,6 @@ static void mips_cpu_initfn(Object *obj) CPUMIPSState *env =3D &cpu->env; MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(obj); =20 - cpu_set_cpustate_pointers(cpu); cpu->clock =3D qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); cpu->count_div =3D clock_new(OBJECT(obj), "clk-div-count"); env->count_clock =3D clock_new(OBJECT(obj), "clk-count"); diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 598976305f..15e499f828 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -113,11 +113,9 @@ static void iic_set_irq(void *opaque, int irq, int lev= el) =20 static void nios2_cpu_initfn(Object *obj) { +#if !defined(CONFIG_USER_ONLY) Nios2CPU *cpu =3D NIOS2_CPU(obj); =20 - cpu_set_cpustate_pointers(cpu); - -#if !defined(CONFIG_USER_ONLY) mmu_init(&cpu->env); #endif } diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index be067709b8..f5a3d5273b 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -149,12 +149,8 @@ static void openrisc_cpu_realizefn(DeviceState *dev, E= rror **errp) =20 static void openrisc_cpu_initfn(Object *obj) { - OpenRISCCPU *cpu =3D OPENRISC_CPU(obj); - - cpu_set_cpustate_pointers(cpu); - #ifndef CONFIG_USER_ONLY - qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_I= RQS); + qdev_init_gpio_in_named(DEVICE(obj), openrisc_cpu_set_irq, "IRQ", NR_I= RQS); #endif } =20 diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 7ab5ee92d9..85dbf54192 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7246,7 +7246,6 @@ static void ppc_cpu_instance_init(Object *obj) PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env =3D &cpu->env; =20 - cpu_set_cpustate_pointers(cpu); cpu->vcpu_id =3D UNASSIGNED_CPU_INDEX; =20 env->msr_mask =3D pcc->msr_mask; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8a765d5117..6fca8ce0d2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1649,12 +1649,8 @@ static void riscv_cpu_set_irq(void *opaque, int irq,= int level) =20 static void riscv_cpu_init(Object *obj) { - RISCVCPU *cpu =3D RISCV_CPU(obj); - - cpu_set_cpustate_pointers(cpu); - #ifndef CONFIG_USER_ONLY - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, + qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); #endif /* CONFIG_USER_ONLY */ } diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 2e7a736590..4d0d3a0c8c 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -185,7 +185,6 @@ static void rx_cpu_init(Object *obj) { RXCPU *cpu =3D RX_CPU(obj); =20 - cpu_set_cpustate_pointers(cpu); qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); } =20 diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index df167493c3..4f7599d72c 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -274,9 +274,7 @@ out: static void s390_cpu_initfn(Object *obj) { CPUState *cs =3D CPU(obj); - S390CPU *cpu =3D S390_CPU(obj); =20 - cpu_set_cpustate_pointers(cpu); cs->exception_index =3D EXCP_HLT; =20 #if !defined(CONFIG_USER_ONLY) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index a90e41c4ec..788e41fea6 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -239,8 +239,6 @@ static void superh_cpu_initfn(Object *obj) SuperHCPU *cpu =3D SUPERH_CPU(obj); CPUSH4State *env =3D &cpu->env; =20 - cpu_set_cpustate_pointers(cpu); - env->movcal_backup_tail =3D &(env->movcal_backup); } =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index d6d3c4b031..8ba96ae225 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -793,8 +793,6 @@ static void sparc_cpu_initfn(Object *obj) SPARCCPUClass *scc =3D SPARC_CPU_GET_CLASS(obj); CPUSPARCState *env =3D &cpu->env; =20 - cpu_set_cpustate_pointers(cpu); - if (scc->cpu_def) { env->def =3D *scc->cpu_def; } diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 50aec6cf10..d1477622e6 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -124,14 +124,6 @@ static void tricore_cpu_realizefn(DeviceState *dev, Er= ror **errp) tcc->parent_realize(dev, errp); } =20 - -static void tricore_cpu_initfn(Object *obj) -{ - TriCoreCPU *cpu =3D TRICORE_CPU(obj); - - cpu_set_cpustate_pointers(cpu); -} - static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; @@ -231,7 +223,6 @@ static const TypeInfo tricore_cpu_type_infos[] =3D { .parent =3D TYPE_CPU, .instance_size =3D sizeof(TriCoreCPU), .instance_align =3D __alignof(TriCoreCPU), - .instance_init =3D tricore_cpu_initfn, .abstract =3D true, .class_size =3D sizeof(TriCoreCPUClass), .class_init =3D tricore_cpu_class_init, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 281872d7ca..ea1dae7390 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -185,7 +185,6 @@ static void xtensa_cpu_initfn(Object *obj) XtensaCPUClass *xcc =3D XTENSA_CPU_GET_CLASS(obj); CPUXtensaState *env =3D &cpu->env; =20 - cpu_set_cpustate_pointers(cpu); env->config =3D xcc->config; =20 #ifndef CONFIG_USER_ONLY --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900500; x=1695505300; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6QVLNJyN2G52bpcFup5Ax4sLOIg8vU0FXaShnSFcJ5A=; b=RP0Ao3mFU/fMl9Jvrg3UruhBM3LguDCUmSmf2O9jGZXbCrGFftNNMMLpkuWDYXaS7x aZ5yh9ccRByPZDtyn3NXIfcHrVkEOQitg2whNwww+3Kf4FmslHbfKHGWStvSBpZ0k072 Khk8v2HLZUonH9FoqK/gf24ycixIUZxmIARxZiXgkl5LHldFIeFgBxpYXvw9spVEAK9e xFpFjazFkA96MJcLU3ePuTK+uDpCZVnkO2/CDSIACzLzePDxOz8/oi8wFjF+V6sKgV+S juFUMj2T3hc79FIgFEJlkPiYLoB8mD58/KKRPbMGMa/jU0oZzW3ySac/9BcZvsABTqfE Pe4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900500; x=1695505300; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6QVLNJyN2G52bpcFup5Ax4sLOIg8vU0FXaShnSFcJ5A=; b=hC/N1hvv8as0cSpnw9FVp47iCfxpNT3aPnjQs6+BI4oulcg/YKDTir/BuBeYIh9s/0 9JLvwgdDHpkVoXEMQgsyja4sFB7yzHrI0Vn3km+cWoX5mddWOTkrtSOa4imid607o4rY njZuVraCvF1lpiGvNqMnOmM0rEdzjtocz/O/wgZw6OQpqEPSeJQlIBbbqzyuapane2g4 D2yfQ4U9pOqK8iiBDFcVMrHaMlk9y2fjfiJrpfd6cworEPU/JhHcfhktux1QaEowFN3u 6sBlqXfuPo+C+NoBsnKrGTuwyaoOP9dRWNH0oKrCDsb0mJ3g1gWvh5xfIx1B7fzplzVg CWzg== X-Gm-Message-State: AOJu0YyX+30U3t7SBo5tEeNsOunkJ2VsmNlv94HspO/jIzIKCCOXS9Ad lFRtu+dNNjsU6ZJRP86ElqzCpSBwlvr15quTWr4= X-Google-Smtp-Source: AGHT+IGC04a1QgIU0shTTJpFrgKqm1nXBn3bvSugf5LNhGqnsBkTs+I4aFJxFfqd43VOQWbJS+2skQ== X-Received: by 2002:a05:6a00:3014:b0:68f:cdb8:ae33 with SMTP id ay20-20020a056a00301400b0068fcdb8ae33mr12517557pfb.10.1694900499894; Sat, 16 Sep 2023 14:41:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 14/39] accel/tcg: Remove env_neg() Date: Sat, 16 Sep 2023 14:40:58 -0700 Message-Id: <20230916214123.525796-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900572090100001 Content-Type: text/plain; charset="utf-8" Replace the single use within env_tlb() and remove. Reviewed-by: Anton Johansson Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-all.h | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 477e59b4b3..af9516654a 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -451,17 +451,6 @@ static inline CPUState *env_cpu(CPUArchState *env) return (void *)env - sizeof(CPUState); } =20 -/** - * env_neg(env) - * @env: The architecture environment - * - * Return the CPUNegativeOffsetState associated with the environment. - */ -static inline CPUNegativeOffsetState *env_neg(CPUArchState *env) -{ - return &env_cpu(env)->neg; -} - /** * env_tlb(env) * @env: The architecture environment @@ -470,7 +459,7 @@ static inline CPUNegativeOffsetState *env_neg(CPUArchSt= ate *env) */ static inline CPUTLB *env_tlb(CPUArchState *env) { - return &env_neg(env)->tlb; + return &env_cpu(env)->neg.tlb; } =20 #endif /* CPU_ALL_H */ --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900582; cv=none; d=zohomail.com; s=zohoarc; b=KIxdqS8koTuGKkPS2HiyXN+RVWT/KWF/a59ptJjX+KU+n2WbmFps6Th0LGoHU9rirPKgDo903Z3JinK+boRXgRmj7JC6XFQpZEm7dQtkSqdzKRZGYBd36mKXOW1NTy+SKrympKJ8hM0eFwJ7MHoieHtWBOg3TvpQUYYpe+I97ZA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900582; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GwL0g4t7pLWk/ND+/4S+A46VLWCkPxcxxcvyHi0Mx8k=; b=ZJk4dN7/pn0ZHE/phLsk6jdA9dEi1Ty+RI3QnFgkL7lWJeYlc+G6f29HiEvD48MPTC274qsVyJU/m0aXhZQLSZ6XGq7YbFPddIqRoJWHrJ0VR4Po9OaOMiLTgjTVg4UkIqUojjq0jaxQY0V/sjpTCNIP/gXA/WD7Rz4ibKMitZ0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900582670161.20359046253793; Sat, 16 Sep 2023 14:43:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd2z-0005BD-Ns; Sat, 16 Sep 2023 17:41:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd2x-0005A5-8w for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:47 -0400 Received: from mail-ot1-x334.google.com ([2607:f8b0:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd2s-0000Sa-06 for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:47 -0400 Received: by mail-ot1-x334.google.com with SMTP id 46e09a7af769-6bd0a0a6766so2164887a34.2 for ; Sat, 16 Sep 2023 14:41:41 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900501; x=1695505301; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GwL0g4t7pLWk/ND+/4S+A46VLWCkPxcxxcvyHi0Mx8k=; b=ElO/TSVxTvZL684QYwJlQsvzDGYWPnnBFEkKPHa+FqccFMGW6y6/eSb2Ij4f3xLMya Dru1hXTasTPjxxSStJ8eF7n/QGYq7eZM4qsPJQr3hh1xHYJhB6AbPkT5navhtACB8obN ufcvs/joGRa6n8nclJGrqT093ILIR1HqTKl2KAS9lS8ea3Grj9HkuWY5W/A46OhsgLS3 ONc1uGo17Ah2LntJT77xs70QXE0UyOS2m8SQ3IzFeq+qLe+om4tBKU8g5TUg+xKIhuXC E0mZxyUm6g1cp25LcPzeyCpDD/teifvSDj1hHflEF3au/jX9YANd9hYhhRh6LtESfPFv LzXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900501; x=1695505301; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GwL0g4t7pLWk/ND+/4S+A46VLWCkPxcxxcvyHi0Mx8k=; b=reoepyo+mCRufRxKvhSBhgfUY8a0oYPg/ZWRd79NqsoxjIsuQsy4/rF86MYF0GvffH VBdoJAP+8VJv2bozzwAX4UER1pLYgJcb9ZORyJBNGB2c8eR9V0yZSpQKqGq8r/fTcxSJ TGGXXzTZC7nNDn4fQN823n1xijo1eKXVKW/upLfxzaDUaGaOZ/+XmlFTHYoWTHJ+TKMH OKx0hGDBGjtdMpRCGibMTnm4BiZSe+EeoftfimdUkYE0NXKRZM9stTpeBDOOIfuG64RX q8157p8IjpBqd2g8mSfUviv8qvyl9HDoae0mtty4x8juYdLytP1npvWLoTGTbo8JT1k1 KVNA== X-Gm-Message-State: AOJu0YxF6SIWdljFInogOidkBIw3yAYi4on61QQRY7ZAWbIX0265zkbr 5TjPt+XPw3bglvkP+MRJhAiwUgZz+4t0P3Z0gHI= X-Google-Smtp-Source: AGHT+IGHBlmSWs47ILLmevgB0EfOHGWsZ/E0m050newPVh9I49bj+s08dd69Xu5pRB0bgNhku1KVCQ== X-Received: by 2002:a05:6358:5929:b0:135:99fa:5040 with SMTP id g41-20020a056358592900b0013599fa5040mr5851475rwf.12.1694900500719; Sat, 16 Sep 2023 14:41:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 15/39] tcg: Remove TCGContext.tlb_fast_offset Date: Sat, 16 Sep 2023 14:40:59 -0700 Message-Id: <20230916214123.525796-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900583205100001 Content-Type: text/plain; charset="utf-8" Now that there is no padding between CPUNegativeOffsetState and CPUArchState, this value is constant across all targets. Reviewed-by: Anton Johansson Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 - accel/tcg/translate-all.c | 2 -- tcg/tcg.c | 15 +++++++++------ 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 3cdbeaf460..7743868dc9 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -489,7 +489,6 @@ struct TCGContext { TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */ =20 #ifdef CONFIG_SOFTMMU - int tlb_fast_offset; int page_mask; uint8_t page_bits; uint8_t tlb_dyn_max_bits; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 6fac5b7e29..83e07b830f 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -344,8 +344,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->page_bits =3D TARGET_PAGE_BITS; tcg_ctx->page_mask =3D TARGET_PAGE_MASK; tcg_ctx->tlb_dyn_max_bits =3D CPU_TLB_DYN_MAX_BITS; - tcg_ctx->tlb_fast_offset =3D (int)offsetof(ArchCPU, parent_obj.neg.tlb= .f) - - (int)offsetof(ArchCPU, env); #endif tcg_ctx->insn_start_words =3D TARGET_INSN_START_WORDS; #ifdef TCG_GUEST_DEFAULT_MO diff --git a/tcg/tcg.c b/tcg/tcg.c index 72b113ad53..c72790cdf1 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -406,7 +406,8 @@ static uintptr_t G_GNUC_UNUSED get_jmp_target_addr(TCGC= ontext *s, int which) #if defined(CONFIG_SOFTMMU) && !defined(CONFIG_TCG_INTERPRETER) static int tlb_mask_table_ofs(TCGContext *s, int which) { - return s->tlb_fast_offset + which * sizeof(CPUTLBDescFast); + return (offsetof(CPUNegativeOffsetState, tlb.f[which]) - + sizeof(CPUNegativeOffsetState)); } #endif =20 @@ -734,6 +735,13 @@ static const TCGTargetOpDef constraint_sets[] =3D { =20 #include "tcg-target.c.inc" =20 +#ifndef CONFIG_TCG_INTERPRETER +/* Validate CPUTLBDescFast placement. */ +QEMU_BUILD_BUG_ON((int)(offsetof(CPUNegativeOffsetState, tlb.f[0]) - + sizeof(CPUNegativeOffsetState)) + < MIN_TLB_MASK_TABLE_OFS); +#endif + static void alloc_tcg_plugin_context(TCGContext *s) { #ifdef CONFIG_PLUGIN @@ -1497,11 +1505,6 @@ void tcg_func_start(TCGContext *s) tcg_debug_assert(s->addr_type =3D=3D TCG_TYPE_I32 || s->addr_type =3D=3D TCG_TYPE_I64); =20 -#if defined(CONFIG_SOFTMMU) && !defined(CONFIG_TCG_INTERPRETER) - tcg_debug_assert(s->tlb_fast_offset < 0); - tcg_debug_assert(s->tlb_fast_offset >=3D MIN_TLB_MASK_TABLE_OFS); -#endif - tcg_debug_assert(s->insn_start_words > 0); } =20 --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900612; cv=none; d=zohomail.com; s=zohoarc; b=V9GKCl5kTRI083BD3TVNvQ4ydcyQ8V4/fquTSrYHIJA+kDRZUtDcO+rTFQjnwQIVVS+VBGBSt4WXzdH3WfprTv7+ZfMls5JVQ2hmCP+F8jzt5B34BqPQr7Lc2z0TbX/I6eFZxiW/Yl8UHsnvc87pwf8oNccoNErf/RlM73OImTk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900612; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Eqdx5KYfe7+Tgpre/r7adTy9jlck+D44aSymYCDoQAc=; b=CnfF6AOLaQUTLmDJb5rb03Ds6JzxQ2mnPatKCENUDj+ml4pN+QsRkkkbyEnFxh/x5PRJSIHNnxyMR0U6+7Uc40n0lOc/SQKf6IWW6YQrMzh3LZxQ3LO2ugJ0aYFR6qNu196nb6mmsVdfK03C7hn2i1tQMJE7m8m29a2IsSZii8w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900611976810.2966081747443; Sat, 16 Sep 2023 14:43:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd32-0005CU-DT; Sat, 16 Sep 2023 17:41:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd2y-0005AT-LA for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:48 -0400 Received: from mail-oa1-x32.google.com ([2001:4860:4864:20::32]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd2t-0000Sg-BS for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:48 -0400 Received: by mail-oa1-x32.google.com with SMTP id 586e51a60fabf-1c504386370so2017818fac.1 for ; Sat, 16 Sep 2023 14:41:43 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900502; x=1695505302; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Eqdx5KYfe7+Tgpre/r7adTy9jlck+D44aSymYCDoQAc=; b=RfcDki/Y13BUGq6pMNr8KJ5uN6DBfKutzo5IG7fE9s28WsBje0azxhZr35bwBoTGZv 8jnaBQ8ErzDJZcRpC5YcADxpjtNUeG3Havvvne4o5kbJ7jWhj+Nb9FEGpqtIJ8yt0sWy NC16YrE1hepNpyJFHveeOBeP2ydcayhZVapoI3nlLIZQb1rmAy7muZPi7b2GhOlfBknx YWpmuf5bmLZX2MdxvyS3XF/1dYHvHjr3mgddDB4hUBvTrteMnw3ugqG41hfs8IGtyBm8 b4BTcRV3ToVo4ykSSfPv8XJ4HDABOSnNbuPctdTQjfQQeZjwBwu9Y9JQZbut0KhLHHq7 qEBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900502; x=1695505302; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Eqdx5KYfe7+Tgpre/r7adTy9jlck+D44aSymYCDoQAc=; b=A6FsvKynMFpRuA0anofIMlG4Qngga/y66B2m625/Qvkp3DLtafFeZJu4pB+mzhbg8R 8vgVxx3vAPFlIEcsn0Xr+TSNngb5GC0hBhEt+5Vq+IPVUn+djQY5xM3wbJrbWmzFuxsQ pFkXRqGG42oNaCzjAYqokVXejzDhkUMlfDL8thONiC3Z6U2EIVCvdwk0rPomsi3fwrIJ J2pk9SmaHM8PHFMFw7fspX8Z1iIwAiTkUCZYkESpPic+CrGulwP51eUJFsO6SKfo2ldb HZ9WILWnBwUvUEJ2gIYDGbJnuk6WXRZm6jCc2VcIkm3/rSr5Dl4jmbnE3yD2eVkVqQeP FIRw== X-Gm-Message-State: AOJu0YygYLaSyrVND7qiWo2d9rC0le9kInYKyVG3fVMxTZBuzUPpdq1T pa/VIC6ynqh/gtRKX0J0V1TpFrWT6YWfRPe6BiU= X-Google-Smtp-Source: AGHT+IGxVeDOACbxEqDjClh/WuibLYGpmClwa/oHQjfpST76CBS/GSc0kn4Wp2mdPFGn0sW6yF3z/g== X-Received: by 2002:a05:6871:687:b0:1ba:caf2:acc3 with SMTP id l7-20020a056871068700b001bacaf2acc3mr6488145oao.5.1694900501758; Sat, 16 Sep 2023 14:41:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 16/39] accel/tcg: Modify tlb_*() to use CPUState Date: Sat, 16 Sep 2023 14:41:00 -0700 Message-Id: <20230916214123.525796-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900612769100001 Content-Type: text/plain; charset="utf-8" From: Anton Johansson Changes tlb_*() functions to take CPUState instead of CPUArchState, as they don't require the full CPUArchState. This makes it easier to decouple target-(in)dependent code. Signed-off-by: Anton Johansson Message-Id: <20230912153428.17816-4-anjo@rev.ng> Reviewed-by: Richard Henderson [rth: Use cpu->neg.tlb instead of cpu_tlb()] Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu_ldst.h | 8 +- accel/tcg/cputlb.c | 220 +++++++++++++++++++--------------------- 2 files changed, 108 insertions(+), 120 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index da10ba1433..6061e33ac9 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -361,19 +361,19 @@ static inline uint64_t tlb_addr_write(const CPUTLBEnt= ry *entry) } =20 /* Find the TLB index corresponding to the mmu_idx + address pair. */ -static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx, +static inline uintptr_t tlb_index(CPUState *cpu, uintptr_t mmu_idx, vaddr addr) { - uintptr_t size_mask =3D env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY= _BITS; + uintptr_t size_mask =3D cpu->neg.tlb.f[mmu_idx].mask >> CPU_TLB_ENTRY_= BITS; =20 return (addr >> TARGET_PAGE_BITS) & size_mask; } =20 /* Find the TLB entry corresponding to the mmu_idx + address pair. */ -static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx, +static inline CPUTLBEntry *tlb_entry(CPUState *cpu, uintptr_t mmu_idx, vaddr addr) { - return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)]; + return &cpu->neg.tlb.f[mmu_idx].table[tlb_index(cpu, mmu_idx, addr)]; } =20 #endif /* defined(CONFIG_USER_ONLY) */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f790be5b6e..f88c394594 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -240,11 +240,11 @@ static void tlb_mmu_flush_locked(CPUTLBDesc *desc, CP= UTLBDescFast *fast) memset(desc->vtable, -1, sizeof(desc->vtable)); } =20 -static void tlb_flush_one_mmuidx_locked(CPUArchState *env, int mmu_idx, +static void tlb_flush_one_mmuidx_locked(CPUState *cpu, int mmu_idx, int64_t now) { - CPUTLBDesc *desc =3D &env_tlb(env)->d[mmu_idx]; - CPUTLBDescFast *fast =3D &env_tlb(env)->f[mmu_idx]; + CPUTLBDesc *desc =3D &cpu->neg.tlb.d[mmu_idx]; + CPUTLBDescFast *fast =3D &cpu->neg.tlb.f[mmu_idx]; =20 tlb_mmu_resize_locked(desc, fast, now); tlb_mmu_flush_locked(desc, fast); @@ -262,41 +262,39 @@ static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDesc= Fast *fast, int64_t now) tlb_mmu_flush_locked(desc, fast); } =20 -static inline void tlb_n_used_entries_inc(CPUArchState *env, uintptr_t mmu= _idx) +static inline void tlb_n_used_entries_inc(CPUState *cpu, uintptr_t mmu_idx) { - env_tlb(env)->d[mmu_idx].n_used_entries++; + cpu->neg.tlb.d[mmu_idx].n_used_entries++; } =20 -static inline void tlb_n_used_entries_dec(CPUArchState *env, uintptr_t mmu= _idx) +static inline void tlb_n_used_entries_dec(CPUState *cpu, uintptr_t mmu_idx) { - env_tlb(env)->d[mmu_idx].n_used_entries--; + cpu->neg.tlb.d[mmu_idx].n_used_entries--; } =20 void tlb_init(CPUState *cpu) { - CPUArchState *env =3D cpu_env(cpu); int64_t now =3D get_clock_realtime(); int i; =20 - qemu_spin_init(&env_tlb(env)->c.lock); + qemu_spin_init(&cpu->neg.tlb.c.lock); =20 /* All tlbs are initialized flushed. */ - env_tlb(env)->c.dirty =3D 0; + cpu->neg.tlb.c.dirty =3D 0; =20 for (i =3D 0; i < NB_MMU_MODES; i++) { - tlb_mmu_init(&env_tlb(env)->d[i], &env_tlb(env)->f[i], now); + tlb_mmu_init(&cpu->neg.tlb.d[i], &cpu->neg.tlb.f[i], now); } } =20 void tlb_destroy(CPUState *cpu) { - CPUArchState *env =3D cpu_env(cpu); int i; =20 - qemu_spin_destroy(&env_tlb(env)->c.lock); + qemu_spin_destroy(&cpu->neg.tlb.c.lock); for (i =3D 0; i < NB_MMU_MODES; i++) { - CPUTLBDesc *desc =3D &env_tlb(env)->d[i]; - CPUTLBDescFast *fast =3D &env_tlb(env)->f[i]; + CPUTLBDesc *desc =3D &cpu->neg.tlb.d[i]; + CPUTLBDescFast *fast =3D &cpu->neg.tlb.f[i]; =20 g_free(fast->table); g_free(desc->fulltlb); @@ -328,11 +326,9 @@ void tlb_flush_counts(size_t *pfull, size_t *ppart, si= ze_t *pelide) size_t full =3D 0, part =3D 0, elide =3D 0; =20 CPU_FOREACH(cpu) { - CPUArchState *env =3D cpu_env(cpu); - - full +=3D qatomic_read(&env_tlb(env)->c.full_flush_count); - part +=3D qatomic_read(&env_tlb(env)->c.part_flush_count); - elide +=3D qatomic_read(&env_tlb(env)->c.elide_flush_count); + full +=3D qatomic_read(&cpu->neg.tlb.c.full_flush_count); + part +=3D qatomic_read(&cpu->neg.tlb.c.part_flush_count); + elide +=3D qatomic_read(&cpu->neg.tlb.c.elide_flush_count); } *pfull =3D full; *ppart =3D part; @@ -341,7 +337,6 @@ void tlb_flush_counts(size_t *pfull, size_t *ppart, siz= e_t *pelide) =20 static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data = data) { - CPUArchState *env =3D cpu_env(cpu); uint16_t asked =3D data.host_int; uint16_t all_dirty, work, to_clean; int64_t now =3D get_clock_realtime(); @@ -350,32 +345,32 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *= cpu, run_on_cpu_data data) =20 tlb_debug("mmu_idx:0x%04" PRIx16 "\n", asked); =20 - qemu_spin_lock(&env_tlb(env)->c.lock); + qemu_spin_lock(&cpu->neg.tlb.c.lock); =20 - all_dirty =3D env_tlb(env)->c.dirty; + all_dirty =3D cpu->neg.tlb.c.dirty; to_clean =3D asked & all_dirty; all_dirty &=3D ~to_clean; - env_tlb(env)->c.dirty =3D all_dirty; + cpu->neg.tlb.c.dirty =3D all_dirty; =20 for (work =3D to_clean; work !=3D 0; work &=3D work - 1) { int mmu_idx =3D ctz32(work); - tlb_flush_one_mmuidx_locked(env, mmu_idx, now); + tlb_flush_one_mmuidx_locked(cpu, mmu_idx, now); } =20 - qemu_spin_unlock(&env_tlb(env)->c.lock); + qemu_spin_unlock(&cpu->neg.tlb.c.lock); =20 tcg_flush_jmp_cache(cpu); =20 if (to_clean =3D=3D ALL_MMUIDX_BITS) { - qatomic_set(&env_tlb(env)->c.full_flush_count, - env_tlb(env)->c.full_flush_count + 1); + qatomic_set(&cpu->neg.tlb.c.full_flush_count, + cpu->neg.tlb.c.full_flush_count + 1); } else { - qatomic_set(&env_tlb(env)->c.part_flush_count, - env_tlb(env)->c.part_flush_count + ctpop16(to_clean)); + qatomic_set(&cpu->neg.tlb.c.part_flush_count, + cpu->neg.tlb.c.part_flush_count + ctpop16(to_clean)); if (to_clean !=3D asked) { - qatomic_set(&env_tlb(env)->c.elide_flush_count, - env_tlb(env)->c.elide_flush_count + - ctpop16(asked & ~to_clean)); + qatomic_set(&cpu->neg.tlb.c.elide_flush_count, + cpu->neg.tlb.c.elide_flush_count + + ctpop16(asked & ~to_clean)); } } } @@ -470,43 +465,43 @@ static inline bool tlb_flush_entry_locked(CPUTLBEntry= *tlb_entry, vaddr page) } =20 /* Called with tlb_c.lock held */ -static void tlb_flush_vtlb_page_mask_locked(CPUArchState *env, int mmu_idx, +static void tlb_flush_vtlb_page_mask_locked(CPUState *cpu, int mmu_idx, vaddr page, vaddr mask) { - CPUTLBDesc *d =3D &env_tlb(env)->d[mmu_idx]; + CPUTLBDesc *d =3D &cpu->neg.tlb.d[mmu_idx]; int k; =20 - assert_cpu_is_self(env_cpu(env)); + assert_cpu_is_self(cpu); for (k =3D 0; k < CPU_VTLB_SIZE; k++) { if (tlb_flush_entry_mask_locked(&d->vtable[k], page, mask)) { - tlb_n_used_entries_dec(env, mmu_idx); + tlb_n_used_entries_dec(cpu, mmu_idx); } } } =20 -static inline void tlb_flush_vtlb_page_locked(CPUArchState *env, int mmu_i= dx, +static inline void tlb_flush_vtlb_page_locked(CPUState *cpu, int mmu_idx, vaddr page) { - tlb_flush_vtlb_page_mask_locked(env, mmu_idx, page, -1); + tlb_flush_vtlb_page_mask_locked(cpu, mmu_idx, page, -1); } =20 -static void tlb_flush_page_locked(CPUArchState *env, int midx, vaddr page) +static void tlb_flush_page_locked(CPUState *cpu, int midx, vaddr page) { - vaddr lp_addr =3D env_tlb(env)->d[midx].large_page_addr; - vaddr lp_mask =3D env_tlb(env)->d[midx].large_page_mask; + vaddr lp_addr =3D cpu->neg.tlb.d[midx].large_page_addr; + vaddr lp_mask =3D cpu->neg.tlb.d[midx].large_page_mask; =20 /* Check if we need to flush due to large pages. */ if ((page & lp_mask) =3D=3D lp_addr) { tlb_debug("forcing full flush midx %d (%016" VADDR_PRIx "/%016" VADDR_PRIx ")\n", midx, lp_addr, lp_mask); - tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime()); + tlb_flush_one_mmuidx_locked(cpu, midx, get_clock_realtime()); } else { - if (tlb_flush_entry_locked(tlb_entry(env, midx, page), page)) { - tlb_n_used_entries_dec(env, midx); + if (tlb_flush_entry_locked(tlb_entry(cpu, midx, page), page)) { + tlb_n_used_entries_dec(cpu, midx); } - tlb_flush_vtlb_page_locked(env, midx, page); + tlb_flush_vtlb_page_locked(cpu, midx, page); } } =20 @@ -523,20 +518,19 @@ static void tlb_flush_page_by_mmuidx_async_0(CPUState= *cpu, vaddr addr, uint16_t idxmap) { - CPUArchState *env =3D cpu_env(cpu); int mmu_idx; =20 assert_cpu_is_self(cpu); =20 tlb_debug("page addr: %016" VADDR_PRIx " mmu_map:0x%x\n", addr, idxmap= ); =20 - qemu_spin_lock(&env_tlb(env)->c.lock); + qemu_spin_lock(&cpu->neg.tlb.c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { if ((idxmap >> mmu_idx) & 1) { - tlb_flush_page_locked(env, mmu_idx, addr); + tlb_flush_page_locked(cpu, mmu_idx, addr); } } - qemu_spin_unlock(&env_tlb(env)->c.lock); + qemu_spin_unlock(&cpu->neg.tlb.c.lock); =20 /* * Discard jump cache entries for any tb which might potentially @@ -709,12 +703,12 @@ void tlb_flush_page_all_cpus_synced(CPUState *src, va= ddr addr) tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS); } =20 -static void tlb_flush_range_locked(CPUArchState *env, int midx, +static void tlb_flush_range_locked(CPUState *cpu, int midx, vaddr addr, vaddr len, unsigned bits) { - CPUTLBDesc *d =3D &env_tlb(env)->d[midx]; - CPUTLBDescFast *f =3D &env_tlb(env)->f[midx]; + CPUTLBDesc *d =3D &cpu->neg.tlb.d[midx]; + CPUTLBDescFast *f =3D &cpu->neg.tlb.f[midx]; vaddr mask =3D MAKE_64BIT_MASK(0, bits); =20 /* @@ -731,7 +725,7 @@ static void tlb_flush_range_locked(CPUArchState *env, i= nt midx, tlb_debug("forcing full flush midx %d (" "%016" VADDR_PRIx "/%016" VADDR_PRIx "+%016" VADDR_PRIx = ")\n", midx, addr, mask, len); - tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime()); + tlb_flush_one_mmuidx_locked(cpu, midx, get_clock_realtime()); return; } =20 @@ -744,18 +738,18 @@ static void tlb_flush_range_locked(CPUArchState *env,= int midx, tlb_debug("forcing full flush midx %d (" "%016" VADDR_PRIx "/%016" VADDR_PRIx ")\n", midx, d->large_page_addr, d->large_page_mask); - tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime()); + tlb_flush_one_mmuidx_locked(cpu, midx, get_clock_realtime()); return; } =20 for (vaddr i =3D 0; i < len; i +=3D TARGET_PAGE_SIZE) { vaddr page =3D addr + i; - CPUTLBEntry *entry =3D tlb_entry(env, midx, page); + CPUTLBEntry *entry =3D tlb_entry(cpu, midx, page); =20 if (tlb_flush_entry_mask_locked(entry, page, mask)) { - tlb_n_used_entries_dec(env, midx); + tlb_n_used_entries_dec(cpu, midx); } - tlb_flush_vtlb_page_mask_locked(env, midx, page, mask); + tlb_flush_vtlb_page_mask_locked(cpu, midx, page, mask); } } =20 @@ -769,7 +763,6 @@ typedef struct { static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu, TLBFlushRangeData d) { - CPUArchState *env =3D cpu_env(cpu); int mmu_idx; =20 assert_cpu_is_self(cpu); @@ -777,13 +770,13 @@ static void tlb_flush_range_by_mmuidx_async_0(CPUStat= e *cpu, tlb_debug("range: %016" VADDR_PRIx "/%u+%016" VADDR_PRIx " mmu_map:0x%= x\n", d.addr, d.bits, d.len, d.idxmap); =20 - qemu_spin_lock(&env_tlb(env)->c.lock); + qemu_spin_lock(&cpu->neg.tlb.c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { if ((d.idxmap >> mmu_idx) & 1) { - tlb_flush_range_locked(env, mmu_idx, d.addr, d.len, d.bits); + tlb_flush_range_locked(cpu, mmu_idx, d.addr, d.len, d.bits); } } - qemu_spin_unlock(&env_tlb(env)->c.lock); + qemu_spin_unlock(&cpu->neg.tlb.c.lock); =20 /* * If the length is larger than the jump cache size, then it will take @@ -1028,27 +1021,24 @@ static inline void copy_tlb_helper_locked(CPUTLBEnt= ry *d, const CPUTLBEntry *s) */ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) { - CPUArchState *env; - int mmu_idx; =20 - env =3D cpu_env(cpu); - qemu_spin_lock(&env_tlb(env)->c.lock); + qemu_spin_lock(&cpu->neg.tlb.c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; - unsigned int n =3D tlb_n_entries(&env_tlb(env)->f[mmu_idx]); + unsigned int n =3D tlb_n_entries(&cpu->neg.tlb.f[mmu_idx]); =20 for (i =3D 0; i < n; i++) { - tlb_reset_dirty_range_locked(&env_tlb(env)->f[mmu_idx].table[i= ], + tlb_reset_dirty_range_locked(&cpu->neg.tlb.f[mmu_idx].table[i], start1, length); } =20 for (i =3D 0; i < CPU_VTLB_SIZE; i++) { - tlb_reset_dirty_range_locked(&env_tlb(env)->d[mmu_idx].vtable[= i], + tlb_reset_dirty_range_locked(&cpu->neg.tlb.d[mmu_idx].vtable[i= ], start1, length); } } - qemu_spin_unlock(&env_tlb(env)->c.lock); + qemu_spin_unlock(&cpu->neg.tlb.c.lock); } =20 /* Called with tlb_c.lock held */ @@ -1064,32 +1054,31 @@ static inline void tlb_set_dirty1_locked(CPUTLBEntr= y *tlb_entry, so that it is no longer dirty */ void tlb_set_dirty(CPUState *cpu, vaddr addr) { - CPUArchState *env =3D cpu_env(cpu); int mmu_idx; =20 assert_cpu_is_self(cpu); =20 addr &=3D TARGET_PAGE_MASK; - qemu_spin_lock(&env_tlb(env)->c.lock); + qemu_spin_lock(&cpu->neg.tlb.c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { - tlb_set_dirty1_locked(tlb_entry(env, mmu_idx, addr), addr); + tlb_set_dirty1_locked(tlb_entry(cpu, mmu_idx, addr), addr); } =20 for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { int k; for (k =3D 0; k < CPU_VTLB_SIZE; k++) { - tlb_set_dirty1_locked(&env_tlb(env)->d[mmu_idx].vtable[k], add= r); + tlb_set_dirty1_locked(&cpu->neg.tlb.d[mmu_idx].vtable[k], addr= ); } } - qemu_spin_unlock(&env_tlb(env)->c.lock); + qemu_spin_unlock(&cpu->neg.tlb.c.lock); } =20 /* Our TLB does not support large pages, so remember the area covered by large pages and trigger a full TLB flush if these are invalidated. */ -static void tlb_add_large_page(CPUArchState *env, int mmu_idx, +static void tlb_add_large_page(CPUState *cpu, int mmu_idx, vaddr addr, uint64_t size) { - vaddr lp_addr =3D env_tlb(env)->d[mmu_idx].large_page_addr; + vaddr lp_addr =3D cpu->neg.tlb.d[mmu_idx].large_page_addr; vaddr lp_mask =3D ~(size - 1); =20 if (lp_addr =3D=3D (vaddr)-1) { @@ -1099,13 +1088,13 @@ static void tlb_add_large_page(CPUArchState *env, i= nt mmu_idx, /* Extend the existing region to include the new page. This is a compromise between unnecessary flushes and the cost of maintaining a full variable size TLB. */ - lp_mask &=3D env_tlb(env)->d[mmu_idx].large_page_mask; + lp_mask &=3D cpu->neg.tlb.d[mmu_idx].large_page_mask; while (((lp_addr ^ addr) & lp_mask) !=3D 0) { lp_mask <<=3D 1; } } - env_tlb(env)->d[mmu_idx].large_page_addr =3D lp_addr & lp_mask; - env_tlb(env)->d[mmu_idx].large_page_mask =3D lp_mask; + cpu->neg.tlb.d[mmu_idx].large_page_addr =3D lp_addr & lp_mask; + cpu->neg.tlb.d[mmu_idx].large_page_mask =3D lp_mask; } =20 static inline void tlb_set_compare(CPUTLBEntryFull *full, CPUTLBEntry *ent, @@ -1137,8 +1126,7 @@ static inline void tlb_set_compare(CPUTLBEntryFull *f= ull, CPUTLBEntry *ent, void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, CPUTLBEntryFull *full) { - CPUArchState *env =3D cpu_env(cpu); - CPUTLB *tlb =3D env_tlb(env); + CPUTLB *tlb =3D &cpu->neg.tlb; CPUTLBDesc *desc =3D &tlb->d[mmu_idx]; MemoryRegionSection *section; unsigned int index, read_flags, write_flags; @@ -1155,7 +1143,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, sz =3D TARGET_PAGE_SIZE; } else { sz =3D (hwaddr)1 << full->lg_page_size; - tlb_add_large_page(env, mmu_idx, addr, sz); + tlb_add_large_page(cpu, mmu_idx, addr, sz); } addr_page =3D addr & TARGET_PAGE_MASK; paddr_page =3D full->phys_addr & TARGET_PAGE_MASK; @@ -1222,8 +1210,8 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, wp_flags =3D cpu_watchpoint_address_matches(cpu, addr_page, TARGET_PAGE_SIZE); =20 - index =3D tlb_index(env, mmu_idx, addr_page); - te =3D tlb_entry(env, mmu_idx, addr_page); + index =3D tlb_index(cpu, mmu_idx, addr_page); + te =3D tlb_entry(cpu, mmu_idx, addr_page); =20 /* * Hold the TLB lock for the rest of the function. We could acquire/re= lease @@ -1238,7 +1226,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, tlb->c.dirty |=3D 1 << mmu_idx; =20 /* Make sure there's no cached translation for the new page. */ - tlb_flush_vtlb_page_locked(env, mmu_idx, addr_page); + tlb_flush_vtlb_page_locked(cpu, mmu_idx, addr_page); =20 /* * Only evict the old entry to the victim tlb if it's for a @@ -1251,7 +1239,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, /* Evict the old entry into the victim tlb. */ copy_tlb_helper_locked(tv, te); desc->vfulltlb[vidx] =3D desc->fulltlb[index]; - tlb_n_used_entries_dec(env, mmu_idx); + tlb_n_used_entries_dec(cpu, mmu_idx); } =20 /* refill the tlb */ @@ -1296,7 +1284,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, MMU_DATA_STORE, prot & PAGE_WRITE); =20 copy_tlb_helper_locked(te, &tn); - tlb_n_used_entries_inc(env, mmu_idx); + tlb_n_used_entries_inc(cpu, mmu_idx); qemu_spin_unlock(&tlb->c.lock); } =20 @@ -1390,28 +1378,28 @@ static void io_failed(CPUArchState *env, CPUTLBEntr= yFull *full, vaddr addr, =20 /* Return true if ADDR is present in the victim tlb, and has been copied back to the main tlb. */ -static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, +static bool victim_tlb_hit(CPUState *cpu, size_t mmu_idx, size_t index, MMUAccessType access_type, vaddr page) { size_t vidx; =20 - assert_cpu_is_self(env_cpu(env)); + assert_cpu_is_self(cpu); for (vidx =3D 0; vidx < CPU_VTLB_SIZE; ++vidx) { - CPUTLBEntry *vtlb =3D &env_tlb(env)->d[mmu_idx].vtable[vidx]; + CPUTLBEntry *vtlb =3D &cpu->neg.tlb.d[mmu_idx].vtable[vidx]; uint64_t cmp =3D tlb_read_idx(vtlb, access_type); =20 if (cmp =3D=3D page) { /* Found entry in victim tlb, swap tlb and iotlb. */ - CPUTLBEntry tmptlb, *tlb =3D &env_tlb(env)->f[mmu_idx].table[i= ndex]; + CPUTLBEntry tmptlb, *tlb =3D &cpu->neg.tlb.f[mmu_idx].table[in= dex]; =20 - qemu_spin_lock(&env_tlb(env)->c.lock); + qemu_spin_lock(&cpu->neg.tlb.c.lock); copy_tlb_helper_locked(&tmptlb, tlb); copy_tlb_helper_locked(tlb, vtlb); copy_tlb_helper_locked(vtlb, &tmptlb); - qemu_spin_unlock(&env_tlb(env)->c.lock); + qemu_spin_unlock(&cpu->neg.tlb.c.lock); =20 - CPUTLBEntryFull *f1 =3D &env_tlb(env)->d[mmu_idx].fulltlb[inde= x]; - CPUTLBEntryFull *f2 =3D &env_tlb(env)->d[mmu_idx].vfulltlb[vid= x]; + CPUTLBEntryFull *f1 =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index= ]; + CPUTLBEntryFull *f2 =3D &cpu->neg.tlb.d[mmu_idx].vfulltlb[vidx= ]; CPUTLBEntryFull tmpf; tmpf =3D *f1; *f1 =3D *f2; *f2 =3D tmpf; return true; @@ -1450,8 +1438,8 @@ static int probe_access_internal(CPUArchState *env, v= addr addr, void **phost, CPUTLBEntryFull **pfull, uintptr_t retaddr, bool check_mem_cbs) { - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + uintptr_t index =3D tlb_index(env_cpu(env), mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(env_cpu(env), mmu_idx, addr); uint64_t tlb_addr =3D tlb_read_idx(entry, access_type); vaddr page_addr =3D addr & TARGET_PAGE_MASK; int flags =3D TLB_FLAGS_MASK & ~TLB_FORCE_SLOW; @@ -1459,7 +1447,8 @@ static int probe_access_internal(CPUArchState *env, v= addr addr, CPUTLBEntryFull *full; =20 if (!tlb_hit_page(tlb_addr, page_addr)) { - if (!victim_tlb_hit(env, mmu_idx, index, access_type, page_addr)) { + if (!victim_tlb_hit(env_cpu(env), mmu_idx, index, + access_type, page_addr)) { CPUState *cs =3D env_cpu(env); =20 if (!cs->cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_ty= pe, @@ -1471,8 +1460,8 @@ static int probe_access_internal(CPUArchState *env, v= addr addr, } =20 /* TLB resize via tlb_fill may have moved the entry. */ - index =3D tlb_index(env, mmu_idx, addr); - entry =3D tlb_entry(env, mmu_idx, addr); + index =3D tlb_index(env_cpu(env), mmu_idx, addr); + entry =3D tlb_entry(env_cpu(env), mmu_idx, addr); =20 /* * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately, @@ -1662,9 +1651,8 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState = *env, vaddr addr, bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, int mmu_idx, bool is_store, struct qemu_plugin_hwaddr *data) { - CPUArchState *env =3D cpu_env(cpu); - CPUTLBEntry *tlbe =3D tlb_entry(env, mmu_idx, addr); - uintptr_t index =3D tlb_index(env, mmu_idx, addr); + CPUTLBEntry *tlbe =3D tlb_entry(cpu, mmu_idx, addr); + uintptr_t index =3D tlb_index(cpu, mmu_idx, addr); MMUAccessType access_type =3D is_store ? MMU_DATA_STORE : MMU_DATA_LOA= D; uint64_t tlb_addr =3D tlb_read_idx(tlbe, access_type); CPUTLBEntryFull *full; @@ -1673,7 +1661,7 @@ bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, int= mmu_idx, return false; } =20 - full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; data->phys_addr =3D full->phys_addr | (addr & ~TARGET_PAGE_MASK); =20 /* We must have an iotlb entry for MMIO */ @@ -1727,8 +1715,8 @@ static bool mmu_lookup1(CPUArchState *env, MMULookupP= ageData *data, int mmu_idx, MMUAccessType access_type, uintptr_t = ra) { vaddr addr =3D data->addr; - uintptr_t index =3D tlb_index(env, mmu_idx, addr); - CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); + uintptr_t index =3D tlb_index(env_cpu(env), mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(env_cpu(env), mmu_idx, addr); uint64_t tlb_addr =3D tlb_read_idx(entry, access_type); bool maybe_resized =3D false; CPUTLBEntryFull *full; @@ -1736,12 +1724,12 @@ static bool mmu_lookup1(CPUArchState *env, MMULooku= pPageData *data, =20 /* If the TLB entry is for a different page, reload and try again. */ if (!tlb_hit(tlb_addr, addr)) { - if (!victim_tlb_hit(env, mmu_idx, index, access_type, + if (!victim_tlb_hit(env_cpu(env), mmu_idx, index, access_type, addr & TARGET_PAGE_MASK)) { tlb_fill(env_cpu(env), addr, data->size, access_type, mmu_idx,= ra); maybe_resized =3D true; - index =3D tlb_index(env, mmu_idx, addr); - entry =3D tlb_entry(env, mmu_idx, addr); + index =3D tlb_index(env_cpu(env), mmu_idx, addr); + entry =3D tlb_entry(env_cpu(env), mmu_idx, addr); } tlb_addr =3D tlb_read_idx(entry, access_type) & ~TLB_INVALID_MASK; } @@ -1849,7 +1837,7 @@ static bool mmu_lookup(CPUArchState *env, vaddr addr,= MemOpIdx oi, */ mmu_lookup1(env, &l->page[0], l->mmu_idx, type, ra); if (mmu_lookup1(env, &l->page[1], l->mmu_idx, type, ra)) { - uintptr_t index =3D tlb_index(env, l->mmu_idx, addr); + uintptr_t index =3D tlb_index(env_cpu(env), l->mmu_idx, addr); l->page[0].full =3D &env_tlb(env)->d[l->mmu_idx].fulltlb[index= ]; } =20 @@ -1907,18 +1895,18 @@ static void *atomic_mmu_lookup(CPUArchState *env, v= addr addr, MemOpIdx oi, goto stop_the_world; } =20 - index =3D tlb_index(env, mmu_idx, addr); - tlbe =3D tlb_entry(env, mmu_idx, addr); + index =3D tlb_index(env_cpu(env), mmu_idx, addr); + tlbe =3D tlb_entry(env_cpu(env), mmu_idx, addr); =20 /* Check TLB entry and enforce page permissions. */ tlb_addr =3D tlb_addr_write(tlbe); if (!tlb_hit(tlb_addr, addr)) { - if (!victim_tlb_hit(env, mmu_idx, index, MMU_DATA_STORE, + if (!victim_tlb_hit(env_cpu(env), mmu_idx, index, MMU_DATA_STORE, addr & TARGET_PAGE_MASK)) { tlb_fill(env_cpu(env), addr, size, MMU_DATA_STORE, mmu_idx, retaddr); - index =3D tlb_index(env, mmu_idx, addr); - tlbe =3D tlb_entry(env, mmu_idx, addr); + index =3D tlb_index(env_cpu(env), mmu_idx, addr); + tlbe =3D tlb_entry(env_cpu(env), mmu_idx, addr); } tlb_addr =3D tlb_addr_write(tlbe) & ~TLB_INVALID_MASK; } --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900690; cv=none; d=zohomail.com; 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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900502; x=1695505302; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TVqkrTpBkS08OOtc33GfGLABbq/z0dDCKK+SIF9n4BI=; b=xBhSxwBFxtMVxXpESsrhr4sY7V/isHrdnVzr/wuhWM4Ftg9pGipAi4QBNh3Gu/y1pD hY6NAugzDYBEiiozKUKUJob+ZoORPkO7zCQaxwxu85XsGub1zBfQviYDBynECf7AVLhi fynuc4ODWs6iYhN8U6BV6ZJbuIEdZX2hXepE5RgpCWTfLvxeyem0Uxpp6h7lrOvXT9WM Ue0Y1rMjFBnWY4U5jccXer3BYS0gEZi14Gtjir88bz6liuwOA8PuW8kEeelae5/0QS1/ 4n1ChtIehRncTLWOkdTLu+GtKKk1veTzvKK1Znt/g2y5o7K6rGvvLqAQAJI66TwyNMT9 Jzrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900502; x=1695505302; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TVqkrTpBkS08OOtc33GfGLABbq/z0dDCKK+SIF9n4BI=; b=bCL5CJbaS31YTzvYcTuxI9Hp8Msh9KKDqca13BE0PnGwvPS3QiTI/iJWRngiGV2cd7 ryaQr1equLBP/LCbweInudDWbTp1pQhuKPyPOrcS97AiHDrt5/Y/sMaln9y+56aY2C2m DKRcly2yHzOyn5RvX2A2BRymcaM5cC1onC5scOSaZXEgpjNFtRUCpFsZTyRV5JkZ75L5 ZkkvYjZj1u5zFGOk97V1xJqVu62SCmWi9coKY3SId4AVcI0BWr1NfW/utjyzvJvs678M AEegRAS0QnullGtyrwUqRFgz/Jss61p9XCeWVbjktJOWtR3Xaa5X6RSl5EMD2Qp6Xrjl rx5Q== X-Gm-Message-State: AOJu0YygJTGpzDI2zet9p4F7lbCfT6hQ/YdOY4jAacpXBQNWFFF4Ovox 8J5N88fpnOxOx3SRQU/lz6fpuQ+G66VTGQl2sD0= X-Google-Smtp-Source: AGHT+IHanDw+X59OTMvGbSm548V7cHPuQ2nar0uTOAzAUC/wAYOMJieVpkafANx29dQt6jSMj6H3wA== X-Received: by 2002:a05:6a00:1250:b0:68c:69c8:e0f0 with SMTP id u16-20020a056a00125000b0068c69c8e0f0mr6434709pfi.18.1694900502660; Sat, 16 Sep 2023 14:41:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 17/39] accel/tcg: Modify probe_access_internal() to use CPUState Date: Sat, 16 Sep 2023 14:41:01 -0700 Message-Id: <20230916214123.525796-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900690894100001 From: Anton Johansson probe_access_internal() is changed to instead take the generic CPUState over CPUArchState, in order to lessen the target-specific coupling of cputlb.c. Note: probe_access*() also don't need the full CPUArchState, but aren't touched in this patch as they are target-facing. Signed-off-by: Anton Johansson Message-Id: <20230912153428.17816-5-anjo@rev.ng> Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 [rth: Use cpu->neg.tlb instead of cpu_tlb()] Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 46 +++++++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f88c394594..ab52afb3f3 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1432,27 +1432,24 @@ static void notdirty_write(CPUState *cpu, vaddr mem= _vaddr, unsigned size, } } =20 -static int probe_access_internal(CPUArchState *env, vaddr addr, +static int probe_access_internal(CPUState *cpu, vaddr addr, int fault_size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, CPUTLBEntryFull **pfull, uintptr_t retaddr, bool check_mem_cbs) { - uintptr_t index =3D tlb_index(env_cpu(env), mmu_idx, addr); - CPUTLBEntry *entry =3D tlb_entry(env_cpu(env), mmu_idx, addr); + uintptr_t index =3D tlb_index(cpu, mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(cpu, mmu_idx, addr); uint64_t tlb_addr =3D tlb_read_idx(entry, access_type); vaddr page_addr =3D addr & TARGET_PAGE_MASK; int flags =3D TLB_FLAGS_MASK & ~TLB_FORCE_SLOW; - bool force_mmio =3D check_mem_cbs && cpu_plugin_mem_cbs_enabled(env_cp= u(env)); + bool force_mmio =3D check_mem_cbs && cpu_plugin_mem_cbs_enabled(cpu); CPUTLBEntryFull *full; =20 if (!tlb_hit_page(tlb_addr, page_addr)) { - if (!victim_tlb_hit(env_cpu(env), mmu_idx, index, - access_type, page_addr)) { - CPUState *cs =3D env_cpu(env); - - if (!cs->cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_ty= pe, - mmu_idx, nonfault, retaddr)) { + if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, page_addr)) { + if (!cpu->cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_= type, + mmu_idx, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost =3D NULL; *pfull =3D NULL; @@ -1460,8 +1457,8 @@ static int probe_access_internal(CPUArchState *env, v= addr addr, } =20 /* TLB resize via tlb_fill may have moved the entry. */ - index =3D tlb_index(env_cpu(env), mmu_idx, addr); - entry =3D tlb_entry(env_cpu(env), mmu_idx, addr); + index =3D tlb_index(cpu, mmu_idx, addr); + entry =3D tlb_entry(cpu, mmu_idx, addr); =20 /* * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately, @@ -1474,7 +1471,7 @@ static int probe_access_internal(CPUArchState *env, v= addr addr, } flags &=3D tlb_addr; =20 - *pfull =3D full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + *pfull =3D full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; flags |=3D full->slow_flags[access_type]; =20 /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ @@ -1495,8 +1492,9 @@ int probe_access_full(CPUArchState *env, vaddr addr, = int size, bool nonfault, void **phost, CPUTLBEntryFull **pfull, uintptr_t retaddr) { - int flags =3D probe_access_internal(env, addr, size, access_type, mmu_= idx, - nonfault, phost, pfull, retaddr, tru= e); + int flags =3D probe_access_internal(env_cpu(env), addr, size, access_t= ype, + mmu_idx, nonfault, phost, pfull, ret= addr, + true); =20 /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { @@ -1518,8 +1516,8 @@ int probe_access_full_mmu(CPUArchState *env, vaddr ad= dr, int size, phost =3D phost ? phost : &discard_phost; pfull =3D pfull ? pfull : &discard_tlb; =20 - int flags =3D probe_access_internal(env, addr, size, access_type, mmu_= idx, - true, phost, pfull, 0, false); + int flags =3D probe_access_internal(env_cpu(env), addr, size, access_t= ype, + mmu_idx, true, phost, pfull, 0, fals= e); =20 /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { @@ -1539,8 +1537,9 @@ int probe_access_flags(CPUArchState *env, vaddr addr,= int size, =20 g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); =20 - flags =3D probe_access_internal(env, addr, size, access_type, mmu_idx, - nonfault, phost, &full, retaddr, true); + flags =3D probe_access_internal(env_cpu(env), addr, size, access_type, + mmu_idx, nonfault, phost, &full, retaddr, + true); =20 /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { @@ -1560,8 +1559,9 @@ void *probe_access(CPUArchState *env, vaddr addr, int= size, =20 g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); =20 - flags =3D probe_access_internal(env, addr, size, access_type, mmu_idx, - false, &host, &full, retaddr, true); + flags =3D probe_access_internal(env_cpu(env), addr, size, access_type, + mmu_idx, false, &host, &full, retaddr, + true); =20 /* Per the interface, size =3D=3D 0 merely faults the access. */ if (size =3D=3D 0) { @@ -1593,7 +1593,7 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr ad= dr, void *host; int flags; =20 - flags =3D probe_access_internal(env, addr, 0, access_type, + flags =3D probe_access_internal(env_cpu(env), addr, 0, access_type, mmu_idx, true, &host, &full, 0, false); =20 /* No combination of flags are expected by the caller. */ @@ -1616,7 +1616,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState = *env, vaddr addr, CPUTLBEntryFull *full; void *p; =20 - (void)probe_access_internal(env, addr, 1, MMU_INST_FETCH, + (void)probe_access_internal(env_cpu(env), addr, 1, MMU_INST_FETCH, cpu_mmu_index(env, true), false, &p, &full, 0, false); if (p =3D=3D NULL) { --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900624; cv=none; d=zohomail.com; s=zohoarc; b=nKC+P8l9I6/rvo69nTnlwK5fHmxx7wQ7ulICJSy1WJ/A1KI7lsMBjsdlGqsmuaj0+j0dzeZej3qVr/nQTFwkiDdExLDqHcVbKvQ+q4JTJVT21okM9reKnsf13RS68BerdgMTZaxGZtu1nwW4iStHCCYFMPlMCXBXeMuEye4+p9s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900624; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+MOXHAYWRt1NBMGx/8qJG158g8ws8XFH4dqMDtNCnIk=; b=L3Z0m11bPj8oqojtNKPPA6VbDSTE0Ufpqto8kTus1GJ3fgVy9olnhlEhXg+WxoDGlpZGImPIvIsNlTq/1ibk8sM1wqKU5dFtR0QVMcf94I86rTW9vuIybXK27IkpYtG7+VZ9VaMboxL0Ui8Qg07SCcX+PmEd7MmeLhNn1fmIBss= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900624641586.88236771077; Sat, 16 Sep 2023 14:43:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd3G-0005Ew-5y; Sat, 16 Sep 2023 17:42:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd30-0005Bu-Qj for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:51 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd2v-0000Ss-6f for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:50 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-68fb79ef55eso3072283b3a.0 for ; Sat, 16 Sep 2023 14:41:44 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900503; x=1695505303; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+MOXHAYWRt1NBMGx/8qJG158g8ws8XFH4dqMDtNCnIk=; b=YbIb2cL89mwCNLh2gQiphaTbVoeZaOt/zlA+SzAU33WbDGOzF6QIlFGOesgOjF4E5g SbmOWxpfyT4GYgY8XHrP8mbAqRDpQmP/uNZ0AOjxZCvbvl04TNnuOiLGXcKWjG7laUpT K78GusNeCtDa3Nkn09mFvrbRKzv62Ju+dTT29HYhsg3a4BFv6hu8eSoQpqS4LtUGoNpS gqykfiCPILFZj1zIKB6oWjOVd6dByTxH92byocHrHAp9MY6J5lRdW6cyENC4OvxMBVpS JsGb4+ORa6HQvt1sS2iebBk6JQHNLqPD2/3J7J8LNRXuyeFatSOlX44jkpQRDtMhMgwL AxaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900503; x=1695505303; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+MOXHAYWRt1NBMGx/8qJG158g8ws8XFH4dqMDtNCnIk=; b=gReh2XGImv1yF3G0QHSP06WgmuDOn/7Dzl6513/zk26HjqvUdRz+zEpuIiaGQk7ZNU G2EgFmUw1swNoaGKKgC4bKeqxS43VsHskx89lEuTJSSaHBZaKP2PeRSsQatie3lpoGAe +ITOivgds6CVkwqJGwDLc6UwVEOEaDGFjqK0IvXOOZnHGft4J8NEkARAohuzJXH0bcL1 b7N9+8eYulxJMsKNbmHs0fwNWqQZkMKOIaNO9YimhEWqcee1bYtKFb7YimsP/pd6qYXl BRLsISeY92qw1ZdfXMul9d/CHf2aLfbp/0hIQTqCX6wxJpvmKpLtYT/bKkkI6lLBOb73 ptzQ== X-Gm-Message-State: AOJu0Ywwqt6984twId4rlqTAsBxDNARb19IBOMvNj76p+yzDzNagLdBC jDXywYsDeLtbCNsy2dbxG5Fr2vFCl0Hly4ojX/U= X-Google-Smtp-Source: AGHT+IEZ6jF2AyQXlyE13H5t/ilkoaxuAcGDRLc10wIOjbsl42Mruys9ubzI9Il2fWl6QremqSM12g== X-Received: by 2002:a05:6a00:1490:b0:690:454a:dc7b with SMTP id v16-20020a056a00149000b00690454adc7bmr6778917pfu.28.1694900503488; Sat, 16 Sep 2023 14:41:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 18/39] accel/tcg: Modify memory access functions to use CPUState Date: Sat, 16 Sep 2023 14:41:02 -0700 Message-Id: <20230916214123.525796-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900625663100007 From: Anton Johansson do_[ld|st]*() and mmu_lookup*() are changed to use CPUState over CPUArchState, moving the target-dependence to the target-facing facing cpu_[ld|st] functions. Signed-off-by: Anton Johansson Message-Id: <20230912153428.17816-6-anjo@rev.ng> Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 [rth: Use cpu->neg.tlb instead of cpu_tlb; cpu_env instead of env_ptr.] Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 348 ++++++++++++++++++++++----------------------- 1 file changed, 171 insertions(+), 177 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ab52afb3f3..0e4bc82294 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1339,10 +1339,9 @@ static inline void cpu_unaligned_access(CPUState *cp= u, vaddr addr, } =20 static MemoryRegionSection * -io_prepare(hwaddr *out_offset, CPUArchState *env, hwaddr xlat, +io_prepare(hwaddr *out_offset, CPUState *cpu, hwaddr xlat, MemTxAttrs attrs, vaddr addr, uintptr_t retaddr) { - CPUState *cpu =3D env_cpu(env); MemoryRegionSection *section; hwaddr mr_offset; =20 @@ -1357,22 +1356,17 @@ io_prepare(hwaddr *out_offset, CPUArchState *env, h= waddr xlat, return section; } =20 -static void io_failed(CPUArchState *env, CPUTLBEntryFull *full, vaddr addr, +static void io_failed(CPUState *cpu, CPUTLBEntryFull *full, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_id= x, MemTxResult response, uintptr_t retaddr) { - CPUState *cpu =3D env_cpu(env); + if (!cpu->ignore_memory_transaction_failures + && cpu->cc->tcg_ops->do_transaction_failed) { + hwaddr physaddr =3D full->phys_addr | (addr & ~TARGET_PAGE_MASK); =20 - if (!cpu->ignore_memory_transaction_failures) { - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - if (cc->tcg_ops->do_transaction_failed) { - hwaddr physaddr =3D full->phys_addr | (addr & ~TARGET_PAGE_MAS= K); - - cc->tcg_ops->do_transaction_failed(cpu, physaddr, addr, size, - access_type, mmu_idx, - full->attrs, response, reta= ddr); - } + cpu->cc->tcg_ops->do_transaction_failed(cpu, physaddr, addr, size, + access_type, mmu_idx, + full->attrs, response, ret= addr); } } =20 @@ -1700,7 +1694,7 @@ typedef struct MMULookupLocals { =20 /** * mmu_lookup1: translate one page - * @env: cpu context + * @cpu: generic cpu state * @data: lookup parameters * @mmu_idx: virtual address context * @access_type: load/store/code @@ -1711,12 +1705,12 @@ typedef struct MMULookupLocals { * tlb_fill will longjmp out. Return true if the softmmu tlb for * @mmu_idx may have resized. */ -static bool mmu_lookup1(CPUArchState *env, MMULookupPageData *data, +static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, int mmu_idx, MMUAccessType access_type, uintptr_t = ra) { vaddr addr =3D data->addr; - uintptr_t index =3D tlb_index(env_cpu(env), mmu_idx, addr); - CPUTLBEntry *entry =3D tlb_entry(env_cpu(env), mmu_idx, addr); + uintptr_t index =3D tlb_index(cpu, mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(cpu, mmu_idx, addr); uint64_t tlb_addr =3D tlb_read_idx(entry, access_type); bool maybe_resized =3D false; CPUTLBEntryFull *full; @@ -1724,17 +1718,17 @@ static bool mmu_lookup1(CPUArchState *env, MMULooku= pPageData *data, =20 /* If the TLB entry is for a different page, reload and try again. */ if (!tlb_hit(tlb_addr, addr)) { - if (!victim_tlb_hit(env_cpu(env), mmu_idx, index, access_type, + if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, addr & TARGET_PAGE_MASK)) { - tlb_fill(env_cpu(env), addr, data->size, access_type, mmu_idx,= ra); + tlb_fill(cpu, addr, data->size, access_type, mmu_idx, ra); maybe_resized =3D true; - index =3D tlb_index(env_cpu(env), mmu_idx, addr); - entry =3D tlb_entry(env_cpu(env), mmu_idx, addr); + index =3D tlb_index(cpu, mmu_idx, addr); + entry =3D tlb_entry(cpu, mmu_idx, addr); } tlb_addr =3D tlb_read_idx(entry, access_type) & ~TLB_INVALID_MASK; } =20 - full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; flags =3D tlb_addr & (TLB_FLAGS_MASK & ~TLB_FORCE_SLOW); flags |=3D full->slow_flags[access_type]; =20 @@ -1748,7 +1742,7 @@ static bool mmu_lookup1(CPUArchState *env, MMULookupP= ageData *data, =20 /** * mmu_watch_or_dirty - * @env: cpu context + * @cpu: generic cpu state * @data: lookup parameters * @access_type: load/store/code * @ra: return address into tcg generated code, or 0 @@ -1756,7 +1750,7 @@ static bool mmu_lookup1(CPUArchState *env, MMULookupP= ageData *data, * Trigger watchpoints for @data.addr:@data.size; * record writes to protected clean pages. */ -static void mmu_watch_or_dirty(CPUArchState *env, MMULookupPageData *data, +static void mmu_watch_or_dirty(CPUState *cpu, MMULookupPageData *data, MMUAccessType access_type, uintptr_t ra) { CPUTLBEntryFull *full =3D data->full; @@ -1767,13 +1761,13 @@ static void mmu_watch_or_dirty(CPUArchState *env, M= MULookupPageData *data, /* On watchpoint hit, this will longjmp out. */ if (flags & TLB_WATCHPOINT) { int wp =3D access_type =3D=3D MMU_DATA_STORE ? BP_MEM_WRITE : BP_M= EM_READ; - cpu_check_watchpoint(env_cpu(env), addr, size, full->attrs, wp, ra= ); + cpu_check_watchpoint(cpu, addr, size, full->attrs, wp, ra); flags &=3D ~TLB_WATCHPOINT; } =20 /* Note that notdirty is only set for writes. */ if (flags & TLB_NOTDIRTY) { - notdirty_write(env_cpu(env), addr, size, full, ra); + notdirty_write(cpu, addr, size, full, ra); flags &=3D ~TLB_NOTDIRTY; } data->flags =3D flags; @@ -1781,7 +1775,7 @@ static void mmu_watch_or_dirty(CPUArchState *env, MMU= LookupPageData *data, =20 /** * mmu_lookup: translate page(s) - * @env: cpu context + * @cpu: generic cpu state * @addr: virtual address * @oi: combined mmu_idx and MemOp * @ra: return address into tcg generated code, or 0 @@ -1791,7 +1785,7 @@ static void mmu_watch_or_dirty(CPUArchState *env, MMU= LookupPageData *data, * Resolve the translation for the page(s) beginning at @addr, for MemOp.s= ize * bytes. Return true if the lookup crosses a page boundary. */ -static bool mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi, +static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType type, MMULookupLocals *= l) { unsigned a_bits; @@ -1806,7 +1800,7 @@ static bool mmu_lookup(CPUArchState *env, vaddr addr,= MemOpIdx oi, /* Handle CPU specific unaligned behaviour */ a_bits =3D get_alignment_bits(l->memop); if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(env_cpu(env), addr, type, l->mmu_idx, ra); + cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); } =20 l->page[0].addr =3D addr; @@ -1816,11 +1810,11 @@ static bool mmu_lookup(CPUArchState *env, vaddr add= r, MemOpIdx oi, crosspage =3D (addr ^ l->page[1].addr) & TARGET_PAGE_MASK; =20 if (likely(!crosspage)) { - mmu_lookup1(env, &l->page[0], l->mmu_idx, type, ra); + mmu_lookup1(cpu, &l->page[0], l->mmu_idx, type, ra); =20 flags =3D l->page[0].flags; if (unlikely(flags & (TLB_WATCHPOINT | TLB_NOTDIRTY))) { - mmu_watch_or_dirty(env, &l->page[0], type, ra); + mmu_watch_or_dirty(cpu, &l->page[0], type, ra); } if (unlikely(flags & TLB_BSWAP)) { l->memop ^=3D MO_BSWAP; @@ -1835,16 +1829,16 @@ static bool mmu_lookup(CPUArchState *env, vaddr add= r, MemOpIdx oi, * Lookup both pages, recognizing exceptions from either. If the * second lookup potentially resized, refresh first CPUTLBEntryFul= l. */ - mmu_lookup1(env, &l->page[0], l->mmu_idx, type, ra); - if (mmu_lookup1(env, &l->page[1], l->mmu_idx, type, ra)) { - uintptr_t index =3D tlb_index(env_cpu(env), l->mmu_idx, addr); - l->page[0].full =3D &env_tlb(env)->d[l->mmu_idx].fulltlb[index= ]; + mmu_lookup1(cpu, &l->page[0], l->mmu_idx, type, ra); + if (mmu_lookup1(cpu, &l->page[1], l->mmu_idx, type, ra)) { + uintptr_t index =3D tlb_index(cpu, l->mmu_idx, addr); + l->page[0].full =3D &cpu->neg.tlb.d[l->mmu_idx].fulltlb[index]; } =20 flags =3D l->page[0].flags | l->page[1].flags; if (unlikely(flags & (TLB_WATCHPOINT | TLB_NOTDIRTY))) { - mmu_watch_or_dirty(env, &l->page[0], type, ra); - mmu_watch_or_dirty(env, &l->page[1], type, ra); + mmu_watch_or_dirty(cpu, &l->page[0], type, ra); + mmu_watch_or_dirty(cpu, &l->page[1], type, ra); } =20 /* @@ -1984,7 +1978,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, vad= dr addr, MemOpIdx oi, =20 /** * do_ld_mmio_beN: - * @env: cpu context + * @cpu: generic cpu state * @full: page parameters * @ret_be: accumulated data * @addr: virtual address @@ -1996,7 +1990,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, vad= dr addr, MemOpIdx oi, * Load @size bytes from @addr, which is memory-mapped i/o. * The bytes are concatenated in big-endian order with @ret_be. */ -static uint64_t int_ld_mmio_beN(CPUArchState *env, CPUTLBEntryFull *full, +static uint64_t int_ld_mmio_beN(CPUState *cpu, CPUTLBEntryFull *full, uint64_t ret_be, vaddr addr, int size, int mmu_idx, MMUAccessType type, uintptr_t= ra, MemoryRegion *mr, hwaddr mr_offset) @@ -2015,7 +2009,7 @@ static uint64_t int_ld_mmio_beN(CPUArchState *env, CP= UTLBEntryFull *full, r =3D memory_region_dispatch_read(mr, mr_offset, &val, this_mop, full->attrs); if (unlikely(r !=3D MEMTX_OK)) { - io_failed(env, full, addr, this_size, type, mmu_idx, r, ra); + io_failed(cpu, full, addr, this_size, type, mmu_idx, r, ra); } if (this_size =3D=3D 8) { return val; @@ -2030,7 +2024,7 @@ static uint64_t int_ld_mmio_beN(CPUArchState *env, CP= UTLBEntryFull *full, return ret_be; } =20 -static uint64_t do_ld_mmio_beN(CPUArchState *env, CPUTLBEntryFull *full, +static uint64_t do_ld_mmio_beN(CPUState *cpu, CPUTLBEntryFull *full, uint64_t ret_be, vaddr addr, int size, int mmu_idx, MMUAccessType type, uintptr_t = ra) { @@ -2043,18 +2037,18 @@ static uint64_t do_ld_mmio_beN(CPUArchState *env, C= PUTLBEntryFull *full, tcg_debug_assert(size > 0 && size <=3D 8); =20 attrs =3D full->attrs; - section =3D io_prepare(&mr_offset, env, full->xlat_section, attrs, add= r, ra); + section =3D io_prepare(&mr_offset, cpu, full->xlat_section, attrs, add= r, ra); mr =3D section->mr; =20 qemu_mutex_lock_iothread(); - ret =3D int_ld_mmio_beN(env, full, ret_be, addr, size, mmu_idx, + ret =3D int_ld_mmio_beN(cpu, full, ret_be, addr, size, mmu_idx, type, ra, mr, mr_offset); qemu_mutex_unlock_iothread(); =20 return ret; } =20 -static Int128 do_ld16_mmio_beN(CPUArchState *env, CPUTLBEntryFull *full, +static Int128 do_ld16_mmio_beN(CPUState *cpu, CPUTLBEntryFull *full, uint64_t ret_be, vaddr addr, int size, int mmu_idx, uintptr_t ra) { @@ -2067,13 +2061,13 @@ static Int128 do_ld16_mmio_beN(CPUArchState *env, C= PUTLBEntryFull *full, tcg_debug_assert(size > 8 && size <=3D 16); =20 attrs =3D full->attrs; - section =3D io_prepare(&mr_offset, env, full->xlat_section, attrs, add= r, ra); + section =3D io_prepare(&mr_offset, cpu, full->xlat_section, attrs, add= r, ra); mr =3D section->mr; =20 qemu_mutex_lock_iothread(); - a =3D int_ld_mmio_beN(env, full, ret_be, addr, size - 8, mmu_idx, + a =3D int_ld_mmio_beN(cpu, full, ret_be, addr, size - 8, mmu_idx, MMU_DATA_LOAD, ra, mr, mr_offset); - b =3D int_ld_mmio_beN(env, full, ret_be, addr + size - 8, 8, mmu_idx, + b =3D int_ld_mmio_beN(cpu, full, ret_be, addr + size - 8, 8, mmu_idx, MMU_DATA_LOAD, ra, mr, mr_offset + size - 8); qemu_mutex_unlock_iothread(); =20 @@ -2174,11 +2168,11 @@ static uint64_t do_ld_whole_be4(MMULookupPageData *= p, uint64_t ret_be) * As do_ld_bytes_beN, but with one atomic load. * Eight aligned bytes are guaranteed to cover the load. */ -static uint64_t do_ld_whole_be8(CPUArchState *env, uintptr_t ra, +static uint64_t do_ld_whole_be8(CPUState *cpu, uintptr_t ra, MMULookupPageData *p, uint64_t ret_be) { int o =3D p->addr & 7; - uint64_t x =3D load_atomic8_or_exit(env, ra, p->haddr - o); + uint64_t x =3D load_atomic8_or_exit(cpu_env(cpu), ra, p->haddr - o); =20 x =3D cpu_to_be64(x); x <<=3D o * 8; @@ -2194,11 +2188,11 @@ static uint64_t do_ld_whole_be8(CPUArchState *env, = uintptr_t ra, * As do_ld_bytes_beN, but with one atomic load. * 16 aligned bytes are guaranteed to cover the load. */ -static Int128 do_ld_whole_be16(CPUArchState *env, uintptr_t ra, +static Int128 do_ld_whole_be16(CPUState *cpu, uintptr_t ra, MMULookupPageData *p, uint64_t ret_be) { int o =3D p->addr & 15; - Int128 x, y =3D load_atomic16_or_exit(env, ra, p->haddr - o); + Int128 x, y =3D load_atomic16_or_exit(cpu_env(cpu), ra, p->haddr - o); int size =3D p->size; =20 if (!HOST_BIG_ENDIAN) { @@ -2214,7 +2208,7 @@ static Int128 do_ld_whole_be16(CPUArchState *env, uin= tptr_t ra, /* * Wrapper for the above. */ -static uint64_t do_ld_beN(CPUArchState *env, MMULookupPageData *p, +static uint64_t do_ld_beN(CPUState *cpu, MMULookupPageData *p, uint64_t ret_be, int mmu_idx, MMUAccessType type, MemOp mop, uintptr_t ra) { @@ -2222,7 +2216,7 @@ static uint64_t do_ld_beN(CPUArchState *env, MMULooku= pPageData *p, unsigned tmp, half_size; =20 if (unlikely(p->flags & TLB_MMIO)) { - return do_ld_mmio_beN(env, p->full, ret_be, p->addr, p->size, + return do_ld_mmio_beN(cpu, p->full, ret_be, p->addr, p->size, mmu_idx, type, ra); } =20 @@ -2246,7 +2240,7 @@ static uint64_t do_ld_beN(CPUArchState *env, MMULooku= pPageData *p, if (!HAVE_al8_fast && p->size < 4) { return do_ld_whole_be4(p, ret_be); } else { - return do_ld_whole_be8(env, ra, p, ret_be); + return do_ld_whole_be8(cpu, ra, p, ret_be); } } /* fall through */ @@ -2264,7 +2258,7 @@ static uint64_t do_ld_beN(CPUArchState *env, MMULooku= pPageData *p, /* * Wrapper for the above, for 8 < size < 16. */ -static Int128 do_ld16_beN(CPUArchState *env, MMULookupPageData *p, +static Int128 do_ld16_beN(CPUState *cpu, MMULookupPageData *p, uint64_t a, int mmu_idx, MemOp mop, uintptr_t ra) { int size =3D p->size; @@ -2272,7 +2266,7 @@ static Int128 do_ld16_beN(CPUArchState *env, MMULooku= pPageData *p, MemOp atom; =20 if (unlikely(p->flags & TLB_MMIO)) { - return do_ld16_mmio_beN(env, p->full, a, p->addr, size, mmu_idx, r= a); + return do_ld16_mmio_beN(cpu, p->full, a, p->addr, size, mmu_idx, r= a); } =20 /* @@ -2291,7 +2285,7 @@ static Int128 do_ld16_beN(CPUArchState *env, MMULooku= pPageData *p, =20 case MO_ATOM_WITHIN16_PAIR: /* Since size > 8, this is the half that must be atomic. */ - return do_ld_whole_be16(env, ra, p, a); + return do_ld_whole_be16(cpu, ra, p, a); =20 case MO_ATOM_IFALIGN_PAIR: /* @@ -2313,29 +2307,29 @@ static Int128 do_ld16_beN(CPUArchState *env, MMULoo= kupPageData *p, return int128_make128(b, a); } =20 -static uint8_t do_ld_1(CPUArchState *env, MMULookupPageData *p, int mmu_id= x, +static uint8_t do_ld_1(CPUState *cpu, MMULookupPageData *p, int mmu_idx, MMUAccessType type, uintptr_t ra) { if (unlikely(p->flags & TLB_MMIO)) { - return do_ld_mmio_beN(env, p->full, 0, p->addr, 1, mmu_idx, type, = ra); + return do_ld_mmio_beN(cpu, p->full, 0, p->addr, 1, mmu_idx, type, = ra); } else { return *(uint8_t *)p->haddr; } } =20 -static uint16_t do_ld_2(CPUArchState *env, MMULookupPageData *p, int mmu_i= dx, +static uint16_t do_ld_2(CPUState *cpu, MMULookupPageData *p, int mmu_idx, MMUAccessType type, MemOp memop, uintptr_t ra) { uint16_t ret; =20 if (unlikely(p->flags & TLB_MMIO)) { - ret =3D do_ld_mmio_beN(env, p->full, 0, p->addr, 2, mmu_idx, type,= ra); + ret =3D do_ld_mmio_beN(cpu, p->full, 0, p->addr, 2, mmu_idx, type,= ra); if ((memop & MO_BSWAP) =3D=3D MO_LE) { ret =3D bswap16(ret); } } else { /* Perform the load host endian, then swap if necessary. */ - ret =3D load_atom_2(env, ra, p->haddr, memop); + ret =3D load_atom_2(cpu_env(cpu), ra, p->haddr, memop); if (memop & MO_BSWAP) { ret =3D bswap16(ret); } @@ -2343,19 +2337,19 @@ static uint16_t do_ld_2(CPUArchState *env, MMULooku= pPageData *p, int mmu_idx, return ret; } =20 -static uint32_t do_ld_4(CPUArchState *env, MMULookupPageData *p, int mmu_i= dx, +static uint32_t do_ld_4(CPUState *cpu, MMULookupPageData *p, int mmu_idx, MMUAccessType type, MemOp memop, uintptr_t ra) { uint32_t ret; =20 if (unlikely(p->flags & TLB_MMIO)) { - ret =3D do_ld_mmio_beN(env, p->full, 0, p->addr, 4, mmu_idx, type,= ra); + ret =3D do_ld_mmio_beN(cpu, p->full, 0, p->addr, 4, mmu_idx, type,= ra); if ((memop & MO_BSWAP) =3D=3D MO_LE) { ret =3D bswap32(ret); } } else { /* Perform the load host endian. */ - ret =3D load_atom_4(env, ra, p->haddr, memop); + ret =3D load_atom_4(cpu_env(cpu), ra, p->haddr, memop); if (memop & MO_BSWAP) { ret =3D bswap32(ret); } @@ -2363,19 +2357,19 @@ static uint32_t do_ld_4(CPUArchState *env, MMULooku= pPageData *p, int mmu_idx, return ret; } =20 -static uint64_t do_ld_8(CPUArchState *env, MMULookupPageData *p, int mmu_i= dx, +static uint64_t do_ld_8(CPUState *cpu, MMULookupPageData *p, int mmu_idx, MMUAccessType type, MemOp memop, uintptr_t ra) { uint64_t ret; =20 if (unlikely(p->flags & TLB_MMIO)) { - ret =3D do_ld_mmio_beN(env, p->full, 0, p->addr, 8, mmu_idx, type,= ra); + ret =3D do_ld_mmio_beN(cpu, p->full, 0, p->addr, 8, mmu_idx, type,= ra); if ((memop & MO_BSWAP) =3D=3D MO_LE) { ret =3D bswap64(ret); } } else { /* Perform the load host endian. */ - ret =3D load_atom_8(env, ra, p->haddr, memop); + ret =3D load_atom_8(cpu_env(cpu), ra, p->haddr, memop); if (memop & MO_BSWAP) { ret =3D bswap64(ret); } @@ -2383,27 +2377,27 @@ static uint64_t do_ld_8(CPUArchState *env, MMULooku= pPageData *p, int mmu_idx, return ret; } =20 -static uint8_t do_ld1_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, +static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { MMULookupLocals l; bool crosspage; =20 cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - crosspage =3D mmu_lookup(env, addr, oi, ra, access_type, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); tcg_debug_assert(!crosspage); =20 - return do_ld_1(env, &l.page[0], l.mmu_idx, access_type, ra); + return do_ld_1(cpu, &l.page[0], l.mmu_idx, access_type, ra); } =20 tcg_target_ulong helper_ldub_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); - return do_ld1_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); + return do_ld1_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD); } =20 -static uint16_t do_ld2_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, +static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { MMULookupLocals l; @@ -2412,13 +2406,13 @@ static uint16_t do_ld2_mmu(CPUArchState *env, vaddr= addr, MemOpIdx oi, uint8_t a, b; =20 cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - crosspage =3D mmu_lookup(env, addr, oi, ra, access_type, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { - return do_ld_2(env, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); + return do_ld_2(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); } =20 - a =3D do_ld_1(env, &l.page[0], l.mmu_idx, access_type, ra); - b =3D do_ld_1(env, &l.page[1], l.mmu_idx, access_type, ra); + a =3D do_ld_1(cpu, &l.page[0], l.mmu_idx, access_type, ra); + b =3D do_ld_1(cpu, &l.page[1], l.mmu_idx, access_type, ra); =20 if ((l.memop & MO_BSWAP) =3D=3D MO_LE) { ret =3D a | (b << 8); @@ -2432,10 +2426,10 @@ tcg_target_ulong helper_lduw_mmu(CPUArchState *env,= uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); - return do_ld2_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); + return do_ld2_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD); } =20 -static uint32_t do_ld4_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, +static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { MMULookupLocals l; @@ -2443,13 +2437,13 @@ static uint32_t do_ld4_mmu(CPUArchState *env, vaddr= addr, MemOpIdx oi, uint32_t ret; =20 cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - crosspage =3D mmu_lookup(env, addr, oi, ra, access_type, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { - return do_ld_4(env, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); + return do_ld_4(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); } =20 - ret =3D do_ld_beN(env, &l.page[0], 0, l.mmu_idx, access_type, l.memop,= ra); - ret =3D do_ld_beN(env, &l.page[1], ret, l.mmu_idx, access_type, l.memo= p, ra); + ret =3D do_ld_beN(cpu, &l.page[0], 0, l.mmu_idx, access_type, l.memop,= ra); + ret =3D do_ld_beN(cpu, &l.page[1], ret, l.mmu_idx, access_type, l.memo= p, ra); if ((l.memop & MO_BSWAP) =3D=3D MO_LE) { ret =3D bswap32(ret); } @@ -2460,10 +2454,10 @@ tcg_target_ulong helper_ldul_mmu(CPUArchState *env,= uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); - return do_ld4_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); + return do_ld4_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD); } =20 -static uint64_t do_ld8_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, +static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { MMULookupLocals l; @@ -2471,13 +2465,13 @@ static uint64_t do_ld8_mmu(CPUArchState *env, vaddr= addr, MemOpIdx oi, uint64_t ret; =20 cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - crosspage =3D mmu_lookup(env, addr, oi, ra, access_type, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { - return do_ld_8(env, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); + return do_ld_8(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); } =20 - ret =3D do_ld_beN(env, &l.page[0], 0, l.mmu_idx, access_type, l.memop,= ra); - ret =3D do_ld_beN(env, &l.page[1], ret, l.mmu_idx, access_type, l.memo= p, ra); + ret =3D do_ld_beN(cpu, &l.page[0], 0, l.mmu_idx, access_type, l.memop,= ra); + ret =3D do_ld_beN(cpu, &l.page[1], ret, l.mmu_idx, access_type, l.memo= p, ra); if ((l.memop & MO_BSWAP) =3D=3D MO_LE) { ret =3D bswap64(ret); } @@ -2488,7 +2482,7 @@ uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t a= ddr, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); - return do_ld8_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); + return do_ld8_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD); } =20 /* @@ -2514,7 +2508,7 @@ tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, u= int64_t addr, return (int32_t)helper_ldul_mmu(env, addr, oi, retaddr); } =20 -static Int128 do_ld16_mmu(CPUArchState *env, vaddr addr, +static Int128 do_ld16_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; @@ -2524,17 +2518,17 @@ static Int128 do_ld16_mmu(CPUArchState *env, vaddr = addr, int first; =20 cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_LOAD, &l); if (likely(!crosspage)) { if (unlikely(l.page[0].flags & TLB_MMIO)) { - ret =3D do_ld16_mmio_beN(env, l.page[0].full, 0, addr, 16, + ret =3D do_ld16_mmio_beN(cpu, l.page[0].full, 0, addr, 16, l.mmu_idx, ra); if ((l.memop & MO_BSWAP) =3D=3D MO_LE) { ret =3D bswap128(ret); } } else { /* Perform the load host endian. */ - ret =3D load_atom_16(env, ra, l.page[0].haddr, l.memop); + ret =3D load_atom_16(cpu_env(cpu), ra, l.page[0].haddr, l.memo= p); if (l.memop & MO_BSWAP) { ret =3D bswap128(ret); } @@ -2546,8 +2540,8 @@ static Int128 do_ld16_mmu(CPUArchState *env, vaddr ad= dr, if (first =3D=3D 8) { MemOp mop8 =3D (l.memop & ~MO_SIZE) | MO_64; =20 - a =3D do_ld_8(env, &l.page[0], l.mmu_idx, MMU_DATA_LOAD, mop8, ra); - b =3D do_ld_8(env, &l.page[1], l.mmu_idx, MMU_DATA_LOAD, mop8, ra); + a =3D do_ld_8(cpu, &l.page[0], l.mmu_idx, MMU_DATA_LOAD, mop8, ra); + b =3D do_ld_8(cpu, &l.page[1], l.mmu_idx, MMU_DATA_LOAD, mop8, ra); if ((mop8 & MO_BSWAP) =3D=3D MO_LE) { ret =3D int128_make128(a, b); } else { @@ -2557,15 +2551,15 @@ static Int128 do_ld16_mmu(CPUArchState *env, vaddr = addr, } =20 if (first < 8) { - a =3D do_ld_beN(env, &l.page[0], 0, l.mmu_idx, + a =3D do_ld_beN(cpu, &l.page[0], 0, l.mmu_idx, MMU_DATA_LOAD, l.memop, ra); - ret =3D do_ld16_beN(env, &l.page[1], a, l.mmu_idx, l.memop, ra); + ret =3D do_ld16_beN(cpu, &l.page[1], a, l.mmu_idx, l.memop, ra); } else { - ret =3D do_ld16_beN(env, &l.page[0], 0, l.mmu_idx, l.memop, ra); + ret =3D do_ld16_beN(cpu, &l.page[0], 0, l.mmu_idx, l.memop, ra); b =3D int128_getlo(ret); ret =3D int128_lshift(ret, l.page[1].size * 8); a =3D int128_gethi(ret); - b =3D do_ld_beN(env, &l.page[1], b, l.mmu_idx, + b =3D do_ld_beN(cpu, &l.page[1], b, l.mmu_idx, MMU_DATA_LOAD, l.memop, ra); ret =3D int128_make128(b, a); } @@ -2579,7 +2573,7 @@ Int128 helper_ld16_mmu(CPUArchState *env, uint64_t ad= dr, uint32_t oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); - return do_ld16_mmu(env, addr, oi, retaddr); + return do_ld16_mmu(env_cpu(env), addr, oi, retaddr); } =20 Int128 helper_ld_i128(CPUArchState *env, uint64_t addr, uint32_t oi) @@ -2601,7 +2595,7 @@ uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, = MemOpIdx oi, uintptr_t ra) uint8_t ret; =20 tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_UB); - ret =3D do_ld1_mmu(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D do_ld1_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; } @@ -2612,7 +2606,7 @@ uint16_t cpu_ldw_mmu(CPUArchState *env, abi_ptr addr, uint16_t ret; =20 tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); - ret =3D do_ld2_mmu(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D do_ld2_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; } @@ -2623,7 +2617,7 @@ uint32_t cpu_ldl_mmu(CPUArchState *env, abi_ptr addr, uint32_t ret; =20 tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); - ret =3D do_ld4_mmu(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D do_ld4_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; } @@ -2634,7 +2628,7 @@ uint64_t cpu_ldq_mmu(CPUArchState *env, abi_ptr addr, uint64_t ret; =20 tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); - ret =3D do_ld8_mmu(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D do_ld8_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; } @@ -2645,7 +2639,7 @@ Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, Int128 ret; =20 tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); - ret =3D do_ld16_mmu(env, addr, oi, ra); + ret =3D do_ld16_mmu(env_cpu(env), addr, oi, ra); plugin_load_cb(env, addr, oi); return ret; } @@ -2656,7 +2650,7 @@ Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, =20 /** * do_st_mmio_leN: - * @env: cpu context + * @cpu: generic cpu state * @full: page parameters * @val_le: data to store * @addr: virtual address @@ -2669,7 +2663,7 @@ Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, * The bytes to store are extracted in little-endian order from @val_le; * return the bytes of @val_le beyond @p->size that have not been stored. */ -static uint64_t int_st_mmio_leN(CPUArchState *env, CPUTLBEntryFull *full, +static uint64_t int_st_mmio_leN(CPUState *cpu, CPUTLBEntryFull *full, uint64_t val_le, vaddr addr, int size, int mmu_idx, uintptr_t ra, MemoryRegion *mr, hwaddr mr_offset) @@ -2687,7 +2681,7 @@ static uint64_t int_st_mmio_leN(CPUArchState *env, CP= UTLBEntryFull *full, r =3D memory_region_dispatch_write(mr, mr_offset, val_le, this_mop, full->attrs); if (unlikely(r !=3D MEMTX_OK)) { - io_failed(env, full, addr, this_size, MMU_DATA_STORE, + io_failed(cpu, full, addr, this_size, MMU_DATA_STORE, mmu_idx, r, ra); } if (this_size =3D=3D 8) { @@ -2703,7 +2697,7 @@ static uint64_t int_st_mmio_leN(CPUArchState *env, CP= UTLBEntryFull *full, return val_le; } =20 -static uint64_t do_st_mmio_leN(CPUArchState *env, CPUTLBEntryFull *full, +static uint64_t do_st_mmio_leN(CPUState *cpu, CPUTLBEntryFull *full, uint64_t val_le, vaddr addr, int size, int mmu_idx, uintptr_t ra) { @@ -2716,18 +2710,18 @@ static uint64_t do_st_mmio_leN(CPUArchState *env, C= PUTLBEntryFull *full, tcg_debug_assert(size > 0 && size <=3D 8); =20 attrs =3D full->attrs; - section =3D io_prepare(&mr_offset, env, full->xlat_section, attrs, add= r, ra); + section =3D io_prepare(&mr_offset, cpu, full->xlat_section, attrs, add= r, ra); mr =3D section->mr; =20 qemu_mutex_lock_iothread(); - ret =3D int_st_mmio_leN(env, full, val_le, addr, size, mmu_idx, + ret =3D int_st_mmio_leN(cpu, full, val_le, addr, size, mmu_idx, ra, mr, mr_offset); qemu_mutex_unlock_iothread(); =20 return ret; } =20 -static uint64_t do_st16_mmio_leN(CPUArchState *env, CPUTLBEntryFull *full, +static uint64_t do_st16_mmio_leN(CPUState *cpu, CPUTLBEntryFull *full, Int128 val_le, vaddr addr, int size, int mmu_idx, uintptr_t ra) { @@ -2740,13 +2734,13 @@ static uint64_t do_st16_mmio_leN(CPUArchState *env,= CPUTLBEntryFull *full, tcg_debug_assert(size > 8 && size <=3D 16); =20 attrs =3D full->attrs; - section =3D io_prepare(&mr_offset, env, full->xlat_section, attrs, add= r, ra); + section =3D io_prepare(&mr_offset, cpu, full->xlat_section, attrs, add= r, ra); mr =3D section->mr; =20 qemu_mutex_lock_iothread(); - int_st_mmio_leN(env, full, int128_getlo(val_le), addr, 8, + int_st_mmio_leN(cpu, full, int128_getlo(val_le), addr, 8, mmu_idx, ra, mr, mr_offset); - ret =3D int_st_mmio_leN(env, full, int128_gethi(val_le), addr + 8, + ret =3D int_st_mmio_leN(cpu, full, int128_gethi(val_le), addr + 8, size - 8, mmu_idx, ra, mr, mr_offset + 8); qemu_mutex_unlock_iothread(); =20 @@ -2756,7 +2750,7 @@ static uint64_t do_st16_mmio_leN(CPUArchState *env, C= PUTLBEntryFull *full, /* * Wrapper for the above. */ -static uint64_t do_st_leN(CPUArchState *env, MMULookupPageData *p, +static uint64_t do_st_leN(CPUState *cpu, MMULookupPageData *p, uint64_t val_le, int mmu_idx, MemOp mop, uintptr_t ra) { @@ -2764,7 +2758,7 @@ static uint64_t do_st_leN(CPUArchState *env, MMULooku= pPageData *p, unsigned tmp, half_size; =20 if (unlikely(p->flags & TLB_MMIO)) { - return do_st_mmio_leN(env, p->full, val_le, p->addr, + return do_st_mmio_leN(cpu, p->full, val_le, p->addr, p->size, mmu_idx, ra); } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { return val_le >> (p->size * 8); @@ -2792,7 +2786,7 @@ static uint64_t do_st_leN(CPUArchState *env, MMULooku= pPageData *p, } else if (HAVE_al8) { return store_whole_le8(p->haddr, p->size, val_le); } else { - cpu_loop_exit_atomic(env_cpu(env), ra); + cpu_loop_exit_atomic(cpu, ra); } } /* fall through */ @@ -2810,7 +2804,7 @@ static uint64_t do_st_leN(CPUArchState *env, MMULooku= pPageData *p, /* * Wrapper for the above, for 8 < size < 16. */ -static uint64_t do_st16_leN(CPUArchState *env, MMULookupPageData *p, +static uint64_t do_st16_leN(CPUState *cpu, MMULookupPageData *p, Int128 val_le, int mmu_idx, MemOp mop, uintptr_t ra) { @@ -2818,7 +2812,7 @@ static uint64_t do_st16_leN(CPUArchState *env, MMULoo= kupPageData *p, MemOp atom; =20 if (unlikely(p->flags & TLB_MMIO)) { - return do_st16_mmio_leN(env, p->full, val_le, p->addr, + return do_st16_mmio_leN(cpu, p->full, val_le, p->addr, size, mmu_idx, ra); } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { return int128_gethi(val_le) >> ((size - 8) * 8); @@ -2838,7 +2832,7 @@ static uint64_t do_st16_leN(CPUArchState *env, MMULoo= kupPageData *p, case MO_ATOM_WITHIN16_PAIR: /* Since size > 8, this is the half that must be atomic. */ if (!HAVE_ATOMIC128_RW) { - cpu_loop_exit_atomic(env_cpu(env), ra); + cpu_loop_exit_atomic(cpu, ra); } return store_whole_le16(p->haddr, p->size, val_le); =20 @@ -2859,11 +2853,11 @@ static uint64_t do_st16_leN(CPUArchState *env, MMUL= ookupPageData *p, } } =20 -static void do_st_1(CPUArchState *env, MMULookupPageData *p, uint8_t val, +static void do_st_1(CPUState *cpu, MMULookupPageData *p, uint8_t val, int mmu_idx, uintptr_t ra) { if (unlikely(p->flags & TLB_MMIO)) { - do_st_mmio_leN(env, p->full, val, p->addr, 1, mmu_idx, ra); + do_st_mmio_leN(cpu, p->full, val, p->addr, 1, mmu_idx, ra); } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { /* nothing */ } else { @@ -2871,14 +2865,14 @@ static void do_st_1(CPUArchState *env, MMULookupPag= eData *p, uint8_t val, } } =20 -static void do_st_2(CPUArchState *env, MMULookupPageData *p, uint16_t val, +static void do_st_2(CPUState *cpu, MMULookupPageData *p, uint16_t val, int mmu_idx, MemOp memop, uintptr_t ra) { if (unlikely(p->flags & TLB_MMIO)) { if ((memop & MO_BSWAP) !=3D MO_LE) { val =3D bswap16(val); } - do_st_mmio_leN(env, p->full, val, p->addr, 2, mmu_idx, ra); + do_st_mmio_leN(cpu, p->full, val, p->addr, 2, mmu_idx, ra); } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { /* nothing */ } else { @@ -2886,18 +2880,18 @@ static void do_st_2(CPUArchState *env, MMULookupPag= eData *p, uint16_t val, if (memop & MO_BSWAP) { val =3D bswap16(val); } - store_atom_2(env, ra, p->haddr, memop, val); + store_atom_2(cpu_env(cpu), ra, p->haddr, memop, val); } } =20 -static void do_st_4(CPUArchState *env, MMULookupPageData *p, uint32_t val, +static void do_st_4(CPUState *cpu, MMULookupPageData *p, uint32_t val, int mmu_idx, MemOp memop, uintptr_t ra) { if (unlikely(p->flags & TLB_MMIO)) { if ((memop & MO_BSWAP) !=3D MO_LE) { val =3D bswap32(val); } - do_st_mmio_leN(env, p->full, val, p->addr, 4, mmu_idx, ra); + do_st_mmio_leN(cpu, p->full, val, p->addr, 4, mmu_idx, ra); } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { /* nothing */ } else { @@ -2905,18 +2899,18 @@ static void do_st_4(CPUArchState *env, MMULookupPag= eData *p, uint32_t val, if (memop & MO_BSWAP) { val =3D bswap32(val); } - store_atom_4(env, ra, p->haddr, memop, val); + store_atom_4(cpu_env(cpu), ra, p->haddr, memop, val); } } =20 -static void do_st_8(CPUArchState *env, MMULookupPageData *p, uint64_t val, +static void do_st_8(CPUState *cpu, MMULookupPageData *p, uint64_t val, int mmu_idx, MemOp memop, uintptr_t ra) { if (unlikely(p->flags & TLB_MMIO)) { if ((memop & MO_BSWAP) !=3D MO_LE) { val =3D bswap64(val); } - do_st_mmio_leN(env, p->full, val, p->addr, 8, mmu_idx, ra); + do_st_mmio_leN(cpu, p->full, val, p->addr, 8, mmu_idx, ra); } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { /* nothing */ } else { @@ -2924,7 +2918,7 @@ static void do_st_8(CPUArchState *env, MMULookupPageD= ata *p, uint64_t val, if (memop & MO_BSWAP) { val =3D bswap64(val); } - store_atom_8(env, ra, p->haddr, memop, val); + store_atom_8(cpu_env(cpu), ra, p->haddr, memop, val); } } =20 @@ -2936,13 +2930,13 @@ void helper_stb_mmu(CPUArchState *env, uint64_t add= r, uint32_t val, =20 tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); + crosspage =3D mmu_lookup(env_cpu(env), addr, oi, ra, MMU_DATA_STORE, &= l); tcg_debug_assert(!crosspage); =20 - do_st_1(env, &l.page[0], val, l.mmu_idx, ra); + do_st_1(env_cpu(env), &l.page[0], val, l.mmu_idx, ra); } =20 -static void do_st2_mmu(CPUArchState *env, vaddr addr, uint16_t val, +static void do_st2_mmu(CPUState *cpu, vaddr addr, uint16_t val, MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; @@ -2950,9 +2944,9 @@ static void do_st2_mmu(CPUArchState *env, vaddr addr,= uint16_t val, uint8_t a, b; =20 cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { - do_st_2(env, &l.page[0], val, l.mmu_idx, l.memop, ra); + do_st_2(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); return; } =20 @@ -2961,27 +2955,27 @@ static void do_st2_mmu(CPUArchState *env, vaddr add= r, uint16_t val, } else { b =3D val, a =3D val >> 8; } - do_st_1(env, &l.page[0], a, l.mmu_idx, ra); - do_st_1(env, &l.page[1], b, l.mmu_idx, ra); + do_st_1(cpu, &l.page[0], a, l.mmu_idx, ra); + do_st_1(cpu, &l.page[1], b, l.mmu_idx, ra); } =20 void helper_stw_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); - do_st2_mmu(env, addr, val, oi, retaddr); + do_st2_mmu(env_cpu(env), addr, val, oi, retaddr); } =20 -static void do_st4_mmu(CPUArchState *env, vaddr addr, uint32_t val, +static void do_st4_mmu(CPUState *cpu, vaddr addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; bool crosspage; =20 cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { - do_st_4(env, &l.page[0], val, l.mmu_idx, l.memop, ra); + do_st_4(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); return; } =20 @@ -2989,27 +2983,27 @@ static void do_st4_mmu(CPUArchState *env, vaddr add= r, uint32_t val, if ((l.memop & MO_BSWAP) !=3D MO_LE) { val =3D bswap32(val); } - val =3D do_st_leN(env, &l.page[0], val, l.mmu_idx, l.memop, ra); - (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); + val =3D do_st_leN(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); + (void) do_st_leN(cpu, &l.page[1], val, l.mmu_idx, l.memop, ra); } =20 void helper_stl_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); - do_st4_mmu(env, addr, val, oi, retaddr); + do_st4_mmu(env_cpu(env), addr, val, oi, retaddr); } =20 -static void do_st8_mmu(CPUArchState *env, vaddr addr, uint64_t val, +static void do_st8_mmu(CPUState *cpu, vaddr addr, uint64_t val, MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; bool crosspage; =20 cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { - do_st_8(env, &l.page[0], val, l.mmu_idx, l.memop, ra); + do_st_8(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); return; } =20 @@ -3017,18 +3011,18 @@ static void do_st8_mmu(CPUArchState *env, vaddr add= r, uint64_t val, if ((l.memop & MO_BSWAP) !=3D MO_LE) { val =3D bswap64(val); } - val =3D do_st_leN(env, &l.page[0], val, l.mmu_idx, l.memop, ra); - (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); + val =3D do_st_leN(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); + (void) do_st_leN(cpu, &l.page[1], val, l.mmu_idx, l.memop, ra); } =20 void helper_stq_mmu(CPUArchState *env, uint64_t addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); - do_st8_mmu(env, addr, val, oi, retaddr); + do_st8_mmu(env_cpu(env), addr, val, oi, retaddr); } =20 -static void do_st16_mmu(CPUArchState *env, vaddr addr, Int128 val, +static void do_st16_mmu(CPUState *cpu, vaddr addr, Int128 val, MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; @@ -3037,13 +3031,13 @@ static void do_st16_mmu(CPUArchState *env, vaddr ad= dr, Int128 val, int first; =20 cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { if (unlikely(l.page[0].flags & TLB_MMIO)) { if ((l.memop & MO_BSWAP) !=3D MO_LE) { val =3D bswap128(val); } - do_st16_mmio_leN(env, l.page[0].full, val, addr, 16, l.mmu_idx= , ra); + do_st16_mmio_leN(cpu, l.page[0].full, val, addr, 16, l.mmu_idx= , ra); } else if (unlikely(l.page[0].flags & TLB_DISCARD_WRITE)) { /* nothing */ } else { @@ -3051,7 +3045,7 @@ static void do_st16_mmu(CPUArchState *env, vaddr addr= , Int128 val, if (l.memop & MO_BSWAP) { val =3D bswap128(val); } - store_atom_16(env, ra, l.page[0].haddr, l.memop, val); + store_atom_16(cpu_env(cpu), ra, l.page[0].haddr, l.memop, val); } return; } @@ -3068,8 +3062,8 @@ static void do_st16_mmu(CPUArchState *env, vaddr addr= , Int128 val, } else { a =3D int128_getlo(val), b =3D int128_gethi(val); } - do_st_8(env, &l.page[0], a, l.mmu_idx, mop8, ra); - do_st_8(env, &l.page[1], b, l.mmu_idx, mop8, ra); + do_st_8(cpu, &l.page[0], a, l.mmu_idx, mop8, ra); + do_st_8(cpu, &l.page[1], b, l.mmu_idx, mop8, ra); return; } =20 @@ -3077,12 +3071,12 @@ static void do_st16_mmu(CPUArchState *env, vaddr ad= dr, Int128 val, val =3D bswap128(val); } if (first < 8) { - do_st_leN(env, &l.page[0], int128_getlo(val), l.mmu_idx, l.memop, = ra); + do_st_leN(cpu, &l.page[0], int128_getlo(val), l.mmu_idx, l.memop, = ra); val =3D int128_urshift(val, first * 8); - do_st16_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); + do_st16_leN(cpu, &l.page[1], val, l.mmu_idx, l.memop, ra); } else { - b =3D do_st16_leN(env, &l.page[0], val, l.mmu_idx, l.memop, ra); - do_st_leN(env, &l.page[1], b, l.mmu_idx, l.memop, ra); + b =3D do_st16_leN(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); + do_st_leN(cpu, &l.page[1], b, l.mmu_idx, l.memop, ra); } } =20 @@ -3090,7 +3084,7 @@ void helper_st16_mmu(CPUArchState *env, uint64_t addr= , Int128 val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); - do_st16_mmu(env, addr, val, oi, retaddr); + do_st16_mmu(env_cpu(env), addr, val, oi, retaddr); } =20 void helper_st_i128(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx= oi) @@ -3118,7 +3112,7 @@ void cpu_stw_mmu(CPUArchState *env, abi_ptr addr, uin= t16_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); - do_st2_mmu(env, addr, val, oi, retaddr); + do_st2_mmu(env_cpu(env), addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 @@ -3126,7 +3120,7 @@ void cpu_stl_mmu(CPUArchState *env, abi_ptr addr, uin= t32_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); - do_st4_mmu(env, addr, val, oi, retaddr); + do_st4_mmu(env_cpu(env), addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 @@ -3134,7 +3128,7 @@ void cpu_stq_mmu(CPUArchState *env, abi_ptr addr, uin= t64_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); - do_st8_mmu(env, addr, val, oi, retaddr); + do_st8_mmu(env_cpu(env), addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 @@ -3142,7 +3136,7 @@ void cpu_st16_mmu(CPUArchState *env, abi_ptr addr, In= t128 val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); - do_st16_mmu(env, addr, val, oi, retaddr); + do_st16_mmu(env_cpu(env), addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 @@ -3184,47 +3178,47 @@ void cpu_st16_mmu(CPUArchState *env, abi_ptr addr, = Int128 val, uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr) { MemOpIdx oi =3D make_memop_idx(MO_UB, cpu_mmu_index(env, true)); - return do_ld1_mmu(env, addr, oi, 0, MMU_INST_FETCH); + return do_ld1_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); } =20 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr) { MemOpIdx oi =3D make_memop_idx(MO_TEUW, cpu_mmu_index(env, true)); - return do_ld2_mmu(env, addr, oi, 0, MMU_INST_FETCH); + return do_ld2_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); } =20 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr) { MemOpIdx oi =3D make_memop_idx(MO_TEUL, cpu_mmu_index(env, true)); - return do_ld4_mmu(env, addr, oi, 0, MMU_INST_FETCH); + return do_ld4_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); } =20 uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr) { MemOpIdx oi =3D make_memop_idx(MO_TEUQ, cpu_mmu_index(env, true)); - return do_ld8_mmu(env, addr, oi, 0, MMU_INST_FETCH); + return do_ld8_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); } =20 uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t retaddr) { - return do_ld1_mmu(env, addr, oi, retaddr, MMU_INST_FETCH); + return do_ld1_mmu(env_cpu(env), addr, oi, retaddr, MMU_INST_FETCH); } =20 uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t retaddr) { - return do_ld2_mmu(env, addr, oi, retaddr, MMU_INST_FETCH); + return do_ld2_mmu(env_cpu(env), addr, oi, retaddr, MMU_INST_FETCH); } =20 uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t retaddr) { - return do_ld4_mmu(env, addr, oi, retaddr, MMU_INST_FETCH); + return do_ld4_mmu(env_cpu(env), addr, oi, retaddr, MMU_INST_FETCH); } =20 uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t retaddr) { - return do_ld8_mmu(env, addr, oi, retaddr, MMU_INST_FETCH); + return do_ld8_mmu(env_cpu(env), addr, oi, retaddr, MMU_INST_FETCH); } --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900576; cv=none; d=zohomail.com; s=zohoarc; b=klXYpc4M2zS8Uxn1nzTpf0OAlayrINzZaALr52H0laJ/J/zY8g9tIEpJxDCpyBfs+JTeUZ9+Ts+9aQH5qk8VAS5A6iz3YTEe8sWeTOk6XgMUNzFvQ5A2E9i8pwontyUqrlxISDOVoqJYu2CBEdVzNf29ZEopIJmpfEEtYXsyQzA= ARC-Message-Signature: i=1; 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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900504; x=1695505304; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RvbFDtGLZivKyhzTWEmUTibtY/MIhWAoXf/kD9e6jJo=; b=ZFX6tegQ31+UtytKhaPOcxZdSjmUEzF4hMaR0xrUg5wV/AnUa4g+P4Gq5EXpaVvTjq IjEaDIFAhXPhIJuRf6ypW8hAy88LPJgSi4qw2RapJIOUvl//0+HDpDaAT860k29fVnBu f69MDUYkecJO9KMXIDmO+NvTRqjGV2O118vtkvCaCEtW2SnMoKyrbavBTvXYF98r33dv kbTM7vxaSPbs2AQHuPpZYwsIykIbN/sDA63OOzFcN4gT+cBRx2/0yZHXoxWexoVUY0ic CwNVd7oNEVpipX/hjdmlA1v9Sf4H0RXRpXQZNh+/JYNf317hUbVK+ZgViIuzdmmfKIHm HgPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900504; x=1695505304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RvbFDtGLZivKyhzTWEmUTibtY/MIhWAoXf/kD9e6jJo=; b=X9PwXYodP0NXBNukQzjrBBnXEWDooBn8yvVBAy+Zvr8AJcg4yy+ewoTJMBa3a+R1bL n3uq1evI7ysXrJjeCBLfMK5I4NoVtiKh7Y/LOaFnNn/bomNzsH+RU40k++XWUJMTMFz8 Cy6Zq98bh5Xj6wvkBdW87SXxFJtd9VYKQRXitSoJRMWfQBIKPYjFRNrCAMEXlFlOyVdH ZJIwUaDUbTn1I/g8hwnvfif7N5A0QFUlTGlrhfoVlg3vjRkMNji/EMS74Qu8jSivH81U ntJVwwiw/b84Hxraxh6eRMU7m9tSwFA1vX7URjCwffansP+balnjoWpjEQPGcZ0Fd30f AuXw== X-Gm-Message-State: AOJu0YwOeUTTUw8tjhQIySi3rrxcOHE+ViPeU0aZuvRL/PVL+fX3IRg9 3/yDHfCaHwH+h1uDW/yGuiF+bs7hr1fH08vKuDw= X-Google-Smtp-Source: AGHT+IEBJYp/rh5CbIbN+Y+ou80rmO1KP0beQwDb+O+dEJsljzcELbuFpdx4ZOKhyJb94GKvcXULuA== X-Received: by 2002:a05:6870:9728:b0:1d6:3b6d:f824 with SMTP id n40-20020a056870972800b001d63b6df824mr7072837oaq.36.1694900504294; Sat, 16 Sep 2023 14:41:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 19/39] accel/tcg: Modify atomic_mmu_lookup() to use CPUState Date: Sat, 16 Sep 2023 14:41:03 -0700 Message-Id: <20230916214123.525796-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2e; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900578547100006 From: Anton Johansson The goal is to (in the future) allow for per-target compilation of functions in atomic_template.h whilst atomic_mmu_lookup() and cputlb.c are compiled once-per user- or system mode. Signed-off-by: Anton Johansson Message-Id: <20230912153428.17816-7-anjo@rev.ng> Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 [rth: Use cpu->neg.tlb instead of cpu_tlb()] Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 20 ++++++++++++-------- accel/tcg/cputlb.c | 26 +++++++++++++------------- accel/tcg/user-exec.c | 8 ++++---- 3 files changed, 29 insertions(+), 25 deletions(-) diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index 84c08b1425..1dc2151daf 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -73,7 +73,8 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, abi_ptr = addr, ABI_TYPE cmpv, ABI_TYPE newv, MemOpIdx oi, uintptr_t retaddr) { - DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retad= dr); + DATA_TYPE *haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, + DATA_SIZE, retaddr); DATA_TYPE ret; =20 #if DATA_SIZE =3D=3D 16 @@ -90,7 +91,8 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, abi_ptr = addr, ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, abi_ptr addr, ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) { - DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retad= dr); + DATA_TYPE *haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, + DATA_SIZE, retaddr); DATA_TYPE ret; =20 ret =3D qatomic_xchg__nocheck(haddr, val); @@ -104,7 +106,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, abi_ptr addr= , \ ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \ { \ DATA_TYPE *haddr, ret; \ - haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr); \ + haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, DATA_SIZE, retaddr= ); \ ret =3D qatomic_##X(haddr, val); \ ATOMIC_MMU_CLEANUP; \ atomic_trace_rmw_post(env, addr, oi); \ @@ -135,7 +137,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, abi_ptr addr= , \ ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \ { \ XDATA_TYPE *haddr, cmp, old, new, val =3D xval; \ - haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr); \ + haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, DATA_SIZE, retaddr= ); \ smp_mb(); \ cmp =3D qatomic_read__nocheck(haddr); \ do { \ @@ -176,7 +178,8 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, abi_pt= r addr, ABI_TYPE cmpv, ABI_TYPE newv, MemOpIdx oi, uintptr_t retaddr) { - DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retad= dr); + DATA_TYPE *haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, + DATA_SIZE, retaddr); DATA_TYPE ret; =20 #if DATA_SIZE =3D=3D 16 @@ -193,7 +196,8 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, abi_pt= r addr, ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, abi_ptr addr, ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) { - DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retad= dr); + DATA_TYPE *haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, + DATA_SIZE, retaddr); ABI_TYPE ret; =20 ret =3D qatomic_xchg__nocheck(haddr, BSWAP(val)); @@ -207,7 +211,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, abi_ptr addr= , \ ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \ { \ DATA_TYPE *haddr, ret; \ - haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr); \ + haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, DATA_SIZE, retaddr= ); \ ret =3D qatomic_##X(haddr, BSWAP(val)); \ ATOMIC_MMU_CLEANUP; \ atomic_trace_rmw_post(env, addr, oi); \ @@ -235,7 +239,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, abi_ptr addr= , \ ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \ { \ XDATA_TYPE *haddr, ldo, ldn, old, new, val =3D xval; \ - haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr); \ + haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, DATA_SIZE, retaddr= ); \ smp_mb(); \ ldn =3D qatomic_read__nocheck(haddr); \ do { \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 0e4bc82294..3703443b5c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1856,7 +1856,7 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, Mem= OpIdx oi, * Probe for an atomic operation. Do not allow unaligned operations, * or io operations to proceed. Return the host address. */ -static void *atomic_mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi, +static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, int size, uintptr_t retaddr) { uintptr_t mmu_idx =3D get_mmuidx(oi); @@ -1876,7 +1876,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, vad= dr addr, MemOpIdx oi, /* Enforce guest required alignment. */ if (unlikely(a_bits > 0 && (addr & ((1 << a_bits) - 1)))) { /* ??? Maybe indicate atomic op to cpu_unaligned_access */ - cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, + cpu_unaligned_access(cpu, addr, MMU_DATA_STORE, mmu_idx, retaddr); } =20 @@ -1889,18 +1889,18 @@ static void *atomic_mmu_lookup(CPUArchState *env, v= addr addr, MemOpIdx oi, goto stop_the_world; } =20 - index =3D tlb_index(env_cpu(env), mmu_idx, addr); - tlbe =3D tlb_entry(env_cpu(env), mmu_idx, addr); + index =3D tlb_index(cpu, mmu_idx, addr); + tlbe =3D tlb_entry(cpu, mmu_idx, addr); =20 /* Check TLB entry and enforce page permissions. */ tlb_addr =3D tlb_addr_write(tlbe); if (!tlb_hit(tlb_addr, addr)) { - if (!victim_tlb_hit(env_cpu(env), mmu_idx, index, MMU_DATA_STORE, + if (!victim_tlb_hit(cpu, mmu_idx, index, MMU_DATA_STORE, addr & TARGET_PAGE_MASK)) { - tlb_fill(env_cpu(env), addr, size, + tlb_fill(cpu, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); - index =3D tlb_index(env_cpu(env), mmu_idx, addr); - tlbe =3D tlb_entry(env_cpu(env), mmu_idx, addr); + index =3D tlb_index(cpu, mmu_idx, addr); + tlbe =3D tlb_entry(cpu, mmu_idx, addr); } tlb_addr =3D tlb_addr_write(tlbe) & ~TLB_INVALID_MASK; } @@ -1912,7 +1912,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, vad= dr addr, MemOpIdx oi, * but addr_read will only be -1 if PAGE_READ was unset. */ if (unlikely(tlbe->addr_read =3D=3D -1)) { - tlb_fill(env_cpu(env), addr, size, MMU_DATA_LOAD, mmu_idx, retaddr= ); + tlb_fill(cpu, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); /* * Since we don't support reads and writes to different * addresses, and we do have the proper page loaded for @@ -1932,10 +1932,10 @@ static void *atomic_mmu_lookup(CPUArchState *env, v= addr addr, MemOpIdx oi, } =20 hostaddr =3D (void *)((uintptr_t)addr + tlbe->addend); - full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; =20 if (unlikely(tlb_addr & TLB_NOTDIRTY)) { - notdirty_write(env_cpu(env), addr, size, full, retaddr); + notdirty_write(cpu, addr, size, full, retaddr); } =20 if (unlikely(tlb_addr & TLB_FORCE_SLOW)) { @@ -1948,7 +1948,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, vad= dr addr, MemOpIdx oi, wp_flags |=3D BP_MEM_READ; } if (wp_flags) { - cpu_check_watchpoint(env_cpu(env), addr, size, + cpu_check_watchpoint(cpu, addr, size, full->attrs, wp_flags, retaddr); } } @@ -1956,7 +1956,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, vad= dr addr, MemOpIdx oi, return hostaddr; =20 stop_the_world: - cpu_loop_exit_atomic(env_cpu(env), retaddr); + cpu_loop_exit_atomic(cpu, retaddr); } =20 /* diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index ab48cb41e4..d2daeafbab 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1386,7 +1386,7 @@ uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr = addr, /* * Do not allow unaligned operations to proceed. Return the host address. */ -static void *atomic_mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi, +static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, int size, uintptr_t retaddr) { MemOp mop =3D get_memop(oi); @@ -1395,15 +1395,15 @@ static void *atomic_mmu_lookup(CPUArchState *env, v= addr addr, MemOpIdx oi, =20 /* Enforce guest required alignment. */ if (unlikely(addr & ((1 << a_bits) - 1))) { - cpu_loop_exit_sigbus(env_cpu(env), addr, MMU_DATA_STORE, retaddr); + cpu_loop_exit_sigbus(cpu, addr, MMU_DATA_STORE, retaddr); } =20 /* Enforce qemu required alignment. */ if (unlikely(addr & (size - 1))) { - cpu_loop_exit_atomic(env_cpu(env), retaddr); + cpu_loop_exit_atomic(cpu, retaddr); } =20 - ret =3D g2h(env_cpu(env), addr); + ret =3D g2h(cpu, addr); set_helper_retaddr(retaddr); return ret; } --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900737; cv=none; d=zohomail.com; s=zohoarc; b=fABc/mf6z16zfAM+W/MABrOSQFPzxOt+fKeBaYR5vp3pGs9hnoROdcFRNlNhhioloMhvfPju7LHWeMQsWeAPLSAoGtigamw9SqkY2BVvT0sQF9TDJXJr3Y+4lTzPbpF0n7KeYUJHsITOLsMGfuW2Q5F7Hhx1bQTtw8W2MhHM2SM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900737; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qW54hCoTAvx/Z0R8zzoqjJQHmhjcOZWUd1CkyEKZiYI=; b=npDUcJWSwK86sZlPQ5+caeo78Y5eR/l52YghVpxvMJ2jd0+YWsGLZsrEPQbl8AWESVAtd/Ui2H9haJ7MrLJPnIgLFFgewUGMb5LGxjiOfkZ80sCy1E4K03RwAAyEoRl5oRydzquEc3/nJLVOC+LQFVZCgFnSdm3kM6RUAWPfLKE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900737525743.0477935493174; Sat, 16 Sep 2023 14:45:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd3l-0006Ca-4H; Sat, 16 Sep 2023 17:42:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd2z-0005BS-II for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:49 -0400 Received: from mail-oo1-xc2e.google.com ([2607:f8b0:4864:20::c2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd2w-0000TL-LX for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:49 -0400 Received: by mail-oo1-xc2e.google.com with SMTP id 006d021491bc7-571194584e2so1977731eaf.3 for ; Sat, 16 Sep 2023 14:41:46 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900505; x=1695505305; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qW54hCoTAvx/Z0R8zzoqjJQHmhjcOZWUd1CkyEKZiYI=; b=X2DKDHYuEk2joN7cF/iHEZggqv8aq3pG3wrawCqP8Gu7R66mSPJptZfd5tXVg5fvrf jRFI0jswa+o1FABHbnarSBsMi8Psv5Ob9JSVe67cpxfNFO4zGU24N4jr14+Kjko//g6Z oQEUF/urCjnNzGPWcp2S9GIZGC8MWzDtAKXkmFZbF4Nf8rbiTpA8zXkjKOidMsvPuK+K QTDBe+wIqLViUqmbfMEJN0AZ1FJyjNnatEdV02Mhbk4+kbIHFaFIp8Rn6xciotBUdlBb Wrkbq/7MNJlVs5K4I/mMp7i+JEDDLk8/1N9Vdy64PvFZzCyn2m5o18tpwTp5LAVYCfcw BV+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900505; x=1695505305; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qW54hCoTAvx/Z0R8zzoqjJQHmhjcOZWUd1CkyEKZiYI=; b=T2diJlofxe6t1+ARCLPjzgvUQzVmSBoVMWP6+CR2yzlOXPljAzNcaCT5/5TLoP1368 rK6H0XtmtxsBeD6Ng3c7qBdLOa3kbha2deTG4qIREmXBPFOPEoRXkTeWmVh0jzCShXAe snCYJihsAx9OPcqeOqmfZ9M5s49BdzXalUebAhKl4AWAUGkXRISMYtMseQgl7MOY1+XF StTjDeAECk/p3kyLBRxuXFz1uStL7FcPKQAe5HdDUSgVn4kgbVUgfSm+cZ/y7ppzVWzc yMKD+n90j9i7D8t79HHHvvA3UI1sB5e0DUYT/jOhpPnJYkMnps3BN59jAKuddaVGDEuk NQlA== X-Gm-Message-State: AOJu0YwdMDC4Jt3yRe/1abJ9q4zVqXbgvZ8jiDtLcjRagx7YPEW2rl7C AUAxUqacNKR0ig3uCerpXSySLiKbST79vENcxcY= X-Google-Smtp-Source: AGHT+IEvFRiGtXfATglDBTV+x7VNTcZtKBoNT1SNDIzwOZk1wISmN/3lzwz9cj4E8Ks3smY7mn8vRQ== X-Received: by 2002:a05:6358:52cd:b0:132:d333:4a5c with SMTP id z13-20020a05635852cd00b00132d3334a5cmr6398993rwz.10.1694900505440; Sat, 16 Sep 2023 14:41:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 20/39] accel/tcg: Use CPUState in atomicity helpers Date: Sat, 16 Sep 2023 14:41:04 -0700 Message-Id: <20230916214123.525796-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2e; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900739604100003 From: Anton Johansson Makes ldst_atomicity.c.inc almost target-independent, with the exception of TARGET_PAGE_MASK, which will be addressed in a future patch. Signed-off-by: Anton Johansson Message-Id: <20230912153428.17816-8-anjo@rev.ng> Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 20 ++++---- accel/tcg/user-exec.c | 16 +++---- accel/tcg/ldst_atomicity.c.inc | 88 +++++++++++++++++----------------- 3 files changed, 62 insertions(+), 62 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3703443b5c..17fa7a514c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2172,7 +2172,7 @@ static uint64_t do_ld_whole_be8(CPUState *cpu, uintpt= r_t ra, MMULookupPageData *p, uint64_t ret_be) { int o =3D p->addr & 7; - uint64_t x =3D load_atomic8_or_exit(cpu_env(cpu), ra, p->haddr - o); + uint64_t x =3D load_atomic8_or_exit(cpu, ra, p->haddr - o); =20 x =3D cpu_to_be64(x); x <<=3D o * 8; @@ -2192,7 +2192,7 @@ static Int128 do_ld_whole_be16(CPUState *cpu, uintptr= _t ra, MMULookupPageData *p, uint64_t ret_be) { int o =3D p->addr & 15; - Int128 x, y =3D load_atomic16_or_exit(cpu_env(cpu), ra, p->haddr - o); + Int128 x, y =3D load_atomic16_or_exit(cpu, ra, p->haddr - o); int size =3D p->size; =20 if (!HOST_BIG_ENDIAN) { @@ -2329,7 +2329,7 @@ static uint16_t do_ld_2(CPUState *cpu, MMULookupPageD= ata *p, int mmu_idx, } } else { /* Perform the load host endian, then swap if necessary. */ - ret =3D load_atom_2(cpu_env(cpu), ra, p->haddr, memop); + ret =3D load_atom_2(cpu, ra, p->haddr, memop); if (memop & MO_BSWAP) { ret =3D bswap16(ret); } @@ -2349,7 +2349,7 @@ static uint32_t do_ld_4(CPUState *cpu, MMULookupPageD= ata *p, int mmu_idx, } } else { /* Perform the load host endian. */ - ret =3D load_atom_4(cpu_env(cpu), ra, p->haddr, memop); + ret =3D load_atom_4(cpu, ra, p->haddr, memop); if (memop & MO_BSWAP) { ret =3D bswap32(ret); } @@ -2369,7 +2369,7 @@ static uint64_t do_ld_8(CPUState *cpu, MMULookupPageD= ata *p, int mmu_idx, } } else { /* Perform the load host endian. */ - ret =3D load_atom_8(cpu_env(cpu), ra, p->haddr, memop); + ret =3D load_atom_8(cpu, ra, p->haddr, memop); if (memop & MO_BSWAP) { ret =3D bswap64(ret); } @@ -2528,7 +2528,7 @@ static Int128 do_ld16_mmu(CPUState *cpu, vaddr addr, } } else { /* Perform the load host endian. */ - ret =3D load_atom_16(cpu_env(cpu), ra, l.page[0].haddr, l.memo= p); + ret =3D load_atom_16(cpu, ra, l.page[0].haddr, l.memop); if (l.memop & MO_BSWAP) { ret =3D bswap128(ret); } @@ -2880,7 +2880,7 @@ static void do_st_2(CPUState *cpu, MMULookupPageData = *p, uint16_t val, if (memop & MO_BSWAP) { val =3D bswap16(val); } - store_atom_2(cpu_env(cpu), ra, p->haddr, memop, val); + store_atom_2(cpu, ra, p->haddr, memop, val); } } =20 @@ -2899,7 +2899,7 @@ static void do_st_4(CPUState *cpu, MMULookupPageData = *p, uint32_t val, if (memop & MO_BSWAP) { val =3D bswap32(val); } - store_atom_4(cpu_env(cpu), ra, p->haddr, memop, val); + store_atom_4(cpu, ra, p->haddr, memop, val); } } =20 @@ -2918,7 +2918,7 @@ static void do_st_8(CPUState *cpu, MMULookupPageData = *p, uint64_t val, if (memop & MO_BSWAP) { val =3D bswap64(val); } - store_atom_8(cpu_env(cpu), ra, p->haddr, memop, val); + store_atom_8(cpu, ra, p->haddr, memop, val); } } =20 @@ -3045,7 +3045,7 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, In= t128 val, if (l.memop & MO_BSWAP) { val =3D bswap128(val); } - store_atom_16(cpu_env(cpu), ra, l.page[0].haddr, l.memop, val); + store_atom_16(cpu, ra, l.page[0].haddr, l.memop, val); } return; } diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index d2daeafbab..f9f5cd1770 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1002,7 +1002,7 @@ static uint16_t do_ld2_mmu(CPUArchState *env, abi_ptr= addr, tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_16); cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); - ret =3D load_atom_2(env, ra, haddr, mop); + ret =3D load_atom_2(env_cpu(env), ra, haddr, mop); clear_helper_retaddr(); =20 if (mop & MO_BSWAP) { @@ -1040,7 +1040,7 @@ static uint32_t do_ld4_mmu(CPUArchState *env, abi_ptr= addr, tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_32); cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); - ret =3D load_atom_4(env, ra, haddr, mop); + ret =3D load_atom_4(env_cpu(env), ra, haddr, mop); clear_helper_retaddr(); =20 if (mop & MO_BSWAP) { @@ -1078,7 +1078,7 @@ static uint64_t do_ld8_mmu(CPUArchState *env, abi_ptr= addr, tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_64); cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); - ret =3D load_atom_8(env, ra, haddr, mop); + ret =3D load_atom_8(env_cpu(env), ra, haddr, mop); clear_helper_retaddr(); =20 if (mop & MO_BSWAP) { @@ -1110,7 +1110,7 @@ static Int128 do_ld16_mmu(CPUArchState *env, abi_ptr = addr, tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_128); cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); - ret =3D load_atom_16(env, ra, haddr, mop); + ret =3D load_atom_16(env_cpu(env), ra, haddr, mop); clear_helper_retaddr(); =20 if (mop & MO_BSWAP) { @@ -1175,7 +1175,7 @@ static void do_st2_mmu(CPUArchState *env, abi_ptr add= r, uint16_t val, if (mop & MO_BSWAP) { val =3D bswap16(val); } - store_atom_2(env, ra, haddr, mop, val); + store_atom_2(env_cpu(env), ra, haddr, mop, val); clear_helper_retaddr(); } =20 @@ -1204,7 +1204,7 @@ static void do_st4_mmu(CPUArchState *env, abi_ptr add= r, uint32_t val, if (mop & MO_BSWAP) { val =3D bswap32(val); } - store_atom_4(env, ra, haddr, mop, val); + store_atom_4(env_cpu(env), ra, haddr, mop, val); clear_helper_retaddr(); } =20 @@ -1233,7 +1233,7 @@ static void do_st8_mmu(CPUArchState *env, abi_ptr add= r, uint64_t val, if (mop & MO_BSWAP) { val =3D bswap64(val); } - store_atom_8(env, ra, haddr, mop, val); + store_atom_8(env_cpu(env), ra, haddr, mop, val); clear_helper_retaddr(); } =20 @@ -1262,7 +1262,7 @@ static void do_st16_mmu(CPUArchState *env, abi_ptr ad= dr, Int128 val, if (mop & MO_BSWAP) { val =3D bswap128(val); } - store_atom_16(env, ra, haddr, mop, val); + store_atom_16(env_cpu(env), ra, haddr, mop, val); clear_helper_retaddr(); } =20 diff --git a/accel/tcg/ldst_atomicity.c.inc b/accel/tcg/ldst_atomicity.c.inc index 1b793e6935..1cf5b92166 100644 --- a/accel/tcg/ldst_atomicity.c.inc +++ b/accel/tcg/ldst_atomicity.c.inc @@ -26,7 +26,7 @@ * If the operation must be split into two operations to be * examined separately for atomicity, return -lg2. */ -static int required_atomicity(CPUArchState *env, uintptr_t p, MemOp memop) +static int required_atomicity(CPUState *cpu, uintptr_t p, MemOp memop) { MemOp atom =3D memop & MO_ATOM_MASK; MemOp size =3D memop & MO_SIZE; @@ -93,7 +93,7 @@ static int required_atomicity(CPUArchState *env, uintptr_= t p, MemOp memop) * host atomicity in order to avoid racing. This reduction * avoids looping with cpu_loop_exit_atomic. */ - if (cpu_in_serial_context(env_cpu(env))) { + if (cpu_in_serial_context(cpu)) { return MO_8; } return atmax; @@ -139,14 +139,14 @@ static inline uint64_t load_atomic8(void *pv) =20 /** * load_atomic8_or_exit: - * @env: cpu context + * @cpu: generic cpu state * @ra: host unwind address * @pv: host address * * Atomically load 8 aligned bytes from @pv. * If this is not possible, longjmp out to restart serially. */ -static uint64_t load_atomic8_or_exit(CPUArchState *env, uintptr_t ra, void= *pv) +static uint64_t load_atomic8_or_exit(CPUState *cpu, uintptr_t ra, void *pv) { if (HAVE_al8) { return load_atomic8(pv); @@ -168,19 +168,19 @@ static uint64_t load_atomic8_or_exit(CPUArchState *en= v, uintptr_t ra, void *pv) #endif =20 /* Ultimate fallback: re-execute in serial context. */ - cpu_loop_exit_atomic(env_cpu(env), ra); + cpu_loop_exit_atomic(cpu, ra); } =20 /** * load_atomic16_or_exit: - * @env: cpu context + * @cpu: generic cpu state * @ra: host unwind address * @pv: host address * * Atomically load 16 aligned bytes from @pv. * If this is not possible, longjmp out to restart serially. */ -static Int128 load_atomic16_or_exit(CPUArchState *env, uintptr_t ra, void = *pv) +static Int128 load_atomic16_or_exit(CPUState *cpu, uintptr_t ra, void *pv) { Int128 *p =3D __builtin_assume_aligned(pv, 16); =20 @@ -212,7 +212,7 @@ static Int128 load_atomic16_or_exit(CPUArchState *env, = uintptr_t ra, void *pv) } =20 /* Ultimate fallback: re-execute in serial context. */ - cpu_loop_exit_atomic(env_cpu(env), ra); + cpu_loop_exit_atomic(cpu, ra); } =20 /** @@ -263,7 +263,7 @@ static uint64_t load_atom_extract_al8x2(void *pv) =20 /** * load_atom_extract_al8_or_exit: - * @env: cpu context + * @cpu: generic cpu state * @ra: host unwind address * @pv: host address * @s: object size in bytes, @s <=3D 4. @@ -273,7 +273,7 @@ static uint64_t load_atom_extract_al8x2(void *pv) * 8-byte load and extract. * The value is returned in the low bits of a uint32_t. */ -static uint32_t load_atom_extract_al8_or_exit(CPUArchState *env, uintptr_t= ra, +static uint32_t load_atom_extract_al8_or_exit(CPUState *cpu, uintptr_t ra, void *pv, int s) { uintptr_t pi =3D (uintptr_t)pv; @@ -281,12 +281,12 @@ static uint32_t load_atom_extract_al8_or_exit(CPUArch= State *env, uintptr_t ra, int shr =3D (HOST_BIG_ENDIAN ? 8 - s - o : o) * 8; =20 pv =3D (void *)(pi & ~7); - return load_atomic8_or_exit(env, ra, pv) >> shr; + return load_atomic8_or_exit(cpu, ra, pv) >> shr; } =20 /** * load_atom_extract_al16_or_exit: - * @env: cpu context + * @cpu: generic cpu state * @ra: host unwind address * @p: host address * @s: object size in bytes, @s <=3D 8. @@ -299,7 +299,7 @@ static uint32_t load_atom_extract_al8_or_exit(CPUArchSt= ate *env, uintptr_t ra, * * If this is not possible, longjmp out to restart serially. */ -static uint64_t load_atom_extract_al16_or_exit(CPUArchState *env, uintptr_= t ra, +static uint64_t load_atom_extract_al16_or_exit(CPUState *cpu, uintptr_t ra, void *pv, int s) { uintptr_t pi =3D (uintptr_t)pv; @@ -312,7 +312,7 @@ static uint64_t load_atom_extract_al16_or_exit(CPUArchS= tate *env, uintptr_t ra, * Provoke SIGBUS if possible otherwise. */ pv =3D (void *)(pi & ~7); - r =3D load_atomic16_or_exit(env, ra, pv); + r =3D load_atomic16_or_exit(cpu, ra, pv); =20 r =3D int128_urshift(r, shr); return int128_getlo(r); @@ -394,7 +394,7 @@ static inline uint64_t load_atom_8_by_8_or_4(void *pv) * * Load 2 bytes from @p, honoring the atomicity of @memop. */ -static uint16_t load_atom_2(CPUArchState *env, uintptr_t ra, +static uint16_t load_atom_2(CPUState *cpu, uintptr_t ra, void *pv, MemOp memop) { uintptr_t pi =3D (uintptr_t)pv; @@ -410,7 +410,7 @@ static uint16_t load_atom_2(CPUArchState *env, uintptr_= t ra, } } =20 - atmax =3D required_atomicity(env, pi, memop); + atmax =3D required_atomicity(cpu, pi, memop); switch (atmax) { case MO_8: return lduw_he_p(pv); @@ -421,9 +421,9 @@ static uint16_t load_atom_2(CPUArchState *env, uintptr_= t ra, return load_atomic4(pv - 1) >> 8; } if ((pi & 15) !=3D 7) { - return load_atom_extract_al8_or_exit(env, ra, pv, 2); + return load_atom_extract_al8_or_exit(cpu, ra, pv, 2); } - return load_atom_extract_al16_or_exit(env, ra, pv, 2); + return load_atom_extract_al16_or_exit(cpu, ra, pv, 2); default: g_assert_not_reached(); } @@ -436,7 +436,7 @@ static uint16_t load_atom_2(CPUArchState *env, uintptr_= t ra, * * Load 4 bytes from @p, honoring the atomicity of @memop. */ -static uint32_t load_atom_4(CPUArchState *env, uintptr_t ra, +static uint32_t load_atom_4(CPUState *cpu, uintptr_t ra, void *pv, MemOp memop) { uintptr_t pi =3D (uintptr_t)pv; @@ -452,7 +452,7 @@ static uint32_t load_atom_4(CPUArchState *env, uintptr_= t ra, } } =20 - atmax =3D required_atomicity(env, pi, memop); + atmax =3D required_atomicity(cpu, pi, memop); switch (atmax) { case MO_8: case MO_16: @@ -466,9 +466,9 @@ static uint32_t load_atom_4(CPUArchState *env, uintptr_= t ra, return load_atom_extract_al4x2(pv); case MO_32: if (!(pi & 4)) { - return load_atom_extract_al8_or_exit(env, ra, pv, 4); + return load_atom_extract_al8_or_exit(cpu, ra, pv, 4); } - return load_atom_extract_al16_or_exit(env, ra, pv, 4); + return load_atom_extract_al16_or_exit(cpu, ra, pv, 4); default: g_assert_not_reached(); } @@ -481,7 +481,7 @@ static uint32_t load_atom_4(CPUArchState *env, uintptr_= t ra, * * Load 8 bytes from @p, honoring the atomicity of @memop. */ -static uint64_t load_atom_8(CPUArchState *env, uintptr_t ra, +static uint64_t load_atom_8(CPUState *cpu, uintptr_t ra, void *pv, MemOp memop) { uintptr_t pi =3D (uintptr_t)pv; @@ -498,12 +498,12 @@ static uint64_t load_atom_8(CPUArchState *env, uintpt= r_t ra, return load_atom_extract_al16_or_al8(pv, 8); } =20 - atmax =3D required_atomicity(env, pi, memop); + atmax =3D required_atomicity(cpu, pi, memop); if (atmax =3D=3D MO_64) { if (!HAVE_al8 && (pi & 7) =3D=3D 0) { - load_atomic8_or_exit(env, ra, pv); + load_atomic8_or_exit(cpu, ra, pv); } - return load_atom_extract_al16_or_exit(env, ra, pv, 8); + return load_atom_extract_al16_or_exit(cpu, ra, pv, 8); } if (HAVE_al8_fast) { return load_atom_extract_al8x2(pv); @@ -519,7 +519,7 @@ static uint64_t load_atom_8(CPUArchState *env, uintptr_= t ra, if (HAVE_al8) { return load_atom_extract_al8x2(pv); } - cpu_loop_exit_atomic(env_cpu(env), ra); + cpu_loop_exit_atomic(cpu, ra); default: g_assert_not_reached(); } @@ -532,7 +532,7 @@ static uint64_t load_atom_8(CPUArchState *env, uintptr_= t ra, * * Load 16 bytes from @p, honoring the atomicity of @memop. */ -static Int128 load_atom_16(CPUArchState *env, uintptr_t ra, +static Int128 load_atom_16(CPUState *cpu, uintptr_t ra, void *pv, MemOp memop) { uintptr_t pi =3D (uintptr_t)pv; @@ -548,7 +548,7 @@ static Int128 load_atom_16(CPUArchState *env, uintptr_t= ra, return atomic16_read_ro(pv); } =20 - atmax =3D required_atomicity(env, pi, memop); + atmax =3D required_atomicity(cpu, pi, memop); switch (atmax) { case MO_8: memcpy(&r, pv, 16); @@ -563,20 +563,20 @@ static Int128 load_atom_16(CPUArchState *env, uintptr= _t ra, break; case MO_64: if (!HAVE_al8) { - cpu_loop_exit_atomic(env_cpu(env), ra); + cpu_loop_exit_atomic(cpu, ra); } a =3D load_atomic8(pv); b =3D load_atomic8(pv + 8); break; case -MO_64: if (!HAVE_al8) { - cpu_loop_exit_atomic(env_cpu(env), ra); + cpu_loop_exit_atomic(cpu, ra); } a =3D load_atom_extract_al8x2(pv); b =3D load_atom_extract_al8x2(pv + 8); break; case MO_128: - return load_atomic16_or_exit(env, ra, pv); + return load_atomic16_or_exit(cpu, ra, pv); default: g_assert_not_reached(); } @@ -857,7 +857,7 @@ static uint64_t store_whole_le16(void *pv, int size, In= t128 val_le) * * Store 2 bytes to @p, honoring the atomicity of @memop. */ -static void store_atom_2(CPUArchState *env, uintptr_t ra, +static void store_atom_2(CPUState *cpu, uintptr_t ra, void *pv, MemOp memop, uint16_t val) { uintptr_t pi =3D (uintptr_t)pv; @@ -868,7 +868,7 @@ static void store_atom_2(CPUArchState *env, uintptr_t r= a, return; } =20 - atmax =3D required_atomicity(env, pi, memop); + atmax =3D required_atomicity(cpu, pi, memop); if (atmax =3D=3D MO_8) { stw_he_p(pv, val); return; @@ -897,7 +897,7 @@ static void store_atom_2(CPUArchState *env, uintptr_t r= a, g_assert_not_reached(); } =20 - cpu_loop_exit_atomic(env_cpu(env), ra); + cpu_loop_exit_atomic(cpu, ra); } =20 /** @@ -908,7 +908,7 @@ static void store_atom_2(CPUArchState *env, uintptr_t r= a, * * Store 4 bytes to @p, honoring the atomicity of @memop. */ -static void store_atom_4(CPUArchState *env, uintptr_t ra, +static void store_atom_4(CPUState *cpu, uintptr_t ra, void *pv, MemOp memop, uint32_t val) { uintptr_t pi =3D (uintptr_t)pv; @@ -919,7 +919,7 @@ static void store_atom_4(CPUArchState *env, uintptr_t r= a, return; } =20 - atmax =3D required_atomicity(env, pi, memop); + atmax =3D required_atomicity(cpu, pi, memop); switch (atmax) { case MO_8: stl_he_p(pv, val); @@ -961,7 +961,7 @@ static void store_atom_4(CPUArchState *env, uintptr_t r= a, return; } } - cpu_loop_exit_atomic(env_cpu(env), ra); + cpu_loop_exit_atomic(cpu, ra); default: g_assert_not_reached(); } @@ -975,7 +975,7 @@ static void store_atom_4(CPUArchState *env, uintptr_t r= a, * * Store 8 bytes to @p, honoring the atomicity of @memop. */ -static void store_atom_8(CPUArchState *env, uintptr_t ra, +static void store_atom_8(CPUState *cpu, uintptr_t ra, void *pv, MemOp memop, uint64_t val) { uintptr_t pi =3D (uintptr_t)pv; @@ -986,7 +986,7 @@ static void store_atom_8(CPUArchState *env, uintptr_t r= a, return; } =20 - atmax =3D required_atomicity(env, pi, memop); + atmax =3D required_atomicity(cpu, pi, memop); switch (atmax) { case MO_8: stq_he_p(pv, val); @@ -1029,7 +1029,7 @@ static void store_atom_8(CPUArchState *env, uintptr_t= ra, default: g_assert_not_reached(); } - cpu_loop_exit_atomic(env_cpu(env), ra); + cpu_loop_exit_atomic(cpu, ra); } =20 /** @@ -1040,7 +1040,7 @@ static void store_atom_8(CPUArchState *env, uintptr_t= ra, * * Store 16 bytes to @p, honoring the atomicity of @memop. */ -static void store_atom_16(CPUArchState *env, uintptr_t ra, +static void store_atom_16(CPUState *cpu, uintptr_t ra, void *pv, MemOp memop, Int128 val) { uintptr_t pi =3D (uintptr_t)pv; @@ -1052,7 +1052,7 @@ static void store_atom_16(CPUArchState *env, uintptr_= t ra, return; } =20 - atmax =3D required_atomicity(env, pi, memop); + atmax =3D required_atomicity(cpu, pi, memop); =20 a =3D HOST_BIG_ENDIAN ? int128_gethi(val) : int128_getlo(val); b =3D HOST_BIG_ENDIAN ? int128_getlo(val) : int128_gethi(val); @@ -1111,5 +1111,5 @@ static void store_atom_16(CPUArchState *env, uintptr_= t ra, default: g_assert_not_reached(); } - cpu_loop_exit_atomic(env_cpu(env), ra); + cpu_loop_exit_atomic(cpu, ra); } --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900648; cv=none; d=zohomail.com; s=zohoarc; b=P6BktoWM/zGPmCYDHX0QJ2Pq5Ms94Hf6XRSwKl/TTWpAr5xXoObAV9Z+/Peg6oGFKfKkWG94+TNqu0CoPw3q6qLh39KJX9w6Iis+FwJSA0kF/nWKY06YE4Hr/2Er2sshrSnl1ziQ997Ou2GjzOYV4nRV3BSdPinPLrLM/8ElekQ= ARC-Message-Signature: i=1; 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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900506; x=1695505306; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=s/Muc6q58T/I8t1/FsgbZeb0GzvuwJNmxxUL80PV3EI=; b=x9DbYvOopgiM4ZMQx2STZemBCbiuXhX6RjvuwAwbZMFzbsrHzty+/4FCEWxqQd3NLy mRb5BcGUGwR1debq1lO1MSYjl0Ly5NfB60czSajcjph6uy3vDGJRCcVOfHnIFsPLP++9 h4dyydOf8OHYfeHfARlDFW4GJL+jzgxZf3BJxQsQ6TN8WEakyulTH3alhrHaalKfFmmP bueLeEBHOMINrMShPmw6PLYmumTd7NmBgZdTeQmtR+wIJ5v2bGQzKF63UYnQvBpLvuhx Y8L78sZswEqlk3b4LUNjxp6QyyreJHicxEZ5XM3uSBh3OHSqjLRCsk+0+NJOG38LdbEZ DYqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900506; x=1695505306; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s/Muc6q58T/I8t1/FsgbZeb0GzvuwJNmxxUL80PV3EI=; b=kPQF4eqNqmjKoyY0XuYXBraYNVoL+M1cuc8l586Ax0OdksniFpZ6m0FhxVk0ezAQTM LCKPDGuebIPuTMjXjLkldVUZWQrqzNObz9grwZw6Jecf6pcuClw2QtTgWKvKnjZ2u7gB TzjByppFJgFzE6UlywN/fjF3KHD8ix+sRMauBAADkOTTMq6wC3LTdLfAhaprtVldFzI6 uiJy0uOViCY5DTcE6uxGHwxQz95DkZwSiNS+Nmktl/D4QFVMNF6x6jPFcGrX/zv06RNS /ybtA3pd+YIrT6aIfXIf5f1+Qxov5dszGtkL37j2WqLP4DVJnIU4RQyUcp4EtSCIJQdC xNhg== X-Gm-Message-State: AOJu0Yx4AjHAVnm4vuBc8vjUwSiA3DbJbsMy/4I42u0zwoPfJXK8et6S R3LCCRjvpK2he0bbrMZppDmX7OEZsrOM/6MtPjQ= X-Google-Smtp-Source: AGHT+IHu8O42J/rLDRCelearY9ZXyxcJ/2Z1bFtlsOAo1jqdTRIL4C8pKRVGERNv6uQlaLTLZk8QsQ== X-Received: by 2002:a05:6358:9907:b0:135:3f5c:9675 with SMTP id w7-20020a056358990700b001353f5c9675mr6568585rwa.19.1694900506323; Sat, 16 Sep 2023 14:41:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 21/39] accel/tcg: Remove env_tlb() Date: Sat, 16 Sep 2023 14:41:05 -0700 Message-Id: <20230916214123.525796-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900650305100003 Content-Type: text/plain; charset="utf-8" From: Anton Johansson The function is no longer used to access the TLB, and has been replaced by cpu->neg.tlb. Signed-off-by: Anton Johansson Message-Id: <20230912153428.17816-9-anjo@rev.ng> Reviewed-by: Richard Henderson [rth: Merge comment update patch] Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/exec/cpu-all.h | 11 ----------- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 2 +- 3 files changed, 2 insertions(+), 13 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index af9516654a..b37715c27d 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -451,15 +451,4 @@ static inline CPUState *env_cpu(CPUArchState *env) return (void *)env - sizeof(CPUState); } =20 -/** - * env_tlb(env) - * @env: The architecture environment - * - * Return the CPUTLB state associated with the environment. - */ -static inline CPUTLB *env_tlb(CPUArchState *env) -{ - return &env_cpu(env)->neg.tlb; -} - #endif /* CPU_ALL_H */ diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 06ea3c7652..69f2daf2c2 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1679,7 +1679,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, mask_type =3D (s->page_bits + s->tlb_dyn_max_bits > 32 ? TCG_TYPE_I64 : TCG_TYPE_I32); =20 - /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {tmp0,tmp1}. */ + /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {tmp0,tmp1}. */ QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 8); tcg_out_insn(s, 3314, LDP, TCG_REG_TMP0, TCG_REG_TMP1, TCG_AREG0, diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index b1d56362a7..a2f60106af 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1420,7 +1420,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ldst->addrlo_reg =3D addrlo; ldst->addrhi_reg =3D addrhi; =20 - /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ + /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */ QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 4); tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900581; cv=none; d=zohomail.com; s=zohoarc; b=IJLZJ/BDWmE3WuzIRg7fAQmfTouFy42n4214JmiFZNWUvsQgxWygCzkapMRINrEiZovxnaU7jOPUorsFtjkiH+8pnqTaPmlDCEfiGPzaQjhgMywSPiSG5ETmQqWAwgS4Xkg0q+tTiZ0sb/GLVL92kZbtlexd9urGZvFb8ZrtLnc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900581; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FLoclqklTYtdXUp0chTqVPswhpdSmhtE7w0yYQS8LHQ=; b=ZwNXletwrH/qqOFBsk18Vq/tcilLVPUXAj4JBtEctcQ+n2lXzagpLaclvaGs5tWvW/QSCqwXrdjkrGy4eHsALXzyxi96FbFla7l1Haaf9paWlLyB7+fjP9sQFpJwEoNyBLOhpL++kr2T3o1OxRAHpwJSJ338v6ECalpJ5+Uwltc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16949005814841001.1526209605323; Sat, 16 Sep 2023 14:43:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd3k-00068n-Lh; Sat, 16 Sep 2023 17:42:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd34-0005D3-93 for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:54 -0400 Received: from mail-oa1-x36.google.com ([2001:4860:4864:20::36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd30-0000Tr-2o for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:52 -0400 Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-1d5a8cb70d3so2049523fac.0 for ; Sat, 16 Sep 2023 14:41:48 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900507; x=1695505307; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FLoclqklTYtdXUp0chTqVPswhpdSmhtE7w0yYQS8LHQ=; b=aaRU2x9iYBA5HqJMglrCp9aodzWYXX5y6sz0VJlONQ9Uvpj8MZ1a3lQbLLiItDXYbs 172ybLxJXZx5LxpMRPvfjZ1o/f9qpNzpt1G0SOFNU7eD3ygSZRjD85S0vwiqXVXMt5+V kaXonznRGbTwDdU9cjkbuRUT79UbuzGS8vtHWRj8zBsWEbjTNVNkDtBLXzQb6bpbT54M Yv8eqKmXfLxZE+X/dAYc0220k0dFB5+O5ebfwfCixUjVsz0lVwSymsGtJ+NV+VZLUmoB 02dFO7XsrTLKnaNq3LeB6gUu0JrfU+SAN1pMNj5cDYN5Luk4tdI/E4qHyyEVvcnogH+s Oyvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900507; x=1695505307; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FLoclqklTYtdXUp0chTqVPswhpdSmhtE7w0yYQS8LHQ=; b=WfCzO5iDKMb6XW22jFNGiAZbTQRMh1C9g60ynj3VlJzc1KZ/9pA2UyaN2yogJZgETg +RwxxVmlin1bgnpJ55kXuLDWJLApcNs4Y1qz09NLmV5fTmGQFNC9D8+vBaBYltKPHnNO 2WyzRTvdBGdU5Pu1XqToAV47MbXFloB7yxsoUC38/2FGEVJpezTWw45oYwNrhrpCHsDY 2br4Cm5CeUhFLu0O1rkITqJZyZgEHH7FKMgFc+x2nfqUr3nW8TeUWQNto5UJNdC9y8FJ G+YAW1TH2e3hL/jkN2BdcdLUCCcH571XZeuc+QTKyH4CsSn4+fI/EOjsOh9rZ9ZvhHEf VSQw== X-Gm-Message-State: AOJu0YzplcCtDDNXl292xBijXA5kCmNAeDv+7mFArE1qYT16UCe6cuxf 1TF5NuXtHYbCx8IN6DkmAMrPQHpql0kIo+ySx88= X-Google-Smtp-Source: AGHT+IEla4jwYMvDE5J3rqDdo/yfG7fffsXpHNOtB2EW3IoW+M3j56IVYkGOCVciUSQ5B/dYGmz3Qw== X-Received: by 2002:a05:6870:178e:b0:1be:deef:748a with SMTP id r14-20020a056870178e00b001bedeef748amr6157423oae.50.1694900507185; Sat, 16 Sep 2023 14:41:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 22/39] accel/tcg: Unify user and softmmu do_[st|ld]*_mmu() Date: Sat, 16 Sep 2023 14:41:06 -0700 Message-Id: <20230916214123.525796-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900583238100003 Content-Type: text/plain; charset="utf-8" From: Anton Johansson The prototype of do_[st|ld]*_mmu() is unified between system- and user-mode allowing a large chunk of helper_[st|ld]*() and cpu_[st|ld]*() functions to be expressed in same manner between both modes. These functions will be moved to ldst_common.c.inc in a following commit. Signed-off-by: Anton Johansson Message-Id: <20230912153428.17816-11-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 16 ++-- accel/tcg/user-exec.c | 183 ++++++++++++++++++++++++------------------ 2 files changed, 117 insertions(+), 82 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 17fa7a514c..dc43839f87 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2922,18 +2922,24 @@ static void do_st_8(CPUState *cpu, MMULookupPageDat= a *p, uint64_t val, } } =20 -void helper_stb_mmu(CPUArchState *env, uint64_t addr, uint32_t val, - MemOpIdx oi, uintptr_t ra) +static void do_st1_mmu(CPUState *cpu, vaddr addr, uint8_t val, + MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; bool crosspage; =20 - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - crosspage =3D mmu_lookup(env_cpu(env), addr, oi, ra, MMU_DATA_STORE, &= l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); tcg_debug_assert(!crosspage); =20 - do_st_1(env_cpu(env), &l.page[0], val, l.mmu_idx, ra); + do_st_1(cpu, &l.page[0], val, l.mmu_idx, ra); +} + +void helper_stb_mmu(CPUArchState *env, uint64_t addr, uint32_t val, + MemOpIdx oi, uintptr_t ra) +{ + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); + do_st1_mmu(env_cpu(env), addr, val, oi, ra); } =20 static void do_st2_mmu(CPUState *cpu, vaddr addr, uint16_t val, diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index f9f5cd1770..a6593d0e0f 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -941,7 +941,7 @@ void page_reset_target_data(target_ulong start, target_= ulong last) { } =20 /* The softmmu versions of these helpers are in cputlb.c. */ =20 -static void *cpu_mmu_lookup(CPUArchState *env, vaddr addr, +static void *cpu_mmu_lookup(CPUState *cpu, vaddr addr, MemOp mop, uintptr_t ra, MMUAccessType type) { int a_bits =3D get_alignment_bits(mop); @@ -949,25 +949,24 @@ static void *cpu_mmu_lookup(CPUArchState *env, vaddr = addr, =20 /* Enforce guest required alignment. */ if (unlikely(addr & ((1 << a_bits) - 1))) { - cpu_loop_exit_sigbus(env_cpu(env), addr, type, ra); + cpu_loop_exit_sigbus(cpu, addr, type, ra); } =20 - ret =3D g2h(env_cpu(env), addr); + ret =3D g2h(cpu, addr); set_helper_retaddr(ra); return ret; } =20 #include "ldst_atomicity.c.inc" =20 -static uint8_t do_ld1_mmu(CPUArchState *env, abi_ptr addr, - MemOp mop, uintptr_t ra) +static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, + uintptr_t ra, MMUAccessType access_type) { void *haddr; uint8_t ret; =20 - tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_8); cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); + haddr =3D cpu_mmu_lookup(cpu, addr, get_memop(oi), ra, access_type); ret =3D ldub_p(haddr); clear_helper_retaddr(); return ret; @@ -976,33 +975,38 @@ static uint8_t do_ld1_mmu(CPUArchState *env, abi_ptr = addr, tcg_target_ulong helper_ldub_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { - return do_ld1_mmu(env, addr, get_memop(oi), ra); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); + return do_ld1_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); } =20 tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { - return (int8_t)do_ld1_mmu(env, addr, get_memop(oi), ra); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); + return (int8_t)do_ld1_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); } =20 uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - uint8_t ret =3D do_ld1_mmu(env, addr, get_memop(oi), ra); + uint8_t ret; + + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); + ret =3D do_ld1_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 -static uint16_t do_ld2_mmu(CPUArchState *env, abi_ptr addr, - MemOp mop, uintptr_t ra) +static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, + uintptr_t ra, MMUAccessType access_type) { void *haddr; uint16_t ret; + MemOp mop =3D get_memop(oi); =20 - tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_16); cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); - ret =3D load_atom_2(env_cpu(env), ra, haddr, mop); + haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); + ret =3D load_atom_2(cpu, ra, haddr, mop); clear_helper_retaddr(); =20 if (mop & MO_BSWAP) { @@ -1014,33 +1018,38 @@ static uint16_t do_ld2_mmu(CPUArchState *env, abi_p= tr addr, tcg_target_ulong helper_lduw_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { - return do_ld2_mmu(env, addr, get_memop(oi), ra); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); + return do_ld2_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); } =20 tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { - return (int16_t)do_ld2_mmu(env, addr, get_memop(oi), ra); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); + return (int16_t)do_ld2_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); } =20 uint16_t cpu_ldw_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - uint16_t ret =3D do_ld2_mmu(env, addr, get_memop(oi), ra); + uint16_t ret; + + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); + ret =3D do_ld2_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 -static uint32_t do_ld4_mmu(CPUArchState *env, abi_ptr addr, - MemOp mop, uintptr_t ra) +static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, + uintptr_t ra, MMUAccessType access_type) { void *haddr; uint32_t ret; + MemOp mop =3D get_memop(oi); =20 - tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_32); cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); - ret =3D load_atom_4(env_cpu(env), ra, haddr, mop); + haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); + ret =3D load_atom_4(cpu, ra, haddr, mop); clear_helper_retaddr(); =20 if (mop & MO_BSWAP) { @@ -1052,33 +1061,38 @@ static uint32_t do_ld4_mmu(CPUArchState *env, abi_p= tr addr, tcg_target_ulong helper_ldul_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { - return do_ld4_mmu(env, addr, get_memop(oi), ra); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); + return do_ld4_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); } =20 tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { - return (int32_t)do_ld4_mmu(env, addr, get_memop(oi), ra); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); + return (int32_t)do_ld4_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); } =20 uint32_t cpu_ldl_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - uint32_t ret =3D do_ld4_mmu(env, addr, get_memop(oi), ra); + uint32_t ret; + + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); + ret =3D do_ld4_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 -static uint64_t do_ld8_mmu(CPUArchState *env, abi_ptr addr, - MemOp mop, uintptr_t ra) +static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, + uintptr_t ra, MMUAccessType access_type) { void *haddr; uint64_t ret; + MemOp mop =3D get_memop(oi); =20 - tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_64); cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); - ret =3D load_atom_8(env_cpu(env), ra, haddr, mop); + haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, access_type); + ret =3D load_atom_8(cpu, ra, haddr, mop); clear_helper_retaddr(); =20 if (mop & MO_BSWAP) { @@ -1090,27 +1104,32 @@ static uint64_t do_ld8_mmu(CPUArchState *env, abi_p= tr addr, uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { - return do_ld8_mmu(env, addr, get_memop(oi), ra); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); + return do_ld8_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); } =20 uint64_t cpu_ldq_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - uint64_t ret =3D do_ld8_mmu(env, addr, get_memop(oi), ra); + uint64_t ret; + + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); + ret =3D do_ld8_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 -static Int128 do_ld16_mmu(CPUArchState *env, abi_ptr addr, - MemOp mop, uintptr_t ra) +static Int128 do_ld16_mmu(CPUState *cpu, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) { void *haddr; Int128 ret; + MemOp mop =3D get_memop(oi); =20 tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_128); cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_LOAD); - ret =3D load_atom_16(env_cpu(env), ra, haddr, mop); + haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_LOAD); + ret =3D load_atom_16(cpu, ra, haddr, mop); clear_helper_retaddr(); =20 if (mop & MO_BSWAP) { @@ -1122,7 +1141,7 @@ static Int128 do_ld16_mmu(CPUArchState *env, abi_ptr = addr, Int128 helper_ld16_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { - return do_ld16_mmu(env, addr, get_memop(oi), ra); + return do_ld16_mmu(env_cpu(env), addr, get_memop(oi), ra); } =20 Int128 helper_ld_i128(CPUArchState *env, uint64_t addr, MemOpIdx oi) @@ -1133,19 +1152,18 @@ Int128 helper_ld_i128(CPUArchState *env, uint64_t a= ddr, MemOpIdx oi) Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { - Int128 ret =3D do_ld16_mmu(env, addr, get_memop(oi), ra); + Int128 ret =3D do_ld16_mmu(env_cpu(env), addr, get_memop(oi), ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); return ret; } =20 -static void do_st1_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, - MemOp mop, uintptr_t ra) +static void do_st1_mmu(CPUState *cpu, vaddr addr, uint8_t val, + MemOpIdx oi, uintptr_t ra) { void *haddr; =20 - tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_8); cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE); + haddr =3D cpu_mmu_lookup(cpu, addr, get_memop(oi), ra, MMU_DATA_STORE); stb_p(haddr, val); clear_helper_retaddr(); } @@ -1153,134 +1171,145 @@ static void do_st1_mmu(CPUArchState *env, abi_ptr= addr, uint8_t val, void helper_stb_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { - do_st1_mmu(env, addr, val, get_memop(oi), ra); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); + do_st1_mmu(env_cpu(env), addr, val, oi, ra); } =20 void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, MemOpIdx oi, uintptr_t ra) { - do_st1_mmu(env, addr, val, get_memop(oi), ra); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); + do_st1_mmu(env_cpu(env), addr, val, oi, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -static void do_st2_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, - MemOp mop, uintptr_t ra) +static void do_st2_mmu(CPUState *cpu, vaddr addr, uint16_t val, + MemOpIdx oi, uintptr_t ra) { void *haddr; + MemOp mop =3D get_memop(oi); =20 - tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_16); cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE); + haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { val =3D bswap16(val); } - store_atom_2(env_cpu(env), ra, haddr, mop, val); + store_atom_2(cpu, ra, haddr, mop, val); clear_helper_retaddr(); } =20 void helper_stw_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { - do_st2_mmu(env, addr, val, get_memop(oi), ra); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); + do_st2_mmu(env_cpu(env), addr, val, oi, ra); } =20 void cpu_stw_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, MemOpIdx oi, uintptr_t ra) { - do_st2_mmu(env, addr, val, get_memop(oi), ra); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); + do_st2_mmu(env_cpu(env), addr, val, oi, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -static void do_st4_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, - MemOp mop, uintptr_t ra) +static void do_st4_mmu(CPUState *cpu, vaddr addr, uint32_t val, + MemOpIdx oi, uintptr_t ra) { void *haddr; + MemOp mop =3D get_memop(oi); =20 - tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_32); cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE); + haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { val =3D bswap32(val); } - store_atom_4(env_cpu(env), ra, haddr, mop, val); + store_atom_4(cpu, ra, haddr, mop, val); clear_helper_retaddr(); } =20 void helper_stl_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { - do_st4_mmu(env, addr, val, get_memop(oi), ra); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); + do_st4_mmu(env_cpu(env), addr, val, oi, ra); } =20 void cpu_stl_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { - do_st4_mmu(env, addr, val, get_memop(oi), ra); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); + do_st4_mmu(env_cpu(env), addr, val, oi, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -static void do_st8_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, - MemOp mop, uintptr_t ra) +static void do_st8_mmu(CPUState *cpu, vaddr addr, uint64_t val, + MemOpIdx oi, uintptr_t ra) { void *haddr; + MemOp mop =3D get_memop(oi); =20 - tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_64); cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE); + haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { val =3D bswap64(val); } - store_atom_8(env_cpu(env), ra, haddr, mop, val); + store_atom_8(cpu, ra, haddr, mop, val); clear_helper_retaddr(); } =20 void helper_stq_mmu(CPUArchState *env, uint64_t addr, uint64_t val, MemOpIdx oi, uintptr_t ra) { - do_st8_mmu(env, addr, val, get_memop(oi), ra); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); + do_st8_mmu(env_cpu(env), addr, val, oi, ra); } =20 void cpu_stq_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, MemOpIdx oi, uintptr_t ra) { - do_st8_mmu(env, addr, val, get_memop(oi), ra); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); + do_st8_mmu(env_cpu(env), addr, val, oi, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 -static void do_st16_mmu(CPUArchState *env, abi_ptr addr, Int128 val, - MemOp mop, uintptr_t ra) +static void do_st16_mmu(CPUState *cpu, vaddr addr, Int128 val, + MemOpIdx oi, uintptr_t ra) { void *haddr; + MemOpIdx mop =3D get_memop(oi); =20 - tcg_debug_assert((mop & MO_SIZE) =3D=3D MO_128); cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - haddr =3D cpu_mmu_lookup(env, addr, mop, ra, MMU_DATA_STORE); + haddr =3D cpu_mmu_lookup(cpu, addr, mop, ra, MMU_DATA_STORE); =20 if (mop & MO_BSWAP) { val =3D bswap128(val); } - store_atom_16(env_cpu(env), ra, haddr, mop, val); + store_atom_16(cpu, ra, haddr, mop, val); clear_helper_retaddr(); } =20 void helper_st16_mmu(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx oi, uintptr_t ra) { - do_st16_mmu(env, addr, val, get_memop(oi), ra); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); + do_st16_mmu(env_cpu(env), addr, val, oi, ra); } =20 void helper_st_i128(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx= oi) { + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); helper_st16_mmu(env, addr, val, oi, GETPC()); } =20 void cpu_st16_mmu(CPUArchState *env, abi_ptr addr, Int128 val, MemOpIdx oi, uintptr_t ra) { - do_st16_mmu(env, addr, val, get_memop(oi), ra); + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); + do_st16_mmu(env_cpu(env), addr, val, oi, ra); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } =20 @@ -1330,7 +1359,7 @@ uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr a= ddr, void *haddr; uint8_t ret; =20 - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_INST_FETCH); + haddr =3D cpu_mmu_lookup(env_cpu(env), addr, oi, ra, MMU_INST_FETCH); ret =3D ldub_p(haddr); clear_helper_retaddr(); return ret; @@ -1342,7 +1371,7 @@ uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr = addr, void *haddr; uint16_t ret; =20 - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_INST_FETCH); + haddr =3D cpu_mmu_lookup(env_cpu(env), addr, oi, ra, MMU_INST_FETCH); ret =3D lduw_p(haddr); clear_helper_retaddr(); if (get_memop(oi) & MO_BSWAP) { @@ -1357,7 +1386,7 @@ uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr = addr, void *haddr; uint32_t ret; =20 - haddr =3D cpu_mmu_lookup(env, addr, oi, ra, MMU_INST_FETCH); + haddr =3D cpu_mmu_lookup(env_cpu(env), addr, oi, ra, MMU_INST_FETCH); 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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900508; x=1695505308; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ALHZpOh+PiaOrsMQhqrSyZ+8WveMTk1XpR5VgM7Envk=; b=kXLWsn10c3sdc4A9yakc2klFIgVV4ob10ZvOpap9/t7UqjxV67Vvo0Qlf76lraX8Lr tMrab6tTZiWu821xnkS8wEjeGzmUBBplOI8birlfHgMFvayB5LzA1ptlleIBwqudX5aW 2E6OK6rBc9sJZ6e01foUwoyGkQHD62O0OE0vRTvRiZG+VGkf0jE7Nrvk9+nPEd9OiCmA 16bPgRYsP2OW2874jDapnu/AavVCCXk77nqvYmRYwvUMr5Lwej15MwmsrI5PXpfiY5rQ Jr4rA4wP7J+kqw9i7Vhtam+lNbEk/56gH8aszOrvhKdyDCy89Nlkt5aKznKs0G4MrEtz m6Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900508; x=1695505308; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ALHZpOh+PiaOrsMQhqrSyZ+8WveMTk1XpR5VgM7Envk=; b=IGIGtBCbu/3Pb9ugQk5VguQiz1knj/wKdYt+Jh3ElbIqBBurCbuQHYDIvkHHXtglyo Nzg5nye1IJYEac4+WwbAShJCumQNYneGZUW8X7OIcEABQRb6cskNk9Suv23vJzPaOxem pi1PmfJGSk3xO1m0A7/ND65kOWtxwAzBzvhyEuj8IxffiLzWe/HaEg0pO6Gbcp+/9Lrd i0vYarmgyXRe/52jqjUg4TFdF7X4HjZxx6Ev0OD5wGb0auMV234q4usZmx7vgsinCa21 XLgWtkOJZ11/5Mn2/0TlW4v799wPEN/B3CuoWV2WCij10FYlNYrgMIGyN6wUQBkrYCuw 4eag== X-Gm-Message-State: AOJu0Yz6PZ6n0xQURhkr5wLxeL399EwPxuNsVmWn173sfsk2ghFldisk R4mAZ9HfzvNykN8Sfnt6B+hsmUTfII7TuV/lVnA= X-Google-Smtp-Source: AGHT+IGtDZDmigyIV0YsJEgX1Xnk5Id4XkVxSFK2SsH9G00V3owWX6SnbQIgqAnV/tMrUP1dBl6z2Q== X-Received: by 2002:a05:6358:428c:b0:139:9fc3:eade with SMTP id s12-20020a056358428c00b001399fc3eademr5766333rwc.29.1694900508080; Sat, 16 Sep 2023 14:41:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 23/39] accel/tcg: move ld/st helpers to ldst_common.c.inc Date: Sat, 16 Sep 2023 14:41:07 -0700 Message-Id: <20230916214123.525796-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900806561100005 Content-Type: text/plain; charset="utf-8" From: Anton Johansson A large chunk of ld/st functions are moved from cputlb.c and user-exec.c to ldst_common.c.inc as their implementation is the same between both modes. Eventually, ldst_common.c.inc could be compiled into a separate target-specific compilation unit, and be linked in with the targets. Keeping CPUArchState usage out of cputlb.c (CPUArchState is primarily used to access the mmu index in these functions). Signed-off-by: Anton Johansson Message-Id: <20230912153428.17816-12-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 214 ---------------------------------- accel/tcg/user-exec.c | 193 ------------------------------- accel/tcg/ldst_common.c.inc | 225 ++++++++++++++++++++++++++++++++++++ 3 files changed, 225 insertions(+), 407 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index dc43839f87..c53f434c88 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2390,13 +2390,6 @@ static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, return do_ld_1(cpu, &l.page[0], l.mmu_idx, access_type, ra); } =20 -tcg_target_ulong helper_ldub_mmu(CPUArchState *env, uint64_t addr, - MemOpIdx oi, uintptr_t retaddr) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); - return do_ld1_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD); -} - static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { @@ -2422,13 +2415,6 @@ static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr= , MemOpIdx oi, return ret; } =20 -tcg_target_ulong helper_lduw_mmu(CPUArchState *env, uint64_t addr, - MemOpIdx oi, uintptr_t retaddr) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); - return do_ld2_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD); -} - static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { @@ -2450,13 +2436,6 @@ static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr= , MemOpIdx oi, return ret; } =20 -tcg_target_ulong helper_ldul_mmu(CPUArchState *env, uint64_t addr, - MemOpIdx oi, uintptr_t retaddr) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); - return do_ld4_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD); -} - static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { @@ -2478,36 +2457,6 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr= , MemOpIdx oi, return ret; } =20 -uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t addr, - MemOpIdx oi, uintptr_t retaddr) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); - return do_ld8_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD); -} - -/* - * Provide signed versions of the load routines as well. We can of course - * avoid this for 64-bit data, or for 32-bit data on 32-bit host. - */ - -tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, uint64_t addr, - MemOpIdx oi, uintptr_t retaddr) -{ - return (int8_t)helper_ldub_mmu(env, addr, oi, retaddr); -} - -tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, uint64_t addr, - MemOpIdx oi, uintptr_t retaddr) -{ - return (int16_t)helper_lduw_mmu(env, addr, oi, retaddr); -} - -tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, uint64_t addr, - MemOpIdx oi, uintptr_t retaddr) -{ - return (int32_t)helper_ldul_mmu(env, addr, oi, retaddr); -} - static Int128 do_ld16_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra) { @@ -2569,81 +2518,6 @@ static Int128 do_ld16_mmu(CPUState *cpu, vaddr addr, return ret; } =20 -Int128 helper_ld16_mmu(CPUArchState *env, uint64_t addr, - uint32_t oi, uintptr_t retaddr) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); - return do_ld16_mmu(env_cpu(env), addr, oi, retaddr); -} - -Int128 helper_ld_i128(CPUArchState *env, uint64_t addr, uint32_t oi) -{ - return helper_ld16_mmu(env, addr, oi, GETPC()); -} - -/* - * Load helpers for cpu_ldst.h. - */ - -static void plugin_load_cb(CPUArchState *env, abi_ptr addr, MemOpIdx oi) -{ - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); -} - -uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_= t ra) -{ - uint8_t ret; - - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_UB); - ret =3D do_ld1_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); - plugin_load_cb(env, addr, oi); - return ret; -} - -uint16_t cpu_ldw_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - uint16_t ret; - - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); - ret =3D do_ld2_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); - plugin_load_cb(env, addr, oi); - return ret; -} - -uint32_t cpu_ldl_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - uint32_t ret; - - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); - ret =3D do_ld4_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); - plugin_load_cb(env, addr, oi); - return ret; -} - -uint64_t cpu_ldq_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - uint64_t ret; - - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); - ret =3D do_ld8_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); - plugin_load_cb(env, addr, oi); - return ret; -} - -Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - Int128 ret; - - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); - ret =3D do_ld16_mmu(env_cpu(env), addr, oi, ra); - plugin_load_cb(env, addr, oi); - return ret; -} - /* * Store Helpers */ @@ -2935,13 +2809,6 @@ static void do_st1_mmu(CPUState *cpu, vaddr addr, ui= nt8_t val, do_st_1(cpu, &l.page[0], val, l.mmu_idx, ra); } =20 -void helper_stb_mmu(CPUArchState *env, uint64_t addr, uint32_t val, - MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); - do_st1_mmu(env_cpu(env), addr, val, oi, ra); -} - static void do_st2_mmu(CPUState *cpu, vaddr addr, uint16_t val, MemOpIdx oi, uintptr_t ra) { @@ -2965,13 +2832,6 @@ static void do_st2_mmu(CPUState *cpu, vaddr addr, ui= nt16_t val, do_st_1(cpu, &l.page[1], b, l.mmu_idx, ra); } =20 -void helper_stw_mmu(CPUArchState *env, uint64_t addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); - do_st2_mmu(env_cpu(env), addr, val, oi, retaddr); -} - static void do_st4_mmu(CPUState *cpu, vaddr addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { @@ -2993,13 +2853,6 @@ static void do_st4_mmu(CPUState *cpu, vaddr addr, ui= nt32_t val, (void) do_st_leN(cpu, &l.page[1], val, l.mmu_idx, l.memop, ra); } =20 -void helper_stl_mmu(CPUArchState *env, uint64_t addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); - do_st4_mmu(env_cpu(env), addr, val, oi, retaddr); -} - static void do_st8_mmu(CPUState *cpu, vaddr addr, uint64_t val, MemOpIdx oi, uintptr_t ra) { @@ -3021,13 +2874,6 @@ static void do_st8_mmu(CPUState *cpu, vaddr addr, ui= nt64_t val, (void) do_st_leN(cpu, &l.page[1], val, l.mmu_idx, l.memop, ra); } =20 -void helper_stq_mmu(CPUArchState *env, uint64_t addr, uint64_t val, - MemOpIdx oi, uintptr_t retaddr) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); - do_st8_mmu(env_cpu(env), addr, val, oi, retaddr); -} - static void do_st16_mmu(CPUState *cpu, vaddr addr, Int128 val, MemOpIdx oi, uintptr_t ra) { @@ -3086,66 +2932,6 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, I= nt128 val, } } =20 -void helper_st16_mmu(CPUArchState *env, uint64_t addr, Int128 val, - MemOpIdx oi, uintptr_t retaddr) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); - do_st16_mmu(env_cpu(env), addr, val, oi, retaddr); -} - -void helper_st_i128(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx= oi) -{ - helper_st16_mmu(env, addr, val, oi, GETPC()); -} - -/* - * Store Helpers for cpu_ldst.h - */ - -static void plugin_store_cb(CPUArchState *env, abi_ptr addr, MemOpIdx oi) -{ - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); -} - -void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, - MemOpIdx oi, uintptr_t retaddr) -{ - helper_stb_mmu(env, addr, val, oi, retaddr); - plugin_store_cb(env, addr, oi); -} - -void cpu_stw_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, - MemOpIdx oi, uintptr_t retaddr) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); - do_st2_mmu(env_cpu(env), addr, val, oi, retaddr); - plugin_store_cb(env, addr, oi); -} - -void cpu_stl_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, - MemOpIdx oi, uintptr_t retaddr) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); - do_st4_mmu(env_cpu(env), addr, val, oi, retaddr); - plugin_store_cb(env, addr, oi); -} - -void cpu_stq_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, - MemOpIdx oi, uintptr_t retaddr) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); - do_st8_mmu(env_cpu(env), addr, val, oi, retaddr); - plugin_store_cb(env, addr, oi); -} - -void cpu_st16_mmu(CPUArchState *env, abi_ptr addr, Int128 val, - MemOpIdx oi, uintptr_t retaddr) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); - do_st16_mmu(env_cpu(env), addr, val, oi, retaddr); - plugin_store_cb(env, addr, oi); -} - #include "ldst_common.c.inc" =20 /* diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index a6593d0e0f..17f9aff0cf 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -972,31 +972,6 @@ static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, M= emOpIdx oi, return ret; } =20 -tcg_target_ulong helper_ldub_mmu(CPUArchState *env, uint64_t addr, - MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); - return do_ld1_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); -} - -tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, uint64_t addr, - MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); - return (int8_t)do_ld1_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); -} - -uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - uint8_t ret; - - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); - ret =3D do_ld1_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return ret; -} - static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { @@ -1015,31 +990,6 @@ static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr,= MemOpIdx oi, return ret; } =20 -tcg_target_ulong helper_lduw_mmu(CPUArchState *env, uint64_t addr, - MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); - return do_ld2_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); -} - -tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, uint64_t addr, - MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); - return (int16_t)do_ld2_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); -} - -uint16_t cpu_ldw_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - uint16_t ret; - - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); - ret =3D do_ld2_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return ret; -} - static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { @@ -1058,31 +1008,6 @@ static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr= , MemOpIdx oi, return ret; } =20 -tcg_target_ulong helper_ldul_mmu(CPUArchState *env, uint64_t addr, - MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); - return do_ld4_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); -} - -tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, uint64_t addr, - MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); - return (int32_t)do_ld4_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); -} - -uint32_t cpu_ldl_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - uint32_t ret; - - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); - ret =3D do_ld4_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return ret; -} - static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { @@ -1101,24 +1026,6 @@ static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr= , MemOpIdx oi, return ret; } =20 -uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t addr, - MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); - return do_ld8_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); -} - -uint64_t cpu_ldq_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - uint64_t ret; - - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); - ret =3D do_ld8_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return ret; -} - static Int128 do_ld16_mmu(CPUState *cpu, abi_ptr addr, MemOpIdx oi, uintptr_t ra) { @@ -1138,25 +1045,6 @@ static Int128 do_ld16_mmu(CPUState *cpu, abi_ptr add= r, return ret; } =20 -Int128 helper_ld16_mmu(CPUArchState *env, uint64_t addr, - MemOpIdx oi, uintptr_t ra) -{ - return do_ld16_mmu(env_cpu(env), addr, get_memop(oi), ra); -} - -Int128 helper_ld_i128(CPUArchState *env, uint64_t addr, MemOpIdx oi) -{ - return helper_ld16_mmu(env, addr, oi, GETPC()); -} - -Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, - MemOpIdx oi, uintptr_t ra) -{ - Int128 ret =3D do_ld16_mmu(env_cpu(env), addr, get_memop(oi), ra); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); - return ret; -} - static void do_st1_mmu(CPUState *cpu, vaddr addr, uint8_t val, MemOpIdx oi, uintptr_t ra) { @@ -1168,21 +1056,6 @@ static void do_st1_mmu(CPUState *cpu, vaddr addr, ui= nt8_t val, clear_helper_retaddr(); } =20 -void helper_stb_mmu(CPUArchState *env, uint64_t addr, uint32_t val, - MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); - do_st1_mmu(env_cpu(env), addr, val, oi, ra); -} - -void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, - MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); - do_st1_mmu(env_cpu(env), addr, val, oi, ra); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); -} - static void do_st2_mmu(CPUState *cpu, vaddr addr, uint16_t val, MemOpIdx oi, uintptr_t ra) { @@ -1199,21 +1072,6 @@ static void do_st2_mmu(CPUState *cpu, vaddr addr, ui= nt16_t val, clear_helper_retaddr(); } =20 -void helper_stw_mmu(CPUArchState *env, uint64_t addr, uint32_t val, - MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); - do_st2_mmu(env_cpu(env), addr, val, oi, ra); -} - -void cpu_stw_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, - MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); - do_st2_mmu(env_cpu(env), addr, val, oi, ra); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); -} - static void do_st4_mmu(CPUState *cpu, vaddr addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { @@ -1230,21 +1088,6 @@ static void do_st4_mmu(CPUState *cpu, vaddr addr, ui= nt32_t val, clear_helper_retaddr(); } =20 -void helper_stl_mmu(CPUArchState *env, uint64_t addr, uint32_t val, - MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); - do_st4_mmu(env_cpu(env), addr, val, oi, ra); -} - -void cpu_stl_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, - MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); - do_st4_mmu(env_cpu(env), addr, val, oi, ra); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); -} - static void do_st8_mmu(CPUState *cpu, vaddr addr, uint64_t val, MemOpIdx oi, uintptr_t ra) { @@ -1261,21 +1104,6 @@ static void do_st8_mmu(CPUState *cpu, vaddr addr, ui= nt64_t val, clear_helper_retaddr(); } =20 -void helper_stq_mmu(CPUArchState *env, uint64_t addr, uint64_t val, - MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); - do_st8_mmu(env_cpu(env), addr, val, oi, ra); -} - -void cpu_stq_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, - MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); - do_st8_mmu(env_cpu(env), addr, val, oi, ra); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); -} - static void do_st16_mmu(CPUState *cpu, vaddr addr, Int128 val, MemOpIdx oi, uintptr_t ra) { @@ -1292,27 +1120,6 @@ static void do_st16_mmu(CPUState *cpu, vaddr addr, I= nt128 val, clear_helper_retaddr(); } =20 -void helper_st16_mmu(CPUArchState *env, uint64_t addr, Int128 val, - MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); - do_st16_mmu(env_cpu(env), addr, val, oi, ra); -} - -void helper_st_i128(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx= oi) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); - helper_st16_mmu(env, addr, val, oi, GETPC()); -} - -void cpu_st16_mmu(CPUArchState *env, abi_ptr addr, - Int128 val, MemOpIdx oi, uintptr_t ra) -{ - tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); - do_st16_mmu(env_cpu(env), addr, val, oi, ra); - qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); -} - uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr) { uint32_t ret; diff --git a/accel/tcg/ldst_common.c.inc b/accel/tcg/ldst_common.c.inc index 5f8144b33a..44833513fb 100644 --- a/accel/tcg/ldst_common.c.inc +++ b/accel/tcg/ldst_common.c.inc @@ -8,6 +8,231 @@ * This work is licensed under the terms of the GNU GPL, version 2 or late= r. * See the COPYING file in the top-level directory. */ +/* + * Load helpers for tcg-ldst.h + */ + +tcg_target_ulong helper_ldub_mmu(CPUArchState *env, uint64_t addr, + MemOpIdx oi, uintptr_t retaddr) +{ + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); + return do_ld1_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD); +} + +tcg_target_ulong helper_lduw_mmu(CPUArchState *env, uint64_t addr, + MemOpIdx oi, uintptr_t retaddr) +{ + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); + return do_ld2_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD); +} + +tcg_target_ulong helper_ldul_mmu(CPUArchState *env, uint64_t addr, + MemOpIdx oi, uintptr_t retaddr) +{ + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); + return do_ld4_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD); +} + +uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t addr, + MemOpIdx oi, uintptr_t retaddr) +{ + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); + return do_ld8_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD); +} + +/* + * Provide signed versions of the load routines as well. We can of course + * avoid this for 64-bit data, or for 32-bit data on 32-bit host. + */ + +tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, uint64_t addr, + MemOpIdx oi, uintptr_t retaddr) +{ + return (int8_t)helper_ldub_mmu(env, addr, oi, retaddr); +} + +tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, uint64_t addr, + MemOpIdx oi, uintptr_t retaddr) +{ + return (int16_t)helper_lduw_mmu(env, addr, oi, retaddr); +} + +tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, uint64_t addr, + MemOpIdx oi, uintptr_t retaddr) +{ + return (int32_t)helper_ldul_mmu(env, addr, oi, retaddr); +} + +Int128 helper_ld16_mmu(CPUArchState *env, uint64_t addr, + MemOpIdx oi, uintptr_t retaddr) +{ + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); + return do_ld16_mmu(env_cpu(env), addr, oi, retaddr); +} + +Int128 helper_ld_i128(CPUArchState *env, uint64_t addr, uint32_t oi) +{ + return helper_ld16_mmu(env, addr, oi, GETPC()); +} + +/* + * Store helpers for tcg-ldst.h + */ + +void helper_stb_mmu(CPUArchState *env, uint64_t addr, uint32_t val, + MemOpIdx oi, uintptr_t ra) +{ + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); + do_st1_mmu(env_cpu(env), addr, val, oi, ra); +} + +void helper_stw_mmu(CPUArchState *env, uint64_t addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr) +{ + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); + do_st2_mmu(env_cpu(env), addr, val, oi, retaddr); +} + +void helper_stl_mmu(CPUArchState *env, uint64_t addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr) +{ + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); + do_st4_mmu(env_cpu(env), addr, val, oi, retaddr); +} + +void helper_stq_mmu(CPUArchState *env, uint64_t addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr) +{ + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); + do_st8_mmu(env_cpu(env), addr, val, oi, retaddr); +} + +void helper_st16_mmu(CPUArchState *env, uint64_t addr, Int128 val, + MemOpIdx oi, uintptr_t retaddr) +{ + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); + do_st16_mmu(env_cpu(env), addr, val, oi, retaddr); +} + +void helper_st_i128(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx= oi) +{ + helper_st16_mmu(env, addr, val, oi, GETPC()); +} + +/* + * Load helpers for cpu_ldst.h + */ + +static void plugin_load_cb(CPUArchState *env, abi_ptr addr, MemOpIdx oi) +{ + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); +} + +uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_= t ra) +{ + uint8_t ret; + + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_UB); + ret =3D do_ld1_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); + plugin_load_cb(env, addr, oi); + return ret; +} + +uint16_t cpu_ldw_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + uint16_t ret; + + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); + ret =3D do_ld2_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); + plugin_load_cb(env, addr, oi); + return ret; +} + +uint32_t cpu_ldl_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + uint32_t ret; + + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); + ret =3D do_ld4_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); + plugin_load_cb(env, addr, oi); + return ret; +} + +uint64_t cpu_ldq_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + uint64_t ret; + + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); + ret =3D do_ld8_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); + plugin_load_cb(env, addr, oi); + return ret; +} + +Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + Int128 ret; + + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); + ret =3D do_ld16_mmu(env_cpu(env), addr, oi, ra); + plugin_load_cb(env, addr, oi); + return ret; +} + +/* + * Store helpers for cpu_ldst.h + */ + +static void plugin_store_cb(CPUArchState *env, abi_ptr addr, MemOpIdx oi) +{ + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + +void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, + MemOpIdx oi, uintptr_t retaddr) +{ + helper_stb_mmu(env, addr, val, oi, retaddr); + plugin_store_cb(env, addr, oi); +} + +void cpu_stw_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, + MemOpIdx oi, uintptr_t retaddr) +{ + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); + do_st2_mmu(env_cpu(env), addr, val, oi, retaddr); + plugin_store_cb(env, addr, oi); +} + +void cpu_stl_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, + MemOpIdx oi, uintptr_t retaddr) +{ + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); + do_st4_mmu(env_cpu(env), addr, val, oi, retaddr); + plugin_store_cb(env, addr, oi); +} + +void cpu_stq_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, + MemOpIdx oi, uintptr_t retaddr) +{ + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); + do_st8_mmu(env_cpu(env), addr, val, oi, retaddr); + plugin_store_cb(env, addr, oi); +} + +void cpu_st16_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t retaddr) +{ + tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); + do_st16_mmu(env_cpu(env), addr, val, oi, retaddr); + plugin_store_cb(env, addr, oi); +} + +/* + * Wrappers of the above + */ =20 uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, int mmu_idx, uintptr_t ra) --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900509; x=1695505309; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L57IbzicfHSbjnc3l70Se432e9VtllXVMLzXjtVZVVw=; b=nc7R5hiaFyZNwmvGTokFUd6P7B64GtaPdcVcmtF14YtTt8uxwOX87EBxdaAYlU77W8 oVof0RV/Omitz6e7EFKdsQus0Ui+Udk1o711DM0OEXqLkOUfmQHwYzB5Df31DrPXXCIa iBZ+F5MC8J8DiQy5j0teTUwhLln+l6u4kR9U00seylSypw4H142JldJBPlkHQrOSNJm1 QXMb9THPOs0Na13mT8YYy+PvSpebMf9XL/Cx8xzpNNX4IgLsX1jMw46fVY9wcA1JnU+C 3AIUPv7uO5Gxz23MWVrqj/Fomh4NcYt/OOnqCUHL4mdVROOwussqQ6hwVYZ38AOk1Slr NuaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900509; x=1695505309; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L57IbzicfHSbjnc3l70Se432e9VtllXVMLzXjtVZVVw=; b=kbykshWaZH6SCG/xblLnPszSgylQfcKH02iz4NPE60awwd97u6Z4GQspiIw8tyC/iv rNrXl7KYHu+lNMmNjkhZpEZ2jpzprIVILkMfY1+QfJEV7uG3EMo3j0rS/yBB9cgjdWsG Ww+BI42GB5DBOnNTBLEnQ1Dj/VTuwrXgv5nnyqfTBKnyS6zlyC3wJ5qOSSPK09BXy+F7 5I+p0GnxRByoHvzWNSIZTZCHSpv2Uu9Yq2vckpimvG5XyM7rm9IzN4E0UppsbFARorhi nFv/fqUj8ji5LnjX9xeQQXUF5kXFDYa184RePaWl9muCl3eIe+Za1kKCvwJawz9booyj iAsQ== X-Gm-Message-State: AOJu0YwQgLA+MfQrgIIzZMef9kKFd1HqE16SN6o1ZC/wlPnby/1YPKU0 c0baQFvxs+njq6r6bl9kgKAX+CBGKzb8/BWd8t0= X-Google-Smtp-Source: AGHT+IFp30Onhelc6IqAUDaYE+UV401FF4q0u5mYT4dBKWIYT33JRHjy4y/0pu8qMm+eLnH9P+/u4g== X-Received: by 2002:a05:6a00:14d5:b0:68a:5197:619f with SMTP id w21-20020a056a0014d500b0068a5197619fmr7130185pfu.31.1694900508859; Sat, 16 Sep 2023 14:41:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 24/39] exec: Make EXCP_FOO definitions target agnostic Date: Sat, 16 Sep 2023 14:41:08 -0700 Message-Id: <20230916214123.525796-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900678864100001 From: Philippe Mathieu-Daud=C3=A9 The EXCP_* definitions don't need to be target specific, move them to "exec/cpu-common.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Message-Id: <20230914185718.76241-2-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 7 ------- include/exec/cpu-common.h | 7 +++++++ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index b37715c27d..6af7944a38 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -26,13 +26,6 @@ #include "hw/core/cpu.h" #include "qemu/rcu.h" =20 -#define EXCP_INTERRUPT 0x10000 /* async interruption */ -#define EXCP_HLT 0x10001 /* hlt instruction reached */ -#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singl= estep */ -#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external eve= nt) */ -#define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another= */ -#define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ - /* some important defines: * * HOST_BIG_ENDIAN : whether the host cpu is big endian and diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 41788c0bdd..360b8298a4 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -7,6 +7,13 @@ #include "exec/hwaddr.h" #endif =20 +#define EXCP_INTERRUPT 0x10000 /* async interruption */ +#define EXCP_HLT 0x10001 /* hlt instruction reached */ +#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singl= estep */ +#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external eve= nt) */ +#define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another= */ +#define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ + /** * vaddr: * Type wide enough to contain any #target_ulong virtual address. --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900734; cv=none; d=zohomail.com; s=zohoarc; b=XkcUvI2AKgu9CZM5lTEuWqC2dlUaAoTSyGteJvMChU1h6Q/HlS/pBPe1QLJdJLhgUapm/aociU5ioZ0vIrCSpEQwI0QoGKIk+F6rrsHJsAFdtRVcsrb1oUHMRzhJFWhFZR0Pr5BocqTTj5jqRnXfM2uRcBWwFhUnfTOFCs44qDQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900734; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CzEQfKezgAt65j3pfMrIbIQsqXw7idxv2pPTvZtkhzo=; b=kNRo+Xb9gwTCJb47rTG4TzL07QXnIp7VPNe25r1ZFrHmESDqf7IrKW8IaGZAhUOZZXT97bYRkpR0fCfD0HWgSK+oGq+470gs5RZRzCC5sHQbAH3P3CXDVKEbJ/F6bOwxGX58v6yTgpLly4cEItEiwnMz0U+tNE5mq6GaCyDfYxo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900734017194.06409932080328; Sat, 16 Sep 2023 14:45:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd3m-0006OF-Bj; Sat, 16 Sep 2023 17:42:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd34-0005D2-8h for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:54 -0400 Received: from mail-ot1-x32b.google.com ([2607:f8b0:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd30-0000Ub-QN for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:53 -0400 Received: by mail-ot1-x32b.google.com with SMTP id 46e09a7af769-6c0d6fef60cso2057733a34.1 for ; Sat, 16 Sep 2023 14:41:50 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900510; x=1695505310; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CzEQfKezgAt65j3pfMrIbIQsqXw7idxv2pPTvZtkhzo=; b=isuMucsfou+3yVWs8gno62tE3kXr+Kj4Cfp299AsL1Q3ZQ3Z7Ck+zXpBlZiK/mfNA+ jWwjVgAii0eFkUICj9UE4nju12y/n5HICbDfjfEzaOQ9Z98uY1wgUXgJwQSCuXevNNWE MgGgo50CTAcsFlSNu4DfKCyUtDiFfcuNYSSSw5Ogq2WtoRcQ/inGAKrrz+6HHQETE1Sb fiRExmjfjTbKgY++IOeIdQWxYUU1dWVLypjgc9ES8vybZFdV58ESOxtH0OCPYUclo0KL crWZuyyFj332yjlOaALfDZi/hFxEE6xX+rC1AJarK2VL/Ke2tgmKurhKqF6L1wO4TrvY YamQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900510; x=1695505310; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CzEQfKezgAt65j3pfMrIbIQsqXw7idxv2pPTvZtkhzo=; b=WkSVYS7vd39i0EySQe8xZ+6yuf4NV8ed90Nrapv39xnoUQf49ztkRaSFdle7ETtnMv bu5uuoAFxwZUUB0qzFuikfp5wlR4W0Vf/MbcOLFX2YOrWQeGtwXfgGpS9/T7S0BrtC8J GvTMbAqzZ2m8+iD2fL3U7PEvYaoZ0V2bsdhSxJXGrK1m6CmE5kfvqQTYKNSB0FuTx7WO TGlXguFFvbBZRnWXa+OF+10pyVYo0vti2zOAc9zVs+WuLO4436kK1+IXtnQhGQuE/VGb Cc0ZUXlDlEAk8IZyhx+a07J+QiQnUSn0DLOjwqaRYEw6smqtprYrqqAMQaa+IIGPVdto Yuhw== X-Gm-Message-State: AOJu0YyQcX02i4fNnugVOIx4pVFJgpDId+mrNbXfToVN/zjmp7n74jlL FfzeSDIfq2YO4+xuHg9kRuwTchotXeiywyGJqfI= X-Google-Smtp-Source: AGHT+IEqE6yoplzJsdu1U2Q9ZjxCQXm76AW1c0/cwUeiDA4ptHEwdPIf1EwO9HWzphpr1f7zXstQTQ== X-Received: by 2002:a05:6358:430c:b0:129:d242:f782 with SMTP id r12-20020a056358430c00b00129d242f782mr6754060rwc.0.1694900509723; Sat, 16 Sep 2023 14:41:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 25/39] exec: Move cpu_loop_foo() target agnostic functions to 'cpu-common.h' Date: Sat, 16 Sep 2023 14:41:09 -0700 Message-Id: <20230916214123.525796-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900735088100011 From: Philippe Mathieu-Daud=C3=A9 While these functions are not TCG specific, they are not target specific. Move them to "exec/cpu-common.h" so their callers don't have to be tainted as target specific. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Message-Id: <20230914185718.76241-3-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/exec/cpu-common.h | 32 ++++++++++++++++++++++++++++++++ include/exec/exec-all.h | 30 ------------------------------ 2 files changed, 32 insertions(+), 30 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 360b8298a4..605b160a7e 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -173,4 +173,36 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, /* vl.c */ void list_cpus(void); =20 +#ifdef CONFIG_TCG +/** + * cpu_unwind_state_data: + * @cpu: the cpu context + * @host_pc: the host pc within the translation + * @data: output data + * + * Attempt to load the the unwind state for a host pc occurring in + * translated code. If @host_pc is not in translated code, the + * function returns false; otherwise @data is loaded. + * This is the same unwind info as given to restore_state_to_opc. + */ +bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *dat= a); + +/** + * cpu_restore_state: + * @cpu: the cpu context + * @host_pc: the host pc within the translation + * @return: true if state was restored, false otherwise + * + * Attempt to restore the state for a fault occurring in translated + * code. If @host_pc is not in translated code no state is + * restored and the function returns false. + */ +bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc); + +G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu); +G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); +#endif /* CONFIG_TCG */ +G_NORETURN void cpu_loop_exit(CPUState *cpu); +G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); + #endif /* CPU_COMMON_H */ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 2e4d337805..ee90ef122b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -27,36 +27,6 @@ #include "exec/translation-block.h" #include "qemu/clang-tsa.h" =20 -/** - * cpu_unwind_state_data: - * @cpu: the cpu context - * @host_pc: the host pc within the translation - * @data: output data - * - * Attempt to load the the unwind state for a host pc occurring in - * translated code. If @host_pc is not in translated code, the - * function returns false; otherwise @data is loaded. - * This is the same unwind info as given to restore_state_to_opc. - */ -bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *dat= a); - -/** - * cpu_restore_state: - * @cpu: the cpu context - * @host_pc: the host pc within the translation - * @return: true if state was restored, false otherwise - * - * Attempt to restore the state for a fault occurring in translated - * code. If @host_pc is not in translated code no state is - * restored and the function returns false. - */ -bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc); - -G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu); -G_NORETURN void cpu_loop_exit(CPUState *cpu); -G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); -G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); - /** * cpu_loop_exit_requested: * @cpu: The CPU state to be tested --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900764; cv=none; d=zohomail.com; s=zohoarc; b=a4gvG2u1trV+h5JqqbelT1UM0GzM03wWDK/i/YRoK1xwbeaCHm15cZLobFh/yEJa1Om63M5fPD48VHnL5oVNQfoUTRBG9JIBVdCSqgVWuBzaUJozDbnuAc6IGhwbzt4y0AbfMaaZcMH8OEhC+myby0xFoOZHJrtD+3LWdgbPG/A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900764; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UBIBs23OlZVEshNt40JGjGpTqqNUJKr0SLco/M6cVKg=; b=cSd/v91YLpI7mHYwDXMnv9jcINAJAV+CK4VYa8pwmwzYCEUlrGlQWhK/kx20MxZjO7lxrCMryJ+wkkmLxyO884NWw9u48EX2hHRwKpIXSYm/Cl6TdGGqQHyQY/OpDykvZ66ILGRywnhRRkz/zY7UVxn7PIQ+sKN04zOUUxqlnDk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900764308274.83575156976883; Sat, 16 Sep 2023 14:46:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd3j-0005l0-87; Sat, 16 Sep 2023 17:42:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd34-0005D4-92 for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:54 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd32-0000Uj-0L for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:53 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-68a3ced3ec6so3062526b3a.1 for ; Sat, 16 Sep 2023 14:41:51 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900510; x=1695505310; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UBIBs23OlZVEshNt40JGjGpTqqNUJKr0SLco/M6cVKg=; b=a402C2fXDvVtOTW3LQV9UXBO/knzU8tu9fGnTji47IjoaMcl44T9c8hddr+Tf6hyPl Z0HF823PttO4NQ7NQkyxYq8zXDs+NnuQGlp26dQSh88WIwm2GHXTkwglw4Bl6vbeRBXJ GjmEiybFkYAyShHf2PmcuEiGgqJEYNfr4wEd1GDk1TCNB8WmHqNs6QGiuPZbFybW7PES 93z4kuW2lRZhlhykhe42vTSH2SnH/I9v97HJ9iux/VDyBkkxfZb5SKszTpkyJrR0ZhY8 wK7oYXOUQmlhsVlvX+mXfHr70DXAnjvKuSMpOxCLl9H76RCFA836zIzieS9z201SDjY7 /2cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900510; x=1695505310; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UBIBs23OlZVEshNt40JGjGpTqqNUJKr0SLco/M6cVKg=; b=RHHO8TPdcu/VYgitV2JtHBGpXu/NERWhFLwc6qcLCvYucvClS/YDho+yRf3VmDHeDd x/w+0d+TvuVaG6fvfAnsFkvH09iZQjfLGplRiK/MjIWrU4F71iM/SXxVnZY9Pg0uE/+0 0TTFE/yUc0KnULIQsSis9EC3ohcY8NPpz8S7N8OXZoC2I3mTpbFX6LmCFU+pPa8ZMNdr 1bcPUwaoFfJoJaMwiePitY/RSw9drCrLR1wayZ/KBGiZdgrAkhvG+5epMBbJ89RTektF KxAIpgA1vDaZScld4EzdyaY6WlRwAocv5LUW5lOuzcAdRus+0lAssaNr0L0CsWgK0MhG zVag== X-Gm-Message-State: AOJu0YzWzdbJ/UCWfXkgkH2uEbsNVVojwqbO/LARU+96m4wMWJXek0F1 jxxLK4e+hDp2EoB6suOgbb70kGbnxhaEKH44T8Q= X-Google-Smtp-Source: AGHT+IFazrvAFowfXeuQDBN+zk4s/Xm6dg3EaRnd2urjsbMAHDw62sRXA9vnLY2AXFMi7LUBdZtG4g== X-Received: by 2002:a05:6a20:7d9a:b0:157:64e4:4260 with SMTP id v26-20020a056a207d9a00b0015764e44260mr216072pzj.9.1694900510633; Sat, 16 Sep 2023 14:41:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 26/39] accel/tcg: Restrict dump_exec_info() declaration Date: Sat, 16 Sep 2023 14:41:10 -0700 Message-Id: <20230916214123.525796-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900765588100011 From: Philippe Mathieu-Daud=C3=A9 In commit 00c9a5c2c3 ("accel/tcg: Restrict 'qapi-commands-machine.h' to system emulation") we moved the definition to accel/tcg/ which is where this function is called. No need to expose it outside. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Message-Id: <20230914185718.76241-4-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/internal.h | 2 ++ include/exec/cpu-all.h | 5 ----- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h index e8cbbde581..cd6b9eb7f0 100644 --- a/accel/tcg/internal.h +++ b/accel/tcg/internal.h @@ -102,6 +102,8 @@ static inline bool cpu_in_serial_context(CPUState *cs) extern int64_t max_delay; extern int64_t max_advance; =20 +void dump_exec_info(GString *buf); + extern bool one_insn_per_tb; =20 /** diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 6af7944a38..8d262d141e 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -406,11 +406,6 @@ static inline bool tlb_hit(uint64_t tlb_addr, vaddr ad= dr) return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); } =20 -#ifdef CONFIG_TCG -/* accel/tcg/translate-all.c */ -void dump_exec_info(GString *buf); -#endif /* CONFIG_TCG */ - #endif /* !CONFIG_USER_ONLY */ =20 /* accel/tcg/cpu-exec.c */ --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900699; cv=none; d=zohomail.com; s=zohoarc; b=alpyR6CCWbNOTUDjI4nFEgCn8ZYfNJrKIgkev6tJNECcs6oCyqwUSkEsgQm3jGDtAM+mqnvZCMmZu5ewLlx9o7r+0sEYtYc2EZQkB/MvQzYcHFJu7m+F9zW4RoJoiyVr0fRYrpes7jnugjtO9iNFQaOGJcOCORZcj7TEhtDSh3o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900699; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FrUTbAqq5Rh4+S6dQa7CskGzlO2N+g4ynCNykCd/g2Q=; b=VotMcn6mD/dM/WA8PS27uaERc6JtXv0jt3IEJ7lS8iRCk1O6z3meWyMfpuj2bbveK/BZ/lWq5UNe/6ZUyjh7wIV0mztv+v1I8suyrOIiGfY269WotmulcA57x+eyv3QN/mArHCx2UkFNLowE0dJjrWXFttBWaLbD+xibSv9Xo5M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900699448738.6653956890668; Sat, 16 Sep 2023 14:44:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd3q-0006ui-R8; Sat, 16 Sep 2023 17:42:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd37-0005Dp-JY for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:57 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd32-0000Ur-JH for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:57 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-68cbbff84f6so3074847b3a.1 for ; Sat, 16 Sep 2023 14:41:52 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900511; x=1695505311; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FrUTbAqq5Rh4+S6dQa7CskGzlO2N+g4ynCNykCd/g2Q=; b=YvzGujSWH9m1mPq1d6wTquDp8a9Jy+Usp6wJcDRbhmFaEegu1iRGbc3JQnOqMgECVc XiJp/9loeTk9YySqzIelb8fvLR0JcrQRkwPgsxAVQgUIJH21JO++1WuEXZ6+ZYdpxbWW T+uZGPy+BQKOAqE6R6ZW33gctzsBT+75HLKJgM2OtbtSFr58awi7OiGH84bbfN19ciWz TP91OdSG/5arOoGM58Nevl5n4xM3VXxbXuTu6Ujkvf93YLUalQfskOK4cZXkaPqwgbOH t359JSXDArx5PgDKpIYwTf8ZzMc8WVKhXopjmUDAJNeBalUAF+FSHf+fw1DeakrwFtx2 P7DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900511; x=1695505311; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FrUTbAqq5Rh4+S6dQa7CskGzlO2N+g4ynCNykCd/g2Q=; b=hbztMprcQ7pGDzPe0xodk7WqtfyNyN+YIZ6dheG7cX30QfjeJG/optaq2HxFm7Itx6 UKwgAW1sgUc3HTloiLuTpdaY/FIZYdDP/JWSpRmCNW4lkFBWDQIzcL+7/T7Or9X0DJdH KF9SxTK/xqGKagjysYkrSLfpk7+wekg6cNH1xUa7T7rEmlnljOqhuaM8A47+zq93Q5um npOddNbicRIvRplrJpSLbfzzCfiV5c6s32NBGUI7ZbnR8VbfRH3fxhruXNRXBLbXHOE7 g7tkr9iib/eFvlUxm+MhWsoDrHU6Yo/Uk3wRwW1d3BtuIUMHbKVaT5eXCNBiOfmhPiYp HkIA== X-Gm-Message-State: AOJu0YxrF8b4GGIeyRkgTbs+4IhJQQ4XSQ2enDxj4kDuheUYXjoMeNu6 l2URLgWidfpfAdXboSVOQzaX+fyEXC3MNAw9NSA= X-Google-Smtp-Source: AGHT+IFHuJeXBnIA13HT1F83cM5mf7IoThrDjCVyXKl2fvTWv0Y05qqpGr4DYmu7oNiDw2g3hlwn0Q== X-Received: by 2002:a05:6a20:4413:b0:13f:13cb:bc50 with SMTP id ce19-20020a056a20441300b0013f13cbbc50mr7892023pzb.25.1694900511377; Sat, 16 Sep 2023 14:41:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 27/39] accel: Make accel-blocker.o target agnostic Date: Sat, 16 Sep 2023 14:41:11 -0700 Message-Id: <20230916214123.525796-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900700875100005 From: Philippe Mathieu-Daud=C3=A9 accel-blocker.c is not target specific, move it to system_ss[]. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Message-Id: <20230914185718.76241-5-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/meson.build | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/accel/meson.build b/accel/meson.build index 638a9a03ba..76f3cbc530 100644 --- a/accel/meson.build +++ b/accel/meson.build @@ -1,5 +1,5 @@ -specific_ss.add(files('accel-common.c', 'accel-blocker.c')) -system_ss.add(files('accel-softmmu.c')) +specific_ss.add(files('accel-common.c')) +system_ss.add(files('accel-softmmu.c', 'accel-blocker.c')) user_ss.add(files('accel-user.c')) =20 subdir('tcg') --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900730; cv=none; d=zohomail.com; s=zohoarc; b=nS/lmTRAzmTIWAwxZ7tacOxbJU+QGqsXj1PajVOFoKPjvTJMtc4odS+dHzLr7+W4mXWLs9cyl49ZobEPSQlbtJY714Rh3oGIpv2rYL8sM12JP8xhxs8BJOb92SJSLeyf3pxsg9yhbNJXyMIZBckjpgY1U5t/mVtioLL7VQVrp7k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900730; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0DUsW3Z1l6kI6dnJslOCZY121JffUsDAYF90PScLnzY=; b=f+rnaybpsFMvtCTD3GSijG2MLWD6nuBiRKT9jXQYCET+9F1jWgVxcFZK+261+zW4mYZ9EuM4/6izcL3fRjJTb52Vo/p2qMhFqWd5qduLzg7FbImyXnHB68E/S0liCsZ0lWuweswh91F7rVcf0Gv982za8z3h8lPoKXJB4vPYVjk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16949007301934.787873988293086; Sat, 16 Sep 2023 14:45:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd3k-00066N-DP; Sat, 16 Sep 2023 17:42:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd35-0005DZ-Vn for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:56 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd34-0000V6-1g for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:55 -0400 Received: by mail-pg1-x52b.google.com with SMTP id 41be03b00d2f7-564b6276941so2688922a12.3 for ; Sat, 16 Sep 2023 14:41:53 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900512; x=1695505312; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0DUsW3Z1l6kI6dnJslOCZY121JffUsDAYF90PScLnzY=; b=uhsPD95JHTksHy0DLfDZ/XyRJmkBqnSvQ+EUYdiPCcHbdELfOz0XqGvNgwAxdzLnID kgz3SqymcHLmfw62V0liHTNlwkjUV5+GMc78ftPsvP3xO2IMcA5yPecTybKO1NPRn+SK uU33mi7tj1UaIZMRtkvhx3IHViakCkXpMS5IUQVpmH/hDODE2Gvl3uuYlj81AMH7KE36 DBoy3Bbjp4ODG1C6Dx4RCj6qbT66i7oMThjuDbiQyEGN/kXA+WV5PhTRVTvWGurgII0y +GscDfz8gpKqitC2dCtq8g/9h3kC7tY/FzH9FXuJFutZsKfZu6sam4rid+oxgFRr9808 f1dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900512; x=1695505312; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0DUsW3Z1l6kI6dnJslOCZY121JffUsDAYF90PScLnzY=; b=UQzJB8njWUoG9G0yQ3z83sF7mKSoc3SoA8zj0B7qNQXzTN9gh+vfPIYqpDPRypT5jA EK8jMXpBeH+KuU+9RHQHdcjNCPBheJ4rg89BYGQUykNtxDrR2m4E9Ezr6dwC5TdBsub8 IzkvYXdpIH3eqAZdr/Tf8hJLL0XbL55ekY1Y/G7p+vKXTjRYcv2LoLTh+lq9RtVjBGIV t6TU4PofanIaUPJkili1cZBGP5uqTF7iN7VauJuiOPbokk6DNkW00g7Q+v20TbS4lHnc Mn1qH85pWNuSMrCtz9LVsbSj6hz3VV9QI7yGtAnHOAh6DseWlH7BVzGebXDuh5tvasgE AvHg== X-Gm-Message-State: AOJu0Yx6SESQXnVBu9FNg1m3GtzCKezBlOLH0OLRUyHq/Zc4A4nhTK4o 1KpfGUhJQNszkYoxEjpJJmvuuqQ8OCnNDbwuCD0= X-Google-Smtp-Source: AGHT+IH6pAw+2ERuJixeICy7lX0U58F6kdjrYudhRL6K2lzLJMYtnuckRbq55JtiGGEDiMvWs7DksA== X-Received: by 2002:a05:6a20:f384:b0:14c:c393:692 with SMTP id qr4-20020a056a20f38400b0014cc3930692mr5850011pzb.7.1694900512245; Sat, 16 Sep 2023 14:41:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 28/39] accel: Rename accel-common.c -> accel-target.c Date: Sat, 16 Sep 2023 14:41:12 -0700 Message-Id: <20230916214123.525796-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900731009100003 From: Philippe Mathieu-Daud=C3=A9 We use the '-common.c' suffix for target agnostic units. This file is target specific, rename it using the '-target' suffix. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Message-Id: <20230914185718.76241-6-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/{accel-common.c =3D> accel-target.c} | 0 accel/meson.build | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename accel/{accel-common.c =3D> accel-target.c} (100%) diff --git a/accel/accel-common.c b/accel/accel-target.c similarity index 100% rename from accel/accel-common.c rename to accel/accel-target.c diff --git a/accel/meson.build b/accel/meson.build index 76f3cbc530..fda3157a6e 100644 --- a/accel/meson.build +++ b/accel/meson.build @@ -1,4 +1,4 @@ -specific_ss.add(files('accel-common.c')) +specific_ss.add(files('accel-target.c')) system_ss.add(files('accel-softmmu.c', 'accel-blocker.c')) user_ss.add(files('accel-user.c')) =20 --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900635; cv=none; d=zohomail.com; s=zohoarc; b=EcBRPHiWJFHYI6EYF1alp7ovELn/OeX0Sqgbb2cvf1cCYYZjJCnIlYMfFCdiqTUwmdBf2i4BtLBQpt6rNGIPNN5kkEOFDnQjb/dYDr6OK8CTsffmOYfZ2+yB10/S7WTdVAVjGX8ToZqbbN88ow1CX1iy2KJVQJocRX8dpnngokI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900635; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HHBE2N1zmj6JeCBieiTBjGikB9utE52NnbMbL9slySg=; b=M7Vy/GVwn/MJw++ASnIw8KXdnE8x/zMpB/zIVyCha85NabVWkHlFYESA29WA0yqGWArAd7iN66ugRzDqzZKPh7qC3EX9pKAEBPInZIEej6F1fVK9pKPomPSsHng/GjTJfguUJ9OI+SBADzrnD3UQmVpBecr5fn2VPiIW/BMnPWM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900635543266.51116924455084; Sat, 16 Sep 2023 14:43:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd3o-0006iU-GS; Sat, 16 Sep 2023 17:42:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd37-0005Do-JL for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:57 -0400 Received: from mail-oo1-xc2e.google.com ([2607:f8b0:4864:20::c2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd34-0000VD-Hq for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:56 -0400 Received: by mail-oo1-xc2e.google.com with SMTP id 006d021491bc7-57355a16941so2076379eaf.2 for ; Sat, 16 Sep 2023 14:41:54 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900513; x=1695505313; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HHBE2N1zmj6JeCBieiTBjGikB9utE52NnbMbL9slySg=; b=XmZJ97sNMHx5KuGy6wnVFiDjrk65q4HGmAX7bxH/iUumSsujQ9FC276QMybyeeVB1E chvZWDhGC3JcWMjbuEmu27OL3O2pAd61CLTbUx06X02xyVaFVfTXug9EJSi34i2fwpzA JTciEX3Rs+2Q1oqTzD1hf8yYLwRQadAFJJEfXGvDPNqNv9YQNRIrAyx1NCWnE+vRZXLC QfPt4aI6HyRva+86wA7J/pDah+mhN3+l6fnoQyyo9CiAknpahzj4rWIGpMtUCikCtAL+ 72CgcP/e837roooBKBM20IAWBjmbCW0C6WgyLQSy9ryAzs2hmos2/t0QYXcSSns0c1mV Vpwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900513; x=1695505313; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HHBE2N1zmj6JeCBieiTBjGikB9utE52NnbMbL9slySg=; b=XkqAGSh/TLjc+LaNYkiyERvchE62qHIIAwPuLr4lLnCyXi8htaHQD1FCpbdG/dEral H3uzunG7jTsr7Bv9czBpBbvfrHJ7P70Qm+Qm2lDcPdDS2pS+SIGRlqOm9mLlRzBuz39Z ukRizhSJIE0Eur97p0PVDe5h1an9IGRfJaqd5qb6RpHIXN2fzbGHM7SaB2U2mL7YbLQf VgQcWd6zhQjD9BNUq2HVHpK8Mvw7ht4xIYJNXfZ65p1FI4befhXTEb86GeklX1BUdC9m wN0HGxuPjv6faqRbtRptkQMmO3JCq39ZjAePc68F8lADCLm2o9X8dLE6wuTY7BDwv3fk NU7Q== X-Gm-Message-State: AOJu0YzMGqoIWt5EIEfUXUz9wni6z08JnmsIAsvM012HJvN0Pj8oIgGx N1h9pH75+pptvKPrkRu65+U8jCF1o//fzreoKhg= X-Google-Smtp-Source: AGHT+IF5kUHx+KRIDXplYx9ID/+MIVZ+7PBuDy8F96q3q0aWdn4h6+eeyjsF4SKsdG9vLQoERk45wA== X-Received: by 2002:a05:6358:93a7:b0:142:fd2b:d165 with SMTP id h39-20020a05635893a700b00142fd2bd165mr6816545rwb.13.1694900513017; Sat, 16 Sep 2023 14:41:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 29/39] exec: Rename cpu.c -> cpu-target.c Date: Sat, 16 Sep 2023 14:41:13 -0700 Message-Id: <20230916214123.525796-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2e; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900636087100003 From: Philippe Mathieu-Daud=C3=A9 We have exec/cpu code split in 2 files for target agnostic ("common") and specific. Rename 'cpu.c' which is target specific using the '-target' suffix. Update MAINTAINERS. Remove the 's from 'cpus-common.c' to match the API cpu_foo() functions. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Message-Id: <20230914185718.76241-7-philmd@linaro.org> Signed-off-by: Richard Henderson --- MAINTAINERS | 4 ++-- meson.build | 4 ++-- cpus-common.c =3D> cpu-common.c | 0 cpu.c =3D> cpu-target.c | 0 4 files changed, 4 insertions(+), 4 deletions(-) rename cpus-common.c =3D> cpu-common.c (100%) rename cpu.c =3D> cpu-target.c (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 00562f924f..12261d8eaf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -139,7 +139,8 @@ R: Paolo Bonzini S: Maintained F: softmmu/cpus.c F: softmmu/watchpoint.c -F: cpus-common.c +F: cpu-common.c +F: cpu-target.c F: page-vary.c F: page-vary-common.c F: accel/tcg/ @@ -1772,7 +1773,6 @@ M: Marcel Apfelbaum R: Philippe Mathieu-Daud=C3=A9 R: Yanan Wang S: Supported -F: cpu.c F: hw/core/cpu.c F: hw/core/machine-qmp-cmds.c F: hw/core/machine.c diff --git a/meson.build b/meson.build index 5150a74831..3e86a6cebf 100644 --- a/meson.build +++ b/meson.build @@ -3416,8 +3416,8 @@ if have_block system_ss.add(when: 'CONFIG_WIN32', if_true: [files('os-win32.c')]) endif =20 -common_ss.add(files('cpus-common.c')) -specific_ss.add(files('cpu.c')) +common_ss.add(files('cpu-common.c')) +specific_ss.add(files('cpu-target.c')) =20 subdir('softmmu') =20 diff --git a/cpus-common.c b/cpu-common.c similarity index 100% rename from cpus-common.c rename to cpu-common.c diff --git a/cpu.c b/cpu-target.c similarity index 100% rename from cpu.c rename to cpu-target.c --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900576; cv=none; d=zohomail.com; s=zohoarc; b=Dbti7S5QAuoqwHmR7J0CJqpu3rWYiwrq+Q5siXayxR4WVrqrtE9fS2aE2Vc3s4hJdhId3O5gdXJKcM3rDUGDMoGMK8gNJ3SmODGc3BA8g8mOuOHXdrS4rnrJfdDcSHxdhHsmrLtWDHDiLHgGoN9BXlVFaU2tAIuD+ms7B/OOyEE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900576; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=50A87DiNBui2Aabq1+Nxd0earov0nrUH3Txq9Zcvjq0=; b=oDdWU9V85xDuXT4+mb5CVHTpvX4d7Nl2Fs1gOhqAXfyYr4pVnh8lBYtkyIK52cPFR6BOJBVsBtaSVBsOEKKX46MBexkK1gnmrXQ53+kGK1rKSjMI6OjLRwk+cnbu33R9ZVmSGBy7UuR8cJXsUfMNDDjBWI2qt004ZBUa8tqS1bY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169490057686914.750700113919834; Sat, 16 Sep 2023 14:42:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd3V-0005VM-3f; Sat, 16 Sep 2023 17:42:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd37-0005Dn-Is for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:57 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd35-0000VT-AO for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:56 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-68fb98745c1so2628339b3a.1 for ; Sat, 16 Sep 2023 14:41:54 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900514; x=1695505314; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=50A87DiNBui2Aabq1+Nxd0earov0nrUH3Txq9Zcvjq0=; b=PT4MrCq9UdpKjdeukrDd3wyIXbkbiqieGHplQzMBn7weCWL34jRZJMAs4KaO0sjs0b z456e94v3hS6mxbjzBdShGbj4ECc4f1r13Wy1jLu+Zqt5a2g/Kp0kmdoWKpNs5sEkf8/ jjtDhdsk8GjONe5eScSAPW5cUfaWopgEWVGfFE0E4tZn3qVG+NDp98dSxBxZf+i/EcFo xytgigmEZir9VjAI9E8c/gyEu0mgZyMGUQTO0m51o9+yGbfslB7rDJhpfGYIj9hqSfw/ cx6VOTZhqnXiO9bfpvxoKd5rbFWIV7xvK2SwZEbaLIHv16KPSZAI5gDg7E7lwJIP+dBZ JGmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900514; x=1695505314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=50A87DiNBui2Aabq1+Nxd0earov0nrUH3Txq9Zcvjq0=; b=ajD/NHzmha+F2xXjQugZzWSIcOYo8HIms3UCSXHoC6huXDQ/3qG4s10q9rAS6n3SbX EUs0vgwHw+DU114K4CWUZwufZ7z/hrHcg7JH27T3m6o+eAOdcQCvnBIfVJCRH159FoAu Gv4V+j9ofvOmRIM65y0z6kCtoMO94UzGVy1La3RHr2q5fK9HCiWFJQ8CyJowisuX7Tgf 5axs8igOg8g9mLRY5mEICV4zExf0KSQK/8eTmqf5GIARJsPoPPww676P8cLXlPDFnhO9 BDa3sI6Qg5pL5axUqVsF82oF//FqwpQO+YTT+/4Kztuvl0w0DHN7LyAXqXs/DdvCeCYl k+Fw== X-Gm-Message-State: AOJu0Yxh65HsJStK/QY1cdPDDCi1BN5Cz0cjl2YS48oxWjcY5PPfJfdu UBlBe2Bqg+DXXPvDqQ+8GmwW896GVOgkkBAEt+g= X-Google-Smtp-Source: AGHT+IFm1UpsAJsbxMCZuZaJ6JUoSWQBqanN+cdIT9Jw+XQB/tw9B3bUmUYNi4Pt2/GT1caO4yFrDg== X-Received: by 2002:a05:6a00:b92:b0:68e:2cc4:c720 with SMTP id g18-20020a056a000b9200b0068e2cc4c720mr5837543pfj.12.1694900513870; Sat, 16 Sep 2023 14:41:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 30/39] exec: Rename target specific page-vary.c -> page-vary-target.c Date: Sat, 16 Sep 2023 14:41:14 -0700 Message-Id: <20230916214123.525796-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900578521100005 From: Philippe Mathieu-Daud=C3=A9 This matches the target agnostic 'page-vary-common.c' counterpart. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Message-Id: <20230914185718.76241-8-philmd@linaro.org> Signed-off-by: Richard Henderson --- MAINTAINERS | 2 +- meson.build | 2 +- page-vary.c =3D> page-vary-target.c | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename page-vary.c =3D> page-vary-target.c (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 12261d8eaf..ff436dbf21 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -141,7 +141,7 @@ F: softmmu/cpus.c F: softmmu/watchpoint.c F: cpu-common.c F: cpu-target.c -F: page-vary.c +F: page-vary-target.c F: page-vary-common.c F: accel/tcg/ F: accel/stubs/tcg-stub.c diff --git a/meson.build b/meson.build index 3e86a6cebf..3282f888a3 100644 --- a/meson.build +++ b/meson.build @@ -3439,7 +3439,7 @@ if get_option('b_lto') pagevary =3D declare_dependency(link_with: pagevary) endif common_ss.add(pagevary) -specific_ss.add(files('page-vary.c')) +specific_ss.add(files('page-vary-target.c')) =20 subdir('backends') subdir('disas') diff --git a/page-vary.c b/page-vary-target.c similarity index 100% rename from page-vary.c rename to page-vary-target.c --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900763; cv=none; d=zohomail.com; s=zohoarc; b=BODT1mH5P5hcDWIblCa0/tYdfvU0ct5nmtTHeI8wmA8VIb7+eD31k5nhLGzzNuLMpe98/HhwYuPm+9dEOAVrPHbwt3CRlW21a83HRuTxgOAphV8u41YQjUdAozwyf+xGwUeaIXwl2UM4kNb2pSln1UEvHMTDd+ycSNEOTVNiKk4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900763; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cHpFBBe6K7wL+xxrh3LaMDkBxsYBz22j+LgYC5aNQv8=; b=Wm2e6f0X7ToV/+eZscQgMV/bdLKiY3xUB3TR9sxkWn3o6m/C1QwRsRrJkFp1X82+m1WgtAVT6kjJt5mJYiemJCH2czf+O4MgihK9T/S9KxfnJqmFLQLIglTtK1LW73LIm/Z4vanxKwNnX4N23EQgNQR52LztbSE9W94QQdOng1o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169490076351197.52661244627257; Sat, 16 Sep 2023 14:46:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd3l-0006Fo-L1; Sat, 16 Sep 2023 17:42:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd39-0005EP-TF for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:42:01 -0400 Received: from mail-oa1-x2f.google.com ([2001:4860:4864:20::2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd35-0000Va-Vt for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:41:58 -0400 Received: by mail-oa1-x2f.google.com with SMTP id 586e51a60fabf-1cca0a1b3c7so2003860fac.2 for ; Sat, 16 Sep 2023 14:41:55 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900515; x=1695505315; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cHpFBBe6K7wL+xxrh3LaMDkBxsYBz22j+LgYC5aNQv8=; b=e0YcULW3E51hjei8nhyEnleMXCR9IoGMtiGwPDEIhEvdOs/rEfrc0viX4WSuVHx2F2 LW7xVZPJEqn0ouSFB9Hstp3HC+rxX0jpF4dVyXaRKYfruTfzHdpamXYcMuhEb0Lq0Dyx uAUEHYDeuzlCIP7/lNNZvBjBtfzDt9/kFLj16u9+UJ7HRiCU+kSmFJUGygdtpMQBdQ2S impaSfkzh5SFaCBtO61Kky/MrPe8BpsSAcOQqcLpqFlmsHxKhVCPK5XDiKze7dFG6ylF bMGULrCBR4J5Bj4od28sJdwLZtmu0uO0g7p3FPKYaFk/9XlsRbSfuPwxOy/GM3SpMtSx w5QA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900515; x=1695505315; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cHpFBBe6K7wL+xxrh3LaMDkBxsYBz22j+LgYC5aNQv8=; b=AjGrkhBH6IYWljowS1B2+oxcEjit8H7Ps4+d77PqfFpskuNEGfACoXUJuxuz2nBep/ Sxj6q9TCdXlaBTJCGp+5YecQ4Dp3lM/DluHND5dTy9cv9XwUMBdQD92gZSsgKz7IMUhb 1NvGEJ3OWrZNG4ZPaN1heS2ugJ2u8EhybfEjnT9ngK11d6PZYwVUB+CtXV9SNnbml2sC RvTewxf+VHFc4TCcdyh+YlER3iwFAVoJe8Pl33xqm7z4lmcHN6mCG4XxQOqksO6a19gg Sp0Rz1C5cNiITdWd+8LLq0CPaW8JOiRvc+TVXeiUzkfWT20NG+Nt/DCI5uMubpXbOQzm PhZA== X-Gm-Message-State: AOJu0Yy/BGIc5OUrzz4gS5G/3jSqyE/t396iUfIdomDST4U8CIyAx+sD gkepSxRqYovBL0E589DQZaxUgqhop/kGWOpXSXo= X-Google-Smtp-Source: AGHT+IF7z7ugop9DOECSzjFihelhlMyh8APXdgjDG3R5IlAL8IU0+v4cdnn/zengarRbx/mEj717rA== X-Received: by 2002:a05:6871:687:b0:1ba:caf2:acc3 with SMTP id l7-20020a056871068700b001bacaf2acc3mr6488679oao.5.1694900514772; Sat, 16 Sep 2023 14:41:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 31/39] accel/tcg: Rename target-specific 'internal.h' -> 'internal-target.h' Date: Sat, 16 Sep 2023 14:41:15 -0700 Message-Id: <20230916214123.525796-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900763932100001 From: Philippe Mathieu-Daud=C3=A9 accel/tcg/internal.h contains target specific declarations. Unit files including it become "target tainted": they can not be compiled as target agnostic. Rename using the '-target' suffix to make this explicit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Message-Id: <20230914185718.76241-9-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/{internal.h =3D> internal-target.h} | 6 +++--- accel/tcg/cpu-exec-common.c | 2 +- accel/tcg/cpu-exec.c | 2 +- accel/tcg/cputlb.c | 2 +- accel/tcg/monitor.c | 2 +- accel/tcg/tb-maint.c | 2 +- accel/tcg/tcg-all.c | 2 +- accel/tcg/translate-all.c | 2 +- accel/tcg/translator.c | 2 +- accel/tcg/user-exec.c | 2 +- 10 files changed, 12 insertions(+), 12 deletions(-) rename accel/tcg/{internal.h =3D> internal-target.h} (96%) diff --git a/accel/tcg/internal.h b/accel/tcg/internal-target.h similarity index 96% rename from accel/tcg/internal.h rename to accel/tcg/internal-target.h index cd6b9eb7f0..4ce3b29056 100644 --- a/accel/tcg/internal.h +++ b/accel/tcg/internal-target.h @@ -1,13 +1,13 @@ /* - * Internal execution defines for qemu + * Internal execution defines for qemu (target specific) * * Copyright (c) 2003 Fabrice Bellard * * SPDX-License-Identifier: LGPL-2.1-or-later */ =20 -#ifndef ACCEL_TCG_INTERNAL_H -#define ACCEL_TCG_INTERNAL_H +#ifndef ACCEL_TCG_INTERNAL_TARGET_H +#define ACCEL_TCG_INTERNAL_TARGET_H =20 #include "exec/exec-all.h" #include "exec/translate-all.h" diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index 8ac2af4d0c..55980417b4 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -22,7 +22,7 @@ #include "sysemu/tcg.h" #include "exec/exec-all.h" #include "qemu/plugin.h" -#include "internal.h" +#include "internal-target.h" =20 bool tcg_allowed; =20 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 0e7eeef001..f5625e047a 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -42,7 +42,7 @@ #include "tb-jmp-cache.h" #include "tb-hash.h" #include "tb-context.h" -#include "internal.h" +#include "internal-target.h" =20 /* -icount align implementation. */ =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index c53f434c88..df20bf4034 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -35,7 +35,7 @@ #include "exec/translate-all.h" #include "trace.h" #include "tb-hash.h" -#include "internal.h" +#include "internal-target.h" #ifdef CONFIG_PLUGIN #include "qemu/plugin-memory.h" #endif diff --git a/accel/tcg/monitor.c b/accel/tcg/monitor.c index d48de23999..30724fdb98 100644 --- a/accel/tcg/monitor.c +++ b/accel/tcg/monitor.c @@ -16,7 +16,7 @@ #include "sysemu/cpu-timers.h" #include "sysemu/tcg.h" #include "tcg/tcg.h" -#include "internal.h" +#include "internal-target.h" =20 =20 static void dump_drift_info(GString *buf) diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 32ae8af61c..85cf51445d 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -29,7 +29,7 @@ #include "tcg/tcg.h" #include "tb-hash.h" #include "tb-context.h" -#include "internal.h" +#include "internal-target.h" =20 =20 /* List iterators for lists of tagged pointers in TranslationBlock. */ diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 03dfd67e9e..b32e0b80ec 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -38,7 +38,7 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/boards.h" #endif -#include "internal.h" +#include "internal-target.h" =20 struct TCGState { AccelState parent_obj; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 83e07b830f..6c09b7f50d 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -61,7 +61,7 @@ #include "tb-jmp-cache.h" #include "tb-hash.h" #include "tb-context.h" -#include "internal.h" +#include "internal-target.h" #include "perf.h" #include "tcg/insn-start-words.h" =20 diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index d9fcb4cbe8..65219b52eb 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -14,7 +14,7 @@ #include "exec/translator.h" #include "exec/plugin-gen.h" #include "tcg/tcg-op-common.h" -#include "internal.h" +#include "internal-target.h" =20 static void gen_io_start(void) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 17f9aff0cf..f925dd0305 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -29,7 +29,7 @@ #include "qemu/atomic128.h" #include "trace/trace-root.h" #include "tcg/tcg-ldst.h" -#include "internal.h" +#include "internal-target.h" =20 __thread uintptr_t helper_retaddr; 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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900516; x=1695505316; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=l6gfR2aUZDEN0GM3qWd4UDvByhc2dFh0dzXal65oWsM=; b=gW6YjUHpNd+282hZ+6ZJ3vKpH9mw79O2G1ytk+zRHBQWZDTYV3/2zzLDpF/yoy6ozo rlixmSPeNnIlwKF5MxkI2drgmFBuUbnAHvvUy1MwVyJS6rk74OzSLYyvW08OnoW1AJoO W9z1YfhVUN3enLkV8EMT3v8/atb1VGp8xhXQM/RLf6IIHipxF9vX3CgmqxzhaKTwrdsY 4PHdG+ZcSZSvVP8IlhhubdfM9NrNvLtl3Ldddh5R5jaehk3S92mLeTtJYzCHcRoY2NEX t4MdTKH0AEr94ZC/xmNEyza6ZU7FFL/GATxfEkDthxiZNoIzN/efDV7nGKtd4jULFjIP N0og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900516; x=1695505316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=l6gfR2aUZDEN0GM3qWd4UDvByhc2dFh0dzXal65oWsM=; b=IwIUXRUozp4zK7KkOiNVwqeee+Bnw5C+AfKoNtBxg7Fwkt5YegoOa5iw4O8a75nra/ GKUnI0BP6YSuA74P/vG+9v37ccKtrHktHrECbe0i7u1GaA9/5jTvlVbYoetCPbVThu22 PBMJhQfDam401YvKQj7S9jXVtqF6JdkCfQN1kyar0wk+i5piZ6/3zjOHPvnvengYxHCj UYahVIKJD86kd2gHBNRxxwJQ5Moo6bBFXM+SmgRn2WSM/j6qQ9s+KalkXYMXiFNFVw6A cBbTtBWU7xPcVkOpsAHkBF4LvPn1lTAi0AYSrAPjpmXGrRaWKV5ps9dhn7hJIBWDbYam tyHg== X-Gm-Message-State: AOJu0YykTnLjIq3Q2qdqlWO0wf9U62Cm0gPTX63lSbWW5Vtdea0v2PQZ +TaoNu4HeJouyV937DtGyO7CM5SDX0N5ZF70rIY= X-Google-Smtp-Source: AGHT+IFvtbbemW1iDJQU0YCk+iHWY84hHSeAZBFDIc/E9Keh6PrwWQUOZqCLxLUuo3b8lewRdXrREA== X-Received: by 2002:a05:6a00:24ca:b0:68e:2f6e:b4c0 with SMTP id d10-20020a056a0024ca00b0068e2f6eb4c0mr6242884pfv.28.1694900515679; Sat, 16 Sep 2023 14:41:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 32/39] accel/tcg: Make monitor.c a target-agnostic unit Date: Sat, 16 Sep 2023 14:41:16 -0700 Message-Id: <20230916214123.525796-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900785152100003 From: Philippe Mathieu-Daud=C3=A9 Move target-agnostic declarations from "internal-target.h" to a new "internal-common.h" header. monitor.c now don't include target specific headers and can be compiled once in system_ss[]. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Message-Id: <20230914185718.76241-10-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/internal-common.h | 17 +++++++++++++++++ accel/tcg/internal-target.h | 5 ----- accel/tcg/cpu-exec.c | 1 + accel/tcg/monitor.c | 2 +- accel/tcg/translate-all.c | 1 + accel/tcg/meson.build | 3 +++ 6 files changed, 23 insertions(+), 6 deletions(-) create mode 100644 accel/tcg/internal-common.h diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h new file mode 100644 index 0000000000..5d5247442e --- /dev/null +++ b/accel/tcg/internal-common.h @@ -0,0 +1,17 @@ +/* + * Internal execution defines for qemu (target agnostic) + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ACCEL_TCG_INTERNAL_COMMON_H +#define ACCEL_TCG_INTERNAL_COMMON_H + +extern int64_t max_delay; +extern int64_t max_advance; + +void dump_exec_info(GString *buf); + +#endif diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 4ce3b29056..f9eec1ce28 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -99,11 +99,6 @@ static inline bool cpu_in_serial_context(CPUState *cs) return !(cs->tcg_cflags & CF_PARALLEL) || cpu_in_exclusive_context(cs); } =20 -extern int64_t max_delay; -extern int64_t max_advance; - -void dump_exec_info(GString *buf); - extern bool one_insn_per_tb; =20 /** diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f5625e047a..95dd8a30cb 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -42,6 +42,7 @@ #include "tb-jmp-cache.h" #include "tb-hash.h" #include "tb-context.h" +#include "internal-common.h" #include "internal-target.h" =20 /* -icount align implementation. */ diff --git a/accel/tcg/monitor.c b/accel/tcg/monitor.c index 30724fdb98..caf1189e0b 100644 --- a/accel/tcg/monitor.c +++ b/accel/tcg/monitor.c @@ -16,7 +16,7 @@ #include "sysemu/cpu-timers.h" #include "sysemu/tcg.h" #include "tcg/tcg.h" -#include "internal-target.h" +#include "internal-common.h" =20 =20 static void dump_drift_info(GString *buf) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 6c09b7f50d..8cb6ad3511 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -61,6 +61,7 @@ #include "tb-jmp-cache.h" #include "tb-hash.h" #include "tb-context.h" +#include "internal-common.h" #include "internal-target.h" #include "perf.h" #include "tcg/insn-start-words.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 8ace783707..0fb03bd7d3 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -20,6 +20,9 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) =20 specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', +)) + +system_ss.add(when: ['CONFIG_TCG'], if_true: files( 'monitor.c', )) =20 --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900516; x=1695505316; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pwAW1yDMAGo64PQxKFedXSqZpiMNes3r170GM9uSE/0=; b=TmMM4lZS//FNpzkbjnsTUjN9QfgIiZJhQ8sgtbV7BDohwgxN6qwS5Fh0XaPGvVKT6J DsG9zKaIvE4DZgbVtyJusuIHiXNUn8TL7yUnsPxACiiJ9JkO62ov4yiCI06Ldgdgz+mo m/zLt3qzsP5qQE455TcOWXJGUriM6OUjlAHrDhB9NnIqeWOKfCRJuyDXkFJvTvoOrOzZ qgNGuLh2XsZMElGp8tEBJD8CYCqzuM0B48CTDSlQJdns96bo9Ut6w9Wpw2JiW9n27UtB hU0nzrx8Okzw2pQrSWwfeMtJUj9VNDIuO6iRcb21yAXCcJiFVW/ZetPkB2i8469cVTgI QENw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900516; x=1695505316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pwAW1yDMAGo64PQxKFedXSqZpiMNes3r170GM9uSE/0=; b=GeoUMBRfFtIizyiHgrwJIVlCBI07I3QIaNvIPX05PXTPpVA2ZOWrcJ+8RKhwOAbcEX x+dLO9oq9FxoavC+YBbRQGfmUtEpe6EBPIj87h5cZTODhAJNg2/CqxvGOEiVcV9Vz5L8 YiVkM+0HE8ZhCErrkc2Q0mvxv2C+tt3OhryUQigRSTqyGeQo8+G+cfIkRQUQ3pyTNk8l bDiyfrICfZxUczg83tcKGqYnlNNPc+fBNJswwwxvXhyAPJfS8tjAPBuZH/qHplasMvNF r8wzGpvaLwgdx6QwQD6nuB0Knylmxvu9RtSTIBLyUxdD5lpBraWDxZSJatT2Ub9Gl29s fOLg== X-Gm-Message-State: AOJu0Yw3IjZPzcDH4ytkM1oTfxaHIIiG3GIiUETyfg9MgYqqP0cAU+L7 EaXrRZC/9sQI/jIcDloj0+sFibFSGrr/ar2gm/w= X-Google-Smtp-Source: AGHT+IFfb8T50wfHGcCeNUcBrunri+MckzdQmUnL+Ivfri/AbKIIpLIz2sVELD3FnuoaFqJPutJ5sQ== X-Received: by 2002:a05:6870:e30f:b0:1d6:57ab:433e with SMTP id z15-20020a056870e30f00b001d657ab433emr6247855oad.47.1694900516561; Sat, 16 Sep 2023 14:41:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 33/39] accel/tcg: Make icount.o a target agnostic unit Date: Sat, 16 Sep 2023 14:41:17 -0700 Message-Id: <20230916214123.525796-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c32; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900644217100003 From: Philippe Mathieu-Daud=C3=A9 Remove the unused "exec/exec-all.h" header. There is no more target specific code in it: make it target agnostic (rename using the '-common' suffix). Since it is TCG specific, move it to accel/tcg, updating MAINTAINERS. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Message-Id: <20230914185718.76241-11-philmd@linaro.org> Signed-off-by: Richard Henderson --- MAINTAINERS | 1 - softmmu/icount.c =3D> accel/tcg/icount-common.c | 3 +-- accel/tcg/meson.build | 1 + softmmu/meson.build | 4 ---- 4 files changed, 2 insertions(+), 7 deletions(-) rename softmmu/icount.c =3D> accel/tcg/icount-common.c (99%) diff --git a/MAINTAINERS b/MAINTAINERS index ff436dbf21..047d143b9d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2912,7 +2912,6 @@ F: softmmu/main.c F: softmmu/cpus.c F: softmmu/cpu-throttle.c F: softmmu/cpu-timers.c -F: softmmu/icount.c F: softmmu/runstate* F: qapi/run-state.json =20 diff --git a/softmmu/icount.c b/accel/tcg/icount-common.c similarity index 99% rename from softmmu/icount.c rename to accel/tcg/icount-common.c index 4527bfbd6e..0bf5bb5e21 100644 --- a/softmmu/icount.c +++ b/accel/tcg/icount-common.c @@ -27,7 +27,6 @@ #include "migration/vmstate.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "exec/exec-all.h" #include "sysemu/cpus.h" #include "sysemu/qtest.h" #include "qemu/main-loop.h" @@ -38,7 +37,7 @@ #include "hw/core/cpu.h" #include "sysemu/cpu-timers.h" #include "sysemu/cpu-throttle.h" -#include "timers-state.h" +#include "softmmu/timers-state.h" =20 /* * ICOUNT: Instruction Counter diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 0fb03bd7d3..4633a34d28 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -23,6 +23,7 @@ specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'= ], if_true: files( )) =20 system_ss.add(when: ['CONFIG_TCG'], if_true: files( + 'icount-common.c', 'monitor.c', )) =20 diff --git a/softmmu/meson.build b/softmmu/meson.build index c18b7ad738..3a64dd89de 100644 --- a/softmmu/meson.build +++ b/softmmu/meson.build @@ -6,10 +6,6 @@ specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_true: [file= s( 'watchpoint.c', )]) =20 -specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: [file= s( - 'icount.c', -)]) - system_ss.add(files( 'balloon.c', 'bootdevice.c', --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900763; cv=none; d=zohomail.com; s=zohoarc; b=T4SOvwTSQrnMKoDohrmymBUCAmMZ1jmvSHA8WkveFu3BHAJDrQdA5wp/5oP7mONe2vJ7T6mdWRoMOVwzdEoCieC3eqSycSYeNNU25TL7VXW8cerSZUpek/Q4D0LeavqnvIXosCx8d1T4AWhWPfiQtBtsWi3AcyJ86HipJN34vn4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900763; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6VTpBWRs4wNK7fliIDMYgMpLG0bEcOQT795ogcrcYr0=; b=EveraoR27+qxoANbnK4QnzXpYSHaNnpQ5sErTR0FdMIu6sI6l7Qjd013/zsRFcyEh9engRzjT9fqctUjp7lKhtHgT3HUk6lRJ5yOmiLstz0xKwRuEh6NCl0NUKAd0Aw8Y91Nv5dcDipA26/UA9UwRQlDP+HMA8K7zIy4zDcg1yc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169490076334722.559496702799834; Sat, 16 Sep 2023 14:46:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd3j-0005vk-Au; Sat, 16 Sep 2023 17:42:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd3C-0005Eu-7l for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:42:03 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd39-0000WK-MQ for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:42:01 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-68c576d35feso3072296b3a.2 for ; Sat, 16 Sep 2023 14:41:59 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900517; x=1695505317; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6VTpBWRs4wNK7fliIDMYgMpLG0bEcOQT795ogcrcYr0=; b=yRy/7G7Pm0V2+MwkQKB9d9p+Zc5ozkrW57msve/Uyn5o3I4jnOqmDbAa1D8iyi8lJM EUkvbxnVzH/mtUR4iJwhBqZUwwsaicwGiYfquQCI2PC/ecKby/e1CLA5UPUaWkgyd9Iy 0vI2QJIMHbYit7GksR3ZHxrkLzQNeDT53HepI6CPI0UUPy07QCbuMz2VtkOxww0nYkFw 9Kmj4DQC1hQaJgzG65eAojR9PM+LGTZtPn68Yiw9Tb4M1l9671zoKZUm8uA5uGtVqTMx 4tBp+I7yQ6Hrz2r7zFnHm5VpNMTU6sXYtNqibdGZQGQVIUslaPnnnaL+qAHvgTmtQ2Bs /f2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900517; x=1695505317; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6VTpBWRs4wNK7fliIDMYgMpLG0bEcOQT795ogcrcYr0=; b=pIFvwaND3/dSt2CAJXrU6nv0NnEpPwCsGe6SJg8z2ICLqlgIDaWp34EDBWSVpm0fhi L1Rrf+pr1UDFatM0AhJzO1aMk6g3BjFVGgeTZUGCdcCgRkh9Ygq6JL6bg78Qx8SyXOX3 5aHThh4tRDiRUPX6rZ0knplTI8QndEHbgOHX958aVYPa3W52ADwpQi/9ndNQoKKNS2v7 DFNK9rlvuUfM7OmMIlnp11XAhxWXUS56UdxybeHYtBNJEN/PYbhDSyrmnZJRKjdJIcoT ahhnEvmjTuRnFpzn7WHsiIuZ0NnZj96vX90+zoTVB333TisZgQxym5wBjs5fKnrrqohB RW4Q== X-Gm-Message-State: AOJu0Yy6k5lUCbdxlAw80pUhiuKzPOmSGCHNbwor1mx3jqdCwlsP+AJo Z07sUEa8460f9620pXn9fOyMG6o3z2Sc+4f984o= X-Google-Smtp-Source: AGHT+IEBaRerfQfLVI3HNp2zSufW/MjL0q8V3zM5SEUjxSJrYAOWlyj0POm/BQjRntRIZb4LnxHs8Q== X-Received: by 2002:a05:6a00:c96:b0:68f:d864:596 with SMTP id a22-20020a056a000c9600b0068fd8640596mr6961545pfv.3.1694900517281; Sat, 16 Sep 2023 14:41:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 34/39] accel/tcg: Make cpu-exec-common.c a target agnostic unit Date: Sat, 16 Sep 2023 14:41:18 -0700 Message-Id: <20230916214123.525796-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900763984100002 From: Philippe Mathieu-Daud=C3=A9 cpu_in_serial_context() is not target specific, move it declaration to "internal-common.h" (which we include in the 4 source files modified). Remove the unused "exec/exec-all.h" header from cpu-exec-common.c. There is no more target specific code in this file: make it target agnostic. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Anton Johansson Message-Id: <20230914185718.76241-12-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/internal-common.h | 11 +++++++++++ accel/tcg/internal-target.h | 9 --------- accel/tcg/cpu-exec-common.c | 3 +-- accel/tcg/cputlb.c | 1 + accel/tcg/tb-maint.c | 1 + accel/tcg/user-exec.c | 1 + accel/tcg/meson.build | 4 +++- 7 files changed, 18 insertions(+), 12 deletions(-) diff --git a/accel/tcg/internal-common.h b/accel/tcg/internal-common.h index 5d5247442e..3b2277e6e9 100644 --- a/accel/tcg/internal-common.h +++ b/accel/tcg/internal-common.h @@ -9,9 +9,20 @@ #ifndef ACCEL_TCG_INTERNAL_COMMON_H #define ACCEL_TCG_INTERNAL_COMMON_H =20 +#include "exec/translation-block.h" + extern int64_t max_delay; extern int64_t max_advance; =20 void dump_exec_info(GString *buf); =20 +/* + * Return true if CS is not running in parallel with other cpus, either + * because there are no other cpus or we are within an exclusive context. + */ +static inline bool cpu_in_serial_context(CPUState *cs) +{ + return !(cs->tcg_cflags & CF_PARALLEL) || cpu_in_exclusive_context(cs); +} + #endif diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index f9eec1ce28..932bbe4b63 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -90,15 +90,6 @@ static inline vaddr log_pc(CPUState *cpu, const Translat= ionBlock *tb) } } =20 -/* - * Return true if CS is not running in parallel with other cpus, either - * because there are no other cpus or we are within an exclusive context. - */ -static inline bool cpu_in_serial_context(CPUState *cs) -{ - return !(cs->tcg_cflags & CF_PARALLEL) || cpu_in_exclusive_context(cs); -} - extern bool one_insn_per_tb; =20 /** diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index 55980417b4..b6cc387482 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -20,9 +20,8 @@ #include "qemu/osdep.h" #include "sysemu/cpus.h" #include "sysemu/tcg.h" -#include "exec/exec-all.h" #include "qemu/plugin.h" -#include "internal-target.h" +#include "internal-common.h" =20 bool tcg_allowed; =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index df20bf4034..b8c5e345b8 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -35,6 +35,7 @@ #include "exec/translate-all.h" #include "trace.h" #include "tb-hash.h" +#include "internal-common.h" #include "internal-target.h" #ifdef CONFIG_PLUGIN #include "qemu/plugin-memory.h" diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 85cf51445d..b194f8f065 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -29,6 +29,7 @@ #include "tcg/tcg.h" #include "tb-hash.h" #include "tb-context.h" +#include "internal-common.h" #include "internal-target.h" =20 =20 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index f925dd0305..5bf2761bf4 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -29,6 +29,7 @@ #include "qemu/atomic128.h" #include "trace/trace-root.h" #include "tcg/tcg-ldst.h" +#include "internal-common.h" #include "internal-target.h" =20 __thread uintptr_t helper_retaddr; diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 4633a34d28..8783edd06e 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -1,7 +1,9 @@ tcg_ss =3D ss.source_set() +common_ss.add(when: 'CONFIG_TCG', if_true: files( + 'cpu-exec-common.c', +)) tcg_ss.add(files( 'tcg-all.c', - 'cpu-exec-common.c', 'cpu-exec.c', 'tb-maint.c', 'tcg-runtime-gvec.c', --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900518; x=1695505318; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2JL8rjLVD092FwcI3216ms8eo5o4CvSUxoIR2XgkySs=; b=C3aVPzFSb6sKY7GjEk5FMERAPd6qWkqK5kawrH01Fm1T7S86+91RhHdBxWFuZ4SxR5 obrmMRVkJNDLAYlkNB0w5VrPja67uZhQgi3u+o/cclrNj86KseiGVb61GjUUQUGJWIe2 ItPVfsqHU+DS8nVyTV35FYrMP82gQm6s8ylkpyhx7ue9o+Eh4lkTYHm2K2WFKTLSFDf2 d1l1lzCxHc/ud9QjadRN9mKCTjXpElTBe7ll+Z0Sbm0qkiNlYcNaz8/nJGxFiwHRmdMV jgTzgwFr5QZpsgAHytEU5pDhgV4aGV96QrXaNtLpMpqNOg+xyakCRPBve1QC0t1luRnR jpHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900518; x=1695505318; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2JL8rjLVD092FwcI3216ms8eo5o4CvSUxoIR2XgkySs=; b=eYM6dDBfuivKD0eHlFquwempcujmWxJk/5cR2z4ijOOx98oCsME+uOcEPjSnlUlj87 ZCMG7lrDc+Y8peLAJL0+Iq16BQTgkyvem5Ag9qik/pHx+KiEQTMRUiswEXlEbjKRryhE lg2GUTqyILYg6nI1/AG84IpmpljisSL6EPBbi/ceG9nRDCUZ8yWXhJcpNkg3I7zsX7pY JGmCQdwZtJxB7EK/Btc1y/7LTtlY9WWXaG74060sKVXWYRsfbmv2Fx+kpSTqECP7v2D3 /Mu6rItyPstO2ZpHvjLAWpTAo+3g0VkMPHziIxVwm2+eglsJbhMv/xcwWlYUUWRmD+X9 3zXA== X-Gm-Message-State: AOJu0YwqF6TAYbCr/q7HL5QUbAgs6Usd3aqeLyZn6iGOfAD3bBAwDH2T KhX6wsTaHbxSBuNulu2i49tnhMWeeRvOA1rPXkY= X-Google-Smtp-Source: AGHT+IGLBbl3oBKFjOyaS5oQce75UxI3GonvyE9r23p4b9EKmV2chnTHKP0mSuKAOnty1AuXu0u1Vg== X-Received: by 2002:a05:6a00:1a92:b0:68f:b015:ea99 with SMTP id e18-20020a056a001a9200b0068fb015ea99mr6962101pfv.10.1694900518167; Sat, 16 Sep 2023 14:41:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 35/39] accel: Rename accel_cpu_realizefn() -> accel_cpu_realize() Date: Sat, 16 Sep 2023 14:41:19 -0700 Message-Id: <20230916214123.525796-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900590173100003 From: Philippe Mathieu-Daud=C3=A9 We use the '*fn' suffix for handlers, this is a public method. Drop the suffix. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230915190009.68404-2-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/qemu/accel.h | 4 ++-- accel/accel-target.c | 2 +- cpu-target.c | 2 +- target/i386/kvm/kvm-cpu.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/qemu/accel.h b/include/qemu/accel.h index e84db2e3e5..cb64a07b84 100644 --- a/include/qemu/accel.h +++ b/include/qemu/accel.h @@ -90,11 +90,11 @@ void accel_setup_post(MachineState *ms); void accel_cpu_instance_init(CPUState *cpu); =20 /** - * accel_cpu_realizefn: + * accel_cpu_realize: * @cpu: The CPU that needs to call accel-specific cpu realization. * @errp: currently unused. */ -bool accel_cpu_realizefn(CPUState *cpu, Error **errp); +bool accel_cpu_realize(CPUState *cpu, Error **errp); =20 /** * accel_supported_gdbstub_sstep_flags: diff --git a/accel/accel-target.c b/accel/accel-target.c index df72cc989a..b953855e8b 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -119,7 +119,7 @@ void accel_cpu_instance_init(CPUState *cpu) } } =20 -bool accel_cpu_realizefn(CPUState *cpu, Error **errp) +bool accel_cpu_realize(CPUState *cpu, Error **errp) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 diff --git a/cpu-target.c b/cpu-target.c index 0769b0b153..61c9760e62 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -136,7 +136,7 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) /* cache the cpu class for the hotpath */ cpu->cc =3D CPU_GET_CLASS(cpu); =20 - if (!accel_cpu_realizefn(cpu, errp)) { + if (!accel_cpu_realize(cpu, errp)) { return; } =20 diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index 7237378a7d..4474689f81 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -35,7 +35,7 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp) * x86_cpu_realize(): * -> x86_cpu_expand_features() * -> cpu_exec_realizefn(): - * -> accel_cpu_realizefn() + * -> accel_cpu_realize() * kvm_cpu_realizefn() -> host_cpu_realizefn() * -> check/update ucode_rev, phys_bits, mwait */ --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900711; cv=none; d=zohomail.com; s=zohoarc; b=eSmksYJdy3+Kly4JjI/0P8hA+9pm6bZMzeytJiZstHesyhsq31IFX4ty6GJydjmMe7b/wdafLYG05ZJPXGTBlGoWUf1ZOoNCD+rmSTdCU6DX1uDgOC/CTu8t/bGL0qL2Z7KgMs+XOLcmPajDFFbOAbRnmy2yiWtili0cCtW49n4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900711; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AHcFvVjiu81dG+FC6IAxYA+pdBiv307/mnWZeRBLY1I=; b=nnOwlXTbXYzu8Moq/Av09XWghrAnYnTzhwH0S/BwWsbdqDPjbYrsDsbwuMoUZYs9hOBooYozx3GreFM4UX2WyDkoNVGNn8w+2NXAtgNfxv+RpRbYRFJRjrHePNo3QHr60AKGqMUaK1Ck9sWa0FSxz0YZk1BOFDTzoQ9tXqfJE6E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900711685782.2956890922742; Sat, 16 Sep 2023 14:45:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd3t-0007Lv-Fo; Sat, 16 Sep 2023 17:42:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd3D-0005Ex-8f for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:42:04 -0400 Received: from mail-ot1-x335.google.com ([2607:f8b0:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd3A-0000WX-Cg for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:42:02 -0400 Received: by mail-ot1-x335.google.com with SMTP id 46e09a7af769-6c0bbbbad81so2053961a34.3 for ; Sat, 16 Sep 2023 14:42:00 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900519; x=1695505319; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AHcFvVjiu81dG+FC6IAxYA+pdBiv307/mnWZeRBLY1I=; b=nG90b1h+iK2jk5y+hu4e5nfAoDE9CIWBovFbE+bC4vbwUiQog7j1y7+7eNL6HOEl3j ILlaOC7nsIhM8PmzPKJFPeR2+aRDZs+sZvZteD1gmYzcVSBoYKBL9ESIR1jfQCzseAiB 8ngtuO1T8/PLVijQZvXng89iVMJVnJXzs3StbvFHjG244Cjtw6pamKG7K12+mXO8ghaZ IEP6mr2Ps1iDYRXyUTphbhOL/GjG9LHR5fCm/5OGb4EJw0yBv8rZ+UkZtJmo+ZOEwQYh m7X1AFqwyz3mrN+QZNr0biceOXwZ1lQ4kgI8KUHGbge+TVh5mLNkYjJJG3gEkhKVJJWO r5eA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900519; x=1695505319; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AHcFvVjiu81dG+FC6IAxYA+pdBiv307/mnWZeRBLY1I=; b=WIXTJsg2UARb7LxUaVrl1OoPRNPvtu4PHayPzN+lGWmQoHuQw1gFnk4uSvT3Mh0s+x RkOmVuRMqgflOap+3ui/cY0rz/06jJGOSp9PjtBORsivfXwIwpvncWTUEsaviRwB2kRI 8YozzFEbMRDN1ztpq960HmooWQJuREVM5xMrguyw9I5Zx+KGs4u4IKBgDGKSKavz2IwY KhdSV/CwWANLn0JF3tnePd0MYA3ouckOejhNVAHnFjR1dwl1Xu9rNLYofSWNbqD2Hjp1 ki7i7TjxjrCW75Igl4e2Chy9FIPaRuP+cwtpQlYxKRPuSnejzsSpr6wIezLdUQ0Mxj94 gJsw== X-Gm-Message-State: AOJu0YyRBsmI2no/kXA1k1HmFZaEe4sTSLY8Fyf+kA8Eof7Aqujbfkpn cdKTFGB5KLP2fN6kpQMExJ1TAxFTyZ40cPEifqk= X-Google-Smtp-Source: AGHT+IGp5LYINqAaNccd3XIeGRRfXDTn405pFfVxSJor8r7/j2mnBPkf/ht++B969c1gK4ONrXszgQ== X-Received: by 2002:a05:6358:899:b0:13f:183b:f049 with SMTP id m25-20020a056358089900b0013f183bf049mr5566313rwj.1.1694900519017; Sat, 16 Sep 2023 14:41:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 36/39] accel: Introduce accel_cpu_unrealize() stub Date: Sat, 16 Sep 2023 14:41:20 -0700 Message-Id: <20230916214123.525796-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900713072100001 From: Philippe Mathieu-Daud=C3=A9 Prepare the stub for parity with accel_cpu_realize(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230915190009.68404-3-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/qemu/accel.h | 6 ++++++ accel/accel-target.c | 4 ++++ cpu-target.c | 3 ++- 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/include/qemu/accel.h b/include/qemu/accel.h index cb64a07b84..7b02cb40e5 100644 --- a/include/qemu/accel.h +++ b/include/qemu/accel.h @@ -96,6 +96,12 @@ void accel_cpu_instance_init(CPUState *cpu); */ bool accel_cpu_realize(CPUState *cpu, Error **errp); =20 +/** + * accel_cpu_unrealize: + * @cpu: The CPU that needs to call accel-specific cpu unrealization. + */ +void accel_cpu_unrealize(CPUState *cpu); + /** * accel_supported_gdbstub_sstep_flags: * diff --git a/accel/accel-target.c b/accel/accel-target.c index b953855e8b..cc3a45e663 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -129,6 +129,10 @@ bool accel_cpu_realize(CPUState *cpu, Error **errp) return true; } =20 +void accel_cpu_unrealize(CPUState *cpu) +{ +} + int accel_supported_gdbstub_sstep_flags(void) { AccelState *accel =3D current_accel(); diff --git a/cpu-target.c b/cpu-target.c index 61c9760e62..b928bbed50 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -187,8 +187,9 @@ void cpu_exec_unrealizefn(CPUState *cpu) cpu_list_remove(cpu); /* * Now that the vCPU has been removed from the RCU list, we can call - * tcg_exec_unrealizefn, which may free fields using call_rcu. + * accel_cpu_unrealize, which may free fields using call_rcu. */ + accel_cpu_unrealize(cpu); if (tcg_enabled()) { tcg_exec_unrealizefn(cpu); } --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900684; cv=none; d=zohomail.com; s=zohoarc; b=YEZpZxvaCcHYeICLrdX3NEusFVXx7yPHi1VSaiwKE55mDopl0xfhZ+2CgyJnItkZs7pZFEhaVBKnJTmKoLHLE6sKG3+6nQHQ3784NBK73S5G3HTOyNM7pIZV8qcKNeLo1zGaaeDwSaTVPat/ZpR0eXKMTYPFpU4VHROJB+z6las= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900684; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9frgVbpvR/cKhB4Eeaz6aEQy82XBehF08OdWl52rupE=; b=hFAd14KClRSBIaYXnww1ZQoArsbA2Yl9qHwqxhAwAblN2OGFyY39K6QNy4RNqXs9w5/jQOoa9aW1UI8SQ6upeFFM+RB879fleyljP4Iac+j5rQ0k7gHFWZVh1HtMLZlClTAtrQiRiOKAP22Ap1Gn6gX9ra6BLzR3n0iQRVGdIfc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900684161263.7685236448076; Sat, 16 Sep 2023 14:44:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd3u-0007TN-69; Sat, 16 Sep 2023 17:42:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd3D-0005Ey-DS for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:42:04 -0400 Received: from mail-oa1-x2f.google.com ([2001:4860:4864:20::2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd3B-0000Wl-Hi for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:42:03 -0400 Received: by mail-oa1-x2f.google.com with SMTP id 586e51a60fabf-1d643db2c98so1640346fac.0 for ; Sat, 16 Sep 2023 14:42:00 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900520; x=1695505320; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9frgVbpvR/cKhB4Eeaz6aEQy82XBehF08OdWl52rupE=; b=Yo3+1zJb4yxuZE9XIRgHbZuTIgu5F67ksKyYPS4JT8QZjMKSuI06v9vQjjKCXFbht1 yiGOY8D9Ct4kaHOtK+1j6Qr0x4zLbzkRMjqQd0TdqCLL1ktoFOgpqTPbt5QzxaOhe8ni g3unY/McDRCAZ+tlGgTmVJ3NQ3UdXTddbEP4JLTowZYGNCxwC8SK6ttmYCnXtx2W8+nd zZLctXIsd27I8jw7EdxL8zurSfVa+gM7FOlvZh2Dg4c2IwuqnI64lkENlw3O/ATDaYr4 H0rZPFr1nVfcrBpdE6R+RBgpjpEvEDDuD6e2zMZqgytnHOLUrWdEhkoDz3Y9JfNBa68/ A37Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900520; x=1695505320; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9frgVbpvR/cKhB4Eeaz6aEQy82XBehF08OdWl52rupE=; b=A00EiEfXHQJ4L5T5UXlaX8ZEiEVT3hewd8Srh3U45uUFJvfBpxoszj8F1tmI5SKZhy 7pLWstBqPQOpInMc+4ESuyY1rFB98fN4WDPsvZ8RRJO+Cxkw+ZjTJxTfSPNJ6egX1ZzU BxU8yO4y/+/Xla7G+d+z63H2tBU4/YdzR7r6IH+ZEkQpcllwF7XPDFr75e1XtB5i8XxY 8PufjsBT9TckEpbHqjZB/j777zK4fqpoMVs6OO58QYxQiao8SZN3mSMkHvDHQw21ormg pmWst9m8Oul5Cv2iajHdq84dOm8UkmKaYtzaYhzu59JrDa+6/h7JHzrr9Wa+wIiDLLm3 n48A== X-Gm-Message-State: AOJu0YwnA6NmS9WHmf3t+Pw0//nA3Kak+/s07Q+OyXlhEgmLFCLEoJlv nknArHomCX7CHclKn20EoMdcTGZDa2B0w6lJkkc= X-Google-Smtp-Source: AGHT+IHJ4nSrLQNu9jUVJlvLbnLxH+GklS/R7rjqp3RhIPkf6woyNEbUVBvgzU/eEDwxJMQWmtevXQ== X-Received: by 2002:a05:6870:95aa:b0:1ba:d044:8a4 with SMTP id k42-20020a05687095aa00b001bad04408a4mr6774135oao.18.1694900519795; Sat, 16 Sep 2023 14:41:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 37/39] accel: Declare AccelClass::[un]realize_cpu() handlers Date: Sat, 16 Sep 2023 14:41:21 -0700 Message-Id: <20230916214123.525796-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900684976100001 From: Philippe Mathieu-Daud=C3=A9 Currently accel_cpu_realize() only performs target-specific realization. Introduce the [un]realize_cpu fields in the base AccelClass to be able to perform target-agnostic [un]realization of vCPUs. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230915190009.68404-4-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/qemu/accel.h | 2 ++ accel/accel-target.c | 21 +++++++++++++++++++-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/include/qemu/accel.h b/include/qemu/accel.h index 7b02cb40e5..0b6031bd82 100644 --- a/include/qemu/accel.h +++ b/include/qemu/accel.h @@ -43,6 +43,8 @@ typedef struct AccelClass { bool (*has_memory)(MachineState *ms, AddressSpace *as, hwaddr start_addr, hwaddr size); #endif + bool (*realize_cpu)(CPUState *cpu, Error **errp); + void (*unrealize_cpu)(CPUState *cpu); =20 /* gdbstub related hooks */ int (*gdbstub_supported_sstep_flags)(void); diff --git a/accel/accel-target.c b/accel/accel-target.c index cc3a45e663..6d427f2b9d 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -122,15 +122,32 @@ void accel_cpu_instance_init(CPUState *cpu) bool accel_cpu_realize(CPUState *cpu, Error **errp) { CPUClass *cc =3D CPU_GET_CLASS(cpu); + AccelState *accel =3D current_accel(); + AccelClass *acc =3D ACCEL_GET_CLASS(accel); =20 - if (cc->accel_cpu && cc->accel_cpu->cpu_realizefn) { - return cc->accel_cpu->cpu_realizefn(cpu, errp); + /* target specific realization */ + if (cc->accel_cpu && cc->accel_cpu->cpu_realizefn + && !cc->accel_cpu->cpu_realizefn(cpu, errp)) { + return false; } + + /* generic realization */ + if (acc->realize_cpu && !acc->realize_cpu(cpu, errp)) { + return false; + } + return true; } =20 void accel_cpu_unrealize(CPUState *cpu) { + AccelState *accel =3D current_accel(); + AccelClass *acc =3D ACCEL_GET_CLASS(accel); + + /* generic unrealization */ + if (acc->unrealize_cpu) { + acc->unrealize_cpu(cpu); + } } =20 int accel_supported_gdbstub_sstep_flags(void) --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900672; cv=none; d=zohomail.com; s=zohoarc; b=i4VJOerIeDfjQbqzg5oConArcKprMBTnONN9/eWF7ZfUMyCFiV05N3aF8aKADUkr7JnkIOgmaJa5piBQ327ZLEFBm6hdwWnFhwovamVn+O/9LNyKaWQ/3zEvbidmniBHX6N3+OaC3B3qOs3MW8bO/MbcMGd2Zl2SAr/1496km20= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900672; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lwou9dRiH+VLiT9ntm3uIOKDMNj+TRwXlOoqSwbcsYA=; b=Bj2ZUPUxuOc0jIJJTZhG04KJswx8n+Z+58GXHPGgIQd925Ec4EMZaB2ZHqgg08wh80MJFV/LXZkCkXR8vPGdM0GGEAwT/0h+t7PkgXz/SfnOf+lwbHUNa58LW4B9XePoxDYenDrL6lCsgJ7y1au7u+kmSqiTg4DHSKkppFwHEeg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900672329421.6220297836405; Sat, 16 Sep 2023 14:44:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd3u-0007Wx-WA; Sat, 16 Sep 2023 17:42:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd3E-0005FC-Io for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:42:05 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd3C-0000Ww-HQ for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:42:04 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-68fcb4dc8a9so3074941b3a.2 for ; Sat, 16 Sep 2023 14:42:02 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:42:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900520; x=1695505320; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lwou9dRiH+VLiT9ntm3uIOKDMNj+TRwXlOoqSwbcsYA=; b=ynxZioXjWkj/dPEqLVn1mbxMUDpza9ieT5z64FA0DhpIcpcpJNeRPhFqnAwjAqAqH5 MbYlEfl/kl7e8T0ioHLOpuDYmNQv/FmMly8Vzg+nFowzru8m4LudVMzL5nKr0P7Y2N+b jcK/0qrPPVZmZNPoWy5qY3Zgy0ff/bT7GKUzclvZsziy47UDs4/akz795toR9F0lja91 N+WvP8+VJ8VzqlIOrA5NiNpnqiPetBg5YmTccZilRRlre6QF/tOER0MOus37hBqpBXl3 A7PwHOydbfW57v/VSdGm1WOA5Ca37y1py4OegAy15mWD5MKYBD70FFN9PNYR4ibLFO7E TK4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900520; x=1695505320; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lwou9dRiH+VLiT9ntm3uIOKDMNj+TRwXlOoqSwbcsYA=; b=Vm3W6Xwx70iPfdB51fOOuxqBEmDJaEyKX/z4nYiQunuhLY6FxTROtSO/3D/Nuds1WR C4L4pl68E/EPpcGbXD2Aw2DyZkMPP07ZFIwk9c3+dXHMSPQLWBEsG/YiGqK9GyXSTYuT RdTGTVWzL7gZEvgwRtJZxKNwGMDQK8Gi7iTmfGtrZuCzbJQjXQZqcCIFP0PXV0i0Vgjb wl8Cl+28m6e5DrLP010vB/OKV56I+e+m3LaZ/kmsL/Lm1Ffoq5Wo93Ff2iuobc2IXRWY FXdKHdfllOH8xcUIZiQhTxdlLRH56gVfVIyW/jxBvaqTuY/c/kMIWqmjm4wSSBuezdul ozag== X-Gm-Message-State: AOJu0YzrbMCeMR6SluUFgXXHDL7vD+Ui6Q88tjor4Vy9MedcdAXzChse qNDysTbpfXwSvxa5m9idU6nMSufasUysDyuAA+c= X-Google-Smtp-Source: AGHT+IEGtvoH04fRCAf19BV6YNcrkNM2pxS5/3TtZKMvd2E0HYK/xM9ytzLm7ht5TTE8mTsALRmWrg== X-Received: by 2002:a05:6a00:b83:b0:68f:ee51:7db1 with SMTP id g3-20020a056a000b8300b0068fee517db1mr5624088pfj.11.1694900520667; Sat, 16 Sep 2023 14:42:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 38/39] accel/tcg: Have tcg_exec_realizefn() return a boolean Date: Sat, 16 Sep 2023 14:41:22 -0700 Message-Id: <20230916214123.525796-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900672604100001 From: Philippe Mathieu-Daud=C3=A9 Following the example documented since commit e3fe3988d7 ("error: Document Error API usage rules"), have tcg_exec_realizefn() return a boolean indicating whether an error is set or not. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230915190009.68404-5-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 2 +- accel/tcg/cpu-exec.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 8d262d141e..6c1db14842 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -410,7 +410,7 @@ static inline bool tlb_hit(uint64_t tlb_addr, vaddr add= r) =20 /* accel/tcg/cpu-exec.c */ int cpu_exec(CPUState *cpu); -void tcg_exec_realizefn(CPUState *cpu, Error **errp); +bool tcg_exec_realizefn(CPUState *cpu, Error **errp); void tcg_exec_unrealizefn(CPUState *cpu); =20 /* Validate correct placement of CPUArchState. */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 95dd8a30cb..fd0fc08f76 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -1089,7 +1089,7 @@ int cpu_exec(CPUState *cpu) return ret; } =20 -void tcg_exec_realizefn(CPUState *cpu, Error **errp) +bool tcg_exec_realizefn(CPUState *cpu, Error **errp) { static bool tcg_target_initialized; CPUClass *cc =3D CPU_GET_CLASS(cpu); @@ -1105,6 +1105,8 @@ void tcg_exec_realizefn(CPUState *cpu, Error **errp) tcg_iommu_init_notifier_list(cpu); #endif /* !CONFIG_USER_ONLY */ /* qemu_plugin_vcpu_init_hook delayed until cpu_index assigned. */ + + return true; } =20 /* undo the initializations in reverse order */ --=20 2.34.1 From nobody Fri May 17 08:39:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1694900660; cv=none; d=zohomail.com; s=zohoarc; b=WJ+349/8fZIf2Xy3SeIAqhrZmbO8OZeCG8p1+4CTuiPVf4rtoI2gn8/L5gQkEMir6h80swjjkjJaRjSv9KY3TIyA9em0BcyxjINtDSg7CRdrD2xOJwmnd8WTpC3XmBIY+yHRqVvDHz1nYvc4mqgUpWIWndW9yISEG1c1CPMVU/k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694900660; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/vqtkvJT/Vw/H5/mpmX6Mg0BjPMCG8MlnFWEAZngwVE=; b=BGwu0Jvsizyfw1NQglExCO0qAXwJc6reCWGj1VBX93/MnUjCz/fDUZ9nOn3M/UJI41JVDQOIoEjD08jpep0U/KUTH5s42NjO+AlmBbrLxes6+9T8Elaw3JV97B4PvGgpOS7p/Yr2p2R6bbaQydBBYuMX/WCIdLFMC0UAxKfby5o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694900660188909.3186440140712; Sat, 16 Sep 2023 14:44:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qhd3n-0006Tw-0N; Sat, 16 Sep 2023 17:42:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qhd3E-0005FB-GW for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:42:05 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qhd3C-0000X0-H0 for qemu-devel@nongnu.org; Sat, 16 Sep 2023 17:42:04 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-68fb79ef55eso3072383b3a.0 for ; Sat, 16 Sep 2023 14:42:02 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.42.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:42:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900521; x=1695505321; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/vqtkvJT/Vw/H5/mpmX6Mg0BjPMCG8MlnFWEAZngwVE=; b=n+BkgR+qhBzCHIcmlgxhaJH/RKCgbvyUWORMjaBhYLW88hMQF6yRAAP1tBe4hilYtW d2oOYGOPyLflM41Gcr687D6DjWQ8lNe/tcGEcYKrQiKC6eG7vZ7WUldQabfALSR0sn4I 1MSbSnyi7sVNxpwKaGx2Pdz/odffefl+LYLH5aH67T+HiBtzvBvtu2fTdeQxF3imDb86 8G92BpPjsMcKQoT1kmM5lP7bDTG/zCLfvOHpcLRXOWRMSbk9D7wtOCE9L0aGOPiHG+4C w7rOQqW2Iw95kxf+oKAuuBdSHobN9hwAst75x82rEa4iSN0xkhgF4Req3ItPuA32a+xd rA/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900521; x=1695505321; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/vqtkvJT/Vw/H5/mpmX6Mg0BjPMCG8MlnFWEAZngwVE=; b=i6yzjk9ALXdpXPc/6wHijfgz/b7sI0rulrULDCcH6Mh+MmUoy2f0uPmeqieNT30kEM WQGC1KiUDVstrj1iXEwzHtVwtmHSHajYncn0xiGG0pd+N6+JAcgbv7RryJ4oD7ju14Zl M/aTFPjRY09s07Vj/HHA/Kgiy0285VdwCYlsDRniC1jv25Sb12ii6ViGu9YmLBSMixnY ZAlUB9tHyICnvGxsSK9TYR5Col1zcECJtQq20R8O6e8csxl9HvFql7jbiiJlHYuyNH6w 3CmwP1OzeGtqVysUxH90ffKzaJXC9lalZ5Mt9e8uQoJkj5gAMChqCY0Gc2HJINx1jlUd 3DaA== X-Gm-Message-State: AOJu0Yyy3YIs7k5cBdta/lQ7gykle0wt/L296LKYUB/z+bpquRCqZKZ5 QfOATWQAtn9/h5oyPr2t8EpoaOEdfMNP7ReQDHA= X-Google-Smtp-Source: AGHT+IHHWkkEcG43cmjohgmyerrsd6EDb86z8Fos3TLM0S2vCuwu+2kaqR1tvyvCIZyogV8Q8jo0yQ== X-Received: by 2002:a05:6a00:1490:b0:690:454a:dc7b with SMTP id v16-20020a056a00149000b00690454adc7bmr6779612pfu.28.1694900521393; Sat, 16 Sep 2023 14:42:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 39/39] accel/tcg: Restrict tcg_exec_[un]realizefn() to TCG Date: Sat, 16 Sep 2023 14:41:23 -0700 Message-Id: <20230916214123.525796-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900660764100003 From: Philippe Mathieu-Daud=C3=A9 We don't need to expose these TCG-specific methods to the whole code base. Register them as AccelClass handlers, they will be called by the generic accel_cpu_[un]realize() methods. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230915190009.68404-6-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/internal-target.h | 3 +++ include/exec/cpu-all.h | 2 -- accel/tcg/tcg-all.c | 2 ++ cpu-target.c | 8 -------- 4 files changed, 5 insertions(+), 10 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 932bbe4b63..4e36cf858e 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -80,6 +80,9 @@ bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, = uintptr_t pc); void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t host_pc); =20 +bool tcg_exec_realizefn(CPUState *cpu, Error **errp); +void tcg_exec_unrealizefn(CPUState *cpu); + /* Return the current PC from CPU, which may be cached in TB. */ static inline vaddr log_pc(CPUState *cpu, const TranslationBlock *tb) { diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 6c1db14842..5340907cfd 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -410,8 +410,6 @@ static inline bool tlb_hit(uint64_t tlb_addr, vaddr add= r) =20 /* accel/tcg/cpu-exec.c */ int cpu_exec(CPUState *cpu); -bool tcg_exec_realizefn(CPUState *cpu, Error **errp); -void tcg_exec_unrealizefn(CPUState *cpu); =20 /* Validate correct placement of CPUArchState. */ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) !=3D 0); diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index b32e0b80ec..a40e0aee37 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -227,6 +227,8 @@ static void tcg_accel_class_init(ObjectClass *oc, void = *data) AccelClass *ac =3D ACCEL_CLASS(oc); ac->name =3D "tcg"; ac->init_machine =3D tcg_init_machine; + ac->realize_cpu =3D tcg_exec_realizefn; + ac->unrealize_cpu =3D tcg_exec_unrealizefn; ac->allowed =3D &tcg_allowed; ac->gdbstub_supported_sstep_flags =3D tcg_gdbstub_supported_sstep_flag= s; =20 diff --git a/cpu-target.c b/cpu-target.c index b928bbed50..1a8e730bed 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -140,11 +140,6 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) return; } =20 - /* NB: errp parameter is unused currently */ - if (tcg_enabled()) { - tcg_exec_realizefn(cpu, errp); - } - /* Wait until cpu initialization complete before exposing cpu. */ cpu_list_add(cpu); =20 @@ -190,9 +185,6 @@ void cpu_exec_unrealizefn(CPUState *cpu) * accel_cpu_unrealize, which may free fields using call_rcu. */ accel_cpu_unrealize(cpu); - if (tcg_enabled()) { - tcg_exec_unrealizefn(cpu); - } } =20 /* --=20 2.34.1