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Thu, 14 Sep 2023 12:02:01 GMT Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3t411s85gu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Sep 2023 12:02:00 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 38EC1edj014126 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Sep 2023 12:01:40 GMT Received: from qc-i7.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Thu, 14 Sep 2023 05:01:39 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=Lqdl6Z1r2s58ylVKuHPXl/YcHu8ZddiHLMl9E7wr8vI=; b=jzqy/YPPUH7IIc/s2cFvpoSHIUVrXMgVkj0ZQVrJ/hBxkbdsb2t4M9hsV/aOJfPIOHCb FlwBURkKDHQNoyiqWfLIadSXRx+VCWdlmvCOfQHu3v1tF1ThBLf1F8RWyY76SlLcK0Cn GFrYjeZyksp5C+rh4WLJdGymfzYg2D7Fs8mJk/Pi2H+ubZ64fxS+f/CZBFbQfqFYNHrX 9H0HdDtskyLY6rsNmaOV9QL/swsfqLZW0bb7USTUdej6Kp3Ca5u/AqTrzrYpSD2Pb/k7 ozMWYSer3mXpsqoN8ZZ0UMHDMFwdAKliutmqQb184fTyXa7n9V6ZtsPQSJT1Z4w5cgye mA== From: Leif Lindholm To: CC: , Radoslaw Biernacki , Peter Maydell , Marcin Juszkiewicz Subject: [RFC PATCH 1/3] include/hw/arm: move BSA definitions to bsa.h Date: Thu, 14 Sep 2023 13:01:22 +0100 Message-ID: <20230914120124.55410-2-quic_llindhol@quicinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230914120124.55410-1-quic_llindhol@quicinc.com> References: <20230914120124.55410-1-quic_llindhol@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: HdSWgMbPp3FyKuawXKVXrTCiQXLgvhau X-Proofpoint-GUID: HdSWgMbPp3FyKuawXKVXrTCiQXLgvhau X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-14_09,2023-09-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 bulkscore=0 adultscore=0 phishscore=0 priorityscore=1501 impostorscore=0 mlxlogscore=352 lowpriorityscore=0 suspectscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309140103 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=quic_llindhol@quicinc.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1694693012265100005 Content-Type: text/plain; charset="utf-8" virt.h defines a number of IRQs that are ultimately described by Arm's Base System Architecture specification. Move these to a dedicated header so that they can be reused by other platforms that do the same. Include that header from virt.h to minimise churn. Signed-off-by: Leif Lindholm --- include/hw/arm/bsa.h | 35 +++++++++++++++++++++++++++++++++++ include/hw/arm/virt.h | 12 +----------- 2 files changed, 36 insertions(+), 11 deletions(-) create mode 100644 include/hw/arm/bsa.h diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h new file mode 100644 index 0000000000..8277b3a379 --- /dev/null +++ b/include/hw/arm/bsa.h @@ -0,0 +1,35 @@ +/* + * Common definitions for Arm Base System Architecture (BSA) platforms. + * + * Copyright (c) 2015 Linaro Limited + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + * + */ + +#ifndef QEMU_ARM_BSA_H +#define QEMU_ARM_BSA_H + +#define ARCH_GIC_MAINT_IRQ 9 + +#define ARCH_TIMER_VIRT_IRQ 11 +#define ARCH_TIMER_S_EL1_IRQ 13 +#define ARCH_TIMER_NS_EL1_IRQ 14 +#define ARCH_TIMER_NS_EL2_IRQ 10 + +#define VIRTUAL_PMU_IRQ 7 + +#define PPI(irq) ((irq) + 16) + +#endif /* QEMU_ARM_BSA_H */ diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index e1ddbea96b..f69239850e 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -34,6 +34,7 @@ #include "qemu/notify.h" #include "hw/boards.h" #include "hw/arm/boot.h" +#include "hw/arm/bsa.h" #include "hw/block/flash.h" #include "sysemu/kvm.h" #include "hw/intc/arm_gicv3_common.h" @@ -43,17 +44,6 @@ #define NUM_VIRTIO_TRANSPORTS 32 #define NUM_SMMU_IRQS 4 =20 -#define ARCH_GIC_MAINT_IRQ 9 - -#define ARCH_TIMER_VIRT_IRQ 11 -#define ARCH_TIMER_S_EL1_IRQ 13 -#define ARCH_TIMER_NS_EL1_IRQ 14 -#define ARCH_TIMER_NS_EL2_IRQ 10 - -#define VIRTUAL_PMU_IRQ 7 - -#define PPI(irq) ((irq) + 16) - /* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */ #define PVTIME_SIZE_PER_CPU 64 =20 --=20 2.30.2 From nobody Thu Oct 31 23:38:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1694693009; cv=none; d=zohomail.com; s=zohoarc; b=XqHo9rJ+3C/a5jehR/pOACBv79AylufA6ctN5JQUyHk/sT6BbZM7x83T7EQF76hg2c3eumRM09mNrc4rkVXqLWWDvjY2lPLCVg7WAj9e93FYlH30b8xbHl21JWBdSsSRiR6KA/XGWWJdTigfDiENECHeTWmflqob6yslXSehGxc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694693009; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3FGUYySYZxKnz78fstv0mHNiEKrlt5b7fwvduZANZIc=; b=TtMtyC+xvOwmg6eLaXCDcVCI6mHbav2g044+QIVdXuOdb2QFcp5EpXfsEzDmTECoT05DZeWEJ5q3jvYq397r4y+srWS9cKVBI32t9xzfCT4AXHb+RFZb9By5Y1Ax6q3fWH/p34Itvb+btF+FDyF/M/okVfJk7KBDXPrZe7YHAr4= ARC-Authentication-Results: i=1; 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Thu, 14 Sep 2023 12:01:55 GMT Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3t3wx18n5e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Sep 2023 12:01:54 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 38EC1gvE032547 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Sep 2023 12:01:42 GMT Received: from qc-i7.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Thu, 14 Sep 2023 05:01:41 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=3FGUYySYZxKnz78fstv0mHNiEKrlt5b7fwvduZANZIc=; b=ho4pmsTXUmBMc+i2QxGN3NKo54sGvDORHZJs93a7CNFePxTg0aAfctZPUcJKvrYxoxtX zOEEGo2Sivn9MYJ3R7+9dV+FV938EmV4/0eG0e8QlZ+MT3v7/7yWtoxrk25BHZwXMgQO c7ulYMDIrbrV9FaD+HE8p5a94FbWA/J4iyxnna5M4pSLfcA1HrkNGWeVGYllZ+SGA6X+ O538qHAOyoYZcOakqQL2cdItew6eTe1qeey/JBi15seaphIxNfEdeCFpGQMzLGW622FC kObyTebkyqT0VKuCRr4i44ej1dQJISWlwH6XrmRjaCGToB0sKTgOriHBDPAF1QVJJKH5 YA== From: Leif Lindholm To: CC: , Radoslaw Biernacki , Peter Maydell , Marcin Juszkiewicz Subject: [RFC PATCH 2/3] {include/}hw/arm: refactor BSA/virt PPI logic Date: Thu, 14 Sep 2023 13:01:23 +0100 Message-ID: <20230914120124.55410-3-quic_llindhol@quicinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230914120124.55410-1-quic_llindhol@quicinc.com> References: <20230914120124.55410-1-quic_llindhol@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: J5q4eM-BUMTOjtzlJb56wZHm1Ta2mxnO X-Proofpoint-ORIG-GUID: J5q4eM-BUMTOjtzlJb56wZHm1Ta2mxnO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-14_09,2023-09-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 adultscore=0 clxscore=1015 phishscore=0 mlxlogscore=411 impostorscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309140103 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=quic_llindhol@quicinc.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1694693010532100002 Content-Type: text/plain; charset="utf-8" GIC Private Peripheral Interrupts (PPI) are defined as GIC INTID 16-31. As in, PPI0 is INTID16 .. PPI15 is INTID31. Arm's Base System Architecture specification (BSA) lists the mandated and recommended private interrupt IDs by INTID, not by PPI index. But current definitions in qemu define them by PPI index, complicating cross referencing. Meanwhile, the PPI(x) macro counterintuitively adds 16 to the input value, converting a PPI index to an INTID. Resolve this by redefining the BSA-allocated PPIs by their INTIDs, inverting the logic of the PPI(x) macro and flipping where it is used. Signed-off-by: Leif Lindholm --- hw/arm/virt-acpi-build.c | 4 ++-- hw/arm/virt.c | 9 +++++---- include/hw/arm/bsa.h | 14 +++++++------- 3 files changed, 14 insertions(+), 13 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 6b674231c2..963c58a88a 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -729,9 +729,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) for (i =3D 0; i < MACHINE(vms)->smp.cpus; i++) { ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i)); uint64_t physical_base_address =3D 0, gich =3D 0, gicv =3D 0; - uint32_t vgic_interrupt =3D vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : = 0; + uint32_t vgic_interrupt =3D vms->virt ? ARCH_GIC_MAINT_IRQ : 0; uint32_t pmu_interrupt =3D arm_feature(&armcpu->env, ARM_FEATURE_P= MU) ? - PPI(VIRTUAL_PMU_IRQ) : 0; + VIRTUAL_PMU_IRQ : 0; =20 if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { physical_base_address =3D memmap[VIRT_GIC_CPU].base; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 8ad78b23c2..bb70f3eec8 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -815,23 +815,24 @@ static void create_gic(VirtMachineState *vms, MemoryR= egion *mem) for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { qdev_connect_gpio_out(cpudev, irq, qdev_get_gpio_in(vms->gic, - ppibase + timer_irq[irq= ])); + ppibase + + PPI(timer_irq[irq]))); } =20 if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { qemu_irq irq =3D qdev_get_gpio_in(vms->gic, - ppibase + ARCH_GIC_MAINT_IRQ); + ppibase + PPI(ARCH_GIC_MAINT_I= RQ)); qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interru= pt", 0, irq); } else if (vms->virt) { qemu_irq irq =3D qdev_get_gpio_in(vms->gic, - ppibase + ARCH_GIC_MAINT_IRQ); + ppibase + PPI(ARCH_GIC_MAINT_I= RQ)); sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); } =20 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, qdev_get_gpio_in(vms->gic, ppibase - + VIRTUAL_PMU_IRQ)); + + PPI(VIRTUAL_PMU_IRQ= ))); =20 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); sysbus_connect_irq(gicbusdev, i + smp_cpus, diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h index 8277b3a379..b7db1cacf1 100644 --- a/include/hw/arm/bsa.h +++ b/include/hw/arm/bsa.h @@ -21,15 +21,15 @@ #ifndef QEMU_ARM_BSA_H #define QEMU_ARM_BSA_H =20 -#define ARCH_GIC_MAINT_IRQ 9 +#define ARCH_GIC_MAINT_IRQ 25 =20 -#define ARCH_TIMER_VIRT_IRQ 11 -#define ARCH_TIMER_S_EL1_IRQ 13 -#define ARCH_TIMER_NS_EL1_IRQ 14 -#define ARCH_TIMER_NS_EL2_IRQ 10 +#define ARCH_TIMER_VIRT_IRQ 27 +#define ARCH_TIMER_S_EL1_IRQ 29 +#define ARCH_TIMER_NS_EL1_IRQ 30 +#define ARCH_TIMER_NS_EL2_IRQ 26 =20 -#define VIRTUAL_PMU_IRQ 7 +#define VIRTUAL_PMU_IRQ 23 =20 -#define PPI(irq) ((irq) + 16) +#define PPI(irq) ((irq) - 16) =20 #endif /* QEMU_ARM_BSA_H */ --=20 2.30.2 From nobody Thu Oct 31 23:38:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=bsGlARh6QHZ0Je9J54hIEsTk3MK5Cqb6UxxMZeWc4Jk=; b=oDMeI0SRd1e1qygwgjTL4gRm/PoR/5n+YMASWGIxeE1Yg8PM3KONNGvRWLYTmEecWlGz AxCOM5VMsLOgQgo11eNBwpL0JNjrbz9Ws3OO9zA13uSMKhSXFGpLz7BUW2TDWr+utwgk s7p4/9MnITr/nHAQRswBiloR065SiqSTTPXmVmsxDSYvL8kRsVAC4N9tRNduIDYPtDNN 9988lAZSMKkDrKl25Npj/MfU/mNnntG8A+ltbsK3EGiqNn+gBdHc6dtX21gw2RGfVHaO 4BETFpxRtIQ4Ju8Nr1gBa9tAAevoQfmjw26PbkLJRSqGL4AYlydjG6ykCX13B2JPm7N5 yQ== From: Leif Lindholm To: CC: , Radoslaw Biernacki , Peter Maydell , Marcin Juszkiewicz Subject: [RFC PATCH 3/3] hw/arm/sbsa-ref: use bsa.h for PPI definitions Date: Thu, 14 Sep 2023 13:01:24 +0100 Message-ID: <20230914120124.55410-4-quic_llindhol@quicinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230914120124.55410-1-quic_llindhol@quicinc.com> References: <20230914120124.55410-1-quic_llindhol@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 2VHp2AZiAS2EJEnESTavuqOJoCW4BQj9 X-Proofpoint-GUID: 2VHp2AZiAS2EJEnESTavuqOJoCW4BQj9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-14_09,2023-09-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 mlxlogscore=480 priorityscore=1501 lowpriorityscore=0 suspectscore=0 adultscore=0 spamscore=0 impostorscore=0 clxscore=1015 phishscore=0 malwarescore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309140102 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=quic_llindhol@quicinc.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1694693059204100001 Content-Type: text/plain; charset="utf-8" Use the private peripheral interrupt definitions from bsa.h instead of defining them locally. Refactor to use PPI() to convert from INTID macro where necessary. Signed-off-by: Leif Lindholm Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/sbsa-ref.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index bc89eb4806..589b17e3bc 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -2,6 +2,7 @@ * ARM SBSA Reference Platform emulation * * Copyright (c) 2018 Linaro Limited + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * Written by Hongbo Zhang * * This program is free software; you can redistribute it and/or modify it @@ -30,6 +31,7 @@ #include "exec/hwaddr.h" #include "kvm_arm.h" #include "hw/arm/boot.h" +#include "hw/arm/bsa.h" #include "hw/arm/fdt.h" #include "hw/arm/smmuv3.h" #include "hw/block/flash.h" @@ -55,13 +57,6 @@ #define NUM_SMMU_IRQS 4 #define NUM_SATA_PORTS 6 =20 -#define VIRTUAL_PMU_IRQ 7 -#define ARCH_GIC_MAINT_IRQ 9 -#define ARCH_TIMER_VIRT_IRQ 11 -#define ARCH_TIMER_S_EL1_IRQ 13 -#define ARCH_TIMER_NS_EL1_IRQ 14 -#define ARCH_TIMER_NS_EL2_IRQ 10 - enum { SBSA_FLASH, SBSA_MEM, @@ -494,15 +489,18 @@ static void create_gic(SBSAMachineState *sms, MemoryR= egion *mem) for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { qdev_connect_gpio_out(cpudev, irq, qdev_get_gpio_in(sms->gic, - ppibase + timer_irq[irq= ])); + ppibase + + PPI(timer_irq[irq]))); } =20 + irq =3D qdev_get_gpio_in(sms->gic, + ppibase + PPI(ARCH_GIC_MAINT_IRQ)); qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",= 0, - qdev_get_gpio_in(sms->gic, ppibase - + ARCH_GIC_MAINT_IRQ)= ); - qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, - qdev_get_gpio_in(sms->gic, ppibase - + VIRTUAL_PMU_IRQ)); + irq); + + irq =3D qdev_get_gpio_in(sms->gic, + ppibase + PPI(VIRTUAL_PMU_IRQ)); + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, irq); =20 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); sysbus_connect_irq(gicbusdev, i + smp_cpus, --=20 2.30.2