[v4] hw/cxl: Support emulating 4 HDM decoders throughout topology

[PATCH v4 0/4] hw/cxl: Support emulating 4 HDM decoders throughout topology

Jonathan Cameron via posted 4 patches 7 months, 2 weeks ago

Diff against v1 v2 v3
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20230913132523.29780-1-Jonathan.Cameron@huawei.com

Maintainers: Jonathan Cameron <jonathan.cameron@huawei.com>, Fan Ni <fan.ni@samsung.com>

include/hw/cxl/cxl_component.h |  30 +++++-----
hw/cxl/cxl-component-utils.c   |  92 +++++++++++++++++++++++++----
hw/cxl/cxl-host.c              |  67 +++++++++++++++-------
hw/mem/cxl_type3.c             | 102 +++++++++++++++++++++++----------
4 files changed, 213 insertions(+), 78 deletions(-)

Expand all Fold all

[PATCH v4 0/4] hw/cxl: Support emulating 4 HDM decoders throughout topology

Posted by Jonathan Cameron via 7 months, 2 weeks ago

v4: Thanks to Fan and Philippe for reviews.
 - Add specification reference for interleave ways encodings
 - Gathered tags.

Note I'm sending this out quicker than I normally would because I want
to post another series on top of it and the additional comment will add
some fuzz for that.

For initial CXL emulation / kernel driver bring up a single Host-managed
Device Memory (HDM) decoder instance was sufficient as it let us test the
basic region creation code etc. More complex testing appropriate today
requires a more realistic configuration with multiple decoders.

The Linux kernel will use separate decoders for each memory type (and
shortly per DCD region) and for each interleave set within a memory type
or DCD region. 4 decoders are sufficient for most test cases today but
we may need to grow these further in future.

This patch set already allowed us to identify one kernel bug which is
now fixed.
https://lore.kernel.org/linux-cxl/168696507968.3590522.14484000711718573626.stgit@dwillia2-xfh.jf.intel.com/

Note that, whilst I'm proposing this series for upstream (based on
priorities of what we have out of tree) it hasn't previously been posted
so needs review. (I failed to send it out previously)

Based on: [PATCH 0/4] hw/cxl: Minor CXL emulation fixes and cleanup
Based on: [PATCH v2 0/3] hw/cxl: Add dummy ACPI QTG DSM

Based on: Message ID: 20230904132806.6094-1-Jonathan.Cameron@huawei.com
Based on: Message ID: 20230904161847.18468-1-Jonathan.Cameron@huawei.com

Jonathan Cameron (4):
  hw/cxl: Push cxl_decoder_count_enc() and cxl_decode_ig() into .c
  hw/cxl: Add utility functions decoder interleave ways and target
    count.
  hw/cxl: Fix and use same calculation for HDM decoder block size
    everywhere
  hw/cxl: Support 4 HDM decoders at all levels of topology

 include/hw/cxl/cxl_component.h |  30 +++++-----
 hw/cxl/cxl-component-utils.c   |  92 +++++++++++++++++++++++++----
 hw/cxl/cxl-host.c              |  67 +++++++++++++++-------
 hw/mem/cxl_type3.c             | 102 +++++++++++++++++++++++----------
 4 files changed, 213 insertions(+), 78 deletions(-)

-- 
2.39.2