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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2023 21:18:53.2843 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0660bd5f-268e-46e8-4533-08dbb3d5ddc5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5091 Received-SPF: softfail client-ip=2a01:111:f400:7e83::604; envelope-from=John.Allen@amd.com; helo=NAM02-DM3-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1694553607107100005 Content-Type: text/plain; charset="utf-8" For the most part, AMD hosts can use the same MCE injection code as Intel, = but there are instances where the qemu implementation is Intel specific. First,= MCE delivery works differently on AMD and does not support broadcast. Second, kvm_mce_inject generates MCEs that include a number of Intel specific status bits. Modify kvm_mce_inject to properly generate MCEs on AMD platforms. Reported-by: William Roche Signed-off-by: John Allen --- v3: - Update to latest qemu code that introduces using MCG_STATUS_RIPV in the case of a BUS_MCEERR_AR on a non-AMD machine. --- target/i386/helper.c | 4 ++++ target/i386/kvm/kvm.c | 17 +++++++++++------ 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/target/i386/helper.c b/target/i386/helper.c index 89aa696c6d..9547e2b09d 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -91,6 +91,10 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env) int family =3D 0; int model =3D 0; =20 + if (IS_AMD_CPU(env)) { + return 0; + } + cpu_x86_version(env, &family, &model); if ((family =3D=3D 6 && model >=3D 14) || family > 6) { return 1; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 639a242ad8..5fce74aac5 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -590,16 +590,21 @@ static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr,= int code) CPUState *cs =3D CPU(cpu); CPUX86State *env =3D &cpu->env; uint64_t status =3D MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | - MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; + MCI_STATUS_MISCV | MCI_STATUS_ADDRV; uint64_t mcg_status =3D MCG_STATUS_MCIP; int flags =3D 0; =20 - if (code =3D=3D BUS_MCEERR_AR) { - status |=3D MCI_STATUS_AR | 0x134; - mcg_status |=3D MCG_STATUS_RIPV | MCG_STATUS_EIPV; + if (!IS_AMD_CPU(env)) { + status |=3D MCI_STATUS_S; + if (code =3D=3D BUS_MCEERR_AR) { + status |=3D MCI_STATUS_AR | 0x134; + mcg_status |=3D MCG_STATUS_RIPV | MCG_STATUS_EIPV; + } else { + status |=3D 0xc0; + mcg_status |=3D MCG_STATUS_RIPV; + } } else { - status |=3D 0xc0; - mcg_status |=3D MCG_STATUS_RIPV; + mcg_status |=3D MCG_STATUS_EIPV | MCG_STATUS_RIPV; } =20 flags =3D cpu_x86_support_mca_broadcast(env) ? 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: John Allen To: CC: , , , , , , , Subject: [PATCH v4 2/3] i386: Explicitly ignore unsupported BUS_MCEERR_AO MCE on AMD guest Date: Tue, 12 Sep 2023 21:18:23 +0000 Message-ID: <20230912211824.90952-3-john.allen@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912211824.90952-1-john.allen@amd.com> References: <20230912211824.90952-1-john.allen@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4B:EE_|SA1PR12MB8966:EE_ X-MS-Office365-Filtering-Correlation-Id: 3a5a77ee-4d01-408e-e881-08dbb3d5e6af X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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envelope-from=John.Allen@amd.com; helo=NAM02-DM3-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1694553607646100007 Content-Type: text/plain; charset="utf-8" From: William Roche AMD guests can't currently deal with BUS_MCEERR_AO MCE injection as it panics the VM kernel. We filter this event and provide a warning message. Signed-off-by: William Roche --- v3: - New patch v4: - Remove redundant check for AO errors --- target/i386/kvm/kvm.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 5fce74aac5..7e9fc0cac5 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -604,6 +604,10 @@ static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, = int code) mcg_status |=3D MCG_STATUS_RIPV; } } else { + if (code =3D=3D BUS_MCEERR_AO) { + /* XXX we don't support BUS_MCEERR_AO injection on AMD yet */ + return; + } mcg_status |=3D MCG_STATUS_EIPV | MCG_STATUS_RIPV; } =20 @@ -668,8 +672,9 @@ void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, voi= d *addr) addr, paddr, "BUS_MCEERR_AR"); } else { warn_report("Guest MCE Memory Error at QEMU addr %p and " - "GUEST addr 0x%" HWADDR_PRIx " of type %s injected", - addr, paddr, "BUS_MCEERR_AO"); + "GUEST addr 0x%" HWADDR_PRIx " of type %s %s", + addr, paddr, "BUS_MCEERR_AO", + IS_AMD_CPU(env) ? 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charset="utf-8" Add cpuid bit definition for the SUCCOR feature. This cpuid bit is required= to be exposed to guests to allow them to handle machine check exceptions on AMD hosts. Reported-by: William Roche Reviewed-by: Joao Martins Signed-off-by: John Allen ---- v2: - Add "succor" feature word. - Add case to kvm_arch_get_supported_cpuid for the SUCCOR feature. --- target/i386/cpu.c | 18 +++++++++++++++++- target/i386/cpu.h | 4 ++++ target/i386/kvm/kvm.c | 2 ++ 3 files changed, 23 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 00f913b638..d90d3a9489 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1029,6 +1029,22 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { .tcg_features =3D TCG_APM_FEATURES, .unmigratable_flags =3D CPUID_APM_INVTSC, }, + [FEAT_8000_0007_EBX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + NULL, "succor", NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .cpuid =3D { .eax =3D 0x80000007, .reg =3D R_EBX, }, + .tcg_features =3D 0, + .unmigratable_flags =3D 0, + }, [FEAT_8000_0008_EBX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -6554,7 +6570,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; case 0x80000007: *eax =3D 0; - *ebx =3D 0; + *ebx =3D env->features[FEAT_8000_0007_EBX]; *ecx =3D 0; *edx =3D env->features[FEAT_8000_0007_EDX]; break; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a6000e93bd..f5afc5e4fd 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -598,6 +598,7 @@ typedef enum FeatureWord { FEAT_7_1_EAX, /* CPUID[EAX=3D7,ECX=3D1].EAX */ FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ + FEAT_8000_0007_EBX, /* CPUID[8000_0007].EBX */ FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ FEAT_8000_0021_EAX, /* CPUID[8000_0021].EAX */ @@ -942,6 +943,9 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord= w, /* Packets which contain IP payload have LIP values */ #define CPUID_14_0_ECX_LIP (1U << 31) =20 +/* RAS Features */ +#define CPUID_8000_0007_EBX_SUCCOR (1U << 1) + /* CLZERO instruction */ #define CPUID_8000_0008_EBX_CLZERO (1U << 0) /* Always save/restore FP error pointers */ diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 7e9fc0cac5..15a642a894 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -477,6 +477,8 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint= 32_t function, */ cpuid_1_edx =3D kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); ret |=3D cpuid_1_edx & CPUID_EXT2_AMD_ALIASES; + } else if (function =3D=3D 0x80000007 && reg =3D=3D R_EBX) { + ret |=3D CPUID_8000_0007_EBX_SUCCOR; } else if (function =3D=3D KVM_CPUID_FEATURES && reg =3D=3D R_EAX) { /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't * be enabled without the in-kernel irqchip --=20 2.39.3