From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414710; cv=none; d=zohomail.com; s=zohoarc; b=V1Dv0Dq94GeIeYg4QhLiCEMVRQJg5Ye4Meh/91xbgUl/sFI7hJmuUHWt3EEKxQziyRDyhx6xw242GeARg9rxWqJ3DOVFo9x038HKI/M4aqPNQrBlKLvREZcORkuCu57smUOl8g3xjxgp6ZHOPZGILWR+hyFjykQvXVNz0CMCb8I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414710; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2hidEe0WK9qfQspdXyERizbv/cOtqOtrvyLGVTGCseA=; b=lW38BV+bn21cB8v3TsmDaUFY3Nnzq6/m+/05bmxPOemDq6W6QRinpSjleb3T6dECngREpHzbbZ5Lf2G+gVIGLXiEgGHlkYH+EVMv/X0b4kgy+je8Duz6A9i8FrhSGLFrDCSW4o59Krtp4ySybDfywtyOf1CQv2EwRKhCYSTafnQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414710587331.07830324484235; Sun, 10 Sep 2023 23:45:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfaeD-0000An-RW; Mon, 11 Sep 2023 02:43:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfaeC-0000AY-4A for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:43:48 -0400 Received: from mail-oi1-x22e.google.com ([2607:f8b0:4864:20::22e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfae9-0004Qs-Hn for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:43:47 -0400 Received: by mail-oi1-x22e.google.com with SMTP id 5614622812f47-3a76d882080so3181681b6e.2 for ; Sun, 10 Sep 2023 23:43:43 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.43.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:43:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414621; x=1695019421; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2hidEe0WK9qfQspdXyERizbv/cOtqOtrvyLGVTGCseA=; b=sY7tD6veAv+U4XCKMIoc1O9ZHWNkm0yScI1mAGlGuOS8O3jI+qH+sZlfNtzQ+Nysaz NfHBOy7YSnsuC1vwDjAvl1FfDs2RQcuOXP80R96N7mYl8Sp1mIHNUBTo9RWSQPXbrEHe ESYsWt6MtAQ4YGc+NuW2595X48PLxYZDui2ewXBw6cceKfTCYEjbqUBFmrx9hvQIPyTq kNuK3INhEcb3l5i43hdyDza00VYTD2tskdDpiZhmlw15pCfEiYSEKIIlxqxu9Wpn2Cy4 dee27EQmKPRanEHMMW3fQnaV1Jg1p1dEevKWV+ykk5PkZ0kCqWPD1R/I62J28Fl0ElKb Xjvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414621; x=1695019421; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2hidEe0WK9qfQspdXyERizbv/cOtqOtrvyLGVTGCseA=; b=rk5fNS3zGfh5/2GhnmamVg1/F390ExT+FhcX7RVqIJ7XYgOnAlgZfq3ucQif6o0s26 yuJw9HoIO4yUG5WmdpyYnuTfEj45+TQv8GbZtBvRzTbR6kEyfimfh/pdlmCZVoc8BAz7 81tzjiSz7RfqGzIzkBKgFM+njZzVJwaAksq6pm1P8/6j/XwlUhnNRORuQVqKd0An7EoU ACY9ooXsKhRuRyDzWysDg+/UblX/PVmCn5Cf5kVSEQLH18rz9j3HC5XEoL6Fdi2JOSuZ snTApFNEDsQ4fUF8UvUowacawNNBLLtLDwkit2+O7736MlQY/ldJItFG/ott34KlLcLi AULg== X-Gm-Message-State: AOJu0YzSmZjm6+mSE2AzN8WMIzkNOwUYCpi8AnATWRO/mERQzMbeeO/t 759lWXElNRmfWuqxaT7yw7ECUQDw3qXNnw== X-Google-Smtp-Source: AGHT+IEqXBODj7T2Ze0wKrDTKCVIaT0E1RvEYMvQcwTHdGz1CyhAmd3AZHQOUjG3v6TAHFvUvubWnA== X-Received: by 2002:a05:6870:818f:b0:1b0:db2:189e with SMTP id k15-20020a056870818f00b001b00db2189emr11051662oae.17.1694414621508; Sun, 10 Sep 2023 23:43:41 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL v2 01/45] target/riscv/cpu.c: do not run 'host' CPU with TCG Date: Mon, 11 Sep 2023 16:42:36 +1000 Message-ID: <20230911064320.939791-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=alistair23@gmail.com; helo=mail-oi1-x22e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414711462100001 From: Daniel Henrique Barboza The 'host' CPU is available in a CONFIG_KVM build and it's currently available for all accels, but is a KVM only CPU. This means that in a RISC-V KVM capable host we can do things like this: $ ./build/qemu-system-riscv64 -M virt,accel=3Dtcg -cpu host --nographic qemu-system-riscv64: H extension requires priv spec 1.12.0 This CPU does not have a priv spec because we don't filter its extensions via priv spec. We shouldn't be reaching riscv_cpu_realize_tcg() at all with the 'host' CPU. We don't have a way to filter the 'host' CPU out of the available CPU options (-cpu help) if the build includes both KVM and TCG. What we can do is to error out during riscv_cpu_realize_tcg() if the user chooses the 'host' CPU with accel=3Dtcg: $ ./build/qemu-system-riscv64 -M virt,accel=3Dtcg -cpu host --nographic qemu-system-riscv64: 'host' CPU is not compatible with TCG acceleration Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230721133411.474105-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b93b04453..08db3d613f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1395,6 +1395,11 @@ static void riscv_cpu_realize_tcg(DeviceState *dev, = Error **errp) CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; =20 + if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) { + error_setg(errp, "'host' CPU is not compatible with TCG accelerati= on"); + return; + } + riscv_cpu_validate_misa_mxl(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414701; cv=none; d=zohomail.com; s=zohoarc; b=cFKpmN5SxJV4MUVAiU2ZmR2PlRr5H7RhOZZ+59aiAZZP9CsAR85W6xbropnjB4BR79TEQOoBzLcT3JD3WC7u7PveU0+CGb0ro8trRvW7A5Bmlc2oW0TlFSGoc99N+f4FJ6Nn/GSxz7R3NBvTP9Z4uL7vENdWJ/hZ2O1foYaI82k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414701; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vym8XbbEH4MOTDPO5rs9mKsM5VAOMq/9GygQwXQnKYA=; b=letNZ1l0DdmoheZFX1Y0rKsWC3fLlLxeVkPh2Fj5ywEcpe1s0KA4/SMzeTkmFseuLb3meqDKFgI+3tqFDsXQltzN+lmwT6jvWWochcIBNXrkWzrlkeDb/UE2+WaFNN8DxkcoZEWsljC2qrCuONDi/dhWWh7NKn5gLnXGbFL/89s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414701876906.2991142649446; Sun, 10 Sep 2023 23:45:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfaeF-0000BG-D0; Mon, 11 Sep 2023 02:43:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfaeD-0000Ao-V7 for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:43:49 -0400 Received: from mail-oa1-x29.google.com ([2001:4860:4864:20::29]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfaeB-0004R5-62 for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:43:49 -0400 Received: by mail-oa1-x29.google.com with SMTP id 586e51a60fabf-1d5c54160a8so230524fac.0 for ; Sun, 10 Sep 2023 23:43:46 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.43.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:43:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414625; x=1695019425; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vym8XbbEH4MOTDPO5rs9mKsM5VAOMq/9GygQwXQnKYA=; b=KC9/kyy9swxVPXMz4b5W4kcSDU4LVxIbnMnr+/kcyl0meUO4R5xk+RmDgBZZX6AzaP 1YxqtYiaFEP0TmND74H9TwqNczvWw4nlokjrFkEEtIqRL2aafLBv9I47EeKLMrBAHjfe d+2CeAZP6ORWp2vYcDzZ5UiWpYPW+dLlGoaCvpW1hd1uf09HZMCvztZCHyrtA+z/Ks9T RT4bwMbtd0zCZxfqD8TvwZur+Ahh3Vy7XsBk/deMr9UWO2ruX5UiWneTSShSYexXifhX prnYLg7JQHsUTphcEegaa3q9/r/gb39bEDFsMxknAmB+WBRVhBkg5Fjd9z15KopJPOom nhMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414625; x=1695019425; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vym8XbbEH4MOTDPO5rs9mKsM5VAOMq/9GygQwXQnKYA=; b=WyTWukWzMOUN92dXwBvKZvmxiOnlRwN9/5N60lZAeLCbQLATBwCFJsMMhseUh36hSq yAdh0LiOrdSxhVbV5M+XpNt58vHqwYfrjQ+z21Fo8Vb5qHSt8X+hJe2rXzhizJAH8I8r Eb7G3lpWc/dCXyItCisxSFewcwTpjpYhDBcK8HivOo+mMIEIQVASoWIIUd6T8eYIgX7/ /6ulTg+syP8X0s1BR0jtbXKeTU1PUDhnOXivv9jaOuRKh6lwY6FBGLONKCoNaeBoIi7x fifnLFKcpjOnssnA6L7/ypR5BhGXSjfoL16OQTqza0lkjrvSiJhEtwF0LhpV9iVe1lWy Vbkg== X-Gm-Message-State: AOJu0Yy1P7W/l3oYo9xSu7Rb5wy8K1NGwO7AwrAr/yQ9UMZ1e0i17t7r dSZncnLUVgZBrDVifvbRWnvDPI/bhVhTzg== X-Google-Smtp-Source: AGHT+IGLTw3M64I1rtN6GBwEA4GPPH5DxBv7UdRjuDpleizu6L2jaVTRRjJERvzkGkUTZwteoynj+A== X-Received: by 2002:a05:6870:b014:b0:196:45b7:9385 with SMTP id y20-20020a056870b01400b0019645b79385mr10440514oae.27.1694414625541; Sun, 10 Sep 2023 23:43:45 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Thomas Huth , Alistair Francis , Bin Meng , Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL v2 02/45] hw/char/riscv_htif: Fix printing of console characters on big endian hosts Date: Mon, 11 Sep 2023 16:42:37 +1000 Message-ID: <20230911064320.939791-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::29; envelope-from=alistair23@gmail.com; helo=mail-oa1-x29.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414704539100001 From: Thomas Huth The character that should be printed is stored in the 64 bit "payload" variable. The code currently tries to print it by taking the address of the variable and passing this pointer to qemu_chr_fe_write(). However, this only works on little endian hosts where the least significant bits are stored on the lowest address. To do this in a portable way, we have to store the value in an uint8_t variable instead. Fixes: 5033606780 ("RISC-V HTIF Console") Signed-off-by: Thomas Huth Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230721094720.902454-2-thuth@redhat.com> Signed-off-by: Alistair Francis --- hw/char/riscv_htif.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 37d3ccc76b..f96df40124 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -232,7 +232,8 @@ static void htif_handle_tohost_write(HTIFState *s, uint= 64_t val_written) s->tohost =3D 0; /* clear to indicate we read */ return; } else if (cmd =3D=3D HTIF_CONSOLE_CMD_PUTC) { - qemu_chr_fe_write(&s->chr, (uint8_t *)&payload, 1); + uint8_t ch =3D (uint8_t)payload; + qemu_chr_fe_write(&s->chr, &ch, 1); resp =3D 0x100 | (uint8_t)payload; } else { qemu_log("HTIF device %d: unknown command\n", device); --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414710; cv=none; d=zohomail.com; s=zohoarc; b=eu17HSEFxPEI9oa2K4uBVX2ODFZnRXtyj3FGZH95h28JEjx6pJX1RsL4P9X2ivlleEnEE757HQ2oQsSa5qH6J+mPdWtjyf+ocFiB0yOWi4TYt+/fHZnQgswj+SdxPfo8u1xt+NwG25IbYV57p9fAbU4WrNfk+sNOFbjhh+22Iss= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414710; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TjdxtVU3gNPjJmXFfAVRml366UxrtlzbUcZBrAyMCEU=; b=M636hlT3ZMxRfnqNSddz4/u76YU75yGGQnX52mkDnJT8WSEDjoVkLuzgLFqz2igGfG6OV1O8661gjzZ+Irzc714HBaUxdrJgFPa6Fiil86sA+sWRMdH+c73OLxEjU76IhncEwOIQ17WxyE/fc/QNA5NvJorAkzOjTFURJylWCN4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414710176985.4960476456127; Sun, 10 Sep 2023 23:45:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfaeH-0000Bc-Uq; Mon, 11 Sep 2023 02:43:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfaeG-0000BU-Rq for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:43:52 -0400 Received: from mail-oi1-x22d.google.com ([2607:f8b0:4864:20::22d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfaeE-0004RK-Ou for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:43:52 -0400 Received: by mail-oi1-x22d.google.com with SMTP id 5614622812f47-3a85c5854deso3171395b6e.0 for ; Sun, 10 Sep 2023 23:43:50 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.43.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:43:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414629; x=1695019429; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TjdxtVU3gNPjJmXFfAVRml366UxrtlzbUcZBrAyMCEU=; b=rrkF9KoRGYqQE6nn68Dz6IgQNwkf1VojbPKoiTlAFRFpSrsL8pTFcKLlHdkz8ISRHv JozrvQGEpAkdCyfZptj8vog1FnHDhLsewGIS1jxq9Mh5AesEZpARu0Dq8xTV93i8Lrwv nQEmRvCxIrcAxnJZsSLaY/LIvJ0PkCPDLak2uCCMs25MMwglVL0HMEO3QiF02alfoG0m WCc8H4tGT+1f4BPGIUxLmLg0f42NhukQF7NWGnBVlkXaupixNrv4xP9DLvSoexzOEDNi ysOLLtoKdW6GiRAUvJsgJFbb1zU3stSkG1kia+BwfT4EGBHZ4wCm1rKEsv9DKyJamCDG ZEyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414629; x=1695019429; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TjdxtVU3gNPjJmXFfAVRml366UxrtlzbUcZBrAyMCEU=; b=qUrlPKOVvC7i/u5KVtRkucZKnPOBxWn9niEU31Y1UrcOuoO8txRQ+PCnsE+QF1MVPd YELsidbfjbzYnkAJBhCE/lHv+7LD03Kd/NW8npBPudJYdlmLSltXK9Pgttdb0+wUe7ie uRBTvqgef7EU1YgfapMCIHpvMl4ghY5NRDEK49kNI0R2n/tfdt8JAut3qBj+wI2MBsSl sPgnCe6mnejx2LSa/EYUJ+aj0KMPQg9oBTrgZI4vE2X50J3KCO8AAamUFGei5ZOOD8u0 mAHevfMqYKZkt4dQNo/xRlWSCULU1u8bmDkqwb5l9UijJ+PcHmyfb/UkXrJeOKlkF/0R 7I4A== X-Gm-Message-State: AOJu0YzbMLcWOV0S9aGUQ1+lUbhdDPegU7t5xDnZk9uJEfjD0xoa2KV+ YnRQL6Fln9aU42/v77VBlxxObw6PLyM7uw== X-Google-Smtp-Source: AGHT+IFbxi1u0b2fGmog/ZAbQjSXcL7y3oPbFjAD0rFVukgXds0qPjrqHkD6nJNdW4adqbza89FdIg== X-Received: by 2002:aca:1216:0:b0:3a7:3ea1:b5a0 with SMTP id 22-20020aca1216000000b003a73ea1b5a0mr11063314ois.47.1694414629302; Sun, 10 Sep 2023 23:43:49 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Thomas Huth , Alistair Francis , Bin Meng , Daniel Henrique Barboza Subject: [PULL v2 03/45] hw/char/riscv_htif: Fix the console syscall on big endian hosts Date: Mon, 11 Sep 2023 16:42:38 +1000 Message-ID: <20230911064320.939791-4-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=alistair23@gmail.com; helo=mail-oi1-x22d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414711855100003 Content-Type: text/plain; charset="utf-8" From: Thomas Huth Values that have been read via cpu_physical_memory_read() from the guest's memory have to be swapped in case the host endianess differs from the guest. Fixes: a6e13e31d5 ("riscv_htif: Support console output via proxy syscall") Signed-off-by: Thomas Huth Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Daniel Henrique Barboza Message-Id: <20230721094720.902454-3-thuth@redhat.com> Signed-off-by: Alistair Francis --- hw/char/riscv_htif.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index f96df40124..40de6b8b77 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -30,6 +30,7 @@ #include "qemu/timer.h" #include "qemu/error-report.h" #include "exec/address-spaces.h" +#include "exec/tswap.h" #include "sysemu/dma.h" =20 #define RISCV_DEBUG_HTIF 0 @@ -209,11 +210,11 @@ static void htif_handle_tohost_write(HTIFState *s, ui= nt64_t val_written) } else { uint64_t syscall[8]; cpu_physical_memory_read(payload, syscall, sizeof(syscall)= ); - if (syscall[0] =3D=3D PK_SYS_WRITE && - syscall[1] =3D=3D HTIF_DEV_CONSOLE && - syscall[3] =3D=3D HTIF_CONSOLE_CMD_PUTC) { + if (tswap64(syscall[0]) =3D=3D PK_SYS_WRITE && + tswap64(syscall[1]) =3D=3D HTIF_DEV_CONSOLE && + tswap64(syscall[3]) =3D=3D HTIF_CONSOLE_CMD_PUTC) { uint8_t ch; - cpu_physical_memory_read(syscall[2], &ch, 1); + cpu_physical_memory_read(tswap64(syscall[2]), &ch, 1); qemu_chr_fe_write(&s->chr, &ch, 1); resp =3D 0x100 | (uint8_t)payload; } else { --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414866; cv=none; d=zohomail.com; s=zohoarc; b=ORU3IYmPGa4ciwR9YE3Psnz9BWJbMr0unp0DVgCVc6O+cE3BX9S4BM1zvJO9VwhX4qdUde4tgkfActHhmFUoaK1hvsBDNyDWZC1SI2h6rAwt+8pczsyhW30V6TpDXEmXwVkTDVq1bI53ow22NT04vPnq4HuLIsqKxEXB2ps2r24= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414866; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hxgyHj3pWoEqxLeuIclC5zzk9fMaICBkgpM0QGf+99I=; b=SfwLf89gB06/4MaJVSNET+VqITw6fRCq5km0pCIA62pfympXQehJwZMH/BrCYozs1j/tdWI3MicUC2ZKhyvP15l+QhZLruZfkrngKa8hFM37RYQmTnd10p1DpMhf8sVy2fjvXts8rZg5TcHfBQ8rE8sFjUddhNcnmnHmNEzn2MU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414866155156.48202649937957; Sun, 10 Sep 2023 23:47:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfaeL-0000C6-Hw; Mon, 11 Sep 2023 02:43:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfaeK-0000By-5y for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:43:56 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfaeI-0004RX-3g for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:43:55 -0400 Received: by mail-oi1-x22b.google.com with SMTP id 5614622812f47-3a7781225b4so2811071b6e.3 for ; Sun, 10 Sep 2023 23:43:53 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.43.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:43:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414633; x=1695019433; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hxgyHj3pWoEqxLeuIclC5zzk9fMaICBkgpM0QGf+99I=; b=QAs3LfpJQzpcoM4xoC+oMJ5HWyuUatkEpTuwj+YVkK+yfEfc2qVslSZUwfSNnZ4avJ 40BBakj3xX1kAst75xnWsKyBOgL7zWuPefEg7wKCvqapa/f/Vyl8bMZmoHdByIH3qtLT Dy8Sf0TJ7tbiPcRmExivp8dlokjFZk7HPiRwZcsg8GmFB/Gisz/Utyxy9Nev3Urswzcl JIoaJeJcHnK6yMAYSFTa3lwNtPo3Cn7Nk2TZ8CjdXMj2oxTiB1lml1w6lv/ufiGtmzlu w7qXWLq4loevQQhAj2yJRTU0/rKk+mkGl1PRKHEn0h1gjny0sAItQ/ZUi0W1MjJqNuIe ntOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414633; x=1695019433; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hxgyHj3pWoEqxLeuIclC5zzk9fMaICBkgpM0QGf+99I=; b=lkJ9SKmm4ro2rmXzS139M57OSgTJIBRbc+ZRHL6fkp5hCM7K569Ga48U8S9mIWy1yh uFkDhdvAM+5EbHNUaK+a23arTyHtDMGL5M6GZT2q30VBiLtld5qxvbAt6aLEzW3NgXCo 6H/XUF2Yxz4VjP7rCDttljUSrokCyXGRaiSIliiw11t2ys+iXhdFI3g47/BTGzHpck31 oHWRgSAIMp9pKm5WEhBdb2yyUhVrtDBuxOJWvA+5bUOXBncorlermFs6BTzJFJaTeLcE kz3h2RT3C4IECmmLj0LnaFUEIXGSWwhsFSlPZY8pVhuuKBCKQQRqtPBLJEd8/uY270E+ hZRQ== X-Gm-Message-State: AOJu0YyaGvYjpAsI6zc/q+ILqaO3an1hFSRqy1E4uraMj9qbzbmIT9/K aFv0xCocsjfCvKBv6w9r8xoiyBTCw8C/ew== X-Google-Smtp-Source: AGHT+IH1MVjmjYtGkKHWpOWoboUznBfuKBVTTKAStaC8L6FG9TiD+Tk0MwYuUuKTsbw2K+nOpIy+fQ== X-Received: by 2002:a05:6808:8f0:b0:3ab:83fe:e185 with SMTP id d16-20020a05680808f000b003ab83fee185mr4600347oic.33.1694414632766; Sun, 10 Sep 2023 23:43:52 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL v2 04/45] target/riscv/cpu.c: add zmmul isa string Date: Mon, 11 Sep 2023 16:42:39 +1000 Message-ID: <20230911064320.939791-5-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=alistair23@gmail.com; helo=mail-oi1-x22b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414867808100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza zmmul was promoted from experimental to ratified in commit 6d00ffad4e95. Add a riscv,isa string for it. Fixes: 6d00ffad4e95 ("target/riscv: move zmmul out of the experimental prop= erties") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230720132424.371132-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 08db3d613f..6d02e85102 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -88,6 +88,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), + ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa), ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin), --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414959; cv=none; d=zohomail.com; s=zohoarc; b=dGaxQJ1cN3c8Z0wBWq5Q2bjag4JY5QCBjQB9UnTCXVjjHt/9kCThBi5VhKLN8W/n9eALnCAUa58495m0Ihnq+kiCurHp02j0NlBtOmDjlxFlTrutPIAW/3VhkriZFGY2kaH6whiDwN1uDVhM7mN9X3MlOCT5Qw/JxIhoOUWcOmg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414959; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=R6nXUs6b9Y10nxctaibQIThdXKgyxUl6sbEBr/ysALI=; b=IDaHiD+MSq1ncPgoZO3QouyC4h3erh6UxCEGBsOxb4+5L1HY3OpPxyJFeukniUG2orTkVF1D6sGE5N8cd8xz+/881WydjOZfFuebXadnmxUy+tEibREQ7OgJLTih1Zs7j0JvHuvCeeuu+QQLr5xm2OmA++zyU9xqc8BElTsiRNo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414959667793.0379305177896; Sun, 10 Sep 2023 23:49:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfaeQ-0000CZ-D8; Mon, 11 Sep 2023 02:44:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfaeO-0000CR-MF for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:44:00 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfaeM-0004Ro-Db for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:44:00 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-68fb98745c1so509245b3a.1 for ; Sun, 10 Sep 2023 23:43:57 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.43.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:43:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414636; x=1695019436; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=R6nXUs6b9Y10nxctaibQIThdXKgyxUl6sbEBr/ysALI=; b=rWIMesH7o52tUCqOqMGKMGaZA1gdn8YrzpPdHwNs/T/40I/oPg7G3WaWPv27Z2EhNX L/UiookFiHXeGvuWT5t5QYi8mifCPso4peDCYxNlGamNoldkqmTmecvXS/q3im3/+kip dyvdXcj3iMHR1VwuXuiSOOe7UvqwKg7UNe0Lm8jOBfdMHKUPud4nxVWSXpuiU2U9LQrz FuzZYjkpVrCA04iKiBJJ/IhJCfKdgQXonzDsEMeb9Xf0qMJBIOiJhteVI+/ppRU5mMko UkNtOyu5oaDUZgFwQVGEOx2AelZFLnLm6IwUUEWPsbPyMqkg/QLnPEXtABVshJAAyLw4 E0BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414636; x=1695019436; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R6nXUs6b9Y10nxctaibQIThdXKgyxUl6sbEBr/ysALI=; b=SvlyIPPHtn8nyqboxGbN3AZF2BYyGpE8ld6vLEIfVhjSEgPgEUI9zcgTU7xXGFf1xq tmEo2nH8kN+wXVvGIsmw8FN+UzkIpug9NrZxVGRFt6zj2MlWKzXp4JfBRhLuaT0of7Oh 5ZCvoTMQQpc5/iXaeWKanSk0MwitULe/M26OMIXXTLPZAoP9TJStihbAC2hXaz8TdF3V b5/DIqTnMuGStZif3ipPOTYTumz/VI6ci7I1tVIRDDSGMdjswR1pmTL5Un0ZdYZitmp4 Xgj/3clTJhbt8HOvCFOeKPJPDlZLKMlFAiNvWaakJPU/sWlJpq1XNCRkDiHncBgSkAFK xybw== X-Gm-Message-State: AOJu0YyZlmO3yvdEOHJn8wvEo8TKkbnhIpH/Pu3Vh7nQ4/cJXadikSDm vpfJyVSPMQdXsBqPAbPbjOd7tcWVGfvxbA== X-Google-Smtp-Source: AGHT+IHgPOtMuyPLJoQ0hpWPNcEBYmsO3xVO4wxrZLbfxzpjshTf83bLbr6YIebk9tW+0rYyjX4bSQ== X-Received: by 2002:a05:6a00:22c2:b0:68e:2c3a:8775 with SMTP id f2-20020a056a0022c200b0068e2c3a8775mr8651206pfj.33.1694414636239; Sun, 10 Sep 2023 23:43:56 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL v2 05/45] target/riscv/cpu.c: add smepmp isa string Date: Mon, 11 Sep 2023 16:42:40 +1000 Message-ID: <20230911064320.939791-6-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414960661100003 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza The cpu->cfg.epmp extension is still experimental, but it already has a 'smepmp' riscv,isa string. Add it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis Message-Id: <20230720132424.371132-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6d02e85102..921c19e6cd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -130,6 +130,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), + ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414774; cv=none; d=zohomail.com; s=zohoarc; b=LhwoSlgYi/CJWBfUxQSyFGEFHJc9WzJnH7EH6tr2A+tAeirVFSg7FEPVgXP/AXKUzrLrK0vBZwpJVi6C3LagXtSSQbxDE5Vj7lAr/u9FD2B9Z+YHu5k45ZFhX9YLJ+AuD8QHndT8DtnQXsUc8RjAsC7aGZsZmUcz/9tFP9pZEtQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414774; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wJk34toFNyidTQI3XnnaKroUPxNRe6WC7SlLZ/NA1WQ=; b=TXUzDEujQu++8Y39wNVHrE6b4kxnKvmKx5XMDylIg9MSvmIYDtT7VNXv+hxy4T3c7NJo9wFGKpF1OnX7rpYuOKDuM9n7EJ0xos7mEUA6leSfqzJ50acPxVUzx87VIyyJbC6vPUyQZUxHG6Hp/Vleu9Iu6YbRwwl7RXh6lwN+btI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169441477464662.5879341883026; Sun, 10 Sep 2023 23:46:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfaeS-0000D2-07; Mon, 11 Sep 2023 02:44:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfaeR-0000Cs-9D for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:44:03 -0400 Received: from mail-ot1-x32f.google.com ([2607:f8b0:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfaeP-0004Rw-82 for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:44:03 -0400 Received: by mail-ot1-x32f.google.com with SMTP id 46e09a7af769-6bf58009a8dso2890271a34.1 for ; Sun, 10 Sep 2023 23:44:00 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.43.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:43:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414640; x=1695019440; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wJk34toFNyidTQI3XnnaKroUPxNRe6WC7SlLZ/NA1WQ=; b=LCDbqOaaEe/b5xs2y0XNNBiDLlO+oMv9THFjngFeJMyHbMBT6usgluCZISKH2G6Wbb 9w4J72IJ6CisPS9ugpy4bbp56MkeQ7JlD9Si7GfPlBn/dikmkOvosxGDTWrvYKziyS/a Cejk/DFVN9epTlhbfkXSmVC52QuXNpMbbJ35lD0vpnUwdRDQJvGveMe1zAgE58MVKulK bLE9thJrLLri8RgR7UyxBKNNrXNjSTitdCduD8R+RT+qyamirfNJ4YgO0ZyDrO5Ha5D2 A8n0tuSjp0LNJOzBdeeJd3LhLD5Mxbyds9SEY9APQSOkqTsPB7/AUqE3ltiJQhl64Yo9 3SjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414640; x=1695019440; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wJk34toFNyidTQI3XnnaKroUPxNRe6WC7SlLZ/NA1WQ=; b=FZoB2TFS6j8bU/mxNH+os8J3NItbNZIgFN0Gtww810DccuT1R4pKRvMOmaTj3jpLkq J/z/xg4g/xvK9owcWBPmt1Kt25jiEArxAlW3UIRozUQxv4KTVJwurT59PAo4SGMEfEE+ iQQpNbtNkWiUjiC8yULJUlgtvL4wKMmDwnWMydKqpRBot3Gu1SQ1mRGc1GWurUmnrVpS FlcfZJlkR02B1CeiKn9laR/tyNsWjNPQGjqxfJvp2dpLhAxbeG65hSstpcuoI+flIpM+ z31wKPTkC65wojxeFA1ZHD62GAzGEEh7gEDR5B4WywOi9q/dc1bj5hfKZHuHGqcCRvj4 9KHQ== X-Gm-Message-State: AOJu0YxiW7O/3rIwZ/mTgkaBaVDrePGtNI8U7OJ7vRDNzjJXYZz01N3p ChAOmacNVcfm4AY9pwKCw8fyeP2X4UkO4A== X-Google-Smtp-Source: AGHT+IH9RB2zLKdLYHjpIs5CYv+SYjtllCKTR2ZYE91scVk1Yo0AUA06WIGPMABn2QX+jDxdDQfBaw== X-Received: by 2002:a05:6830:18e7:b0:6b9:b1b1:135 with SMTP id d7-20020a05683018e700b006b9b1b10135mr9084411otf.13.1694414639824; Sun, 10 Sep 2023 23:43:59 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, LIU Zhiwei , Richard Henderson , Alistair Francis Subject: [PULL v2 06/45] target/riscv: Fix page_check_range use in fault-only-first Date: Mon, 11 Sep 2023 16:42:41 +1000 Message-ID: <20230911064320.939791-7-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=alistair23@gmail.com; helo=mail-ot1-x32f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414776904100003 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Commit bef6f008b98(accel/tcg: Return bool from page_check_range) converts integer return value to bool type. However, it wrongly converted the use of the API in riscv fault-only-first, where page_check_range < =3D 0, should be converted to !page_check_range. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-ID: <20230729031618.821-1-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index bc9e151aa9..379f03df06 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -584,7 +584,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, cpu_mmu_index(env, false)); if (host) { #ifdef CONFIG_USER_ONLY - if (page_check_range(addr, offset, PAGE_READ)) { + if (!page_check_range(addr, offset, PAGE_READ)) { vl =3D i; goto ProbeSuccess; } --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694415023; cv=none; d=zohomail.com; s=zohoarc; b=m47OMqjp9Gjqk1Xykbnfw9ye9uOXRWHAi6T2ZQZUa9MyibleCULHrao+yAPbi/hZBJBZlxOpSvFhFHGpvDb2tGOqYRI4uXhRoGMsYtoOQAJ3Z8kqZBZ2GffRYmbqPBMekOXEoRo/prfqgfrJahtknJu/JxYIAXz8Xkv9xPt/dLw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694415023; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Uzpy+y6xrg4iHp+mbMOAUvxFawE2a4d7du1HjRHTWNg=; b=HyU23aZYJGqolCH5980XmgFwT/jHaepn6CaBiDNKvFGU77E925FGQ1SjsMy2S2jQMNPpDwoZs8gur7qIAqlGTqtXG/bNB9DQCyAEcIOhaH7XcaslWe16r+r6LnrG49xWjiuKJSGfjp3JrZBTptY7RkgazGyqd9QXeZvru1zWNyE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694415023506188.32780795627912; Sun, 10 Sep 2023 23:50:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfaeX-0000Dt-Ha; Mon, 11 Sep 2023 02:44:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfaeW-0000Dc-FX for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:44:08 -0400 Received: from mail-oi1-x229.google.com ([2607:f8b0:4864:20::229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfaeU-0004SU-4y for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:44:08 -0400 Received: by mail-oi1-x229.google.com with SMTP id 5614622812f47-3aa1c04668bso2513581b6e.0 for ; Sun, 10 Sep 2023 23:44:05 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.44.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:44:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414644; x=1695019444; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Uzpy+y6xrg4iHp+mbMOAUvxFawE2a4d7du1HjRHTWNg=; b=Jyz9STwUF1MaoqpsvOVCH9xwAAPgk2WuQisO9keCfpd1oOARYdRHKiNEyZ+//Dl4ct N5ihNw4iPfD2pRlNY3S3j890Be8T2VjTByxsKLeOOYNGUooZbI59GkwyAa94lHSnkEvI InwBPDl5Uk6Ag39gnEfA6f0I8ZEvl1r2DkRVYzqXJUM8IipT7TwQR3IwWCOiy2XYO6Fv N3BeCQw/TTl364HG1JVnDD1iGFLduJAn4HSNfEIwFidAeabsac2XAdOkjVfNlaE9iolx jtaLvyqpS6TTEagchn0kWKlSX0c2RR+rJVK1/fhtJl+bmAM9EGFNDhUizI+uuDe74Bqs x2Hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414644; x=1695019444; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Uzpy+y6xrg4iHp+mbMOAUvxFawE2a4d7du1HjRHTWNg=; b=TsWZXLbYbwUHLS98WUeVID5GchB+FFZlmpEtcrlaxfTHoIBbwwfhRHro7zJ8sHPCpy tVIGnTm2WIb5K0fp6FqBqShTYBKwOGbm02hpTWvzXcrtPQxy6GgaKjpTSvV0sqZkyrh2 I3M9U/2ipygh+KFUlSDBe2KcShWMKd7guOk1FZ+IcKpTwDEbW1FqjIPuUd9X5kvMUIMk C3F1XqON3dUKAervLhH1mG/qFHphrLfvHWBVvoVbkh0sYgY+R2PGWAf8ZDRN6ZrZcmrI fD0Ad6g6JWq8qo9wRfxLHt6QS0vbpmK9jkQgAh6+rhVTxOEmGlFpcmJVIyhNtUO+uACj 2tQQ== X-Gm-Message-State: AOJu0YyU28kp30g+PVhpOr5c0pFcobd7t+cJ90BGYaIB9V84xigjNf+v +1O5pAHJd8OBOLoyTw/sQVDXE7qTZIZmsA== X-Google-Smtp-Source: AGHT+IFgyWRmq/qpuzRV+XRvmhnYclZDrJ7ZMX3pLX5nYqDwTtvLOyAIKAhT2xkhPWdPYeQbDxhQYQ== X-Received: by 2002:a05:6870:b401:b0:1d0:e3b7:395b with SMTP id x1-20020a056870b40100b001d0e3b7395bmr8545804oap.52.1694414644391; Sun, 10 Sep 2023 23:44:04 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Ard Biesheuvel , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Zewen Ye , Weiwei Li , Junqiang Wang , Alistair Francis Subject: [PULL v2 07/45] target/riscv: Use existing lookup tables for MixColumns Date: Mon, 11 Sep 2023 16:42:42 +1000 Message-ID: <20230911064320.939791-8-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=alistair23@gmail.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694415023844100001 From: Ard Biesheuvel The AES MixColumns and InvMixColumns operations are relatively expensive 4x4 matrix multiplications in GF(2^8), which is why C implementations usually rely on precomputed lookup tables rather than performing the calculations on demand. Given that we already carry those tables in QEMU, we can just grab the right value in the implementation of the RISC-V AES32 instructions. Note that the tables in question are permuted according to the respective Sbox, so we can omit the Sbox lookup as well in this case. Cc: Richard Henderson Cc: Philippe Mathieu-Daud=C3=A9 Cc: Zewen Ye Cc: Weiwei Li Cc: Junqiang Wang Signed-off-by: Ard Biesheuvel Reviewed-by: Richard Henderson Message-ID: <20230731084043.1791984-1-ardb@kernel.org> Signed-off-by: Alistair Francis --- include/crypto/aes.h | 7 +++++++ crypto/aes.c | 4 ++-- target/riscv/crypto_helper.c | 34 ++++------------------------------ 3 files changed, 13 insertions(+), 32 deletions(-) diff --git a/include/crypto/aes.h b/include/crypto/aes.h index 709d4d226b..381f24c902 100644 --- a/include/crypto/aes.h +++ b/include/crypto/aes.h @@ -30,4 +30,11 @@ void AES_decrypt(const unsigned char *in, unsigned char = *out, extern const uint8_t AES_sbox[256]; extern const uint8_t AES_isbox[256]; =20 +/* +AES_Te0[x] =3D S [x].[02, 01, 01, 03]; +AES_Td0[x] =3D Si[x].[0e, 09, 0d, 0b]; +*/ + +extern const uint32_t AES_Te0[256], AES_Td0[256]; + #endif diff --git a/crypto/aes.c b/crypto/aes.c index 836d7d5c0b..df4362ac60 100644 --- a/crypto/aes.c +++ b/crypto/aes.c @@ -272,7 +272,7 @@ AES_Td3[x] =3D Si[x].[09, 0d, 0b, 0e]; AES_Td4[x] =3D Si[x].[01, 01, 01, 01]; */ =20 -static const uint32_t AES_Te0[256] =3D { +const uint32_t AES_Te0[256] =3D { 0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU, 0xfff2f20dU, 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U, 0x60303050U, 0x02010103U, 0xce6767a9U, 0x562b2b7dU, @@ -607,7 +607,7 @@ static const uint32_t AES_Te4[256] =3D { 0xb0b0b0b0U, 0x54545454U, 0xbbbbbbbbU, 0x16161616U, }; =20 -static const uint32_t AES_Td0[256] =3D { +const uint32_t AES_Td0[256] =3D { 0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U, 0x3bab6bcbU, 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U, 0x2030fa55U, 0xad766df6U, 0x88cc7691U, 0xf5024c25U, diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c index 99d85a6188..4d65945429 100644 --- a/target/riscv/crypto_helper.c +++ b/target/riscv/crypto_helper.c @@ -25,29 +25,6 @@ #include "crypto/aes-round.h" #include "crypto/sm4.h" =20 -#define AES_XTIME(a) \ - ((a << 1) ^ ((a & 0x80) ? 0x1b : 0)) - -#define AES_GFMUL(a, b) (( \ - (((b) & 0x1) ? (a) : 0) ^ \ - (((b) & 0x2) ? AES_XTIME(a) : 0) ^ \ - (((b) & 0x4) ? AES_XTIME(AES_XTIME(a)) : 0) ^ \ - (((b) & 0x8) ? AES_XTIME(AES_XTIME(AES_XTIME(a))) : 0)) & 0xFF) - -static inline uint32_t aes_mixcolumn_byte(uint8_t x, bool fwd) -{ - uint32_t u; - - if (fwd) { - u =3D (AES_GFMUL(x, 3) << 24) | (x << 16) | (x << 8) | - (AES_GFMUL(x, 2) << 0); - } else { - u =3D (AES_GFMUL(x, 0xb) << 24) | (AES_GFMUL(x, 0xd) << 16) | - (AES_GFMUL(x, 0x9) << 8) | (AES_GFMUL(x, 0xe) << 0); - } - return u; -} - #define sext32_xlen(x) (target_ulong)(int32_t)(x) =20 static inline target_ulong aes32_operation(target_ulong shamt, @@ -55,23 +32,20 @@ static inline target_ulong aes32_operation(target_ulong= shamt, bool enc, bool mix) { uint8_t si =3D rs2 >> shamt; - uint8_t so; uint32_t mixed; target_ulong res; =20 if (enc) { - so =3D AES_sbox[si]; if (mix) { - mixed =3D aes_mixcolumn_byte(so, true); + mixed =3D be32_to_cpu(AES_Te0[si]); } else { - mixed =3D so; + mixed =3D AES_sbox[si]; } } else { - so =3D AES_isbox[si]; if (mix) { - mixed =3D aes_mixcolumn_byte(so, false); + mixed =3D be32_to_cpu(AES_Td0[si]); } else { - mixed =3D so; + mixed =3D AES_isbox[si]; } } mixed =3D rol32(mixed, shamt); --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414686; cv=none; d=zohomail.com; s=zohoarc; b=X+7yPUELEJCVKBo15im9+TGKEsDWatJWkk+K2iuaH3ogS+u5Iv1lttMgW+W5FU/jfg8J6ovIr/RnvirQJHVIasGTvFN19YtSm9mDpAPeRPAKYoaiCgcDxfDT7eQ8+AYsIGeQiYaVRR+liXy0fXttEaGlnpHhr28cD2yDLAVTSzE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414686; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sSeyTQyuBwnxsxZ+/qUq8xyLuzir65M8yR4fVevxw4Y=; b=SpxXedTQAQXVYeqVdJ/mSCZ0N+i0cJltNHGLJcas3uE1fUl0bPxjC88pGsUxk08/f8LBUF1LoDtkQAa3jfPIiLoQuKtMzZVI2RFVJ745lq7M41nBq8sHfg1Ia2wLbKOf5EoKZNbaEzu4yF15JiSIy3j/MJpu7zYMWmu3UE6ag1I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414686275862.5066811762498; Sun, 10 Sep 2023 23:44:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfaec-0000EW-1a; Mon, 11 Sep 2023 02:44:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfaeb-0000EM-9w for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:44:13 -0400 Received: from mail-oi1-x232.google.com ([2607:f8b0:4864:20::232]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfaeX-0004Si-TN for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:44:13 -0400 Received: by mail-oi1-x232.google.com with SMTP id 5614622812f47-3aa1254fb45so2806714b6e.2 for ; Sun, 10 Sep 2023 23:44:09 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. 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This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk Reviewed-by: Weiwei Li Signed-off-by: Max Chou Acked-by: Alistair Francis Message-ID: <20230711165917.2629866-2-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_internals.h | 182 +++++++++++++++++++++++++++++ target/riscv/vector_helper.c | 201 +------------------------------- target/riscv/vector_internals.c | 81 +++++++++++++ target/riscv/meson.build | 1 + 4 files changed, 265 insertions(+), 200 deletions(-) create mode 100644 target/riscv/vector_internals.h create mode 100644 target/riscv/vector_internals.c diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internal= s.h new file mode 100644 index 0000000000..749d138beb --- /dev/null +++ b/target/riscv/vector_internals.h @@ -0,0 +1,182 @@ +/* + * RISC-V Vector Extension Internals + * + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef TARGET_RISCV_VECTOR_INTERNALS_H +#define TARGET_RISCV_VECTOR_INTERNALS_H + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "cpu.h" +#include "tcg/tcg-gvec-desc.h" +#include "internals.h" + +static inline uint32_t vext_nf(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, NF); +} + +/* + * Note that vector data is stored in host-endian 64-bit chunks, + * so addressing units smaller than that needs a host-endian fixup. + */ +#if HOST_BIG_ENDIAN +#define H1(x) ((x) ^ 7) +#define H1_2(x) ((x) ^ 6) +#define H1_4(x) ((x) ^ 4) +#define H2(x) ((x) ^ 3) +#define H4(x) ((x) ^ 1) +#define H8(x) ((x)) +#else +#define H1(x) (x) +#define H1_2(x) (x) +#define H1_4(x) (x) +#define H2(x) (x) +#define H4(x) (x) +#define H8(x) (x) +#endif + +/* + * Encode LMUL to lmul as following: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + */ +static inline int32_t vext_lmul(uint32_t desc) +{ + return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); +} + +static inline uint32_t vext_vm(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VM); +} + +static inline uint32_t vext_vma(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VMA); +} + +static inline uint32_t vext_vta(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VTA); +} + +static inline uint32_t vext_vta_all_1s(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S); +} + +/* + * Earlier designs (pre-0.9) had a varying number of bits + * per mask value (MLEN). In the 0.9 design, MLEN=3D1. + * (Section 4.5) + */ +static inline int vext_elem_mask(void *v0, int index) +{ + int idx =3D index / 64; + int pos =3D index % 64; + return (((uint64_t *)v0)[idx] >> pos) & 1; +} + +/* + * Get number of total elements, including prestart, body and tail element= s. + * Note that when LMUL < 1, the tail includes the elements past VLMAX that + * are held in the same vector register. + */ +static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t d= esc, + uint32_t esz) +{ + uint32_t vlenb =3D simd_maxsz(desc); + uint32_t sew =3D 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); + int8_t emul =3D ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 : + ctzl(esz) - ctzl(sew) + vext_lmul(desc); + return (vlenb << emul) / esz; +} + +/* set agnostic elements to 1s */ +void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, + uint32_t tot); + +/* expand macro args before macro */ +#define RVVCALL(macro, ...) macro(__VA_ARGS__) + +/* (TD, T1, T2, TX1, TX2) */ +#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t +#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t +#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t +#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t + +/* operation of two vector elements */ +typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); + +#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ +static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ +{ \ + TX1 s1 =3D *((T1 *)vs1 + HS1(i)); \ + TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) =3D OP(s2, s1); \ +} + +void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivv2_fn *fn, uint32_t esz); + +/* generate the helpers for OPIVV */ +#define GEN_VEXT_VV(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + do_vext_vv(vd, v0, vs1, vs2, env, desc, \ + do_##NAME, ESZ); \ +} + +typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); + +/* + * (T1)s1 gives the real operator type. + * (TX1)(T1)s1 expands the operator type of widen or narrow operations. + */ +#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ +{ \ + TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) =3D OP(s2, (TX1)(T1)s1); \ +} + +void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivx2_fn fn, uint32_t esz); + +/* generate the helpers for OPIVX */ +#define GEN_VEXT_VX(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + do_vext_vx(vd, v0, s1, vs2, env, desc, \ + do_##NAME, ESZ); \ +} + +#endif /* TARGET_RISCV_VECTOR_INTERNALS_H */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 379f03df06..1f29236a63 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -27,6 +27,7 @@ #include "fpu/softfloat.h" #include "tcg/tcg-gvec-desc.h" #include "internals.h" +#include "vector_internals.h" #include =20 target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, @@ -73,68 +74,6 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_u= long s1, return vl; } =20 -/* - * Note that vector data is stored in host-endian 64-bit chunks, - * so addressing units smaller than that needs a host-endian fixup. - */ -#if HOST_BIG_ENDIAN -#define H1(x) ((x) ^ 7) -#define H1_2(x) ((x) ^ 6) -#define H1_4(x) ((x) ^ 4) -#define H2(x) ((x) ^ 3) -#define H4(x) ((x) ^ 1) -#define H8(x) ((x)) -#else -#define H1(x) (x) -#define H1_2(x) (x) -#define H1_4(x) (x) -#define H2(x) (x) -#define H4(x) (x) -#define H8(x) (x) -#endif - -static inline uint32_t vext_nf(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, NF); -} - -static inline uint32_t vext_vm(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VM); -} - -/* - * Encode LMUL to lmul as following: - * LMUL vlmul lmul - * 1 000 0 - * 2 001 1 - * 4 010 2 - * 8 011 3 - * - 100 - - * 1/8 101 -3 - * 1/4 110 -2 - * 1/2 111 -1 - */ -static inline int32_t vext_lmul(uint32_t desc) -{ - return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); -} - -static inline uint32_t vext_vta(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VTA); -} - -static inline uint32_t vext_vma(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VMA); -} - -static inline uint32_t vext_vta_all_1s(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S); -} - /* * Get the maximum number of elements can be operated. * @@ -153,21 +92,6 @@ static inline uint32_t vext_max_elems(uint32_t desc, ui= nt32_t log2_esz) return scale < 0 ? vlenb >> -scale : vlenb << scale; } =20 -/* - * Get number of total elements, including prestart, body and tail element= s. - * Note that when LMUL < 1, the tail includes the elements past VLMAX that - * are held in the same vector register. - */ -static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t d= esc, - uint32_t esz) -{ - uint32_t vlenb =3D simd_maxsz(desc); - uint32_t sew =3D 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); - int8_t emul =3D ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 : - ctzl(esz) - ctzl(sew) + vext_lmul(desc); - return (vlenb << emul) / esz; -} - static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad= dr) { return (addr & ~env->cur_pmmask) | env->cur_pmbase; @@ -200,20 +124,6 @@ static void probe_pages(CPURISCVState *env, target_ulo= ng addr, } } =20 -/* set agnostic elements to 1s */ -static void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t c= nt, - uint32_t tot) -{ - if (is_agnostic =3D=3D 0) { - /* policy undisturbed */ - return; - } - if (tot - cnt =3D=3D 0) { - return; - } - memset(base + cnt, -1, tot - cnt); -} - static inline void vext_set_elem_mask(void *v0, int index, uint8_t value) { @@ -223,18 +133,6 @@ static inline void vext_set_elem_mask(void *v0, int in= dex, ((uint64_t *)v0)[idx] =3D deposit64(old, pos, 1, value); } =20 -/* - * Earlier designs (pre-0.9) had a varying number of bits - * per mask value (MLEN). In the 0.9 design, MLEN=3D1. - * (Section 4.5) - */ -static inline int vext_elem_mask(void *v0, int index) -{ - int idx =3D index / 64; - int pos =3D index % 64; - return (((uint64_t *)v0)[idx] >> pos) & 1; -} - /* elements operations for load and store */ typedef void vext_ldst_elem_fn(CPURISCVState *env, abi_ptr addr, uint32_t idx, void *vd, uintptr_t retaddr); @@ -729,18 +627,11 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) * Vector Integer Arithmetic Instructions */ =20 -/* expand macro args before macro */ -#define RVVCALL(macro, ...) macro(__VA_ARGS__) - /* (TD, T1, T2, TX1, TX2) */ #define OP_SSS_B int8_t, int8_t, int8_t, int8_t, int8_t #define OP_SSS_H int16_t, int16_t, int16_t, int16_t, int16_t #define OP_SSS_W int32_t, int32_t, int32_t, int32_t, int32_t #define OP_SSS_D int64_t, int64_t, int64_t, int64_t, int64_t -#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t -#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t -#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t -#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t #define OP_SUS_B int8_t, uint8_t, int8_t, uint8_t, int8_t #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t @@ -764,16 +655,6 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) #define NOP_UUU_H uint16_t, uint16_t, uint32_t, uint16_t, uint32_t #define NOP_UUU_W uint32_t, uint32_t, uint64_t, uint32_t, uint64_t =20 -/* operation of two vector elements */ -typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); - -#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ -static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ -{ \ - TX1 s1 =3D *((T1 *)vs1 + HS1(i)); \ - TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ - *((TD *)vd + HD(i)) =3D OP(s2, s1); \ -} #define DO_SUB(N, M) (N - M) #define DO_RSUB(N, M) (M - N) =20 @@ -786,40 +667,6 @@ RVVCALL(OPIVV2, vsub_vv_h, OP_SSS_H, H2, H2, H2, DO_SU= B) RVVCALL(OPIVV2, vsub_vv_w, OP_SSS_W, H4, H4, H4, DO_SUB) RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB) =20 -static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, - CPURISCVState *env, uint32_t desc, - opivv2_fn *fn, uint32_t esz) -{ - uint32_t vm =3D vext_vm(desc); - uint32_t vl =3D env->vl; - uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); - uint32_t vta =3D vext_vta(desc); - uint32_t vma =3D vext_vma(desc); - uint32_t i; - - for (i =3D env->vstart; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, i)) { - /* set masked-off elements to 1s */ - vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); - continue; - } - fn(vd, vs1, vs2, i); - } - env->vstart =3D 0; - /* set tail elements to 1s */ - vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); -} - -/* generate the helpers for OPIVV */ -#define GEN_VEXT_VV(NAME, ESZ) \ -void HELPER(NAME)(void *vd, void *v0, void *vs1, \ - void *vs2, CPURISCVState *env, \ - uint32_t desc) \ -{ \ - do_vext_vv(vd, v0, vs1, vs2, env, desc, \ - do_##NAME, ESZ); \ -} - GEN_VEXT_VV(vadd_vv_b, 1) GEN_VEXT_VV(vadd_vv_h, 2) GEN_VEXT_VV(vadd_vv_w, 4) @@ -829,18 +676,6 @@ GEN_VEXT_VV(vsub_vv_h, 2) GEN_VEXT_VV(vsub_vv_w, 4) GEN_VEXT_VV(vsub_vv_d, 8) =20 -typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); - -/* - * (T1)s1 gives the real operator type. - * (TX1)(T1)s1 expands the operator type of widen or narrow operations. - */ -#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ -static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ -{ \ - TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ - *((TD *)vd + HD(i)) =3D OP(s2, (TX1)(T1)s1); \ -} =20 RVVCALL(OPIVX2, vadd_vx_b, OP_SSS_B, H1, H1, DO_ADD) RVVCALL(OPIVX2, vadd_vx_h, OP_SSS_H, H2, H2, DO_ADD) @@ -855,40 +690,6 @@ RVVCALL(OPIVX2, vrsub_vx_h, OP_SSS_H, H2, H2, DO_RSUB) RVVCALL(OPIVX2, vrsub_vx_w, OP_SSS_W, H4, H4, DO_RSUB) RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB) =20 -static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, - CPURISCVState *env, uint32_t desc, - opivx2_fn fn, uint32_t esz) -{ - uint32_t vm =3D vext_vm(desc); - uint32_t vl =3D env->vl; - uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); - uint32_t vta =3D vext_vta(desc); - uint32_t vma =3D vext_vma(desc); - uint32_t i; - - for (i =3D env->vstart; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, i)) { - /* set masked-off elements to 1s */ - vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); - continue; - } - fn(vd, s1, vs2, i); - } - env->vstart =3D 0; - /* set tail elements to 1s */ - vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); -} - -/* generate the helpers for OPIVX */ -#define GEN_VEXT_VX(NAME, ESZ) \ -void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ - void *vs2, CPURISCVState *env, \ - uint32_t desc) \ -{ \ - do_vext_vx(vd, v0, s1, vs2, env, desc, \ - do_##NAME, ESZ); \ -} - GEN_VEXT_VX(vadd_vx_b, 1) GEN_VEXT_VX(vadd_vx_h, 2) GEN_VEXT_VX(vadd_vx_w, 4) diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internal= s.c new file mode 100644 index 0000000000..9cf5c17cde --- /dev/null +++ b/target/riscv/vector_internals.c @@ -0,0 +1,81 @@ +/* + * RISC-V Vector Extension Internals + * + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "vector_internals.h" + +/* set agnostic elements to 1s */ +void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, + uint32_t tot) +{ + if (is_agnostic =3D=3D 0) { + /* policy undisturbed */ + return; + } + if (tot - cnt =3D=3D 0) { + return ; + } + memset(base + cnt, -1, tot - cnt); +} + +void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivv2_fn *fn, uint32_t esz) +{ + uint32_t vm =3D vext_vm(desc); + uint32_t vl =3D env->vl; + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); + uint32_t i; + + for (i =3D env->vstart; i < vl; i++) { + if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); + continue; + } + fn(vd, vs1, vs2, i); + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); +} + +void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivx2_fn fn, uint32_t esz) +{ + uint32_t vm =3D vext_vm(desc); + uint32_t vl =3D env->vl; + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); + uint32_t i; + + for (i =3D env->vstart; i < vl; i++) { + if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); + continue; + } + fn(vd, s1, vs2, i); + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 7f56c5f88d..c3801ee5e0 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -16,6 +16,7 @@ riscv_ss.add(files( 'gdbstub.c', 'op_helper.c', 'vector_helper.c', + 'vector_internals.c', 'bitmanip_helper.c', 'translate.c', 'm128_helper.c', --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414836; cv=none; d=zohomail.com; s=zohoarc; b=Z0a+S80UhhyGzlO6ja7GqDhhOBUWwOTM8C15lZe5IJ06iIAsL59qmCM5ArEq2h2VM42CFmHYyPzKV8WJsw4jfm0HHvKAM2nAZ8KURXLKV7Z4YugcLzshxaOS/jc0ZflwXe1LPdfmYfuA9O0PkSr2Mfak81JmcfvgwlrJd9oMowc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414836; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Hb86roSpucFtFVrGVIrvRJLLDNap4CZvVWBqWv3NMdw=; b=TikujOfSRrElOC6arV8yE1y3zdeZl3OT9bTUbxlcP6eEkVd4OTMiOHR2VBVYaMeYDLOSJ4ytAzcCHAB0W7xtkNoel69Ov2cF/rRiFAtOtP2MycjwBdpo4kPEz53WC+3VklyphbfzspMEsdpLjFBtztUnyJUoc9i4znnbFaUeoM8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414836936996.4366582619343; Sun, 10 Sep 2023 23:47:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfaeg-0000FB-4b; Mon, 11 Sep 2023 02:44:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfaef-0000Eu-5F for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:44:17 -0400 Received: from mail-oi1-x231.google.com ([2607:f8b0:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfaeb-0004Sw-QP for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:44:16 -0400 Received: by mail-oi1-x231.google.com with SMTP id 5614622812f47-3a9b41ffe12so3267026b6e.3 for ; Sun, 10 Sep 2023 23:44:13 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.44.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:44:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414652; x=1695019452; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hb86roSpucFtFVrGVIrvRJLLDNap4CZvVWBqWv3NMdw=; b=DWFznsYYtjbeYqwQorLCFHq3RuRhNgtR+mXAoiP3xUE3Fnbc0/ffFXpo7+CeGrMKDO SAAgYNpXx9Dh27scqHphMQTyKb0P5gVajlqam+jSVkTjVlwlIWN0YgNJrbA0vw3ofDXm UNdK2PJRpgp6WmpXQ7ipRnt446AqmqUHLCC6vskeSA4J7VvKHAcJUqKXk8uYGbCugiUl NPmGqvT12eM3wC5ZI4FZAS/EszEtNmayR6gvNZmTjxemK+8rQUyH7yDh7pjt4P+ytydc ifuINMuQcu9CwGvmAxzLozMu8Yz7sapf9v3AImuvOmINwsHtRLVKZPLXCgRRpFqzB5sW Ku8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414652; x=1695019452; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hb86roSpucFtFVrGVIrvRJLLDNap4CZvVWBqWv3NMdw=; b=d+jIa80EG/2Z0WdJbj8U1Cehh3tyyUvhgeYps0oCjBgu99a2FjQX5+JOum5FrYL+Qe uvfXp6/h062pVN1tPyPNBVIBAij9lzmIJX65YlKmwsYVfXuAR9v94yW5b7yMk2dUoLjD Zh9H0+6mggd2AX+azwBmGTFINszLarOl+LhLzaHZkDNKHs6UOfDDjiGEvTOOkBj4CvA9 sS+B6Q88HdLHqD/7YlvFCpCUfgPMDNP8S8j/3qqpORKvZP3TdI1wbXVy/CNSuKgijE/M yJe6vRfcmDs5sJ6P+SgmFNfNUlAmxzhvwVto+uL3erV5aIH4asBFl/5XRIsmaxsAGXsv eKpg== X-Gm-Message-State: AOJu0Yx9G0a8VSJYi8Mg5hJVEPeY5b5kylsU6XZAAqLlzh5g5gOUrGhv aLkpmMv9IHTRB0RMBqhNq4AwJ8KOOIHaFw== X-Google-Smtp-Source: AGHT+IHsr+Wzk987muubF4I5k35HYX/VaeEo+5ppPHVlfGzr6p6QYprLdzizBIIA+xUyz8GUugfpTg== X-Received: by 2002:a05:6808:14cb:b0:3a3:47c5:1de3 with SMTP id f11-20020a05680814cb00b003a347c51de3mr12363669oiw.49.1694414652326; Sun, 10 Sep 2023 23:44:12 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Kiran Ostrolenk , Richard Henderson , Alistair Francis , Weiwei Li , Max Chou Subject: [PULL v2 09/45] target/riscv: Refactor vector-vector translation macro Date: Mon, 11 Sep 2023 16:42:44 +1000 Message-ID: <20230911064320.939791-10-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=alistair23@gmail.com; helo=mail-oi1-x231.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414837291100003 Content-Type: text/plain; charset="utf-8" From: Kiran Ostrolenk Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be used in proceeding vector-crypto commits. Signed-off-by: Kiran Ostrolenk Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Signed-off-by: Max Chou Message-ID: <20230711165917.2629866-3-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 62 +++++++++++++------------ 1 file changed, 32 insertions(+), 30 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 6ab63f4442..f9dcb747a6 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1643,38 +1643,40 @@ GEN_OPIWX_WIDEN_TRANS(vwadd_wx) GEN_OPIWX_WIDEN_TRANS(vwsubu_wx) GEN_OPIWX_WIDEN_TRANS(vwsub_wx) =20 +static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t = vm, + gen_helper_gvec_4_ptr *fn, DisasContext *s) +{ + uint32_t data =3D 0; + TCGLabel *over =3D gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); + + data =3D FIELD_DP32(data, VDATA, VM, vm); + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); + tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1), + vreg_ofs(s, vs2), cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fn); + mark_vs_dirty(s); + gen_set_label(over); + return true; +} + /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */ /* OPIVV without GVEC IR */ -#define GEN_OPIVV_TRANS(NAME, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (CHECK(s, a)) { \ - uint32_t data =3D 0; \ - static gen_helper_gvec_4_ptr * const fns[4] =3D { \ - gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ - }; \ - TCGLabel *over =3D gen_new_label(); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ - \ - data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ - data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ - data =3D \ - FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\ - data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs1), \ - vreg_ofs(s, a->rs2), cpu_env, \ - s->cfg_ptr->vlen / 8, \ - s->cfg_ptr->vlen / 8, data, \ - fns[s->sew]); \ - mark_vs_dirty(s); \ - gen_set_label(over); \ - return true; \ - } \ - return false; \ +#define GEN_OPIVV_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + static gen_helper_gvec_4_ptr * const fns[4] =3D { = \ + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ + }; \ + return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\ + } \ + return false; \ } =20 /* --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Nazar Kazakov Reviewed-by: Weiwei Li Signed-off-by: Max Chou Acked-by: Alistair Francis Message-ID: <20230711165917.2629866-4-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 31 +------------------------ 1 file changed, 1 insertion(+), 30 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index f9dcb747a6..bf7384c065 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -617,7 +617,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, ui= nt32_t data, TCGv_i32 desc; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -786,7 +785,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1= , uint32_t rs2, TCGv_i32 desc; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -893,7 +891,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1,= uint32_t vs2, TCGv_i32 desc; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -1034,7 +1031,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uin= t32_t data, TCGv_i32 desc; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -1191,7 +1187,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3F= n *gvec_fn, return false; } =20 - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { @@ -1241,7 +1236,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, uint32_t vm, uint32_t data =3D 0; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -1405,7 +1399,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, ui= nt32_t vs2, uint32_t vm, uint32_t data =3D 0; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -1492,7 +1485,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr = *a, if (checkfn(s, a)) { uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -1575,7 +1567,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr = *a, if (opiwv_widen_check(s, a)) { uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -1648,7 +1639,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, ui= nt32_t vs2, uint32_t vm, { uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, vm); @@ -1842,7 +1832,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_w, \ }; \ TCGLabel *over =3D gen_new_label(); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2054,7 +2043,6 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_= v *a) gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d, }; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), @@ -2078,7 +2066,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) vext_check_ss(s, a->rd, 0, 1)) { TCGv s1; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 s1 =3D get_gpr(s, a->rs1, EXT_SIGN); @@ -2140,7 +2127,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, }; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 s1 =3D tcg_constant_i64(simm); @@ -2288,7 +2274,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm(s, RISCV_FRM_DYN); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2323,7 +2308,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, TCGv_i64 t1; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -2408,7 +2392,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm(s, RISCV_FRM_DYN); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2483,7 +2466,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm(s, RISCV_FRM_DYN); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2601,7 +2583,6 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); gen_set_rm_chkfrm(s, rm); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -2713,7 +2694,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) gen_helper_vmv_v_x_d, }; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 t1 =3D tcg_temp_new_i64(); @@ -2792,7 +2772,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm_chkfrm(s, FRM); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2844,7 +2823,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm(s, RISCV_FRM_DYN); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2912,7 +2890,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm_chkfrm(s, FRM); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2962,7 +2939,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm_chkfrm(s, FRM); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -3053,7 +3029,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) = \ uint32_t data =3D 0; \ gen_helper_gvec_4_ptr *fn =3D gen_helper_##NAME; \ TCGLabel *over =3D gen_new_label(); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ @@ -3224,7 +3199,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) require_vm(a->vm, a->rd)) { uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -3411,7 +3385,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_= x *a) TCGv s1; TCGLabel *over =3D gen_new_label(); =20 - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 t1 =3D tcg_temp_new_i64(); @@ -3468,8 +3441,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_= s_f *a) TCGv_i64 t1; TCGLabel *over =3D gen_new_label(); =20 - /* if vl =3D=3D 0 or vstart >=3D vl, skip vector register write ba= ck */ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + /* if vstart >=3D vl, skip vector register write back */ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 /* NaN-box f[rs1] */ @@ -3720,7 +3692,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, u= int8_t seq) uint32_t data =3D 0; gen_helper_gvec_3_ptr *fn; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 static gen_helper_gvec_3_ptr * const fns[6][4] =3D { --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414794; cv=none; d=zohomail.com; s=zohoarc; b=D3DTGGQa79xX1bmIGhX35Hm1eWhk3PozE0ipfgL0+0VMS/udOoAqFoBSQibd8FnicPNuFXKyCIcm+CYqzILlhoqxS/fYmRnSa6IVeXc6YcMiX5Qa3dVZEr/hrEHDMmrkY+RM21f1R6jOcSLKFi60zisaC2gq5y5upC0qHHvg8IE= ARC-Message-Signature: i=1; a=rsa-sha256; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.44.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:44:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414660; x=1695019460; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9eCj/NCScyqByJ/iYRppRDzEwAdB3DuVsfWQAxGoaj4=; b=Ju7wRtTzf5mBN/FD4NX/r+YpTtQgXq5JMWn/ceYrI7lv0MOWuuC+d9ItVM4Ob9Xs3o zBw9ryvP7KL+sPmqJRNLRLPv6ZNUExFeJv2ljIBaNuNAXKrl6wpEtsVGm8kikJ2Z1EiM Ay1no/v7QmvXcckMijRMpKbYn1QyL3mRzdqHJE5YLhBuKB4PIoaUDucZDJuVmmCPV5KY C4OgYjALWo6II5YDCEw6X+k2k0s7UL6RPLVn8qiZyRWo6DM20ju3ls98L4H7y+hXBnqs 4naa+DR7QFqDRDXdT2TOGLzq1uAXQK95kSNcpvl5AptZw3tjPFTaTH8HumXnQPCHcSPA DXIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414660; x=1695019460; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9eCj/NCScyqByJ/iYRppRDzEwAdB3DuVsfWQAxGoaj4=; b=podi6wczEPiLMTSkAEzo/BCQB/pZXrYCUrfrmqAcTFEYpygXWWZYSy480mHr7sSNrd elNXr9Wrn26X0xpPyQQ4cLa9yCx2O+myjcIMy7p9+4uMw9fT4lEMdKCdHDpsfwxuLhVy BBuVkuFP000rNWcAGoLJr907F1qtX7bqFPmlQRbevyKnkou41OQ4VvjQFLIu1dAbQOLS VpWiN2mvoDbrCytpYTKJywAt9ZZD1xqQ39C7y4HpU3Wsx440D1RxBGISINacOCPUYN19 Z3x8WBTnBS7mEXlvmGQc7XGLyNPI6QEoAhw8tg/tDHdQK/9O5MfTmAFOyu9Fh+SawbZh 62YA== X-Gm-Message-State: AOJu0YxTnJCQXF6ptO25EGc6ME/fwkBXwcg97sxS5iPlsLfpI0SvaRtf Dnuo0AWp7v9zoeFMiWThkH5xjmUwuiEXgA== X-Google-Smtp-Source: AGHT+IHHK6556Z7H0jgiji6760Yve5zWDurBQ813PoEfsExAlT67H+oC9qw0UGpK16ngoZhblAI39Q== X-Received: by 2002:a05:6358:5e1a:b0:13f:3368:92b4 with SMTP id q26-20020a0563585e1a00b0013f336892b4mr7708350rwn.27.1694414660279; Sun, 10 Sep 2023 23:44:20 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Lawrence Hunter , Nazar Kazakov , Max Chou , Alistair Francis Subject: [PULL v2 11/45] target/riscv: Add Zvbc ISA extension support Date: Mon, 11 Sep 2023 16:42:46 +1000 Message-ID: <20230911064320.939791-12-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c30; envelope-from=alistair23@gmail.com; helo=mail-oo1-xc30.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414795399100001 Content-Type: text/plain; charset="utf-8" From: Lawrence Hunter This commit adds support for the Zvbc vector-crypto extension, which consists of the following instructions: * vclmulh.[vx,vv] * vclmul.[vx,vv] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov Co-authored-by: Max Chou Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter Signed-off-by: Max Chou [max.chou@sifive.com: Exposed x-zvbc property] Message-ID: <20230711165917.2629866-5-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/riscv/helper.h | 6 +++ target/riscv/insn32.decode | 6 +++ target/riscv/cpu.c | 9 ++++ target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 59 ++++++++++++++++++++++ target/riscv/insn_trans/trans_rvvk.c.inc | 62 ++++++++++++++++++++++++ target/riscv/meson.build | 3 +- 8 files changed, 146 insertions(+), 1 deletion(-) create mode 100644 target/riscv/vcrypto_helper.c create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2bd9510ba3..d25b36a512 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -85,6 +85,7 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; bool ext_zve64d; + bool ext_zvbc; bool ext_zmmul; bool ext_zvfbfmin; bool ext_zvfbfwma; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c95adaf08a..6776777c4e 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1182,3 +1182,9 @@ DEF_HELPER_5(vfwcvtbf16_f_f_v, void, ptr, ptr, ptr, e= nv, i32) =20 DEF_HELPER_6(vfwmaccbf16_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwmaccbf16_vf, void, ptr, ptr, i64, ptr, env, i32) + +/* Vector crypto functions */ +DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e341fa9213..dd50d5a48c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -946,3 +946,9 @@ vfwcvtbf16_f_f_v 010010 . ..... 01101 001 ..... 101011= 1 @r2_vm # *** Zvfbfwma Standard Extension *** vfwmaccbf16_vv 111011 . ..... ..... 001 ..... 1010111 @r_vm vfwmaccbf16_vf 111011 . ..... ..... 101 ..... 1010111 @r_vm + +# *** Zvbc vector crypto extension *** +vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm +vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm +vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm +vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 921c19e6cd..f74e0926c2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -120,6 +120,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), + ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc), ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), @@ -1271,6 +1272,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu= , Error **errp) return; } =20 + if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) { + error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensio= ns"); + return; + } + if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn =3D true; cpu->cfg.ext_zkr =3D true; @@ -1853,6 +1859,9 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false), DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false), =20 + /* Vector cryptography extensions */ + DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), + DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 697df1be9e..7dbf173adb 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1094,6 +1094,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) #include "insn_trans/trans_rvzfa.c.inc" #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_rvk.c.inc" +#include "insn_trans/trans_rvvk.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_rvbf16.c.inc" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c new file mode 100644 index 0000000000..8b7c63d499 --- /dev/null +++ b/target/riscv/vcrypto_helper.c @@ -0,0 +1,59 @@ +/* + * RISC-V Vector Crypto Extension Helpers for QEMU. + * + * Copyright (C) 2023 SiFive, Inc. + * Written by Codethink Ltd and SiFive. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/host-utils.h" +#include "qemu/bitops.h" +#include "cpu.h" +#include "exec/memop.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "internals.h" +#include "vector_internals.h" + +static uint64_t clmul64(uint64_t y, uint64_t x) +{ + uint64_t result =3D 0; + for (int j =3D 63; j >=3D 0; j--) { + if ((y >> j) & 1) { + result ^=3D (x << j); + } + } + return result; +} + +static uint64_t clmulh64(uint64_t y, uint64_t x) +{ + uint64_t result =3D 0; + for (int j =3D 63; j >=3D 1; j--) { + if ((y >> j) & 1) { + result ^=3D (x >> (64 - j)); + } + } + return result; +} + +RVVCALL(OPIVV2, vclmul_vv, OP_UUU_D, H8, H8, H8, clmul64) +GEN_VEXT_VV(vclmul_vv, 8) +RVVCALL(OPIVX2, vclmul_vx, OP_UUU_D, H8, H8, clmul64) +GEN_VEXT_VX(vclmul_vx, 8) +RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmulh64) +GEN_VEXT_VV(vclmulh_vv, 8) +RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64) +GEN_VEXT_VX(vclmulh_vx, 8) diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc new file mode 100644 index 0000000000..552b08a2fd --- /dev/null +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -0,0 +1,62 @@ +/* + * RISC-V translation routines for the vector crypto extension. + * + * Copyright (C) 2023 SiFive, Inc. + * Written by Codethink Ltd and SiFive. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +/* + * Zvbc + */ + +#define GEN_VV_MASKED_TRANS(NAME, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, \ + gen_helper_##NAME, s); \ + } \ + return false; \ + } + +static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a) +{ + return opivv_check(s, a) && + s->cfg_ptr->ext_zvbc =3D=3D true && + s->sew =3D=3D MO_64; +} + +GEN_VV_MASKED_TRANS(vclmul_vv, vclmul_vv_check) +GEN_VV_MASKED_TRANS(vclmulh_vv, vclmul_vv_check) + +#define GEN_VX_MASKED_TRANS(NAME, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \ + gen_helper_##NAME, s); \ + } \ + return false; \ + } + +static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a) +{ + return opivx_check(s, a) && + s->cfg_ptr->ext_zvbc =3D=3D true && + s->sew =3D=3D MO_64; +} + +GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check) +GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check) diff --git a/target/riscv/meson.build b/target/riscv/meson.build index c3801ee5e0..660078bda1 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -21,7 +21,8 @@ riscv_ss.add(files( 'translate.c', 'm128_helper.c', 'crypto_helper.c', - 'zce_helper.c' + 'zce_helper.c', + 'vcrypto_helper.c' )) riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files(= 'kvm-stub.c')) =20 --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414780; cv=none; d=zohomail.com; s=zohoarc; b=O3+sZo7UtEV9Bwt96T1UvbPm1nsEAlf9ptiC+SMBH9Opoi6TdHDpDubXUxk9fo4gDlfF/EcX8KeIjFtzqg/OTlNsKUrpjbtiL3gqeYjq6R5p36ia27FvmJtHIYJy+Kdvaa5ch6l/qECsysM8rdozKr5AmBA0dvW95PF44s0Mc3c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414780; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nTIPyYdgqpfPvLBboQ7TsJe7pH9+EMYhManEx2tFzDg=; b=QJTaRP62tBdEzf+GM/u61V26mnNYiYTJgYr1L4OZm2qpo+MXB+8HrJtixX+kzUVdNVpGcOmSFKa60hSkqsrn0hDLFnyGG5PaFq3KVBT3TIgr9aAd7pfHFoQR/xLnaFNR9zqChFHn4mWyMSsAJ6Ag3/BSrmbasbwVvrA/ek08tXU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414780128820.3896433619061; Sun, 10 Sep 2023 23:46:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfaer-0000cW-8r; Mon, 11 Sep 2023 02:44:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfaeq-0000cC-K5 for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:44:28 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfaeo-0004Vz-8j for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:44:28 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-68cbbff84f6so3528861b3a.1 for ; Sun, 10 Sep 2023 23:44:25 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.44.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:44:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414664; x=1695019464; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nTIPyYdgqpfPvLBboQ7TsJe7pH9+EMYhManEx2tFzDg=; b=WDUOKm6ia2YpBYzk+ucDec2MhLsfE+L1EYxh03bAXBoBDlkNkdqoDjf3AMmQ501niZ s3t8P0isffuBLr5SK1X9LSjQK4GBA9Ix3huSBUx0AFjJsd7LgJBQUT6LMGQRZku8oVKn j+jWhsFYwMGjcsDofiEAxiXUqcHHBu0lCaPnA8gB8D5BZCuBL07a58QXGjRhZOPZ9kto 7ffd9vP7KyHHSu3he7n1dNE+yuw7MZ4jBNZPHkMLdfaJnPC60VzGNNLGI+E0UspdPjXB zM31p6HYyIqqeOcXmuRsUuC4zBlapweYvnDtYvcwl+yTTh3AHY929bsk4JxSE2J31FDm k2og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414664; x=1695019464; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nTIPyYdgqpfPvLBboQ7TsJe7pH9+EMYhManEx2tFzDg=; b=maSmhHw0fKVB6R42ynAtqzOdYs6rWwFUodkMcsvUXxXVIwjRRl2xIDtWIACw9glyjA 6gytnpFOiPOjrorHfxdRNwptGO6c6AHnh7+pgyzQoFT3UHkXYb6c2dwYVZSzd2kCfyc3 0q/6/ZK070SZ3HUMxGP1N6QQqyLhJCT6pcFhX5AdzYFarGvmAcBsyE1Su/rl/HeS7haR NSWE1WnIp+DFyKhDfRxB0XpsmQbganaIclCdpS+wUPTWke+m2OOSxgLsU5OFzwsPzA1L cy0GrnDVX3f+oGGwV5n3+zr5OkI57WanHx/KaVa7ao8ie+0UxsQ7U2Rh2XrIrq/SwW2l KWtA== X-Gm-Message-State: AOJu0YxqtUgD7WrnoohRmhrSL6Z6Hnsrs6dtEUC1krcgOsZNUSsUZ8V1 32aHBd56CIocXrkft10CnE6RQi9XDPufHQ== X-Google-Smtp-Source: AGHT+IEjWyZmGzMoiDvriRSPlBIy0FkULnBOAsBMEYOX61DPSCqz882UpcokJSqtMMKTbHkeRKnq9g== X-Received: by 2002:a05:6a20:2444:b0:14b:f78e:d061 with SMTP id t4-20020a056a20244400b0014bf78ed061mr11669321pzc.19.1694414664304; Sun, 10 Sep 2023 23:44:24 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Nazar Kazakov , Richard Henderson , Weiwei Li , Max Chou , Alistair Francis Subject: [PULL v2 12/45] target/riscv: Move vector translation checks Date: Mon, 11 Sep 2023 16:42:47 +1000 Message-ID: <20230911064320.939791-13-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=alistair23@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414781947100005 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions and into the corresponding macros. This enables the functions to be reused in proceeding commits without check duplication. Signed-off-by: Nazar Kazakov Reviewed-by: Richard Henderson Reviewed-by: Weiwei Li Signed-off-by: Max Chou Message-ID: <20230711165917.2629866-6-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 28 +++++++++++-------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index bf7384c065..641cf5da6f 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1183,9 +1183,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3F= n *gvec_fn, gen_helper_gvec_4_ptr *fn) { TCGLabel *over =3D gen_new_label(); - if (!opivv_check(s, a)) { - return false; - } =20 tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 @@ -1218,6 +1215,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ }; \ + if (!opivv_check(s, a)) { \ + return false; \ + } \ return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ } =20 @@ -1276,10 +1276,6 @@ static inline bool do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn, gen_helper_opivx *fn) { - if (!opivx_check(s, a)) { - return false; - } - if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { TCGv_i64 src1 =3D tcg_temp_new_i64(); =20 @@ -1301,6 +1297,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ }; \ + if (!opivx_check(s, a)) { \ + return false; \ + } \ return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ } =20 @@ -1432,10 +1431,6 @@ static inline bool do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn, gen_helper_opivx *fn, imm_mode_t imm_mode) { - if (!opivx_check(s, a)) { - return false; - } - if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s)); @@ -1453,6 +1448,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \ gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \ }; \ + if (!opivx_check(s, a)) { \ + return false; \ + } \ return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \ fns[s->sew], IMM_MODE); \ } @@ -1775,10 +1773,6 @@ static inline bool do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn, gen_helper_opivx *fn) { - if (!opivx_check(s, a)) { - return false; - } - if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { TCGv_i32 src1 =3D tcg_temp_new_i32(); =20 @@ -1800,7 +1794,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ }; \ - \ + if (!opivx_check(s, a)) { \ + return false; \ + } \ return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ } =20 --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.44.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:44:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414668; x=1695019468; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=efQOIBGtsWyc+ddZFa0dzw9L9TQODzu5kS/+kHoVuWs=; b=rTi15PN4HBIS+3LwdE9MPEUMhrCr6l6PltyOqYJt+Co6kuH3OeCIry7BSaFpfNLlwn 94uR0pLitbbWRHGcrM3Be1oVRJ5j5dXq3bc/ebIwtenF7CHZtdlPJ050cM6q70VAMR+o SCOtqWetXBBwABk3jKzYaazRKsnFViWl1vGYoBGbFXEG3WnHbSET8wUh6UoggvFBwPzV GQsrbIPozoJ6l2qcx5LtJ4PVg+91abyi2SVcup1n8S/8arkJOo/IkFJ8w6SnsUrALYGu y3k3c+J4FYPE2VwKyiB79R9IbVx+Yv3OmphYsj4i8hV0zK60vCe0mfUdDVGdnXF0n/QW 1/0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414668; x=1695019468; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=efQOIBGtsWyc+ddZFa0dzw9L9TQODzu5kS/+kHoVuWs=; b=hIYMm3ouaB7owRB4kXlyihQ07snGz3z9ighAwcehCs4yK5lYb0+U2k8Dk/zhvSJ9Hr ZjuRdIE4BeoEnYROFi2+TKsxTjF6lXqdAUhRXhpUUCgH20GsBoYuzBwf37yi2BoSlrL2 1ePUb1dfie7V1vDW+4fB7OacgyDP5tu99rkp++HUGiMlczG4292oCivCal8pfWux8l3W PDlDRfxjg8QBc9urTxBlw5fxpfqrpUk29s8cmsZxeBDz21tedtOhGpFDLIGwD+XLcjHH MLavw6ZXB3dtBEYXL+tRZsLAT2HL822imKCXIXeEQJs91QMhN5R47gw2tINCOOMksAQI DDbg== X-Gm-Message-State: AOJu0YxgiXBtClApTqxJqCXR9jK3XBhsmqdb6fx1MU7lApUR6qsVAxTv SrCCSu8iuVZKZsACNNgnqiAS0XzZmnEn9g== X-Google-Smtp-Source: AGHT+IGKGPkYdrasbn0utX4O0yjTSh6h6xMNvJqgsyrOP1UVGKtmz3gOU0GAvhr8A6tI0x4V5w9+dw== X-Received: by 2002:a05:6358:9916:b0:139:b1c8:a28a with SMTP id w22-20020a056358991600b00139b1c8a28amr10004673rwa.0.1694414668407; Sun, 10 Sep 2023 23:44:28 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Dickon Hood , Richard Henderson , Weiwei Li , Max Chou , Alistair Francis Subject: [PULL v2 13/45] target/riscv: Refactor translation of vector-widening instruction Date: Mon, 11 Sep 2023 16:42:48 +1000 Message-ID: <20230911064320.939791-14-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2b; envelope-from=alistair23@gmail.com; helo=mail-oo1-xc2b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414976955100007 Content-Type: text/plain; charset="utf-8" From: Dickon Hood Zvbb (implemented in later commit) has a widening instruction, which requires an extra check on the enabled extensions. Refactor GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing it. Signed-off-by: Dickon Hood Reviewed-by: Richard Henderson Reviewed-by: Weiwei Li Signed-off-by: Max Chou Message-ID: <20230711165917.2629866-7-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 52 +++++++++++-------------- 1 file changed, 23 insertions(+), 29 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 641cf5da6f..63404f61fc 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1526,30 +1526,24 @@ static bool opivx_widen_check(DisasContext *s, arg_= rmrr *a) vext_check_ds(s, a->rd, a->rs2, a->vm); } =20 -static bool do_opivx_widen(DisasContext *s, arg_rmrr *a, - gen_helper_opivx *fn) -{ - if (opivx_widen_check(s, a)) { - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); - } - return false; -} - -#define GEN_OPIVX_WIDEN_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - static gen_helper_opivx * const fns[3] =3D { \ - gen_helper_##NAME##_b, \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w \ - }; \ - return do_opivx_widen(s, a, fns[s->sew]); \ +#define GEN_OPIVX_WIDEN_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + static gen_helper_opivx * const fns[3] =3D { = \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w \ + }; \ + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s); \ + } \ + return false; \ } =20 -GEN_OPIVX_WIDEN_TRANS(vwaddu_vx) -GEN_OPIVX_WIDEN_TRANS(vwadd_vx) -GEN_OPIVX_WIDEN_TRANS(vwsubu_vx) -GEN_OPIVX_WIDEN_TRANS(vwsub_vx) +GEN_OPIVX_WIDEN_TRANS(vwaddu_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwadd_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwsubu_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwsub_vx, opivx_widen_check) =20 /* WIDEN OPIVV with WIDEN */ static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a) @@ -1997,9 +1991,9 @@ GEN_OPIVX_TRANS(vrem_vx, opivx_check) GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check) GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check) GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check) -GEN_OPIVX_WIDEN_TRANS(vwmul_vx) -GEN_OPIVX_WIDEN_TRANS(vwmulu_vx) -GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx) +GEN_OPIVX_WIDEN_TRANS(vwmul_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmulu_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx, opivx_widen_check) =20 /* Vector Single-Width Integer Multiply-Add Instructions */ GEN_OPIVV_TRANS(vmacc_vv, opivv_check) @@ -2015,10 +2009,10 @@ GEN_OPIVX_TRANS(vnmsub_vx, opivx_check) GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check) GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check) GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check) -GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx) -GEN_OPIVX_WIDEN_TRANS(vwmacc_vx) -GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx) -GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx) +GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmacc_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx, opivx_widen_check) =20 /* Vector Integer Merge and Move Instructions */ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.44.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:44:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414672; x=1695019472; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KCzcagA45q4P5ZXNWFhRkkRERr88WEyNrG4CtwWBxb4=; b=jZdKklWvr/rTas2sZm+Cc9uqJHphSsY737FQRMcHchnHvuzmO9FQf8223SAd04vYef ZDekAU9VGr7D+sjOkb4C5a8GWXQ6/3R2G9Y7BJg+zQA7c4xuZUlPGWk/teLupZCxRo9C NHZc5aYSkSymti6J4o0fBY/j4a5UrVW9j9rrD9P3g/TQvF5oFtvv8c3TOxon2tsbu42X j4NqnOJcbAseetK1xTzTWhKcUUr79MRtrEsmz8w4paDGADJVwzeAS4kuXteLvPe4Tq/h T9sPua3im0C5iqwIbsLEH7+Fhcmb5Rss/kmtlfiehn8pHLPd76PjA5MMxBibkDl7+Fp+ jHlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414672; x=1695019472; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KCzcagA45q4P5ZXNWFhRkkRERr88WEyNrG4CtwWBxb4=; b=JVdDpa8I+4Zv3jQem8dmi/hgk35XLbfp6BrYw+f1F6fsbtGoAgxDB1ykXnJB/WvwWh MAjJuAfaEKUYJOhOH3I+jiX6SbxiOwOzn44eu60N+m4BTzdKOzsHusAmnJedUnOG49Rd iYM5VSIRdzH8g4CkYdSaIuXfzq8717JEUh9QCa8ha3jkFeAWoOw/1N+18gMMVZ8C+ttZ 9szCzZVWbhdGINf772cDNiJFaJ4hONebfOcaKK4J2/7rqAv2mRERbrxYcM1HtASs6olK oILffpV0/4qRwjqeFtZ2caTud4H6S6gw+vSbvMjOjLrorWmL3EcbQTdip6OKxRUaTKaf ukrQ== X-Gm-Message-State: AOJu0YzdlJjLF1bgGd7geXxXNp1wR+IBK2Rc+pgLVR5O9IbToyFDvyeZ yyQfB6SKymbmjV0CWbD6JzlpW/I5NaK0Zw== X-Google-Smtp-Source: AGHT+IFVhMA9Lxr8HdIJ117S8+CjbJquvX1LVAkSZk23oclZ+Hjq5Ms0jHjuNnvj+8N85Tt0pCkJbw== X-Received: by 2002:a05:6a20:7f84:b0:154:8d7a:aeb3 with SMTP id d4-20020a056a207f8400b001548d7aaeb3mr8347785pzj.28.1694414672051; Sun, 10 Sep 2023 23:44:32 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Kiran Ostrolenk , Weiwei Li , Max Chou , Alistair Francis Subject: [PULL v2 14/45] target/riscv: Refactor some of the generic vector functionality Date: Mon, 11 Sep 2023 16:42:49 +1000 Message-ID: <20230911064320.939791-15-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=alistair23@gmail.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414844233100001 Content-Type: text/plain; charset="utf-8" From: Kiran Ostrolenk Move some macros out of `vector_helper` and into `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk Reviewed-by: Weiwei Li Signed-off-by: Max Chou Message-ID: <20230711165917.2629866-8-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/vector_internals.h | 46 +++++++++++++++++++++++++++++++++ target/riscv/vector_helper.c | 42 ------------------------------ 2 files changed, 46 insertions(+), 42 deletions(-) diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internal= s.h index 749d138beb..8133111e5f 100644 --- a/target/riscv/vector_internals.h +++ b/target/riscv/vector_internals.h @@ -121,12 +121,52 @@ void vext_set_elems_1s(void *base, uint32_t is_agnost= ic, uint32_t cnt, /* expand macro args before macro */ #define RVVCALL(macro, ...) macro(__VA_ARGS__) =20 +/* (TD, T2, TX2) */ +#define OP_UU_B uint8_t, uint8_t, uint8_t +#define OP_UU_H uint16_t, uint16_t, uint16_t +#define OP_UU_W uint32_t, uint32_t, uint32_t +#define OP_UU_D uint64_t, uint64_t, uint64_t + /* (TD, T1, T2, TX1, TX2) */ #define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t #define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t #define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t #define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t =20 +#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, void *vs2, int i) \ +{ \ + TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) =3D OP(s2); \ +} + +#define GEN_VEXT_V(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm =3D vext_vm(desc); \ + uint32_t vl =3D env->vl; \ + uint32_t total_elems =3D \ + vext_get_total_elems(env, desc, ESZ); \ + uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ + uint32_t i; \ + \ + for (i =3D env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * ESZ, \ + (i + 1) * ESZ); \ + continue; \ + } \ + do_##NAME(vd, vs2, i); \ + } \ + env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * ESZ, \ + total_elems * ESZ); \ +} + /* operation of two vector elements */ typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); =20 @@ -179,4 +219,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,= \ do_##NAME, ESZ); \ } =20 +/* Three of the widening shortening macros: */ +/* (TD, T1, T2, TX1, TX2) */ +#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t +#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t +#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t + #endif /* TARGET_RISCV_VECTOR_INTERNALS_H */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 1f29236a63..3fb05cc3d6 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -636,9 +636,6 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t #define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t -#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t -#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t -#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t #define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t #define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t #define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t @@ -3438,11 +3435,6 @@ GEN_VEXT_VF(vfwnmsac_vf_h, 4) GEN_VEXT_VF(vfwnmsac_vf_w, 8) =20 /* Vector Floating-Point Square-Root Instruction */ -/* (TD, T2, TX2) */ -#define OP_UU_H uint16_t, uint16_t, uint16_t -#define OP_UU_W uint32_t, uint32_t, uint32_t -#define OP_UU_D uint64_t, uint64_t, uint64_t - #define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, void *vs2, int i, \ CPURISCVState *env) \ @@ -4139,40 +4131,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32) GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64) =20 /* Vector Floating-Point Classify Instruction */ -#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ -static void do_##NAME(void *vd, void *vs2, int i) \ -{ \ - TX2 s2 =3D *((T2 *)vs2 + HS2(i)); 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.44.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:44:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414677; x=1695019477; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xoSFwtuFhZkWGmCcMsedigUW2QpAqxRib5e5PEzJ78c=; b=EmSpUPeFS1S24p2XWgkwYqLw81IWAYl62psl3/1oL9MkGbgf+IUrL8QSC+uLBOmxAa qsqMRMjsDt5oby4ARKMuWaUoVmexdBE2y9hH4/f9X/zQDHvrhsZgWqJf5RHgTty0zE2m WWyXBBf5oL8dBWkf4QgaDmxrMeYUXJICz3lMjw4EYrqkcJDJB5uHfThZMIeoQNVpP3y7 InuaGqIfliDJDU8nB60WRkgBEXhTwn+vfaWT1pLk17gKOBiL6PaL1rJMmrM7XePScbtH 8e1y2PMPGiz0ypaa2kN19X2Gq5dnYbcblv49tSAHjDhkePXxL67yw1/AvQmCFj6ihmvZ 2efQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414677; x=1695019477; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xoSFwtuFhZkWGmCcMsedigUW2QpAqxRib5e5PEzJ78c=; b=HgjEX6aSJSJxNj60kNo3RCaOUdp3z2pEdtaY6EGNexUkov/sMTopL7KpQYc3khD6tG X7x9N6Ssz6lpCw60m5fb7TLiZKuHeFyHhguvBCRbSFtzg/I1dK/lZXaLdYQYitW3ajQV A7RYkHwDX0hahyFXl7CLx0lzmIQyiv0tFTU6TtiQfFFSXLk8xH6jBrhIUY2U4uCZNves BMdUzt/YTZdjUppRDJOVMoNOo/GlRVokDIppF2m/BiAM0XMo5FjF2FYb1rcr6OmG9q4B IMtwJNu68EpND0lJCspPGiWAmHLo+exS5cVtUlBq3BjhlTQmCgHn49194I7ae4XJBpnQ rNbw== X-Gm-Message-State: AOJu0Yy2lLWMqZWp2j3rVROLPDUpRskKjVy6GPsSnj2JJ9zXfOgJgZXS /S0gZQdgObkAkx8Esk4M1YvZYwcdciwpmw== X-Google-Smtp-Source: AGHT+IG6BeRLyHTPBGeplIwaqqnJ/bVg72CyvZYRjwNQ0CtlS7M6+4Bk31WTaF1CnB4FMvk8XfsX9A== X-Received: by 2002:a05:6808:144a:b0:3ab:83e1:ef6d with SMTP id x10-20020a056808144a00b003ab83e1ef6dmr7084907oiv.6.1694414676637; Sun, 10 Sep 2023 23:44:36 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Dickon Hood , Nazar Kazakov , William Salmon , Kiran Ostrolenk , Max Chou , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 15/45] target/riscv: Add Zvbb ISA extension support Date: Mon, 11 Sep 2023 16:42:50 +1000 Message-ID: <20230911064320.939791-16-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=alistair23@gmail.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414837258100001 Content-Type: text/plain; charset="utf-8" From: Dickon Hood This commit adds support for the Zvbb vector-crypto extension, which consists of the following instructions: * vrol.[vv,vx] * vror.[vv,vx,vi] * vbrev8.v * vrev8.v * vandn.[vv,vx] * vbrev.v * vclz.v * vctz.v * vcpop.v * vwsll.[vv,vx,vi] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov Co-authored-by: William Salmon Co-authored-by: Kiran Ostrolenk [max.chou@sifive.com: Fix imm mode of vror.vi] Signed-off-by: Nazar Kazakov Signed-off-by: William Salmon Signed-off-by: Kiran Ostrolenk Signed-off-by: Dickon Hood Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza [max.chou@sifive.com: Exposed x-zvbb property] Message-ID: <20230711165917.2629866-9-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/riscv/helper.h | 62 +++++++++ target/riscv/insn32.decode | 20 +++ target/riscv/cpu.c | 12 ++ target/riscv/vcrypto_helper.c | 138 +++++++++++++++++++ target/riscv/insn_trans/trans_rvvk.c.inc | 164 +++++++++++++++++++++++ 6 files changed, 397 insertions(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index d25b36a512..0e31ebeed9 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -85,6 +85,7 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; bool ext_zve64d; + bool ext_zvbb; bool ext_zvbc; bool ext_zmmul; bool ext_zvfbfmin; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 6776777c4e..3db25ed2a2 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1188,3 +1188,65 @@ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, en= v, i32) DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vror_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vror_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vror_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vror_vv_d, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vror_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vror_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vror_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vror_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vrol_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrol_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrol_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrol_vv_d, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vrol_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_5(vrev8_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev_v_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(vclz_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vclz_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vclz_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vclz_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vctz_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vctz_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vctz_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vctz_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vcpop_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vcpop_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vcpop_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vcpop_v_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vwsll_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsll_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsll_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsll_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsll_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsll_vx_w, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vandn_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index dd50d5a48c..b982a8325b 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -37,6 +37,7 @@ %imm_u 12:s20 !function=3Dex_shift_12 %imm_bs 30:2 !function=3Dex_shift_3 %imm_rnum 20:4 +%imm_z6 26:1 15:5 =20 # Argument sets: &empty @@ -82,6 +83,7 @@ @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=3D1 %rs2 %rs1 = %rd @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=3D0 %rs2 %rs1 = %rd +@r2_zimm6 ..... . vm:1 ..... ..... ... ..... ....... &rmrr %rs2 rs1=3D%i= mm_z6 %rd @r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd @r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 @@ -952,3 +954,21 @@ vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_= vm vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm + +# *** Zvbb vector crypto extension *** +vrol_vv 010101 . ..... ..... 000 ..... 1010111 @r_vm +vrol_vx 010101 . ..... ..... 100 ..... 1010111 @r_vm +vror_vv 010100 . ..... ..... 000 ..... 1010111 @r_vm +vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm +vror_vi 01010. . ..... ..... 011 ..... 1010111 @r2_zimm6 +vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm +vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm +vandn_vv 000001 . ..... ..... 000 ..... 1010111 @r_vm +vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm +vbrev_v 010010 . ..... 01010 010 ..... 1010111 @r2_vm +vclz_v 010010 . ..... 01100 010 ..... 1010111 @r2_vm +vctz_v 010010 . ..... 01101 010 ..... 1010111 @r2_vm +vcpop_v 010010 . ..... 01110 010 ..... 1010111 @r2_vm +vwsll_vv 110101 . ..... ..... 000 ..... 1010111 @r_vm +vwsll_vx 110101 . ..... ..... 100 ..... 1010111 @r_vm +vwsll_vi 110101 . ..... ..... 011 ..... 1010111 @r_vm diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f74e0926c2..ccffbad4f5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -120,6 +120,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), + ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb), ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc), ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), @@ -1272,6 +1273,16 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu= , Error **errp) return; } =20 + /* + * In principle Zve*x would also suffice here, were they supported + * in qemu + */ + if (cpu->cfg.ext_zvbb && !cpu->cfg.ext_zve32f) { + error_setg(errp, + "Vector crypto extensions require V or Zve* extensions"= ); + return; + } + if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) { error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensio= ns"); return; @@ -1860,6 +1871,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false), =20 /* Vector cryptography extensions */ + DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false), DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), =20 DEFINE_PROP_END_OF_LIST(), diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 8b7c63d499..11239b59d6 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" #include "qemu/bitops.h" +#include "qemu/bswap.h" #include "cpu.h" #include "exec/memop.h" #include "exec/exec-all.h" @@ -57,3 +58,140 @@ RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmul= h64) GEN_VEXT_VV(vclmulh_vv, 8) RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64) GEN_VEXT_VX(vclmulh_vx, 8) + +RVVCALL(OPIVV2, vror_vv_b, OP_UUU_B, H1, H1, H1, ror8) +RVVCALL(OPIVV2, vror_vv_h, OP_UUU_H, H2, H2, H2, ror16) +RVVCALL(OPIVV2, vror_vv_w, OP_UUU_W, H4, H4, H4, ror32) +RVVCALL(OPIVV2, vror_vv_d, OP_UUU_D, H8, H8, H8, ror64) +GEN_VEXT_VV(vror_vv_b, 1) +GEN_VEXT_VV(vror_vv_h, 2) +GEN_VEXT_VV(vror_vv_w, 4) +GEN_VEXT_VV(vror_vv_d, 8) + +RVVCALL(OPIVX2, vror_vx_b, OP_UUU_B, H1, H1, ror8) +RVVCALL(OPIVX2, vror_vx_h, OP_UUU_H, H2, H2, ror16) +RVVCALL(OPIVX2, vror_vx_w, OP_UUU_W, H4, H4, ror32) +RVVCALL(OPIVX2, vror_vx_d, OP_UUU_D, H8, H8, ror64) +GEN_VEXT_VX(vror_vx_b, 1) +GEN_VEXT_VX(vror_vx_h, 2) +GEN_VEXT_VX(vror_vx_w, 4) +GEN_VEXT_VX(vror_vx_d, 8) + +RVVCALL(OPIVV2, vrol_vv_b, OP_UUU_B, H1, H1, H1, rol8) +RVVCALL(OPIVV2, vrol_vv_h, OP_UUU_H, H2, H2, H2, rol16) +RVVCALL(OPIVV2, vrol_vv_w, OP_UUU_W, H4, H4, H4, rol32) +RVVCALL(OPIVV2, vrol_vv_d, OP_UUU_D, H8, H8, H8, rol64) +GEN_VEXT_VV(vrol_vv_b, 1) +GEN_VEXT_VV(vrol_vv_h, 2) +GEN_VEXT_VV(vrol_vv_w, 4) +GEN_VEXT_VV(vrol_vv_d, 8) + +RVVCALL(OPIVX2, vrol_vx_b, OP_UUU_B, H1, H1, rol8) +RVVCALL(OPIVX2, vrol_vx_h, OP_UUU_H, H2, H2, rol16) +RVVCALL(OPIVX2, vrol_vx_w, OP_UUU_W, H4, H4, rol32) +RVVCALL(OPIVX2, vrol_vx_d, OP_UUU_D, H8, H8, rol64) +GEN_VEXT_VX(vrol_vx_b, 1) +GEN_VEXT_VX(vrol_vx_h, 2) +GEN_VEXT_VX(vrol_vx_w, 4) +GEN_VEXT_VX(vrol_vx_d, 8) + +static uint64_t brev8(uint64_t val) +{ + val =3D ((val & 0x5555555555555555ull) << 1) | + ((val & 0xAAAAAAAAAAAAAAAAull) >> 1); + val =3D ((val & 0x3333333333333333ull) << 2) | + ((val & 0xCCCCCCCCCCCCCCCCull) >> 2); + val =3D ((val & 0x0F0F0F0F0F0F0F0Full) << 4) | + ((val & 0xF0F0F0F0F0F0F0F0ull) >> 4); + + return val; +} + +RVVCALL(OPIVV1, vbrev8_v_b, OP_UU_B, H1, H1, brev8) +RVVCALL(OPIVV1, vbrev8_v_h, OP_UU_H, H2, H2, brev8) +RVVCALL(OPIVV1, vbrev8_v_w, OP_UU_W, H4, H4, brev8) +RVVCALL(OPIVV1, vbrev8_v_d, OP_UU_D, H8, H8, brev8) +GEN_VEXT_V(vbrev8_v_b, 1) +GEN_VEXT_V(vbrev8_v_h, 2) +GEN_VEXT_V(vbrev8_v_w, 4) +GEN_VEXT_V(vbrev8_v_d, 8) + +#define DO_IDENTITY(a) (a) +RVVCALL(OPIVV1, vrev8_v_b, OP_UU_B, H1, H1, DO_IDENTITY) +RVVCALL(OPIVV1, vrev8_v_h, OP_UU_H, H2, H2, bswap16) +RVVCALL(OPIVV1, vrev8_v_w, OP_UU_W, H4, H4, bswap32) +RVVCALL(OPIVV1, vrev8_v_d, OP_UU_D, H8, H8, bswap64) +GEN_VEXT_V(vrev8_v_b, 1) +GEN_VEXT_V(vrev8_v_h, 2) +GEN_VEXT_V(vrev8_v_w, 4) +GEN_VEXT_V(vrev8_v_d, 8) + +#define DO_ANDN(a, b) ((a) & ~(b)) +RVVCALL(OPIVV2, vandn_vv_b, OP_UUU_B, H1, H1, H1, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_h, OP_UUU_H, H2, H2, H2, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_w, OP_UUU_W, H4, H4, H4, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_d, OP_UUU_D, H8, H8, H8, DO_ANDN) +GEN_VEXT_VV(vandn_vv_b, 1) +GEN_VEXT_VV(vandn_vv_h, 2) +GEN_VEXT_VV(vandn_vv_w, 4) +GEN_VEXT_VV(vandn_vv_d, 8) + +RVVCALL(OPIVX2, vandn_vx_b, OP_UUU_B, H1, H1, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_h, OP_UUU_H, H2, H2, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_w, OP_UUU_W, H4, H4, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_d, OP_UUU_D, H8, H8, DO_ANDN) +GEN_VEXT_VX(vandn_vx_b, 1) +GEN_VEXT_VX(vandn_vx_h, 2) +GEN_VEXT_VX(vandn_vx_w, 4) +GEN_VEXT_VX(vandn_vx_d, 8) + +RVVCALL(OPIVV1, vbrev_v_b, OP_UU_B, H1, H1, revbit8) +RVVCALL(OPIVV1, vbrev_v_h, OP_UU_H, H2, H2, revbit16) +RVVCALL(OPIVV1, vbrev_v_w, OP_UU_W, H4, H4, revbit32) +RVVCALL(OPIVV1, vbrev_v_d, OP_UU_D, H8, H8, revbit64) +GEN_VEXT_V(vbrev_v_b, 1) +GEN_VEXT_V(vbrev_v_h, 2) +GEN_VEXT_V(vbrev_v_w, 4) +GEN_VEXT_V(vbrev_v_d, 8) + +RVVCALL(OPIVV1, vclz_v_b, OP_UU_B, H1, H1, clz8) +RVVCALL(OPIVV1, vclz_v_h, OP_UU_H, H2, H2, clz16) +RVVCALL(OPIVV1, vclz_v_w, OP_UU_W, H4, H4, clz32) +RVVCALL(OPIVV1, vclz_v_d, OP_UU_D, H8, H8, clz64) +GEN_VEXT_V(vclz_v_b, 1) +GEN_VEXT_V(vclz_v_h, 2) +GEN_VEXT_V(vclz_v_w, 4) +GEN_VEXT_V(vclz_v_d, 8) + +RVVCALL(OPIVV1, vctz_v_b, OP_UU_B, H1, H1, ctz8) +RVVCALL(OPIVV1, vctz_v_h, OP_UU_H, H2, H2, ctz16) +RVVCALL(OPIVV1, vctz_v_w, OP_UU_W, H4, H4, ctz32) +RVVCALL(OPIVV1, vctz_v_d, OP_UU_D, H8, H8, ctz64) +GEN_VEXT_V(vctz_v_b, 1) +GEN_VEXT_V(vctz_v_h, 2) +GEN_VEXT_V(vctz_v_w, 4) +GEN_VEXT_V(vctz_v_d, 8) + +RVVCALL(OPIVV1, vcpop_v_b, OP_UU_B, H1, H1, ctpop8) +RVVCALL(OPIVV1, vcpop_v_h, OP_UU_H, H2, H2, ctpop16) +RVVCALL(OPIVV1, vcpop_v_w, OP_UU_W, H4, H4, ctpop32) +RVVCALL(OPIVV1, vcpop_v_d, OP_UU_D, H8, H8, ctpop64) +GEN_VEXT_V(vcpop_v_b, 1) +GEN_VEXT_V(vcpop_v_h, 2) +GEN_VEXT_V(vcpop_v_w, 4) +GEN_VEXT_V(vcpop_v_d, 8) + +#define DO_SLL(N, M) (N << (M & (sizeof(N) * 8 - 1))) +RVVCALL(OPIVV2, vwsll_vv_b, WOP_UUU_B, H2, H1, H1, DO_SLL) +RVVCALL(OPIVV2, vwsll_vv_h, WOP_UUU_H, H4, H2, H2, DO_SLL) +RVVCALL(OPIVV2, vwsll_vv_w, WOP_UUU_W, H8, H4, H4, DO_SLL) +GEN_VEXT_VV(vwsll_vv_b, 2) +GEN_VEXT_VV(vwsll_vv_h, 4) +GEN_VEXT_VV(vwsll_vv_w, 8) + +RVVCALL(OPIVX2, vwsll_vx_b, WOP_UUU_B, H2, H1, DO_SLL) +RVVCALL(OPIVX2, vwsll_vx_h, WOP_UUU_H, H4, H2, DO_SLL) +RVVCALL(OPIVX2, vwsll_vx_w, WOP_UUU_W, H8, H4, DO_SLL) +GEN_VEXT_VX(vwsll_vx_b, 2) +GEN_VEXT_VX(vwsll_vx_h, 4) +GEN_VEXT_VX(vwsll_vx_w, 8) diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index 552b08a2fd..0e4b337613 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -60,3 +60,167 @@ static bool vclmul_vx_check(DisasContext *s, arg_rmrr *= a) =20 GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check) GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check) + +/* + * Zvbb + */ + +#define GEN_OPIVI_GVEC_TRANS_CHECK(NAME, IMM_MODE, OPIVX, SUF, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + static gen_helper_opivx *const fns[4] =3D { \ + gen_helper_##OPIVX##_b, \ + gen_helper_##OPIVX##_h, \ + gen_helper_##OPIVX##_w, \ + gen_helper_##OPIVX##_d, \ + }; \ + return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew], \ + IMM_MODE); \ + } \ + return false; \ + } + +#define GEN_OPIVV_GVEC_TRANS_CHECK(NAME, SUF, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + static gen_helper_gvec_4_ptr *const fns[4] =3D { = \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ + } \ + return false; \ + } + +#define GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(NAME, SUF, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + static gen_helper_opivx *const fns[4] =3D { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, \ + fns[s->sew]); \ + } \ + return false; \ + } + +static bool zvbb_vv_check(DisasContext *s, arg_rmrr *a) +{ + return opivv_check(s, a) && s->cfg_ptr->ext_zvbb =3D=3D true; +} + +static bool zvbb_vx_check(DisasContext *s, arg_rmrr *a) +{ + return opivx_check(s, a) && s->cfg_ptr->ext_zvbb =3D=3D true; +} + +/* vrol.v[vx] */ +GEN_OPIVV_GVEC_TRANS_CHECK(vrol_vv, rotlv, zvbb_vv_check) +GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vrol_vx, rotls, zvbb_vx_check) + +/* vror.v[vxi] */ +GEN_OPIVV_GVEC_TRANS_CHECK(vror_vv, rotrv, zvbb_vv_check) +GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vror_vx, rotrs, zvbb_vx_check) +GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri, zvbb_vx= _check) + +#define GEN_OPIVX_GVEC_TRANS_CHECK(NAME, SUF, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + static gen_helper_opivx *const fns[4] =3D { = \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ + } \ + return false; \ + } + +/* vandn.v[vx] */ +GEN_OPIVV_GVEC_TRANS_CHECK(vandn_vv, andc, zvbb_vv_check) +GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvbb_vx_check) + +#define GEN_OPIV_TRANS(NAME, CHECK) = \ + static bool trans_##NAME(DisasContext *s, arg_rmr *a) = \ + { = \ + if (CHECK(s, a)) { = \ + uint32_t data =3D 0; = \ + static gen_helper_gvec_3_ptr *const fns[4] =3D { = \ + gen_helper_##NAME##_b, = \ + gen_helper_##NAME##_h, = \ + gen_helper_##NAME##_w, = \ + gen_helper_##NAME##_d, = \ + }; = \ + TCGLabel *over =3D gen_new_label(); = \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); = \ + = \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); = \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); = \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s= ); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), = \ + vreg_ofs(s, a->rs2), cpu_env, = \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,= \ + data, fns[s->sew]); = \ + mark_vs_dirty(s); = \ + gen_set_label(over); = \ + return true; = \ + } = \ + return false; = \ + } + +static bool zvbb_opiv_check(DisasContext *s, arg_rmr *a) +{ + return s->cfg_ptr->ext_zvbb =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_ss(s, a->rd, a->rs2, a->vm); +} + +GEN_OPIV_TRANS(vbrev8_v, zvbb_opiv_check) +GEN_OPIV_TRANS(vrev8_v, zvbb_opiv_check) +GEN_OPIV_TRANS(vbrev_v, zvbb_opiv_check) +GEN_OPIV_TRANS(vclz_v, zvbb_opiv_check) +GEN_OPIV_TRANS(vctz_v, zvbb_opiv_check) +GEN_OPIV_TRANS(vcpop_v, zvbb_opiv_check) + +static bool vwsll_vv_check(DisasContext *s, arg_rmrr *a) +{ + return s->cfg_ptr->ext_zvbb && opivv_widen_check(s, a); +} + +static bool vwsll_vx_check(DisasContext *s, arg_rmrr *a) +{ + return s->cfg_ptr->ext_zvbb && opivx_widen_check(s, a); +} + +/* OPIVI without GVEC IR */ +#define GEN_OPIVI_WIDEN_TRANS(NAME, IMM_MODE, OPIVX, CHECK) = \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) = \ + { = \ + if (CHECK(s, a)) { = \ + static gen_helper_opivx *const fns[3] =3D { = \ + gen_helper_##OPIVX##_b, = \ + gen_helper_##OPIVX##_h, = \ + gen_helper_##OPIVX##_w, = \ + }; = \ + return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], = s, \ + IMM_MODE); = \ + } = \ + return false; = \ + } + +GEN_OPIVV_WIDEN_TRANS(vwsll_vv, vwsll_vv_check) +GEN_OPIVX_WIDEN_TRANS(vwsll_vx, vwsll_vx_check) +GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check) --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted 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Co-authored-by: Lawrence Hunter Co-authored-by: William Salmon [max.chou@sifive.com: Replaced vstart checking by TCG op] Signed-off-by: Lawrence Hunter Signed-off-by: William Salmon Signed-off-by: Nazar Kazakov Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza [max.chou@sifive.com: Imported aes-round.h and exposed x-zvkned property] [max.chou@sifive.com: Fixed endian issues and replaced the vstart & vl egs checking by helper function] [max.chou@sifive.com: Replaced bswap32 calls in aes key expanding] Message-ID: <20230711165917.2629866-10-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/riscv/helper.h | 14 ++ target/riscv/insn32.decode | 14 ++ target/riscv/cpu.c | 4 +- target/riscv/vcrypto_helper.c | 202 +++++++++++++++++++++++ target/riscv/insn_trans/trans_rvvk.c.inc | 147 +++++++++++++++++ 6 files changed, 381 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 0e31ebeed9..c7eafe27c0 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -87,6 +87,7 @@ struct RISCVCPUConfig { bool ext_zve64d; bool ext_zvbb; bool ext_zvbc; + bool ext_zvkned; bool ext_zmmul; bool ext_zvfbfmin; bool ext_zvfbfwma; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 3db25ed2a2..02e5dbe6ee 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1250,3 +1250,17 @@ DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, en= v, i32) DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_2(egs_check, void, i32, env) + +DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesem_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesem_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) +DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32) +DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b982a8325b..4f3c50f10f 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -75,6 +75,7 @@ @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd @r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd +@r2_vm_1 ...... . ..... ..... ... ..... ....... &rmr vm=3D1 %rs2 %rd @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd @@ -972,3 +973,16 @@ vcpop_v 010010 . ..... 01110 010 ..... 1010111 @r2= _vm vwsll_vv 110101 . ..... ..... 000 ..... 1010111 @r_vm vwsll_vx 110101 . ..... ..... 100 ..... 1010111 @r_vm vwsll_vi 110101 . ..... ..... 011 ..... 1010111 @r_vm + +# *** Zvkned vector crypto extension *** +vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1 +vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 +vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 +vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 +vaesem_vv 101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1 +vaesem_vs 101001 1 ..... 00010 010 ..... 1110111 @r2_vm_1 +vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 +vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 +vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 +vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ccffbad4f5..8e3ae4d7e0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -129,6 +129,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), + ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), @@ -1277,7 +1278,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) * In principle Zve*x would also suffice here, were they supported * in qemu */ - if (cpu->cfg.ext_zvbb && !cpu->cfg.ext_zve32f) { + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned) && !cpu->cfg.ext_zve32f= ) { error_setg(errp, "Vector crypto extensions require V or Zve* extensions"= ); return; @@ -1873,6 +1874,7 @@ static Property riscv_cpu_extensions[] =3D { /* Vector cryptography extensions */ DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false), DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), + DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), =20 DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 11239b59d6..cca78184e9 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -22,6 +22,8 @@ #include "qemu/bitops.h" #include "qemu/bswap.h" #include "cpu.h" +#include "crypto/aes.h" +#include "crypto/aes-round.h" #include "exec/memop.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -195,3 +197,203 @@ RVVCALL(OPIVX2, vwsll_vx_w, WOP_UUU_W, H8, H4, DO_SLL) GEN_VEXT_VX(vwsll_vx_b, 2) GEN_VEXT_VX(vwsll_vx_h, 4) GEN_VEXT_VX(vwsll_vx_w, 8) + +void HELPER(egs_check)(uint32_t egs, CPURISCVState *env) +{ + uint32_t vl =3D env->vl; + uint32_t vstart =3D env->vstart; + + if (vl % egs !=3D 0 || vstart % egs !=3D 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } +} + +static inline void xor_round_key(AESState *round_state, AESState *round_ke= y) +{ + round_state->v =3D round_state->v ^ round_key->v; +} + +#define GEN_ZVKNED_HELPER_VV(NAME, ...) \ + void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \ + uint32_t desc) \ + { \ + uint32_t vl =3D env->vl; = \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); = \ + uint32_t vta =3D vext_vta(desc); = \ + \ + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { = \ + AESState round_key; \ + round_key.d[0] =3D *((uint64_t *)vs2 + H8(i * 2 + 0)); = \ + round_key.d[1] =3D *((uint64_t *)vs2 + H8(i * 2 + 1)); = \ + AESState round_state; \ + round_state.d[0] =3D *((uint64_t *)vd + H8(i * 2 + 0)); = \ + round_state.d[1] =3D *((uint64_t *)vd + H8(i * 2 + 1)); = \ + __VA_ARGS__; \ + *((uint64_t *)vd + H8(i * 2 + 0)) =3D round_state.d[0]; = \ + *((uint64_t *)vd + H8(i * 2 + 1)) =3D round_state.d[1]; = \ + } \ + env->vstart =3D 0; = \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \ + } + +#define GEN_ZVKNED_HELPER_VS(NAME, ...) \ + void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \ + uint32_t desc) \ + { \ + uint32_t vl =3D env->vl; = \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); = \ + uint32_t vta =3D vext_vta(desc); = \ + \ + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { = \ + AESState round_key; \ + round_key.d[0] =3D *((uint64_t *)vs2 + H8(0)); = \ + round_key.d[1] =3D *((uint64_t *)vs2 + H8(1)); = \ + AESState round_state; \ + round_state.d[0] =3D *((uint64_t *)vd + H8(i * 2 + 0)); = \ + round_state.d[1] =3D *((uint64_t *)vd + H8(i * 2 + 1)); = \ + __VA_ARGS__; \ + *((uint64_t *)vd + H8(i * 2 + 0)) =3D round_state.d[0]; = \ + *((uint64_t *)vd + H8(i * 2 + 1)) =3D round_state.d[1]; = \ + } \ + env->vstart =3D 0; = \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \ + } + +GEN_ZVKNED_HELPER_VV(vaesef_vv, aesenc_SB_SR_AK(&round_state, + &round_state, + &round_key, + false);) +GEN_ZVKNED_HELPER_VS(vaesef_vs, aesenc_SB_SR_AK(&round_state, + &round_state, + &round_key, + false);) +GEN_ZVKNED_HELPER_VV(vaesdf_vv, aesdec_ISB_ISR_AK(&round_state, + &round_state, + &round_key, + false);) +GEN_ZVKNED_HELPER_VS(vaesdf_vs, aesdec_ISB_ISR_AK(&round_state, + &round_state, + &round_key, + false);) +GEN_ZVKNED_HELPER_VV(vaesem_vv, aesenc_SB_SR_MC_AK(&round_state, + &round_state, + &round_key, + false);) +GEN_ZVKNED_HELPER_VS(vaesem_vs, aesenc_SB_SR_MC_AK(&round_state, + &round_state, + &round_key, + false);) +GEN_ZVKNED_HELPER_VV(vaesdm_vv, aesdec_ISB_ISR_AK_IMC(&round_state, + &round_state, + &round_key, + false);) +GEN_ZVKNED_HELPER_VS(vaesdm_vs, aesdec_ISB_ISR_AK_IMC(&round_state, + &round_state, + &round_key, + false);) +GEN_ZVKNED_HELPER_VS(vaesz_vs, xor_round_key(&round_state, &round_key);) + +void HELPER(vaeskf1_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, + CPURISCVState *env, uint32_t desc) +{ + uint32_t *vd =3D vd_vptr; + uint32_t *vs2 =3D vs2_vptr; + uint32_t vl =3D env->vl; + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); + uint32_t vta =3D vext_vta(desc); + + uimm &=3D 0b1111; + if (uimm > 10 || uimm =3D=3D 0) { + uimm ^=3D 0b1000; + } + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + uint32_t rk[8], tmp; + static const uint32_t rcon[] =3D { + 0x00000001, 0x00000002, 0x00000004, 0x00000008, 0x00000010, + 0x00000020, 0x00000040, 0x00000080, 0x0000001B, 0x00000036, + }; + + rk[0] =3D vs2[i * 4 + H4(0)]; + rk[1] =3D vs2[i * 4 + H4(1)]; + rk[2] =3D vs2[i * 4 + H4(2)]; + rk[3] =3D vs2[i * 4 + H4(3)]; + tmp =3D ror32(rk[3], 8); + + rk[4] =3D rk[0] ^ (((uint32_t)AES_sbox[(tmp >> 24) & 0xff] << 24) | + ((uint32_t)AES_sbox[(tmp >> 16) & 0xff] << 16) | + ((uint32_t)AES_sbox[(tmp >> 8) & 0xff] << 8) | + ((uint32_t)AES_sbox[(tmp >> 0) & 0xff] << 0)) + ^ rcon[uimm - 1]; + rk[5] =3D rk[1] ^ rk[4]; + rk[6] =3D rk[2] ^ rk[5]; + rk[7] =3D rk[3] ^ rk[6]; + + vd[i * 4 + H4(0)] =3D rk[4]; + vd[i * 4 + H4(1)] =3D rk[5]; + vd[i * 4 + H4(2)] =3D rk[6]; + vd[i * 4 + H4(3)] =3D rk[7]; + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); +} + +void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, + CPURISCVState *env, uint32_t desc) +{ + uint32_t *vd =3D vd_vptr; + uint32_t *vs2 =3D vs2_vptr; + uint32_t vl =3D env->vl; + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); + uint32_t vta =3D vext_vta(desc); + + uimm &=3D 0b1111; + if (uimm > 14 || uimm < 2) { + uimm ^=3D 0b1000; + } + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + uint32_t rk[12], tmp; + static const uint32_t rcon[] =3D { + 0x00000001, 0x00000002, 0x00000004, 0x00000008, 0x00000010, + 0x00000020, 0x00000040, 0x00000080, 0x0000001B, 0x00000036, + }; + + rk[0] =3D vd[i * 4 + H4(0)]; + rk[1] =3D vd[i * 4 + H4(1)]; + rk[2] =3D vd[i * 4 + H4(2)]; + rk[3] =3D vd[i * 4 + H4(3)]; + rk[4] =3D vs2[i * 4 + H4(0)]; + rk[5] =3D vs2[i * 4 + H4(1)]; + rk[6] =3D vs2[i * 4 + H4(2)]; + rk[7] =3D vs2[i * 4 + H4(3)]; + + if (uimm % 2 =3D=3D 0) { + tmp =3D ror32(rk[7], 8); + rk[8] =3D rk[0] ^ (((uint32_t)AES_sbox[(tmp >> 24) & 0xff] << = 24) | + ((uint32_t)AES_sbox[(tmp >> 16) & 0xff] << 16= ) | + ((uint32_t)AES_sbox[(tmp >> 8) & 0xff] << 8) | + ((uint32_t)AES_sbox[(tmp >> 0) & 0xff] << 0)) + ^ rcon[(uimm - 1) / 2]; + } else { + rk[8] =3D rk[0] ^ (((uint32_t)AES_sbox[(rk[7] >> 24) & 0xff] <= < 24) | + ((uint32_t)AES_sbox[(rk[7] >> 16) & 0xff] << = 16) | + ((uint32_t)AES_sbox[(rk[7] >> 8) & 0xff] << 8= ) | + ((uint32_t)AES_sbox[(rk[7] >> 0) & 0xff] << 0= )); + } + rk[9] =3D rk[1] ^ rk[8]; + rk[10] =3D rk[2] ^ rk[9]; + rk[11] =3D rk[3] ^ rk[10]; + + vd[i * 4 + H4(0)] =3D rk[8]; + vd[i * 4 + H4(1)] =3D rk[9]; + vd[i * 4 + H4(2)] =3D rk[10]; + vd[i * 4 + H4(3)] =3D rk[11]; + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); +} diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index 0e4b337613..817353f4d3 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -224,3 +224,150 @@ static bool vwsll_vx_check(DisasContext *s, arg_rmrr = *a) GEN_OPIVV_WIDEN_TRANS(vwsll_vv, vwsll_vv_check) GEN_OPIVX_WIDEN_TRANS(vwsll_vx, vwsll_vx_check) GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check) + +/* + * Zvkned + */ + +#define ZVKNED_EGS 4 + +#define GEN_V_UNMASKED_TRANS(NAME, CHECK, EGS) = \ + static bool trans_##NAME(DisasContext *s, arg_##NAME *a) = \ + { = \ + if (CHECK(s, a)) { = \ + TCGv_ptr rd_v, rs2_v; = \ + TCGv_i32 desc, egs; = \ + uint32_t data =3D 0; = \ + TCGLabel *over =3D gen_new_label(); = \ + = \ + if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { = \ + /* save opcode for unwinding in case we throw an exception= */ \ + decode_save_opc(s); = \ + egs =3D tcg_constant_i32(EGS); = \ + gen_helper_egs_check(egs, cpu_env); = \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);= \ + } = \ + = \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); = \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); = \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s= ); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ + rd_v =3D tcg_temp_new_ptr(); = \ + rs2_v =3D tcg_temp_new_ptr(); = \ + desc =3D tcg_constant_i32( = \ + simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data= )); \ + tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); = \ + tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); = \ + gen_helper_##NAME(rd_v, rs2_v, cpu_env, desc); = \ + mark_vs_dirty(s); = \ + gen_set_label(over); = \ + return true; = \ + } = \ + return false; = \ + } + +static bool vaes_check_vv(DisasContext *s, arg_rmr *a) +{ + int egw_bytes =3D ZVKNED_EGS << s->sew; + return s->cfg_ptr->ext_zvkned =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + MAXSZ(s) >=3D egw_bytes && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul) && + s->sew =3D=3D MO_32; +} + +static bool vaes_check_overlap(DisasContext *s, int vd, int vs2) +{ + int8_t op_size =3D s->lmul <=3D 0 ? 1 : 1 << s->lmul; + return !is_overlapped(vd, op_size, vs2, 1); +} + +static bool vaes_check_vs(DisasContext *s, arg_rmr *a) +{ + int egw_bytes =3D ZVKNED_EGS << s->sew; + return vaes_check_overlap(s, a->rd, a->rs2) && + MAXSZ(s) >=3D egw_bytes && + s->cfg_ptr->ext_zvkned =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->lmul) && + s->sew =3D=3D MO_32; +} + +GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv, ZVKNED_EGS) +GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs, ZVKNED_EGS) +GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv, ZVKNED_EGS) +GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs, ZVKNED_EGS) +GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv, ZVKNED_EGS) +GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs, ZVKNED_EGS) +GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs, ZVKNED_EGS) +GEN_V_UNMASKED_TRANS(vaesem_vv, vaes_check_vv, ZVKNED_EGS) +GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS) + +#define GEN_VI_UNMASKED_TRANS(NAME, CHECK, EGS) = \ + static bool trans_##NAME(DisasContext *s, arg_##NAME *a) = \ + { = \ + if (CHECK(s, a)) { = \ + TCGv_ptr rd_v, rs2_v; = \ + TCGv_i32 uimm_v, desc, egs; = \ + uint32_t data =3D 0; = \ + TCGLabel *over =3D gen_new_label(); = \ + = \ + if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { = \ + /* save opcode for unwinding in case we throw an exception= */ \ + decode_save_opc(s); = \ + egs =3D tcg_constant_i32(EGS); = \ + gen_helper_egs_check(egs, cpu_env); = \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);= \ + } = \ + = \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); = \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); = \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s= ); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ + = \ + rd_v =3D tcg_temp_new_ptr(); = \ + rs2_v =3D tcg_temp_new_ptr(); = \ + uimm_v =3D tcg_constant_i32(a->rs1); = \ + desc =3D tcg_constant_i32( = \ + simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data= )); \ + tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); = \ + tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); = \ + gen_helper_##NAME(rd_v, rs2_v, uimm_v, cpu_env, desc); = \ + mark_vs_dirty(s); = \ + gen_set_label(over); = \ + return true; = \ + } = \ + return false; = \ + } + +static bool vaeskf1_check(DisasContext *s, arg_vaeskf1_vi *a) +{ + int egw_bytes =3D ZVKNED_EGS << s->sew; + return s->cfg_ptr->ext_zvkned =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + MAXSZ(s) >=3D egw_bytes && + s->sew =3D=3D MO_32 && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul); +} + +static bool vaeskf2_check(DisasContext *s, arg_vaeskf2_vi *a) +{ + int egw_bytes =3D ZVKNED_EGS << s->sew; + return s->cfg_ptr->ext_zvkned =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + MAXSZ(s) >=3D egw_bytes && + s->sew =3D=3D MO_32 && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul); +} + +GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check, ZVKNED_EGS) +GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS) --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.44.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:44:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414685; x=1695019485; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mTs5EAXQCNv7xKSmVs3cJPCQuWtkfKVB1HbSg6LBKOk=; b=irWl4UKNVWPu/jL4Es4dgV/uhDU6yji9lrXd1zfFM61n+0huMpmtIXOpCl2LzAzq8P muFOwtnMBI0PfsQ6FvNsAOBBBp0rLAT/x8X4Kc6I3XWe59dgjiFHlP0dZ3kKeYk3NPX2 eILhKUX3PzDuFl6DSm33SWxBHpU+fkd2NwNDeV313KCDNAp1TCEKWWxr0qwKHF5ElfdQ JDHhiXwdkkeP7GguK1qGCHhaNbcnA+j3c5X1eSTn2aiiuMSStbeOh6LKfQcN6jybwqDs 4c0UE1G2OgZqrjHw9Iuq24bKJkNh+4W/aC5mnOSf+tBvQkNVMqrJ2yzDl8jWMxVTeSnI DeAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414685; x=1695019485; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mTs5EAXQCNv7xKSmVs3cJPCQuWtkfKVB1HbSg6LBKOk=; b=fJ9w94m5ciu+7FUNmsRB6DcYBP7cFRLfCUhXvY74D5EONigjcddw5/5mKvydTeQpyD 7Sw/S7Nnudfh0SdpHK2xURUjhaTiVdCwgXFnox6G+DCTfZRIE/QbOL5sON2d8JxBVbqg kvZFHZhU/T2oxOLGbKdF/v5+C7hI57aU2JKb5iJJuar0tTygnseWcr4PqpalVXc2hdOD 7t+jLW2vHVqjhE52AoPEQaeLhMGVvaIiG2jk/R12cIE1rIN/eo88pmIiVOA0XEDJ8R6l sBA3oUhw5+asNGHCdgmg7GUqZdmbMSnI3zShonprB7uWCHxSiQYyXe8aYSbnRav4jNHB 4JKg== X-Gm-Message-State: AOJu0YwyrTJVvvwuAk8iLc/MH8yYOOMcQDt35KZ90ILUvJv9NhdV6cVK i9lqXeaZILghEtGdoMAzaBesiAAanwqtOg== X-Google-Smtp-Source: AGHT+IF+wcGVGLLGBJCFdVpPA2JXYTBb/R9CMYH00kmJUc9R7lo47Hc1pMAQPDP0n2ZH6BejU+Znfg== X-Received: by 2002:a54:4011:0:b0:3a7:316e:9886 with SMTP id x17-20020a544011000000b003a7316e9886mr7657266oie.8.1694414685462; Sun, 10 Sep 2023 23:44:45 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Kiran Ostrolenk , Nazar Kazakov , Lawrence Hunter , Max Chou , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 17/45] target/riscv: Add Zvknh ISA extension support Date: Mon, 11 Sep 2023 16:42:52 +1000 Message-ID: <20230911064320.939791-18-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=alistair23@gmail.com; helo=mail-oi1-x22d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414763374100002 Content-Type: text/plain; charset="utf-8" From: Kiran Ostrolenk This commit adds support for the Zvknh vector-crypto extension, which consists of the following instructions: * vsha2ms.vv * vsha2c[hl].vv Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov Co-authored-by: Lawrence Hunter [max.chou@sifive.com: Replaced vstart checking by TCG op] Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter Signed-off-by: Kiran Ostrolenk Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza [max.chou@sifive.com: Exposed x-zvknha & x-zvknhb properties] [max.chou@sifive.com: Replaced SEW selection to happened during translation] Message-ID: <20230711165917.2629866-11-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 2 + target/riscv/helper.h | 6 + target/riscv/insn32.decode | 5 + target/riscv/cpu.c | 13 +- target/riscv/vcrypto_helper.c | 238 +++++++++++++++++++++++ target/riscv/insn_trans/trans_rvvk.c.inc | 129 ++++++++++++ 6 files changed, 390 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index c7eafe27c0..800b8783c1 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -88,6 +88,8 @@ struct RISCVCPUConfig { bool ext_zvbb; bool ext_zvbc; bool ext_zvkned; + bool ext_zvknha; + bool ext_zvknhb; bool ext_zmmul; bool ext_zvfbfmin; bool ext_zvfbfwma; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 02e5dbe6ee..34329b52fe 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1264,3 +1264,9 @@ DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32) DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32) + +DEF_HELPER_5(vsha2ms_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsha2ch32_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsha2ch64_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsha2cl32_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsha2cl64_vv, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4f3c50f10f..e2b83186dc 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -986,3 +986,8 @@ vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_= vm_1 vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1 vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** Zvknh vector crypto extension *** +vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8e3ae4d7e0..f103f536fd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -130,6 +130,8 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), + ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), + ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), @@ -1278,14 +1280,17 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) * In principle Zve*x would also suffice here, were they supported * in qemu */ - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned) && !cpu->cfg.ext_zve32f= ) { + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha) = && + !cpu->cfg.ext_zve32f) { error_setg(errp, "Vector crypto extensions require V or Zve* extensions"= ); return; } =20 - if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) { - error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensio= ns"); + if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f= ) { + error_setg( + errp, + "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions= "); return; } =20 @@ -1875,6 +1880,8 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false), DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), + DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false), + DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false), =20 DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index cca78184e9..2f2099b6fb 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -397,3 +397,241 @@ void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr= , uint32_t uimm, /* set tail elements to 1s */ vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); } + +static inline uint32_t sig0_sha256(uint32_t x) +{ + return ror32(x, 7) ^ ror32(x, 18) ^ (x >> 3); +} + +static inline uint32_t sig1_sha256(uint32_t x) +{ + return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10); +} + +static inline uint64_t sig0_sha512(uint64_t x) +{ + return ror64(x, 1) ^ ror64(x, 8) ^ (x >> 7); +} + +static inline uint64_t sig1_sha512(uint64_t x) +{ + return ror64(x, 19) ^ ror64(x, 61) ^ (x >> 6); +} + +static inline void vsha2ms_e32(uint32_t *vd, uint32_t *vs1, uint32_t *vs2) +{ + uint32_t res[4]; + res[0] =3D sig1_sha256(vs1[H4(2)]) + vs2[H4(1)] + sig0_sha256(vd[H4(1)= ]) + + vd[H4(0)]; + res[1] =3D sig1_sha256(vs1[H4(3)]) + vs2[H4(2)] + sig0_sha256(vd[H4(2)= ]) + + vd[H4(1)]; + res[2] =3D + sig1_sha256(res[0]) + vs2[H4(3)] + sig0_sha256(vd[H4(3)]) + vd[H4(= 2)]; + res[3] =3D + sig1_sha256(res[1]) + vs1[H4(0)] + sig0_sha256(vs2[H4(0)]) + vd[H4= (3)]; + vd[H4(3)] =3D res[3]; + vd[H4(2)] =3D res[2]; + vd[H4(1)] =3D res[1]; + vd[H4(0)] =3D res[0]; +} + +static inline void vsha2ms_e64(uint64_t *vd, uint64_t *vs1, uint64_t *vs2) +{ + uint64_t res[4]; + res[0] =3D sig1_sha512(vs1[2]) + vs2[1] + sig0_sha512(vd[1]) + vd[0]; + res[1] =3D sig1_sha512(vs1[3]) + vs2[2] + sig0_sha512(vd[2]) + vd[1]; + res[2] =3D sig1_sha512(res[0]) + vs2[3] + sig0_sha512(vd[3]) + vd[2]; + res[3] =3D sig1_sha512(res[1]) + vs1[0] + sig0_sha512(vs2[0]) + vd[3]; + vd[3] =3D res[3]; + vd[2] =3D res[2]; + vd[1] =3D res[1]; + vd[0] =3D res[0]; +} + +void HELPER(vsha2ms_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, + uint32_t desc) +{ + uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t esz =3D sew =3D=3D MO_32 ? 4 : 8; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + if (sew =3D=3D MO_32) { + vsha2ms_e32(((uint32_t *)vd) + i * 4, ((uint32_t *)vs1) + i * = 4, + ((uint32_t *)vs2) + i * 4); + } else { + /* If not 32 then SEW should be 64 */ + vsha2ms_e64(((uint64_t *)vd) + i * 4, ((uint64_t *)vs1) + i * = 4, + ((uint64_t *)vs2) + i * 4); + } + } + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} + +static inline uint64_t sum0_64(uint64_t x) +{ + return ror64(x, 28) ^ ror64(x, 34) ^ ror64(x, 39); +} + +static inline uint32_t sum0_32(uint32_t x) +{ + return ror32(x, 2) ^ ror32(x, 13) ^ ror32(x, 22); +} + +static inline uint64_t sum1_64(uint64_t x) +{ + return ror64(x, 14) ^ ror64(x, 18) ^ ror64(x, 41); +} + +static inline uint32_t sum1_32(uint32_t x) +{ + return ror32(x, 6) ^ ror32(x, 11) ^ ror32(x, 25); +} + +#define ch(x, y, z) ((x & y) ^ ((~x) & z)) + +#define maj(x, y, z) ((x & y) ^ (x & z) ^ (y & z)) + +static void vsha2c_64(uint64_t *vs2, uint64_t *vd, uint64_t *vs1) +{ + uint64_t a =3D vs2[3], b =3D vs2[2], e =3D vs2[1], f =3D vs2[0]; + uint64_t c =3D vd[3], d =3D vd[2], g =3D vd[1], h =3D vd[0]; + uint64_t W0 =3D vs1[0], W1 =3D vs1[1]; + uint64_t T1 =3D h + sum1_64(e) + ch(e, f, g) + W0; + uint64_t T2 =3D sum0_64(a) + maj(a, b, c); + + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + T1 =3D h + sum1_64(e) + ch(e, f, g) + W1; + T2 =3D sum0_64(a) + maj(a, b, c); + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + vd[0] =3D f; + vd[1] =3D e; + vd[2] =3D b; + vd[3] =3D a; +} + +static void vsha2c_32(uint32_t *vs2, uint32_t *vd, uint32_t *vs1) +{ + uint32_t a =3D vs2[H4(3)], b =3D vs2[H4(2)], e =3D vs2[H4(1)], f =3D v= s2[H4(0)]; + uint32_t c =3D vd[H4(3)], d =3D vd[H4(2)], g =3D vd[H4(1)], h =3D vd[H= 4(0)]; + uint32_t W0 =3D vs1[H4(0)], W1 =3D vs1[H4(1)]; + uint32_t T1 =3D h + sum1_32(e) + ch(e, f, g) + W0; + uint32_t T2 =3D sum0_32(a) + maj(a, b, c); + + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + T1 =3D h + sum1_32(e) + ch(e, f, g) + W1; + T2 =3D sum0_32(a) + maj(a, b, c); + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + vd[H4(0)] =3D f; + vd[H4(1)] =3D e; + vd[H4(2)] =3D b; + vd[H4(3)] =3D a; +} + +void HELPER(vsha2ch32_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *e= nv, + uint32_t desc) +{ + const uint32_t esz =3D 4; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, + ((uint32_t *)vs1) + 4 * i + 2); + } + + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} + +void HELPER(vsha2ch64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *e= nv, + uint32_t desc) +{ + const uint32_t esz =3D 8; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, + ((uint64_t *)vs1) + 4 * i + 2); + } + + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} + +void HELPER(vsha2cl32_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *e= nv, + uint32_t desc) +{ + const uint32_t esz =3D 4; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, + (((uint32_t *)vs1) + 4 * i)); + } + + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} + +void HELPER(vsha2cl64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *e= nv, + uint32_t desc) +{ + uint32_t esz =3D 8; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, + (((uint64_t *)vs1) + 4 * i)); + } + + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index 817353f4d3..a35be11b95 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -371,3 +371,132 @@ static bool vaeskf2_check(DisasContext *s, arg_vaeskf= 2_vi *a) =20 GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check, ZVKNED_EGS) GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS) + +/* + * Zvknh + */ + +#define ZVKNH_EGS 4 + +#define GEN_VV_UNMASKED_TRANS(NAME, CHECK, EGS) = \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) = \ + { = \ + if (CHECK(s, a)) { = \ + uint32_t data =3D 0; = \ + TCGLabel *over =3D gen_new_label(); = \ + TCGv_i32 egs; = \ + = \ + if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { = \ + /* save opcode for unwinding in case we throw an exception= */ \ + decode_save_opc(s); = \ + egs =3D tcg_constant_i32(EGS); = \ + gen_helper_egs_check(egs, cpu_env); = \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);= \ + } = \ + = \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); = \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); = \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s= ); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ + = \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), = \ + vreg_ofs(s, a->rs2), cpu_env, = \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,= \ + data, gen_helper_##NAME); = \ + = \ + mark_vs_dirty(s); = \ + gen_set_label(over); = \ + return true; = \ + } = \ + return false; = \ + } + +static bool vsha_check_sew(DisasContext *s) +{ + return (s->cfg_ptr->ext_zvknha =3D=3D true && s->sew =3D=3D MO_32) || + (s->cfg_ptr->ext_zvknhb =3D=3D true && + (s->sew =3D=3D MO_32 || s->sew =3D=3D MO_64)); +} + +static bool vsha_check(DisasContext *s, arg_rmrr *a) +{ + int egw_bytes =3D ZVKNH_EGS << s->sew; + int mult =3D 1 << MAX(s->lmul, 0); + return opivv_check(s, a) && + vsha_check_sew(s) && + MAXSZ(s) >=3D egw_bytes && + !is_overlapped(a->rd, mult, a->rs1, mult) && + !is_overlapped(a->rd, mult, a->rs2, mult) && + s->lmul >=3D 0; +} + +GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check, ZVKNH_EGS) + +static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a) +{ + if (vsha_check(s, a)) { + uint32_t data =3D 0; + TCGLabel *over =3D gen_new_label(); + TCGv_i32 egs; + + if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { + /* save opcode for unwinding in case we throw an exception */ + decode_save_opc(s); + egs =3D tcg_constant_i32(ZVKNH_EGS); + gen_helper_egs_check(egs, cpu_env); + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); + } + + data =3D FIELD_DP32(data, VDATA, VM, a->vm); + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); + + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), + vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, + s->sew =3D=3D MO_32 ? + gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv); + + mark_vs_dirty(s); + gen_set_label(over); + return true; + } + return false; +} + +static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a) +{ + if (vsha_check(s, a)) { + uint32_t data =3D 0; + TCGLabel *over =3D gen_new_label(); + TCGv_i32 egs; + + if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { + /* save opcode for unwinding in case we throw an exception */ + decode_save_opc(s); + egs =3D tcg_constant_i32(ZVKNH_EGS); + gen_helper_egs_check(egs, cpu_env); + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); + } + + data =3D FIELD_DP32(data, VDATA, VM, a->vm); + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); + + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), + vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, + s->sew =3D=3D MO_32 ? + gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv); 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Co-authored-by: Kiran Ostrolenk [max.chou@sifive.com: Replaced vstart checking by TCG op] Signed-off-by: Kiran Ostrolenk Signed-off-by: Lawrence Hunter Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza [max.chou@sifive.com: Exposed x-zvksh property] Message-ID: <20230711165917.2629866-12-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/riscv/helper.h | 3 + target/riscv/insn32.decode | 4 + target/riscv/cpu.c | 6 +- target/riscv/vcrypto_helper.c | 134 +++++++++++++++++++++++ target/riscv/insn_trans/trans_rvvk.c.inc | 31 ++++++ 6 files changed, 177 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 800b8783c1..ab2d9294db 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -90,6 +90,7 @@ struct RISCVCPUConfig { bool ext_zvkned; bool ext_zvknha; bool ext_zvknhb; + bool ext_zvksh; bool ext_zmmul; bool ext_zvfbfmin; bool ext_zvfbfwma; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 34329b52fe..6d21347c39 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1270,3 +1270,6 @@ DEF_HELPER_5(vsha2ch32_vv, void, ptr, ptr, ptr, env, = i32) DEF_HELPER_5(vsha2ch64_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsha2cl32_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsha2cl64_vv, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e2b83186dc..4050e843f7 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -991,3 +991,7 @@ vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_v= m_1 vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** Zvksh vector crypto extension *** +vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f103f536fd..ce0d32eef3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -132,6 +132,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), + ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), @@ -1280,8 +1281,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) * In principle Zve*x would also suffice here, were they supported * in qemu */ - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha) = && - !cpu->cfg.ext_zve32f) { + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || + cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { error_setg(errp, "Vector crypto extensions require V or Zve* extensions"= ); return; @@ -1882,6 +1883,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false), DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false), + DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false), =20 DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 2f2099b6fb..e8bbb698c1 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -635,3 +635,137 @@ void HELPER(vsha2cl64_vv)(void *vd, void *vs1, void *= vs2, CPURISCVState *env, vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); env->vstart =3D 0; } + +static inline uint32_t p1(uint32_t x) +{ + return x ^ rol32(x, 15) ^ rol32(x, 23); +} + +static inline uint32_t zvksh_w(uint32_t m16, uint32_t m9, uint32_t m3, + uint32_t m13, uint32_t m6) +{ + return p1(m16 ^ m9 ^ rol32(m3, 15)) ^ rol32(m13, 7) ^ m6; +} + +void HELPER(vsm3me_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr, + CPURISCVState *env, uint32_t desc) +{ + uint32_t esz =3D memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW)); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t *vd =3D vd_vptr; + uint32_t *vs1 =3D vs1_vptr; + uint32_t *vs2 =3D vs2_vptr; + + for (int i =3D env->vstart / 8; i < env->vl / 8; i++) { + uint32_t w[24]; + for (int j =3D 0; j < 8; j++) { + w[j] =3D bswap32(vs1[H4((i * 8) + j)]); + w[j + 8] =3D bswap32(vs2[H4((i * 8) + j)]); + } + for (int j =3D 0; j < 8; j++) { + w[j + 16] =3D + zvksh_w(w[j], w[j + 7], w[j + 13], w[j + 3], w[j + 10]); + } + for (int j =3D 0; j < 8; j++) { + vd[(i * 8) + j] =3D bswap32(w[H4(j + 16)]); + } + } + vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} + +static inline uint32_t ff1(uint32_t x, uint32_t y, uint32_t z) +{ + return x ^ y ^ z; +} + +static inline uint32_t ff2(uint32_t x, uint32_t y, uint32_t z) +{ + return (x & y) | (x & z) | (y & z); +} + +static inline uint32_t ff_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j) +{ + return (j <=3D 15) ? ff1(x, y, z) : ff2(x, y, z); +} + +static inline uint32_t gg1(uint32_t x, uint32_t y, uint32_t z) +{ + return x ^ y ^ z; +} + +static inline uint32_t gg2(uint32_t x, uint32_t y, uint32_t z) +{ + return (x & y) | (~x & z); +} + +static inline uint32_t gg_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j) +{ + return (j <=3D 15) ? gg1(x, y, z) : gg2(x, y, z); +} + +static inline uint32_t t_j(uint32_t j) +{ + return (j <=3D 15) ? 0x79cc4519 : 0x7a879d8a; +} + +static inline uint32_t p_0(uint32_t x) +{ + return x ^ rol32(x, 9) ^ rol32(x, 17); +} + +static void sm3c(uint32_t *vd, uint32_t *vs1, uint32_t *vs2, uint32_t uimm) +{ + uint32_t x0, x1; + uint32_t j; + uint32_t ss1, ss2, tt1, tt2; + x0 =3D vs2[0] ^ vs2[4]; + x1 =3D vs2[1] ^ vs2[5]; + j =3D 2 * uimm; + ss1 =3D rol32(rol32(vs1[0], 12) + vs1[4] + rol32(t_j(j), j % 32), 7); + ss2 =3D ss1 ^ rol32(vs1[0], 12); + tt1 =3D ff_j(vs1[0], vs1[1], vs1[2], j) + vs1[3] + ss2 + x0; + tt2 =3D gg_j(vs1[4], vs1[5], vs1[6], j) + vs1[7] + ss1 + vs2[0]; + vs1[3] =3D vs1[2]; + vd[3] =3D rol32(vs1[1], 9); + vs1[1] =3D vs1[0]; + vd[1] =3D tt1; + vs1[7] =3D vs1[6]; + vd[7] =3D rol32(vs1[5], 19); + vs1[5] =3D vs1[4]; + vd[5] =3D p_0(tt2); + j =3D 2 * uimm + 1; + ss1 =3D rol32(rol32(vd[1], 12) + vd[5] + rol32(t_j(j), j % 32), 7); + ss2 =3D ss1 ^ rol32(vd[1], 12); + tt1 =3D ff_j(vd[1], vs1[1], vd[3], j) + vs1[3] + ss2 + x1; + tt2 =3D gg_j(vd[5], vs1[5], vd[7], j) + vs1[7] + ss1 + vs2[1]; + vd[2] =3D rol32(vs1[1], 9); + vd[0] =3D tt1; + vd[6] =3D rol32(vs1[5], 19); + vd[4] =3D p_0(tt2); +} + +void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, + CPURISCVState *env, uint32_t desc) +{ + uint32_t esz =3D memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW)); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t *vd =3D vd_vptr; + uint32_t *vs2 =3D vs2_vptr; + uint32_t v1[8], v2[8], v3[8]; + + for (int i =3D env->vstart / 8; i < env->vl / 8; i++) { + for (int k =3D 0; k < 8; k++) { + v2[k] =3D bswap32(vd[H4(i * 8 + k)]); + v3[k] =3D bswap32(vs2[H4(i * 8 + k)]); + } + sm3c(v1, v2, v3, uimm); + for (int k =3D 0; k < 8; k++) { + vd[i * 8 + k] =3D bswap32(v1[H4(k)]); + } + } + vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index a35be11b95..6469dd2f02 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -500,3 +500,34 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr= *a) } return false; } + +/* + * Zvksh + */ + +#define ZVKSH_EGS 8 + +static inline bool vsm3_check(DisasContext *s, arg_rmrr *a) +{ + int egw_bytes =3D ZVKSH_EGS << s->sew; + int mult =3D 1 << MAX(s->lmul, 0); + return s->cfg_ptr->ext_zvksh =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + !is_overlapped(a->rd, mult, a->rs2, mult) && + MAXSZ(s) >=3D egw_bytes && + s->sew =3D=3D MO_32; +} + +static inline bool vsm3me_check(DisasContext *s, arg_rmrr *a) +{ + return vsm3_check(s, a) && vext_check_sss(s, a->rd, a->rs1, a->rs2, a-= >vm); +} + +static inline bool vsm3c_check(DisasContext *s, arg_rmrr *a) +{ + return vsm3_check(s, a) && vext_check_ss(s, a->rd, a->rs2, a->vm); +} + +GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check, ZVKSH_EGS) +GEN_VI_UNMASKED_TRANS(vsm3c_vi, vsm3c_check, ZVKSH_EGS) --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414942; cv=none; d=zohomail.com; s=zohoarc; b=K3i2PFQQvipb6r8Ji14f1086fNn/0YBw3SIq+gaIjNiPVTsKijcmIqjECD11raDs8W2tv6FJ8nxoKQrNUgIwlweI9OSJm/41Dckjx6iJDxKHSdtjeOTpZzgkGb8wKYj1o+it6f71E8BrhSRVSjdFmkvSLg6tmvpDFMWrbGfAYGM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414942; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.44.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:44:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414693; x=1695019493; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CG534oqdKvZg93XhHJTveosyzNAkM7GvLcEv8iTROyU=; b=Bd/EtiIQ/mYcOuKELkCG1OuDPOtzjMteUMY+JJ3WyTt0EozLvSN3fXTyBUCx+70bM4 GOzAGOapV5iIZ2fKjPKyh8tzw38euJ/maZWzsINhQGAfQ8bSCz8pztxVPE483EfvY/y3 skco42Mg6KRrC/sJMrHQrLsIWakbAbz42IEmG6QvSwzFb5ZnJnLzt5Txvp+m2VCItXOA ToZXjEAI8FKH3EhtZ0YTpN8PQjz3lue5XLFc6xI6r/aQauJcbUYAj4Iynqfa9kd9C6hx wCtkzGZMJ0BTbJpHyUYbuF/gV5iP3xjsJ+VAt8HR8fMyynG1hd80rtZftIJZ/x5pRFeU myxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414693; x=1695019493; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CG534oqdKvZg93XhHJTveosyzNAkM7GvLcEv8iTROyU=; b=Idn9CmCEob2zpvpIiL2MWiJzF+2S3apcGlZUWat5b+yeAQejWt1o4/GVOFAbXUwYWb kNc22WsfRUl5whYI+3onQtKbQjqo6sRruVrYFSBWIg4p2fhQ+oGUvR+slFY+KBOb89Y+ nlXX2zAyWab+TsAaqdci+2jufaVc7db04wB4oaRvL/pRvQNey5IKM1J7Or7VIcX7p3fN Pdk0pWsSNQpCIqRDWTAs7WbwzhQceoxhKS4hw+UexXgXtTjtIj9CAnqN/0E81DJYfme3 ot5KFPq3JkWlYwGPEpbsxwrWYHYcOGy43VzML+g7NozWxwjcQXTjAOEJlDrl0WbmDlF5 6bMQ== X-Gm-Message-State: AOJu0Yzr17cAjaC4y1BRNlnhY3KupxEbWS4e+F7+v5MvbhI+OFewkusu flEMeulaoxIAXEAzNdsc8tPsGlycJLRXTA== X-Google-Smtp-Source: AGHT+IG4EWLu+7pUqFxDaTSsfFZojh3vsswM7X9oULkGiCKgbyqVjWlhPsgzgV8JyG/gZdBhWfd6vQ== X-Received: by 2002:a05:6358:7241:b0:13a:319f:a56b with SMTP id i1-20020a056358724100b0013a319fa56bmr11325226rwa.20.1694414693611; Sun, 10 Sep 2023 23:44:53 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Nazar Kazakov , Lawrence Hunter , Max Chou , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 19/45] target/riscv: Add Zvkg ISA extension support Date: Mon, 11 Sep 2023 16:42:54 +1000 Message-ID: <20230911064320.939791-20-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2a; envelope-from=alistair23@gmail.com; helo=mail-oo1-xc2a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414944229100001 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov This commit adds support for the Zvkg vector-crypto extension, which consists of the following instructions: * vgmul.vv * vghsh.vv Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Lawrence Hunter [max.chou@sifive.com: Replaced vstart checking by TCG op] Signed-off-by: Lawrence Hunter Signed-off-by: Nazar Kazakov Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza [max.chou@sifive.com: Exposed x-zvkg property] [max.chou@sifive.com: Replaced uint by int for cross win32 build] Message-ID: <20230711165917.2629866-13-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/riscv/helper.h | 3 + target/riscv/insn32.decode | 4 ++ target/riscv/cpu.c | 6 +- target/riscv/vcrypto_helper.c | 72 ++++++++++++++++++++++++ target/riscv/insn_trans/trans_rvvk.c.inc | 30 ++++++++++ 6 files changed, 114 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index ab2d9294db..b754ec2344 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -87,6 +87,7 @@ struct RISCVCPUConfig { bool ext_zve64d; bool ext_zvbb; bool ext_zvbc; + bool ext_zvkg; bool ext_zvkned; bool ext_zvknha; bool ext_zvknhb; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 6d21347c39..ceec97e165 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1273,3 +1273,6 @@ DEF_HELPER_5(vsha2cl64_vv, void, ptr, ptr, ptr, env, = i32) =20 DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) + +DEF_HELPER_5(vghsh_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_4(vgmul_vv, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4050e843f7..0fae01c6bb 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -995,3 +995,7 @@ vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_v= m_1 # *** Zvksh vector crypto extension *** vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** Zvkg vector crypto extension *** +vghsh_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ce0d32eef3..981907c033 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -129,6 +129,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), + ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), @@ -1281,8 +1282,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) * In principle Zve*x would also suffice here, were they supported * in qemu */ - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || - cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || + cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32= f) { error_setg(errp, "Vector crypto extensions require V or Zve* extensions"= ); return; @@ -1880,6 +1881,7 @@ static Property riscv_cpu_extensions[] =3D { /* Vector cryptography extensions */ DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false), DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), + DEFINE_PROP_BOOL("x-zvkg", RISCVCPU, cfg.ext_zvkg, false), DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false), DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false), diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index e8bbb698c1..a5e2f7fbb0 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -769,3 +769,75 @@ void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, u= int32_t uimm, vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); env->vstart =3D 0; } + +void HELPER(vghsh_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr, + CPURISCVState *env, uint32_t desc) +{ + uint64_t *vd =3D vd_vptr; + uint64_t *vs1 =3D vs1_vptr; + uint64_t *vs2 =3D vs2_vptr; + uint32_t vta =3D vext_vta(desc); + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + uint64_t Y[2] =3D {vd[i * 2 + 0], vd[i * 2 + 1]}; + uint64_t H[2] =3D {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])}; + uint64_t X[2] =3D {vs1[i * 2 + 0], vs1[i * 2 + 1]}; + uint64_t Z[2] =3D {0, 0}; + + uint64_t S[2] =3D {brev8(Y[0] ^ X[0]), brev8(Y[1] ^ X[1])}; + + for (int j =3D 0; j < 128; j++) { + if ((S[j / 64] >> (j % 64)) & 1) { + Z[0] ^=3D H[0]; + Z[1] ^=3D H[1]; + } + bool reduce =3D ((H[1] >> 63) & 1); + H[1] =3D H[1] << 1 | H[0] >> 63; + H[0] =3D H[0] << 1; + if (reduce) { + H[0] ^=3D 0x87; + } + } + + vd[i * 2 + 0] =3D brev8(Z[0]); + vd[i * 2 + 1] =3D brev8(Z[1]); + } + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); + env->vstart =3D 0; +} + +void HELPER(vgmul_vv)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, + uint32_t desc) +{ + uint64_t *vd =3D vd_vptr; + uint64_t *vs2 =3D vs2_vptr; + uint32_t vta =3D vext_vta(desc); + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + uint64_t Y[2] =3D {brev8(vd[i * 2 + 0]), brev8(vd[i * 2 + 1])}; + uint64_t H[2] =3D {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])}; + uint64_t Z[2] =3D {0, 0}; + + for (int j =3D 0; j < 128; j++) { + if ((Y[j / 64] >> (j % 64)) & 1) { + Z[0] ^=3D H[0]; + Z[1] ^=3D H[1]; + } + bool reduce =3D ((H[1] >> 63) & 1); + H[1] =3D H[1] << 1 | H[0] >> 63; + H[0] =3D H[0] << 1; + if (reduce) { + H[0] ^=3D 0x87; + } + } + + vd[i * 2 + 0] =3D brev8(Z[0]); + vd[i * 2 + 1] =3D brev8(Z[1]); + } + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); + env->vstart =3D 0; +} diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index 6469dd2f02..af7cd62e7d 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -531,3 +531,33 @@ static inline bool vsm3c_check(DisasContext *s, arg_rm= rr *a) =20 GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check, ZVKSH_EGS) GEN_VI_UNMASKED_TRANS(vsm3c_vi, vsm3c_check, ZVKSH_EGS) + +/* + * Zvkg + */ + +#define ZVKG_EGS 4 + +static bool vgmul_check(DisasContext *s, arg_rmr *a) +{ + int egw_bytes =3D ZVKG_EGS << s->sew; + return s->cfg_ptr->ext_zvkg =3D=3D true && + vext_check_isa_ill(s) && + require_rvv(s) && + MAXSZ(s) >=3D egw_bytes && + vext_check_ss(s, a->rd, a->rs2, a->vm) && + s->sew =3D=3D MO_32; +} + +GEN_V_UNMASKED_TRANS(vgmul_vv, vgmul_check, ZVKG_EGS) + +static bool vghsh_check(DisasContext *s, arg_rmrr *a) +{ + int egw_bytes =3D ZVKG_EGS << s->sew; + return s->cfg_ptr->ext_zvkg =3D=3D true && + opivv_check(s, a) && + MAXSZ(s) >=3D egw_bytes && + s->sew =3D=3D MO_32; +} + +GEN_VV_UNMASKED_TRANS(vghsh_vv, vghsh_check, ZVKG_EGS) --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414993; cv=none; d=zohomail.com; s=zohoarc; b=Yr50YEoqgl8lpyL8+SburAPP3Y/7U6qxQha/kMbB+u3TQ1U5HWtkcJ8YlieZYVgoVPIrXxKsFVet20wfTgUkVDiOD+3UlhZ9THd3F7WH+Fq+WGgI9fgfetWDiH+nW1ARv6yFT5KjSTPocJKvnF6fWUanVjSLuKogoH0QYs9Xylg= ARC-Message-Signature: i=1; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.44.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:44:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414697; x=1695019497; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KTZoQQBHRX8Eh4+DjB2iRGNyN+rFo0jz7PJ5kMgxxIY=; b=RDIXf3ZyNFSG+7ZvVG8VMlEYsM4QaTwD4V2eS2yq1WEuVLYc4avHXH3MYXLxn1KZRc ravhh8K/95cFRZFg1nG1eQCqIwRFntRD5lj5aNDA2OEb1n13KxPcRl3cNQtqx6SO9nd3 OWsI9ygTVa+s3PKN7rVLosFN/Jo2+T8aNRWUr/IXG1bNT8lKsgdCAM1KPfgd3QXC+z3w LSt1sn49sfPihZp3jAtdBmvvfykwguxgtv3tC+U36hwgUOfenUdw/YO5YSABIjqumae8 COauQJP+BPPXy12Ep0bht3Q2m2ZXszTqLzK08BSN/FRiUK8NhSQoYko2sCqf2EloZRye xvZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414697; x=1695019497; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KTZoQQBHRX8Eh4+DjB2iRGNyN+rFo0jz7PJ5kMgxxIY=; b=HOALf3U0U0YDXlWmnArhDprHppEKe+Z6rnhUCGFnnaVMNA7R7edS5bKEmBZN9+Wump 7QzfELn0q09uYQRjHr3GLSOV1icfs23atvGQJ+RCH4p6F9vA9UFPthKbYuz3gq/0lvig x4+UGUC5MxMSOU0/uAKTT9KJ4r292SfOSS+gYm1VVPmhRbD6pfsJcFEUBR6QnM6VnRDg xDOzTcCy+1Oomy7eExWVvq0B49cEkJDyOxt01Wg4D6D4JNugCrGC7svjdAM4bcz2NTUB zP99g0sGdJdzQLq0pUju8g7jWMJFqbG3vLcqmUFQ7RI28dnHByXZpOFgr1W1quYEGBhx fyzQ== X-Gm-Message-State: AOJu0YzmPFGSMUWCgQRWRxxBpH6eIuP8bilLHol+LkKSjploMoX+VLva iM7DaG5FWik58e09HLMsHEtKdQ/L7ZEbmQ== X-Google-Smtp-Source: AGHT+IESdESBxaCF3gC+BQPPgfRGDSJiUzzwr3FTA7LoJsSKJGSKZJIUqh6U8CLparNheG9lbwqUgw== X-Received: by 2002:a05:6a00:2d06:b0:68e:2c2a:5172 with SMTP id fa6-20020a056a002d0600b0068e2c2a5172mr12107251pfb.6.1694414697329; Sun, 10 Sep 2023 23:44:57 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Max Chou , Frank Chang , Richard Henderson , Alistair Francis Subject: [PULL v2 20/45] crypto: Create sm4_subword Date: Mon, 11 Sep 2023 16:42:55 +1000 Message-ID: <20230911064320.939791-21-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414994896100003 Content-Type: text/plain; charset="utf-8" From: Max Chou Allows sharing of sm4_subword between different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang Reviewed-by: Richard Henderson Signed-off-by: Max Chou Message-ID: <20230711165917.2629866-14-max.chou@sifive.com> Signed-off-by: Alistair Francis --- include/crypto/sm4.h | 8 ++++++++ target/arm/tcg/crypto_helper.c | 10 ++-------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h index 9bd3ebc62e..de8245d8a7 100644 --- a/include/crypto/sm4.h +++ b/include/crypto/sm4.h @@ -3,4 +3,12 @@ =20 extern const uint8_t sm4_sbox[256]; =20 +static inline uint32_t sm4_subword(uint32_t word) +{ + return sm4_sbox[word & 0xff] | + sm4_sbox[(word >> 8) & 0xff] << 8 | + sm4_sbox[(word >> 16) & 0xff] << 16 | + sm4_sbox[(word >> 24) & 0xff] << 24; +} + #endif diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index fdd70abbfd..7cadd61e12 100644 --- a/target/arm/tcg/crypto_helper.c +++ b/target/arm/tcg/crypto_helper.c @@ -614,10 +614,7 @@ static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn,= uint64_t *rm) CR_ST_WORD(d, (i + 3) % 4) ^ CR_ST_WORD(n, i); =20 - t =3D sm4_sbox[t & 0xff] | - sm4_sbox[(t >> 8) & 0xff] << 8 | - sm4_sbox[(t >> 16) & 0xff] << 16 | - sm4_sbox[(t >> 24) & 0xff] << 24; + t =3D sm4_subword(t); =20 CR_ST_WORD(d, i) ^=3D t ^ rol32(t, 2) ^ rol32(t, 10) ^ rol32(t, 18= ) ^ rol32(t, 24); @@ -651,10 +648,7 @@ static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *= rn, uint64_t *rm) CR_ST_WORD(d, (i + 3) % 4) ^ CR_ST_WORD(m, i); =20 - t =3D sm4_sbox[t & 0xff] | - sm4_sbox[(t >> 8) & 0xff] << 8 | - sm4_sbox[(t >> 16) & 0xff] << 16 | - sm4_sbox[(t >> 24) & 0xff] << 24; + t =3D sm4_subword(t); =20 CR_ST_WORD(d, i) ^=3D t ^ rol32(t, 13) ^ rol32(t, 23); } --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414781; cv=none; d=zohomail.com; s=zohoarc; b=ZAs93KAXmwlDeQFF8Iw6hsE0jA3cWP8iLAx+Hh8qdwdwFQvh9nTUBerYBhJqbUXPO0up3ATzj9F/FsJ+mx5Gyd1YBhVf+779+uy+S8cCZ+/FzoSp/s5NtcGSTq3NgkQTdT/rFfa98DHnUBtWU/elO7Djz6ply5pth917jdhX6KI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414781; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sW3nOVBepNUyjAGvpAdig0q954l70YYp+9BKZ+7kzlc=; b=Qsw1hQ8bVad82TViCHNpbkIpN4jWWv1UGa75eAyK7Jro4fp7/wV5VS3OOtY0jl2Z0KxwN5PDE6pvNEsc/CzpNyH/NeJlEh7f/bOTO6ZdAqim1VqsU4s+4vfyLWtGhAG0zaPe6swPeCnrHKNZN+ibv+gKz+njTyoMRUkJ3sd0oC0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414781102323.1214178883141; Sun, 10 Sep 2023 23:46:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfafS-0001nR-QC; Mon, 11 Sep 2023 02:45:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfafR-0001kq-3J for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:05 -0400 Received: from mail-oo1-xc33.google.com ([2607:f8b0:4864:20::c33]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfafO-0004fT-OC for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:04 -0400 Received: by mail-oo1-xc33.google.com with SMTP id 006d021491bc7-57124ee486dso2677788eaf.3 for ; Sun, 10 Sep 2023 23:45:02 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.44.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:44:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414701; x=1695019501; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sW3nOVBepNUyjAGvpAdig0q954l70YYp+9BKZ+7kzlc=; b=UFFhWbY0W5S7EZP5pCtSqkUhapkwuX+rmVFu7IE7z70ujNX8Dtg3VnsUH90Fwgh2vp pBKKsiftY2Jebm3ROa0y5kU8isRNQOTW4lzJr5/pu6P0kCsY0fsu7Y4q8x7KKqztw7Bb +4LTvcZUEnc9JjXKZsslYZhbqDn6OkGBoZn5WgvCkpFHXPhfqQJSfNGJWDEv9a0TWOrr U5LuFNLjMfce0oBMdYpg7L4ow6CO5tKCmQQkHyn3ltgbQWUx8nIvQH9O2yLFIUbfQY4N p1BgA+Ay+bKJBD66mAXd8JanOL2gvPRg3nPoSvXcI4ZbLbm/67ijxypmFvX3sg57wtY5 snXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414701; x=1695019501; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sW3nOVBepNUyjAGvpAdig0q954l70YYp+9BKZ+7kzlc=; b=h8e5z0usaaXcwFLnV9b3feAKiFrXzxv8GMBh/Tf5m27VJ9/58zc9noLq8R2Wthext+ Ctjq59u3aDlb/52yObWoWVvK6mfrcsp0T9iYH43BGIMLLB1HJF1MEosECZFuRwPkgr3a G7Br1KrEn3rAsXqguoErCCU9gYOrqyZjOxRqWggwkTsfTvstyswAaDybq3M0FmBi+URK e6PWtuj9pN88st+y3T9oeoc5on/znfKI08l46UtVjR9pPmIE1kgDTwWOAWvbWNqHPI1e 1OaU9KF3nZsKGvSQdLmrbVwXGYg704cISDzhsmybubjhFFD2RGpib6Dj5G/Rqtooqn/N 6l5g== X-Gm-Message-State: AOJu0YxGpu5c1E0yN2IEsgCPfbGHG2/MFqN8V1sR+GAWUNtamSgR9ydi 7vF16XdwbBrYBYUElBOXoxDQseG7KT1r/w== X-Google-Smtp-Source: AGHT+IF0ADbk6IoopBYRh9ysCJo2Y8GUubm1xOWKLc/ehcswANyrWYSTBKUfFzPkW7igDw3CxIOwUw== X-Received: by 2002:a05:6359:7387:b0:140:f08c:2b55 with SMTP id uz7-20020a056359738700b00140f08c2b55mr4713793rwb.9.1694414701134; Sun, 10 Sep 2023 23:45:01 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Max Chou , Frank Chang , Alistair Francis Subject: [PULL v2 21/45] crypto: Add SM4 constant parameter CK Date: Mon, 11 Sep 2023 16:42:56 +1000 Message-ID: <20230911064320.939791-22-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c33; envelope-from=alistair23@gmail.com; helo=mail-oo1-xc33.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414783020100007 Content-Type: text/plain; charset="utf-8" From: Max Chou Adds sm4_ck constant for use in sm4 cryptography across different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang Signed-off-by: Max Chou Message-ID: <20230711165917.2629866-15-max.chou@sifive.com> Signed-off-by: Alistair Francis --- include/crypto/sm4.h | 1 + crypto/sm4.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h index de8245d8a7..382b26d922 100644 --- a/include/crypto/sm4.h +++ b/include/crypto/sm4.h @@ -2,6 +2,7 @@ #define QEMU_SM4_H =20 extern const uint8_t sm4_sbox[256]; +extern const uint32_t sm4_ck[32]; =20 static inline uint32_t sm4_subword(uint32_t word) { diff --git a/crypto/sm4.c b/crypto/sm4.c index 9f0cd452c7..2987306cf7 100644 --- a/crypto/sm4.c +++ b/crypto/sm4.c @@ -47,3 +47,13 @@ uint8_t const sm4_sbox[] =3D { 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48, }; =20 +uint32_t const sm4_ck[] =3D { + 0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269, + 0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9, + 0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249, + 0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9, + 0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229, + 0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299, + 0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209, + 0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279 +}; --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414871; cv=none; d=zohomail.com; s=zohoarc; b=Pn4rIGpeaNnkcSQBqaSEoqmXSpN1Zp7jrPH6snWw5R/rqSe6IyHqptL2eCIHa62bhDhBPCpJABWKMbV4J91tp5cELt/+9gICC3af2BFnAttirUkwh4fDBbz6uULCKTV+NPr7X1fH/aVzkEhZTI4VVXF2XeQIK8RM41SnNMP5jVs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414871; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fh5NRbb/cu0m756EGY6sy0BB/1IMqMKi0hjfM6Xip7Q=; b=NFPL2Sey21fHhj3DwROvr/7kPBPfE5JdD2V7D/nNAQhjQAoIwyKoYZr7T6NKQqQc5R8xI8z/ts44lKf9R9+8CcXu+YOpcErK1CK7rOuKZ5EBhPx/iwAf8Fcdy/nsCj5/WY3ibk9uxUSwz3C4oIQg9wKDo5daqR29nwcKrrHTRlY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169441487161522.700510838568334; Sun, 10 Sep 2023 23:47:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagC-0002tP-DN; Mon, 11 Sep 2023 02:45:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfafY-0002II-KY for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:16 -0400 Received: from mail-oa1-x34.google.com ([2001:4860:4864:20::34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfafS-0004jC-7T for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:11 -0400 Received: by mail-oa1-x34.google.com with SMTP id 586e51a60fabf-1d5a8cb70d3so866053fac.0 for ; Sun, 10 Sep 2023 23:45:05 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.45.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:45:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414704; x=1695019504; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fh5NRbb/cu0m756EGY6sy0BB/1IMqMKi0hjfM6Xip7Q=; b=XqyCC7ycs5c0T7cGMbaq3FVce+WlSrtrtUt00CSii+2sfmTOGDML4kYmBrWE1gaHwR OX+y20uWbDwuFCSpOeTBIVtw4Nj2EAmO8NECEeWnKpi5mad+Vj1y+piUXeo4mPMOADSj sKylVI1AX3t1uzHuSdMoN/e/9mLB8cW3KMJq6VWQSeDGokoU5afzzZUSpC5ov8fQmzPK I9izH/qoAw4ikBV+zQzFg8reFQcIa4iuCexp0DG1wq8jqvlMPFp0ObndK5yacdOWE05q gPSHdjJOtQ9esx3jCzdcMQzaIWMW50mFNWBqZzSelZknZozsvxye/686hb865dfzkdPD wxKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414704; x=1695019504; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fh5NRbb/cu0m756EGY6sy0BB/1IMqMKi0hjfM6Xip7Q=; b=lixWZb9apjCt8x6U9UKfgYlCHPtf0mBu+IG4rEmRzdHnmzCeCcf507bvXtgSFmGGWO jRURaMowUqKsJkJu87OxV327xPscDs4DhxBT5sM7xhvXKVA3aVR+Af507gzGJwVfSZhD 6V6v+kHBOxzZx9f49xgq0xF9nVXh/atkWbNGIKfglmGrhOnE7Ub/gj53/XsBbbdACn++ 2l1doGSEetxZcxIp3rpjQkaScpXbVhE87vd7TtIpWL1dK/pM4D8C6nPixJWYEkw1oQLD PhT62DjW7Zdf9C1i18FdHk61TbYshUijK29azzs6oagaWLybU45NDn/5aAVlTwkbwEIj vDKg== X-Gm-Message-State: AOJu0YwrEpB29AZsJuDmmdV0z/YzNwCjLgGJg2W9D8ZU27pH6NAuTR41 IgLIZ/pf/CE3+MKJZbwR+AOn34ALPWIIeA== X-Google-Smtp-Source: AGHT+IEgT4h2jB/fYZvBgDdVd4gQwYunPG38fOBzs2n1GPXeGRdnmRB3ywV2hXoat/6gB7SKBg32gQ== X-Received: by 2002:a05:6870:a11b:b0:1bf:16f7:c901 with SMTP id m27-20020a056870a11b00b001bf16f7c901mr11678864oae.49.1694414704650; Sun, 10 Sep 2023 23:45:04 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Max Chou , Frank Chang , Alistair Francis Subject: [PULL v2 22/45] target/riscv: Add Zvksed ISA extension support Date: Mon, 11 Sep 2023 16:42:57 +1000 Message-ID: <20230911064320.939791-23-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::34; envelope-from=alistair23@gmail.com; helo=mail-oa1-x34.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414872967100003 Content-Type: text/plain; charset="utf-8" From: Max Chou This commit adds support for the Zvksed vector-crypto extension, which consists of the following instructions: * vsm4k.vi * vsm4r.[vv,vs] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Signed-off-by: Max Chou Reviewed-by: Frank Chang [lawrence.hunter@codethink.co.uk: Moved SM4 functions from crypto_helper.c to vcrypto_helper.c] [nazar.kazakov@codethink.co.uk: Added alignment checks, refactored code to use macros, and minor style changes] Signed-off-by: Max Chou Message-ID: <20230711165917.2629866-16-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/riscv/helper.h | 4 + target/riscv/insn32.decode | 5 + target/riscv/cpu.c | 5 +- target/riscv/vcrypto_helper.c | 127 +++++++++++++++++++++++ target/riscv/insn_trans/trans_rvvk.c.inc | 43 ++++++++ 6 files changed, 184 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index b754ec2344..61f6238756 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -91,6 +91,7 @@ struct RISCVCPUConfig { bool ext_zvkned; bool ext_zvknha; bool ext_zvknhb; + bool ext_zvksed; bool ext_zvksh; bool ext_zmmul; bool ext_zvfbfmin; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index ceec97e165..8a63523851 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1276,3 +1276,7 @@ DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) =20 DEF_HELPER_5(vghsh_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_4(vgmul_vv, void, ptr, ptr, env, i32) + +DEF_HELPER_5(vsm4k_vi, void, ptr, ptr, i32, env, i32) +DEF_HELPER_4(vsm4r_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 0fae01c6bb..33597fe2bb 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -999,3 +999,8 @@ vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_v= m_1 # *** Zvkg vector crypto extension *** vghsh_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1 vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1 + +# *** Zvksed vector crypto extension *** +vsm4k_vi 100001 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsm4r_vv 101000 1 ..... 10000 010 ..... 1110111 @r2_vm_1 +vsm4r_vs 101001 1 ..... 10000 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 981907c033..dc4b88e625 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -133,6 +133,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), + ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed), ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), @@ -1283,7 +1284,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) * in qemu */ if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || - cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32= f) { + cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh)= && + !cpu->cfg.ext_zve32f) { error_setg(errp, "Vector crypto extensions require V or Zve* extensions"= ); return; @@ -1885,6 +1887,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false), DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false), + DEFINE_PROP_BOOL("x-zvksed", RISCVCPU, cfg.ext_zvksed, false), DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false), =20 DEFINE_PROP_END_OF_LIST(), diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index a5e2f7fbb0..e2d719b13b 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -24,6 +24,7 @@ #include "cpu.h" #include "crypto/aes.h" #include "crypto/aes-round.h" +#include "crypto/sm4.h" #include "exec/memop.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -841,3 +842,129 @@ void HELPER(vgmul_vv)(void *vd_vptr, void *vs2_vptr, = CPURISCVState *env, vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); env->vstart =3D 0; } + +void HELPER(vsm4k_vi)(void *vd, void *vs2, uint32_t uimm5, CPURISCVState *= env, + uint32_t desc) +{ + const uint32_t egs =3D 4; + uint32_t rnd =3D uimm5 & 0x7; + uint32_t group_start =3D env->vstart / egs; + uint32_t group_end =3D env->vl / egs; + uint32_t esz =3D sizeof(uint32_t); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + + for (uint32_t i =3D group_start; i < group_end; ++i) { + uint32_t vstart =3D i * egs; + uint32_t vend =3D (i + 1) * egs; + uint32_t rk[4] =3D {0}; + uint32_t tmp[8] =3D {0}; + + for (uint32_t j =3D vstart; j < vend; ++j) { + rk[j - vstart] =3D *((uint32_t *)vs2 + H4(j)); + } + + for (uint32_t j =3D 0; j < egs; ++j) { + tmp[j] =3D rk[j]; + } + + for (uint32_t j =3D 0; j < egs; ++j) { + uint32_t b, s; + b =3D tmp[j + 1] ^ tmp[j + 2] ^ tmp[j + 3] ^ sm4_ck[rnd * 4 + = j]; + + s =3D sm4_subword(b); + + tmp[j + 4] =3D tmp[j] ^ (s ^ rol32(s, 13) ^ rol32(s, 23)); + } + + for (uint32_t j =3D vstart; j < vend; ++j) { + *((uint32_t *)vd + H4(j)) =3D tmp[egs + (j - vstart)]; + } + } + + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz= ); +} + +static void do_sm4_round(uint32_t *rk, uint32_t *buf) +{ + const uint32_t egs =3D 4; + uint32_t s, b; + + for (uint32_t j =3D egs; j < egs * 2; ++j) { + b =3D buf[j - 3] ^ buf[j - 2] ^ buf[j - 1] ^ rk[j - 4]; + + s =3D sm4_subword(b); + + buf[j] =3D buf[j - 4] ^ (s ^ rol32(s, 2) ^ rol32(s, 10) ^ rol32(s,= 18) ^ + rol32(s, 24)); + } +} + +void HELPER(vsm4r_vv)(void *vd, void *vs2, CPURISCVState *env, uint32_t de= sc) +{ + const uint32_t egs =3D 4; + uint32_t group_start =3D env->vstart / egs; + uint32_t group_end =3D env->vl / egs; + uint32_t esz =3D sizeof(uint32_t); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + + for (uint32_t i =3D group_start; i < group_end; ++i) { + uint32_t vstart =3D i * egs; + uint32_t vend =3D (i + 1) * egs; + uint32_t rk[4] =3D {0}; + uint32_t tmp[8] =3D {0}; + + for (uint32_t j =3D vstart; j < vend; ++j) { + rk[j - vstart] =3D *((uint32_t *)vs2 + H4(j)); + } + + for (uint32_t j =3D vstart; j < vend; ++j) { + tmp[j - vstart] =3D *((uint32_t *)vd + H4(j)); + } + + do_sm4_round(rk, tmp); + + for (uint32_t j =3D vstart; j < vend; ++j) { + *((uint32_t *)vd + H4(j)) =3D tmp[egs + (j - vstart)]; + } + } + + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz= ); +} + +void HELPER(vsm4r_vs)(void *vd, void *vs2, CPURISCVState *env, uint32_t de= sc) +{ + const uint32_t egs =3D 4; + uint32_t group_start =3D env->vstart / egs; + uint32_t group_end =3D env->vl / egs; + uint32_t esz =3D sizeof(uint32_t); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + + for (uint32_t i =3D group_start; i < group_end; ++i) { + uint32_t vstart =3D i * egs; + uint32_t vend =3D (i + 1) * egs; + uint32_t rk[4] =3D {0}; + uint32_t tmp[8] =3D {0}; + + for (uint32_t j =3D 0; j < egs; ++j) { + rk[j] =3D *((uint32_t *)vs2 + H4(j)); + } + + for (uint32_t j =3D vstart; j < vend; ++j) { + tmp[j - vstart] =3D *((uint32_t *)vd + H4(j)); + } + + do_sm4_round(rk, tmp); + + for (uint32_t j =3D vstart; j < vend; ++j) { + *((uint32_t *)vd + H4(j)) =3D tmp[egs + (j - vstart)]; + } + } + + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz= ); +} diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index af7cd62e7d..c00c70dfc6 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -561,3 +561,46 @@ static bool vghsh_check(DisasContext *s, arg_rmrr *a) } =20 GEN_VV_UNMASKED_TRANS(vghsh_vv, vghsh_check, ZVKG_EGS) + +/* + * Zvksed + */ + +#define ZVKSED_EGS 4 + +static bool zvksed_check(DisasContext *s) +{ + int egw_bytes =3D ZVKSED_EGS << s->sew; + return s->cfg_ptr->ext_zvksed =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + MAXSZ(s) >=3D egw_bytes && + s->sew =3D=3D MO_32; +} + +static bool vsm4k_vi_check(DisasContext *s, arg_rmrr *a) +{ + return zvksed_check(s) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul); +} + +GEN_VI_UNMASKED_TRANS(vsm4k_vi, vsm4k_vi_check, ZVKSED_EGS) + +static bool vsm4r_vv_check(DisasContext *s, arg_rmr *a) +{ + return zvksed_check(s) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul); +} + +GEN_V_UNMASKED_TRANS(vsm4r_vv, vsm4r_vv_check, ZVKSED_EGS) + +static bool vsm4r_vs_check(DisasContext *s, arg_rmr *a) +{ + return zvksed_check(s) && + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) && + require_align(a->rd, s->lmul); +} + +GEN_V_UNMASKED_TRANS(vsm4r_vs, vsm4r_vs_check, ZVKSED_EGS) --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414934; cv=none; d=zohomail.com; s=zohoarc; b=lgddn6Uusg0o/ePc4HJlcRAE+2JOa1puFIdvpEIZIFZxPdPHVMGNbajIjRPGNH/g1+42xNtnxbANo9+H+tin0tJhseHbQ1b4pLMa5mkB/9cm6XPPlveokEVKM4PsOWy12dK9rAOrVkWD0DO+rQVgPJQpJLASxHb/MOzremjTodo= ARC-Message-Signature: i=1; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.45.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:45:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414708; x=1695019508; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xCsrBGCOStJmv04kLZFtAJ2x5uul1n88A5rBVq3QvKM=; b=WcddKje0ZYXF/E5LXR+gYy2RvO9cKroQmku7OmU7WEfcu4WtyMKFJtnTLxv357N/FN eoPP0ERc9meNByF+FH6KsEz8Z36vX/KfdUZglHOaQjtSpw9zidjuYp0bbpwCRUoL9K9d XXOhvsu3tyniKJNotiXdW+vDXXfGQSmBPx8HiYWPP7807LpReA5oQoEnQSm456pj7j/p YRda4KXKwj4pwa+29ppiCPGPpixKNbhoYrmG3lgjN/h0m18DwFhd4IzmEfLKUKNwTOdt cFqSjOt+lLdylZok/r5sdTP5QJBJ4M9fBes7ksK/8oHXjrYmvlM030hBHreWXCLk7APg sdJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414708; x=1695019508; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xCsrBGCOStJmv04kLZFtAJ2x5uul1n88A5rBVq3QvKM=; b=iGoxD7+j/Q2bckwvli9c41UPIF+el15ymp/OmKywU15SOl1RwBeIc7muywxVMh0zkw HbhBVzKMitt10Z9O/aZhtLoxK1RAdJwg4bTQTyDgPkwLD0TTCUAKKxWPd8+Zppd1Q2dH r8gCUxtNj6UlctUwWN0NPHPUdwUWnV7z+rYOavDHBdpnBariGQ4/ED6bBeQowE8X/or8 CIlSPgfMv/i6v2PI0fp/5GulIDHOmTeopvjHB62EI3Q1mqp0tkL5w/fmIQNS2mRg7/ia 9dgxJ9lGo91HY8CY/5doINmskRoGSTGcxYGhxxmUJqwSD6JbeUlijpmeTxLLCZswsqz1 aEWw== X-Gm-Message-State: AOJu0YzOV5TZlK8j/pzCPi0yzsWgmoBxLnIn87i8WGcOW3lmNwGJWA2z AssnI34QSJKaUyjeUNsa+7mc0Jb/UeZVjA== X-Google-Smtp-Source: AGHT+IGahW4wu2D4Cf7+AczCiwuStSzpsRl9DZ3cHxYzPBZiOv+I0xrUN8vc7Q/8ouLgo/nTRyqkUg== X-Received: by 2002:a17:90b:180a:b0:273:7bf5:b1bf with SMTP id lw10-20020a17090b180a00b002737bf5b1bfmr16442727pjb.9.1694414708036; Sun, 10 Sep 2023 23:45:08 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Rob Bradford , Alistair Francis , Atish Patra Subject: [PULL v2 23/45] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren Date: Mon, 11 Sep 2023 16:42:58 +1000 Message-ID: <20230911064320.939791-24-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=alistair23@gmail.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414936218100007 Content-Type: text/plain; charset="utf-8" From: Rob Bradford These are WARL fields - zero out the bits for unavailable counters and special case the TM bit in mcountinhibit which is hardwired to zero. This patch achieves this by modifying the value written so that any use of the field will see the correctly masked bits. Tested by modifying OpenSBI to write max value to these CSRs and upon subsequent read the appropriate number of bits for number of PMUs is enabled and the TM bit is zero in mcountinhibit. Signed-off-by: Rob Bradford Acked-by: Alistair Francis Reviewed-by: Atish Patra Message-ID: <20230802124906.24197-1-rbradford@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ca95ae1527..661744e6d4 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1833,8 +1833,11 @@ static RISCVException write_mcountinhibit(CPURISCVSt= ate *env, int csrno, { int cidx; PMUCTRState *counter; + RISCVCPU *cpu =3D env_archcpu(env); =20 - env->mcountinhibit =3D val; + /* WARL register - disable unavailable counters; TM bit is always 0 */ + env->mcountinhibit =3D + val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_IR); =20 /* Check if any other counter is also monitoring cycles/instructions */ for (cidx =3D 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) { @@ -1857,7 +1860,11 @@ static RISCVException read_mcounteren(CPURISCVState = *env, int csrno, static RISCVException write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) { - env->mcounteren =3D val; + RISCVCPU *cpu =3D env_archcpu(env); + + /* WARL register - disable unavailable counters */ + env->mcounteren =3D val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTE= REN_TM | + COUNTEREN_IR); return RISCV_EXCP_NONE; } =20 --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694415001; cv=none; d=zohomail.com; s=zohoarc; b=Dqs8H/5NI5rPcZCo2pJZeGCTTtIkqcmorQIuyy9QaqUTxwt3pP0fSF1dSBrkTnp3Z+0I7Z8g+wlC/MOc7JHKgRRr0dCH/ccoxuTKHvQdTX01xulMu9szlYwz+Xuoq8tHeQJXWAV0xPJsQr1XrIRQSZJq8zlO+wvGNjtsyununxM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694415001; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=g72WiAV5qZ1oQb/83wFsWAvyLD7y1PtWQ+7+Ow3xVqA=; b=gSYfN0qFFRHlo7oe87tPI3bIzKCb/Zg3s7yyj+x3WN6/QDdrQXNo9SBSfqhrMI9eXTuOtnGZwwppcLAaf/BvL/nvSMSdmrdr7ChjHtrb8fd8awQJ4Wzyzz4fxLhdIZ79upGi7u4q5mdcb0tVlGzz0hpIW7Y4Xl5eY2qRzzJtDqk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694415001176390.02517952544565; Sun, 10 Sep 2023 23:50:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagV-0003av-0e; Mon, 11 Sep 2023 02:46:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfafc-0002Ou-Qo for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:19 -0400 Received: from mail-oi1-x22b.google.com ([2607:f8b0:4864:20::22b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfafa-0004tF-5i for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:16 -0400 Received: by mail-oi1-x22b.google.com with SMTP id 5614622812f47-3a812843f0fso2499496b6e.2 for ; Sun, 10 Sep 2023 23:45:12 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.45.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:45:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414712; x=1695019512; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g72WiAV5qZ1oQb/83wFsWAvyLD7y1PtWQ+7+Ow3xVqA=; b=Jfw3NfpEuxZX1wDK6hRbJqd2yCcvPrHMjwpHkShL1gb7VQ9iyHfNllsR+YTMlusLJ5 DDjUTIZvWZNXUfbD2v7mm/F+I/ZbL2hKfrOlK2+zJZujBJzOmanjNEfTecj3i+JdkiG7 xF+di4guaAqEJSYx1GaEgB5rr77fYb8BZxhx/hAvnSp8WEwhMOkCfES8ZJrn4IBvgeql tNeodUXWLlBV2a9ix0tbebTvAX1KH58w3GS+2JWKJfGYrWx5hsGbZ8uZk1dQOA4/Zm06 V7ad8XdRjIX9W75rZzT6G+b8bEswANTY4GN2MYmDL0/f/iFk6ICQE7HsklfbGepZMPa4 CSEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414712; x=1695019512; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g72WiAV5qZ1oQb/83wFsWAvyLD7y1PtWQ+7+Ow3xVqA=; b=Knz7Hwq95vk5K5CXKifLpAo2zOPL6gsw7YwYsioLVSIerjJwPdWhiMNzvNVKM/Q7m1 caQV9/7r600kaOz49qLSU+cDtJankXW+WRAOBdo1t1CI9PFiRRIePlsCnrPsS5qCs6sv 5WZMgovreNwNuwrz3KHTB8cw4POl3BUsinBWsbeD/b0VE0/4kfeOaYT4HWtHN0HIYLNr wEv43FdF8cXZUh1m9zseQP+ETXc4FHJNjvWvfnnJ6prGg4I+3yXTEhlTd0YZiErdaWVG gILken7B0fmrBxkzp4DX6K0wKrs8lsiiG4C2svR2ota8bFCm7EAVI3d81pb/ENgX3GvA w4nA== X-Gm-Message-State: AOJu0Yw8/ljAlC2uk8mIkRYA6rr4b3ixm6E6VRIAQfZC1V5MSGlPyZ2E c1krt6fLdU1vzzqjyqJYU6bNg8wuDDMH9Q== X-Google-Smtp-Source: AGHT+IHFPtCFB3WbC8IEGGtwqWtsQAGqRgtsMfU90NoPotAeR1xjZVfOZXncADTbhxPcPL60vqClgQ== X-Received: by 2002:a05:6808:2189:b0:3a4:6b13:b721 with SMTP id be9-20020a056808218900b003a46b13b721mr10207455oib.46.1694414711700; Sun, 10 Sep 2023 23:45:11 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Jason Chien , Frank Chang , Alistair Francis Subject: [PULL v2 24/45] target/riscv: Add Zihintntl extension ISA string to DTS Date: Mon, 11 Sep 2023 16:42:59 +1000 Message-ID: <20230911064320.939791-25-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=alistair23@gmail.com; helo=mail-oi1-x22b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694415003010100007 Content-Type: text/plain; charset="utf-8" From: Jason Chien RVA23 Profiles states: The RVA23 profiles are intended to be used for 64-bit application processors that will run rich OS stacks from standard binary OS distributions and with a substantial number of third-party binary user applications that will be supported over a considerable length of time in the field. The chapter 4 of the unprivileged spec introduces the Zihintntl extension and Zihintntl is a mandatory extension presented in RVA23 Profiles, whose purpose is to enable application and operating system portability across different implementations. Thus the DTS should contain the Zihintntl ISA string in order to pass to software. The unprivileged spec states: Like any HINTs, these instructions may be freely ignored. Hence, although they are described in terms of cache-based memory hierarchies, they do not mandate the provision of caches. These instructions are encoded with non-used opcode, e.g. ADD x0, x0, x2, which QEMU already supports, and QEMU does not emulate cache. Therefore these instructions can be considered as a no-op, and we only need to add a new property for the Zihintntl extension. Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Signed-off-by: Jason Chien Message-ID: <20230726074049.19505-2-jason.chien@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/riscv/cpu.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 61f6238756..0e6a0f245c 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -66,6 +66,7 @@ struct RISCVCPUConfig { bool ext_icbom; bool ext_icboz; bool ext_zicond; + bool ext_zihintntl; bool ext_zihintpause; bool ext_smstateen; bool ext_sstc; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index dc4b88e625..fae1c92c5c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -87,6 +87,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), + ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), @@ -1790,6 +1791,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), + DEFINE_PROP_BOOL("Zihintntl", RISCVCPU, cfg.ext_zihintntl, true), DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), DEFINE_PROP_BOOL("Zfa", RISCVCPU, cfg.ext_zfa, true), --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414979; cv=none; d=zohomail.com; s=zohoarc; b=FLbIEV/JNzPWW8BHwTj/ij5fAAxJUcs1gdh3LQFCFsk7cuxkNEcBedU8Ond65T3Yf+NLpf1L8iV9tifHPISQgvw+z3EvE3djBwtrE5/qC+BT/yxjRNr1eS6VV5mS8BbzKflAk/JFiGdzB54qPiHutgicsfGWQk/jRU0ToLCv39Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414979; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9c267mtx4FDo5BCCDJhdU8KtpdHS7OWZ9xPSR5tVl8Q=; b=OjcPGzxkIfphZbsB9CuxdrgE/IgnIXTJXeJKkE32KRarTwg2iyXkQBu2ccGK/TAND72bMeFMdv6P3tw8pqaawh0RsHTG3H9F8gkwpBdk7pjoXkV+ocuEePBVJf8LVBO6haw2vHbFRf8R1PNFblbYC3ydq+GIR+FrAvv0ql1CeWc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414979936296.2402181290539; Sun, 10 Sep 2023 23:49:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagI-0002zW-2F; Mon, 11 Sep 2023 02:45:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfafe-0002PN-Uz for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:19 -0400 Received: from mail-oi1-x234.google.com ([2607:f8b0:4864:20::234]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfafc-0004uc-Oy for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:18 -0400 Received: by mail-oi1-x234.google.com with SMTP id 5614622812f47-3ab2a0391c0so3173026b6e.1 for ; Sun, 10 Sep 2023 23:45:16 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.45.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:45:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414715; x=1695019515; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9c267mtx4FDo5BCCDJhdU8KtpdHS7OWZ9xPSR5tVl8Q=; b=eOky8bHGJ5CnCiRkiE6EEtX+excYiNDykYGfBYP+6N4oohvHs0lwTl7ghrrzjlQGAm hN4qPFNdfY85/Odp3BcKj23d1omFJvz1YMGRnHgQ1fdcrnT/EXab8y17hUku2c3Q6rdk Biyzdp6iViL8kU6lWH7mmRgvSJfGK8LGUl6m8BmJqe/+MSdx0SrAd4KvSKTuYnejGGXT NkKd4DNsCQj6uqkyll9z+gyMJ9v7gTZvhllUE0HNBD9jFY5LlWc6ja7N/DlfW5yHI4pN Fsy3qpm5Dn+49yAwVFbEk8MAfPSzg7QniHJ5mJgQEhSW3D9yADB4NX1jxCXWxtptZOB4 7fWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414715; x=1695019515; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9c267mtx4FDo5BCCDJhdU8KtpdHS7OWZ9xPSR5tVl8Q=; b=ev+XYhS4RniaMYJFwt13QVu1ZB/RaxG4JKIEKuadpOAfc/uUD90r3xQUAOX2miS4yH F8Eu0kJwKcDez08BTqYg77mKsDHUv0zlXkytekF8HTa4xa9/VD3cBRB6EKaoum9L13er gvdaAi6i5GmYduK/ZAK9FBAZSqHLwM8OW6/NvfH3uhu6jlKP64gi7SxgAeXY6p28wcR3 DPGt/PacGO8a9GDaFeSFR3A0N4eg8CN1N0v+0v68+AgvhFR9+pDAhh+8/ZpOGil3kcye 7Td8Yeq7kzT66FKc5TyxAZV9vWPu2uJ/UHl9RuJa4khYrOumEKEpvEaoYjSz9m0Smuar 6TRg== X-Gm-Message-State: AOJu0Yy4MYXWswnpf9pTiS7K/BR7UQQDIjfaJXaGS0YEpcusG/0WDOUK Us+IDiyummg1lWhim0mbpBSZhvs/oou9iQ== X-Google-Smtp-Source: AGHT+IHBIiKhj5xpfiL30kMNpW6K3HslAibRXUxdrVttWUwg6iTDKGvCZgT08wUCKbtO3Ik/ErLV1w== X-Received: by 2002:a05:6808:1152:b0:3a7:330d:93da with SMTP id u18-20020a056808115200b003a7330d93damr13804293oiu.19.1694414715414; Sun, 10 Sep 2023 23:45:15 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, LIU Zhiwei , Daniel Henrique Barboza , Weiwei Li , Alistair Francis Subject: [PULL v2 25/45] target/riscv: Fix zfa fleq.d and fltq.d Date: Mon, 11 Sep 2023 16:43:00 +1000 Message-ID: <20230911064320.939791-26-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=alistair23@gmail.com; helo=mail-oi1-x234.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414981002100001 Content-Type: text/plain; charset="utf-8" From: LIU Zhiwei Commit a47842d ("riscv: Add support for the Zfa extension") implemented the= zfa extension. However, it has some typos for fleq.d and fltq.d. Both of them misused the = fltq.s helper function. Fixes: a47842d ("riscv: Add support for the Zfa extension") Signed-off-by: LIU Zhiwei Reviewed-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Message-ID: <20230728003906.768-1-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvzfa.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvzfa.c.inc b/target/riscv/insn_= trans/trans_rvzfa.c.inc index 2c715af3e5..0fdd2698f6 100644 --- a/target/riscv/insn_trans/trans_rvzfa.c.inc +++ b/target/riscv/insn_trans/trans_rvzfa.c.inc @@ -470,7 +470,7 @@ bool trans_fleq_d(DisasContext *ctx, arg_fleq_d *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fltq_s(dest, cpu_env, src1, src2); + gen_helper_fleq_d(dest, cpu_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -485,7 +485,7 @@ bool trans_fltq_d(DisasContext *ctx, arg_fltq_d *a) TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fltq_s(dest, cpu_env, src1, src2); + gen_helper_fltq_d(dest, cpu_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414951; cv=none; d=zohomail.com; s=zohoarc; b=OyqRxPXFt9lhZW6l2iz+YAwcB2Gs01X8S6Jm/7YtvbBGk0G086+2rbG7PL/FBGU+sRjL28ocTVWwuYHjUVLfPdSCjKR4LtR3rb9cS7bDpT0rdiIOVdJ6PJEshvls5IoTcy4teMBpnJc5Jsgtcc4pofbkKKUrswXHMPbqnd0+iyk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414951; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RbNY4sxLzfh+2ICvNwghFUDrAY++mutb7jKSlH2h1II=; b=RDDOfSB9iv0FMWkH31aVQaa+Y0Rut4X8Hdq4E32++6EHZUZQuNeDI0B+8yFZfcWgSA0wSArOq/X8iByOKo6NUMxcPSRUos/8KrG7jNS8a3nU77Y3OI4DqHV4dJRizEMGikHtZMAvY26oKXO3ijCgClnn52mthmHNunlHCphbDT0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414951557357.8342846591653; Sun, 10 Sep 2023 23:49:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagP-00038t-2a; Mon, 11 Sep 2023 02:46:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfafl-0002Vw-2a for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:27 -0400 Received: from mail-ot1-x32b.google.com ([2607:f8b0:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfafg-0004wp-BJ for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:22 -0400 Received: by mail-ot1-x32b.google.com with SMTP id 46e09a7af769-6bf298ef1f5so2990132a34.0 for ; Sun, 10 Sep 2023 23:45:19 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.45.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:45:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414718; x=1695019518; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RbNY4sxLzfh+2ICvNwghFUDrAY++mutb7jKSlH2h1II=; b=VYHzoOsyMqNRZrPBmBCo31CYKGbRygXILGlvkJxMzpGJI+sH6NYitTPX+qa5BqLS+i GwiqTAuaITPmtRLVBy6ZxskoKULGMU+chl33+LSjBTwQSPtaRK9DAG9oMyDhsc00hCXz OBs53ZzPAeVv1ublMreU/5DxQOBMrWo9ZMJrxArup2KZpw6GQ4gyIhAM0kJJ314My/ZR yunGOWoHywaEUpZ/k7cZryp48rAwU2ah6nfbAPaUBWin1YiYV3XsScJP7l2wWgQQo/aL 121PSAxQHfdtLbJLr7QuDO2GZMOigiBd+9pJtKtns9txTgrXdDVCBFrTh/KON65j2w9d VLVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414718; x=1695019518; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RbNY4sxLzfh+2ICvNwghFUDrAY++mutb7jKSlH2h1II=; b=kJ2HSIAPL97KhtI5PpeH22tmECRya69PjU60L3gofg5MdWVRGZJ1tBPwKvWqIOzXWT b/dLAtqaSephKPs8012E1aAwvkLaKuTxWlaMRHMBJbZcAWdi9Y6r5gEOPem/KWYTctEr 3ieOnGpvZJ/UowF8HAAXr0GKyKNhq5I8XFTL0bEHeEVjG8pPxzLAQOAGwDFnzFXy3qN6 UyjFgsfML/6tT17SQFuvM7TjpSKyHQDvPKhfNsP7bYJmuhdRPIqzKfQ6mQPsobNjA0h6 V5LpevHNx1q7vHpMSC3lyXLL1WNCs67GLSxRiOpNCRff4eYkuu58i2UCAHX2pCiv0PHl Z17Q== X-Gm-Message-State: AOJu0YyGPcOhln6VgKGSlTZiRoxsqz8ift8wPQkwEy/YlLNBIPfBVA9M zmQcJkRfNmE5c1m93DOUSYxToQLf6rqhTQ== X-Google-Smtp-Source: AGHT+IEX9KKxz6AMnkhmuzQGFuq0k9a0YyKVKuDRtR8vxlDV25xosQnn2gUJ69h0ioreTNukkVTaqw== X-Received: by 2002:a05:6358:3422:b0:134:de8b:17f0 with SMTP id h34-20020a056358342200b00134de8b17f0mr9698587rwd.19.1694414718546; Sun, 10 Sep 2023 23:45:18 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Jason Chien , Alistair Francis Subject: [PULL v2 26/45] hw/intc: Fix upper/lower mtime write calculation Date: Mon, 11 Sep 2023 16:43:01 +1000 Message-ID: <20230911064320.939791-27-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=alistair23@gmail.com; helo=mail-ot1-x32b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414952395100005 Content-Type: text/plain; charset="utf-8" From: Jason Chien When writing the upper mtime, we should keep the original lower mtime whose value is given by cpu_riscv_read_rtc() instead of cpu_riscv_read_rtc_raw(). The same logic applies to writes to lower mtime. Signed-off-by: Jason Chien Reviewed-by: Alistair Francis Message-ID: <20230728082502.26439-1-jason.chien@sifive.com> Signed-off-by: Alistair Francis --- hw/intc/riscv_aclint.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index b466a6abaf..bf77e29a70 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -208,11 +208,12 @@ static void riscv_aclint_mtimer_write(void *opaque, h= waddr addr, return; } else if (addr =3D=3D mtimer->time_base || addr =3D=3D mtimer->time_b= ase + 4) { uint64_t rtc_r =3D cpu_riscv_read_rtc_raw(mtimer->timebase_freq); + uint64_t rtc =3D cpu_riscv_read_rtc(mtimer); =20 if (addr =3D=3D mtimer->time_base) { if (size =3D=3D 4) { /* time_lo for RV32/RV64 */ - mtimer->time_delta =3D ((rtc_r & ~0xFFFFFFFFULL) | value) = - rtc_r; + mtimer->time_delta =3D ((rtc & ~0xFFFFFFFFULL) | value) - = rtc_r; } else { /* time for RV64 */ mtimer->time_delta =3D value - rtc_r; @@ -220,7 +221,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwa= ddr addr, } else { if (size =3D=3D 4) { /* time_hi for RV32/RV64 */ - mtimer->time_delta =3D (value << 32 | (rtc_r & 0xFFFFFFFF)= ) - rtc_r; + mtimer->time_delta =3D (value << 32 | (rtc & 0xFFFFFFFF)) = - rtc_r; } else { qemu_log_mask(LOG_GUEST_ERROR, "aclint-mtimer: invalid time_hi write: %08x", --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414925; cv=none; d=zohomail.com; s=zohoarc; b=M0WF7oIztFbZRnIrTsif4iRo5u3VyaV/LQCIEE4BuZPH8TuCiO8KDoYTm9sszNO6b8P1HfABn+LqAznvAJQbobJ3ffkaCPfDMsEQxBgc1WtyYy57lMbTHU372TJshkJ5pitx+Yjx8VhoXs0E2HyG9D+xJzhzeMWu5bmCoK/vdqY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414925; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ccGf/43x5nzKqeckplvIj3QC6H4I6RRe2CJqwTH4Zqo=; b=efa4vhZhityJSOh6MNSaoecNrOQDUAC8+uwaAdKZgmt4O8wAb5UMztucRSazmCE8Uw2Rx/7noUvLbwvBqGkA+yqIPHkRiwdgrLDVKwu0A0qPfRhT1DNHh3zSh1ugqgvTXf2U3lylRGKQ/vIlm6071lDM66jDKJDrWOEh6vCCjpM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414925923761.2265294417779; Sun, 10 Sep 2023 23:48:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagP-000392-2p; Mon, 11 Sep 2023 02:46:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfafp-0002a7-1W for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:32 -0400 Received: from mail-oa1-x34.google.com ([2001:4860:4864:20::34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfafk-0004yp-OH for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:28 -0400 Received: by mail-oa1-x34.google.com with SMTP id 586e51a60fabf-1d544a4a315so3186959fac.3 for ; Sun, 10 Sep 2023 23:45:22 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.45.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:45:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414721; x=1695019521; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ccGf/43x5nzKqeckplvIj3QC6H4I6RRe2CJqwTH4Zqo=; b=l78ZIk/Ya75/XN2VH273NULrt9fIy2iCWH24h8Jxd0elOZ/Gy0Y9uVsdHh4YrmXnaX NZ+pKw6zr7pqdGjEtJvmTQWgfFsWLrApAU8lCfGgs/f2AP5c4feiqjkdduzacHnD8n7x adw3t/fYBvzHHx+kgBAjfVndfcs0ybhKc9okWZt63/5tiqSHv8xkoiALJH+zje3KU553 7CcW/0k/NKLUMlSVTG7r/D8nqpR3GczsYN2iQyyMScFJVWf2EB5Js5iH4ApcgYuIige0 F4MJRjeQY2d1RtyfhLxngKhAkpij68zbsoJNhjk79XSrIVWutW8MY66C/qjmKe2eJ9bS NW9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414721; x=1695019521; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ccGf/43x5nzKqeckplvIj3QC6H4I6RRe2CJqwTH4Zqo=; b=SVUkof1zJx2UPX76wi8mjfKXz65bBOahvX3UaOBFkwFnQ70/Y2jVmm0LerNqn+6k20 uqy6aUol6jtAw5cowQ/qUsUyXThGoXcZTPfWloIUI+lyiaHXmKRdCgcPoALIPOPthiyv leLEG1d44zx8ZJppBZ1ktbTlWKSJsJp6Zb8VDBAZ2AZoQkTEIedccisDDT9phfacnYgj mfxjuAYcYemvxCNkipqJ9mnMHk4U0utatgelLDGI+q12ed9lWk2FwLNSEqb6ya9ZdxsU MZAOfnzlP8Pc7dWpRAicQ/RWHQyS3jHsaRFNnhqtiTrWAs99SvVgy5xHb3A04uUKd7hJ RS6A== X-Gm-Message-State: AOJu0YxVAdw6arKjjx6d0Ar9CP8R6VNOm4Euzq789D8GtEqr8tTvur+9 AgjRnBJ+FqCLJEWiKM/8Rj2YNGQrmRH2Hw== X-Google-Smtp-Source: AGHT+IGgqAZeAe9tRs/gCJ7VvBy5tHnMXA7bHnlZx9w6XVQqL3e7hv3JfVnr8/+Qc7zBzdVsgmgJ9Q== X-Received: by 2002:a05:6870:f225:b0:1ba:2a58:b15e with SMTP id t37-20020a056870f22500b001ba2a58b15emr11411592oao.2.1694414721703; Sun, 10 Sep 2023 23:45:21 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Jason Chien , Alistair Francis Subject: [PULL v2 27/45] hw/intc: Make rtc variable names consistent Date: Mon, 11 Sep 2023 16:43:02 +1000 Message-ID: <20230911064320.939791-28-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::34; envelope-from=alistair23@gmail.com; helo=mail-oa1-x34.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414927931100019 Content-Type: text/plain; charset="utf-8" From: Jason Chien The variables whose values are given by cpu_riscv_read_rtc() should be named "rtc". The variables whose value are given by cpu_riscv_read_rtc_raw() should be named "rtc_r". Signed-off-by: Jason Chien Reviewed-by: Alistair Francis Message-ID: <20230728082502.26439-2-jason.chien@sifive.com> Signed-off-by: Alistair Francis --- hw/intc/riscv_aclint.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index bf77e29a70..25cf7a5d9d 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -64,13 +64,13 @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAcli= ntMTimerState *mtimer, uint64_t next; uint64_t diff; =20 - uint64_t rtc_r =3D cpu_riscv_read_rtc(mtimer); + uint64_t rtc =3D cpu_riscv_read_rtc(mtimer); =20 /* Compute the relative hartid w.r.t the socket */ hartid =3D hartid - mtimer->hartid_base; =20 mtimer->timecmp[hartid] =3D value; - if (mtimer->timecmp[hartid] <=3D rtc_r) { + if (mtimer->timecmp[hartid] <=3D rtc) { /* * If we're setting an MTIMECMP value in the "past", * immediately raise the timer interrupt @@ -81,7 +81,7 @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAclint= MTimerState *mtimer, =20 /* otherwise, set up the future timer interrupt */ qemu_irq_lower(mtimer->timer_irqs[hartid]); - diff =3D mtimer->timecmp[hartid] - rtc_r; + diff =3D mtimer->timecmp[hartid] - rtc; /* back to ns (note args switched in muldiv64) */ uint64_t ns_diff =3D muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_f= req); =20 --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414933; cv=none; d=zohomail.com; s=zohoarc; b=M9Vlnh0uNwLvstjaCX+jEAS+yplWfp5FNm/wuzI1zg7erPxNYjf6t3oTQyuSM5UJ0SjLJyI01out7HOWCEpPWXQ5hCdVzffqFWcUcn4SukdLLxH8MZwk4qDLXB0h9XYreK5iOWuhNmtMaYHHXoYjaQZQ7xG0g2kjInHo9IcWf7w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414933; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=s9QHVi3wOzOBTnchANYcU4Sl/KIRcnvifC0QwRT4WCQ=; b=Kz2uU44PlpBC2n39aHyG/uuWKd1IOkSFskDQUANLjdqh6j5AbfPoPAazEYs6uKRxeowoKA6R5hvhMqkNZJS6s2w8xNnhYLLc4Zwr64HJ769w3TAYNh7PKRv6Vnim086V299ZCSjXOYEPhDr20CCtOKNvFItv50lnG8W4pktPPLQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16944149335581014.3861213548953; Sun, 10 Sep 2023 23:48:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagY-0003et-PT; Mon, 11 Sep 2023 02:46:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfafq-0002jf-Fk for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:33 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfafo-00051d-6k for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:30 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-68fb7fb537dso688941b3a.2 for ; Sun, 10 Sep 2023 23:45:27 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.45.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:45:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414726; x=1695019526; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=s9QHVi3wOzOBTnchANYcU4Sl/KIRcnvifC0QwRT4WCQ=; b=DamTlWPBpPu8GR3df+JHTFLT1EvMJ7Wq914e6K2cYAgJvTmxQ5Z/TXmM7s/1PRxoPx LI8Uvk1CeLO7q70GCIL6Kw68t2iLQCgkif4YnugjW+YqB+mKSTXA3Qss/6U2pHKwdrcQ ZaJhBqki9bHYl2FNK1sB0EfsHoAy1M+lD0esbwbVDLhQQim3TVjFyOndXPJJ2XQKiQfc onTxCJPxxfyt4XG+9DL/KCjClvkCb3xrSrilt+KKSwkwVpoXFQJ01Un8rlizamPWg1N8 qMcgjszBgag8mGsFDMW/UxaMTUYBxLzyH9H4I9cqcz/nIbXmPafiRUlTcBGPsSlozKL4 nmtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414726; x=1695019526; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s9QHVi3wOzOBTnchANYcU4Sl/KIRcnvifC0QwRT4WCQ=; b=SnF/Fu4wEetwrznz86Nt0W3TxYBRGgrCnKWYP2pQIWYzPNvOILy93uxdz8SMC8wzPf yzk+M5qXWjdc2HX2bDQjlLHW/taDibfN0cPpykVc6Su8QLn1dErmcwlLFbaeRtX9QxH+ 5Pqaj/9CJMQ4u3z06fi0pHnFwnNEnuBluL6rchg32MhUgZjM0qN31qkcmps31U5g13XE RWFuAQ1sTDjWxq3RKudDv8AnhkOTrG7NR/sV4gAQAiFiD9+bYhrbilJG+c+GTydUTRQe 3qugI08RG8yCZvyuFfJfe2depwx9IlOL6v3v8Yq18bseCyL6+n1hiN4k8vjjBurGPIub PQwg== X-Gm-Message-State: AOJu0YwrVing0z9MJoTQHDHqPVEFHLr9CcfknRp4TyIbT4lBimzFI1hl DdloeEjREL6jRnQr3h9sEm69Z1DCwkITEw== X-Google-Smtp-Source: AGHT+IGE1HaLby79ASquSyO64T38p1dwtsaXWt9ueOFD7md0hnAIuT0SR8U1WTehXo+Zs8JbTPjXKw== X-Received: by 2002:a05:6a00:2d11:b0:68b:daa9:7bf2 with SMTP id fa17-20020a056a002d1100b0068bdaa97bf2mr8723061pfb.7.1694414725725; Sun, 10 Sep 2023 23:45:25 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, LIU Zhiwei , Richard Henderson , Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL v2 28/45] linux-user/riscv: Use abi type for target_ucontext Date: Mon, 11 Sep 2023 16:43:03 +1000 Message-ID: <20230911064320.939791-29-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=alistair23@gmail.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414934082100001 From: LIU Zhiwei We should not use types dependend on host arch for target_ucontext. This bug is found when run rv32 applications. Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20230811055438.1945-1-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis --- linux-user/riscv/signal.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c index eaa168199a..f989f7f51f 100644 --- a/linux-user/riscv/signal.c +++ b/linux-user/riscv/signal.c @@ -38,8 +38,8 @@ struct target_sigcontext { }; /* cf. riscv-linux:arch/riscv/include/uapi/asm/ptrace.h */ =20 struct target_ucontext { - unsigned long uc_flags; - struct target_ucontext *uc_link; + abi_ulong uc_flags; + abi_ptr uc_link; target_stack_t uc_stack; target_sigset_t uc_sigmask; uint8_t __unused[1024 / 8 - sizeof(target_sigset_t)]; --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414937; cv=none; d=zohomail.com; s=zohoarc; b=aXFlcOxLf6wbJRDP+24kaoCtHZdsq/QwL48lQR8uFG8MwO7hB4SSOndpVQJoUX6vzfr+JIIYMH+pvrHpRkcJXNj9V155ugcPI7kVcrqbRTx1zK5l3M6fWG05+ZHHVpO2Z6vxYJVdV8ZYp+MQ7m1igQxTgBEJ/uDAsHua78CQ+44= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414937; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bXqHn2YKT+j1879LOqFmr+mGqpuhppW4yiS7eOHb+XE=; b=XKu7P0runwK/8B8NiWA5RNQ4B7U1qx0u39cdShnGA+pBUH/MOFiyWJUQjvqLeEg28ZoAtfLThWjr7UwnyVTVoyJ8+I13RVuaQOhVRhlS3/RlS68DL3Xig8dftdRSrho/JO9XaUammm8XgxgzIHJ3mpoodM55xMUhfjn0/4dW1WQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414937379126.87478487364024; Sun, 10 Sep 2023 23:48:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagR-0003MO-HI; Mon, 11 Sep 2023 02:46:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfafw-0002qG-0t for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:39 -0400 Received: from mail-oi1-x22d.google.com ([2607:f8b0:4864:20::22d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfafr-00053u-DF for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:34 -0400 Received: by mail-oi1-x22d.google.com with SMTP id 5614622812f47-3a88ef953adso3286472b6e.0 for ; Sun, 10 Sep 2023 23:45:31 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.45.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:45:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414730; x=1695019530; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bXqHn2YKT+j1879LOqFmr+mGqpuhppW4yiS7eOHb+XE=; b=khugNoMAorCIRFP41/MnoKdFYafWPEV0LCV7Pwe568NEnHviVlpoNMV8gLJfk3sLpI CNP+7z3vnyoDjk3ILdSbLbRhSBloJbPU0gWB4qvhKT9jAuwUm5+OdaJkSyqVmr9WTxxB 5C6bCQ+EtG9plf72AyCByZeTZoEr22tNrhSk6wDBxYBeBlWC4CAcp+MnqWPSS6zVRPiD qwBmAiOnE1Ma2tnHRvmStWlo6f/Vd0ZlLyH9Y0JHBDRyOZH5uJt0IX1JTf6nLhqkvstr VhQWiGZNsROISQRyNTxKGTUqab3JJXxlD4H1NjOOLeWR8LneEwSMcdpVe18ybq8Lhfer bL5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414730; x=1695019530; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bXqHn2YKT+j1879LOqFmr+mGqpuhppW4yiS7eOHb+XE=; b=u9mQkVc6dulFbug0ynS4Um0aJArTvYdqtDRCYfGL3IGJDOkZOzqXrycKYIRWfTBWqV nnQV0BlRrntbpUDxF2Qw4G823KesXN8DZKq/UmbQ4EhBNajLy/d9v169tVCO/g5kkkXK beW0YYaIoTnRheCnuK4OUK0XqnZb7Td9YBLjEgnA5k5kpTBoX5qHQJ2gHfAaSrd+2eRl 040ySDyPMq773taUEEuMqgJrUJzapyZws6+TCPUJfZQrq/9G8K6VGK+ckNNVHZiG/2in viyCJxC0o08651hfgCcW1M6etDbVuRKBkG8tu9u189fj2wJ8ocr4bh8J8blG6aZ1y8nL Y1Xw== X-Gm-Message-State: AOJu0YyfXAuPfWhVWeF6aiQncygMXcKVec2NnxFkrILqmsqlViDPCCPQ gViwGo8zQuO7NsWWRz0rqDVty1eZqxkDoA== X-Google-Smtp-Source: AGHT+IFsiMa8HYuWkihjFZKGj2UWt3bliNRxUufgvRqe190TciYzcUST0FW30Y6BEQ3fRDpl/Thbcg== X-Received: by 2002:aca:6743:0:b0:3a9:ba39:6d4a with SMTP id b3-20020aca6743000000b003a9ba396d4amr9854603oiy.18.1694414729794; Sun, 10 Sep 2023 23:45:29 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Yong-Xuan Wang , Jim Shu , Daniel Henrique Barboza , Andrew Jones , Alistair Francis Subject: [PULL v2 29/45] target/riscv: support the AIA device emulation with KVM enabled Date: Mon, 11 Sep 2023 16:43:04 +1000 Message-ID: <20230911064320.939791-30-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=alistair23@gmail.com; helo=mail-oi1-x22d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414938320100013 Content-Type: text/plain; charset="utf-8" From: Yong-Xuan Wang In this patch, we create the APLIC and IMSIC FDT helper functions and remove M mode AIA devices when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Message-ID: <20230727102439.22554-2-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 290 +++++++++++++++++++++++------------------------- 1 file changed, 137 insertions(+), 153 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a5ac3ab777..09a4030d4a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -516,79 +516,28 @@ static uint32_t imsic_num_bits(uint32_t count) return ret; } =20 -static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, - uint32_t *phandle, uint32_t *intc_phandles, - uint32_t *msi_m_phandle, uint32_t *msi_s_phan= dle) +static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, + uint32_t *intc_phandles, uint32_t msi_pha= ndle, + bool m_mode, uint32_t imsic_guest_bits) { int cpu, socket; char *imsic_name; MachineState *ms =3D MACHINE(s); int socket_count =3D riscv_socket_count(ms); - uint32_t imsic_max_hart_per_socket, imsic_guest_bits; + uint32_t imsic_max_hart_per_socket; uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; =20 - *msi_m_phandle =3D (*phandle)++; - *msi_s_phandle =3D (*phandle)++; imsic_cells =3D g_new0(uint32_t, ms->smp.cpus * 2); imsic_regs =3D g_new0(uint32_t, socket_count * 4); =20 - /* M-level IMSIC node */ for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { imsic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_EXT); + imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_= S_EXT); } - imsic_max_hart_per_socket =3D 0; - for (socket =3D 0; socket < socket_count; socket++) { - imsic_addr =3D memmap[VIRT_IMSIC_M].base + - socket * VIRT_IMSIC_GROUP_MAX_SIZE; - imsic_size =3D IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; - imsic_regs[socket * 4 + 0] =3D 0; - imsic_regs[socket * 4 + 1] =3D cpu_to_be32(imsic_addr); - imsic_regs[socket * 4 + 2] =3D 0; - imsic_regs[socket * 4 + 3] =3D cpu_to_be32(imsic_size); - if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { - imsic_max_hart_per_socket =3D s->soc[socket].num_harts; - } - } - imsic_name =3D g_strdup_printf("/soc/imsics@%lx", - (unsigned long)memmap[VIRT_IMSIC_M].base); - qemu_fdt_add_subnode(ms->fdt, imsic_name); - qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", - "riscv,imsics"); - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", - FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", - NULL, 0); - qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", - NULL, 0); - qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", - imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); - qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, - socket_count * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", - VIRT_IRQCHIP_NUM_MSIS); - if (socket_count > 1) { - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", - imsic_num_bits(imsic_max_hart_per_socket)); - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits= ", - imsic_num_bits(socket_count)); - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shif= t", - IMSIC_MMIO_GROUP_MIN_SHIFT); - } - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle); - - g_free(imsic_name); =20 - /* S-level IMSIC node */ - for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { - imsic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_S_EXT); - } - imsic_guest_bits =3D imsic_num_bits(s->aia_guests + 1); imsic_max_hart_per_socket =3D 0; for (socket =3D 0; socket < socket_count; socket++) { - imsic_addr =3D memmap[VIRT_IMSIC_S].base + - socket * VIRT_IMSIC_GROUP_MAX_SIZE; + imsic_addr =3D base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; imsic_size =3D IMSIC_HART_SIZE(imsic_guest_bits) * s->soc[socket].num_harts; imsic_regs[socket * 4 + 0] =3D 0; @@ -599,119 +548,151 @@ static void create_fdt_imsic(RISCVVirtState *s, con= st MemMapEntry *memmap, imsic_max_hart_per_socket =3D s->soc[socket].num_harts; } } - imsic_name =3D g_strdup_printf("/soc/imsics@%lx", - (unsigned long)memmap[VIRT_IMSIC_S].base); + + imsic_name =3D g_strdup_printf("/soc/imsics@%lx", (unsigned long)base_= addr); qemu_fdt_add_subnode(ms->fdt, imsic_name); - qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", - "riscv,imsics"); + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsi= cs"); qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", - FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", - NULL, 0); - qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", - NULL, 0); + FDT_IMSIC_INT_CELLS); + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", - imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, - socket_count * sizeof(uint32_t) * 4); + socket_count * sizeof(uint32_t) * 4); qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", - VIRT_IRQCHIP_NUM_MSIS); + VIRT_IRQCHIP_NUM_MSIS); + if (imsic_guest_bits) { qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits= ", - imsic_guest_bits); + imsic_guest_bits); } + if (socket_count > 1) { qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", - imsic_num_bits(imsic_max_hart_per_socket)); + imsic_num_bits(imsic_max_hart_per_socket)); qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits= ", - imsic_num_bits(socket_count)); + imsic_num_bits(socket_count)); qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shif= t", - IMSIC_MMIO_GROUP_MIN_SHIFT); + IMSIC_MMIO_GROUP_MIN_SHIFT); } - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle); - g_free(imsic_name); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); =20 + g_free(imsic_name); g_free(imsic_regs); g_free(imsic_cells); } =20 -static void create_fdt_socket_aplic(RISCVVirtState *s, - const MemMapEntry *memmap, int socket, - uint32_t msi_m_phandle, - uint32_t msi_s_phandle, - uint32_t *phandle, - uint32_t *intc_phandles, - uint32_t *aplic_phandles) +static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, + uint32_t *phandle, uint32_t *intc_phandles, + uint32_t *msi_m_phandle, uint32_t *msi_s_phan= dle) +{ + *msi_m_phandle =3D (*phandle)++; + *msi_s_phandle =3D (*phandle)++; + + if (!kvm_enabled()) { + /* M-level IMSIC node */ + create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles, + *msi_m_phandle, true, 0); + } + + /* S-level IMSIC node */ + create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles, + *msi_s_phandle, false, + imsic_num_bits(s->aia_guests + 1)); + +} + +static void create_fdt_one_aplic(RISCVVirtState *s, int socket, + unsigned long aplic_addr, uint32_t aplic_= size, + uint32_t msi_phandle, + uint32_t *intc_phandles, + uint32_t aplic_phandle, + uint32_t aplic_child_phandle, + bool m_mode) { int cpu; char *aplic_name; uint32_t *aplic_cells; - unsigned long aplic_addr; MachineState *ms =3D MACHINE(s); - uint32_t aplic_m_phandle, aplic_s_phandle; =20 - aplic_m_phandle =3D (*phandle)++; - aplic_s_phandle =3D (*phandle)++; aplic_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 2); =20 - /* M-level APLIC node */ for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { aplic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - aplic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_EXT); + aplic_cells[cpu * 2 + 1] =3D cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_= S_EXT); } - aplic_addr =3D memmap[VIRT_APLIC_M].base + - (memmap[VIRT_APLIC_M].size * socket); + aplic_name =3D g_strdup_printf("/soc/aplic@%lx", aplic_addr); qemu_fdt_add_subnode(ms->fdt, aplic_name); qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,apli= c"); qemu_fdt_setprop_cell(ms->fdt, aplic_name, - "#interrupt-cells", FDT_APLIC_INT_CELLS); + "#interrupt-cells", FDT_APLIC_INT_CELLS); qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); + if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC) { qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", - aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); + aplic_cells, + s->soc[socket].num_harts * sizeof(uint32_t) * 2); } else { - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", - msi_m_phandle); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phand= le); } + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", - 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); + 0x0, aplic_addr, 0x0, aplic_size); qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", - VIRT_IRQCHIP_NUM_SOURCES); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", - aplic_s_phandle); - qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", - aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); + VIRT_IRQCHIP_NUM_SOURCES); + + if (aplic_child_phandle) { + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", + aplic_child_phandle); + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", + aplic_child_phandle, 0x1, + VIRT_IRQCHIP_NUM_SOURCES); + } + riscv_socket_fdt_write_id(ms, aplic_name, socket); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); + g_free(aplic_name); + g_free(aplic_cells); +} =20 - /* S-level APLIC node */ - for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { - aplic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - aplic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_S_EXT); +static void create_fdt_socket_aplic(RISCVVirtState *s, + const MemMapEntry *memmap, int socket, + uint32_t msi_m_phandle, + uint32_t msi_s_phandle, + uint32_t *phandle, + uint32_t *intc_phandles, + uint32_t *aplic_phandles) +{ + char *aplic_name; + unsigned long aplic_addr; + MachineState *ms =3D MACHINE(s); + uint32_t aplic_m_phandle, aplic_s_phandle; + + aplic_m_phandle =3D (*phandle)++; + aplic_s_phandle =3D (*phandle)++; + + if (!kvm_enabled()) { + /* M-level APLIC node */ + aplic_addr =3D memmap[VIRT_APLIC_M].base + + (memmap[VIRT_APLIC_M].size * socket); + create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].s= ize, + msi_m_phandle, intc_phandles, + aplic_m_phandle, aplic_s_phandle, + true); } + + /* S-level APLIC node */ aplic_addr =3D memmap[VIRT_APLIC_S].base + (memmap[VIRT_APLIC_S].size * socket); + create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, + msi_s_phandle, intc_phandles, + aplic_s_phandle, 0, + false); + aplic_name =3D g_strdup_printf("/soc/aplic@%lx", aplic_addr); - qemu_fdt_add_subnode(ms->fdt, aplic_name); - qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,apli= c"); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, - "#interrupt-cells", FDT_APLIC_INT_CELLS); - qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); - if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC) { - qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", - aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); - } else { - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", - msi_s_phandle); - } - qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", - 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", - VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(ms, aplic_name, socket); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle); =20 if (!socket) { platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, @@ -722,7 +703,6 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, =20 g_free(aplic_name); =20 - g_free(aplic_cells); aplic_phandles[socket] =3D aplic_s_phandle; } =20 @@ -1163,16 +1143,20 @@ static DeviceState *virt_create_aia(RISCVVirtAIATyp= e aia_type, int aia_guests, int i; hwaddr addr; uint32_t guest_bits; - DeviceState *aplic_m; - bool msimode =3D (aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) ? true : = false; + DeviceState *aplic_s =3D NULL; + DeviceState *aplic_m =3D NULL; + bool msimode =3D aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC; =20 if (msimode) { - /* Per-socket M-level IMSICs */ - addr =3D memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX= _SIZE; - for (i =3D 0; i < hart_count; i++) { - riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), - base_hartid + i, true, 1, - VIRT_IRQCHIP_NUM_MSIS); + if (!kvm_enabled()) { + /* Per-socket M-level IMSICs */ + addr =3D memmap[VIRT_IMSIC_M].base + + socket * VIRT_IMSIC_GROUP_MAX_SIZE; + for (i =3D 0; i < hart_count; i++) { + riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), + base_hartid + i, true, 1, + VIRT_IRQCHIP_NUM_MSIS); + } } =20 /* Per-socket S-level IMSICs */ @@ -1185,29 +1169,29 @@ static DeviceState *virt_create_aia(RISCVVirtAIATyp= e aia_type, int aia_guests, } } =20 - /* Per-socket M-level APLIC */ - aplic_m =3D riscv_aplic_create( - memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, - memmap[VIRT_APLIC_M].size, - (msimode) ? 0 : base_hartid, - (msimode) ? 0 : hart_count, - VIRT_IRQCHIP_NUM_SOURCES, - VIRT_IRQCHIP_NUM_PRIO_BITS, - msimode, true, NULL); - - if (aplic_m) { - /* Per-socket S-level APLIC */ - riscv_aplic_create( - memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, - memmap[VIRT_APLIC_S].size, - (msimode) ? 0 : base_hartid, - (msimode) ? 0 : hart_count, - VIRT_IRQCHIP_NUM_SOURCES, - VIRT_IRQCHIP_NUM_PRIO_BITS, - msimode, false, aplic_m); + if (!kvm_enabled()) { + /* Per-socket M-level APLIC */ + aplic_m =3D riscv_aplic_create(memmap[VIRT_APLIC_M].base + + socket * memmap[VIRT_APLIC_M].size, + memmap[VIRT_APLIC_M].size, + (msimode) ? 0 : base_hartid, + (msimode) ? 0 : hart_count, + VIRT_IRQCHIP_NUM_SOURCES, + VIRT_IRQCHIP_NUM_PRIO_BITS, + msimode, true, NULL); } =20 - return aplic_m; + /* Per-socket S-level APLIC */ + aplic_s =3D riscv_aplic_create(memmap[VIRT_APLIC_S].base + + socket * memmap[VIRT_APLIC_S].size, + memmap[VIRT_APLIC_S].size, + (msimode) ? 0 : base_hartid, + (msimode) ? 0 : hart_count, + VIRT_IRQCHIP_NUM_SOURCES, + VIRT_IRQCHIP_NUM_PRIO_BITS, + msimode, false, aplic_m); + + return kvm_enabled() ? aplic_s : aplic_m; } =20 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414923; cv=none; d=zohomail.com; s=zohoarc; b=HsU/fr/GuqJC69NdWFkq8im/UtwQmSywjoRaHr/4PDFBE4y0hVrMA57fZT3QZqdGTHTD9AI476iSS1u0zM+12BoCKoAFczXHt99g3gQvW8i+4rl7GNw//rmP/SvFT751psYLyqpME9cd/iWUYPArXDoed3Yyc4ymBySES5aVy2I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414923; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vLQpbDK+vhuZxw59pu2RWadiyahlNw5xeOR7KVVdyRM=; b=IP1PkUp5KePkxRJXSJvtdzcsqeOgF1BNWZg1YPR9kASAeumUlnXgq1fZuF7+tHGmBaO3YJ/zH3xvh7hIxgVqGWr8Bde2G65Zumj4eQWZXZKA/kTTT2Oi19CRr2EUexAi/JzReKrpeWGdKVH7+tNqcpRnBxiUeZLak16Ay6ZPLW4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169441492365056.4444357065064; Sun, 10 Sep 2023 23:48:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagR-0003MJ-Gn; Mon, 11 Sep 2023 02:46:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfafy-0002tI-DB for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:45 -0400 Received: from mail-oi1-x233.google.com ([2607:f8b0:4864:20::233]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfafv-00056u-Q1 for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:38 -0400 Received: by mail-oi1-x233.google.com with SMTP id 5614622812f47-3ab244ef065so3152130b6e.0 for ; Sun, 10 Sep 2023 23:45:34 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. 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Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Message-ID: <20230727102439.22554-3-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/kvm.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index dbcf26f27d..2953547cb6 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -926,7 +926,15 @@ int kvm_arch_init(MachineState *ms, KVMState *s) =20 int kvm_arch_irqchip_create(KVMState *s) { - return 0; + if (kvm_kernel_irqchip_split()) { + error_report("-machine kernel_irqchip=3Dsplit is not supported on = RISC-V."); + exit(1); + } + + /* + * We can create the VAIA using the newer device control API. + */ + return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); } =20 int kvm_arch_process_async_events(CPUState *cs) --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414968; cv=none; d=zohomail.com; s=zohoarc; b=f9n6hBBrZhtbfAUfTgg589Vet3P3vTCJ7KnN7m7jFljXz6L6q/g2OigZFrBGFEZAbU6fb+EvZnf+04T7YxU8IxroqjrXRUKjMKGIlIcbZYKV82M+q2gUBXhNHiT9fNRb+M/z3Mr+wDPPevYWxUO/UPeF2H0Vz4O3yl3U3G9P3Wo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414968; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YFC/Wd1PZEGT1vXAEy/Fv/qkqYKA8VvtbmwE/sCiNlE=; b=G+JjhAqTCB6ii60k5PtXvSQ8aWV2kBUJ/J3CjhHfFa7kImfT6IwE7FEzEoGtAo0xDplPntWe/enZUdvVtdK7pSONUNIxU0tv05+ZqZa2TkLDxNHLt0z/e4MmJ4yH7HSyEKSM8r4hAEoKnRaz74QHznRtL7H/muepxc1gIR2eTM4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169441496857960.86946399240708; Sun, 10 Sep 2023 23:49:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfaga-00049i-9G; Mon, 11 Sep 2023 02:46:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfag2-0002wA-QV for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:45 -0400 Received: from mail-ua1-x935.google.com ([2607:f8b0:4864:20::935]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfafz-00057b-EY for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:42 -0400 Received: by mail-ua1-x935.google.com with SMTP id a1e0cc1a2514c-7a50a1d1246so1608197241.3 for ; Sun, 10 Sep 2023 23:45:39 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.45.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:45:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414738; x=1695019538; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YFC/Wd1PZEGT1vXAEy/Fv/qkqYKA8VvtbmwE/sCiNlE=; b=DkprJlF9KfQcrMaxP1rkWtATomlXeVOGfOPgWC0v6iCUKxsdjd8O8DJ62Ev39n+Boh uT5xNSmJ5Jlpbd6yPE0JkHYWnTI0FDocT3vd763EJDTLx0zTYW9yaLqdGs4bngOunZPj K1JeNBcEbrXd97MOE4U0oRtdbG4PqvaZs+AxmuBOsKdEvg1GkBvdzJj3jJibG481C/UQ UiEtIQ0wsNX0SPNGgwDK9OIW7zZmrQm7/eb73F3Fyl9jabpKTiKi4sD3YiQFrgQhICzt m+oHr1WkXvTWgcGY+87JL0k3VfwoYkSOfsdbB5IaA6ZS762ncoMgfH1+N6KN88dcFMbZ EXMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414738; x=1695019538; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YFC/Wd1PZEGT1vXAEy/Fv/qkqYKA8VvtbmwE/sCiNlE=; b=rwtpeVs67SzwX5RBaY3Zj4mS0oeqBg5/o/jOss9Kimoakrc7GjFVV89cosg/Fpkcek YqIyQD0EwJPwH6SZhe10yoyZPbbuxs/AfCrRp2oShO1qngxn5agNir1ySR+zVQlNDqld iEfCBVYlnyNC3ZzV5JdiFqM6KIx1jhs5VAL2lBGRQH6FQUEihTxepLnQHX3IScD3CDYI UBoLPNdavYBu0HiTZ2c9JtnYIb4BYfCqvIsJ7cEMPwC8xkw0tT+gbgVqU4m5g9JsllcT FX/Vzc59NVM3HEppuQ4GV32bUu5SueeYUwVaKKpsUTPgcVvPb6bqpWK5t2RgMHUljFZT YKBw== X-Gm-Message-State: AOJu0Yx04phBG61hepu0KZe8Wv0tIuT6CMXPYcoEAByuYm10U9ODBRdn 4EIzZVDKUp8fk40cx2BxZq4L8Hc/azoiFA== X-Google-Smtp-Source: AGHT+IF6uR6ArMaYh24HsCLyXnPDwTpubffUoEno9y5KU//5mjKQBRUvk/pYP77UHGWX3bpZsxCQ7w== X-Received: by 2002:a67:ec8a:0:b0:44e:a39d:a43f with SMTP id h10-20020a67ec8a000000b0044ea39da43fmr6891128vsp.28.1694414738155; Sun, 10 Sep 2023 23:45:38 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Yong-Xuan Wang , Jim Shu , Daniel Henrique Barboza , Andrew Jones , Alistair Francis Subject: [PULL v2 31/45] target/riscv: Create an KVM AIA irqchip Date: Mon, 11 Sep 2023 16:43:06 +1000 Message-ID: <20230911064320.939791-32-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::935; envelope-from=alistair23@gmail.com; helo=mail-ua1-x935.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414971007100001 Content-Type: text/plain; charset="utf-8" From: Yong-Xuan Wang We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs. We also extend KVM accelerator to specify the KVM AIA mode. The "riscv-aia" parameter is passed along with --accel in QEMU command-line. 1) "riscv-aia=3Demul": IMSIC is emulated by hypervisor 2) "riscv-aia=3Dhwaccel": use hardware guest IMSIC 3) "riscv-aia=3Dauto": use the hardware guest IMSICs whenever available otherwise we fallback to software emulation. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Message-ID: <20230727102439.22554-4-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/kvm_riscv.h | 4 + target/riscv/kvm.c | 186 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 190 insertions(+) diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index e3ba935808..7d4b7c60e2 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -22,5 +22,9 @@ void kvm_riscv_init_user_properties(Object *cpu_obj); void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); +void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, + uint64_t aia_irq_num, uint64_t aia_msi_num, + uint64_t aplic_base, uint64_t imsic_base, + uint64_t guest_num); =20 #endif diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 2953547cb6..6e909d0fdd 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -36,6 +36,7 @@ #include "exec/address-spaces.h" #include "hw/boards.h" #include "hw/irq.h" +#include "hw/intc/riscv_imsic.h" #include "qemu/log.h" #include "hw/loader.h" #include "kvm_riscv.h" @@ -43,6 +44,7 @@ #include "chardev/char-fe.h" #include "migration/migration.h" #include "sysemu/runstate.h" +#include "hw/riscv/numa.h" =20 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, uint64_t idx) @@ -1035,6 +1037,190 @@ bool kvm_arch_cpu_check_are_resettable(void) return true; } =20 +static int aia_mode; + +static const char *kvm_aia_mode_str(uint64_t mode) +{ + switch (mode) { + case KVM_DEV_RISCV_AIA_MODE_EMUL: + return "emul"; + case KVM_DEV_RISCV_AIA_MODE_HWACCEL: + return "hwaccel"; + case KVM_DEV_RISCV_AIA_MODE_AUTO: + default: + return "auto"; + }; +} + +static char *riscv_get_kvm_aia(Object *obj, Error **errp) +{ + return g_strdup(kvm_aia_mode_str(aia_mode)); +} + +static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) +{ + if (!strcmp(val, "emul")) { + aia_mode =3D KVM_DEV_RISCV_AIA_MODE_EMUL; + } else if (!strcmp(val, "hwaccel")) { + aia_mode =3D KVM_DEV_RISCV_AIA_MODE_HWACCEL; + } else if (!strcmp(val, "auto")) { + aia_mode =3D KVM_DEV_RISCV_AIA_MODE_AUTO; + } else { + error_setg(errp, "Invalid KVM AIA mode"); + error_append_hint(errp, "Valid values are emul, hwaccel, and auto.= \n"); + } +} + void kvm_arch_accel_class_init(ObjectClass *oc) { + object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, + riscv_set_kvm_aia); + object_class_property_set_description(oc, "riscv-aia", + "Set KVM AIA mode. Valid values = are " + "emul, hwaccel, and auto. Defaul= t " + "is auto."); + object_property_set_default_str(object_class_property_find(oc, "riscv-= aia"), + "auto"); +} + +void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, + uint64_t aia_irq_num, uint64_t aia_msi_num, + uint64_t aplic_base, uint64_t imsic_base, + uint64_t guest_num) +{ + int ret, i; + int aia_fd =3D -1; + uint64_t default_aia_mode; + uint64_t socket_count =3D riscv_socket_count(machine); + uint64_t max_hart_per_socket =3D 0; + uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; + uint64_t socket_bits, hart_bits, guest_bits; + + aia_fd =3D kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); + + if (aia_fd < 0) { + error_report("Unable to create in-kernel irqchip"); + exit(1); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_MODE, + &default_aia_mode, false, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to get current KVM AIA mode"); + exit(1); + } + qemu_log("KVM AIA: default mode is %s\n", + kvm_aia_mode_str(default_aia_mode)); + + if (default_aia_mode !=3D aia_mode) { + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_MODE, + &aia_mode, true, NULL); + if (ret < 0) + warn_report("KVM AIA: failed to set KVM AIA mode"); + else + qemu_log("KVM AIA: set current mode to %s\n", + kvm_aia_mode_str(aia_mode)); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_SRCS, + &aia_irq_num, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set number of input irq lines"); + exit(1); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_IDS, + &aia_msi_num, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set number of msi"); + exit(1); + } + + socket_bits =3D find_last_bit(&socket_count, BITS_PER_LONG) + 1; + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, + &socket_bits, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set group_bits"); + exit(1); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, + &group_shift, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set group_shift"); + exit(1); + } + + guest_bits =3D guest_num =3D=3D 0 ? 0 : + find_last_bit(&guest_num, BITS_PER_LONG) + 1; + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, + &guest_bits, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set guest_bits"); + exit(1); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, + KVM_DEV_RISCV_AIA_ADDR_APLIC, + &aplic_base, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set the base address of APLIC"); + exit(1); + } + + for (socket =3D 0; socket < socket_count; socket++) { + socket_imsic_base =3D imsic_base + socket * (1U << group_shift); + hart_count =3D riscv_socket_hart_count(machine, socket); + base_hart =3D riscv_socket_first_hartid(machine, socket); + + if (max_hart_per_socket < hart_count) { + max_hart_per_socket =3D hart_count; + } + + for (i =3D 0; i < hart_count; i++) { + imsic_addr =3D socket_imsic_base + i * IMSIC_HART_SIZE(guest_b= its); + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, + KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_= hart), + &imsic_addr, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set the IMSIC address for= hart %d", i); + exit(1); + } + } + } + + hart_bits =3D find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, + &hart_bits, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set hart_bits"); + exit(1); + } + + if (kvm_has_gsi_routing()) { + for (uint64_t idx =3D 0; idx < aia_irq_num + 1; ++idx) { + /* KVM AIA only has one APLIC instance */ + kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); + } + kvm_gsi_routing_allowed =3D true; + kvm_irqchip_commit_routes(kvm_state); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, + KVM_DEV_RISCV_AIA_CTRL_INIT, + NULL, true, NULL); + if (ret < 0) { + error_report("KVM AIA: initialized fail"); + exit(1); + } + + kvm_msi_via_irqfd_allowed =3D kvm_irqfds_enabled(); } --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414923; cv=none; d=zohomail.com; s=zohoarc; b=nB0jV9n7V4VOXGWejX5HXRyXKuHIBCLQ9uWpNtppPEZa4Eo3m9OBKDDvTCq2u1Z6cuSwCGYufZkYHg/dkhV+7xfTaxsZnulxxMDfRoHflNysWKewKWvQnM647LuwpDHU4jIMtnwLCO7Us3GiGEBI0RNGvj6xCNjEW+bAvguy4d0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414923; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LC1iRCb/qoM78YnEP3ofg9nP8nM+h7xg35CBjBCHbHg=; b=VlV4Wb+mngHe4o5GdQUtY+PrSY75/h0iKyr7RRnpA24ef8TAJSTgEOsURy2aKd2TlqE0RtroE/LW9EfE06vPLFLjpfnHDqROc9AUdYgws6c9iDSuL0+oWZzUdjyla1f5fp3XF5cJt/iKE6rh2KCULFdqt1RtLpAaH8RJI+kVGBg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414923565890.0497290899292; Sun, 10 Sep 2023 23:48:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagT-0003Uo-I4; Mon, 11 Sep 2023 02:46:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfag5-0002wl-WA for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:50 -0400 Received: from mail-oi1-x22a.google.com ([2607:f8b0:4864:20::22a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfag3-0005B3-I9 for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:45 -0400 Received: by mail-oi1-x22a.google.com with SMTP id 5614622812f47-3a751d2e6ecso3207471b6e.0 for ; Sun, 10 Sep 2023 23:45:43 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. 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When "aia=3Daplic" parameter is passed, APLIC devices is emulated by QEMU. For "aia=3Daplic-imsic", remove the mmio operations of APLIC when using KVM AIA and send wired interrupt signal via KVM_IRQ_LINE API. After KVM AIA enabled, MSI messages are delivered by KVM_SIGNAL_MSI API when the IMSICs receive mmio write requests. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Message-ID: <20230727102439.22554-5-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis --- hw/intc/riscv_aplic.c | 56 ++++++++++++++++++++++++++++++------------- hw/intc/riscv_imsic.c | 25 +++++++++++++++---- 2 files changed, 61 insertions(+), 20 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 4bdc6a5d1a..592c3ce768 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -31,6 +31,7 @@ #include "hw/irq.h" #include "target/riscv/cpu.h" #include "sysemu/sysemu.h" +#include "sysemu/kvm.h" #include "migration/vmstate.h" =20 #define APLIC_MAX_IDC (1UL << 14) @@ -148,6 +149,15 @@ =20 #define APLIC_IDC_CLAIMI 0x1c =20 +/* + * KVM AIA only supports APLIC MSI, fallback to QEMU emulation if we want = to use + * APLIC Wired. + */ +static bool is_kvm_aia(bool msimode) +{ + return kvm_irqchip_in_kernel() && msimode; +} + static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic, uint32_t word) { @@ -471,6 +481,11 @@ static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState= *aplic, uint32_t idc) return topi; } =20 +static void riscv_kvm_aplic_request(void *opaque, int irq, int level) +{ + kvm_set_irq(kvm_state, irq, !!level); +} + static void riscv_aplic_request(void *opaque, int irq, int level) { bool update =3D false; @@ -801,29 +816,35 @@ static void riscv_aplic_realize(DeviceState *dev, Err= or **errp) uint32_t i; RISCVAPLICState *aplic =3D RISCV_APLIC(dev); =20 - aplic->bitfield_words =3D (aplic->num_irqs + 31) >> 5; - aplic->sourcecfg =3D g_new0(uint32_t, aplic->num_irqs); - aplic->state =3D g_new0(uint32_t, aplic->num_irqs); - aplic->target =3D g_new0(uint32_t, aplic->num_irqs); - if (!aplic->msimode) { - for (i =3D 0; i < aplic->num_irqs; i++) { - aplic->target[i] =3D 1; + if (!is_kvm_aia(aplic->msimode)) { + aplic->bitfield_words =3D (aplic->num_irqs + 31) >> 5; + aplic->sourcecfg =3D g_new0(uint32_t, aplic->num_irqs); + aplic->state =3D g_new0(uint32_t, aplic->num_irqs); + aplic->target =3D g_new0(uint32_t, aplic->num_irqs); + if (!aplic->msimode) { + for (i =3D 0; i < aplic->num_irqs; i++) { + aplic->target[i] =3D 1; + } } - } - aplic->idelivery =3D g_new0(uint32_t, aplic->num_harts); - aplic->iforce =3D g_new0(uint32_t, aplic->num_harts); - aplic->ithreshold =3D g_new0(uint32_t, aplic->num_harts); + aplic->idelivery =3D g_new0(uint32_t, aplic->num_harts); + aplic->iforce =3D g_new0(uint32_t, aplic->num_harts); + aplic->ithreshold =3D g_new0(uint32_t, aplic->num_harts); =20 - memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, apl= ic, - TYPE_RISCV_APLIC, aplic->aperture_size); - sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio); + memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, + aplic, TYPE_RISCV_APLIC, aplic->aperture_siz= e); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio); + } =20 /* * Only root APLICs have hardware IRQ lines. All non-root APLICs * have IRQ lines delegated by their parent APLIC. */ if (!aplic->parent) { - qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs); + if (is_kvm_aia(aplic->msimode)) { + qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irq= s); + } else { + qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs); + } } =20 /* Create output IRQ lines for non-MSI mode */ @@ -958,7 +979,10 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr si= ze, qdev_prop_set_bit(dev, "mmode", mmode); =20 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + + if (!is_kvm_aia(msimode)) { + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + } =20 if (parent) { riscv_aplic_add_child(parent, dev); diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index fea3385b51..760dbddcf7 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -32,6 +32,7 @@ #include "target/riscv/cpu.h" #include "target/riscv/cpu_bits.h" #include "sysemu/sysemu.h" +#include "sysemu/kvm.h" #include "migration/vmstate.h" =20 #define IMSIC_MMIO_PAGE_LE 0x00 @@ -283,6 +284,20 @@ static void riscv_imsic_write(void *opaque, hwaddr add= r, uint64_t value, goto err; } =20 +#if defined(CONFIG_KVM) + if (kvm_irqchip_in_kernel()) { + struct kvm_msi msi; + + msi.address_lo =3D extract64(imsic->mmio.addr + addr, 0, 32); + msi.address_hi =3D extract64(imsic->mmio.addr + addr, 32, 32); + msi.data =3D le32_to_cpu(value); + + kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi); + + return; + } +#endif + /* Writes only supported for MSI little-endian registers */ page =3D addr >> IMSIC_MMIO_PAGE_SHIFT; if ((addr & (IMSIC_MMIO_PAGE_SZ - 1)) =3D=3D IMSIC_MMIO_PAGE_LE) { @@ -320,10 +335,12 @@ static void riscv_imsic_realize(DeviceState *dev, Err= or **errp) CPUState *cpu =3D cpu_by_arch_id(imsic->hartid); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; =20 - imsic->num_eistate =3D imsic->num_pages * imsic->num_irqs; - imsic->eidelivery =3D g_new0(uint32_t, imsic->num_pages); - imsic->eithreshold =3D g_new0(uint32_t, imsic->num_pages); - imsic->eistate =3D g_new0(uint32_t, imsic->num_eistate); + if (!kvm_irqchip_in_kernel()) { + imsic->num_eistate =3D imsic->num_pages * imsic->num_irqs; + imsic->eidelivery =3D g_new0(uint32_t, imsic->num_pages); + imsic->eithreshold =3D g_new0(uint32_t, imsic->num_pages); + imsic->eistate =3D g_new0(uint32_t, imsic->num_eistate); + } =20 memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops, imsic, TYPE_RISCV_IMSIC, --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414914; cv=none; d=zohomail.com; s=zohoarc; b=Ock+Yp9GzZF0dN3K6SzH/tjDstHYUW32b/1s1HTTvJKf85rFY0dfoVwkpNtn2S4w1toFQsALrCdygWBiYWJBzJ/ynCXdTdaxP6HI5YtlKNIxMsYJHqbVDEd1BEX9s1wdGHS2jzNWnW/0e8v+NZ6fjzDK/PNQg44UaTXAWsGKCp4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414914; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UheOu46bl1g9gK2JEJA5fUhYAbhdjzqfdhb7mPy6Zh4=; b=IotMpWPpCcoB3XvYjfx+2iMmDenV1YGLmPgNtskgU5Mh1ZdVtbkjeOVaCj198S1keH6BD2RkpzN6FLqLNLFNJ3UGnjBqKyvMkTypU7OsVx3isTx/X3ImzL6XrWuQ0QfU1NV571MNpqgxoxQU+NV9QzuytF2HhqLVf5yKvqgli1c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414914414105.58342003695736; Sun, 10 Sep 2023 23:48:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagT-0003U8-6d; Mon, 11 Sep 2023 02:46:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfagB-0002xa-9b for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:55 -0400 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfag8-0005BU-Tw for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:51 -0400 Received: by mail-oi1-x22f.google.com with SMTP id 5614622812f47-3a9b41ffe12so3267779b6e.3 for ; Sun, 10 Sep 2023 23:45:47 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.45.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:45:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414746; x=1695019546; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UheOu46bl1g9gK2JEJA5fUhYAbhdjzqfdhb7mPy6Zh4=; b=qKCkVPwEPL6pWGpnM5MD9ogsEv8vVFAwbFnMDdQDB51dQGRontlI+yWBHLJG7eoZj1 eliP+HJ/Tsv7aGby9TVpMDoY0V/fWUWkGuY/uN+CaFKyNqByFhwwYA+UhBicPFQNw6Mn CIDwldE3EG04uFo3KYsEjYSOuVu3pNEuX0WD7U7qq2KhleG/IjTzQG3lBC/KIalPmGXX 97cxBC521UqTX4Pth1zVlxEj7UgpvrkRTilInnHnNnAYQEECzrh4jXR5EqlTh9wX/XTO OBmiUdp5gk//YAd/yMtXdqrlx/5F0Q9tPGxQi/Xc78T+Jj16Tp55vkqCywkvtFls4oXo E/zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414746; x=1695019546; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UheOu46bl1g9gK2JEJA5fUhYAbhdjzqfdhb7mPy6Zh4=; b=WAkhnQVFX8TjnNPs8HOfAzF2HT0NNFX56eO3EYt1e03ioc4+CZ6BwYEo3JmAjrF+cB 0nSCZxbsgJ2xPu09c7BRwCtlgMgHkL8yAAusCDZom3lqjp9nLwkCNgBQpVcTYn6yJHu/ kDN73+GJ/j8q9okrBXPGDVlScEwET16IRxhiuKLGQ5zbWbzVLAPv9/xioqfT2yH5P66E buAfzSqaJINZ/CABDZMerLirz8tmaxlQlgRc2ojWsH/1KJfi+91ZnaeqfH/toeX9Nlte 5+2ORoJOZ/7u664xmOTguQV3VDh4jLBbCw9pogLbrZ7jlSmMZ2ruK3LpUJlh5fwt6BVn Kp0w== X-Gm-Message-State: AOJu0YytzGVIGyBFinCSwa97Kt24JXloEZBIF5o2QveOkeUjJUf0whYv s9U3kluAEbq9H85esCbPZlotQCNku9kcDg== X-Google-Smtp-Source: AGHT+IHFO8hAw1fiAeJkWOAYfrkTe4i1pCi/s6684rKneDYbDw6bxrAOQGUYtZfCU9H+oBnz7BiC5w== X-Received: by 2002:a05:6808:1410:b0:3a7:5453:a626 with SMTP id w16-20020a056808141000b003a75453a626mr12633648oiv.4.1694414746307; Sun, 10 Sep 2023 23:45:46 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Yong-Xuan Wang , Jim Shu , Daniel Henrique Barboza , Andrew Jones , Alistair Francis Subject: [PULL v2 33/45] target/riscv: select KVM AIA in riscv virt machine Date: Mon, 11 Sep 2023 16:43:08 +1000 Message-ID: <20230911064320.939791-34-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=alistair23@gmail.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414916360100003 Content-Type: text/plain; charset="utf-8" From: Yong-Xuan Wang Select KVM AIA when the host kernel has in-kernel AIA chip support. Since KVM AIA only has one APLIC instance, we map the QEMU APLIC devices to KVM APLIC. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Message-ID: <20230727102439.22554-6-yongxuan.wang@sifive.com> Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 94 +++++++++++++++++++++++++++++++++---------------- 1 file changed, 63 insertions(+), 31 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 09a4030d4a..0353a6de56 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -35,6 +35,7 @@ #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" +#include "kvm_riscv.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/riscv_aplic.h" #include "hw/intc/riscv_imsic.h" @@ -75,6 +76,12 @@ #error "Can't accommodate all IMSIC groups in address space" #endif =20 +/* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU= . */ +static bool virt_use_kvm_aia(RISCVVirtState *s) +{ + return kvm_irqchip_in_kernel() && s->aia_type =3D=3D VIRT_AIA_TYPE_APL= IC_IMSIC; +} + static const MemMapEntry virt_memmap[] =3D { [VIRT_DEBUG] =3D { 0x0, 0x100 }, [VIRT_MROM] =3D { 0x1000, 0xf000 }, @@ -609,16 +616,16 @@ static void create_fdt_one_aplic(RISCVVirtState *s, i= nt socket, uint32_t *intc_phandles, uint32_t aplic_phandle, uint32_t aplic_child_phandle, - bool m_mode) + bool m_mode, int num_harts) { int cpu; char *aplic_name; uint32_t *aplic_cells; MachineState *ms =3D MACHINE(s); =20 - aplic_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 2); + aplic_cells =3D g_new0(uint32_t, num_harts * 2); =20 - for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { + for (cpu =3D 0; cpu < num_harts; cpu++) { aplic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); aplic_cells[cpu * 2 + 1] =3D cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_= S_EXT); } @@ -632,8 +639,7 @@ static void create_fdt_one_aplic(RISCVVirtState *s, int= socket, =20 if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC) { qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", - aplic_cells, - s->soc[socket].num_harts * sizeof(uint32_t) * 2); + aplic_cells, num_harts * sizeof(uint32_t) * 2); } else { qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phand= le); } @@ -664,7 +670,8 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, uint32_t msi_s_phandle, uint32_t *phandle, uint32_t *intc_phandles, - uint32_t *aplic_phandles) + uint32_t *aplic_phandles, + int num_harts) { char *aplic_name; unsigned long aplic_addr; @@ -681,7 +688,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].s= ize, msi_m_phandle, intc_phandles, aplic_m_phandle, aplic_s_phandle, - true); + true, num_harts); } =20 /* S-level APLIC node */ @@ -690,7 +697,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, msi_s_phandle, intc_phandles, aplic_s_phandle, 0, - false); + false, num_harts); =20 aplic_name =3D g_strdup_printf("/soc/aplic@%lx", aplic_addr); =20 @@ -774,34 +781,51 @@ static void create_fdt_sockets(RISCVVirtState *s, con= st MemMapEntry *memmap, *msi_pcie_phandle =3D msi_s_phandle; } =20 - phandle_pos =3D ms->smp.cpus; - for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { - phandle_pos -=3D s->soc[socket].num_harts; - - if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { - create_fdt_socket_plic(s, memmap, socket, phandle, - &intc_phandles[phandle_pos], xplic_phandles); - } else { - create_fdt_socket_aplic(s, memmap, socket, - msi_m_phandle, msi_s_phandle, phandle, - &intc_phandles[phandle_pos], xplic_phandles); + /* KVM AIA only has one APLIC instance */ + if (virt_use_kvm_aia(s)) { + create_fdt_socket_aplic(s, memmap, 0, + msi_m_phandle, msi_s_phandle, phandle, + &intc_phandles[0], xplic_phandles, + ms->smp.cpus); + } else { + phandle_pos =3D ms->smp.cpus; + for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { + phandle_pos -=3D s->soc[socket].num_harts; + + if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { + create_fdt_socket_plic(s, memmap, socket, phandle, + &intc_phandles[phandle_pos], + xplic_phandles); + } else { + create_fdt_socket_aplic(s, memmap, socket, + msi_m_phandle, msi_s_phandle, phan= dle, + &intc_phandles[phandle_pos], + xplic_phandles, + s->soc[socket].num_harts); + } } } =20 g_free(intc_phandles); =20 - for (socket =3D 0; socket < socket_count; socket++) { - if (socket =3D=3D 0) { - *irq_mmio_phandle =3D xplic_phandles[socket]; - *irq_virtio_phandle =3D xplic_phandles[socket]; - *irq_pcie_phandle =3D xplic_phandles[socket]; - } - if (socket =3D=3D 1) { - *irq_virtio_phandle =3D xplic_phandles[socket]; - *irq_pcie_phandle =3D xplic_phandles[socket]; - } - if (socket =3D=3D 2) { - *irq_pcie_phandle =3D xplic_phandles[socket]; + if (virt_use_kvm_aia(s)) { + *irq_mmio_phandle =3D xplic_phandles[0]; + *irq_virtio_phandle =3D xplic_phandles[0]; + *irq_pcie_phandle =3D xplic_phandles[0]; + } else { + for (socket =3D 0; socket < socket_count; socket++) { + if (socket =3D=3D 0) { + *irq_mmio_phandle =3D xplic_phandles[socket]; + *irq_virtio_phandle =3D xplic_phandles[socket]; + *irq_pcie_phandle =3D xplic_phandles[socket]; + } + if (socket =3D=3D 1) { + *irq_virtio_phandle =3D xplic_phandles[socket]; + *irq_pcie_phandle =3D xplic_phandles[socket]; + } + if (socket =3D=3D 2) { + *irq_pcie_phandle =3D xplic_phandles[socket]; + } } } =20 @@ -1437,6 +1461,14 @@ static void virt_machine_init(MachineState *machine) } } =20 + if (virt_use_kvm_aia(s)) { + kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, + VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MS= IS, + memmap[VIRT_APLIC_S].base, + memmap[VIRT_IMSIC_S].base, + s->aia_guests); + } + if (riscv_is_32bit(&s->soc[0])) { #if HOST_LONG_BITS =3D=3D 64 /* limit RAM size in a 32-bit system */ --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.45.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:45:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414750; x=1695019550; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wXlsoQHwf3oyepQRy21sdbcrctFTEGdm2UM7pLp/J8Y=; b=VRAM5mDlOihJbWyET0W6P8EqPbHIM2ChocqQEcLXAUg0SBzBhnr3e2m5h12ojByEHk GKp53asxV/1z4i0Z99frX2eHII01hpyFyL6JO7oM9TbeE9sl0nbU8ONKoViajiRnWiaL tN6MAMndoXDw2fJr6is5pyfn6FufTTgzBbFAS5rnSmS/XB5mzz4VmpjDGEGRgcts4bNW 5jv1hphTm19KhxZND2ha0yK2UKtnT2mGFSYlkb4aaOqgUJmhqTFRT2pSbX3iKOQ2uqxo 4M97tAgc3dEjDAtrtuiLUP86gE2wvCvR8qnX5KCWaSgmjHNcbbriSIg1r3HNH+K3ncYA ss9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414750; x=1695019550; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wXlsoQHwf3oyepQRy21sdbcrctFTEGdm2UM7pLp/J8Y=; b=fAAB1oPiM3d5ti8XK7dkwwn17J2T835hYL/Q+ObbW81NbKYiSmwMkQWjLl+evXRbck qR6/Quiez0dfhPXSuq4qP3NBhs2MiaXisEYKDgGieU5sHOUaBcn1b1uV79vRX3eV9fej +V+I4kDCHIIyNlDtnErdIQiULZc2A0pg+uciEMxhKmzKIyORdDREAdwv5QU4DkhlpL4m HF0yqx8Old5ClaHSlBvIuQvW25oe49HkMArgMQv5L2PAWwVqrNzC+/qte7Is/zO+fE9i u/jZjs9D9MiB3556KfOIqBlwvkE5uDlgfh4I8EzhDP3zHUtDnhbJxK8vqXLJMDGQ4mka nUQQ== X-Gm-Message-State: AOJu0YzwgqplatWkdgHEAcEaCN0LkCZa9O6l2RXT4ZMu+VOGmeQ8ePsy JAsH0iUp8wlxBCrsv3tm2IYF28RfOIuP9Q== X-Google-Smtp-Source: AGHT+IHV7EFViD6xaH5FmIqCRoqL1F/d7corJBm9ZviH+PZIY2g5hUh77CLOn4cbeYiV5A6wNzcVeA== X-Received: by 2002:a05:6358:c17:b0:139:4783:5140 with SMTP id f23-20020a0563580c1700b0013947835140mr9879026rwj.16.1694414749764; Sun, 10 Sep 2023 23:45:49 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Conor Dooley , Alistair Francis , Daniel Henrique Barboza Subject: [PULL v2 34/45] hw/riscv: virt: Fix riscv,pmu DT node path Date: Mon, 11 Sep 2023 16:43:09 +1000 Message-ID: <20230911064320.939791-35-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=alistair23@gmail.com; helo=mail-ot1-x332.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414960696100005 Content-Type: text/plain; charset="utf-8" From: Conor Dooley On a dtb dumped from the virt machine, dt-validate complains: soc: pmu: {'riscv,event-to-mhpmcounters': [[1, 1, 524281], [2, 2, 524284], = [65561, 65561, 524280], [65563, 65563, 524280], [65569, 65569, 524280]], 'c= ompatible': ['riscv,pmu']} should not be valid under {'type': 'object'} from schema $id: http://devicetree.org/schemas/simple-bus.yaml# That's pretty cryptic, but running the dtb back through dtc produces something a lot more reasonable: Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property Moving the riscv,pmu node out of the soc bus solves the problem. Signed-off-by: Conor Dooley Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Message-ID: <20230727-groom-decline-2c57ce42841c@spud> Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 0353a6de56..496c17c644 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -719,7 +719,7 @@ static void create_fdt_pmu(RISCVVirtState *s) MachineState *ms =3D MACHINE(s); RISCVCPU hart =3D s->soc[0].harts[0]; =20 - pmu_name =3D g_strdup_printf("/soc/pmu"); + pmu_name =3D g_strdup_printf("/pmu"); qemu_fdt_add_subnode(ms->fdt, pmu_name); qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name); --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414817; cv=none; d=zohomail.com; s=zohoarc; b=mnQT51BMSBpXwJHNAQMsorVa1CGtyhIzYSf2jpn6we+6Egx30KGKk7itKxK+96UOvB8btRR7uvhUdGmNXTUNaeQAsiOQGmm/rACfaNzS+r1o6UQC3dqGLqPUNXCFuAV5CsHZ/CZhbiont/2ZgKdzbG/GPsZqM8rhZu+mhOqu6jI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414817; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VAOZAeFSdxVr60MLt73fKHVsOxnw3vFeX18pOb0w86I=; b=N0ggXc6/yhN8vaYTm9IkoaSCkvKf5N8tfqJuud8qSCiF8T0BEI4Z/odIEoTBdktUa8d2K+fftRU7ihPUUVpG3lIS0mRhLhH8xdek3XgfYxyPDd2CjHgRTooBqP7cJ/RpqPZDn00WZaCqga5SyYDfzMRNpzdF1fY1c1cq8oBgVxg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414817759221.7133580812431; Sun, 10 Sep 2023 23:46:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagb-0004FW-R9; Mon, 11 Sep 2023 02:46:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfagI-00030W-6Q for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:59 -0400 Received: from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfagE-0005EZ-V7 for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:45:57 -0400 Received: by mail-oi1-x230.google.com with SMTP id 5614622812f47-3aa1443858eso3190901b6e.3 for ; Sun, 10 Sep 2023 23:45:54 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.45.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:45:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414753; x=1695019553; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VAOZAeFSdxVr60MLt73fKHVsOxnw3vFeX18pOb0w86I=; b=mATEwFpcp1VpSenP1xRb9Iy7TZf1KZLtv8NY2TwadFldFeZQQWy82F9k6LL1kmH0Gh pix6jc9PePLYqI1j9RAWuU4yRRhGAvnV3AFdFPqReUX9WAxqUnOxZi6QjWLzQcVcoDzH tbRch1mQyas9JT0E4XMHcB2Xi7Rhkd4V1iP7dafaEZxx6EzWgpGWwG9y87Q2zK1CUe0M GOtobu8BACA7a8DV8C6lDix4lBi8zUnU0oP9WHxcJwGJOGpWZx0j45EdJiojA0fupkxu 5DchroDJibINOy6B9CNk8uGNUAyWmDjRi+0ydhEkeIHF5fDjriv3+lQz4sX2ok3g/XM3 82Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414753; x=1695019553; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VAOZAeFSdxVr60MLt73fKHVsOxnw3vFeX18pOb0w86I=; b=KEE6icHmNWbIcHM5thyurTcLle1L+Yp9v7nGuALXNqi3gcb6dYaIYy6Wc9M6W6mWVh ADTWlPpjin3ZmYal6G7MOvzsVWJDDtXn+HEuQkVtcbmy8CDceAEloX0bsPZZ7pYL9NDt Oq2CMYPgTZacOjq/rj7c6fr5O23UHRdfJjE5FvvnrXp8B0+r6/99fjucyf36H1vvVqVU 3lELVDfqoxcG7ADkiXEL8zOI+00gvGf0kXhUAya4ie+0onFhZEzqHERo6PEY0z9Ic7ld AqnAbQv0oN01iAoBJ4n9tfszmY8CFE3aMKEza2MvRYU7wmW7dHpetKjBYVa9xef/HNXd bo3Q== X-Gm-Message-State: AOJu0YzSongtZALZhDrfse87FolLuad5PVDEzpm5TcnsVbnUjAOboiDa 1MLMe5hSrxuwdTWtBj9ZyCo1ylqphMEzLw== X-Google-Smtp-Source: AGHT+IGMOLzk6K/zLSLFAcTFgpyZWD2Oe2hv+v9dcqELrqMGclttOnOj5EwHzTXSiF0/RUqFyeJ3gQ== X-Received: by 2002:a05:6808:f07:b0:3a9:7634:23f9 with SMTP id m7-20020a0568080f0700b003a9763423f9mr11853008oiw.12.1694414753638; Sun, 10 Sep 2023 23:45:53 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Daniel Henrique Barboza , Alistair Francis Subject: [PULL v2 35/45] target/riscv: Update CSR bits name for svadu extension Date: Mon, 11 Sep 2023 16:43:10 +1000 Message-ID: <20230911064320.939791-36-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=alistair23@gmail.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414818989100003 Content-Type: text/plain; charset="utf-8" From: Weiwei Li The Svadu specification updated the name of the *envcfg bit from HADE to ADUE. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Daniel Henrique Barboza Message-ID: <20230816141916.66898-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 8 ++++---- target/riscv/cpu.c | 4 ++-- target/riscv/cpu_helper.c | 6 +++--- target/riscv/csr.c | 12 ++++++------ 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 31a8d80990..3d6ffaabc7 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -745,12 +745,12 @@ typedef enum RISCVException { #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) -#define MENVCFG_HADE (1ULL << 61) +#define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) =20 /* For RV32 */ -#define MENVCFGH_HADE BIT(29) +#define MENVCFGH_ADUE BIT(29) #define MENVCFGH_PBMTE BIT(30) #define MENVCFGH_STCE BIT(31) =20 @@ -763,12 +763,12 @@ typedef enum RISCVException { #define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBZE MENVCFG_CBZE -#define HENVCFG_HADE MENVCFG_HADE +#define HENVCFG_ADUE MENVCFG_ADUE #define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_STCE MENVCFG_STCE =20 /* For RV32 */ -#define HENVCFGH_HADE MENVCFGH_HADE +#define HENVCFGH_ADUE MENVCFGH_ADUE #define HENVCFGH_PBMTE MENVCFGH_PBMTE #define HENVCFGH_STCE MENVCFGH_STCE =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fae1c92c5c..8071f05f15 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -886,9 +886,9 @@ static void riscv_cpu_reset_hold(Object *obj) env->two_stage_lookup =3D false; =20 env->menvcfg =3D (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | - (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); + (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0); env->henvcfg =3D (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | - (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); + (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0); =20 /* Initialized default priorities of local interrupts. */ for (i =3D 0; i < ARRAY_SIZE(env->miprio); i++) { diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9f611d89bb..3a02079290 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -861,11 +861,11 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, } =20 bool pbmte =3D env->menvcfg & MENVCFG_PBMTE; - bool hade =3D env->menvcfg & MENVCFG_HADE; + bool adue =3D env->menvcfg & MENVCFG_ADUE; =20 if (first_stage && two_stage && env->virt_enabled) { pbmte =3D pbmte && (env->henvcfg & HENVCFG_PBMTE); - hade =3D hade && (env->henvcfg & HENVCFG_HADE); + adue =3D adue && (env->henvcfg & HENVCFG_ADUE); } =20 int ptshift =3D (levels - 1) * ptidxbits; @@ -1026,7 +1026,7 @@ restart: =20 /* Page table updates need to be atomic with MTTCG enabled */ if (updated_pte !=3D pte && !is_debug) { - if (!hade) { + if (!adue) { return TRANSLATE_FAIL; } =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 661744e6d4..63c3b0d9fc 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1957,7 +1957,7 @@ static RISCVException write_menvcfg(CPURISCVState *en= v, int csrno, if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { mask |=3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_svadu ? MENVCFG_HADE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0); } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); =20 @@ -1977,7 +1977,7 @@ static RISCVException write_menvcfgh(CPURISCVState *e= nv, int csrno, const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); uint64_t mask =3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_svadu ? MENVCFG_HADE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0); uint64_t valh =3D (uint64_t)val << 32; =20 env->menvcfg =3D (env->menvcfg & ~mask) | (valh & mask); @@ -2029,7 +2029,7 @@ static RISCVException read_henvcfg(CPURISCVState *env= , int csrno, * henvcfg.stce is read_only 0 when menvcfg.stce =3D 0 * henvcfg.hade is read_only 0 when menvcfg.hade =3D 0 */ - *val =3D env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HADE= ) | + *val =3D env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE= ) | env->menvcfg); return RISCV_EXCP_NONE; } @@ -2046,7 +2046,7 @@ static RISCVException write_henvcfg(CPURISCVState *en= v, int csrno, } =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { - mask |=3D env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_H= ADE); + mask |=3D env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_A= DUE); } =20 env->henvcfg =3D (env->henvcfg & ~mask) | (val & mask); @@ -2064,7 +2064,7 @@ static RISCVException read_henvcfgh(CPURISCVState *en= v, int csrno, return ret; } =20 - *val =3D (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_HAD= E) | + *val =3D (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADU= E) | env->menvcfg)) >> 32; return RISCV_EXCP_NONE; } @@ -2073,7 +2073,7 @@ static RISCVException write_henvcfgh(CPURISCVState *e= nv, int csrno, target_ulong val) { uint64_t mask =3D env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | - HENVCFG_HADE); + HENVCFG_ADUE); uint64_t valh =3D (uint64_t)val << 32; RISCVException ret; =20 --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414923; cv=none; d=zohomail.com; s=zohoarc; b=WVni4o/YoDTZ6evoCginrRphl9jP9jZXUoGMxzkDAKDdPRfIy83ibRa3qXyr+pdNMRq6mjpkhT++51F0e6fXTpFa/fyJOW0R7RG8O/31WAZxpYaX2HUjNoGsq96FL8/UqFIIfGTDpjYlKyMha9RtOS/pYEYHkMlum0+rSEUecZU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414923; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YOggPHEkVLsqxPB2c0/QeriqcmfD3a3w+0iFBDdTsWI=; b=eDsLzXMeFeyfgobwPvfvNyd+80JvxojzmZupxKR2prDyPer4KEVR+yjPPgMJgC7G7HZ3FAleIlP4iekXhheKxM1JLQHJkVAnZlCMnC+oTlM1V4oO7pSL7EWsh0S6YhDI+SV1xOPHxZXXL0Ef7laO1yVTdpy6CBJIwykt0u3R5eE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414923618513.1757497849873; Sun, 10 Sep 2023 23:48:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagU-0003at-UV; Mon, 11 Sep 2023 02:46:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfagL-00036o-M8 for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:46:03 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfagJ-0005Ev-3L for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:46:01 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-68fb2e9ebbfso775086b3a.2 for ; Sun, 10 Sep 2023 23:45:58 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.45.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:45:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414757; x=1695019557; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YOggPHEkVLsqxPB2c0/QeriqcmfD3a3w+0iFBDdTsWI=; b=V4rAojmvoHgzbI6M8xYWQnYfG/TT6vBBR5FM2NBqJu86DahJYE8f02DQ9Mnih5nOcb ju64B0xXH8SAkUSIEYAukxq9dBOZUWUNpqCb1a3KQVuZNo3JKgoINkqmLgP2mqYA19Ij lkANUwCUuENVrFdaaHzhD5IyUgycfczh7VxwVoXnssz3+tLSpiev73VZNec9KjXN/seV KGJKYSn4a0m0M7CNhcUGWfIB6MONtacHzwkvjQ34a+VMGYi96e9U+afltR3mGti04arW 8xnG2cINlvl9efQf/awI0qORUqm7g05NWqjxTKMk4O6AQroSfsVdoTex4tYm3e883K0+ pFkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414757; x=1695019557; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YOggPHEkVLsqxPB2c0/QeriqcmfD3a3w+0iFBDdTsWI=; b=Puii3GBSL5uWEIY8AJUiBKdCUBA3jlcuDADxBdErpZAYzFZN3iXskTLmrXsgGKyY6F hLnLY9qvSOI+d1SKrUhmpA/K0bUlwzbNmNmRC0bsaLzlm42qr03KK4/FEycsqCm6LTYW UCjmq3H1kx4YLQ6E6vXSmdLJLAg2FMP8SMDmiCLpRNQgguviY2pPhXspIhDnrEhKK/hO Il3MV1YQ1Xzf2BvgO97xTK2cq1PjRx3NUmI4m9ah3t5or7fNQAuCZoMIeBvPKVWnKxYx 4qgNOtTNU0HciOPZwmCIvv/RAKVcT3YSGpFv99woAHGmUtL/sCxED98Re3+51KZ9+h/x Yh3Q== X-Gm-Message-State: AOJu0YwmdabrjlZNYmMaBT4ygd/78Rcr1FbCM07fh8+ffB4rsJyQqyqy uYyJ9mk0oXSp+rgHcz74lUzmjvW6v+ZbxA== X-Google-Smtp-Source: AGHT+IE0+2bhCosMVjGFRzxlMlsl+I9IY2KlF7Cuahweq3vner/LBti94nk95xv6BPOjdZCtyPr6ng== X-Received: by 2002:a05:6a00:330a:b0:68f:caaa:e6d5 with SMTP id cq10-20020a056a00330a00b0068fcaaae6d5mr1114528pfb.14.1694414757270; Sun, 10 Sep 2023 23:45:57 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Alexandre Ghiti , Andrew Jones , Alistair Francis Subject: [PULL v2 36/45] target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0 Date: Mon, 11 Sep 2023 16:43:11 +1000 Message-ID: <20230911064320.939791-37-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=alistair23@gmail.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414923915100006 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza In the same emulated RISC-V host, the 'host' KVM CPU takes 4 times longer to boot than the 'rv64' KVM CPU. The reason is an unintended behavior of riscv_cpu_satp_mode_finalize() when satp_mode.supported =3D 0, i.e. when cpu_init() does not set satp_mode_max_supported(). satp_mode_max_from_map(map) does: 31 - __builtin_clz(map) This means that, if satp_mode.supported =3D 0, satp_mode_supported_max wil be '31 - 32'. But this is C, so satp_mode_supported_max will gladly set it to UINT_MAX (4294967295). After that, if the user didn't set a satp_mode, set_satp_mode_default_map(cpu) will make cfg.satp_mode.map =3D cfg.satp_mode.supported So satp_mode.map =3D 0. And then satp_mode_map_max will be set to satp_mode_max_from_map(cpu->cfg.satp_mode.map), i.e. also UINT_MAX. The guard "satp_mode_map_max > satp_mode_supported_max" doesn't protect us here since both are UINT_MAX. And finally we have 2 loops: for (int i =3D satp_mode_map_max - 1; i >=3D 0; --i) { Which are, in fact, 2 loops from UINT_MAX -1 to -1. This is where the extra delay when booting the 'host' CPU is coming from. Commit 43d1de32f8 already set a precedence for satp_mode.supported =3D 0 in a different manner. We're doing the same here. If supported =3D=3D 0, interpret as 'the CPU wants the OS to handle satp mode alone' and skip satp_mode_finalize(). We'll also put a guard in satp_mode_max_from_map() to assert out if map is 0 since the function is not ready to deal with it. Cc: Alexandre Ghiti Fixes: 6f23aaeb9b ("riscv: Allow user to set the satp mode") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Message-ID: <20230817152903.694926-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8071f05f15..34ac26e3ae 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -309,6 +309,17 @@ static uint8_t satp_mode_from_str(const char *satp_mod= e_str) =20 uint8_t satp_mode_max_from_map(uint32_t map) { + /* + * 'map =3D 0' will make us return (31 - 32), which C will + * happily overflow to UINT_MAX. There's no good result to + * return if 'map =3D 0' (e.g. returning 0 will be ambiguous + * with the result for 'map =3D 1'). + * + * Assert out if map =3D 0. Callers will have to deal with + * it outside of this function. + */ + g_assert(map > 0); + /* map here has at least one bit set, so no problem with clz */ return 31 - __builtin_clz(map); } @@ -1333,9 +1344,15 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu= , Error **errp) static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) { bool rv32 =3D riscv_cpu_mxl(&cpu->env) =3D=3D MXL_RV32; - uint8_t satp_mode_map_max; - uint8_t satp_mode_supported_max =3D - satp_mode_max_from_map(cpu->cfg.satp_mode.supporte= d); + uint8_t satp_mode_map_max, satp_mode_supported_max; + + /* The CPU wants the OS to decide which satp mode to use */ + if (cpu->cfg.satp_mode.supported =3D=3D 0) { + return; + } + + satp_mode_supported_max =3D + satp_mode_max_from_map(cpu->cfg.satp_mode.supported); =20 if (cpu->cfg.satp_mode.map =3D=3D 0) { if (cpu->cfg.satp_mode.init =3D=3D 0) { --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414894; cv=none; d=zohomail.com; s=zohoarc; b=cWrgigZSkx4sgWj9nidwV39dLD6xq6H1UCgRU6znhXfgtvRqrGE21irP81/HizKzqxePeKEf6zB0+4vqIFCBghs7siLal2+D0sCxX+ls2NiaFEBeAiGocOVMrtGMtRkkgND69GPrjPexhKuVlJa1WzkisVvrWfeTIxydTn3vch4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414894; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SNW/cl5XE7PcFPCSWK9aTBzwWg07OvJep7oqCwyWKIs=; b=GCTJAc2LtgW7z1TyGFC/4nN+aBnHuicLm2OKGWC6+mE+WWxnXnU9jerNEC57Tzam558P6v6BDGV8B+ERBfc5XnFf4S/Q3AAzxlKpjDMiGoYti2kw4adIJ/B/HTE9KsMENlsTT0CiNk4hH89LAoOp5rVVd650imgMi8t2WUymJ5M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169441489440149.60541306349319; Sun, 10 Sep 2023 23:48:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagT-0003Uk-Ij; Mon, 11 Sep 2023 02:46:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfagO-0003BD-CV for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:46:04 -0400 Received: from mail-oi1-x22a.google.com ([2607:f8b0:4864:20::22a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfagM-0005F5-6I for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:46:04 -0400 Received: by mail-oi1-x22a.google.com with SMTP id 5614622812f47-3ab2436b57dso2929661b6e.0 for ; Sun, 10 Sep 2023 23:46:01 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.45.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:45:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414760; x=1695019560; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SNW/cl5XE7PcFPCSWK9aTBzwWg07OvJep7oqCwyWKIs=; b=pQpQ09o1B6xR0TipSIQ/q0i1Es5BQFlbQhFHJ4k80Fceqds1AX/yunaJx6hCYD7ENP XnAkqnzEYvg8tUy0UG0pjGCw3Z52zGKvSj85wfnAqWXufzd6KUviYqdf2pGJ6oOUY49m JDnOpzf5dzdnOCIHuZ3plFb56KzNSivyBOOj9X70L4rizSluSTPFR+AdxaYMQflhp7Yz cwSoqBQXSCYbNMsttZeXVfgGRU8OA3VGBenwCgMwZQfjyHOW9nzdfeNFuECBkUGwbafz 6lt6+TI4eiidwnpLqPp/nt/jOUW+IlWYrlY4pualc2hcRosZPbm+KyKXI5ZAovdyi22n NDdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414760; x=1695019560; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SNW/cl5XE7PcFPCSWK9aTBzwWg07OvJep7oqCwyWKIs=; b=Hkp/nLro65HbA0QZKdaXYxrdCtOq7fEsCibakTLG2R76sALzbOUQrKJ2OvZ0EcBP0g HLDiOQkdSfIruUSjTWffrchdTpqIemAtznY/nCdXdl2WPZdfwDwKbOpKJfjNKAfUAXBx 5xPQPcxN3xEYePLYf5x9l2btQ0s7sHvQni+nbe5izW/2rzq/QpL+bgggje2/DnUhaCQS o8bh6Tk1tCw3MGpwN+5aqMxodVsiMlvT8EnQ/N7JSd5otRkszDLcx9kJv4g3wotlwkdj PPqbpSUoh7Ybw29cVBrrBmWVHItCuMFnv3/0aZncfxlGJJ8qlhh4oRC5nv/R01jvBJR1 WHHA== X-Gm-Message-State: AOJu0YwfD94OJi8tuM/ZXwHgR+Ni9O6agcuPSTZRRCiVuEL6RT5LMZAe V1DLPFkbcqCoArVVslw+QaUsIXDNUnZREA== X-Google-Smtp-Source: AGHT+IGLB22OHuyr4LgXH4DyuKEsaMn6EBFBVH9aCh7i6TiOu+spJusgMPp3amwIzAuMI6OWH7w5CQ== X-Received: by 2002:a54:439a:0:b0:3a8:1727:5af4 with SMTP id u26-20020a54439a000000b003a817275af4mr9927515oiv.24.1694414760487; Sun, 10 Sep 2023 23:46:00 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Vineet Gupta , Alistair Francis Subject: [PULL v2 37/45] riscv: zicond: make non-experimental Date: Mon, 11 Sep 2023 16:43:12 +1000 Message-ID: <20230911064320.939791-38-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=alistair23@gmail.com; helo=mail-oi1-x22a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414895296100001 Content-Type: text/plain; charset="utf-8" From: Vineet Gupta zicond is now codegen supported in both llvm and gcc. This change allows seamless enabling/testing of zicond in downstream projects. e.g. currently riscv-gnu-toolchain parses elf attributes to create a cmdline for qemu but fails short of enabling it because of the "x-" prefix. Signed-off-by: Vineet Gupta Message-ID: <20230808181715.436395-1-vineetg@rivosinc.com> Reviewed-by: Alistair Francis Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 34ac26e3ae..bf0912014e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1869,6 +1869,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false), DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), + DEFINE_PROP_BOOL("zicond", RISCVCPU, cfg.ext_zicond, false), =20 /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), @@ -1885,7 +1886,6 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), =20 /* These are experimental so mark with 'x-' */ - DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), =20 /* ePMP 0.9.3 */ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414949; cv=none; d=zohomail.com; s=zohoarc; b=PCHf4E/KgJtBD3EPyCQG4bibofCZ9dNNzaQBqiav2NYj5FPuoqbGvdXd8BnwuoG+wSKrfDvHUSM+schNOieUbHtU0vIArxaa1Ucbkjzel4sEKiG6Pg+tG10tYWziQsL19Ka/uryHy2I0JzEm1pwU9PGjKG56tWjNfzfVedth+Hg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414949; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/hFN2dlBubMVtn023qgNLHsDI3Hg9nR/nsnfeLKyUdo=; b=G+3fWb1DB78NJNJO3zVuGNh5eYTVgppD0NTMSfwLd3HIbN4teUr9mtGcp+PJtiImsiA8QBNFim0jbfzAGJGtVsdW1eCMI1L1x4P1W/bAe/b+VR6Z+bhhq1m0h0hdn9Ox8Sv5yyuMo2WZT3Zdu6ANcLgpBdzomOMnxScPEw6uUr8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414949687991.1966577677678; Sun, 10 Sep 2023 23:49:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfage-0004pt-SJ; Mon, 11 Sep 2023 02:46:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfagV-0003dJ-Qi for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:46:11 -0400 Received: from mail-oi1-x236.google.com ([2607:f8b0:4864:20::236]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfagQ-0005FQ-4D for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:46:11 -0400 Received: by mail-oi1-x236.google.com with SMTP id 5614622812f47-3a81154c5f5so2814799b6e.1 for ; Sun, 10 Sep 2023 23:46:05 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.46.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:46:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414764; x=1695019564; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/hFN2dlBubMVtn023qgNLHsDI3Hg9nR/nsnfeLKyUdo=; b=o5UH3k+n0hceMx66DmoWSNxY9NW2fFEXyiR/WImwk1ruV0pZCaZ5hL154PNq+aaZg3 wlW5yU8m7sVN7McU8eiSXdIcTTmQNAEoHl23hGgarUk0blJrbz4sz8hThfFrmUz5iWaE z8SG3aC3oe87wzOpCuh1V65GdctnCrz1h1kHR4qp10jQ2LWu9LJHW87K/uALqbuscyGC ZNHDyFsOi/xOgcosZPitwY9I0utdEgOQmRxih+xqon7z/ROb565vs0I6D7u/uZtW9DQk UFC+m6kjI56ibJBquI7FgS6jzt+U+7hrZy6HxdAfp3qsKQ6EyEOYiaVuuiOyvo0+X5GA zCsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414764; x=1695019564; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/hFN2dlBubMVtn023qgNLHsDI3Hg9nR/nsnfeLKyUdo=; b=UkHSnBh5vitvPkOPLcazbSndkix18uPFdUoKn3J966V6na6s2d/qbRceXC4ngiALca Ax0Lik8tl0zfdU803fLI6jdcZFVKgAP9ERK9yifKUVUeITlKMk+aF3tnkWw04+XVQlFQ KsE+EaUYQHFbfyuXoe6YfEkgFY72CyFY7ci33tPwq+H6rr6pgOAWi5t9B/P5xi/zyl1H wz5aE0ZmWMWgW3d5gpYbHiwaJJ52Xc1BPIAxTtMG5QNQVWAvoiwbvTa24MpSSaAODkib oxwRhplExwq7C2aesd7KKiZ8t4j2h2N1GYyq2pk4u5T2Q7Ql3Hp2+YQdrRIprMhqJ3Tq ydRA== X-Gm-Message-State: AOJu0YwWRVmuG+9LDUSzWIfg2j6/WPnN37wp5bTSpZA6eiHBwVM5JgQ+ plrV3MEG8N7oplzj/oEpRDuD2Nsr4kXGOA== X-Google-Smtp-Source: AGHT+IG0fqLI1us5uOmZNfG6WCoTpp+T1J0tFukk9Ww8vXS4weRh8woFiOH7eFPQH7oq19cigChUBQ== X-Received: by 2002:a05:6808:171c:b0:3a7:4cf6:f0cb with SMTP id bc28-20020a056808171c00b003a74cf6f0cbmr10211108oib.21.1694414764508; Sun, 10 Sep 2023 23:46:04 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Richard Henderson , Andrew Jones , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis Subject: [PULL v2 38/45] hw/riscv/virt.c: fix non-KVM --enable-debug build Date: Mon, 11 Sep 2023 16:43:13 +1000 Message-ID: <20230911064320.939791-39-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=alistair23@gmail.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414950489100001 From: Daniel Henrique Barboza A build with --enable-debug and without KVM will fail as follows: /usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_riscv_virt.c.o: in function `v= irt_machine_init': ./qemu/build/../hw/riscv/virt.c:1465: undefined reference to `kvm_riscv_aia= _create' This happens because the code block with "if virt_use_kvm_aia(s)" isn't being ignored by the debug build, resulting in an undefined reference to a KVM only function. Add a 'kvm_enabled()' conditional together with virt_use_kvm_aia() will make the compiler crop the kvm_riscv_aia_create() call entirely from a non-KVM build. Note that adding the 'kvm_enabled()' conditional inside virt_use_kvm_aia() won't fix the build because this function would need to be inlined multiple times to make the compiler zero out the entire block. While we're at it, use kvm_enabled() in all instances where virt_use_kvm_aia() is checked to allow the compiler to elide these other kvm-only instances as well. Suggested-by: Richard Henderson Fixes: dbdb99948e ("target/riscv: select KVM AIA in riscv virt machine") Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-ID: <20230830133503.711138-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 496c17c644..5edc1d98d2 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -782,7 +782,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, } =20 /* KVM AIA only has one APLIC instance */ - if (virt_use_kvm_aia(s)) { + if (kvm_enabled() && virt_use_kvm_aia(s)) { create_fdt_socket_aplic(s, memmap, 0, msi_m_phandle, msi_s_phandle, phandle, &intc_phandles[0], xplic_phandles, @@ -808,7 +808,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const= MemMapEntry *memmap, =20 g_free(intc_phandles); =20 - if (virt_use_kvm_aia(s)) { + if (kvm_enabled() && virt_use_kvm_aia(s)) { *irq_mmio_phandle =3D xplic_phandles[0]; *irq_virtio_phandle =3D xplic_phandles[0]; *irq_pcie_phandle =3D xplic_phandles[0]; @@ -1461,7 +1461,7 @@ static void virt_machine_init(MachineState *machine) } } =20 - if (virt_use_kvm_aia(s)) { + if (kvm_enabled() && virt_use_kvm_aia(s)) { kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MS= IS, memmap[VIRT_APLIC_S].base, --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414979; cv=none; d=zohomail.com; s=zohoarc; b=dTiSMJo0Nom07S5T8VkXylvgoq5cHKrBH4Roz6EAsFTmgBotoDDlzDTg6OkcBtLU9eFe2GwkN/fiBXnGCh+kvLZdmd7bEL+k2k3EgIMyRFGv7aNrJT71XOXQwmy79QFpLlZXSfCvgq/D49fzeNLnMswY6p04pqYaXn0EcZhClow= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414979; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZSYhbUljQLmwwhGQ4cyo7MT1zkKpeBlZTKYRcuPWFf8=; b=bhlCh+0O5IL37wL8MLD+x1aC3/c+qx5tnV1fcsfn87SCl364F92vq/cvrL06sSI+Qxv/wGKb8vsLRVCtSQw/FS55m7GmJfyBvO/BKR+9l5i/arxVEvPUzkAkL+VJkeo8c1sgKMbiwu1aps134TUxb+yEYV0OTkVMdUmq4q4WEbE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414979661167.8194574482509; Sun, 10 Sep 2023 23:49:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagf-0004yn-SB; Mon, 11 Sep 2023 02:46:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfagX-0003ox-6g for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:46:14 -0400 Received: from mail-oa1-x2a.google.com ([2001:4860:4864:20::2a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfagU-0005Ft-EM for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:46:12 -0400 Received: by mail-oa1-x2a.google.com with SMTP id 586e51a60fabf-1d544a4a2f2so2851082fac.3 for ; Sun, 10 Sep 2023 23:46:10 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.46.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:46:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414768; x=1695019568; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZSYhbUljQLmwwhGQ4cyo7MT1zkKpeBlZTKYRcuPWFf8=; b=hiqDz9zwqHM1mCL1WzsBnIaBpHOxSUxNdUbHomYSmfzLVT0qxJKLawIpj5Bry8VbRd 19rKzxmR2hMkLe6WeBEvq4dqvX79Yr1xus/EXvmS8XhuH0HkI4BV9ZgQFSWe0eTDYzZq p0xsabxXA+QP7H3L2bJ38WDzGvw1mbkK0ciuSJUgdLuGwZeB4/T1m1rrDKWq5j76ARNq to2djK6+qDMpdOwbJ/YTKbrGTXg11wBi+wqxKNXeJZzJCOnbngAumiTBBd6SClWgHuku yutekaLfi5eBk4T8IlMnEGLwiiyDk9jpoMLpbSZljXWMkWMSF5ffuXVveRAd2UAtD8PZ kAsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414768; x=1695019568; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZSYhbUljQLmwwhGQ4cyo7MT1zkKpeBlZTKYRcuPWFf8=; b=g1njohBdR0uZkNzP1nC5T/srvzlMYi7NgC6L3Dddh1d9GSU1MhgqbgtDSIjDdxLo6K jj8UuZEn4ByIWbLUYC7iODs31RNPpvUpROTOMPC3f1Fejk2Ma1cdkliI5S7BUk+8kpCm xWWyqCOW/1FJeodslP8gXOy4O0/5Ji8yee6a86givbeRqIJX3CWtQ6rFFUpJa4/Bt2Fc lflLSHm4IwDpst6owyEMHzONVC8KzqVZKoblPI97hph6DNNlXTSxJzcvuqMAj55p9jlA oEaHdeqarnojQzaghfg9ftxLyF9pf5zpylMw78nYsJtGsoJHIEmTefWXGQjxLMVl5rRF LGVA== X-Gm-Message-State: AOJu0YxYGd+GVDDv+0EAZbzmnQ57y9E54A3+bgpDBADVANYNMbhPi6vP 3kRgAY813RfkGcsCMOpbTfSHTzrE8OGC2Q== X-Google-Smtp-Source: AGHT+IHo/FLd0mab7/j7DFUSSHu7JhMcH1OAkkY/yaJdmApVmqZc0GFAKsOb8YY8M0mgnQjRqPdz4Q== X-Received: by 2002:a05:6870:70a9:b0:1d4:cebb:63ba with SMTP id v41-20020a05687070a900b001d4cebb63bamr11003004oae.1.1694414768594; Sun, 10 Sep 2023 23:46:08 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Andrew Jones , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Alistair Francis Subject: [PULL v2 39/45] hw/intc/riscv_aplic.c fix non-KVM --enable-debug build Date: Mon, 11 Sep 2023 16:43:14 +1000 Message-ID: <20230911064320.939791-40-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2a; envelope-from=alistair23@gmail.com; helo=mail-oa1-x2a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414981015100004 From: Daniel Henrique Barboza Commit 6df0b37e2ab breaks a --enable-debug build in a non-KVM environment with the following error: /usr/bin/ld: libqemu-riscv64-softmmu.fa.p/hw_intc_riscv_aplic.c.o: in funct= ion `riscv_kvm_aplic_request': ./qemu/build/../hw/intc/riscv_aplic.c:486: undefined reference to `kvm_set_= irq' collect2: error: ld returned 1 exit status This happens because the debug build will poke into the 'if (is_kvm_aia(aplic->msimode))' block and fail to find a reference to the KVM only function riscv_kvm_aplic_request(). There are multiple solutions to fix this. We'll go with the same solution from the previous patch, i.e. add a kvm_enabled() conditional to filter out the block. But there's a catch: riscv_kvm_aplic_request() is a local function that would end up being used if the compiler crops the block, and this won't work. Quoting Richard Henderson's explanation in [1]: "(...) the compiler won't eliminate entire unused functions with -O0" We'll solve it by moving riscv_kvm_aplic_request() to kvm.c and add its declaration in kvm_riscv.h, where all other KVM specific public functions are already declared. Other archs handles KVM specific code in this manner and we expect to do the same from now on. [1] https://lore.kernel.org/qemu-riscv/d2f1ad02-eb03-138f-9d08-db676deeed05= @linaro.org/ Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-ID: <20230830133503.711138-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/kvm_riscv.h | 1 + hw/intc/riscv_aplic.c | 8 ++------ target/riscv/kvm.c | 5 +++++ 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index 7d4b7c60e2..de8c209ebc 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -26,5 +26,6 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t= group_shift, uint64_t aia_irq_num, uint64_t aia_msi_num, uint64_t aplic_base, uint64_t imsic_base, uint64_t guest_num); +void riscv_kvm_aplic_request(void *opaque, int irq, int level); =20 #endif diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 592c3ce768..99aae8ccbe 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -32,6 +32,7 @@ #include "target/riscv/cpu.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" +#include "kvm_riscv.h" #include "migration/vmstate.h" =20 #define APLIC_MAX_IDC (1UL << 14) @@ -481,11 +482,6 @@ static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState= *aplic, uint32_t idc) return topi; } =20 -static void riscv_kvm_aplic_request(void *opaque, int irq, int level) -{ - kvm_set_irq(kvm_state, irq, !!level); -} - static void riscv_aplic_request(void *opaque, int irq, int level) { bool update =3D false; @@ -840,7 +836,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error= **errp) * have IRQ lines delegated by their parent APLIC. */ if (!aplic->parent) { - if (is_kvm_aia(aplic->msimode)) { + if (kvm_enabled() && is_kvm_aia(aplic->msimode)) { qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irq= s); } else { qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs); diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 6e909d0fdd..c01cfb03f4 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -46,6 +46,11 @@ #include "sysemu/runstate.h" #include "hw/riscv/numa.h" =20 +void riscv_kvm_aplic_request(void *opaque, int irq, int level) +{ + kvm_set_irq(kvm_state, irq, !!level); +} + static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, uint64_t idx) { --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414886; cv=none; d=zohomail.com; s=zohoarc; b=B4xIuy3hT0VZZB7yd3T3JhGPfKstTwNtQip7kVa8lXoKn4KacgBlasRcbDKrnpPA0+awQ+G6NdLV4Gb9/3r7Kk7MwJNP5AhN21wWcxn5Y3AXz6JnqNyJygEWZ87ZOhcvnKUxmJaXMlYD0jXb8xxn5gYs6TbRz4vtFt5n55TBMoU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414886; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BNko/n7sZ+Pauuo1Y0kdsEEem9IIq4A/xXv8veLPZZU=; b=fjkA+TZEcxT2kuonGCu7yM6rjwEnzXYgUfuA/xHO5fDRvNsKBzVEu3zsxCxp5T2rhvrNgHemvMATey8TiOrhMxcPp0cn/j1pbW9WPJYe+toVFtm6zhq0G891Z/hOxdLcKXO7cW2E1/+Jt3z8Q0kEeeKWkFZe82K5Q5ZRBEj9/uI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414886474129.02455286315262; Sun, 10 Sep 2023 23:48:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagd-0004cL-DJ; Mon, 11 Sep 2023 02:46:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfaga-00049h-32 for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:46:16 -0400 Received: from mail-oo1-xc2c.google.com ([2607:f8b0:4864:20::c2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfagX-0005GL-Q4 for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:46:15 -0400 Received: by mail-oo1-xc2c.google.com with SMTP id 006d021491bc7-5735282d713so2599210eaf.2 for ; Sun, 10 Sep 2023 23:46:13 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.46.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:46:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414772; x=1695019572; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BNko/n7sZ+Pauuo1Y0kdsEEem9IIq4A/xXv8veLPZZU=; b=KNiNVzZGq7hnCKM6hQtDGEgh0b22sGbfKOJWE7eKo+TQGZ/X1YoDqsq5M8y1d2L9rK M+z4S88xQIBQIjd57HkdAdLTg5hYJkjPqbhqOEeYJGL4dP39TrKpQ5VPj05ZjWX1q9gW SPtk5gbALea1tY98LqndhqqC5LQTPH6EKjMxBUUICuDZUCtOnv/aOwy43VRO5c6SQwws USneUwhIHtp6AwktgGUDzxbQpRlCfItzsVaQOEBSbl0+AT++d5QA+G5f6T+BC7NeQZe6 9tRKHfoUVaKZJa6CNpMQMtjoVYxWIKAxlunziQMYit08cXH/ybmMoiqYFBl6F197Ut0A 9T+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414772; x=1695019572; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BNko/n7sZ+Pauuo1Y0kdsEEem9IIq4A/xXv8veLPZZU=; b=bPgRynJN/rCFhUmZOZqr6icnJONmqVGG7AY307k/DPW5+jatbOM/DyDcKRIIBKMeXD vwEf5DADXdugHQaNebLDmO1uYEx7bTRmclZ5CXQcMw+nudd9c768PPZ3x9191Xn20T54 lIKEb/lVpoZD68welOQPNmyZeomRhNvNZHIiz7w2hpKdPAEriF6XerBgVNZBlFMAl5WE nzNooF9SIsWBZlJ9/vqMm/J1KS617nGCF+JeJ9t55kbEWdbdBzBFH0r+OTx6fdej9dso KFJ8M3wN8r/T4IMdF9hnh3xWXx2v9DEmhE00TLc0bl+tQM3TdUWaBElS3ngjpI70n7QH WKCw== X-Gm-Message-State: AOJu0YxuwRehY6ndsLvfwTBRgUspJ2gpg7ImHmB8SbM/Zmr4JKE/pjYT hRoFqlw6m96z/lbNBLSIaSyQ2tzB70nGNw== X-Google-Smtp-Source: AGHT+IHC4N+/QaKbrrexvI4ln+qaPfZQJ/FmVN3kZwGlHzqtr+LbX7AF+wQfttg2dkq1oQOkaUTeVg== X-Received: by 2002:a05:6358:988d:b0:13c:fbdb:57b6 with SMTP id q13-20020a056358988d00b0013cfbdb57b6mr9233909rwa.14.1694414772109; Sun, 10 Sep 2023 23:46:12 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Robbin Ehn , Richard Henderson , Alistair Francis Subject: [PULL v2 40/45] linux-user/riscv: Add new extensions to hwprobe Date: Mon, 11 Sep 2023 16:43:15 +1000 Message-ID: <20230911064320.939791-41-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2c; envelope-from=alistair23@gmail.com; helo=mail-oo1-xc2c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414887331100003 Content-Type: text/plain; charset="utf-8" From: Robbin Ehn This patch adds the new extensions in linux 6.5 to the hwprobe syscall. And fixes RVC check to OR with correct value. The previous variable contains 0 therefore it did work. Signed-off-by: Robbin Ehn Acked-by: Richard Henderson Acked-by: Alistair Francis Message-ID: Signed-off-by: Alistair Francis --- linux-user/syscall.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index dac0641bab..3521a2d70b 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -8793,6 +8793,10 @@ static int do_getdents64(abi_long dirfd, abi_long ar= g2, abi_long count) #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 #define RISCV_HWPROBE_IMA_FD (1 << 0) #define RISCV_HWPROBE_IMA_C (1 << 1) +#define RISCV_HWPROBE_IMA_V (1 << 2) +#define RISCV_HWPROBE_EXT_ZBA (1 << 3) +#define RISCV_HWPROBE_EXT_ZBB (1 << 4) +#define RISCV_HWPROBE_EXT_ZBS (1 << 5) =20 #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) @@ -8840,7 +8844,15 @@ static void risc_hwprobe_fill_pairs(CPURISCVState *e= nv, riscv_has_ext(env, RVD) ? RISCV_HWPROBE_IMA_FD : 0; value |=3D riscv_has_ext(env, RVC) ? - RISCV_HWPROBE_IMA_C : pair->value; + RISCV_HWPROBE_IMA_C : 0; + value |=3D riscv_has_ext(env, RVV) ? + RISCV_HWPROBE_IMA_V : 0; + value |=3D cfg->ext_zba ? + RISCV_HWPROBE_EXT_ZBA : 0; + value |=3D cfg->ext_zbb ? + RISCV_HWPROBE_EXT_ZBB : 0; + value |=3D cfg->ext_zbs ? + RISCV_HWPROBE_EXT_ZBS : 0; __put_user(value, &pair->value); break; case RISCV_HWPROBE_KEY_CPUPERF_0: --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414998; cv=none; d=zohomail.com; s=zohoarc; b=cfQARV5IEbJ1900z+zfPf1TSgAhC24IzejYyevB1Jep191akWIjGvjt8KJHgT3OfDp4YNASui9HI8kzCo7T4VXUNgPmFMt9tyaBbNwfU3viV1ES3f0ztbBwscjMlGBpOCy5iw7BXXTTfMyww28JjK5RZQhmRAvdYSc/9b1AmfRI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414998; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sm5kdR4zPqERpHwNfrDrMNoNCsEGBcjXZveAeFuP0TY=; b=XQ16kGfH9NzSYC3WKtV+HEly19Vx0kU95oa6Dndjp4sE3UiOb5og/N155X/mt0q75+/4JKS01MgHtUzzdEBRAcP4QgCOujMr2zrxMBP8ophSTMDwDuf9y8ZdBQLfCqvghPUbYITXlEK/w+QrDGmr8f5RmxV9qorloxIbwXFDRAE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414998466996.7507603064232; Sun, 10 Sep 2023 23:49:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagf-0004yT-Qk; Mon, 11 Sep 2023 02:46:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfagd-0004jq-V2 for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:46:19 -0400 Received: from mail-oi1-x22a.google.com ([2607:f8b0:4864:20::22a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfagb-0005Gm-LY for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:46:19 -0400 Received: by mail-oi1-x22a.google.com with SMTP id 5614622812f47-3ab244e7113so2959524b6e.3 for ; Sun, 10 Sep 2023 23:46:17 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.46.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:46:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414776; x=1695019576; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sm5kdR4zPqERpHwNfrDrMNoNCsEGBcjXZveAeFuP0TY=; b=WCweJ4wM70UV/yCzNhhxJ/g1u9zbmT3ncmqaTN59+xDVBLo82D7Ww5GaWXjG4O4nJ4 T/rbK+wlaaTNu9FCdNLK5s1LQlozDH9eTHKS2DMrSuCUojwgRKVcpPidamDFwDlqO0YW GuxqP2ad3FWPK9/eiqJ1rf8q/uEhAheALcg/v86rqFTKL4RB3c0HHAlbkfbjOyaRzUsU pM5IGt0uiS9ufn9wGeYHI7sTyH2CsVo1a+HeoRwwZvP8x+Ah22oloktRNg7iDlA5QemZ P1jlKHwdbr/A28nn4zbYoapcTYXxdt4kja+Z2SulZbgrU7c9/IAI+81md+xEKwO7pKjv aHvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414776; x=1695019576; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sm5kdR4zPqERpHwNfrDrMNoNCsEGBcjXZveAeFuP0TY=; b=o8QV3f8gAVY4GPEgKKHyg0WHTKx4NhoEgDPMMBktIEGDJJ14B5q+ztr5Gh2ppoJX1t dmFL3SBLvgPR1iK+BQf/7bgDCABmkYoTVoXPSl2SunDE12RHbwpyN6Xcaq13VedcplCx aGZCZUirRos9kb1JICffioqMSIqdlOn26/Nl1JSKjLFOHhnO8Hr3IjVGmi9Uym92HkoD rpJ4a1HtAOuW8o4t9KDv0B5UyitLnrSALNa/8/8M6IQHdlAbs/sPoV5CbD3sUNqm296m FsNRr3wdULiIy0v9UmTj5vyP7IdpgI5D4uNU/6jBnN+mWG7GTV4eSiha/g0fogJKf62N 6tGw== X-Gm-Message-State: AOJu0YxOjh1U8GczSjIhwTxUuXxSTZJpVn5u6c81vnOqaR84VdiNHJNb n/EY1nEGe3KNrrk58vq6mMsELovZO/wesg== X-Google-Smtp-Source: AGHT+IFD4EsUUvvDSVGoCUoA5YLxY24f8nnIyIhWXbjdOdWdqjNSz+rFfnUhSZV8wKwjWDiVs2mrog== X-Received: by 2002:a05:6870:a10b:b0:1bf:80f2:8429 with SMTP id m11-20020a056870a10b00b001bf80f28429mr10852107oae.40.1694414776271; Sun, 10 Sep 2023 23:46:16 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Ard Biesheuvel , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Alistair Francis Subject: [PULL v2 41/45] target/riscv: Use accelerated helper for AES64KS1I Date: Mon, 11 Sep 2023 16:43:16 +1000 Message-ID: <20230911064320.939791-42-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=alistair23@gmail.com; helo=mail-oi1-x22a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414999317100001 From: Ard Biesheuvel Use the accelerated SubBytes/ShiftRows/AddRoundKey AES helper to implement the first half of the key schedule derivation. This does not actually involve shifting rows, so clone the same value into all four columns of the AES vector to counter that operation. Cc: Richard Henderson Cc: Philippe Mathieu-Daud=C3=A9 Cc: Palmer Dabbelt Cc: Alistair Francis Signed-off-by: Ard Biesheuvel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-ID: <20230831154118.138727-1-ardb@kernel.org> Signed-off-by: Alistair Francis --- target/riscv/crypto_helper.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c index 4d65945429..bb084e00ef 100644 --- a/target/riscv/crypto_helper.c +++ b/target/riscv/crypto_helper.c @@ -148,24 +148,17 @@ target_ulong HELPER(aes64ks1i)(target_ulong rs1, targ= et_ulong rnum) =20 uint8_t enc_rnum =3D rnum; uint32_t temp =3D (RS1 >> 32) & 0xFFFFFFFF; - uint8_t rcon_ =3D 0; - target_ulong result; + AESState t, rc =3D {}; =20 if (enc_rnum !=3D 0xA) { temp =3D ror32(temp, 8); /* Rotate right by 8 */ - rcon_ =3D round_consts[enc_rnum]; + rc.w[0] =3D rc.w[1] =3D round_consts[enc_rnum]; } =20 - temp =3D ((uint32_t)AES_sbox[(temp >> 24) & 0xFF] << 24) | - ((uint32_t)AES_sbox[(temp >> 16) & 0xFF] << 16) | - ((uint32_t)AES_sbox[(temp >> 8) & 0xFF] << 8) | - ((uint32_t)AES_sbox[(temp >> 0) & 0xFF] << 0); + t.w[0] =3D t.w[1] =3D t.w[2] =3D t.w[3] =3D temp; + aesenc_SB_SR_AK(&t, &t, &rc, false); =20 - temp ^=3D rcon_; - - result =3D ((uint64_t)temp << 32) | temp; - - return result; + return t.d[0]; } =20 target_ulong HELPER(aes64im)(target_ulong rs1) --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414994; cv=none; d=zohomail.com; s=zohoarc; b=m8SfEVld1KCr8Zmy07aOvlLKLq6bxF58ZISj3OF7FeG8INVMWYWUGf2Zi8u8q8REWevFWM++jt62QSYM+GUAYaBhcYmeLqQqBXfiS9FWlLoS422VifAvzgoqy9yXCNjHgprPWmX9WC/uqxSwQVlcirvgI2ovq9+bGNM3/OhOl2E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414994; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Uoek3ZrjREzdWi9x/k5swYAWV5D/iUYdPsvID2abYl4=; b=mGMbmq+MWtpn7Kf0eLXSw7RLluCZD18JkYgG/RGpz9rnkX0MOpLPm3yw9HeKPc/nJ14T3S1NF7fcrUffJwQm5CcDwf5o5ysAoeips+ahZBBRorPItn+zc2eYeV6ufi7DXPZ9uTZXmab6MjTRCchLqJ/CJcBLHChL8LgKNwXJBgg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414994329939.7307619846337; Sun, 10 Sep 2023 23:49:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagn-0005hw-5e; Mon, 11 Sep 2023 02:46:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfagj-0005QF-Vh for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:46:26 -0400 Received: from mail-oo1-xc30.google.com ([2607:f8b0:4864:20::c30]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfagg-0005H7-IK for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:46:25 -0400 Received: by mail-oo1-xc30.google.com with SMTP id 006d021491bc7-570e005c480so2523726eaf.0 for ; Sun, 10 Sep 2023 23:46:21 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.46.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:46:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414780; x=1695019580; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Uoek3ZrjREzdWi9x/k5swYAWV5D/iUYdPsvID2abYl4=; b=N3psNYEGotsSwXjViUFWKgZ86vj5U3Qdz/H2OojY7dhfT0ql+B8IB8FfhyXewuitpE zpE5+q0shvPGlvGB2a5ayLJMhnz+7aoCrX6cQCPktE4C9PLWjEanKNWs4Fn4piwhRQ+O vwYZWB1tck3SICJ6j41vhwPe0UD/Pjt7TSfhx6I4ZEpwUJhoVPlFxTSow2joQH9tzRf0 yH10hUwsqXGABcZDUTyZYXEw/+U5cx7Tc8KZ3ZiRnnokPsTuLytH4jKealJhBCW47+GL EizKupXe680rhbtoYu7hpRt+chVfB93/8iSJowuRg8EeVnloANNv51xdijff9ekvmqYe +9Ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414780; x=1695019580; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Uoek3ZrjREzdWi9x/k5swYAWV5D/iUYdPsvID2abYl4=; b=Q/rleVbwRj6nk6iJC1W/31fczOU5hogdeYchjhe2mLvKHFvV8gTFkLn48W0zl4QUp8 81Gv8QqfNKFq+qznRePQbZwMK0742uwx0v87x0oTvO6tODXLVBJfBGG0DGwfUePH3vrS ZaY+zoL5/mLG3IdaXWYTjZ0IiyAPBCUIYfkcHy/U1Mxqe9vGPgDmwBLyVUqjyQ2JXMf/ 3SXOCY1vT+xH08I43tot8kFmCiJRnzw22EmvNBfEtmgA/Bi2nBso3CBGiKpeuu1UQOya HFXqvtHEriBDSyjESZ0HDxFgSDgSWG1ww0zgbKgrLW32QjKD7ubWM4b4Ez35T6RbHxwq xlyQ== X-Gm-Message-State: AOJu0YyCPpMd1WrD1KeAjcuO+kwJDD+57t1H7nCv7fMl2ZeIrR4pRXk2 mfYU2aODkbv9lbFB3sQT+UXmVhzz89lBVg== X-Google-Smtp-Source: AGHT+IEFcKk7qwi1jOO6T2/h3QLYBEDKagXEeo/QCszNUZ+c8RMlSPzztJO5yD1EGbPZ6P/lMDz36w== X-Received: by 2002:a05:6358:1101:b0:134:fdfc:4319 with SMTP id f1-20020a056358110100b00134fdfc4319mr9059668rwi.20.1694414779974; Sun, 10 Sep 2023 23:46:19 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Akihiko Odaki , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , LIU Zhiwei , Alistair Francis Subject: [PULL v2 42/45] target/riscv: Allocate itrigger timers only once Date: Mon, 11 Sep 2023 16:43:17 +1000 Message-ID: <20230911064320.939791-43-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c30; envelope-from=alistair23@gmail.com; helo=mail-oo1-xc30.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414995361100009 From: Akihiko Odaki riscv_trigger_init() had been called on reset events that can happen several times for a CPU and it allocated timers for itrigger. If old timers were present, they were simply overwritten by the new timers, resulting in a memory leak. Divide riscv_trigger_init() into two functions, namely riscv_trigger_realize() and riscv_trigger_reset() and call them in appropriate timing. The timer allocation will happen only once for a CPU in riscv_trigger_realize(). Fixes: 5a4ae64cac ("target/riscv: Add itrigger support when icount is enabl= ed") Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-ID: <20230818034059.9146-1-akihiko.odaki@daynix.com> Signed-off-by: Alistair Francis --- target/riscv/debug.h | 3 ++- target/riscv/cpu.c | 8 +++++++- target/riscv/debug.c | 15 ++++++++++++--- 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index c471748d5a..5794aa6ee5 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -143,7 +143,8 @@ void riscv_cpu_debug_excp_handler(CPUState *cs); bool riscv_cpu_debug_check_breakpoint(CPUState *cs); bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); =20 -void riscv_trigger_init(CPURISCVState *env); +void riscv_trigger_realize(CPURISCVState *env); +void riscv_trigger_reset_hold(CPURISCVState *env); =20 bool riscv_itrigger_enabled(CPURISCVState *env); void riscv_itrigger_update_priv(CPURISCVState *env); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index bf0912014e..f227c7664e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -926,7 +926,7 @@ static void riscv_cpu_reset_hold(Object *obj) =20 #ifndef CONFIG_USER_ONLY if (cpu->cfg.debug) { - riscv_trigger_init(env); + riscv_trigger_reset_hold(env); } =20 if (kvm_enabled()) { @@ -1525,6 +1525,12 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) =20 riscv_cpu_register_gdb_regs_for_features(cs); =20 +#ifndef CONFIG_USER_ONLY + if (cpu->cfg.debug) { + riscv_trigger_realize(&cpu->env); + } +#endif + qemu_init_vcpu(cs); cpu_reset(cs); =20 diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 211f5921b6..4945d1a1f2 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -903,7 +903,17 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CP= UWatchpoint *wp) return false; } =20 -void riscv_trigger_init(CPURISCVState *env) +void riscv_trigger_realize(CPURISCVState *env) +{ + int i; + + for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { + env->itrigger_timer[i] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + riscv_itrigger_timer_cb, env= ); + } +} + +void riscv_trigger_reset_hold(CPURISCVState *env) { target_ulong tdata1 =3D build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0); int i; @@ -928,7 +938,6 @@ void riscv_trigger_init(CPURISCVState *env) env->tdata3[i] =3D 0; env->cpu_breakpoint[i] =3D NULL; env->cpu_watchpoint[i] =3D NULL; - env->itrigger_timer[i] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, - riscv_itrigger_timer_cb, env= ); + timer_del(env->itrigger_timer[i]); } } --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414993; cv=none; d=zohomail.com; s=zohoarc; b=DL7A99WaKnDEzzAdAGgkE9F6xPBNhrTomqfPE4ozw8jd2cSaD63/2lCHuJ7oPKIN2NqjE8s+EG0PBpPZbs9Ni9ReiMXIN34fKeCxY5aU9uh+oGdj0GhbvE00/5mCULePhvQEyVm+QgFZ5S7enpfNhEuchPaAiXBBse37RA5EYm8= ARC-Message-Signature: i=1; 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.46.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:46:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414783; x=1695019583; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0AugPxvR0Xk9MuYdUUIr4+5lfDeBI452w5K1Z6wU4Oo=; b=gfQ8VCfAWU70sVX49r5Rslx72mer9AoRf/QGxcsoHDlxNRANHNOFCJIIpEfYIPooK9 vbZLWcC/OMQvWP+ItKTR6l4sQCfEmPOUXxFcU8u5/QJQN0m7ksSWapxkp0eQ1Q2FNShW 2CwtJP0DVNj9doIIVHHMQccWIHtvf9sDSF6vW0DZC++D7PYMDFI1mJx6009SkIBWSint vCEM0tkoOH8jvdYyvlv1hh12oW6YlA6MOZ0zIM/WxhkSiPDmi1tZTlk4ochrx6ohMQao zkz4pDtyxDkqw9/gGoert1vf9NW2zf4+ND6BzPii44v2u3gclhvFuHOJ1K8onuhEnzWj nSgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414783; x=1695019583; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0AugPxvR0Xk9MuYdUUIr4+5lfDeBI452w5K1Z6wU4Oo=; b=rB2F12GQIYsa3YAPHvpo7vlz893z/CA1WSQ9JuVsCJIeprpCW2wdS0RU3f0Wjder8t NmcDz/4ndr5k5MyC75iURxH8kYNrpHHRVUHk9pBshoJB/DQ9p9EjOoesNrrkInGQ7nWI s+y4EkxrIU3L54SyauyNLmR47kwo0Gs7yyfoDFBWcTgfxkA9IDdV9VKH1pgNab8+yqPR Yk+Uktk7gXIk+2JyQcN0Bfi6x04NYnHPSjzXw4LUo85A375M7AYdkI40N/C151QOTcmT 8nKBVQgnSG3p237it9W+IHxdyy3I7Kbh7FBLh6V9bdvXY7Pke6tW2uBeMG4hwCxmNY/a 98LA== X-Gm-Message-State: AOJu0YykyhGmt98DEF80W7heo0mLg3Rco4S/Ero4mJn4d2l9upbhzMxj deL9Yo0ELCQsdExSUywFulwapAj1mxBZJA== X-Google-Smtp-Source: AGHT+IEVLVEcX79DeXQ3kBd8e1QJoa73XblKltDC7W915UcLk/DVGmWAx1033QvwyS3QFjyiSQxieg== X-Received: by 2002:a05:6808:2390:b0:3a7:48eb:2de2 with SMTP id bp16-20020a056808239000b003a748eb2de2mr12430226oib.26.1694414783561; Sun, 10 Sep 2023 23:46:23 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Leon Schuermann , Mayuresh Chitale , Alistair Francis Subject: [PULL v2 43/45] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes Date: Mon, 11 Sep 2023 16:43:18 +1000 Message-ID: <20230911064320.939791-44-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=alistair23@gmail.com; helo=mail-oi1-x22a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414995220100005 Content-Type: text/plain; charset="utf-8" From: Leon Schuermann When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP configuration lock bits must not apply. While this behavior is implemented for the pmpcfgX CSRs, this bit is not respected for changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR writes work even on locked regions when the global rule-lock bypass is enabled. Signed-off-by: Leon Schuermann Reviewed-by: Mayuresh Chitale Reviewed-by: Alistair Francis Message-ID: <20230829215046.1430463-1-leon@is.currently.online> Signed-off-by: Alistair Francis --- target/riscv/pmp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 9d8db493e6..5e60c26031 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -44,6 +44,10 @@ static inline uint8_t pmp_get_a_field(uint8_t cfg) */ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index) { + /* mseccfg.RLB is set */ + if (MSECCFG_RLB_ISSET(env)) { + return 0; + } =20 if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) { return 1; --=20 2.41.0 From nobody Wed May 15 14:38:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694414902; cv=none; d=zohomail.com; s=zohoarc; b=HGEbe1PUA+/7lHT/eMLc5eVEuGl2C/PEyvPIwlX17lagrV5Yzv14u2JZwbGWw6LQQQY+ExxrooeE9XNk4NABu/pIMO7ny9EunFfJH8aQuf27D1hn5aiwFUX5TrzeFakQGd8GGIRVV3FzJO7i+FX9fSWMJnLKPjD30I5d3MAX3cI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694414902; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nlgYYuBXPFCdLBsWmioJLqNQ2mwRjae6i2nTBUm3gh8=; b=fE2E+ExrxSoNXdUWyLr77bX4PuA44+Fut6s5vl93SuK2BtKcJyCicpla6P7mODv6KzrnUXGN0NuS3XEHjzSNDE1+IPPpbKJTFisirBetEHXsR1Rw8gHJQ0ZPm1oZtedhuR/Jh7dDN8D3vziA3URIw5taoPKkvzUD7Tadd08gmt8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694414902764723.8216810237658; Sun, 10 Sep 2023 23:48:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qfagt-0006nE-3T; Mon, 11 Sep 2023 02:46:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qfagq-0006QK-Hr for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:46:32 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qfagn-0005I7-Tg for qemu-devel@nongnu.org; Mon, 11 Sep 2023 02:46:32 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-68cbbff84f6so3530089b3a.1 for ; Sun, 10 Sep 2023 23:46:29 -0700 (PDT) Received: from toolbox.alistair23.me (2403-580b-97e8-0-321-6fb2-58f1-a1b1.ip6.aussiebb.net. [2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.46.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:46:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414787; x=1695019587; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nlgYYuBXPFCdLBsWmioJLqNQ2mwRjae6i2nTBUm3gh8=; b=BNZSIa5sbTAHNZLQyMNxF7cMnWjsw5cuH0Qmg9hZXMqyeCPKLJYyxo0qEn+6+a4wG+ buocdF9R9QX1Qhx1yZmAtcFVNT8tepX1Vei1gWm6pOyn7DCiAA2FGobFbkwIWyCu3PHW ijfDH7G0I74pjOGKQFPqUYSqGpsNVKEB+EMNsKNJ/DYlkwk8YQytJx7yTFD06NaPfhuD TqGm0tjed1BuR6YMzn2nNI+O30rUOfvkDNzyZBwGQvjXqH/54SGtP0tCXCRIyMxeGj33 H8nmdAbRPYPpwQJl2etHQy1+78UTAqjQzNTL/670aRTM1RKBAlxhilyN/iZlOwIcF6z3 kWMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414787; x=1695019587; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nlgYYuBXPFCdLBsWmioJLqNQ2mwRjae6i2nTBUm3gh8=; b=X4e7R9vuxMPVM3wkbwLY97Tp2hgNwFmVpAu7ibFDMd8605uCKc97j0QJed0nJiyOaA y1EmgNv7Nw2FhF45RMNWw6+jYKRhtczo2Yqv4wT9nGEczHAcd3alwYWX2G6Q5typcAPB atQwe3V1R5AtaVZw+rjUV5hc8bqV+jPvH/L6PUxTtkCEidbVdBE68/f5X6f/V+yfYSwZ bPzaQEaXeZ1ftFU7MjPrTtY1f4iQZxV5bMj5FrgkBeJ3MMBGuo7lhN4BZ1egV+H9HldI oDIuJRlWMXLlW+0RiNqIChwHTA3zAedE9LYpu0PUQNFnXmWYMJeF7KrDBIN1rGru9kmo pv5Q== X-Gm-Message-State: AOJu0YwfJs8k0IEhNkfuyC+M+HLPGEL7tys9DG36xOiGNjdYxXCxVDE1 epI9b5v9EGE+4ggE1/9BElX3MouSvWLAxQ== X-Google-Smtp-Source: AGHT+IGxiw5U9K5wkqC0od1JVaTG5c6BbhNBMEbIor/k6p3Lq6UuIzt1kIkIziV2LtfJx98XafuoZQ== X-Received: by 2002:a05:6a21:a58c:b0:153:4ea6:d12e with SMTP id gd12-20020a056a21a58c00b001534ea6d12emr12374831pzc.17.1694414786970; Sun, 10 Sep 2023 23:46:26 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Tommy Wu , Frank Chang , Alistair Francis Subject: [PULL v2 44/45] target/riscv: Align the AIA model to v1.0 ratified spec Date: Mon, 11 Sep 2023 16:43:19 +1000 Message-ID: <20230911064320.939791-45-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=alistair23@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414903471100001 Content-Type: text/plain; charset="utf-8" From: Tommy Wu According to the new spec, when vsiselect has a reserved value, attempts from M-mode or HS-mode to access vsireg, or from VS-mode to access sireg, should preferably raise an illegal instruction exception. Signed-off-by: Tommy Wu Reviewed-by: Frank Chang Message-ID: <20230816061647.600672-1-tommy.wu@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 63c3b0d9fc..68eecc3c96 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1684,7 +1684,7 @@ static int rmw_iprio(target_ulong xlen, static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { - bool virt; + bool virt, isel_reserved; uint8_t *iprio; int ret =3D -EINVAL; target_ulong priv, isel, vgein; @@ -1694,6 +1694,7 @@ static int rmw_xireg(CPURISCVState *env, int csrno, t= arget_ulong *val, =20 /* Decode register details from CSR number */ virt =3D false; + isel_reserved =3D false; switch (csrno) { case CSR_MIREG: iprio =3D env->miprio; @@ -1738,11 +1739,13 @@ static int rmw_xireg(CPURISCVState *env, int csrno,= target_ulong *val, riscv_cpu_mxl_bits(env)), val, new_val, wr_mask); } + } else { + isel_reserved =3D true; } =20 done: if (ret) { - return (env->virt_enabled && virt) ? + return (env->virt_enabled && virt && !isel_reserved) ? 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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id q12-20020a656a8c000000b00553dcfc2179sm4264606pgu.52.2023.09.10.23.46.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Sep 2023 23:46:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694414790; x=1695019590; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=U4G46vZUX3T6HlmuQo4H9nSm/xnI45i/vWbugcAhR7I=; b=ejulp8BA0JLKZbfoIUFG/KIRozOspxctOVSgUvvUiKktUjVxviABw7A40kCHVMzqGT mQ9fzxXr3Aj1kvPBPbOivhEK3mK5IAcy1VK/lUVNBTw3Dij95EyB41oZEMSu1nC9sJ53 jfv6M1UinCq3TZ0Ya7BIG3W4CISyN28onTJp/7pYSmWlORbalBAr7J9GCKYkVLy/L27/ s8hMyQv+fEhEvpmdD9c9wGOfDX4IrsgJiDFgsnl114jmC3cCBQEK/F/d2P5kE6exD2tl uowxeb/RGnRIjtGmo3orAIFdfyRxtjoVFbYpfRJx+BVNoy98If6nsfSagFLAPexSDSo1 0HWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694414790; x=1695019590; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U4G46vZUX3T6HlmuQo4H9nSm/xnI45i/vWbugcAhR7I=; b=ngQSOJx2t18ymiw0azwRJDsLGHOt1empTqX3ANfMUOIQN8x7DVUXJbMMVHl8+srDZ4 4Tm6LAox5kuoqahrDMJBiToOcueDjCHBWoO0FsKkld1L0Jq+r9t6BH+r2DJfmh47dYFX FkvIUNUDKJ6WfySdmPOiJuj25SN3VuP02EZdVzd/+IwLHS9917gPOjsDLoolJJFhh+W0 brh/CjRXuYRHPVd45GCe32zdM9osO1cZSxOtBFYZnQX0sq+PR+WPOaJJiAWFgXjN8xuY B+y6X/eS3vUmoXQepkivnb0JOKmtsqFqdN0jQlaXd9oJT7lpK81c9Gvrb3gd+lEsSAqn geMw== X-Gm-Message-State: AOJu0YwSf0bj+cg8Y7GHxby+5mGUM2Ma2kRF6M7FAi4oLdR6lJqNfmde itGdLF9XhsI2YBcGqoxVWteMJdWIpJ9NRg== X-Google-Smtp-Source: AGHT+IEQWAr3g0oKZkdhGHmJCKRZKiMkNua7/fXECxTaVzQv+M110EHisgHExNrFpMWAnsBZDJIe1g== X-Received: by 2002:a1f:de84:0:b0:48d:2bcf:f959 with SMTP id v126-20020a1fde84000000b0048d2bcff959mr6387234vkg.3.1694414790187; Sun, 10 Sep 2023 23:46:30 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Nikita Shubin , Alistair Francis Subject: [PULL v2 45/45] target/riscv: don't read CSR in riscv_csrrw_do64 Date: Mon, 11 Sep 2023 16:43:20 +1000 Message-ID: <20230911064320.939791-46-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230911064320.939791-1-alistair.francis@wdc.com> References: <20230911064320.939791-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::a2b; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694414926199100015 Content-Type: text/plain; charset="utf-8" From: Nikita Shubin As per ISA: "For CSRRWI, if rd=3Dx0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read." trans_csrrwi() and trans_csrrw() call do_csrw() if rd=3Dx0, do_csrw() calls riscv_csrrw_do64(), via helper_csrw() passing NULL as *ret_value. Signed-off-by: Nikita Shubin Reviewed-by: Alistair Francis Message-ID: <20230808090914.17634-1-nikita.shubin@maquefel.me> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 68eecc3c96..85a31dc420 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3917,21 +3917,27 @@ static RISCVException riscv_csrrw_do64(CPURISCVStat= e *env, int csrno, target_ulong write_mask) { RISCVException ret; - target_ulong old_value; + target_ulong old_value =3D 0; =20 /* execute combined read/write operation if it exists */ if (csr_ops[csrno].op) { return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_m= ask); } =20 - /* if no accessor exists then return failure */ - if (!csr_ops[csrno].read) { - return RISCV_EXCP_ILLEGAL_INST; - } - /* read old value */ - ret =3D csr_ops[csrno].read(env, csrno, &old_value); - if (ret !=3D RISCV_EXCP_NONE) { - return ret; + /* + * ret_value =3D=3D NULL means that rd=3Dx0 and we're coming from help= er_csrw() + * and we can't throw side effects caused by CSR reads. + */ + if (ret_value) { + /* if no accessor exists then return failure */ + if (!csr_ops[csrno].read) { + return RISCV_EXCP_ILLEGAL_INST; + } + /* read old value */ + ret =3D csr_ops[csrno].read(env, csrno, &old_value); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } } =20 /* write value if writable and write mask set, otherwise drop writes */ --=20 2.41.0