From nobody Wed May 15 16:57:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169426560743470.67594071637188; Sat, 9 Sep 2023 06:20:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qexm3-0008OI-LN; Sat, 09 Sep 2023 09:13:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qexlt-0008EB-SW; Sat, 09 Sep 2023 09:13:11 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qexln-0005H2-3H; Sat, 09 Sep 2023 09:13:08 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 613722062A; Sat, 9 Sep 2023 16:13:51 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 2636026E4A; Sat, 9 Sep 2023 16:13:00 +0300 (MSK) Received: (nullmailer pid 354708 invoked by uid 1000); Sat, 09 Sep 2023 13:12:59 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Michael Tokarev Subject: [PATCH 1/7] bsd-user: spelling fixes Date: Sat, 9 Sep 2023 16:12:52 +0300 Message-Id: <20230909131258.354675-2-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230909131258.354675-1-mjt@tls.msk.ru> References: <20230909131258.354675-1-mjt@tls.msk.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1694265608318100002 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Tokarev Reviewed-by: Kyle Evans Reviewed-by: Warner Losh --- bsd-user/errno_defs.h | 2 +- bsd-user/freebsd/target_os_siginfo.h | 2 +- bsd-user/freebsd/target_os_stack.h | 4 ++-- bsd-user/freebsd/target_os_user.h | 2 +- bsd-user/qemu.h | 2 +- bsd-user/signal-common.h | 4 ++-- bsd-user/signal.c | 6 +++--- 7 files changed, 11 insertions(+), 11 deletions(-) diff --git a/bsd-user/errno_defs.h b/bsd-user/errno_defs.h index f3e8ac3488..abe70119d9 100644 --- a/bsd-user/errno_defs.h +++ b/bsd-user/errno_defs.h @@ -149,7 +149,7 @@ #define TARGET_ELAST 90 /* Must be equal largest e= rrno */ =20 /* Internal errors: */ -#define TARGET_EJUSTRETURN 254 /* Just return without mod= ifing regs */ +#define TARGET_EJUSTRETURN 254 /* Just return without mod= ifying regs */ #define TARGET_ERESTART 255 /* Restart syscall */ =20 #include "special-errno.h" diff --git a/bsd-user/freebsd/target_os_siginfo.h b/bsd-user/freebsd/target= _os_siginfo.h index 4573738752..6c282d8502 100644 --- a/bsd-user/freebsd/target_os_siginfo.h +++ b/bsd-user/freebsd/target_os_siginfo.h @@ -72,7 +72,7 @@ typedef struct target_siginfo { int32_t _mqd; } _mesgp; =20 - /* SIGPOLL -- Not really genreated in FreeBSD ??? */ + /* SIGPOLL -- Not really generated in FreeBSD ??? */ struct { int _band; /* POLL_IN, POLL_OUT, POLL_MSG */ } _poll; diff --git a/bsd-user/freebsd/target_os_stack.h b/bsd-user/freebsd/target_o= s_stack.h index 0590133291..d15fc3263f 100644 --- a/bsd-user/freebsd/target_os_stack.h +++ b/bsd-user/freebsd/target_os_stack.h @@ -25,7 +25,7 @@ #include "qemu/guest-random.h" =20 /* - * The inital FreeBSD stack is as follows: + * The initial FreeBSD stack is as follows: * (see kern/kern_exec.c exec_copyout_strings() ) * * Hi Address -> char **ps_argvstr (struct ps_strings for ps, w, etc.) @@ -59,7 +59,7 @@ static inline int setup_initial_stack(struct bsd_binprm *= bprm, /* Save some space for ps_strings. */ p -=3D sizeof(struct target_ps_strings); =20 - /* Add machine depedent sigcode. */ + /* Add machine dependent sigcode. */ p -=3D TARGET_SZSIGCODE; if (setup_sigtramp(p, (unsigned)offsetof(struct target_sigframe, sf_uc= ), TARGET_FREEBSD_NR_sigreturn)) { diff --git a/bsd-user/freebsd/target_os_user.h b/bsd-user/freebsd/target_os= _user.h index f036a32343..1ca7b5ab17 100644 --- a/bsd-user/freebsd/target_os_user.h +++ b/bsd-user/freebsd/target_os_user.h @@ -26,7 +26,7 @@ struct target_priority { uint8_t pri_class; /* Scheduling class. */ uint8_t pri_level; /* Normal priority level. */ - uint8_t pri_native; /* Priority before propogation. */ + uint8_t pri_native; /* Priority before propagation. */ uint8_t pri_user; /* User priority based on p_cpu and p_nice= . */ }; =20 diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index d3158bc2ed..d9507137cc 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -116,7 +116,7 @@ extern const char *qemu_uname_release; /* * TARGET_ARG_MAX defines the number of bytes allocated for arguments * and envelope for the new program. 256k should suffice for a reasonable - * maxiumum env+arg in 32-bit environments, bump it up to 512k for !ILP32 + * maximum env+arg in 32-bit environments, bump it up to 512k for !ILP32 * platforms. */ #if TARGET_ABI_BITS > 32 diff --git a/bsd-user/signal-common.h b/bsd-user/signal-common.h index 6f90345bb2..c044e81165 100644 --- a/bsd-user/signal-common.h +++ b/bsd-user/signal-common.h @@ -49,11 +49,11 @@ void target_to_host_sigset(sigset_t *d, const target_si= gset_t *s); * union in target_siginfo is valid. This only applies between * host_to_target_siginfo_noswap() and tswap_siginfo(); it does not appear * either within host siginfo_t or in target_siginfo structures which we g= et - * from the guest userspace program. Linux kenrels use this internally, bu= t BSD + * from the guest userspace program. Linux kernels use this internally, bu= t BSD * kernels don't do this, but its a useful abstraction. * * The linux-user version of this uses the top 16 bits, but FreeBSD's SI_U= SER - * and other signal indepenent SI_ codes have bit 16 set, so we only use t= he top + * and other signal independent SI_ codes have bit 16 set, so we only use = the top * byte instead. * * For FreeBSD, we have si_pid, si_uid, si_status, and si_addr always. Lin= ux and diff --git a/bsd-user/signal.c b/bsd-user/signal.c index 4db85a3485..b6beab659e 100644 --- a/bsd-user/signal.c +++ b/bsd-user/signal.c @@ -44,7 +44,7 @@ static inline int sas_ss_flags(TaskState *ts, unsigned lo= ng sp) } =20 /* - * The BSD ABIs use the same singal numbers across all the CPU architectur= es, so + * The BSD ABIs use the same signal numbers across all the CPU architectur= es, so * (unlike Linux) these functions are just the identity mapping. This migh= t not * be true for XyzBSD running on AbcBSD, which doesn't currently work. */ @@ -241,7 +241,7 @@ static inline void host_to_target_siginfo_noswap(target= _siginfo_t *tinfo, #endif /* * Unsure that this can actually be generated, and our support for - * capsicum is somewhere between weak and non-existant, but if we = get + * capsicum is somewhere between weak and non-existent, but if we = get * one, then we know what to save. */ #ifdef QEMU_SI_CAPSICUM @@ -319,7 +319,7 @@ int block_signals(void) /* * It's OK to block everything including SIGSEGV, because we won't run= any * further guest code before unblocking signals in - * process_pending_signals(). We depend on the FreeBSD behaivor here w= here + * process_pending_signals(). We depend on the FreeBSD behavior here w= here * this will only affect this thread's signal mask. We don't use * pthread_sigmask which might seem more correct because that routine = also * does odd things with SIGCANCEL to implement pthread_cancel(). --=20 2.39.2 From nobody Wed May 15 16:57:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694265443228522.0861031423295; Sat, 9 Sep 2023 06:17:23 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qexmV-0000b2-4i; Sat, 09 Sep 2023 09:13:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qexlx-0008JG-HI; Sat, 09 Sep 2023 09:13:18 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qexlt-0005Ho-Dg; Sat, 09 Sep 2023 09:13:12 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 8A6102062B; Sat, 9 Sep 2023 16:13:51 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 53AAC26E4B; Sat, 9 Sep 2023 16:13:00 +0300 (MSK) Received: (nullmailer pid 354711 invoked by uid 1000); Sat, 09 Sep 2023 13:12:59 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Michael Tokarev Subject: [PATCH 2/7] i386: spelling fixes Date: Sat, 9 Sep 2023 16:12:53 +0300 Message-Id: <20230909131258.354675-3-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230909131258.354675-1-mjt@tls.msk.ru> References: <20230909131258.354675-1-mjt@tls.msk.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1694265444945100015 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Tokarev Reviewed-by: Peter Maydell --- host/include/i386/host/cpuinfo.h | 2 +- hw/i386/acpi-build.c | 4 ++-- hw/i386/amd_iommu.c | 4 ++-- hw/i386/intel_iommu.c | 4 ++-- hw/i386/kvm/xen_xenstore.c | 2 +- hw/i386/kvm/xenstore_impl.c | 2 +- hw/i386/pc.c | 4 ++-- include/hw/i386/topology.h | 2 +- target/i386/cpu.c | 4 ++-- target/i386/cpu.h | 4 ++-- target/i386/kvm/kvm.c | 4 ++-- target/i386/kvm/xen-emu.c | 2 +- target/i386/machine.c | 4 ++-- target/i386/tcg/translate.c | 8 ++++---- tests/tcg/i386/system/boot.S | 2 +- tests/tcg/i386/x86.csv | 2 +- 16 files changed, 27 insertions(+), 27 deletions(-) diff --git a/host/include/i386/host/cpuinfo.h b/host/include/i386/host/cpui= nfo.h index 073d0a426f..6e46939132 100644 --- a/host/include/i386/host/cpuinfo.h +++ b/host/include/i386/host/cpuinfo.h @@ -1,6 +1,6 @@ /* * SPDX-License-Identifier: GPL-2.0-or-later - * Host specific cpu indentification for x86. + * Host specific cpu identification for x86. */ =20 #ifndef HOST_CPUINFO_H diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index bb12b0ad43..1afcef5937 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -779,7 +779,7 @@ static Aml *initialize_route(Aml *route, const char *li= nk_name, * * Returns an array of 128 routes, one for each device, * based on device location. - * The main goal is to equaly distribute the interrupts + * The main goal is to equally distribute the interrupts * over the 4 existing ACPI links (works only for i440fx). * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]". * @@ -2079,7 +2079,7 @@ build_srat(GArray *table_data, BIOSLinker *linker, Ma= chineState *machine) } =20 /* - * Insert DMAR scope for PCI bridges and endpoint devcie + * Insert DMAR scope for PCI bridges and endpoint device */ static void insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 9c77304438..c98a3c6e11 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -259,7 +259,7 @@ static void amdvi_log_command_error(AMDVIState *s, hwad= dr addr) pci_word_test_and_set_mask(s->pci.dev.config + PCI_STATUS, PCI_STATUS_SIG_TARGET_ABORT); } -/* log an illegal comand event +/* log an illegal command event * @addr : address of illegal command */ static void amdvi_log_illegalcom_error(AMDVIState *s, uint16_t info, @@ -767,7 +767,7 @@ static void amdvi_mmio_write(void *opaque, hwaddr addr,= uint64_t val, break; case AMDVI_MMIO_COMMAND_BASE: amdvi_mmio_reg_write(s, size, val, addr); - /* FIXME - make sure System Software has finished writing incase + /* FIXME - make sure System Software has finished writing in case * it writes in chucks less than 8 bytes in a robust way.As for * now, this hacks works for the linux driver */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index c9961ef752..c0ce896668 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -52,7 +52,7 @@ =20 /* * PCI bus number (or SID) is not reliable since the device is usaully - * initalized before guest can configure the PCI bridge + * initialized before guest can configure the PCI bridge * (SECONDARY_BUS_NUMBER). */ struct vtd_as_key { @@ -1694,7 +1694,7 @@ static bool vtd_switch_address_space(VTDAddressSpace = *as) * """ * * We enable per as memory region (iommu_ir_fault) for catching - * the tranlsation for interrupt range through PASID + PT. + * the translation for interrupt range through PASID + PT. */ if (pt && as->pasid !=3D PCI_NO_PASID) { memory_region_set_enabled(&as->iommu_ir_fault, true); diff --git a/hw/i386/kvm/xen_xenstore.c b/hw/i386/kvm/xen_xenstore.c index 133d89e953..660d0b72f9 100644 --- a/hw/i386/kvm/xen_xenstore.c +++ b/hw/i386/kvm/xen_xenstore.c @@ -1156,7 +1156,7 @@ static unsigned int copy_to_ring(XenXenstoreState *s,= uint8_t *ptr, =20 /* * This matches the barrier in copy_to_ring() (or the guest's - * equivalent) betweem writing the data to the ring and updating + * equivalent) between writing the data to the ring and updating * rsp_prod. It protects against the pathological case (which * again I think never happened except on Alpha) where our * subsequent writes to the ring could *cross* the read of diff --git a/hw/i386/kvm/xenstore_impl.c b/hw/i386/kvm/xenstore_impl.c index d9732b567e..1d134a6866 100644 --- a/hw/i386/kvm/xenstore_impl.c +++ b/hw/i386/kvm/xenstore_impl.c @@ -1436,7 +1436,7 @@ static void save_node(gpointer key, gpointer value, g= pointer opaque) /* * If we already wrote this node, refer to the previous copy. * There's no rename/move in XenStore, so all we need to find - * it is the tx_id of the transation in which it exists. Which + * it is the tx_id of the transaction in which it exists. Which * may be the root tx. */ if (n->serialized_tx !=3D XBT_NULL) { diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 54838c0c41..2872f60cdf 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -436,7 +436,7 @@ static uint64_t ioport80_read(void *opaque, hwaddr addr= , unsigned size) return 0xffffffffffffffffULL; } =20 -/* MSDOS compatibility mode FPU exception support */ +/* MS-DOS compatibility mode FPU exception support */ static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { @@ -1755,7 +1755,7 @@ static void pc_machine_set_max_fw_size(Object *obj, V= isitor *v, if (value > 16 * MiB) { error_setg(errp, "User specified max allowed firmware size %" PRIu64 " i= s " - "greater than 16MiB. If combined firwmare size exceeds " + "greater than 16MiB. If combined firmware size exceeds " "16MiB the system may not boot, or experience intermitt= ent" "stability issues.", value); diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 81573f6cfd..380cb27ded 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -31,7 +31,7 @@ * * This code should be compatible with AMD's "Extended Method" described a= t: * AMD CPUID Specification (Publication #25481) - * Section 3: Multiple Core Calcuation + * Section 3: Multiple Core Calculation * as long as: * nr_threads is set to 1; * OFFSET_IDX is assumed to be 0; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 24ee67b42d..7033fa3496 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5340,7 +5340,7 @@ static const char *x86_cpu_feature_name(FeatureWord w= , int bitnr) return name; } =20 -/* Compatibily hack to maintain legacy +-feat semantic, +/* Compatibility hack to maintain legacy +-feat semantic, * where +-feat overwrites any feature set by * feat=3Don|feat even if the later is parsed after +-feat * (i.e. "-x2apic,x2apic=3Don" will result in x2apic disabled) @@ -6304,7 +6304,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, * The initial value of xcr0 and ebx =3D=3D 0, On host without= kvm * commit 412a3c41(e.g., CentOS 6), the ebx's value always =3D= =3D 0 * even through guest update xcr0, this will crash some legacy= guest - * (e.g., CentOS 6), So set ebx =3D=3D ecx to workaroud it. + * (e.g., CentOS 6), So set ebx =3D=3D ecx to workaround it. */ *ebx =3D kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, fal= se); } else if (count =3D=3D 1) { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index fbb05eace5..fe06a1b286 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -728,7 +728,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord= w, #define CPUID_EXT2_3DNOWEXT (1U << 30) #define CPUID_EXT2_3DNOW (1U << 31) =20 -/* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD C= PUs */ +/* CPUID[8000_0001].EDX bits that are aliases of CPUID[1].EDX bits on AMD = CPUs */ #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ CPUID_EXT2_DE | CPUID_EXT2_PSE | \ CPUID_EXT2_TSC | CPUID_EXT2_MSR | \ @@ -2071,7 +2071,7 @@ hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cp= u, vaddr addr, MemTxAttrs *attrs); int cpu_get_pic_interrupt(CPUX86State *s); =20 -/* MSDOS compatibility mode FPU exception support */ +/* MS-DOS compatibility mode FPU exception support */ void x86_register_ferr_irq(qemu_irq irq); void fpu_check_raise_ferr_irq(CPUX86State *s); void cpu_set_ignne(void); diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index e5cd7cc806..05dd08b318 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4729,7 +4729,7 @@ int kvm_arch_put_registers(CPUState *cpu, int level) /* * Put MSR_IA32_FEATURE_CONTROL first, this ensures the VM gets out of= VMX * root operation upon vCPU reset. kvm_put_msr_feature_control() shoul= d also - * preceed kvm_put_nested_state() when 'real' nested state is set. + * proceed kvm_put_nested_state() when 'real' nested state is set. */ if (level >=3D KVM_PUT_RESET_STATE) { ret =3D kvm_put_msr_feature_control(x86_cpu); @@ -5653,7 +5653,7 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing_e= ntry *route, } =20 /* - * Handled untranslated compatibilty format interrupt with + * Handled untranslated compatibility format interrupt with * extended destination ID in the low bits 11-5. */ dst.address =3D kvm_swizzle_msi_ext_dest_id(dst.address); =20 diff --git a/target/i386/kvm/xen-emu.c b/target/i386/kvm/xen-emu.c index a8146115f0..76348f9d5d 100644 --- a/target/i386/kvm/xen-emu.c +++ b/target/i386/kvm/xen-emu.c @@ -1033,7 +1033,7 @@ static int do_set_periodic_timer(CPUState *target, ui= nt64_t period_ns) #define MILLISECS(_ms) ((int64_t)((_ms) * 1000000ULL)) #define MICROSECS(_us) ((int64_t)((_us) * 1000ULL)) #define STIME_MAX ((time_t)((int64_t)~0ull >> 1)) -/* Chosen so (NOW() + delta) wont overflow without an uptime of 200 years = */ +/* Chosen so (NOW() + delta) won't overflow without an uptime of 200 years= */ #define STIME_DELTA_MAX ((int64_t)((uint64_t)~0ull >> 2)) =20 static int vcpuop_set_periodic_timer(CPUState *cs, CPUState *target, diff --git a/target/i386/machine.c b/target/i386/machine.c index c7ac8084b2..a1041ef828 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -282,12 +282,12 @@ static int cpu_pre_save(void *opaque) * hypervisor, its exception payload (CR2/DR6 on #PF/#DB) * should not be set yet in the respective vCPU register. * Thus, in case an exception is pending, it is - * important to save the exception payload seperately. + * important to save the exception payload separately. * * Therefore, if an exception is not in a pending state * or vCPU is not in guest-mode, it is not important to * distinguish between a pending and injected exception - * and we don't need to store seperately the exception payload. + * and we don't need to store separately the exception payload. * * In order to preserve better backwards-compatible migration, * convert a pending exception to an injected exception in diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index e0a622941c..c98e42f17a 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -1069,7 +1069,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s= , TCGv reg) } =20 /* perform a conditional store into register 'reg' according to jump opcode - value 'b'. In the fast case, T0 is guaranted not to be used. */ + value 'b'. In the fast case, T0 is guaranteed not to be used. */ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) { int inv, jcc_op, cond; @@ -1202,7 +1202,7 @@ static inline void gen_compute_eflags_c(DisasContext = *s, TCGv reg) } =20 /* generate a conditional jump to label 'l1' according to jump opcode - value 'b'. In the fast case, T0 is guaranted not to be used. */ + value 'b'. In the fast case, T0 is guaranteed not to be used. */ static inline void gen_jcc1_noeob(DisasContext *s, int b, TCGLabel *l1) { CCPrepare cc =3D gen_prepare_cc(s, b, s->T0); @@ -1219,7 +1219,7 @@ static inline void gen_jcc1_noeob(DisasContext *s, in= t b, TCGLabel *l1) } =20 /* Generate a conditional jump to label 'l1' according to jump opcode - value 'b'. In the fast case, T0 is guaranted not to be used. + value 'b'. In the fast case, T0 is guaranteed not to be used. A translation block must end soon. */ static inline void gen_jcc1(DisasContext *s, int b, TCGLabel *l1) { @@ -5355,7 +5355,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (s->prefix & PREFIX_LOCK) { switch (op) { case 0: /* bt */ - /* Needs no atomic ops; we surpressed the normal + /* Needs no atomic ops; we suppressed the normal memory load for LOCK above so do it now. */ gen_op_ld_v(s, ot, s->T0, s->A0); break; diff --git a/tests/tcg/i386/system/boot.S b/tests/tcg/i386/system/boot.S index 794c2cb0ad..9e8920cbfe 100644 --- a/tests/tcg/i386/system/boot.S +++ b/tests/tcg/i386/system/boot.S @@ -71,7 +71,7 @@ _start: add $8,%esp =20 /* - * Don't worry about stack frame, assume everthing + * Don't worry about stack frame, assume everything * is garbage when we return, we won't need it. */ call main diff --git a/tests/tcg/i386/x86.csv b/tests/tcg/i386/x86.csv index c43bf42dd3..5c0f628e35 100644 --- a/tests/tcg/i386/x86.csv +++ b/tests/tcg/i386/x86.csv @@ -19,7 +19,7 @@ # # 4. The instruction encoding. For example, "C1 /4 ib". # -# 5. The validity of the instruction in 32-bit (aka compatiblity, legacy) = mode. +# 5. The validity of the instruction in 32-bit (aka compatibility, legacy)= mode. # # 6. The validity of the instruction in 64-bit mode. # --=20 2.39.2 From nobody Wed May 15 16:57:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169426565335612.672630217453616; Sat, 9 Sep 2023 06:20:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qexmA-0000CF-Mu; Sat, 09 Sep 2023 09:13:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qexly-0008JL-M3; Sat, 09 Sep 2023 09:13:18 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qexlv-0005I9-DM; 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helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1694265654092100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Tokarev Reviewed-by: C=C3=A9dric Le Goater --- host/include/ppc/host/cpuinfo.h | 2 +- hw/ppc/ppc.c | 2 +- hw/ppc/prep_systemio.c | 2 +- hw/ppc/spapr.c | 8 ++++---- hw/ppc/spapr_hcall.c | 2 +- hw/ppc/spapr_nvdimm.c | 4 ++-- hw/ppc/spapr_pci_vfio.c | 2 +- include/hw/ppc/openpic.h | 2 +- include/hw/ppc/spapr.h | 2 +- target/ppc/cpu-models.h | 4 ++-- target/ppc/cpu.h | 2 +- target/ppc/cpu_init.c | 4 ++-- target/ppc/excp_helper.c | 14 +++++++------- target/ppc/power8-pmu-regs.c.inc | 4 ++-- target/ppc/translate/vmx-impl.c.inc | 6 +++--- 15 files changed, 30 insertions(+), 30 deletions(-) diff --git a/host/include/ppc/host/cpuinfo.h b/host/include/ppc/host/cpuinf= o.h index 29ee7f9ef8..38b8eabe2a 100644 --- a/host/include/ppc/host/cpuinfo.h +++ b/host/include/ppc/host/cpuinfo.h @@ -1,6 +1,6 @@ /* * SPDX-License-Identifier: GPL-2.0-or-later - * Host specific cpu indentification for ppc. + * Host specific cpu identification for ppc. */ =20 #ifndef HOST_CPUINFO_H diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index aeb116d919..be167710a3 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -738,7 +738,7 @@ static target_ulong _cpu_ppc_load_decr(CPUPPCState *env= , int64_t now) decr =3D __cpu_ppc_load_decr(env, now, tb_env->decr_next); =20 /* - * If large decrementer is enabled then the decrementer is signed exte= ned + * If large decrementer is enabled then the decrementer is signed exte= nded * to 64 bits, otherwise it is a 32 bit value. */ if (env->spr[SPR_LPCR] & LPCR_LD) { diff --git a/hw/ppc/prep_systemio.c b/hw/ppc/prep_systemio.c index 5a56f155f5..c96cefb13d 100644 --- a/hw/ppc/prep_systemio.c +++ b/hw/ppc/prep_systemio.c @@ -39,7 +39,7 @@ #define TYPE_PREP_SYSTEMIO "prep-systemio" OBJECT_DECLARE_SIMPLE_TYPE(PrepSystemIoState, PREP_SYSTEMIO) =20 -/* Bit as defined in PowerPC Reference Plaform v1.1, sect. 6.1.5, p. 132 */ +/* Bit as defined in PowerPC Reference Platform v1.1, sect. 6.1.5, p. 132 = */ #define PREP_BIT(n) (1 << (7 - (n))) =20 struct PrepSystemIoState { diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index f7cc6a890f..b25b568cee 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2573,7 +2573,7 @@ static void spapr_set_vsmt_mode(SpaprMachineState *sp= apr, Error **errp) return; } =20 - /* Detemine the VSMT mode to use: */ + /* Determine the VSMT mode to use: */ if (vsmt_user) { if (spapr->vsmt < smp_threads) { error_setg(errp, "Cannot support VSMT mode %d" @@ -3109,7 +3109,7 @@ static int spapr_kvm_type(MachineState *machine, cons= t char *vm_type) { /* * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to - * accomodate the 'HV' and 'PV' formats that exists in the + * accommodate the 'HV' and 'PV' formats that exists in the * wild. The 'auto' mode is being introduced already as * lower-case, thus we don't need to bother checking for * "AUTO". @@ -4343,7 +4343,7 @@ spapr_cpu_index_to_props(MachineState *machine, unsig= ned cpu_index) CPUArchId *core_slot; MachineClass *mc =3D MACHINE_GET_CLASS(machine); =20 - /* make sure possible_cpu are intialized */ + /* make sure possible_cpu are initialized */ mc->possible_cpu_arch_ids(machine); /* get CPU core slot containing thread that matches cpu_index */ core_slot =3D spapr_find_cpu_slot(machine, cpu_index, NULL); @@ -5045,7 +5045,7 @@ static void spapr_machine_2_12_class_options(MachineC= lass *mc) =20 /* We depend on kvm_enabled() to choose a default value for the * hpt-max-page-size capability. Of course we can't do it here - * because this is too early and the HW accelerator isn't initialzed + * because this is too early and the HW accelerator isn't initialized * yet. Postpone this to machine init (see default_caps_with_cpu()). */ smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] =3D 0; diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index b7dc388f2f..522a2396c7 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1615,7 +1615,7 @@ static void hypercall_register_types(void) spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS, h_get_cpu_characteristics); =20 - /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenci= ate + /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenti= ate * here between the "CI" and the "CACHE" variants, they will use whate= ver * mapping attributes qemu is using. When using KVM, the kernel will * enforce the attributes more strongly diff --git a/hw/ppc/spapr_nvdimm.c b/hw/ppc/spapr_nvdimm.c index a8688243a6..4e34545dcf 100644 --- a/hw/ppc/spapr_nvdimm.c +++ b/hw/ppc/spapr_nvdimm.c @@ -377,7 +377,7 @@ static target_ulong h_scm_bind_mem(PowerPCCPU *cpu, Spa= prMachineState *spapr, =20 /* * Currently continue token should be zero qemu has already bound - * everything and this hcall doesnt return H_BUSY. + * everything and this hcall doesn't return H_BUSY. */ if (continue_token > 0) { return H_P5; @@ -588,7 +588,7 @@ void spapr_nvdimm_finish_flushes(void) * Called on reset path, the main loop thread which calls * the pending BHs has gotten out running in the reset path, * finally reaching here. Other code path being guest - * h_client_architecture_support, thats early boot up. + * h_client_architecture_support, that's early boot up. */ nvdimms =3D nvdimm_get_device_list(); for (list =3D nvdimms; list; list =3D list->next) { diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c index d8aeee0b7e..9016720547 100644 --- a/hw/ppc/spapr_pci_vfio.c +++ b/hw/ppc/spapr_pci_vfio.c @@ -78,7 +78,7 @@ int spapr_phb_vfio_eeh_set_option(SpaprPhbState *sphb, * call. Now we just need to check the validity of the PCI * pass-through devices (vfio-pci) under this sphb bus. * We have already validated that all the devices under this sphb - * are from same iommu group (within same PE) before comming here. + * are from same iommu group (within same PE) before coming here. * * Prior to linux commit 98ba956f6a389 ("powerpc/pseries/eeh: * Rework device EEH PE determination") kernel would call diff --git a/include/hw/ppc/openpic.h b/include/hw/ppc/openpic.h index bae8dafe16..9c6af8e207 100644 --- a/include/hw/ppc/openpic.h +++ b/include/hw/ppc/openpic.h @@ -14,7 +14,7 @@ enum { OPENPIC_OUTPUT_INT =3D 0, /* IRQ */ OPENPIC_OUTPUT_CINT, /* critical IRQ */ OPENPIC_OUTPUT_MCK, /* Machine check event */ - OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */ + OPENPIC_OUTPUT_DEBUG, /* Unconditional debug event */ OPENPIC_OUTPUT_RESET, /* Core reset event */ OPENPIC_OUTPUT_NB, }; diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index f4bd204d86..b1c7c28fa8 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -197,7 +197,7 @@ struct SpaprMachineState { SpaprResizeHpt resize_hpt; void *htab; uint32_t htab_shift; - uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROC_TBL */ + uint64_t patb_entry; /* Process tbl registered in H_REGISTER_PROC_TBL = */ SpaprPendingHpt *pending_hpt; /* in-progress resize */ =20 hwaddr rma_size; diff --git a/target/ppc/cpu-models.h b/target/ppc/cpu-models.h index 572b5e553a..0229ef3a9a 100644 --- a/target/ppc/cpu-models.h +++ b/target/ppc/cpu-models.h @@ -44,7 +44,7 @@ enum { /* PowerPC 405 cores */ CPU_POWERPC_405D2 =3D 0x20010000, CPU_POWERPC_405D4 =3D 0x41810000, - /* PowerPC 405 microcontrolers */ + /* PowerPC 405 microcontrollers */ /* XXX: missing 0x200108a0 */ CPU_POWERPC_405CRa =3D 0x40110041, CPU_POWERPC_405CRb =3D 0x401100C5, @@ -74,7 +74,7 @@ enum { #define CPU_POWERPC_440 CPU_POWERPC_440GXf /* PowerPC 440 cores */ CPU_POWERPC_440_XILINX =3D 0x7ff21910, - /* PowerPC 440 microcontrolers */ + /* PowerPC 440 microcontrollers */ CPU_POWERPC_440EPa =3D 0x42221850, CPU_POWERPC_440EPb =3D 0x422218D3, CPU_POWERPC_440GPb =3D 0x40120440, diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 173e4c351a..d703a5f3c6 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -428,7 +428,7 @@ FIELD(MSR, LE, MSR_LE, 1) =20 /* PMU bits */ #define MMCR0_FC PPC_BIT(32) /* Freeze Counters */ -#define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Ocurred */ +#define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Occurred */ #define MMCR0_PMAE PPC_BIT(37) /* Perf Monitor Alert Enable */ #define MMCR0_EBE PPC_BIT(43) /* Perf Monitor EBB Enable */ #define MMCR0_FCECE PPC_BIT(38) /* FC on Enabled Cond or Event */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 7ab5ee92d9..c62bf0e437 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5347,7 +5347,7 @@ static void register_970_lpar_sprs(CPUPPCState *env) static void register_power5p_lpar_sprs(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) - /* Logical partitionning */ + /* Logical partitioning */ spr_register_kvm_hv(env, SPR_LPCR, "LPCR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, @@ -5760,7 +5760,7 @@ static void register_power9_mmu_sprs(CPUPPCState *env) static void register_power10_hash_sprs(CPUPPCState *env) { /* - * it's the OS responsability to generate a random value for the regis= ters + * it's the OS responsibility to generate a random value for the regis= ters * in each process' context. So, initialize it with 0 here. */ uint64_t hashkeyr_initial_value =3D 0, hashpkeyr_initial_value =3D 0; diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 72ec2be92e..99099cb1f6 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -455,7 +455,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp) =20 /* * new interrupt handler msr preserves existing ME unless - * explicitly overriden. + * explicitly overridden. */ new_msr =3D env->msr & (((target_ulong)1 << MSR_ME)); =20 @@ -578,7 +578,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp) =20 /* * new interrupt handler msr preserves existing ME unless - * explicitly overriden + * explicitly overridden */ new_msr =3D env->msr & ((target_ulong)1 << MSR_ME); =20 @@ -739,7 +739,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) =20 /* * new interrupt handler msr preserves existing ME unless - * explicitly overriden + * explicitly overridden */ new_msr =3D env->msr & ((target_ulong)1 << MSR_ME); =20 @@ -911,7 +911,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp) =20 /* * new interrupt handler msr preserves existing ME unless - * explicitly overriden + * explicitly overridden */ new_msr =3D env->msr & ((target_ulong)1 << MSR_ME); =20 @@ -1075,7 +1075,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int e= xcp) =20 /* * new interrupt handler msr preserves existing ME unless - * explicitly overriden + * explicitly overridden */ new_msr =3D env->msr & ((target_ulong)1 << MSR_ME); =20 @@ -1288,7 +1288,7 @@ static bool books_vhyp_handles_hcall(PowerPCCPU *cpu) /* * When running a nested KVM HV guest under vhyp, HV exceptions are not * delivered to the guest (because there is no concept of HV support), but - * rather they are sent tothe vhyp to exit from the L2 back to the L1 and + * rather they are sent to the vhyp to exit from the L2 back to the L1 and * return from the H_ENTER_NESTED hypercall. */ static bool books_vhyp_handles_hv_excp(PowerPCCPU *cpu) @@ -1377,7 +1377,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) =20 /* * new interrupt handler msr preserves existing HV and ME unless - * explicitly overriden + * explicitly overridden */ new_msr =3D env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); =20 diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.= c.inc index c82feedaff..75513db894 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -16,7 +16,7 @@ * Checks whether the Group A SPR (MMCR0, MMCR2, MMCRA, and the * PMCs) has problem state read access. * - * Read acccess is granted for all PMCC values but 0b01, where a + * Read access is granted for all PMCC values but 0b01, where a * Facility Unavailable Interrupt will occur. */ static bool spr_groupA_read_allowed(DisasContext *ctx) @@ -33,7 +33,7 @@ static bool spr_groupA_read_allowed(DisasContext *ctx) * Checks whether the Group A SPR (MMCR0, MMCR2, MMCRA, and the * PMCs) has problem state write access. * - * Write acccess is granted for PMCC values 0b10 and 0b11. Userspace + * Write access is granted for PMCC values 0b10 and 0b11. Userspace * writing with PMCC 0b00 will generate a Hypervisor Emulation * Assistance Interrupt. Userspace writing with PMCC 0b01 will * generate a Facility Unavailable Interrupt. diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx= -impl.c.inc index 6d7669aabd..5cdf53a9df 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -119,7 +119,7 @@ static void gen_stve##name(DisasContext *ctx) = \ } =20 GEN_VR_LDX(lvx, 0x07, 0x03); -/* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ +/* As we don't emulate the cache, lvxl is strictly equivalent to lvx */ GEN_VR_LDX(lvxl, 0x07, 0x0B); =20 GEN_VR_LVE(bx, 0x07, 0x00, 1); @@ -127,7 +127,7 @@ GEN_VR_LVE(hx, 0x07, 0x01, 2); GEN_VR_LVE(wx, 0x07, 0x02, 4); =20 GEN_VR_STX(svx, 0x07, 0x07); -/* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ +/* As we don't emulate the cache, stvxl is strictly equivalent to stvx */ GEN_VR_STX(svxl, 0x07, 0x0F); =20 GEN_VR_STVE(bx, 0x07, 0x04, 1); @@ -1526,7 +1526,7 @@ static void gen_vprtyb_vec(unsigned vece, TCGv_vec t,= TCGv_vec b) { int i; TCGv_vec tmp =3D tcg_temp_new_vec_matching(b); - /* MO_32 is 2, so 2 iteractions for MO_32 and 3 for MO_64 */ + /* MO_32 is 2, so 2 iterations for MO_32 and 3 for MO_64 */ for (i =3D 0; i < vece; i++) { tcg_gen_shri_vec(vece, tmp, b, (4 << (vece - i))); tcg_gen_xor_vec(vece, b, tmp, b); --=20 2.39.2 From nobody Wed May 15 16:57:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694265322024689.1404844428511; Sat, 9 Sep 2023 06:15:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qexmd-0000iF-Rv; Sat, 09 Sep 2023 09:13:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qexm7-0000DI-HO; Sat, 09 Sep 2023 09:13:24 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qexlz-0005Jr-0V; Sat, 09 Sep 2023 09:13:22 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id E1FA12062D; Sat, 9 Sep 2023 16:13:51 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id AEB4E26E4D; Sat, 9 Sep 2023 16:13:00 +0300 (MSK) Received: (nullmailer pid 354717 invoked by uid 1000); Sat, 09 Sep 2023 13:13:00 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Michael Tokarev Subject: [PATCH 4/7] hw/net: spelling fixes Date: Sat, 9 Sep 2023 16:12:55 +0300 Message-Id: <20230909131258.354675-5-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230909131258.354675-1-mjt@tls.msk.ru> References: <20230909131258.354675-1-mjt@tls.msk.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1694265323086100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Tokarev Reviewed-by: Peter Maydell --- hw/net/cadence_gem.c | 10 +++++----- hw/net/dp8393x.c | 2 +- hw/net/e1000_regs.h | 2 +- hw/net/e1000x_regs.h | 2 +- hw/net/fsl_etsec/rings.c | 2 +- hw/net/igb_regs.h | 4 ++-- hw/net/mcf_fec.c | 2 +- hw/net/rocker/rocker_fp.c | 2 +- hw/net/rtl8139.c | 2 +- hw/net/smc91c111.c | 2 +- hw/net/sungem.c | 2 +- hw/net/sunhme.c | 2 +- hw/net/virtio-net.c | 6 +++--- hw/net/vmxnet3.c | 2 +- hw/net/vmxnet3.h | 2 +- 15 files changed, 22 insertions(+), 22 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 42ea2411a2..f445d8bb5e 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -81,8 +81,8 @@ #define GEM_IPGSTRETCH (0x000000BC / 4) /* IPG Stretch reg */ #define GEM_SVLAN (0x000000C0 / 4) /* Stacked VLAN reg */ #define GEM_MODID (0x000000FC / 4) /* Module ID reg */ -#define GEM_OCTTXLO (0x00000100 / 4) /* Octects transmitted Low reg = */ -#define GEM_OCTTXHI (0x00000104 / 4) /* Octects transmitted High reg= */ +#define GEM_OCTTXLO (0x00000100 / 4) /* Octets transmitted Low reg */ +#define GEM_OCTTXHI (0x00000104 / 4) /* Octets transmitted High reg = */ #define GEM_TXCNT (0x00000108 / 4) /* Error-free Frames transmitte= d */ #define GEM_TXBCNT (0x0000010C / 4) /* Error-free Broadcast Frames = */ #define GEM_TXMCNT (0x00000110 / 4) /* Error-free Multicast Frame */ @@ -101,8 +101,8 @@ #define GEM_LATECOLLCNT (0x00000144 / 4) /* Late Collision Frames */ #define GEM_DEFERTXCNT (0x00000148 / 4) /* Deferred Transmission Frames= */ #define GEM_CSENSECNT (0x0000014C / 4) /* Carrier Sense Error Counter = */ -#define GEM_OCTRXLO (0x00000150 / 4) /* Octects Received register Lo= w */ -#define GEM_OCTRXHI (0x00000154 / 4) /* Octects Received register Hi= gh */ +#define GEM_OCTRXLO (0x00000150 / 4) /* Octets Received register Low= */ +#define GEM_OCTRXHI (0x00000154 / 4) /* Octets Received register Hig= h */ #define GEM_RXCNT (0x00000158 / 4) /* Error-free Frames Received */ #define GEM_RXBROADCNT (0x0000015C / 4) /* Error-free Broadcast Frames = RX */ #define GEM_RXMULTICNT (0x00000160 / 4) /* Error-free Multicast Frames = RX */ @@ -954,7 +954,7 @@ static ssize_t gem_receive(NetClientState *nc, const ui= nt8_t *buf, size_t size) /* Is this destination MAC address "for us" ? */ maf =3D gem_mac_address_filter(s, buf); if (maf =3D=3D GEM_RX_REJECT) { - return size; /* no, drop siliently b/c it's not an error */ + return size; /* no, drop silently b/c it's not an error */ } =20 /* Discard packets with receive length error enabled ? */ diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index a596f7fbc6..c6f5fb7dce 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -551,7 +551,7 @@ static uint64_t dp8393x_read(void *opaque, hwaddr addr,= unsigned int size) val =3D s->cam[s->regs[SONIC_CEP] & 0xf][SONIC_CAP0 - reg]; } break; - /* All other registers have no special contraints */ + /* All other registers have no special constraints */ default: val =3D s->regs[reg]; } diff --git a/hw/net/e1000_regs.h b/hw/net/e1000_regs.h index 8a4ce82034..39f4882510 100644 --- a/hw/net/e1000_regs.h +++ b/hw/net/e1000_regs.h @@ -130,7 +130,7 @@ =20 #define E1000_GCR2 0x05B64 /* 3GIO Control Register 2 */ #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ -#define E1000_HICR 0x08F00 /* Host Inteface Control */ +#define E1000_HICR 0x08F00 /* Host Interface Control */ =20 #define E1000_RXMTRL 0x0B634 /* Time sync Rx EtherType and Msg Type - = RW */ #define E1000_RXUDP 0x0B638 /* Time Sync Rx UDP Port - RW */ diff --git a/hw/net/e1000x_regs.h b/hw/net/e1000x_regs.h index 13760c66d3..cd896fc0ca 100644 --- a/hw/net/e1000x_regs.h +++ b/hw/net/e1000x_regs.h @@ -839,7 +839,7 @@ union e1000_rx_desc_packet_split { #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ -#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */ +#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ diff --git a/hw/net/fsl_etsec/rings.c b/hw/net/fsl_etsec/rings.c index 788463f1b6..e6c3bf5361 100644 --- a/hw/net/fsl_etsec/rings.c +++ b/hw/net/fsl_etsec/rings.c @@ -365,7 +365,7 @@ void etsec_walk_tx_ring(eTSEC *etsec, int ring_nbr) } while (TRUE); =20 /* Save the Buffer Descriptor Pointers to last bd that was not - * succesfully closed */ + * successfully closed */ etsec->regs[TBPTR0 + ring_nbr].value =3D bd_addr; =20 /* Set transmit halt THLTx */ diff --git a/hw/net/igb_regs.h b/hw/net/igb_regs.h index 82ff195dfc..d6e0405d0a 100644 --- a/hw/net/igb_regs.h +++ b/hw/net/igb_regs.h @@ -364,7 +364,7 @@ union e1000_adv_rx_desc { /* Indicates that VF is still clear to send requests */ #define E1000_VT_MSGTYPE_CTS 0x20000000 #define E1000_VT_MSGINFO_SHIFT 16 -/* bits 23:16 are used for exra info for certain messages */ +/* bits 23:16 are used for extra info for certain messages */ #define E1000_VT_MSGINFO_MASK (0xFF << E1000_VT_MSGINFO_SHIFT) =20 #define E1000_VF_RESET 0x01 /* VF requests reset */ @@ -490,7 +490,7 @@ union e1000_adv_rx_desc { #define E1000_VF_MBX_INIT_DELAY 500 /* usec delay between retries */ =20 #define E1000_VT_MSGINFO_SHIFT 16 -/* bits 23:16 are used for exra info for certain messages */ +/* bits 23:16 are used for extra info for certain messages */ #define E1000_VT_MSGINFO_MASK (0xFF << E1000_VT_MSGINFO_SHIFT) =20 #define E1000_VF_RESET 0x01 /* VF requests reset */ diff --git a/hw/net/mcf_fec.c b/hw/net/mcf_fec.c index 8aa27bd322..ec3ddf520a 100644 --- a/hw/net/mcf_fec.c +++ b/hw/net/mcf_fec.c @@ -571,7 +571,7 @@ static ssize_t mcf_fec_receive(NetClientState *nc, cons= t uint8_t *buf, size_t si size +=3D 4; crc =3D cpu_to_be32(crc32(~0, buf, size)); crc_ptr =3D (uint8_t *)&crc; - /* Huge frames are truncted. */ + /* Huge frames are truncated. */ if (size > FEC_MAX_FRAME_SIZE) { size =3D FEC_MAX_FRAME_SIZE; flags |=3D FEC_BD_TR | FEC_BD_LG; diff --git a/hw/net/rocker/rocker_fp.c b/hw/net/rocker/rocker_fp.c index cbeed65bd5..9afd0c5e3f 100644 --- a/hw/net/rocker/rocker_fp.c +++ b/hw/net/rocker/rocker_fp.c @@ -134,7 +134,7 @@ static ssize_t fp_port_receive_iov(NetClientState *nc, = const struct iovec *iov, FpPort *port =3D qemu_get_nic_opaque(nc); =20 /* If the port is disabled, we want to drop this pkt - * now rather than queing it for later. We don't want + * now rather than queueing it for later. We don't want * any stale pkts getting into the device when the port * transitions to enabled. */ diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c index b4df75b2c9..4525fda383 100644 --- a/hw/net/rtl8139.c +++ b/hw/net/rtl8139.c @@ -100,7 +100,7 @@ enum RTL8139_registers { MAC0 =3D 0, /* Ethernet hardware address. */ MAR0 =3D 8, /* Multicast filter. */ TxStatus0 =3D 0x10,/* Transmit status (Four 32bit registers). C mode o= nly */ - /* Dump Tally Conter control register(64bit). C+ mode= only */ + /* Dump Tally Counter control register(64bit). C+ mod= e only */ TxAddr0 =3D 0x20, /* Tx descriptors (also four 32bit). */ RxBuf =3D 0x30, ChipCmd =3D 0x37, diff --git a/hw/net/smc91c111.c b/hw/net/smc91c111.c index ad778cd8fc..ddbceda967 100644 --- a/hw/net/smc91c111.c +++ b/hw/net/smc91c111.c @@ -361,7 +361,7 @@ static void smc91c111_writeb(void *opaque, hwaddr offse= t, case 4: case 5: case 6: case 7: case 8: case 9: /* IA */ /* Not implemented. */ return; - case 10: /* Genral Purpose */ + case 10: /* General Purpose */ SET_LOW(gpr, value); return; case 11: diff --git a/hw/net/sungem.c b/hw/net/sungem.c index 510b370e5f..c2e2c90668 100644 --- a/hw/net/sungem.c +++ b/hw/net/sungem.c @@ -1228,7 +1228,7 @@ static void sungem_mmio_mif_write(void *opaque, hwadd= r addr, uint64_t val, case MIF_SMACHINE: return; /* No actual write */ case MIF_CFG: - /* Maintain the RO MDI bits to advertize an MDIO PHY on MDI0 */ + /* Maintain the RO MDI bits to advertise an MDIO PHY on MDI0 */ val &=3D ~MIF_CFG_MDI1; val |=3D MIF_CFG_MDI0; break; diff --git a/hw/net/sunhme.c b/hw/net/sunhme.c index 391d26fb82..64d4ea5850 100644 --- a/hw/net/sunhme.c +++ b/hw/net/sunhme.c @@ -901,7 +901,7 @@ static void sunhme_reset(DeviceState *ds) /* Configure internal transceiver */ s->mifregs[HME_MIFI_CFG >> 2] |=3D HME_MIF_CFG_MDI0; =20 - /* Advetise auto, 100Mbps FD */ + /* Advertise auto, 100Mbps FD */ s->miiregs[MII_ANAR] =3D MII_ANAR_TXFD; s->miiregs[MII_BMSR] =3D MII_BMSR_AUTONEG | MII_BMSR_100TX_FD | MII_BMSR_AN_COMP; diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c index 7102ec4817..57a359b7a5 100644 --- a/hw/net/virtio-net.c +++ b/hw/net/virtio-net.c @@ -1307,7 +1307,7 @@ static void virtio_net_detach_epbf_rss(VirtIONet *n) static bool virtio_net_load_ebpf(VirtIONet *n) { if (!virtio_net_attach_ebpf_to_backend(n->nic, -1)) { - /* backend does't support steering ebpf */ + /* backend doesn't support steering ebpf */ return false; } =20 @@ -2046,7 +2046,7 @@ static void virtio_net_rsc_extract_unit6(VirtioNetRsc= Chain *chain, + sizeof(struct ip6_header)); unit->tcp_hdrlen =3D (htons(unit->tcp->th_offset_flags) & 0xF000) >> 1= 0; =20 - /* There is a difference between payload lenght in ipv4 and v6, + /* There is a difference between payload length in ipv4 and v6, ip header is excluded in ipv6 */ unit->payload =3D htons(*unit->ip_plen) - unit->tcp_hdrlen; } @@ -3795,7 +3795,7 @@ static void virtio_net_instance_init(Object *obj) =20 /* * The default config_size is sizeof(struct virtio_net_config). - * Can be overriden with virtio_net_set_config_size. + * Can be overridden with virtio_net_set_config_size. */ n->config_size =3D sizeof(struct virtio_net_config); device_add_bootindex_property(obj, &n->nic_conf.bootindex, diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c index 3fb108751a..7af5f6c821 100644 --- a/hw/net/vmxnet3.c +++ b/hw/net/vmxnet3.c @@ -1887,7 +1887,7 @@ vmxnet3_io_bar1_read(void *opaque, hwaddr addr, unsig= ned size) break; =20 default: - VMW_CBPRN("Unknow read BAR1[%" PRIx64 "], %d bytes", addr, siz= e); + VMW_CBPRN("Unknown read BAR1[%" PRIx64 "], %d bytes", addr, si= ze); break; } =20 diff --git a/hw/net/vmxnet3.h b/hw/net/vmxnet3.h index bf4f6de74a..f9283f9e7b 100644 --- a/hw/net/vmxnet3.h +++ b/hw/net/vmxnet3.h @@ -733,7 +733,7 @@ struct Vmxnet3_TxQueueDesc { struct Vmxnet3_RxQueueDesc { struct Vmxnet3_RxQueueCtrl ctrl; struct Vmxnet3_RxQueueConf conf; - /* Driver read after a GET commad */ + /* Driver read after a GET command */ struct Vmxnet3_QueueStatus status; struct UPT1_RxStats stats; u8 __pad[88]; /* 128 aligned */ --=20 2.39.2 From nobody Wed May 15 16:57:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694265500700134.16673687005493; Sat, 9 Sep 2023 06:18:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qexmr-0001DZ-1o; Sat, 09 Sep 2023 09:14:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qexm9-0000IF-Cm; Sat, 09 Sep 2023 09:13:26 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qexm3-0005K4-6W; Sat, 09 Sep 2023 09:13:24 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 1C8EF2062E; Sat, 9 Sep 2023 16:13:52 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id D984F26E4E; Sat, 9 Sep 2023 16:13:00 +0300 (MSK) Received: (nullmailer pid 354720 invoked by uid 1000); Sat, 09 Sep 2023 13:13:00 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Michael Tokarev Subject: [PATCH 5/7] hw/pci: spelling fixes Date: Sat, 9 Sep 2023 16:12:56 +0300 Message-Id: <20230909131258.354675-6-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230909131258.354675-1-mjt@tls.msk.ru> References: <20230909131258.354675-1-mjt@tls.msk.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1694265501019100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Tokarev Reviewed-by: Peter Maydell --- hw/pci-bridge/cxl_downstream.c | 2 +- hw/pci-bridge/pci_expander_bridge.c | 2 +- hw/pci-host/bonito.c | 2 +- hw/pci-host/designware.c | 4 ++-- hw/pci-host/dino.c | 2 +- hw/pci-host/gpex-acpi.c | 2 +- hw/pci-host/gt64120.c | 4 ++-- hw/pci-host/pnv_phb.c | 2 +- hw/pci-host/pnv_phb3.c | 2 +- hw/pci-host/pnv_phb3_msi.c | 2 +- hw/pci-host/pnv_phb4.c | 6 +++--- hw/pci/pcie_aer.c | 2 +- hw/pci/shpc.c | 2 +- 13 files changed, 17 insertions(+), 17 deletions(-) diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index 54f507318f..5a2b749c8e 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -42,7 +42,7 @@ static void latch_registers(CXLDownstreamPort *dsp) CXL2_DOWNSTREAM_PORT); } =20 -/* TODO: Look at sharing this code acorss all CXL port types */ +/* TODO: Look at sharing this code across all CXL port types */ static void cxl_dsp_dvsec_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len) { diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index 613857b601..535889f7c2 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -263,7 +263,7 @@ static int pxb_map_irq_fn(PCIDevice *pci_dev, int pin) =20 /* * First carry out normal swizzle to handle - * multple root ports on a pxb instance. + * multiple root ports on a pxb instance. */ pin =3D pci_swizzle_map_irq_fn(pci_dev, pin); =20 diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c index 4701481b9b..ee6cb85e97 100644 --- a/hw/pci-host/bonito.c +++ b/hw/pci-host/bonito.c @@ -62,7 +62,7 @@ #define DPRINTF(fmt, ...) #endif =20 -/* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/ +/* from linux source code. include/asm-mips/mips-boards/bonito64.h*/ #define BONITO_BOOT_BASE 0x1fc00000 #define BONITO_BOOT_SIZE 0x00100000 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE + BONITO_BOOT_SIZE - 1) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 388d252ee2..e325514372 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -488,7 +488,7 @@ static void designware_pcie_root_realize(PCIDevice *dev= , Error **errp) =20 /* * If no inbound iATU windows are configured, HW defaults to - * letting inbound TLPs to pass in. We emulate that by exlicitly + * letting inbound TLPs to pass in. We emulate that by explicitly * configuring first inbound window to cover all of target's * address space. * @@ -503,7 +503,7 @@ static void designware_pcie_root_realize(PCIDevice *dev= , Error **errp) &designware_pci_host_msi_ops, root, "pcie-msi", 0x4); /* - * We initially place MSI interrupt I/O region a adress 0 and + * We initially place MSI interrupt I/O region a address 0 and * disable it. It'll be later moved to correct offset and enabled * in designware_pcie_root_update_msi_mapping() as a part of * initialization done by guest OS diff --git a/hw/pci-host/dino.c b/hw/pci-host/dino.c index e8eaebca54..82503229fa 100644 --- a/hw/pci-host/dino.c +++ b/hw/pci-host/dino.c @@ -1,5 +1,5 @@ /* - * HP-PARISC Dino PCI chipset emulation, as in B160L and similiar machines + * HP-PARISC Dino PCI chipset emulation, as in B160L and similar machines * * (C) 2017-2019 by Helge Deller * diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 7c7316bc96..87ba074254 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -177,7 +177,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *= cfg) acpi_dsdt_add_pci_route_table(dev, cfg->irq); =20 /* - * Resources defined for PXBs are composed by the folling part= s: + * Resources defined for PXBs are composed by the following pa= rts: * 1. The resources the pci-brige/pcie-root-port need. * 2. The resources the devices behind pxb need. */ diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index 82c15edb46..143bf053d7 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -331,9 +331,9 @@ static void gt64120_update_pci_cfgdata_mapping(GT64120S= tate *s) /* * The setting of the MByteSwap bit and MWordSwap bit in the PCI Inter= nal * Command Register determines how data transactions from the CPU to/f= rom - * PCI are handled along with the setting of the Endianess bit in the = CPU + * PCI are handled along with the setting of the Endianness bit in the= CPU * Configuration Register. See: - * - Table 16: 32-bit PCI Transaction Endianess + * - Table 16: 32-bit PCI Transaction Endianness * - Table 158: PCI_0 Command, Offset: 0xc00 */ =20 diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c index 82332d7a05..157c00782c 100644 --- a/hw/pci-host/pnv_phb.c +++ b/hw/pci-host/pnv_phb.c @@ -25,7 +25,7 @@ * state associated with the child has an id, use it as QOM id. * Otherwise use object_typename[index] as QOM id. * - * This helper does both operations at the same time because seting + * This helper does both operations at the same time because setting * a new QOM child will erase the bus parent of the device. This happens * because object_unparent() will call object_property_del_child(), * which in turn calls the property release callback prop->release if diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index 7a21497cf8..c5e58f4086 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -757,7 +757,7 @@ static void pnv_phb3_translate_tve(PnvPhb3DMASpace *ds,= hwaddr addr, * We only support non-translate in top window. * * TODO: Venice/Murano support it on bottom window above 4G and - * Naples suports it on everything + * Naples supports it on everything */ if (!(tve & PPC_BIT(51))) { phb3_error(phb, "xlate for invalid non-translate TVE"); diff --git a/hw/pci-host/pnv_phb3_msi.c b/hw/pci-host/pnv_phb3_msi.c index 41e63b066f..dc8d8637f2 100644 --- a/hw/pci-host/pnv_phb3_msi.c +++ b/hw/pci-host/pnv_phb3_msi.c @@ -281,7 +281,7 @@ static void phb3_msi_instance_init(Object *obj) object_property_allow_set_link, OBJ_PROP_LINK_STRONG); =20 - /* Will be overriden later */ + /* Will be overridden later */ ics->offset =3D 0; } =20 diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 6232cbeee1..29cb11a5d9 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -207,7 +207,7 @@ static void pnv_phb4_check_mbt(PnvPHB4 *phb, uint32_t i= ndex) start =3D base | (phb->regs[PHB_M64_UPPER_BITS >> 3]); } =20 - /* TODO: Figure out how to implemet/decode AOMASK */ + /* TODO: Figure out how to implement/decode AOMASK */ =20 /* Check if it matches an enabled MMIO region in the PEC stack */ if (memory_region_is_mapped(&phb->mmbar0) && @@ -391,7 +391,7 @@ static void pnv_phb4_ioda_write(PnvPHB4 *phb, uint64_t = val) case IODA3_TBL_MBT: *tptr =3D val; =20 - /* Copy accross the valid bit to the other half */ + /* Copy across the valid bit to the other half */ phb->ioda_MBT[idx ^ 1] &=3D 0x7fffffffffffffffull; phb->ioda_MBT[idx ^ 1] |=3D 0x8000000000000000ull & val; =20 @@ -1408,7 +1408,7 @@ static void pnv_phb4_msi_write(void *opaque, hwaddr a= ddr, return; } =20 - /* TODO: check PE/MSI assignement */ + /* TODO: check PE/MSI assignment */ =20 qemu_irq_pulse(phb->qirqs[src]); } diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c index 374d593ead..b68c7ecb49 100644 --- a/hw/pci/pcie_aer.c +++ b/hw/pci/pcie_aer.c @@ -324,7 +324,7 @@ static void pcie_aer_msg_root_port(PCIDevice *dev, cons= t PCIEAERMsg *msg) * it isn't implemented in qemu right now. * So just discard the error for now. * OS which cares of aer would receive errors via - * native aer mechanims, so this wouldn't matter. + * native aer mechanisms, so this wouldn't matter. */ } =20 diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c index e7bc7192f1..df7f370111 100644 --- a/hw/pci/shpc.c +++ b/hw/pci/shpc.c @@ -615,7 +615,7 @@ int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegi= on *bar, } if (nslots > SHPC_MAX_SLOTS || SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) { - /* TODO: report an error mesage that makes sense. */ + /* TODO: report an error message that makes sense. */ return -EINVAL; } shpc->nslots =3D nslots; --=20 2.39.2 From nobody Wed May 15 16:57:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1694265497650332.93527794989814; Sat, 9 Sep 2023 06:18:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qexmp-0001Bj-PD; Sat, 09 Sep 2023 09:14:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qexmD-0000Lc-He; Sat, 09 Sep 2023 09:13:31 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qexm9-0005L8-7i; Sat, 09 Sep 2023 09:13:28 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 411542062F; Sat, 9 Sep 2023 16:13:52 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 1459E26E4F; Sat, 9 Sep 2023 16:13:01 +0300 (MSK) Received: (nullmailer pid 354723 invoked by uid 1000); Sat, 09 Sep 2023 13:13:00 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Michael Tokarev Subject: [PATCH 6/7] hw/tpm: spelling fixes Date: Sat, 9 Sep 2023 16:12:57 +0300 Message-Id: <20230909131258.354675-7-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230909131258.354675-1-mjt@tls.msk.ru> References: <20230909131258.354675-1-mjt@tls.msk.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1694265499385100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Michael Tokarev Reviewed-by: Stefan Berger --- hw/tpm/tpm_tis.h | 2 +- hw/tpm/tpm_tis_common.c | 2 +- hw/tpm/tpm_tis_i2c.c | 4 ++-- hw/tpm/tpm_tis_isa.c | 2 +- hw/tpm/tpm_tis_sysbus.c | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/tpm/tpm_tis.h b/hw/tpm/tpm_tis.h index 6f29a508dd..6f14896b97 100644 --- a/hw/tpm/tpm_tis.h +++ b/hw/tpm/tpm_tis.h @@ -19,7 +19,7 @@ * specification. * * TPM TIS for TPM 2 implementation following TCG PC Client Platform - * TPM Profile (PTP) Specification, Familiy 2.0, Revision 00.43 + * TPM Profile (PTP) Specification, Family 2.0, Revision 00.43 */ #ifndef TPM_TPM_TIS_H #define TPM_TPM_TIS_H diff --git a/hw/tpm/tpm_tis_common.c b/hw/tpm/tpm_tis_common.c index c07c179dbc..279ce436b5 100644 --- a/hw/tpm/tpm_tis_common.c +++ b/hw/tpm/tpm_tis_common.c @@ -20,7 +20,7 @@ * specification. * * TPM TIS for TPM 2 implementation following TCG PC Client Platform - * TPM Profile (PTP) Specification, Familiy 2.0, Revision 00.43 + * TPM Profile (PTP) Specification, Family 2.0, Revision 00.43 */ #include "qemu/osdep.h" #include "hw/irq.h" diff --git a/hw/tpm/tpm_tis_i2c.c b/hw/tpm/tpm_tis_i2c.c index b695fd3a46..4ecea7fa3e 100644 --- a/hw/tpm/tpm_tis_i2c.c +++ b/hw/tpm/tpm_tis_i2c.c @@ -13,7 +13,7 @@ * Family 2.0, Level 00, Revision 1.00 * * TPM TIS for TPM 2 implementation following TCG PC Client Platform - * TPM Profile (PTP) Specification, Familiy 2.0, Revision 00.43 + * TPM Profile (PTP) Specification, Family 2.0, Revision 00.43 * */ =20 @@ -507,7 +507,7 @@ static void tpm_tis_i2c_realizefn(DeviceState *dev, Err= or **errp) } =20 /* - * Get the backend pointer. It is not initialized propery during + * Get the backend pointer. It is not initialized properly during * device_class_set_props */ s->be_driver =3D qemu_find_tpm_be("tpm0"); diff --git a/hw/tpm/tpm_tis_isa.c b/hw/tpm/tpm_tis_isa.c index 91e3792248..0367401586 100644 --- a/hw/tpm/tpm_tis_isa.c +++ b/hw/tpm/tpm_tis_isa.c @@ -19,7 +19,7 @@ * specification. * * TPM TIS for TPM 2 implementation following TCG PC Client Platform - * TPM Profile (PTP) Specification, Familiy 2.0, Revision 00.43 + * TPM Profile (PTP) Specification, Family 2.0, Revision 00.43 */ =20 #include "qemu/osdep.h" diff --git a/hw/tpm/tpm_tis_sysbus.c b/hw/tpm/tpm_tis_sysbus.c index 6724b3d4f6..2fc550f119 100644 --- a/hw/tpm/tpm_tis_sysbus.c +++ b/hw/tpm/tpm_tis_sysbus.c @@ -19,7 +19,7 @@ * specification. * * TPM TIS for TPM 2 implementation following TCG PC Client Platform - * TPM Profile (PTP) Specification, Familiy 2.0, Revision 00.43 + * TPM Profile (PTP) Specification, Family 2.0, Revision 00.43 */ =20 #include "qemu/osdep.h" --=20 2.39.2 From nobody Wed May 15 16:57:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Signed-off-by: Michael Tokarev Reviewed-by: Peter Maydell --- hw/acpi/aml-build.c | 6 +++--- hw/acpi/hmat.c | 2 +- hw/acpi/nvdimm.c | 2 +- hw/block/hd-geometry.c | 4 ++-- hw/block/pflash_cfi01.c | 2 +- hw/char/cadence_uart.c | 2 +- hw/char/imx_serial.c | 2 +- hw/char/serial.c | 2 +- hw/core/generic-loader.c | 4 ++-- hw/core/machine.c | 2 +- hw/core/qdev-properties-system.c | 2 +- hw/cpu/a15mpcore.c | 2 +- hw/cxl/cxl-events.c | 2 +- hw/cxl/cxl-mailbox-utils.c | 4 ++-- hw/dma/omap_dma.c | 4 ++-- hw/input/hid.c | 2 +- hw/input/tsc2005.c | 16 ++++++++-------- hw/intc/loongarch_extioi.c | 2 +- hw/intc/loongson_liointc.c | 2 +- hw/intc/omap_intc.c | 2 +- hw/intc/pnv_xive.c | 2 +- hw/intc/spapr_xive.c | 2 +- hw/intc/spapr_xive_kvm.c | 6 +++--- hw/intc/xive.c | 2 +- hw/intc/xive2.c | 6 +++--- hw/ipmi/ipmi_bmc_extern.c | 2 +- hw/mem/cxl_type3.c | 6 +++--- hw/misc/imx7_ccm.c | 2 +- hw/misc/mac_via.c | 2 +- hw/misc/stm32f2xx_syscfg.c | 4 ++-- hw/misc/trace-events | 2 +- hw/misc/zynq_slcr.c | 2 +- hw/nvme/ctrl.c | 6 +++--- hw/nvram/eeprom_at24c.c | 2 +- hw/nvram/fw_cfg.c | 2 +- hw/rtc/exynos4210_rtc.c | 2 +- hw/rx/rx62n.c | 2 +- hw/scsi/lsi53c895a.c | 2 +- hw/scsi/mfi.h | 2 +- hw/sh4/sh7750_regs.h | 26 +++++++++++++------------- hw/smbios/smbios.c | 2 +- hw/ssi/xilinx_spips.c | 6 +++--- hw/ssi/xlnx-versal-ospi.c | 2 +- hw/timer/etraxfs_timer.c | 2 +- hw/timer/renesas_tmr.c | 2 +- hw/virtio/virtio-crypto.c | 4 ++-- hw/virtio/virtio-mem.c | 2 +- hw/virtio/virtio.c | 2 +- 48 files changed, 85 insertions(+), 85 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index ea331a20d1..af66bde0f5 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -312,7 +312,7 @@ build_prepend_package_length(GArray *package, unsigned = length, bool incl_self) /* * PkgLength is the length of the inclusive length of the data * and PkgLength's length itself when used for terms with - * explitit length. + * explicit length. */ length +=3D length_bytes; } @@ -680,7 +680,7 @@ Aml *aml_store(Aml *val, Aml *target) * "Op Operand Operand Target" * pattern. * - * Returns: The newly allocated and composed according to patter Aml objec= t. + * Returns: The newly allocated and composed according to pattern Aml obje= ct. */ static Aml * build_opcode_2arg_dst(uint8_t op, Aml *arg1, Aml *arg2, Aml *dst) @@ -2159,7 +2159,7 @@ void build_fadt(GArray *tbl, BIOSLinker *linker, cons= t AcpiFadtData *f, /* FADT Minor Version */ build_append_int_noprefix(tbl, f->minor_ver, 1); } else { - build_append_int_noprefix(tbl, 0, 3); /* Reserved upto ACPI 5.0 */ + build_append_int_noprefix(tbl, 0, 3); /* Reserved up to ACPI 5.0 */ } build_append_int_noprefix(tbl, 0, 8); /* X_FIRMWARE_CTRL */ =20 diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c index 3a6d51282a..2d5e199ba9 100644 --- a/hw/acpi/hmat.c +++ b/hw/acpi/hmat.c @@ -82,7 +82,7 @@ static void build_hmat_lb(GArray *table_data, HMAT_LB_Inf= o *hmat_lb, uint32_t base; /* Length in bytes for entire structure */ uint32_t lb_length - =3D 32 /* Table length upto and including Entry Base Unit */ + =3D 32 /* Table length up to and including Entry Base Unit */ + 4 * num_initiator /* Initiator Proximity Domain List */ + 4 * num_target /* Target Proximity Domain List */ + 2 * num_initiator * num_target; /* Latency or Bandwidth Entries = */ diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index a3b25a92f3..fe03ce87e0 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -1097,7 +1097,7 @@ static void nvdimm_build_common_dsm(Aml *dev, * be treated as an integer. Moreover, the integer size depends on * DSDT tables revision number. If revision number is < 2, integer * size is 32 bits, otherwise it is 64 bits. - * Because of this CreateField() canot be used if RLEN < Integer Size. + * Because of this CreateField() cannot be used if RLEN < Integer Size. * * Also please note that APCI ASL operator SizeOf() doesn't support * Integer and there isn't any other way to figure out the Integer diff --git a/hw/block/hd-geometry.c b/hw/block/hd-geometry.c index dae13ab14d..2b0af4430f 100644 --- a/hw/block/hd-geometry.c +++ b/hw/block/hd-geometry.c @@ -50,7 +50,7 @@ struct partition { uint32_t nr_sects; /* nr of sectors in partition */ } QEMU_PACKED; =20 -/* try to guess the disk logical geometry from the MSDOS partition table. +/* try to guess the disk logical geometry from the MS-DOS partition table. Return 0 if OK, -1 if could not guess */ static int guess_disk_lchs(BlockBackend *blk, int *pcylinders, int *pheads, int *psectors) @@ -66,7 +66,7 @@ static int guess_disk_lchs(BlockBackend *blk, if (blk_pread(blk, 0, BDRV_SECTOR_SIZE, buf, 0) < 0) { return -1; } - /* test msdos magic */ + /* test MS-DOS magic */ if (buf[510] !=3D 0x55 || buf[511] !=3D 0xaa) { return -1; } diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 3c066e3405..62056b1d74 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -891,7 +891,7 @@ static Property pflash_cfi01_properties[] =3D { /* num-blocks is the number of blocks actually visible to the guest, * ie the total size of the device divided by the sector length. * If we're emulating flash devices wired in parallel the actual - * number of blocks per indvidual device will differ. + * number of blocks per individual device will differ. */ DEFINE_PROP_UINT32("num-blocks", PFlashCFI01, nb_blocs, 0), DEFINE_PROP_UINT64("sector-length", PFlashCFI01, sector_len, 0), diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index eff0304a18..a2ac062b1e 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -575,7 +575,7 @@ static int cadence_uart_pre_load(void *opaque) { CadenceUARTState *s =3D opaque; =20 - /* the frequency will be overriden if the refclk field is present */ + /* the frequency will be overridden if the refclk field is present */ clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK); return 0; } diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index 1b75a89588..377d1d9773 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -112,7 +112,7 @@ static void imx_serial_reset_at_boot(DeviceState *dev) imx_serial_reset(s); =20 /* - * enable the uart on boot, so messages from the linux decompresser + * enable the uart on boot, so messages from the linux decompressor * are visible. On real hardware this is done by the boot rom * before anything else is loaded. */ diff --git a/hw/char/serial.c b/hw/char/serial.c index f3094f860f..a32eb25f58 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -54,7 +54,7 @@ #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ #define UART_IIR_CTI 0x0C /* Character Timeout Indication */ =20 -#define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */ +#define UART_IIR_FENF 0x80 /* Fifo enabled, but not functioning */ #define UART_IIR_FE 0xC0 /* Fifo enabled */ =20 /* diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c index 4f4d77908d..d4b5c501d8 100644 --- a/hw/core/generic-loader.c +++ b/hw/core/generic-loader.c @@ -24,7 +24,7 @@ * callback that does the memory operations. =20 * This device allows the user to monkey patch memory. To be able to do - * this it needs a backend to manage the datas, the same as other + * this it needs a backend to manage the data, the same as other * memory-related devices. In this case as the backend is so trivial we * have merged it with the frontend instead of creating and maintaining a * separate backend. @@ -166,7 +166,7 @@ static void generic_loader_realize(DeviceState *dev, Er= ror **errp) } } =20 - /* Convert the data endiannes */ + /* Convert the data endianness */ if (s->data_be) { s->data =3D cpu_to_be64(s->data); } else { diff --git a/hw/core/machine.c b/hw/core/machine.c index da699cf4e1..73b9f6c661 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1417,7 +1417,7 @@ void machine_run_board_init(MachineState *machine, co= nst char *mem_path, Error * for (i =3D 0; machine_class->valid_cpu_types[i]; i++) { if (object_class_dynamic_cast(oc, machine_class->valid_cpu_types[i= ])) { - /* The user specificed CPU is in the valid field, we are + /* The user specified CPU is in the valid field, we are * good to go. */ break; diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-sys= tem.c index 6d5d43eda2..41b7e682c7 100644 --- a/hw/core/qdev-properties-system.c +++ b/hw/core/qdev-properties-system.c @@ -107,7 +107,7 @@ static void set_drive_helper(Object *obj, Visitor *v, c= onst char *name, } =20 if (*ptr) { - /* BlockBackend alread exists. So, we want to change attached node= */ + /* BlockBackend already exists. So, we want to change attached nod= e */ blk =3D *ptr; ctx =3D blk_get_aio_context(blk); bs =3D bdrv_lookup_bs(NULL, str, errp); diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 774ca9987a..bfd8aa5644 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -161,7 +161,7 @@ static void a15mp_priv_class_init(ObjectClass *klass, v= oid *data) =20 dc->realize =3D a15mp_priv_realize; device_class_set_props(dc, a15mp_priv_properties); - /* We currently have no savable state */ + /* We currently have no saveable state */ } =20 static const TypeInfo a15mp_priv_info =3D { diff --git a/hw/cxl/cxl-events.c b/hw/cxl/cxl-events.c index d161d57456..3ddd6369ad 100644 --- a/hw/cxl/cxl-events.c +++ b/hw/cxl/cxl-events.c @@ -197,7 +197,7 @@ CXLRetCode cxl_event_clear_records(CXLDeviceState *cxld= s, CXLClearEventPayload * =20 QEMU_LOCK_GUARD(&log->lock); /* - * Must itterate the queue twice. + * Must iterate the queue twice. * "The device shall verify the event record handles specified in the = input * payload are in temporal order. If the device detects an older event * record that will not be cleared when Clear Event Records is execute= d, diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 02f9b5a870..434ccc5f6e 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -39,7 +39,7 @@ * fill the output data into cmd->payload (overwriting what was there), * setting the length, and returning a valid return code. * - * XXX: The handler need not worry about endianess. The payload is read o= ut of + * XXX: The handler need not worry about endianness. The payload is read = out of * a register interface that already deals with it. */ =20 @@ -501,7 +501,7 @@ static CXLRetCode cmd_media_get_poison_list(struct cxl_= cmd *cmd, uint16_t out_pl_len; =20 query_start =3D ldq_le_p(&in->pa); - /* 64 byte alignemnt required */ + /* 64 byte alignment required */ if (query_start & 0x3f) { return CXL_MBOX_INVALID_INPUT; } diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c index c6e35ba4b8..77797a67b5 100644 --- a/hw/dma/omap_dma.c +++ b/hw/dma/omap_dma.c @@ -247,7 +247,7 @@ static void omap_dma_deactivate_channel(struct omap_dma= _s *s, return; } =20 - /* Don't deactive the channel if it is synchronized and the DMA reques= t is + /* Don't deactivate the channel if it is synchronized and the DMA requ= est is active */ if (ch->sync && ch->enable && (s->dma->drqbmp & (1ULL << ch->sync))) return; @@ -422,7 +422,7 @@ static void omap_dma_transfer_generic(struct soc_dma_ch= _s *dma) =20 if (ch->fs && ch->bs) { a->pck_element ++; - /* Check if a full packet has beed transferred. */ + /* Check if a full packet has been transferred. */ if (a->pck_element =3D=3D a->pck_elements) { a->pck_element =3D 0; =20 diff --git a/hw/input/hid.c b/hw/input/hid.c index e7ecebdf8f..a9c7dd1ce1 100644 --- a/hw/input/hid.c +++ b/hw/input/hid.c @@ -209,7 +209,7 @@ static void hid_pointer_sync(DeviceState *dev) prev->dz +=3D curr->dz; curr->dz =3D 0; } else { - /* prepate next (clear rel, copy abs + btns) */ + /* prepare next (clear rel, copy abs + btns) */ if (hs->kind =3D=3D HID_MOUSE) { next->xdx =3D 0; next->ydy =3D 0; diff --git a/hw/input/tsc2005.c b/hw/input/tsc2005.c index 555b677173..a4f23705b5 100644 --- a/hw/input/tsc2005.c +++ b/hw/input/tsc2005.c @@ -157,14 +157,14 @@ static uint16_t tsc2005_read(TSC2005State *s, int reg) s->reset =3D true; return ret; =20 - case 0x8: /* AUX high treshold */ + case 0x8: /* AUX high threshold */ return s->aux_thr[1]; - case 0x9: /* AUX low treshold */ + case 0x9: /* AUX low threshold */ return s->aux_thr[0]; =20 - case 0xa: /* TEMP high treshold */ + case 0xa: /* TEMP high threshold */ return s->temp_thr[1]; - case 0xb: /* TEMP low treshold */ + case 0xb: /* TEMP low threshold */ return s->temp_thr[0]; =20 case 0xc: /* CFR0 */ @@ -186,17 +186,17 @@ static uint16_t tsc2005_read(TSC2005State *s, int reg) static void tsc2005_write(TSC2005State *s, int reg, uint16_t data) { switch (reg) { - case 0x8: /* AUX high treshold */ + case 0x8: /* AUX high threshold */ s->aux_thr[1] =3D data; break; - case 0x9: /* AUX low treshold */ + case 0x9: /* AUX low threshold */ s->aux_thr[0] =3D data; break; =20 - case 0xa: /* TEMP high treshold */ + case 0xa: /* TEMP high threshold */ s->temp_thr[1] =3D data; break; - case 0xb: /* TEMP low treshold */ + case 0xb: /* TEMP low threshold */ s->temp_thr[0] =3D data; break; =20 diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c index af75460643..24fb3af8cc 100644 --- a/hw/intc/loongarch_extioi.c +++ b/hw/intc/loongarch_extioi.c @@ -191,7 +191,7 @@ static MemTxResult extioi_writew(void *opaque, hwaddr a= ddr, cpu =3D attrs.requester_id; old_data =3D s->coreisr[cpu][index]; s->coreisr[cpu][index] =3D old_data & ~val; - /* write 1 to clear interrrupt */ + /* write 1 to clear interrupt */ old_data &=3D val; irq =3D ctz32(old_data); while (irq !=3D 32) { diff --git a/hw/intc/loongson_liointc.c b/hw/intc/loongson_liointc.c index cc11b544cb..c10fb97a06 100644 --- a/hw/intc/loongson_liointc.c +++ b/hw/intc/loongson_liointc.c @@ -1,5 +1,5 @@ /* - * QEMU Loongson Local I/O interrupt controler. + * QEMU Loongson Local I/O interrupt controller. * * Copyright (c) 2020 Huacai Chen * Copyright (c) 2020 Jiaxun Yang diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c index 647bf324a8..435c47600f 100644 --- a/hw/intc/omap_intc.c +++ b/hw/intc/omap_intc.c @@ -68,7 +68,7 @@ static void omap_inth_sir_update(OMAPIntcState *s, int is= _fiq) p_intr =3D 255; =20 /* Find the interrupt line with the highest dynamic priority. - * Note: 0 denotes the hightest priority. + * Note: 0 denotes the highest priority. * If all interrupts have the same priority, the default order is IRQ_= N, * IRQ_N-1,...,IRQ_0. */ for (j =3D 0; j < s->nbanks; ++j) { diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 9b10e90519..0679398c45 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -988,7 +988,7 @@ static void pnv_xive_ic_reg_write(void *opaque, hwaddr = offset, */ case VC_SBC_CONFIG: /* Store EOI configuration */ /* - * Configure store EOI if required by firwmare (skiboot has removed + * Configure store EOI if required by firmware (skiboot has removed * support recently though) */ if (val & (VC_SBC_CONF_CPLX_CIST | VC_SBC_CONF_CIST_BOTH)) { diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 8bcab2846c..7f701d414b 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -27,7 +27,7 @@ #include "trace.h" =20 /* - * XIVE Virtualization Controller BAR and Thread Managment BAR that we + * XIVE Virtualization Controller BAR and Thread Management BAR that we * use for the ESB pages and the TIMA pages */ #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c index 61fe7bd2d3..5789062379 100644 --- a/hw/intc/spapr_xive_kvm.c +++ b/hw/intc/spapr_xive_kvm.c @@ -485,7 +485,7 @@ static int kvmppc_xive_get_queues(SpaprXive *xive, Erro= r **errp) * * Whenever the VM is stopped, the VM change handler sets the source * PQs to PENDING to stop the flow of events and to possibly catch a - * triggered interrupt occuring while the VM is stopped. The previous + * triggered interrupt occurring while the VM is stopped. The previous * state is saved in anticipation of a migration. The XIVE controller * is then synced through KVM to flush any in-flight event * notification and stabilize the EQs. @@ -551,7 +551,7 @@ static void kvmppc_xive_change_state_handler(void *opaq= ue, bool running, =20 /* * PQ is set to PENDING to possibly catch a triggered - * interrupt occuring while the VM is stopped (hotplug event + * interrupt occurring while the VM is stopped (hotplug event * for instance) . */ if (pq !=3D XIVE_ESB_OFF) { @@ -633,7 +633,7 @@ int kvmppc_xive_post_load(SpaprXive *xive, int version_= id) /* The KVM XIVE device should be in use */ assert(xive->fd !=3D -1); =20 - /* Restore the ENDT first. The targetting depends on it. */ + /* Restore the ENDT first. The targeting depends on it. */ for (i =3D 0; i < xive->nr_ends; i++) { if (!xive_end_is_valid(&xive->endt[i])) { continue; diff --git a/hw/intc/xive.c b/hw/intc/xive.c index df3ee0496f..a3585593d8 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1608,7 +1608,7 @@ int xive_presenter_tctx_match(XivePresenter *xptr, Xi= veTCTX *tctx, * * It receives notification requests sent by the IVRE to find one * matching NVT (or more) dispatched on the processor threads. In case - * of a single NVT notification, the process is abreviated and the + * of a single NVT notification, the process is abbreviated and the * thread is signaled if a match is found. In case of a logical server * notification (bits ignored at the end of the NVT identifier), the * IVPE and IVRE select a winning thread using different filters. This diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index c37ef25d44..98c0d8ba44 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -542,7 +542,7 @@ static void xive2_router_realize(DeviceState *dev, Erro= r **errp) =20 /* * Notification using the END ESe/ESn bit (Event State Buffer for - * escalation and notification). Profide futher coalescing in the + * escalation and notification). Profide further coalescing in the * Router. */ static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk, @@ -621,7 +621,7 @@ static void xive2_router_end_notify(Xive2Router *xrtr, = uint8_t end_blk, =20 /* * Check the END ESn (Event State Buffer for notification) for - * even futher coalescing in the Router + * even further coalescing in the Router */ if (!xive2_end_is_notify(&end)) { /* ESn[Q]=3D1 : end of notification */ @@ -702,7 +702,7 @@ do_escalation: =20 /* * Check the END ESe (Event State Buffer for escalation) for even - * futher coalescing in the Router + * further coalescing in the Router */ if (!xive2_end_is_uncond_escalation(&end)) { /* ESe[Q]=3D1 : end of escalation notification */ diff --git a/hw/ipmi/ipmi_bmc_extern.c b/hw/ipmi/ipmi_bmc_extern.c index acf2bab35f..e232d35ba2 100644 --- a/hw/ipmi/ipmi_bmc_extern.c +++ b/hw/ipmi/ipmi_bmc_extern.c @@ -301,7 +301,7 @@ static void handle_msg(IPMIBmcExtern *ibe) ipmi_debug("msg checksum failure\n"); return; } else { - ibe->inpos--; /* Remove checkum */ + ibe->inpos--; /* Remove checksum */ } =20 timer_del(ibe->extern_timer); diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 4e314748d3..a98a157065 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -538,7 +538,7 @@ static void ct3d_reg_write(void *opaque, hwaddr offset,= uint64_t value, FIRST_ERROR_POINTER, cxl_err->type); } else { /* - * If no more errors, then follow recomendation of PCI spec + * If no more errors, then follow recommendation of PCI sp= ec * r6.0 6.2.4.2 to set the first error pointer to a status * bit that will never be used. */ @@ -697,7 +697,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **err= p) PCI_BASE_ADDRESS_MEM_TYPE_64, &ct3d->cxl_dstate.device_registers); =20 - /* MSI(-X) Initailization */ + /* MSI(-X) Initialization */ rc =3D msix_init_exclusive_bar(pci_dev, msix_num, 4, NULL); if (rc) { goto err_address_space_free; @@ -706,7 +706,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **err= p) msix_vector_use(pci_dev, i); } =20 - /* DOE Initailization */ + /* DOE Initialization */ pcie_doe_init(pci_dev, &ct3d->doe_cdat, 0x190, doe_cdat_prot, true, 0); =20 cxl_cstate->cdat.build_cdat_table =3D ct3_build_cdat_table; diff --git a/hw/misc/imx7_ccm.c b/hw/misc/imx7_ccm.c index f135ec7b7e..7539f7fb45 100644 --- a/hw/misc/imx7_ccm.c +++ b/hw/misc/imx7_ccm.c @@ -227,7 +227,7 @@ static uint32_t imx7_ccm_get_clock_frequency(IMXCCMStat= e *dev, IMXClk clock) * have fixed frequencies and we can provide requested frequency * easily. However for CCM provided clocks (like IPG) each GPT * timer can have its own clock root. - * This means we need additionnal information when calling this + * This means we need additional information when calling this * function to know the requester's identity. */ uint32_t freq =3D 0; diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index 0787a0268d..f84cc68849 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -246,7 +246,7 @@ #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */ #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */ #define vSR 0x1400 /* [VIA only] Shift register. */ -#define vACR 0x1600 /* [VIA only] Auxilary control register. */ +#define vACR 0x1600 /* [VIA only] Auxiliary control register. */ #define vPCR 0x1800 /* [VIA only] Peripheral control register. */ /* * CHRP sez never ever to *write* this. diff --git a/hw/misc/stm32f2xx_syscfg.c b/hw/misc/stm32f2xx_syscfg.c index 04c22c2850..19c1e86424 100644 --- a/hw/misc/stm32f2xx_syscfg.c +++ b/hw/misc/stm32f2xx_syscfg.c @@ -94,12 +94,12 @@ static void stm32f2xx_syscfg_write(void *opaque, hwaddr= addr, switch (addr) { case SYSCFG_MEMRMP: qemu_log_mask(LOG_UNIMP, - "%s: Changeing the memory mapping isn't supported " \ + "%s: Changing the memory mapping isn't supported " \ "in QEMU\n", __func__); return; case SYSCFG_PMC: qemu_log_mask(LOG_UNIMP, - "%s: Changeing the memory mapping isn't supported " \ + "%s: Changing the memory mapping isn't supported " \ "in QEMU\n", __func__); return; case SYSCFG_EXTICR1: diff --git a/hw/misc/trace-events b/hw/misc/trace-events index e8b2be14c0..bc87cd3670 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -155,7 +155,7 @@ stm32f4xx_syscfg_read(uint64_t addr) "reg read: addr: 0= x%" PRIx64 " " stm32f4xx_syscfg_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%= " PRIx64 " val: 0x%" PRIx64 "" =20 # stm32f4xx_exti.c -stm32f4xx_exti_set_irq(int irq, int leve) "Set EXTI: %d to %d" +stm32f4xx_exti_set_irq(int irq, int level) "Set EXTI: %d to %d" stm32f4xx_exti_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " " stm32f4xx_exti_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" = PRIx64 " val: 0x%" PRIx64 "" =20 diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 8b70285961..41f38a98e9 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -285,7 +285,7 @@ static void zynq_slcr_compute_clocks_internal(ZynqSLCRS= tate *s, uint64_t ps_clk) } =20 /** - * Compute and set the ouputs clocks periods. + * Compute and set the outputs clocks periods. * But do not propagate them further. Connected clocks * will not receive any updates (See zynq_slcr_compute_clocks()) */ diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 539d273553..1dcad5f2e0 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -17,7 +17,7 @@ * Notes on coding style * --------------------- * While QEMU coding style prefers lowercase hexadecimals in constants, the - * NVMe subsystem use thes format from the NVMe specifications in the comm= ents + * NVMe subsystem use this format from the NVMe specifications in the comm= ents * (i.e. 'h' suffix instead of '0x' prefix). * * Usage @@ -730,7 +730,7 @@ static inline void nvme_sg_unmap(NvmeSg *sg) } =20 /* - * When metadata is transfered as extended LBAs, the DPTR mapped into `sg` + * When metadata is transferred as extended LBAs, the DPTR mapped into `sg` * holds both data and metadata. This function splits the data and metadata * into two separate QSG/IOVs. */ @@ -7594,7 +7594,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) /* * NVM Express v1.3d, Section 4.1 state: "If host software wri= tes * an invalid value to the Submission Queue Tail Doorbell or - * Completion Queue Head Doorbell regiter and an Asynchronous = Event + * Completion Queue Head Doorbell register and an Asynchronous= Event * Request command is outstanding, then an asynchronous event = is * posted to the Admin Completion Queue with a status code of * Invalid Doorbell Write Value." diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c index 613c4929e3..3272068663 100644 --- a/hw/nvram/eeprom_at24c.c +++ b/hw/nvram/eeprom_at24c.c @@ -51,7 +51,7 @@ struct EEPROMState { bool writable; /* cells changed since last START? */ bool changed; - /* during WRITE, # of address bytes transfered */ + /* during WRITE, # of address bytes transferred */ uint8_t haveaddr; =20 uint8_t *mem; diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index 29a5bef1d5..4e4524673a 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -877,7 +877,7 @@ static struct { /* * Any sub-page size update to these table MRs will be lost during migrati= on, * as we use aligned size in ram_load_precopy() -> qemu_ram_resize() path. - * In order to avoid the inconsistency in sizes save them seperately and + * In order to avoid the inconsistency in sizes save them separately and * migrate over in vmstate post_load(). */ static void fw_cfg_acpi_mr_save(FWCfgState *s, const char *filename, size_= t len) diff --git a/hw/rtc/exynos4210_rtc.c b/hw/rtc/exynos4210_rtc.c index 2b8a38a296..cc7101c530 100644 --- a/hw/rtc/exynos4210_rtc.c +++ b/hw/rtc/exynos4210_rtc.c @@ -202,7 +202,7 @@ static void exynos4210_rtc_update_freq(Exynos4210RTCSta= te *s, uint32_t freq; =20 freq =3D s->freq; - /* set frequncy for time generator */ + /* set frequency for time generator */ s->freq =3D RTC_BASE_FREQ / (1 << TICCKSEL(reg_value)); =20 if (freq !=3D s->freq) { diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c index 3e887a0fc7..d00fcb0ef0 100644 --- a/hw/rx/rx62n.c +++ b/hw/rx/rx62n.c @@ -114,7 +114,7 @@ static const uint8_t ipr_table[NR_IRQS] =3D { }; =20 /* - * Level triggerd IRQ list + * Level triggered IRQ list * Not listed IRQ is Edge trigger. * See "11.3.1 Interrupt Vector Table" in hardware manual. */ diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c index f7d45b0b20..634ed49c2e 100644 --- a/hw/scsi/lsi53c895a.c +++ b/hw/scsi/lsi53c895a.c @@ -1321,7 +1321,7 @@ again: } trace_lsi_execute_script_io_selected(id, insn & (1 << 3) ? " ATN" : ""= ); - /* ??? Linux drivers compain when this is set. Maybe + /* ??? Linux drivers complain when this is set. Maybe it only applies in low-level mode (unimplemented). lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */ s->select_tag =3D id << 8; diff --git a/hw/scsi/mfi.h b/hw/scsi/mfi.h index 0b4ee53dfc..cf7a2d775b 100644 --- a/hw/scsi/mfi.h +++ b/hw/scsi/mfi.h @@ -65,7 +65,7 @@ #define MFI_IQPH 0xc4 /* Inbound queue port (high bytes)= */ #define MFI_DIAG 0xf8 /* Host diag */ #define MFI_SEQ 0xfc /* Sequencer offset */ -#define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */ +#define MFI_1078_EIM 0x80000004 /* 1078 enable interrupt mask */ #define MFI_RMI 0x2 /* reply message interrupt */ #define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ #define MFI_ODC 0x4 /* outbound doorbell change interr= upt */ diff --git a/hw/sh4/sh7750_regs.h b/hw/sh4/sh7750_regs.h index 94043431e6..edb5d18f00 100644 --- a/hw/sh4/sh7750_regs.h +++ b/hw/sh4/sh7750_regs.h @@ -113,7 +113,7 @@ #define SH7750_TTB SH7750_P4_REG32(SH7750_TTB_REGOFS) #define SH7750_TTB_A7 SH7750_A7_REG32(SH7750_TTB_REGOFS) =20 -/* TLB exeption address register - TEA */ +/* TLB exception address register - TEA */ #define SH7750_TEA_REGOFS 0x00000c /* offset */ #define SH7750_TEA SH7750_P4_REG32(SH7750_TEA_REGOFS) #define SH7750_TEA_A7 SH7750_A7_REG32(SH7750_TEA_REGOFS) @@ -183,19 +183,19 @@ #define SH7750_TRA_IMM 0x000003fd /* Immediate data operand */ #define SH7750_TRA_IMM_S 2 =20 -/* Exeption event register - EXPEVT */ +/* Exception event register - EXPEVT */ #define SH7750_EXPEVT_REGOFS 0x000024 #define SH7750_EXPEVT SH7750_P4_REG32(SH7750_EXPEVT_REGOFS) #define SH7750_EXPEVT_A7 SH7750_A7_REG32(SH7750_EXPEVT_REGOFS) =20 -#define SH7750_EXPEVT_EX 0x00000fff /* Exeption code */ +#define SH7750_EXPEVT_EX 0x00000fff /* Exception code */ #define SH7750_EXPEVT_EX_S 0 =20 /* Interrupt event register */ #define SH7750_INTEVT_REGOFS 0x000028 #define SH7750_INTEVT SH7750_P4_REG32(SH7750_INTEVT_REGOFS) #define SH7750_INTEVT_A7 SH7750_A7_REG32(SH7750_INTEVT_REGOFS) -#define SH7750_INTEVT_EX 0x00000fff /* Exeption code */ +#define SH7750_INTEVT_EX 0x00000fff /* Exception code */ #define SH7750_INTEVT_EX_S 0 =20 /* @@ -1274,15 +1274,15 @@ /* * User Break Controller registers */ -#define SH7750_BARA 0x200000 /* Break address regiser A */ -#define SH7750_BAMRA 0x200004 /* Break address mask regiser A */ -#define SH7750_BBRA 0x200008 /* Break bus cycle regiser A */ -#define SH7750_BARB 0x20000c /* Break address regiser B */ -#define SH7750_BAMRB 0x200010 /* Break address mask regiser B */ -#define SH7750_BBRB 0x200014 /* Break bus cycle regiser B */ -#define SH7750_BASRB 0x000018 /* Break ASID regiser B */ -#define SH7750_BDRB 0x200018 /* Break data regiser B */ -#define SH7750_BDMRB 0x20001c /* Break data mask regiser B */ +#define SH7750_BARA 0x200000 /* Break address register A */ +#define SH7750_BAMRA 0x200004 /* Break address mask register A */ +#define SH7750_BBRA 0x200008 /* Break bus cycle register A */ +#define SH7750_BARB 0x20000c /* Break address register B */ +#define SH7750_BAMRB 0x200010 /* Break address mask register B */ +#define SH7750_BBRB 0x200014 /* Break bus cycle register B */ +#define SH7750_BASRB 0x000018 /* Break ASID register B */ +#define SH7750_BDRB 0x200018 /* Break data register B */ +#define SH7750_BDMRB 0x20001c /* Break data mask register B */ #define SH7750_BRCR 0x200020 /* Break control register */ =20 #define SH7750_BRCR_UDBE 0x0001 /* User break debug enable bit */ diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c index 10cd22f610..b753705856 100644 --- a/hw/smbios/smbios.c +++ b/hw/smbios/smbios.c @@ -1110,7 +1110,7 @@ void smbios_get_tables(MachineState *ms, dimm_cnt =3D QEMU_ALIGN_UP(current_machine->ram_size, MAX_DIMM_SZ)= / MAX_DIMM_SZ; =20 /* - * The offset determines if we need to keep additional space betwe= een + * The offset determines if we need to keep additional space betwe= en * table 17 and table 19 header handle numbers so that they do * not overlap. For example, for a VM with larger than 8 TB guest * memory and DIMM like chunks of 16 GiB, the default space between diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 97009d3a5d..a3955c6c50 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -163,7 +163,7 @@ FIELD(GQSPI_CNFG, ENDIAN, 26, 1) /* Poll timeout not implemented */ FIELD(GQSPI_CNFG, EN_POLL_TIMEOUT, 20, 1) - /* QEMU doesnt care about any of these last three */ + /* QEMU doesn't care about any of these last three */ FIELD(GQSPI_CNFG, BR, 3, 3) FIELD(GQSPI_CNFG, CPH, 2, 1) FIELD(GQSPI_CNFG, CPL, 1, 1) @@ -469,7 +469,7 @@ static void xlnx_zynqmp_qspips_flush_fifo_g(XlnxZynqMPQ= SPIPS *s) =20 imm =3D ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, IMMEDIATE= _DATA); if (!ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, DATA_XFER)) { - /* immedate transfer */ + /* immediate transfer */ if (ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, TRANSMIT)= || ARRAY_FIELD_EX32(s->regs, GQSPI_GF_SNAPSHOT, RECIEVE))= { s->regs[R_GQSPI_DATA_STS] =3D 1; @@ -768,7 +768,7 @@ static void xilinx_spips_check_zero_pump(XilinxSPIPS *s) */ while (s->regs[R_TRANSFER_SIZE] && s->rx_fifo.num + s->tx_fifo.num < RXFF_A_Q - 3) { - /* endianess just doesn't matter when zero pumping */ + /* endianness just doesn't matter when zero pumping */ tx_data_bytes(&s->tx_fifo, 0, 4, false); s->regs[R_TRANSFER_SIZE] &=3D ~0x03ull; s->regs[R_TRANSFER_SIZE] -=3D 4; diff --git a/hw/ssi/xlnx-versal-ospi.c b/hw/ssi/xlnx-versal-ospi.c index c762e0b367..1a61679c2f 100644 --- a/hw/ssi/xlnx-versal-ospi.c +++ b/hw/ssi/xlnx-versal-ospi.c @@ -837,7 +837,7 @@ static void ospi_do_ind_read(XlnxVersalOspi *s) /* Continue to read flash until we run out of space in sram */ while (!ospi_ind_op_completed(op) && !fifo8_is_full(&s->rx_sram)) { - /* Read reqested number of bytes, max bytes limited to size of sra= m */ + /* Read requested number of bytes, max bytes limited to size of sr= am */ next_b =3D ind_op_next_byte(op); end_b =3D next_b + fifo8_num_free(&s->rx_sram); end_b =3D MIN(end_b, ind_op_end_byte(op)); diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c index 2d6d92ef93..f035b74560 100644 --- a/hw/timer/etraxfs_timer.c +++ b/hw/timer/etraxfs_timer.c @@ -236,7 +236,7 @@ static void watchdog_hit(void *opaque) { ETRAXTimerState *t =3D opaque; if (t->wd_hits =3D=3D 0) { - /* real hw gives a single tick before reseting but we are + /* real hw gives a single tick before resetting but we are a bit friendlier to compensate for our slower execution. */ ptimer_set_count(t->ptimer_wd, 10); ptimer_run(t->ptimer_wd, 1); diff --git a/hw/timer/renesas_tmr.c b/hw/timer/renesas_tmr.c index c15f654738..43b31213bc 100644 --- a/hw/timer/renesas_tmr.c +++ b/hw/timer/renesas_tmr.c @@ -115,7 +115,7 @@ static int elapsed_time(RTMRState *tmr, int ch, int64_t= delta) et =3D tmr->div_round[ch] / divrate; tmr->div_round[ch] %=3D divrate; } else { - /* disble clock. so no update */ + /* disable clock. so no update */ et =3D 0; } return et; diff --git a/hw/virtio/virtio-crypto.c b/hw/virtio/virtio-crypto.c index 13aec771e1..0e2cc8d5a8 100644 --- a/hw/virtio/virtio-crypto.c +++ b/hw/virtio/virtio-crypto.c @@ -655,7 +655,7 @@ virtio_crypto_sym_op_helper(VirtIODevice *vdev, op_info->len_to_hash =3D len_to_hash; op_info->cipher_start_src_offset =3D cipher_start_src_offset; op_info->len_to_cipher =3D len_to_cipher; - /* Handle the initilization vector */ + /* Handle the initialization vector */ if (op_info->iv_len > 0) { DPRINTF("iv_len=3D%" PRIu32 "\n", op_info->iv_len); op_info->iv =3D op_info->data + curr_size; @@ -1278,7 +1278,7 @@ static void virtio_crypto_instance_init(Object *obj) =20 /* * The default config_size is sizeof(struct virtio_crypto_config). - * Can be overriden with virtio_crypto_set_config_size. + * Can be overridden with virtio_crypto_set_config_size. */ vcrypto->config_size =3D sizeof(struct virtio_crypto_config); } diff --git a/hw/virtio/virtio-mem.c b/hw/virtio/virtio-mem.c index b6e781741e..da5b09cefc 100644 --- a/hw/virtio/virtio-mem.c +++ b/hw/virtio/virtio-mem.c @@ -1119,7 +1119,7 @@ static int virtio_mem_mig_sanity_checks_post_load(voi= d *opaque, int version_id) return -EINVAL; } /* - * Note: Preparation for resizeable memory regions. The maximum size + * Note: Preparation for resizable memory regions. The maximum size * of the memory region must not change during migration. */ if (tmp->region_size !=3D new_region_size) { diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index 309038fd46..9a06b65bae 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -2096,7 +2096,7 @@ void virtio_queue_enable(VirtIODevice *vdev, uint32_t= queue_index) * being converted to LOG_GUEST_ERROR. * if (!virtio_vdev_has_feature(vdev, VIRTIO_F_VERSION_1)) { - error_report("queue_enable is only suppported in devices of virtio= " + error_report("queue_enable is only supported in devices of virtio " "1.0 or later."); } */ --=20 2.39.2