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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694197700104100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 12 -- target/riscv/cpu.h | 30 +--- target/riscv/cpu_bits.h | 82 --------- target/riscv/cpu_helper.c | 52 ------ target/riscv/csr.c | 326 ----------------------------------- target/riscv/machine.c | 9 - target/riscv/translate.c | 27 +-- target/riscv/vector_helper.c | 2 +- 8 files changed, 9 insertions(+), 531 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b93b04453..f937820976 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -673,13 +673,6 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f= , int flags) CSR_MSCRATCH, CSR_SSCRATCH, CSR_SATP, - CSR_MMTE, - CSR_UPMBASE, - CSR_UPMMASK, - CSR_SPMBASE, - CSR_SPMMASK, - CSR_MPMBASE, - CSR_MPMMASK, }; =20 for (int i =3D 0; i < ARRAY_SIZE(dump_csrs); ++i) { @@ -893,11 +886,8 @@ static void riscv_cpu_reset_hold(Object *obj) } i++; } - /* mmte is supposed to have pm.current hardwired to 1 */ - env->mmte |=3D (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT); #endif env->xl =3D riscv_cpu_mxl(env); - riscv_cpu_update_mask(env); cs->exception_index =3D RISCV_EXCP_NONE; env->load_res =3D -1; set_default_nan_mode(1, &env->fp_status); @@ -1666,7 +1656,6 @@ static const MISAExtInfo misa_ext_info_arr[] =3D { MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"), MISA_EXT_INFO(RVU, "u", "User-level instructions"), MISA_EXT_INFO(RVH, "h", "Hypervisor"), - MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"), MISA_EXT_INFO(RVV, "v", "Vector operations"), MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), }; @@ -1718,7 +1707,6 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] =3D { MISA_CFG(RVS, true), MISA_CFG(RVU, true), MISA_CFG(RVH, true), - MISA_CFG(RVJ, false), MISA_CFG(RVV, false), MISA_CFG(RVG, false), }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6ea22e0eea..62dabfa207 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -338,17 +338,6 @@ struct CPUArchState { /* True if in debugger mode. */ bool debugger; =20 - /* - * CSRs for PointerMasking extension - */ - target_ulong mmte; - target_ulong mpmmask; - target_ulong mpmbase; - target_ulong spmmask; - target_ulong spmbase; - target_ulong upmmask; - target_ulong upmbase; - /* CSRs for execution enviornment configuration */ uint64_t menvcfg; uint64_t mstateen[SMSTATEEN_MAX_COUNT]; @@ -357,8 +346,6 @@ struct CPUArchState { target_ulong senvcfg; uint64_t henvcfg; #endif - target_ulong cur_pmmask; - target_ulong cur_pmbase; =20 /* Fields from here on are preserved across CPU reset. */ QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ @@ -495,17 +482,14 @@ FIELD(TB_FLAGS, VILL, 14, 1) FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ FIELD(TB_FLAGS, XL, 16, 2) -/* If PointerMasking should be applied */ -FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) -FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) -FIELD(TB_FLAGS, VTA, 20, 1) -FIELD(TB_FLAGS, VMA, 21, 1) +FIELD(TB_FLAGS, VTA, 18, 1) +FIELD(TB_FLAGS, VMA, 19, 1) /* Native debug itrigger */ -FIELD(TB_FLAGS, ITRIGGER, 22, 1) +FIELD(TB_FLAGS, ITRIGGER, 20, 1) /* Virtual mode enabled */ -FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) -FIELD(TB_FLAGS, PRIV, 24, 2) -FIELD(TB_FLAGS, AXL, 26, 2) +FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) +FIELD(TB_FLAGS, PRIV, 22, 2) +FIELD(TB_FLAGS, AXL, 24, 2) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) @@ -632,8 +616,6 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, ta= rget_ulong vtype) void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags); =20 -void riscv_cpu_update_mask(CPURISCVState *env); - RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask= ); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 59f0ffd9e1..87a741fe66 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -491,37 +491,6 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f =20 -/* - * User PointerMasking registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_UMTE 0x4c0 -#define CSR_UPMMASK 0x4c1 -#define CSR_UPMBASE 0x4c2 - -/* - * Machine PointerMasking registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_MMTE 0x3c0 -#define CSR_MPMMASK 0x3c1 -#define CSR_MPMBASE 0x3c2 - -/* - * Supervisor PointerMaster registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_SMTE 0x1c0 -#define CSR_SPMMASK 0x1c1 -#define CSR_SPMBASE 0x1c2 - -/* - * Hypervisor PointerMaster registers - * NB: actual CSR numbers might be changed in future - */ -#define CSR_VSMTE 0x2c0 -#define CSR_VSPMMASK 0x2c1 -#define CSR_VSPMBASE 0x2c2 #define CSR_SCOUNTOVF 0xda0 =20 /* Crypto Extension */ @@ -772,57 +741,6 @@ typedef enum RISCVException { #define HENVCFGH_PBMTE MENVCFGH_PBMTE #define HENVCFGH_STCE MENVCFGH_STCE =20 -/* Offsets for every pair of control bits per each priv level */ -#define XS_OFFSET 0ULL -#define U_OFFSET 2ULL -#define S_OFFSET 5ULL -#define M_OFFSET 8ULL - -#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET) -#define U_PM_ENABLE (PM_ENABLE << U_OFFSET) -#define U_PM_CURRENT (PM_CURRENT << U_OFFSET) -#define U_PM_INSN (PM_INSN << U_OFFSET) -#define S_PM_ENABLE (PM_ENABLE << S_OFFSET) -#define S_PM_CURRENT (PM_CURRENT << S_OFFSET) -#define S_PM_INSN (PM_INSN << S_OFFSET) -#define M_PM_ENABLE (PM_ENABLE << M_OFFSET) -#define M_PM_CURRENT (PM_CURRENT << M_OFFSET) -#define M_PM_INSN (PM_INSN << M_OFFSET) - -/* mmte CSR bits */ -#define MMTE_PM_XS_BITS PM_XS_BITS -#define MMTE_U_PM_ENABLE U_PM_ENABLE -#define MMTE_U_PM_CURRENT U_PM_CURRENT -#define MMTE_U_PM_INSN U_PM_INSN -#define MMTE_S_PM_ENABLE S_PM_ENABLE -#define MMTE_S_PM_CURRENT S_PM_CURRENT -#define MMTE_S_PM_INSN S_PM_INSN -#define MMTE_M_PM_ENABLE M_PM_ENABLE -#define MMTE_M_PM_CURRENT M_PM_CURRENT -#define MMTE_M_PM_INSN M_PM_INSN -#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INS= N | \ - MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INS= N | \ - MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INS= N | \ - MMTE_PM_XS_BITS) - -/* (v)smte CSR bits */ -#define SMTE_PM_XS_BITS PM_XS_BITS -#define SMTE_U_PM_ENABLE U_PM_ENABLE -#define SMTE_U_PM_CURRENT U_PM_CURRENT -#define SMTE_U_PM_INSN U_PM_INSN -#define SMTE_S_PM_ENABLE S_PM_ENABLE -#define SMTE_S_PM_CURRENT S_PM_CURRENT -#define SMTE_S_PM_INSN S_PM_INSN -#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INS= N | \ - SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INS= N | \ - SMTE_PM_XS_BITS) - -/* umte CSR bits */ -#define UMTE_U_PM_ENABLE U_PM_ENABLE -#define UMTE_U_PM_CURRENT U_PM_CURRENT -#define UMTE_U_PM_INSN U_PM_INSN -#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_IN= SN) - /* MISELECT, SISELECT, and VSISELECT bits (AIA) */ #define ISELECT_IPRIO0 0x30 #define ISELECT_IPRIO15 0x3f diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9f611d89bb..57859314e3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -136,61 +136,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *= pc, flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); - if (env->cur_pmmask !=3D 0) { - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); - } - if (env->cur_pmbase !=3D 0) { - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); - } =20 *pflags =3D flags; } =20 -void riscv_cpu_update_mask(CPURISCVState *env) -{ - target_ulong mask =3D 0, base =3D 0; - RISCVMXL xl =3D env->xl; - /* - * TODO: Current RVJ spec does not specify - * how the extension interacts with XLEN. - */ -#ifndef CONFIG_USER_ONLY - int mode =3D cpu_address_mode(env); - xl =3D cpu_get_xl(env, mode); - if (riscv_has_ext(env, RVJ)) { - switch (mode) { - case PRV_M: - if (env->mmte & M_PM_ENABLE) { - mask =3D env->mpmmask; - base =3D env->mpmbase; - } - break; - case PRV_S: - if (env->mmte & S_PM_ENABLE) { - mask =3D env->spmmask; - base =3D env->spmbase; - } - break; - case PRV_U: - if (env->mmte & U_PM_ENABLE) { - mask =3D env->upmmask; - base =3D env->upmbase; - } - break; - default: - g_assert_not_reached(); - } - } -#endif - if (xl =3D=3D MXL_RV32) { - env->cur_pmmask =3D mask & UINT32_MAX; - env->cur_pmbase =3D base & UINT32_MAX; - } else { - env->cur_pmmask =3D mask; - env->cur_pmbase =3D base; - } -} - #ifndef CONFIG_USER_ONLY =20 /* @@ -678,7 +627,6 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulon= g newpriv) /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv =3D newpriv; env->xl =3D cpu_recompute_xl(env); - riscv_cpu_update_mask(env); =20 /* * Clear the load reservation - otherwise a reservation placed in one diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ea7585329e..a08285e55d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -477,16 +477,6 @@ static RISCVException hgatp(CPURISCVState *env, int cs= rno) return hmode(env, csrno); } =20 -/* Checks if PointerMasking registers could be accessed */ -static RISCVException pointer_masking(CPURISCVState *env, int csrno) -{ - /* Check if j-ext is present */ - if (riscv_has_ext(env, RVJ)) { - return RISCV_EXCP_NONE; - } - return RISCV_EXCP_ILLEGAL_INST; -} - static int aia_hmode(CPURISCVState *env, int csrno) { if (!riscv_cpu_cfg(env)->ext_ssaia) { @@ -1331,7 +1321,6 @@ static RISCVException write_mstatus(CPURISCVState *en= v, int csrno, env->xl =3D cpu_recompute_xl(env); } =20 - riscv_cpu_update_mask(env); return RISCV_EXCP_NONE; } =20 @@ -3497,302 +3486,6 @@ static RISCVException read_tinfo(CPURISCVState *env= , int csrno, return RISCV_EXCP_NONE; } =20 -/* - * Functions to access Pointer Masking feature registers - * We have to check if current priv lvl could modify - * csr in given mode - */ -static bool check_pm_current_disabled(CPURISCVState *env, int csrno) -{ - int csr_priv =3D get_field(csrno, 0x300); - int pm_current; - - if (env->debugger) { - return false; - } - /* - * If priv lvls differ that means we're accessing csr from higher priv= lvl, - * so allow the access - */ - if (env->priv !=3D csr_priv) { - return false; - } - switch (env->priv) { - case PRV_M: - pm_current =3D get_field(env->mmte, M_PM_CURRENT); - break; - case PRV_S: - pm_current =3D get_field(env->mmte, S_PM_CURRENT); - break; - case PRV_U: - pm_current =3D get_field(env->mmte, U_PM_CURRENT); - break; - default: - g_assert_not_reached(); - } - /* It's same priv lvl, so we allow to modify csr only if pm.current=3D= =3D1 */ - return !pm_current; -} - -static RISCVException read_mmte(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->mmte & MMTE_MASK; - return RISCV_EXCP_NONE; -} - -static RISCVException write_mmte(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - target_ulong wpri_val =3D val & MMTE_MASK; - - if (val !=3D wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" - TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x= ", - val, "vs expected 0x", wpri_val); - } - /* for machine mode pm.current is hardwired to 1 */ - wpri_val |=3D MMTE_M_PM_CURRENT; - - /* hardwiring pm.instruction bit to 0, since it's not supported yet */ - wpri_val &=3D ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN); - env->mmte =3D wpri_val | EXT_STATUS_DIRTY; - riscv_cpu_update_mask(env); - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_smte(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->mmte & SMTE_MASK; - return RISCV_EXCP_NONE; -} - -static RISCVException write_smte(CPURISCVState *env, int csrno, - target_ulong val) -{ - target_ulong wpri_val =3D val & SMTE_MASK; - - if (val !=3D wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" - TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x= ", - val, "vs expected 0x", wpri_val); - } - - /* if pm.current=3D=3D0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - - wpri_val |=3D (env->mmte & ~SMTE_MASK); - write_mmte(env, csrno, wpri_val); - return RISCV_EXCP_NONE; -} - -static RISCVException read_umte(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->mmte & UMTE_MASK; - return RISCV_EXCP_NONE; -} - -static RISCVException write_umte(CPURISCVState *env, int csrno, - target_ulong val) -{ - target_ulong wpri_val =3D val & UMTE_MASK; - - if (val !=3D wpri_val) { - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" - TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x= ", - val, "vs expected 0x", wpri_val); - } - - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - - wpri_val |=3D (env->mmte & ~UMTE_MASK); - write_mmte(env, csrno, wpri_val); - return RISCV_EXCP_NONE; -} - -static RISCVException read_mpmmask(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->mpmmask; - return RISCV_EXCP_NONE; -} - -static RISCVException write_mpmmask(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - env->mpmmask =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE))= { - env->cur_pmmask =3D val; - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_spmmask(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->spmmask; - return RISCV_EXCP_NONE; -} - -static RISCVException write_spmmask(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current=3D=3D0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->spmmask =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE))= { - env->cur_pmmask =3D val; - if (cpu_get_xl(env, PRV_S) =3D=3D MXL_RV32) { - env->cur_pmmask &=3D UINT32_MAX; - } - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_upmmask(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->upmmask; - return RISCV_EXCP_NONE; -} - -static RISCVException write_upmmask(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current=3D=3D0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->upmmask =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE))= { - env->cur_pmmask =3D val; - if (cpu_get_xl(env, PRV_U) =3D=3D MXL_RV32) { - env->cur_pmmask &=3D UINT32_MAX; - } - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_mpmbase(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->mpmbase; - return RISCV_EXCP_NONE; -} - -static RISCVException write_mpmbase(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - env->mpmbase =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_M) && (env->mmte & M_PM_ENABLE))= { - env->cur_pmbase =3D val; - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_spmbase(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->spmbase; - return RISCV_EXCP_NONE; -} - -static RISCVException write_spmbase(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current=3D=3D0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->spmbase =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_S) && (env->mmte & S_PM_ENABLE))= { - env->cur_pmbase =3D val; - if (cpu_get_xl(env, PRV_S) =3D=3D MXL_RV32) { - env->cur_pmbase &=3D UINT32_MAX; - } - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - -static RISCVException read_upmbase(CPURISCVState *env, int csrno, - target_ulong *val) -{ - *val =3D env->upmbase; - return RISCV_EXCP_NONE; -} - -static RISCVException write_upmbase(CPURISCVState *env, int csrno, - target_ulong val) -{ - uint64_t mstatus; - - /* if pm.current=3D=3D0 we can't modify current PM CSRs */ - if (check_pm_current_disabled(env, csrno)) { - return RISCV_EXCP_NONE; - } - env->upmbase =3D val; - if ((cpu_address_mode(env) =3D=3D PRV_U) && (env->mmte & U_PM_ENABLE))= { - env->cur_pmbase =3D val; - if (cpu_get_xl(env, PRV_U) =3D=3D MXL_RV32) { - env->cur_pmbase &=3D UINT32_MAX; - } - } - env->mmte |=3D EXT_STATUS_DIRTY; - - /* Set XS and SD bits, since PM CSRs are dirty */ - mstatus =3D env->mstatus | MSTATUS_XS; - write_mstatus(env, csrno, mstatus); - return RISCV_EXCP_NONE; -} - #endif =20 /* Crypto Extension */ @@ -4393,25 +4086,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_TDATA3] =3D { "tdata3", debug, read_tdata, write_tdata }, [CSR_TINFO] =3D { "tinfo", debug, read_tinfo, write_ignore }, =20 - /* User Pointer Masking */ - [CSR_UMTE] =3D { "umte", pointer_masking, read_umte, write_u= mte }, - [CSR_UPMMASK] =3D { "upmmask", pointer_masking, read_upmmask, - write_upmmask = }, - [CSR_UPMBASE] =3D { "upmbase", pointer_masking, read_upmbase, - write_upmbase = }, - /* Machine Pointer Masking */ - [CSR_MMTE] =3D { "mmte", pointer_masking, read_mmte, write_m= mte }, - [CSR_MPMMASK] =3D { "mpmmask", pointer_masking, read_mpmmask, - write_mpmmask = }, - [CSR_MPMBASE] =3D { "mpmbase", pointer_masking, read_mpmbase, - write_mpmbase = }, - /* Supervisor Pointer Masking */ - [CSR_SMTE] =3D { "smte", pointer_masking, read_smte, write_s= mte }, - [CSR_SPMMASK] =3D { "spmmask", pointer_masking, read_spmmask, - write_spmmask = }, - [CSR_SPMBASE] =3D { "spmbase", pointer_masking, read_spmbase, - write_spmbase = }, - /* Performance Counters */ [CSR_HPMCOUNTER3] =3D { "hpmcounter3", ctr, read_hpmcounter }, [CSR_HPMCOUNTER4] =3D { "hpmcounter4", ctr, read_hpmcounter }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c7c862cdd3..8b1a109275 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -161,14 +161,6 @@ static const VMStateDescription vmstate_pointermasking= =3D { .minimum_version_id =3D 1, .needed =3D pointermasking_needed, .fields =3D (VMStateField[]) { - VMSTATE_UINTTL(env.mmte, RISCVCPU), - VMSTATE_UINTTL(env.mpmmask, RISCVCPU), - VMSTATE_UINTTL(env.mpmbase, RISCVCPU), - VMSTATE_UINTTL(env.spmmask, RISCVCPU), - VMSTATE_UINTTL(env.spmbase, RISCVCPU), - VMSTATE_UINTTL(env.upmmask, RISCVCPU), - VMSTATE_UINTTL(env.upmbase, RISCVCPU), - VMSTATE_END_OF_LIST() } }; @@ -264,7 +256,6 @@ static int riscv_cpu_post_load(void *opaque, int versio= n_id) CPURISCVState *env =3D &cpu->env; =20 env->xl =3D cpu_recompute_xl(env); - riscv_cpu_update_mask(env); return 0; } =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 697df1be9e..ce47904590 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -42,9 +42,6 @@ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cp= u_vstart; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; -/* globals for PM CSRs */ -static TCGv pm_mask; -static TCGv pm_base; =20 /* * If an operation is being performed on less than TARGET_LONG_BITS, @@ -106,9 +103,6 @@ typedef struct DisasContext { bool vl_eq_vlmax; CPUState *cs; TCGv zero; - /* PointerMasking extension */ - bool pm_mask_enabled; - bool pm_base_enabled; /* Use icount trigger for native debug */ bool itrigger; /* FRM is known to contain a valid value. */ @@ -582,14 +576,9 @@ static TCGv get_address(DisasContext *ctx, int rs1, in= t imm) TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_addi_tl(addr, src1, imm); - if (ctx->pm_mask_enabled) { - tcg_gen_andc_tl(addr, addr, pm_mask); - } else if (get_address_xl(ctx) =3D=3D MXL_RV32) { + if (get_address_xl(ctx) =3D=3D MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } - if (ctx->pm_base_enabled) { - tcg_gen_or_tl(addr, addr, pm_base); - } =20 return addr; } @@ -601,14 +590,9 @@ static TCGv get_address_indexed(DisasContext *ctx, int= rs1, TCGv offs) TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_add_tl(addr, src1, offs); - if (ctx->pm_mask_enabled) { - tcg_gen_andc_tl(addr, addr, pm_mask); - } else if (get_xl(ctx) =3D=3D MXL_RV32) { + if (get_xl(ctx) =3D=3D MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } - if (ctx->pm_base_enabled) { - tcg_gen_or_tl(addr, addr, pm_base); - } return addr; } =20 @@ -1191,8 +1175,6 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl =3D FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs =3D cs; - ctx->pm_mask_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLE= D); - ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE= D); ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; @@ -1324,9 +1306,4 @@ void riscv_translate_init(void) "load_res"); load_val =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_= val), "load_val"); - /* Assign PM CSRs to tcg globals */ - pm_mask =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pm= mask), - "pmmask"); - pm_base =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pm= base), - "pmbase"); } diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 4d06754826..af07e1067d 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -169,7 +169,7 @@ static inline uint32_t vext_get_total_elems(CPURISCVSta= te *env, uint32_t desc, =20 static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad= dr) { - return (addr & ~env->cur_pmmask) | env->cur_pmbase; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=baturo.alexey@gmail.com; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1694197694091100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 7 +++++++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/machine.c | 6 ++++-- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f937820976..af8f16b94f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -137,6 +137,9 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(ssnjpm, PRIV_VERSION_1_12_0, ext_ssnjpm), + ISA_EXT_DATA_ENTRY(smnjpm, PRIV_VERSION_1_12_0, ext_smnjpm), + ISA_EXT_DATA_ENTRY(smmjpm, PRIV_VERSION_1_12_0, ext_smmjpm), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), @@ -1796,6 +1799,10 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), =20 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), + /* Zjpm v0.6.1 extensions */ + DEFINE_PROP_BOOL("ssnjpm", RISCVCPU, cfg.ext_ssnjpm, false), + DEFINE_PROP_BOOL("smnjpm", RISCVCPU, cfg.ext_smnjpm, false), + DEFINE_PROP_BOOL("smmjpm", RISCVCPU, cfg.ext_smmjpm, false), =20 DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false), DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2bd9510ba3..9e9eb7cd1d 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -93,6 +93,9 @@ struct RISCVCPUConfig { bool ext_smaia; bool ext_ssaia; bool ext_sscofpmf; + bool ext_ssnjpm; + bool ext_smnjpm; + bool ext_smmjpm; bool rvv_ta_all_1s; bool rvv_ma_all_1s; =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 8b1a109275..d50ff5421f 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -150,9 +150,8 @@ static const VMStateDescription vmstate_vector =3D { static bool pointermasking_needed(void *opaque) { RISCVCPU *cpu =3D opaque; - CPURISCVState *env =3D &cpu->env; =20 - return riscv_has_ext(env, RVJ); + return cpu->cfg.ext_ssnjpm || cpu->cfg.ext_smnjpm || cpu->cfg.ext_smmj= pm; } =20 static const VMStateDescription vmstate_pointermasking =3D { @@ -161,6 +160,9 @@ static const VMStateDescription vmstate_pointermasking = =3D { .minimum_version_id =3D 1, .needed =3D pointermasking_needed, .fields =3D (VMStateField[]) { + VMSTATE_UINTTL(env.mseccfg, RISCVCPU), + VMSTATE_UINTTL(env.senvcfg, RISCVCPU), + VMSTATE_UINTTL(env.menvcfg, RISCVCPU), VMSTATE_END_OF_LIST() } }; --=20 2.34.1 From nobody Tue May 14 16:39:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[188.255.126.251]) by smtp.gmail.com with ESMTPSA id cb22-20020a170906a45600b0099d804da2e9sm1342667ejb.225.2023.09.08.11.26.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 11:26:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694197611; x=1694802411; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xAJzL3UFw1DN5li2iMX/eafl89efIRabG5Xy7FGMFn4=; b=cdpjcFB00WWtJU1kiTf906mqADatAJ2AeRX2/M8DgryRpzm3WyrIE8vAVA9vWZr/+G 4+q4TXW504FkmCbu5WXpRdJ5SjBgrpIM6Z/cbiTWopQUjJTgVmJtROwGk/knL6q/auOw 4Aqfl1RAZkOW84GEZo11YscEuUmvexYEvjUmliC1kTaJcRrd/sO8WHAabIj1bnLigrUU f2GZGCeCj3sHql8xQlrwapxKUDKyfDUzNLeg8bkB407HomEKV7Dk89XVaf2z7GV/aKpk r2Qa44ZDaupxxJQIiKg/CC0Xav2pu9vkgkBp6Mj6h/fYPdfzjqXtgoFDR6ZF7pUTYgKd MXsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694197611; x=1694802411; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694197755136100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Alexey Baturo --- target/riscv/cpu_bits.h | 6 ++++++ target/riscv/csr.c | 8 ++++++++ target/riscv/pmp.c | 5 +++++ target/riscv/pmp.h | 12 +++++++----- 4 files changed, 26 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 87a741fe66..238f7a13f4 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -714,6 +714,8 @@ typedef enum RISCVException { #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) +#define MENVCFG_SPMEN BIT(8) +#define MENVCFG_SPMENSELF BIT(9) #define MENVCFG_HADE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) @@ -727,11 +729,15 @@ typedef enum RISCVException { #define SENVCFG_CBIE MENVCFG_CBIE #define SENVCFG_CBCFE MENVCFG_CBCFE #define SENVCFG_CBZE MENVCFG_CBZE +#define SENVCFG_UPMEN MENVCFG_SPMEN +#define SENVCFG_UPMENSELF MENVCFG_SPMENSELF =20 #define HENVCFG_FIOM MENVCFG_FIOM #define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_HPMEN MENVCFG_SPMEN +#define HENVCFG_HPMENSELF MENVCFG_SPMENSELF #define HENVCFG_HADE MENVCFG_HADE #define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_STCE MENVCFG_STCE diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a08285e55d..c7e59168d2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1942,6 +1942,10 @@ static RISCVException write_menvcfg(CPURISCVState *e= nv, int csrno, (cfg->ext_sstc ? MENVCFG_STCE : 0) | (cfg->ext_svadu ? MENVCFG_HADE : 0); } + if (riscv_cpu_cfg(env)->ext_smnjpm) { + /* for zjpm v0.6.1 MENVCFG_SPMENSELF should be always 0 */ + mask |=3D MENVCFG_SPMEN; + } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); =20 return RISCV_EXCP_NONE; @@ -1993,6 +1997,10 @@ static RISCVException write_senvcfg(CPURISCVState *e= nv, int csrno, return ret; } =20 + if (riscv_cpu_cfg(env)->ext_ssnjpm) { + /* for zjpm v0.6.1 SENVCFG_UPMENSELF should be always 0 */ + mask |=3D SENVCFG_UPMEN; + } env->senvcfg =3D (env->senvcfg & ~mask) | (val & mask); return RISCV_EXCP_NONE; } diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 9d8db493e6..0db49173ef 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -580,6 +580,11 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulon= g val) val &=3D ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB); } =20 + if (riscv_cpu_cfg(env)->ext_smmjpm) { + /* for zjpm v0.6.1 MSECCFG_MPMENSELF should be always 0 */ + val &=3D ~MSECCFG_MPMENSELF; + } + env->mseccfg =3D val; } =20 diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index cf5c99f8e6..e4a58c9974 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -39,11 +39,13 @@ typedef enum { } pmp_am_t; =20 typedef enum { - MSECCFG_MML =3D 1 << 0, - MSECCFG_MMWP =3D 1 << 1, - MSECCFG_RLB =3D 1 << 2, - MSECCFG_USEED =3D 1 << 8, - MSECCFG_SSEED =3D 1 << 9 + MSECCFG_MML =3D 1 << 0, + MSECCFG_MMWP =3D 1 << 1, + MSECCFG_RLB =3D 1 << 2, + MSECCFG_USEED =3D 1 << 8, + MSECCFG_SSEED =3D 1 << 9, + MSECCFG_MPMEN =3D 1 << 10, + MSECCFG_MPMENSELF =3D 1 << 11 } mseccfg_field_t; =20 typedef struct { --=20 2.34.1 From nobody Tue May 14 16:39:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694197754; cv=none; d=zohomail.com; s=zohoarc; b=dZFuxGosYztzjeNzkQF5Eebh1IR91HsIth0eHr6zEeqg6DIW1tv7EWw9DYKLP18W1PQdG7uKgENR5o83btkwA+Q/PYr45h3LTsH76DvA3KjvmBo1Dw8oEHHIiUsLEx1+SYDEQCWn/931Xb8S9pCMVoV1eXNhcJHJHGhwcoFsvZE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1694197754; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject; bh=1sPxs4JxAboRctucSIXoAK0VUiOMnkz7S5Bc5cS9VTU=; b=N5qwYNY3bPXqeb9b0WyaUDsAqiuMhyQU/dc3St4cqG7qAXtkLGWX85ZTwOW5FUWo0SXssEaJXJG++wSOsSLS5Bw+US3FOla1Tq8O7ztTB8DasI9n5kBbhY6gAMco5bbl+zsLypJhPhTKrTxhyatr1C8rVBYNx1M80qRRbj4z4o8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169419775414491.26317141887887; Fri, 8 Sep 2023 11:29:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qegC1-0003KL-Sd; Fri, 08 Sep 2023 14:26:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qegC0-0003Je-Kh; Fri, 08 Sep 2023 14:26:56 -0400 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qegBy-0006mw-IL; Fri, 08 Sep 2023 14:26:56 -0400 Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-99bcf2de59cso295872766b.0; Fri, 08 Sep 2023 11:26:53 -0700 (PDT) Received: from freya.midgard (broadband-188-255-126-251.ip.moscow.rt.ru. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694197755793100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 62dabfa207..25fe60476b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -88,6 +88,16 @@ typedef enum { EXT_STATUS_DIRTY, } RISCVExtStatus; =20 +/* Enum holds maximum for N bits to be ignored depending on privilege leve= l */ +typedef enum { + PM_BARE_N_BITS =3D 16, + PM_SV32_N_BITS =3D 0, + PM_SV39_N_BITS =3D 25, + PM_SV48_N_BITS =3D 16, + PM_SV57_N_BITS =3D 7, + PM_SV64_N_BITS =3D 0, +} RISCVZjpmMaxNBits; + #define MMU_USER_IDX 3 =20 #define MAX_RISCV_PMPS (16) --=20 2.34.1 From nobody Tue May 14 16:39:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694197705; cv=none; d=zohomail.com; s=zohoarc; b=gVF6K9nKRWRs5Ra3MKJ5qTrXJZteS0FpH93JZLIE9c4EolEjUgDz/VBsRYWl0k6SKogCQtbdH4BXVPgY/+71i91+nZprgVFnLauQ10Qk2sKTKfTDjIOQRRfUVl/7CZaFHDzsyW+8xcvVslsv6R2QzPzc0DKbkLOcAE0UvMN2A/A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694197708207100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 19 +++++++++++++------ target/riscv/cpu_helper.c | 4 ++++ target/riscv/translate.c | 10 ++++++++++ 3 files changed, 27 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 25fe60476b..17d0088cb4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -356,6 +356,10 @@ struct CPUArchState { target_ulong senvcfg; uint64_t henvcfg; #endif + /* current number of masked top bits by pointer masking */ + target_ulong pm_n_bits; + /* if pointer masking should do sign extension */ + bool pm_signext; =20 /* Fields from here on are preserved across CPU reset. */ QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ @@ -492,14 +496,17 @@ FIELD(TB_FLAGS, VILL, 14, 1) FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ FIELD(TB_FLAGS, XL, 16, 2) -FIELD(TB_FLAGS, VTA, 18, 1) -FIELD(TB_FLAGS, VMA, 19, 1) +/* If pointer masking should be applied and address sign extended */ +FIELD(TB_FLAGS, PM_ENABLED, 18, 1) +FIELD(TB_FLAGS, PM_SIGNEXTEND, 19, 1) +FIELD(TB_FLAGS, VTA, 20, 1) +FIELD(TB_FLAGS, VMA, 21, 1) /* Native debug itrigger */ -FIELD(TB_FLAGS, ITRIGGER, 20, 1) +FIELD(TB_FLAGS, ITRIGGER, 22, 1) /* Virtual mode enabled */ -FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) -FIELD(TB_FLAGS, PRIV, 22, 2) -FIELD(TB_FLAGS, AXL, 24, 2) +FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) +FIELD(TB_FLAGS, PRIV, 24, 2) +FIELD(TB_FLAGS, AXL, 25, 2) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 57859314e3..b3871b0a28 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -136,6 +136,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *p= c, flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); + if (env->pm_n_bits !=3D 0) { + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, 1); + } + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, env->pm_signext); =20 *pflags =3D flags; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ce47904590..3434ba58b6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -42,6 +42,8 @@ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cp= u_vstart; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; +/* number of top masked address bits by pointer masking extension */ +static TCGv pm_n_bits; =20 /* * If an operation is being performed on less than TARGET_LONG_BITS, @@ -103,6 +105,9 @@ typedef struct DisasContext { bool vl_eq_vlmax; CPUState *cs; TCGv zero; + /* pointer masking extension */ + bool pm_enabled; + bool pm_signext; /* Use icount trigger for native debug */ bool itrigger; /* FRM is known to contain a valid value. */ @@ -1175,6 +1180,8 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl =3D FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs =3D cs; + ctx->pm_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); + ctx->pm_signext =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND); ctx->itrigger =3D FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero =3D tcg_constant_tl(0); ctx->virt_inst_excp =3D false; @@ -1306,4 +1313,7 @@ void riscv_translate_init(void) "load_res"); load_val =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_= val), "load_val"); + /* Assign var with number of pointer masking masked bits to tcg global= */ + pm_n_bits =3D tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pm_n= _bits), + "pmbits"); } --=20 2.34.1 From nobody Tue May 14 16:39:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[188.255.126.251]) by smtp.gmail.com with ESMTPSA id cb22-20020a170906a45600b0099d804da2e9sm1342667ejb.225.2023.09.08.11.26.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 11:26:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1694197615; x=1694802415; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oCMPg3srOuNK1zxCrcmJhIPfQWCsaR+9i85+FTGMjt4=; b=o93fcAmEhcxP13iEn+QQtJbsETYWpPwSdLdS99bYts2NmtL7pFOqBP60gSc+D35YS9 G9CyDkSt6Sh8eOuyvrdHIpGme1BpbffwxnVJzMWNGgvqwb7BChnQ/aH3w7TAuksIbKJ1 ooSOQ9kMUVbr3WQjqCeoKqVIxy1kIO/tdMk7aovG4KXnUhWAEIXqdktLGiErEMdfDfdU 0BpXC669wliFHRslSn9djas9RAtAATBbcqIQyEzV8OqehYGa1e1vmguTypHpQUYNhlUR PC2I0ct5D1+fl+llI5Huw6WjIi3yxS5kr7QqJC0UrSC08n23OQeFYZONfixNEno1WIpO KTIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694197615; x=1694802415; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694197734710100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 6 ++-- target/riscv/cpu_helper.c | 58 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 17d0088cb4..c87c4f26a2 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -91,11 +91,9 @@ typedef enum { /* Enum holds maximum for N bits to be ignored depending on privilege leve= l */ typedef enum { PM_BARE_N_BITS =3D 16, - PM_SV32_N_BITS =3D 0, PM_SV39_N_BITS =3D 25, PM_SV48_N_BITS =3D 16, PM_SV57_N_BITS =3D 7, - PM_SV64_N_BITS =3D 0, } RISCVZjpmMaxNBits; =20 #define MMU_USER_IDX 3 @@ -633,6 +631,10 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, t= arget_ulong vtype) void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags); =20 +void riscv_cpu_update_mask(CPURISCVState *env); +RISCVZjpmMaxNBits riscv_cpu_pm_get_n_bits(int satp_mode, int priv_mode); +bool riscv_cpu_pm_check_applicable(CPURISCVState *env, int priv_mode); + RISCVException riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask= ); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b3871b0a28..6e68b2fc27 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -144,6 +144,64 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *p= c, *pflags =3D flags; } =20 +/* + * Curernt Zjpm v0.6.1 spec doesn't strictly specify the exact value of N = bits. + * It allows it to be dependent on both translation mode and priv level. + * For now let's ignore priv mode and always return max available value. + */ +RISCVZjpmMaxNBits riscv_cpu_pm_get_n_bits(int satp_mode, int priv_mode) +{ + switch (satp_mode) { + case VM_1_10_MBARE: + return PM_BARE_N_BITS; + case VM_1_10_SV39: + return PM_SV39_N_BITS; + case VM_1_10_SV48: + return PM_SV48_N_BITS; + case VM_1_10_SV57: + return PM_SV57_N_BITS; + default: + g_assert_not_reached(); + } +} + +/* For current priv level check if pointer masking should be applied */ +bool riscv_cpu_pm_check_applicable(CPURISCVState *env, int priv_mode) +{ + /* checks if appropriate extension is present and enable bit is set */ + switch (priv_mode) { + case PRV_M: + return riscv_cpu_cfg(env)->ext_smmjpm && env->mseccfg & MSECCFG_MP= MEN; + case PRV_S: + return riscv_cpu_cfg(env)->ext_smnjpm && env->menvcfg & MENVCFG_SP= MEN; + case PRV_U: + return riscv_cpu_cfg(env)->ext_ssnjpm && env->senvcfg & SENVCFG_UP= MEN; + default: + g_assert_not_reached(); + } + g_assert_not_reached(); + return false; +} + +void riscv_cpu_update_mask(CPURISCVState *env) +{ +#ifndef CONFIG_USER_ONLY + int priv_mode =3D cpu_address_mode(env); + int satp_mode =3D 0; + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + satp_mode =3D get_field(env->satp, SATP32_MODE); + } else { + satp_mode =3D get_field(env->satp, SATP64_MODE); + } + RISCVZjpmMaxNBits n_bits =3D riscv_cpu_pm_get_n_bits(satp_mode, priv_m= ode); + /* in bare mode address is not sign extended */ + env->pm_signext =3D (satp_mode !=3D VM_1_10_MBARE); + /* if pointer masking is applicable set env variable */ + bool applicable =3D riscv_cpu_pm_check_applicable(env, priv_mode); + env->pm_n_bits =3D applicable ? n_bits : 0; +#endif +} + #ifndef CONFIG_USER_ONLY =20 /* --=20 2.34.1 From nobody Tue May 14 16:39:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694197670; cv=none; d=zohomail.com; s=zohoarc; b=eh1P8LFHN6zY9HodjzxGkJa0CjzYlXtuqlBFYaX+6mjaVj+IYTKKsp3hfGS/yDOcplTIGX9VP8bxKTZ8rhIXfsYZNVXd/PrMEQYovBxPZjqETUrNHxTV89+v79wYY69nctWs5sCSrxiGjt6CSnV62oQY5n01uKjtRkJzLSmgz4k= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=baturo.alexey@gmail.com; helo=mail-lf1-x12a.google.com X-Spam_score_int: -7 X-Spam_score: -0.8 X-Spam_bar: / X-Spam_report: (-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, TVD_PH_SUBJ_META1=1.249, T_SPF_HELO_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694197671365100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Alexey Baturo --- target/riscv/translate.c | 21 +++++++++++++++++++-- target/riscv/vector_helper.c | 7 +++++++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3434ba58b6..4aa0e2b9e1 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -581,7 +581,15 @@ static TCGv get_address(DisasContext *ctx, int rs1, in= t imm) TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_addi_tl(addr, src1, imm); - if (get_address_xl(ctx) =3D=3D MXL_RV32) { + if (ctx->pm_enabled) { + tcg_gen_shl_tl(addr, addr, pm_n_bits); + /* sign extend address by first non-masked bit otherwise zero exte= nd */ + if (ctx->pm_signext) { + tcg_gen_sar_tl(addr, addr, pm_n_bits); + } else { + tcg_gen_shr_tl(addr, addr, pm_n_bits); + } + } else if (get_address_xl(ctx) =3D=3D MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } =20 @@ -595,7 +603,16 @@ static TCGv get_address_indexed(DisasContext *ctx, int= rs1, TCGv offs) TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); =20 tcg_gen_add_tl(addr, src1, offs); - if (get_xl(ctx) =3D=3D MXL_RV32) { + /* sign extend address by first non-masked bit */ + if (ctx->pm_enabled) { + tcg_gen_shl_tl(addr, addr, pm_n_bits); + /* sign extend address by first non-masked bit otherwise zero exte= nd */ + if (ctx->pm_signext) { + tcg_gen_sar_tl(addr, addr, pm_n_bits); + } else { + tcg_gen_shr_tl(addr, addr, pm_n_bits); + } + } else if (get_xl(ctx) =3D=3D MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } return addr; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index af07e1067d..d3ddc2fd41 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -169,6 +169,13 @@ static inline uint32_t vext_get_total_elems(CPURISCVSt= ate *env, uint32_t desc, =20 static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad= dr) { + addr =3D addr << env->pm_n_bits; + /* sign/zero extend masked address by N-1 bit */ + if (env->pm_signext) { + addr =3D (target_long)addr >> env->pm_n_bits; + } else { + addr =3D addr >> env->pm_n_bits; + } return addr; } =20 --=20 2.34.1 From nobody Tue May 14 16:39:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1694197731; cv=none; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=baturo.alexey@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1694197732640100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 1 + target/riscv/cpu_helper.c | 1 + target/riscv/csr.c | 4 ++++ target/riscv/machine.c | 1 + target/riscv/pmp.c | 1 + 5 files changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index af8f16b94f..928d4b5f5c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -891,6 +891,7 @@ static void riscv_cpu_reset_hold(Object *obj) } #endif env->xl =3D riscv_cpu_mxl(env); + riscv_cpu_update_mask(env); cs->exception_index =3D RISCV_EXCP_NONE; env->load_res =3D -1; set_default_nan_mode(1, &env->fp_status); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6e68b2fc27..6cc1df4fcb 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -689,6 +689,7 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulon= g newpriv) /* tlb_flush is unnecessary as mode is contained in mmu_idx */ env->priv =3D newpriv; env->xl =3D cpu_recompute_xl(env); + riscv_cpu_update_mask(env); =20 /* * Clear the load reservation - otherwise a reservation placed in one diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c7e59168d2..7fe0d83877 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1321,6 +1321,7 @@ static RISCVException write_mstatus(CPURISCVState *en= v, int csrno, env->xl =3D cpu_recompute_xl(env); } =20 + riscv_cpu_update_mask(env); return RISCV_EXCP_NONE; } =20 @@ -1948,6 +1949,7 @@ static RISCVException write_menvcfg(CPURISCVState *en= v, int csrno, } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); =20 + riscv_cpu_update_mask(env); return RISCV_EXCP_NONE; } =20 @@ -2002,6 +2004,8 @@ static RISCVException write_senvcfg(CPURISCVState *en= v, int csrno, mask |=3D SENVCFG_UPMEN; } env->senvcfg =3D (env->senvcfg & ~mask) | (val & mask); + + riscv_cpu_update_mask(env); return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index d50ff5421f..e63a9fc95f 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -258,6 +258,7 @@ static int riscv_cpu_post_load(void *opaque, int versio= n_id) CPURISCVState *env =3D &cpu->env; =20 env->xl =3D cpu_recompute_xl(env); + riscv_cpu_update_mask(env); return 0; } =20 diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 0db49173ef..5ca536bac0 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -586,6 +586,7 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong= val) } =20 env->mseccfg =3D val; + riscv_cpu_update_mask(env); } =20 /* --=20 2.34.1