在 2023/8/22 下午3:13, Philippe Mathieu-Daudé 写道:
> Based-on: https://patchew.org/QEMU/20230821125959.28666-1-philmd@linaro.org/
>
> (all series reviewed, for Song Gao to pick whichever v4/v5 is preferred)
>
> Hi,
>
> This series adds some checks before translating instructions
>
> This includes:
>
> CPUCFG[1].IOCSR
>
> CPUCFG[2].FP
> CPUCFG[2].FP_SP
> CPUCFG[2].FP_DP
> CPUCFG[2].LSPW
> CPUCFG[2].LAM
> CPUCFG[2].LSX
>
> V5:
> - Split 2 patches, extracting helpers
> - R-b
> Thanks!
Applied to loongarch-to-apply queue
Thanks.
Song Gao
> V4:
> - Rebase;
> - Split patch 'Add LoongArch32 cpu la132' in two patch; (PMD)
> - Remove unrelated cpucfgX;(PMD)
> - R-b.
>
> V3:
> - Rebase;
> - The la32 instructions following Table 2 at [2].
>
> V2:
> - Add a check parameter to the TRANS macro.
> - remove TRANS_64.
> - Add avail_ALL/64/FP/FP_SP/FP_DP/LSPW/LAM/LSX/IOCSR
> to check instructions.
>
> [1]: https://patchew.org/QEMU/20230809083258.1787464-1-c@jia.je/
> [2]: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#overview-of-basic-integer-instructions
>
> Jiajie Chen (11):
> target/loongarch: Support LoongArch32 TLB entry
> target/loongarch: Support LoongArch32 DMW
> target/loongarch: Support LoongArch32 VPPN
> target/loongarch: Add LA64 & VA32 to DisasContext
> target/loongarch: Extract make_address_x() helper
> target/loongarch: Extract make_address_i() helper
> target/loongarch: Extract make_address_pc() helper
> target/loongarch: Extract set_pc() helper
> target/loongarch: Truncate high 32 bits of address in VA32 mode
> target/loongarch: Sign extend results in VA32 mode
> target/loongarch: Add LoongArch32 cpu la132
>
> Song Gao (8):
> target/loongarch: Add a check parameter to the TRANS macro
> target/loongarch: Add avail_64 to check la64-only instructions
> hw/loongarch: Remove restriction of la464 cores in the virt machine
> target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions
> target/loongarch: Add avail_LSPW to check LSPW instructions
> target/loongarch: Add avail_LAM to check atomic instructions
> target/loongarch: Add avail_LSX to check LSX instructions
> target/loongarch: Add avail_IOCSR to check iocsr instructions
>
> target/loongarch/cpu-csr.h | 22 +-
> target/loongarch/cpu.h | 22 +
> target/loongarch/translate.h | 19 +-
> hw/loongarch/virt.c | 5 -
> target/loongarch/cpu.c | 46 +-
> target/loongarch/gdbstub.c | 2 +-
> target/loongarch/op_helper.c | 4 +-
> target/loongarch/tlb_helper.c | 66 +-
> target/loongarch/translate.c | 46 +
> target/loongarch/insn_trans/trans_arith.c.inc | 98 +-
> .../loongarch/insn_trans/trans_atomic.c.inc | 85 +-
> target/loongarch/insn_trans/trans_bit.c.inc | 56 +-
> .../loongarch/insn_trans/trans_branch.c.inc | 27 +-
> target/loongarch/insn_trans/trans_extra.c.inc | 24 +-
> .../loongarch/insn_trans/trans_farith.c.inc | 96 +-
> target/loongarch/insn_trans/trans_fcmp.c.inc | 8 +
> target/loongarch/insn_trans/trans_fcnv.c.inc | 56 +-
> .../loongarch/insn_trans/trans_fmemory.c.inc | 62 +-
> target/loongarch/insn_trans/trans_fmov.c.inc | 52 +-
> target/loongarch/insn_trans/trans_lsx.c.inc | 1434 +++++++++--------
> .../loongarch/insn_trans/trans_memory.c.inc | 118 +-
> .../insn_trans/trans_privileged.c.inc | 24 +-
> target/loongarch/insn_trans/trans_shift.c.inc | 34 +-
> 23 files changed, 1386 insertions(+), 1020 deletions(-)
>