This is one of the first generation Armv9 cores, and gives us something
concrete to test in that area.  Notably, it supports MTE.

Changes for v2:
  * Check GMBS during realize.
  * Fix access checks for neoverse implementation registers.
    Mostly just traps EL1/EL2 if EL2/EL3 enabled.
  * Add make_ccsidr64 helper.
  * Reduce MTE with no tag memory to MTE=1.
  * Suppress FEAT_TRBE.
  * Implement HPDS2 as a no-op.
  * Rewrite a710 implementation registers; do try to share code with
    neoverse, because the traps are different.  This of course solves
    the renaming and renumbering issues too.


r~


Richard Henderson (11):
  target/arm: Reduce dcz_blocksize to uint8_t
  target/arm: Allow cpu to configure GM blocksize
  target/arm: Support more GM blocksizes
  target/arm: When tag memory is not present, set MTE=1
  target/arm: Introduce make_ccsidr64
  target/arm: Apply access checks to neoverse-n1 special registers
  target/arm: Apply access checks to neoverse-v1 special registers
  target/arm: Implement RMR_EL3 for neoverse-v1
  target/arm: Suppress FEAT_TRBE (Trace Buffer Extension)
  target/arm: Implement FEAT_HPDS2 as a no-op
  target/arm: Implement cortex-a710

 docs/system/arm/emulation.rst  |   1 +
 docs/system/arm/virt.rst       |   1 +
 target/arm/cpregs.h            |   2 +
 target/arm/cpu.h               |   5 +-
 target/arm/internals.h         |   6 -
 target/arm/tcg/translate.h     |   2 +
 hw/arm/virt.c                  |   1 +
 target/arm/cpu.c               |  28 ++-
 target/arm/helper.c            |  15 +-
 target/arm/tcg/cpu32.c         |   2 +-
 target/arm/tcg/cpu64.c         | 347 ++++++++++++++++++++++++++++++---
 target/arm/tcg/mte_helper.c    |  90 +++++++--
 target/arm/tcg/translate-a64.c |   5 +-
 13 files changed, 437 insertions(+), 68 deletions(-)

-- 
2.34.1

On Fri, 11 Aug 2023 at 22:42, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This is one of the first generation Armv9 cores, and gives us something
> concrete to test in that area.  Notably, it supports MTE.
>
> Changes for v2:
>   * Check GMBS during realize.
>   * Fix access checks for neoverse implementation registers.
>     Mostly just traps EL1/EL2 if EL2/EL3 enabled.
>   * Add make_ccsidr64 helper.
>   * Reduce MTE with no tag memory to MTE=1.
>   * Suppress FEAT_TRBE.
>   * Implement HPDS2 as a no-op.
>   * Rewrite a710 implementation registers; do try to share code with
>     neoverse, because the traps are different.  This of course solves
>     the renaming and renumbering issues too.
>

I've applied patches 1-7, 9 and 10 to target-arm.next.

thanks
-- PMM