While I was fixing a ptw bug recently, I noticed that we had a
somewhat confusing mix of ptw->in_space and ptw->in_secure, where in
theory the two are supposed to be in sync and you can figure out the
in_secure state from the in_space.  This patch series' principal aim
is to clean that up by removing the in_secure and out_secure fields
in the S1Translate struct.

The first three patches are fixes for (minor) bugs I noticed
while I was trying to do this refactoring because they're
in or around places that were using in_secure.
The next four are basically plumbing: passing ARMSecurityState
arguments instead of boolean is_secure arguments.
The next four patches then can get rid of uses of the
in_secure and out_secure fields and drop them entirely.
Finally, the last four patches are minor bug fixes for
various corner cases that I noticed while I was testing this.

Changes v1->v2:
 * in patch 6, avoid calling arm_hcr_el2_eff_secstate()
   with ARMSS_Root, rather than making it return 0
 * new patch 7 ("Pass an ARMSecuritySpace to
   arm_is_el2_enabled_secstate()")

Only patches 6 and 7 still need review.

thanks
-- PMM

Peter Maydell (15):
  target/arm/ptw: Don't set fi->s1ptw for UnsuppAtomicUpdate fault
  target/arm/ptw: Don't report GPC faults on stage 1 ptw as stage2
    faults
  target/arm/ptw: Set s1ns bit in fault info more consistently
  target/arm/ptw: Pass ptw into get_phys_addr_pmsa*() and
    get_phys_addr_disabled()
  target/arm/ptw: Pass ARMSecurityState to regime_translation_disabled()
  target/arm/ptw: Pass an ARMSecuritySpace to arm_hcr_el2_eff_secstate()
  target/arm: Pass an ARMSecuritySpace to arm_is_el2_enabled_secstate()
  target/arm/ptw: Only fold in NSTable bit effects in Secure state
  target/arm/ptw: Remove last uses of ptw->in_secure
  target/arm/ptw: Remove S1Translate::in_secure
  target/arm/ptw: Drop S1Translate::out_secure
  target/arm/ptw: Set attributes correctly for MMU disabled data
    accesses
  target/arm/ptw: Check for block descriptors at invalid levels
  target/arm/ptw: Report stage 2 fault level for stage 2 faults on stage
    1 ptw
  target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types

 target/arm/cpu.h    |  15 ++--
 target/arm/helper.c |  23 +++++-
 target/arm/ptw.c    | 192 +++++++++++++++++++++++++++-----------------
 3 files changed, 146 insertions(+), 84 deletions(-)

-- 
2.34.1