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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id x7-20020adff647000000b00317731a6e07sm18944519wrp.62.2023.08.02.05.49.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Aug 2023 05:49:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1690980556; x=1691585356; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=rqRK90FQlpUq5FFVIJ9r0kLO6CGSKsy3LdjgO9tyOyE=; b=jvNc/hV+EBALMH2Uz8rb2a3YN+IYDFQpQ5hn3hcwCCLopeZBDEnwVpi/lMND1/7hm+ lylEOjqHXN3SXxBb6CpK18XvpTkHDry5yOnbar3Nz4Ghq8dyLazcA9X+Fe+S3k8K0r+h ysw/7mjk0p1Ka6CtUOx22nI/1+WuKVdgyLwEgui1S2OE+OfcPGSTXuLQ/paeEizkAcZm p4kpyMl/iHzpUZjfsIHTIPhsbfoTDaHiV/lNdt498Jgej/YE0uL8PBueavKvGmVTyqDN qq45wAfEaNSOUazsFR/sGPtbCAgen99Cv2rVB6nn57Cy/FFAvvCJdTfDo4si1/5cp3T5 JXbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690980556; x=1691585356; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=rqRK90FQlpUq5FFVIJ9r0kLO6CGSKsy3LdjgO9tyOyE=; b=PbJGsD2UqZEV9HgUvrYgHlerjS0DQwZyuuwfmM6p5zn1LcIsypTu5eBsDVlR3F5t4t 5YJOUrqb6YiO9ZyJpElXFhOUW0G3QrZ2vEzE6EWgkZQFGMtpLo/X4u66W7BDwHSss1dO V8c/DmqUM3RnrpvbQ01AHOiA7WF0ikgCCZ2CsxWt3F0iiypD4FvMPC23m6HyhfE2CeZ6 mMp4mMrd1gvPPqwxd1LDefcJTxFW2MxFOfCavC5ohEW42IzO4vhFdYu/we/fUfNRbY/w UuRT/2z97iCs9o3gmzGFxdkCCSREDb7CZqGvVV0IUxSOVfdXymnbQN7klq379FXxNb6Z 5yHg== X-Gm-Message-State: ABy/qLakEWemp8oDVtXeI28tSKt0gCUX+vxi3PwksvTTgUlLh5dxmrz/ SGMFAx1phAUY+fTAcmfAyb1rsfWV+kf214GBw8o= X-Google-Smtp-Source: APBJJlHcUCn0dPGRvBXhsnpWNgpLL3JdVGN3i34XLM+G1ImV6yQV8iTamKznoIV5l+MUDIFcBgt2Pw== X-Received: by 2002:a5d:50d0:0:b0:317:3c89:7f03 with SMTP id f16-20020a5d50d0000000b003173c897f03mr5194854wrt.5.1690980556449; Wed, 02 Aug 2023 05:49:16 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: Rob Bradford , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [PATCH] target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren Date: Wed, 2 Aug 2023 13:49:06 +0100 Message-ID: <20230802124906.24197-1-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=rbradford@rivosinc.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20221208.gappssmtp.com) X-ZM-MESSAGEID: 1690980638732100001 Content-Type: text/plain; charset="utf-8" These are WARL fields - zero out the bits for unavailable counters and special case the TM bit in mcountinhibit which is hardwired to zero. This patch achieves this by modifying the value written so that any use of the field will see the correctly masked bits. Tested by modifying OpenSBI to write max value to these CSRs and upon subsequent read the appropriate number of bits for number of PMUs is enabled and the TM bit is zero in mcountinhibit. Signed-off-by: Rob Bradford Acked-by: Alistair Francis Reviewed-by: Atish Patra --- target/riscv/csr.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ea7585329e..495ff6a9c2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1834,8 +1834,11 @@ static RISCVException write_mcountinhibit(CPURISCVSt= ate *env, int csrno, { int cidx; PMUCTRState *counter; + RISCVCPU *cpu =3D env_archcpu(env); =20 - env->mcountinhibit =3D val; + /* WARL register - disable unavailable counters; TM bit is always 0 */ + env->mcountinhibit =3D + val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_IR); =20 /* Check if any other counter is also monitoring cycles/instructions */ for (cidx =3D 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) { @@ -1858,7 +1861,11 @@ static RISCVException read_mcounteren(CPURISCVState = *env, int csrno, static RISCVException write_mcounteren(CPURISCVState *env, int csrno, target_ulong val) { - env->mcounteren =3D val; + RISCVCPU *cpu =3D env_archcpu(env); + + /* WARL register - disable unavailable counters */ + env->mcounteren =3D val & (cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTE= REN_TM | + COUNTEREN_IR); return RISCV_EXCP_NONE; } =20 --=20 2.41.0