From nobody Wed May 15 12:14:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1690885974; cv=none; d=zohomail.com; s=zohoarc; b=lxZc3SuWr10Q8Wrm4YDpl9/6qtgK4N1XGmkN5fshRlOV7sXkvHH4Cn1rfMaj0WIHM/weJX3GUHCnZNG+w3/GM5hYmwGLGTS4IUGp6CzOvxHtTQLYHjVuYlgXcI2EWRdH3hpYQ/O0rTiphqXfTk8j88LoWgG9CD989BnnX0+nsnk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690885974; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=o6CGEEDr655P3D8iKGlyZyEZ7GpfiY0hvrvMGUmFOak=; b=fDJF+P5Fqg13b2qdaMfZMjILAVh2K90y0wcxKVwpQ8fS6KIC+wD8iNtKrchB8hPgrGlgHwRwYf8Gztj3Kgkn4dznjIiS9/m3Zv9D9qAH5ymrLrv/gZj6NsSRj2DHGPlfixy9Zj6BzJlDorvPyJdwJsy+yZVUAAyJxS+3eW+2pLk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690885974625493.9087395354469; Tue, 1 Aug 2023 03:32:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qQmg5-00080t-Ay; Tue, 01 Aug 2023 06:32:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qQmg3-00080J-TA for qemu-devel@nongnu.org; Tue, 01 Aug 2023 06:32:31 -0400 Received: from [192.55.52.88] (helo=mgamail.intel.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qQmg1-0002Cy-UH for qemu-devel@nongnu.org; Tue, 01 Aug 2023 06:32:31 -0400 Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Aug 2023 03:25:07 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.28]) by fmsmga007.fm.intel.com with ESMTP; 01 Aug 2023 03:25:04 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690885949; x=1722421949; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1NRuIDlGO7uPFBN38ffRjwuoPxpKblB5uTvtR3cBprc=; b=Vmk7iVdnrgDoLV5ajwKqIiwK4AzTv2iAD1nZ0086o1LuisgOuXtiOQoA 7D7PIaBetaQYPXk2vOz9VCI+F3yu7z+GobR29MhRSomNUM9DAuPsmiVtq AgAKGjItUnBrRVUQizidhJOgDw1Jj4q7hTv/03wJCL1oROhaaU2nQXceC bWyxGJUM8F1NPJURYnd3OSDH+VIkSfY/LXQevlgq5m7xJRcyGQxBf1Iu8 liU+YTWN5Z84tiEFHdYTalGUZfCVbhwTl6Xp2U1V7WpYeHCutmo2oJ1zm SWJ8tacpBEqtu+bEO066R7/01iUdcKLvWcVp5ci9CuGomdektd39TqXt2 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="400210986" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="400210986" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="731931984" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="731931984" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu Subject: [PATCH v3 01/17] i386: Fix comment style in topology.h Date: Tue, 1 Aug 2023 18:35:11 +0800 Message-Id: <20230801103527.397756-2-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1690885975227100001 From: Zhao Liu For function comments in this file, keep the comment style consistent with other places. Signed-off-by: Zhao Liu Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Michael S. Tsirkin Reviewed-by: Xiaoyao Li --- include/hw/i386/topology.h | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 81573f6cfde0..5a19679f618b 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -24,7 +24,8 @@ #ifndef HW_I386_TOPOLOGY_H #define HW_I386_TOPOLOGY_H =20 -/* This file implements the APIC-ID-based CPU topology enumeration logic, +/* + * This file implements the APIC-ID-based CPU topology enumeration logic, * documented at the following document: * Intel=C2=AE 64 Architecture Processor Topology Enumeration * http://software.intel.com/en-us/articles/intel-64-architecture-proces= sor-topology-enumeration/ @@ -41,7 +42,8 @@ =20 #include "qemu/bitops.h" =20 -/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC suppo= rt +/* + * APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC suppo= rt */ typedef uint32_t apic_id_t; =20 @@ -58,8 +60,7 @@ typedef struct X86CPUTopoInfo { unsigned threads_per_core; } X86CPUTopoInfo; =20 -/* Return the bit width needed for 'count' IDs - */ +/* Return the bit width needed for 'count' IDs */ static unsigned apicid_bitwidth_for_count(unsigned count) { g_assert(count >=3D 1); @@ -67,15 +68,13 @@ static unsigned apicid_bitwidth_for_count(unsigned coun= t) return count ? 32 - clz32(count) : 0; } =20 -/* Bit width of the SMT_ID (thread ID) field on the APIC ID - */ +/* Bit width of the SMT_ID (thread ID) field on the APIC ID */ static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info) { return apicid_bitwidth_for_count(topo_info->threads_per_core); } =20 -/* Bit width of the Core_ID field - */ +/* Bit width of the Core_ID field */ static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info) { return apicid_bitwidth_for_count(topo_info->cores_per_die); @@ -87,8 +86,7 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo *t= opo_info) return apicid_bitwidth_for_count(topo_info->dies_per_pkg); } =20 -/* Bit offset of the Core_ID field - */ +/* Bit offset of the Core_ID field */ static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info) { return apicid_smt_width(topo_info); @@ -100,14 +98,14 @@ static inline unsigned apicid_die_offset(X86CPUTopoInf= o *topo_info) return apicid_core_offset(topo_info) + apicid_core_width(topo_info); } =20 -/* Bit offset of the Pkg_ID (socket ID) field - */ +/* Bit offset of the Pkg_ID (socket ID) field */ static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info) { return apicid_die_offset(topo_info) + apicid_die_width(topo_info); } =20 -/* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID +/* + * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. */ @@ -120,7 +118,8 @@ static inline apic_id_t x86_apicid_from_topo_ids(X86CPU= TopoInfo *topo_info, topo_ids->smt_id; } =20 -/* Calculate thread/core/package IDs for a specific topology, +/* + * Calculate thread/core/package IDs for a specific topology, * based on (contiguous) CPU index */ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info, @@ -137,7 +136,8 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo= *topo_info, topo_ids->smt_id =3D cpu_index % nr_threads; } =20 -/* Calculate thread/core/package IDs for a specific topology, +/* + * Calculate thread/core/package IDs for a specific topology, * based on APIC ID */ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, @@ -155,7 +155,8 @@ static inline void x86_topo_ids_from_apicid(apic_id_t a= picid, topo_ids->pkg_id =3D apicid >> apicid_pkg_offset(topo_info); } =20 -/* Make APIC ID for the CPU 'cpu_index' +/* + * Make APIC ID for the CPU 'cpu_index' * * 'cpu_index' is a sequential, contiguous ID for the CPU. */ --=20 2.34.1 From nobody Wed May 15 12:14:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1690885789; cv=none; d=zohomail.com; s=zohoarc; b=E1TPGQCF5/952EodJuwJSH8cIIPp16AMsiVLneV1okwLX+8/0NqwMAH6YUhlo3MIdAMiT61wPqWGCf8dcuzeK4N1zeVhR416xW5CroyflHpI846wOzwNKZyvhmAfHqp6//mWyaDKFPmqfGYdN2fwU799h3T5TETJOYFK0tmL/8w= ARC-Message-Signature: i=1; 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Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu , Yongwei Ma Subject: [PATCH v3 02/17] tests: Rename test-x86-cpuid.c to test-x86-topo.c Date: Tue, 1 Aug 2023 18:35:12 +0800 Message-Id: <20230801103527.397756-3-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1690885792103100003 From: Zhao Liu In fact, this unit tests APIC ID other than CPUID. Rename to test-x86-topo.c to make its name more in line with its actual content. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Changes since v1: * Rename test-x86-apicid.c to test-x86-topo.c. (Yanan) --- MAINTAINERS | 2 +- tests/unit/meson.build | 4 ++-- tests/unit/{test-x86-cpuid.c =3D> test-x86-topo.c} | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) rename tests/unit/{test-x86-cpuid.c =3D> test-x86-topo.c} (99%) diff --git a/MAINTAINERS b/MAINTAINERS index 12e59b6b27de..51ba3d593e90 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1719,7 +1719,7 @@ F: include/hw/southbridge/ich9.h F: include/hw/southbridge/piix.h F: hw/isa/apm.c F: include/hw/isa/apm.h -F: tests/unit/test-x86-cpuid.c +F: tests/unit/test-x86-topo.c F: tests/qtest/test-x86-cpuid-compat.c =20 PC Chipset diff --git a/tests/unit/meson.build b/tests/unit/meson.build index 93977cc32d2b..39b5d0007c69 100644 --- a/tests/unit/meson.build +++ b/tests/unit/meson.build @@ -21,8 +21,8 @@ tests =3D { 'test-opts-visitor': [testqapi], 'test-visitor-serialization': [testqapi], 'test-bitmap': [], - # all code tested by test-x86-cpuid is inside topology.h - 'test-x86-cpuid': [], + # all code tested by test-x86-topo is inside topology.h + 'test-x86-topo': [], 'test-cutils': [], 'test-div128': [], 'test-shift128': [], diff --git a/tests/unit/test-x86-cpuid.c b/tests/unit/test-x86-topo.c similarity index 99% rename from tests/unit/test-x86-cpuid.c rename to tests/unit/test-x86-topo.c index bfabc0403a1a..2b104f86d7c2 100644 --- a/tests/unit/test-x86-cpuid.c +++ b/tests/unit/test-x86-topo.c @@ -1,5 +1,5 @@ /* - * Test code for x86 CPUID and Topology functions + * Test code for x86 APIC ID and Topology functions * * Copyright (c) 2012 Red Hat Inc. * --=20 2.34.1 From nobody Wed May 15 12:14:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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d="scan'208";a="400211021" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="731932011" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="731932011" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu , Zhuocheng Ding Subject: [PATCH v3 03/17] softmmu: Fix CPUSTATE.nr_cores' calculation Date: Tue, 1 Aug 2023 18:35:13 +0800 Message-Id: <20230801103527.397756-4-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1690886002417100003 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding From CPUState.nr_cores' comment, it represents "number of cores within this CPU package". After 003f230e37d7 ("machine: Tweak the order of topology members in struct CpuTopology"), the meaning of smp.cores changed to "the number of cores in one die", but this commit missed to change CPUState.nr_cores' caculation, so that CPUState.nr_cores became wrong and now it misses to consider numbers of clusters and dies. At present, only i386 is using CPUState.nr_cores. But as for i386, which supports die level, the uses of CPUState.nr_cores are very confusing: Early uses are based on the meaning of "cores per package" (before die is introduced into i386), and later uses are based on "cores per die" (after die's introduction). This difference is due to that commit a94e1428991f ("target/i386: Add CPUID.1F generation support for multi-dies PCMachine") misunderstood that CPUState.nr_cores means "cores per die" when caculated CPUID.1FH.01H:EBX. After that, the changes in i386 all followed this wrong understanding. With the influence of 003f230e37d7 and a94e1428991f, for i386 currently the result of CPUState.nr_cores is "cores per die", thus the original uses of CPUState.cores based on the meaning of "cores per package" are wrong when mutiple dies exist: 1. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.01H:EBX[bits 23:16] is incorrect because it expects "cpus per package" but now the result is "cpus per die". 2. In cpu_x86_cpuid() of target/i386/cpu.c, for all leaves of CPUID.04H: EAX[bits 31:26] is incorrect because they expect "cpus per package" but now the result is "cpus per die". The error not only impacts the EAX caculation in cache_info_passthrough case, but also impacts other cases of setting cache topology for Intel CPU according to cpu topology (specifically, the incoming parameter "num_cores" expects "cores per package" in encode_cache_cpuid4()). 3. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.0BH.01H:EBX[bits 15:00] is incorrect because the EBX of 0BH.01H (core level) expects "cpus per package", which may be different with 1FH.01H (The reason is 1FH can support more levels. For QEMU, 1FH also supports die, 1FH.01H:EBX[bits 15:00] expects "cpus per die"). 4. In cpu_x86_cpuid() of target/i386/cpu.c, when CPUID.80000001H is caculated, here "cpus per package" is expected to be checked, but in fact, now it checks "cpus per die". Though "cpus per die" also works for this code logic, this isn't consistent with AMD's APM. 5. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.80000008H:ECX expects "cpus per package" but it obtains "cpus per die". 6. In simulate_rdmsr() of target/i386/hvf/x86_emu.c, in kvm_rdmsr_core_thread_count() of target/i386/kvm/kvm.c, and in helper_rdmsr() of target/i386/tcg/sysemu/misc_helper.c, MSR_CORE_THREAD_COUNT expects "cpus per package" and "cores per package", but in these functions, it obtains "cpus per die" and "cores per die". On the other hand, these uses are correct now (they are added in/after a94e1428991f): 1. In cpu_x86_cpuid() of target/i386/cpu.c, topo_info.cores_per_die meets the actual meaning of CPUState.nr_cores ("cores per die"). 2. In cpu_x86_cpuid() of target/i386/cpu.c, vcpus_per_socket (in CPUID. 04H's caculation) considers number of dies, so it's correct. 3. In cpu_x86_cpuid() of target/i386/cpu.c, CPUID.1FH.01H:EBX[bits 15:00] needs "cpus per die" and it gets the correct result, and CPUID.1FH.02H:EBX[bits 15:00] gets correct "cpus per package". When CPUState.nr_cores is correctly changed to "cores per package" again , the above errors will be fixed without extra work, but the "currently" correct cases will go wrong and need special handling to pass correct "cpus/cores per die" they want. Thus in this patch, we fix CPUState.nr_cores' caculation to fit the original meaning "cores per package", as well as changing calculation of topo_info.cores_per_die, vcpus_per_socket and CPUID.1FH. In addition, in the nr_threads' comment, specify it represents the number of threads in the "core" to avoid confusion, and also add comment for nr_dies in CPUX86State. Fixes: a94e1428991f ("target/i386: Add CPUID.1F generation support for mult= i-dies PCMachine") Fixes: 003f230e37d7 ("machine: Tweak the order of topology members in struc= t CpuTopology") Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- Changes since v2: * Use wrapped helper to get cores per socket in qemu_init_vcpu(). Changes since v1: * Add comment for nr_dies in CPUX86State. (Yanan) --- include/hw/core/cpu.h | 2 +- softmmu/cpus.c | 2 +- target/i386/cpu.c | 9 ++++----- target/i386/cpu.h | 1 + 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index fdcbe8735258..57f4d50ace72 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -277,7 +277,7 @@ struct qemu_work_item; * See TranslationBlock::TCG CF_CLUSTER_MASK. * @tcg_cflags: Pre-computed cflags for this cpu. * @nr_cores: Number of cores within this CPU package. - * @nr_threads: Number of threads within this CPU. + * @nr_threads: Number of threads within this CPU core. * @running: #true if CPU is currently running (lockless). * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; * valid under cpu_list_lock. diff --git a/softmmu/cpus.c b/softmmu/cpus.c index fed20ffb5dd2..984558d7b245 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -630,7 +630,7 @@ void qemu_init_vcpu(CPUState *cpu) { MachineState *ms =3D MACHINE(qdev_get_machine()); =20 - cpu->nr_cores =3D ms->smp.cores; + cpu->nr_cores =3D machine_topo_get_cores_per_socket(ms); cpu->nr_threads =3D ms->smp.threads; cpu->stopped =3D true; cpu->random_seed =3D qemu_guest_random_seed_thread_part1(); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 97ad229d8ba3..50613cd04612 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6011,7 +6011,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, X86CPUTopoInfo topo_info; =20 topo_info.dies_per_pkg =3D env->nr_dies; - topo_info.cores_per_die =3D cs->nr_cores; + topo_info.cores_per_die =3D cs->nr_cores / env->nr_dies; topo_info.threads_per_core =3D cs->nr_threads; =20 /* Calculate & apply limits for different index ranges */ @@ -6087,8 +6087,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, */ if (*eax & 31) { int host_vcpus_per_cache =3D 1 + ((*eax & 0x3FFC000) >> 14= ); - int vcpus_per_socket =3D env->nr_dies * cs->nr_cores * - cs->nr_threads; + int vcpus_per_socket =3D cs->nr_cores * cs->nr_threads; if (cs->nr_cores > 1) { *eax &=3D ~0xFC000000; *eax |=3D (pow2ceil(cs->nr_cores) - 1) << 26; @@ -6266,12 +6265,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, break; case 1: *eax =3D apicid_die_offset(&topo_info); - *ebx =3D cs->nr_cores * cs->nr_threads; + *ebx =3D topo_info.cores_per_die * topo_info.threads_per_core; *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; case 2: *eax =3D apicid_pkg_offset(&topo_info); - *ebx =3D env->nr_dies * cs->nr_cores * cs->nr_threads; + *ebx =3D cs->nr_cores * cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_DIE; break; default: diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e0771a10433b..7638128d59cc 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1878,6 +1878,7 @@ typedef struct CPUArchState { =20 TPRAccess tpr_access_type; =20 + /* Number of dies within this CPU package. */ unsigned nr_dies; } CPUX86State; =20 --=20 2.34.1 From nobody Wed May 15 12:14:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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d="scan'208";a="400211046" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="731932031" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="731932031" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu , Robert Hoo Subject: [PATCH v3 04/17] i386/cpu: Fix i/d-cache topology to core level for Intel CPU Date: Tue, 1 Aug 2023 18:35:14 +0800 Message-Id: <20230801103527.397756-5-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1690886071864100012 Content-Type: text/plain; charset="utf-8" From: Zhao Liu For i-cache and d-cache, the maximum IDs for CPUs sharing cache ( CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]) are both 0, and this means i-cache and d-cache are shared in the SMT level. This is correct if there's single thread per core, but is wrong for the hyper threading case (one core contains multiple threads) since the i-cache and d-cache are shared in the core level other than SMT level. For AMD CPU, commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information for cpuid 0x8000001D") has already introduced i/d cache topology as core level by default. Therefore, in order to be compatible with both multi-threaded and single-threaded situations, we should set i-cache and d-cache be shared at the core level by default. This fix changes the default i/d cache topology from per-thread to per-core. Potentially, this change in L1 cache topology may affect the performance of the VM if the user does not specifically specify the topology or bind the vCPU. However, the way to achieve optimal performance should be to create a reasonable topology and set the appropriate vCPU affinity without relying on QEMU's default topology structure. Fixes: 7e3482f82480 ("i386: Helpers to encode cache information consistentl= y") Suggested-by: Robert Hoo Signed-off-by: Zhao Liu Reviewed-by: Xiaoyao Li --- Changes since v1: * Split this fix from the patch named "i386/cpu: Fix number of addressable IDs in CPUID.04H". * Add the explanation of the impact on performance. (Xiaoyao) --- target/i386/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 50613cd04612..b439a05244ee 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6104,12 +6104,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, switch (count) { case 0: /* L1 dcache info */ encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - 1, cs->nr_cores, + cs->nr_threads, cs->nr_cores, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - 1, cs->nr_cores, + cs->nr_threads, cs->nr_cores, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ --=20 2.34.1 From nobody Wed May 15 12:14:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1690886101; cv=none; d=zohomail.com; s=zohoarc; b=kjP9YinUeP2cb9BQETkOuysySd1OJap4/ke30hE7Y0yr2NzjEabbiEvUhDBNmGkASaI/LUuLfkbmYyffh+ptTrVZaIgNhwtpD7T0mkQP3c2rHjac9MXRw1QHKdwt0yp41/9U0REr8uM/qHuuh/8LdlN1DtrCfo2Y+aPJTgYqdT8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690886101; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AyK4BmcPlOYyj2ShuVfO/0vDKYogZMSglAL/ZK2/FeU=; b=b4LGIfLM2W6VDnG+9kYYZAmyEt7m3ReyYVKnMSo1AK2reV037TchYU2SwxAyJjD/8E52JleYnY4LHsHLGbOifnlevwHR6/snpI8BLe55o+QtTOHOLlOzV6cmUmPDQ4fOcFiXOKGvQcgAH7LPrmmjHt1agAOUH7gVvRS1yrvuXS8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690886101330648.5630265731331; Tue, 1 Aug 2023 03:35:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qQmgP-000843-4u; Tue, 01 Aug 2023 06:32:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qQmgO-00083t-9F for qemu-devel@nongnu.org; Tue, 01 Aug 2023 06:32:52 -0400 Received: from [192.55.52.88] (helo=mgamail.intel.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qQmgM-00032u-J9 for qemu-devel@nongnu.org; Tue, 01 Aug 2023 06:32:52 -0400 Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Aug 2023 03:25:20 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.28]) by fmsmga007.fm.intel.com with ESMTP; 01 Aug 2023 03:25:17 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690885970; x=1722421970; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=79Ftd53nq2U2l6sa4S0yiht7Zx8i6hIdkp6FoTHO65U=; b=hI4Q3fG4r+MTBSxr3L/EJWnC9f/6acSnnJTu+djZHRZleKslTHhKRQGA ljoEC1ZrFrwLLiMJaglXMOuawa01yb/Z32by8NgvoVHsQkk0jURoow90o jKEUySfWKAu19j+zsBZ1WYeqG+ERvwHL6HM/9DWUtDK+rC82un7AlKOen 4MDfvHrANlYX5Ks/b/+VJrnGHLaYpLsR8qjv4RYQR3PlzSiTgv/0MEEUQ Nn0Edg6p3rmWUL37U/0OgZaowTMMc0coSGtsMUPMl0FE74v5U70b7YUFN vJEkCkOJZe8/2jL/gsudR5gcuZPGhNp0Yb4QLH0BX+oK+JzHDyMD7kQu1 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="400211072" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="400211072" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="731932048" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="731932048" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu , Robert Hoo Subject: [PATCH v3 05/17] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4] Date: Tue, 1 Aug 2023 18:35:15 +0800 Message-Id: <20230801103527.397756-6-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1690886101695100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the nearest power-of-2 integer. The nearest power-of-2 integer can be caculated by pow2ceil() or by using APIC ID offset (like L3 topology using 1 << die_offset [3]). But in fact, CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] are associated with APIC ID. For example, in linux kernel, the field "num_threads_sharing" (Bits 25 - 14) is parsed with APIC ID. And for another example, on Alder Lake P, the CPUID.04H:EAX[bits 31:26] is not matched with actual core numbers and it's caculated by: "(1 << (pkg_offset - core_offset)) - 1". Therefore the offset of APIC ID should be preferred to caculate nearest power-of-2 integer for CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26]: 1. d/i cache is shared in a core, 1 << core_offset should be used instand of "cs->nr_threads" in encode_cache_cpuid4() for CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits 25:14]. 2. L2 cache is supposed to be shared in a core as for now, thereby 1 << core_offset should also be used instand of "cs->nr_threads" in encode_cache_cpuid4() for CPUID.04H.02H:EAX[bits 25:14]. 3. Similarly, the value for CPUID.04H:EAX[bits 31:26] should also be replaced by the offsets upper SMT level in APIC ID. In addition, use APIC ID offset to replace "pow2ceil()" for cache_info_passthrough case. [1]: efb3934adf9e ("x86: cpu: make sure number of addressable IDs for proce= ssor cores meets the spec") [2]: d7caf13b5fcf ("x86: cpu: fixup number of addressable IDs for logical p= rocessors sharing cache") [3]: d65af288a84d ("i386: Update new x86_apicid parsing rules with die_offs= et support") Fixes: 7e3482f82480 ("i386: Helpers to encode cache information consistentl= y") Suggested-by: Robert Hoo Signed-off-by: Zhao Liu --- Changes since v1: * Use APIC ID offset to replace "pow2ceil()" for cache_info_passthrough case. (Yanan) * Split the L1 cache fix into a separate patch. * Rename the title of this patch (the original is "i386/cpu: Fix number of addressable IDs in CPUID.04H"). --- target/i386/cpu.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b439a05244ee..c80613bfcded 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6005,7 +6005,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, { X86CPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); - uint32_t die_offset; uint32_t limit; uint32_t signature[3]; X86CPUTopoInfo topo_info; @@ -6089,39 +6088,56 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, int host_vcpus_per_cache =3D 1 + ((*eax & 0x3FFC000) >> 14= ); int vcpus_per_socket =3D cs->nr_cores * cs->nr_threads; if (cs->nr_cores > 1) { + int addressable_cores_offset =3D + apicid_pkg_offset(&topo_in= fo) - + apicid_core_offset(&topo_i= nfo); + *eax &=3D ~0xFC000000; - *eax |=3D (pow2ceil(cs->nr_cores) - 1) << 26; + *eax |=3D (1 << addressable_cores_offset - 1) << 26; } if (host_vcpus_per_cache > vcpus_per_socket) { + int pkg_offset =3D apicid_pkg_offset(&topo_info); + *eax &=3D ~0x3FFC000; - *eax |=3D (pow2ceil(vcpus_per_socket) - 1) << 14; + *eax |=3D (1 << pkg_offset - 1) << 14; } } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { *eax =3D *ebx =3D *ecx =3D *edx =3D 0; } else { *eax =3D 0; + int addressable_cores_offset =3D apicid_pkg_offset(&topo_info)= - + apicid_core_offset(&topo_info); + int core_offset, die_offset; + switch (count) { case 0: /* L1 dcache info */ + core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - cs->nr_threads, cs->nr_cores, + (1 << core_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ + core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - cs->nr_threads, cs->nr_cores, + (1 << core_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ + core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, - cs->nr_threads, cs->nr_cores, + (1 << core_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ die_offset =3D apicid_die_offset(&topo_info); if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - (1 << die_offset), cs->nr_cores, + (1 << die_offset), + (1 << addressable_cores_offset), eax, ebx, ecx, edx); break; } --=20 2.34.1 From nobody Wed May 15 12:14:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1690886070; cv=none; d=zohomail.com; s=zohoarc; b=Hk/vSKdBADTVQBdnYN1D8SlYzudmXBX8utPOv43DWpXd7DeM/Tbsx0rVM4Hr/YOVORjVqRNX2QJrUKQblpWZtz1x1PTBBZKOyuA8gCbNsiN7fZImF/QK63VzjUx+2kT/WRwjK2UBtzKN2l3jy/SZbHK0coqn4l+VgexLjdv2lNY= ARC-Message-Signature: i=1; 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Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu , Robert Hoo Subject: [PATCH v3 06/17] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() Date: Tue, 1 Aug 2023 18:35:16 +0800 Message-Id: <20230801103527.397756-7-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1690886070487100007 Content-Type: text/plain; charset="utf-8" From: Zhao Liu In cpu_x86_cpuid(), there are many variables in representing the cpu topology, e.g., topo_info, cs->nr_cores/cs->nr_threads. Since the names of cs->nr_cores/cs->nr_threads does not accurately represent its meaning, the use of cs->nr_cores/cs->nr_threads is prone to confusion and mistakes. And the structure X86CPUTopoInfo names its memebers clearly, thus the variable "topo_info" should be preferred. In addition, in cpu_x86_cpuid(), to uniformly use the topology variable, replace env->dies with topo_info.dies_per_pkg as well. Suggested-by: Robert Hoo Signed-off-by: Zhao Liu --- Changes since v1: * Extract cores_per_socket from the code block and use it as a local variable for cpu_x86_cpuid(). (Yanan) * Remove vcpus_per_socket variable and use cpus_per_pkg directly. (Yanan) * Replace env->dies with topo_info.dies_per_pkg in cpu_x86_cpuid(). --- target/i386/cpu.c | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c80613bfcded..fc50bf98c60e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6008,11 +6008,16 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, uint32_t limit; uint32_t signature[3]; X86CPUTopoInfo topo_info; + uint32_t cores_per_pkg; + uint32_t cpus_per_pkg; =20 topo_info.dies_per_pkg =3D env->nr_dies; topo_info.cores_per_die =3D cs->nr_cores / env->nr_dies; topo_info.threads_per_core =3D cs->nr_threads; =20 + cores_per_pkg =3D topo_info.cores_per_die * topo_info.dies_per_pkg; + cpus_per_pkg =3D cores_per_pkg * topo_info.threads_per_core; + /* Calculate & apply limits for different index ranges */ if (index >=3D 0xC0000000) { limit =3D env->cpuid_xlevel2; @@ -6048,8 +6053,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *ecx |=3D CPUID_EXT_OSXSAVE; } *edx =3D env->features[FEAT_1_EDX]; - if (cs->nr_cores * cs->nr_threads > 1) { - *ebx |=3D (cs->nr_cores * cs->nr_threads) << 16; + if (cpus_per_pkg > 1) { + *ebx |=3D cpus_per_pkg << 16; *edx |=3D CPUID_HT; } if (!cpu->enable_pmu) { @@ -6086,8 +6091,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, */ if (*eax & 31) { int host_vcpus_per_cache =3D 1 + ((*eax & 0x3FFC000) >> 14= ); - int vcpus_per_socket =3D cs->nr_cores * cs->nr_threads; - if (cs->nr_cores > 1) { + + if (cores_per_pkg > 1) { int addressable_cores_offset =3D apicid_pkg_offset(&topo_in= fo) - apicid_core_offset(&topo_i= nfo); @@ -6095,7 +6100,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *eax &=3D ~0xFC000000; *eax |=3D (1 << addressable_cores_offset - 1) << 26; } - if (host_vcpus_per_cache > vcpus_per_socket) { + if (host_vcpus_per_cache > cpus_per_pkg) { int pkg_offset =3D apicid_pkg_offset(&topo_info); =20 *eax &=3D ~0x3FFC000; @@ -6240,12 +6245,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, switch (count) { case 0: *eax =3D apicid_core_offset(&topo_info); - *ebx =3D cs->nr_threads; + *ebx =3D topo_info.threads_per_core; *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: *eax =3D apicid_pkg_offset(&topo_info); - *ebx =3D cs->nr_cores * cs->nr_threads; + *ebx =3D cpus_per_pkg; *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; default: @@ -6266,7 +6271,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; case 0x1F: /* V2 Extended Topology Enumeration Leaf */ - if (env->nr_dies < 2) { + if (topo_info.dies_per_pkg < 2) { *eax =3D *ebx =3D *ecx =3D *edx =3D 0; break; } @@ -6276,7 +6281,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, switch (count) { case 0: *eax =3D apicid_core_offset(&topo_info); - *ebx =3D cs->nr_threads; + *ebx =3D topo_info.threads_per_core; *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: @@ -6286,7 +6291,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; case 2: *eax =3D apicid_pkg_offset(&topo_info); - *ebx =3D cs->nr_cores * cs->nr_threads; + *ebx =3D cpus_per_pkg; *ecx |=3D CPUID_TOPOLOGY_LEVEL_DIE; break; default: @@ -6511,7 +6516,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, * discards multiple thread information if it is set. * So don't set it here for Intel to make Linux guests happy. */ - if (cs->nr_cores * cs->nr_threads > 1) { + if (cpus_per_pkg > 1) { if (env->cpuid_vendor1 !=3D CPUID_VENDOR_INTEL_1 || env->cpuid_vendor2 !=3D CPUID_VENDOR_INTEL_2 || env->cpuid_vendor3 !=3D CPUID_VENDOR_INTEL_3) { @@ -6577,7 +6582,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *eax |=3D (cpu_x86_virtual_addr_width(env) << 8); } *ebx =3D env->features[FEAT_8000_0008_EBX]; - if (cs->nr_cores * cs->nr_threads > 1) { + if (cpus_per_pkg > 1) { /* * Bits 15:12 is "The number of bits in the initial * Core::X86::Apic::ApicId[ApicId] value that indicate @@ -6585,7 +6590,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, * Bits 7:0 is "The number of threads in the package is NC+1" */ *ecx =3D (apicid_pkg_offset(&topo_info) << 12) | - ((cs->nr_cores * cs->nr_threads) - 1); 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Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu , Zhuocheng Ding Subject: [PATCH v3 07/17] i386: Introduce module-level cpu topology to CPUX86State Date: Tue, 1 Aug 2023 18:35:17 +0800 Message-Id: <20230801103527.397756-8-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1690886037699100001 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding smp command has the "clusters" parameter but x86 hasn't supported that level. "cluster" is a CPU topology level concept above cores, in which the cores may share some resources (L2 cache or some others like L3 cache tags, depending on the Archs) [1][2]. For x86, the resource shared by cores at the cluster level is mainly the L2 cache. However, using cluster to define x86's L2 cache topology will cause the compatibility problem: Currently, x86 defaults that the L2 cache is shared in one core, which actually implies a default setting "cores per L2 cache is 1" and therefore implicitly defaults to having as many L2 caches as cores. For example (i386 PC machine): -smp 16,sockets=3D2,dies=3D2,cores=3D2,threads=3D2,maxcpus=3D16 (*) Considering the topology of the L2 cache, this (*) implicitly means "1 core per L2 cache" and "2 L2 caches per die". If we use cluster to configure L2 cache topology with the new default setting "clusters per L2 cache is 1", the above semantics will change to "2 cores per cluster" and "1 cluster per L2 cache", that is, "2 cores per L2 cache". So the same command (*) will cause changes in the L2 cache topology, further affecting the performance of the virtual machine. Therefore, x86 should only treat cluster as a cpu topology level and avoid using it to change L2 cache by default for compatibility. "cluster" in smp is the CPU topology level which is between "core" and die. For x86, the "cluster" in smp is corresponding to the module level [2], which is above the core level. So use the "module" other than "cluster" in i386 code. And please note that x86 already has a cpu topology level also named "cluster" [3], this level is at the upper level of the package. Here, the cluster in x86 cpu topology is completely different from the "clusters" as the smp parameter. After the module level is introduced, the cluster as the smp parameter will actually refer to the module level of x86. [1]: 864c3b5c32f0 ("hw/core/machine: Introduce CPU cluster topology support= ") [2]: Yanan's comment about "cluster", https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg04051.html [3]: SDM, vol.3, ch.9, 9.9.1 Hierarchical Mapping of Shared Resources. Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu Acked-by: Michael S. Tsirkin --- Changes since v1: * The background of the introduction of the "cluster" parameter and its exact meaning were revised according to Yanan's explanation. (Yanan) --- hw/i386/x86.c | 1 + target/i386/cpu.c | 1 + target/i386/cpu.h | 5 +++++ 3 files changed, 7 insertions(+) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index a88a126123be..4efc390905ff 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -309,6 +309,7 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, init_topo_info(&topo_info, x86ms); =20 env->nr_dies =3D ms->smp.dies; + env->nr_modules =3D ms->smp.clusters; =20 /* * If APIC ID is not set, diff --git a/target/i386/cpu.c b/target/i386/cpu.c index fc50bf98c60e..8a9fd5682efc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7606,6 +7606,7 @@ static void x86_cpu_initfn(Object *obj) CPUX86State *env =3D &cpu->env; =20 env->nr_dies =3D 1; + env->nr_modules =3D 1; cpu_set_cpustate_pointers(cpu); =20 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7638128d59cc..5e97d0b76574 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1880,6 +1880,11 @@ typedef struct CPUArchState { =20 /* Number of dies within this CPU package. */ unsigned nr_dies; + /* + * Number of modules within this CPU package. + * Module level in x86 cpu topology is corresponding to smp.clusters. + */ + unsigned nr_modules; } CPUX86State; =20 struct kvm_msrs; --=20 2.34.1 From nobody Wed May 15 12:14:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1690886006; cv=none; d=zohomail.com; s=zohoarc; b=C/4iaYmiAB+HUUVOb4w4QVkCv8K+pA3MkrI123prbwO1H71XndR+oh/PBvR4DF31Oe2YfWIrwOd/bwaO+Fs9R76jNtyrqqqmfUZ2CzhzPoZiqqlHzvqff7OiYnol/hsddhkHkN/j/bSbMWa4bgzzsAzxFDq71p+Kia5q69B41wo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690886006; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Jg9Vt/gCtWR8Ggv6ELNjUjfwR3JjDtyX/r13iu2QERQ=; b=SGC6XTLnAqJ6Y3GrJxmbthaMdQVlUyQQpWAabm8va4JfTcSNpHZka36DKuPvl9BGk8jW7XARcod4/Yf9gFB+ZNTBgSeOEDPM8tzZBhYybtZfjhL9cbFhsza09oQt29+ehZ/PwZrluaXQmD+Cs4F4bf4XtiKrC7sV5CH7PIXPWks= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690886006523859.4614689472655; Tue, 1 Aug 2023 03:33:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qQmgT-0008De-5J; Tue, 01 Aug 2023 06:32:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qQmgS-00089o-3l for qemu-devel@nongnu.org; Tue, 01 Aug 2023 06:32:56 -0400 Received: from [192.55.52.88] (helo=mgamail.intel.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qQmgQ-00033E-1T for qemu-devel@nongnu.org; Tue, 01 Aug 2023 06:32:55 -0400 Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Aug 2023 03:25:29 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.28]) by fmsmga007.fm.intel.com with ESMTP; 01 Aug 2023 03:25:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690885974; x=1722421974; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=q0qPvdHi9TOhHUcauT5JxVH5cfGURFG9avb6J5MsZWM=; b=lIpAnMpOZr1uiE3TaWWNMCv70xi/9ZJMwVijNfwYfv9AsCzpvFcoBnYh VFy6v+REyGyEYnP2yDoG6IYbpaKA5ypmzT4gYWfOXRCpvyekW5/VppXXa ZnSbsdJfXrDrhEfHqSXSNmFuX62I5xLtZ1Gv03HwUFln1w0wx2+5wjOcB h+3vDODqppMqpuNH/RTcCnLS92fbf0ShIMQEny7NBacpy6GkWAonZj3qg gg7oYGqE3gXbspiXp3qPOpK/bbI/T/KDUncpgoH4eIfJRMDwK4gqBzb6M XOAP9iAI7tLuuwHsWnWIVlfrJr+bSFQNWtKCYqtj7gOGZi07GXnDgjSao A==; X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="400211165" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="400211165" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="731932091" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="731932091" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu , Zhuocheng Ding Subject: [PATCH v3 08/17] i386: Support modules_per_die in X86CPUTopoInfo Date: Tue, 1 Aug 2023 18:35:18 +0800 Message-Id: <20230801103527.397756-9-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1690886008949100003 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding Support module level in i386 cpu topology structure "X86CPUTopoInfo". Since x86 does not yet support the "clusters" parameter in "-smp", X86CPUTopoInfo.modules_per_die is currently always 1. Therefore, the module level width in APIC ID, which can be calculated by "apicid_bitwidth_for_count(topo_info->modules_per_die)", is always 0 for now, so we can directly add APIC ID related helpers to support module level parsing. At present, we don't expose module level in CPUID.1FH because currently linux (v6.4-rc1) doesn't support module level. And exposing module and die levels at the same time in CPUID.1FH will cause linux to calculate the wrong die_id. The module level should be exposed until the real machine has the module level in CPUID.1FH. In addition, update topology structure in test-x86-topo.c. Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu Acked-by: Michael S. Tsirkin --- Changes since v1: * Include module level related helpers (apicid_module_width() and apicid_module_offset()) in this patch. (Yanan) --- hw/i386/x86.c | 3 ++- include/hw/i386/topology.h | 22 +++++++++++++++---- target/i386/cpu.c | 12 ++++++---- tests/unit/test-x86-topo.c | 45 ++++++++++++++++++++------------------ 4 files changed, 52 insertions(+), 30 deletions(-) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 4efc390905ff..a552ae8bb4a8 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -72,7 +72,8 @@ static void init_topo_info(X86CPUTopoInfo *topo_info, MachineState *ms =3D MACHINE(x86ms); =20 topo_info->dies_per_pkg =3D ms->smp.dies; - topo_info->cores_per_die =3D ms->smp.cores; + topo_info->modules_per_die =3D ms->smp.clusters; + topo_info->cores_per_module =3D ms->smp.cores; topo_info->threads_per_core =3D ms->smp.threads; } =20 diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 5a19679f618b..c807d3811dd3 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -56,7 +56,8 @@ typedef struct X86CPUTopoIDs { =20 typedef struct X86CPUTopoInfo { unsigned dies_per_pkg; - unsigned cores_per_die; + unsigned modules_per_die; + unsigned cores_per_module; unsigned threads_per_core; } X86CPUTopoInfo; =20 @@ -77,7 +78,13 @@ static inline unsigned apicid_smt_width(X86CPUTopoInfo *= topo_info) /* Bit width of the Core_ID field */ static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info) { - return apicid_bitwidth_for_count(topo_info->cores_per_die); + return apicid_bitwidth_for_count(topo_info->cores_per_module); +} + +/* Bit width of the Module_ID (cluster ID) field */ +static inline unsigned apicid_module_width(X86CPUTopoInfo *topo_info) +{ + return apicid_bitwidth_for_count(topo_info->modules_per_die); } =20 /* Bit width of the Die_ID field */ @@ -92,10 +99,16 @@ static inline unsigned apicid_core_offset(X86CPUTopoInf= o *topo_info) return apicid_smt_width(topo_info); } =20 +/* Bit offset of the Module_ID (cluster ID) field */ +static inline unsigned apicid_module_offset(X86CPUTopoInfo *topo_info) +{ + return apicid_core_offset(topo_info) + apicid_core_width(topo_info); +} + /* Bit offset of the Die_ID field */ static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info) { - return apicid_core_offset(topo_info) + apicid_core_width(topo_info); + return apicid_module_offset(topo_info) + apicid_module_width(topo_info= ); } =20 /* Bit offset of the Pkg_ID (socket ID) field */ @@ -127,7 +140,8 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoInfo= *topo_info, X86CPUTopoIDs *topo_ids) { unsigned nr_dies =3D topo_info->dies_per_pkg; - unsigned nr_cores =3D topo_info->cores_per_die; + unsigned nr_cores =3D topo_info->cores_per_module * + topo_info->modules_per_die; unsigned nr_threads =3D topo_info->threads_per_core; =20 topo_ids->pkg_id =3D cpu_index / (nr_dies * nr_cores * nr_threads); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 8a9fd5682efc..d6969813ee02 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -339,7 +339,9 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *ca= che, =20 /* L3 is shared among multiple cores */ if (cache->level =3D=3D 3) { - l3_threads =3D topo_info->cores_per_die * topo_info->threads_per_c= ore; + l3_threads =3D topo_info->modules_per_die * + topo_info->cores_per_module * + topo_info->threads_per_core; *eax |=3D (l3_threads - 1) << 14; } else { *eax |=3D ((topo_info->threads_per_core - 1) << 14); @@ -6012,10 +6014,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, uint32_t cpus_per_pkg; =20 topo_info.dies_per_pkg =3D env->nr_dies; - topo_info.cores_per_die =3D cs->nr_cores / env->nr_dies; + topo_info.modules_per_die =3D env->nr_modules; + topo_info.cores_per_module =3D cs->nr_cores / env->nr_dies / env->nr_m= odules; topo_info.threads_per_core =3D cs->nr_threads; =20 - cores_per_pkg =3D topo_info.cores_per_die * topo_info.dies_per_pkg; + cores_per_pkg =3D topo_info.cores_per_module * topo_info.modules_per_d= ie * + topo_info.dies_per_pkg; cpus_per_pkg =3D cores_per_pkg * topo_info.threads_per_core; =20 /* Calculate & apply limits for different index ranges */ @@ -6286,7 +6290,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; case 1: *eax =3D apicid_die_offset(&topo_info); - *ebx =3D topo_info.cores_per_die * topo_info.threads_per_core; + *ebx =3D cpus_per_pkg / topo_info.dies_per_pkg; *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; case 2: diff --git a/tests/unit/test-x86-topo.c b/tests/unit/test-x86-topo.c index 2b104f86d7c2..f21b8a5d95c2 100644 --- a/tests/unit/test-x86-topo.c +++ b/tests/unit/test-x86-topo.c @@ -30,13 +30,16 @@ static void test_topo_bits(void) { X86CPUTopoInfo topo_info =3D {0}; =20 - /* simple tests for 1 thread per core, 1 core per die, 1 die per packa= ge */ - topo_info =3D (X86CPUTopoInfo) {1, 1, 1}; + /* + * simple tests for 1 thread per core, 1 core per module, + * 1 module per die, 1 die per package + */ + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 1}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 0); g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 0); g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 0); =20 - topo_info =3D (X86CPUTopoInfo) {1, 1, 1}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 1}; g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 0), =3D=3D, 0); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1), =3D=3D, 1); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2), =3D=3D, 2); @@ -45,39 +48,39 @@ static void test_topo_bits(void) =20 /* Test field width calculation for multiple values */ - topo_info =3D (X86CPUTopoInfo) {1, 1, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 2}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 1); - topo_info =3D (X86CPUTopoInfo) {1, 1, 3}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 3}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); - topo_info =3D (X86CPUTopoInfo) {1, 1, 4}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 4}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); =20 - topo_info =3D (X86CPUTopoInfo) {1, 1, 14}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 14}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 4); - topo_info =3D (X86CPUTopoInfo) {1, 1, 15}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 15}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 4); - topo_info =3D (X86CPUTopoInfo) {1, 1, 16}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 16}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 4); - topo_info =3D (X86CPUTopoInfo) {1, 1, 17}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 17}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 5); =20 =20 - topo_info =3D (X86CPUTopoInfo) {1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 30, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 5); - topo_info =3D (X86CPUTopoInfo) {1, 31, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 31, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 5); - topo_info =3D (X86CPUTopoInfo) {1, 32, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 32, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 5); - topo_info =3D (X86CPUTopoInfo) {1, 33, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 33, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 6); =20 - topo_info =3D (X86CPUTopoInfo) {1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 0); - topo_info =3D (X86CPUTopoInfo) {2, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {2, 1, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 1); - topo_info =3D (X86CPUTopoInfo) {3, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {3, 1, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 2); - topo_info =3D (X86CPUTopoInfo) {4, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {4, 1, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 2); =20 /* build a weird topology and see if IDs are calculated correctly @@ -85,18 +88,18 @@ static void test_topo_bits(void) =20 /* This will use 2 bits for thread ID and 3 bits for core ID */ - topo_info =3D (X86CPUTopoInfo) {1, 6, 3}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 6, 3}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); g_assert_cmpuint(apicid_core_offset(&topo_info), =3D=3D, 2); g_assert_cmpuint(apicid_die_offset(&topo_info), =3D=3D, 5); g_assert_cmpuint(apicid_pkg_offset(&topo_info), =3D=3D, 5); =20 - topo_info =3D (X86CPUTopoInfo) {1, 6, 3}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 6, 3}; g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 0), =3D=3D, 0); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1), =3D=3D, 1); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2), =3D=3D, 2); =20 - topo_info =3D (X86CPUTopoInfo) {1, 6, 3}; + topo_info =3D (X86CPUTopoInfo) {1, 1, 6, 3}; g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 3 + 0), =3D= =3D, (1 << 2) | 0); g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 3 + 1), =3D= =3D, --=20 2.34.1 From nobody Wed May 15 12:14:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; 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Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu , Zhuocheng Ding Subject: [PATCH v3 09/17] i386: Support module_id in X86CPUTopoIDs Date: Tue, 1 Aug 2023 18:35:19 +0800 Message-Id: <20230801103527.397756-10-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1690886057903100003 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding Add module_id member in X86CPUTopoIDs. module_id can be parsed from APIC ID, so also update APIC ID parsing rule to support module level. With this support, the conversions with module level between X86CPUTopoIDs, X86CPUTopoInfo and APIC ID are completed. module_id can be also generated from cpu topology, and before i386 supports "clusters" in smp, the default "clusters per die" is only 1, thus the module_id generated in this way is 0, so that it will not conflict with the module_id generated by APIC ID. Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu Acked-by: Michael S. Tsirkin --- Changes since v1: * Merge the patch "i386: Update APIC ID parsing rule to support module level" into this one. (Yanan) * Move the apicid_module_width() and apicid_module_offset() support into the previous modules_per_die related patch. (Yanan) --- hw/i386/x86.c | 28 +++++++++++++++++++++------- include/hw/i386/topology.h | 17 +++++++++++++---- 2 files changed, 34 insertions(+), 11 deletions(-) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index a552ae8bb4a8..0b460fd6074d 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -314,11 +314,11 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, =20 /* * If APIC ID is not set, - * set it based on socket/die/core/thread properties. + * set it based on socket/die/cluster/core/thread properties. */ if (cpu->apic_id =3D=3D UNASSIGNED_APIC_ID) { - int max_socket =3D (ms->smp.max_cpus - 1) / - smp_threads / smp_cores / ms->smp.dies; + int max_socket =3D (ms->smp.max_cpus - 1) / smp_threads / smp_core= s / + ms->smp.clusters / ms->smp.dies; =20 /* * die-id was optional in QEMU 4.0 and older, so keep it optional @@ -365,6 +365,14 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, topo_ids.die_id =3D cpu->die_id; topo_ids.core_id =3D cpu->core_id; topo_ids.smt_id =3D cpu->thread_id; + + /* + * TODO: This is the temporary initialization for topo_ids.module_= id to + * avoid "maybe-uninitialized" compilation errors. Will remove when + * X86CPU supports cluster_id. + */ + topo_ids.module_id =3D 0; + cpu->apic_id =3D x86_apicid_from_topo_ids(&topo_info, &topo_ids); } =20 @@ -373,11 +381,13 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, MachineState *ms =3D MACHINE(x86ms); =20 x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + error_setg(errp, - "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" - " APIC ID %" PRIu32 ", valid index range 0:%d", - topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.s= mt_id, - cpu->apic_id, ms->possible_cpus->len - 1); + "Invalid CPU [socket: %u, die: %u, module: %u, core: %u, threa= d: %u]" + " with APIC ID %" PRIu32 ", valid index range 0:%d", + topo_ids.pkg_id, topo_ids.die_id, topo_ids.module_id, + topo_ids.core_id, topo_ids.smt_id, cpu->apic_id, + ms->possible_cpus->len - 1); return; } =20 @@ -498,6 +508,10 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(Machine= State *ms) ms->possible_cpus->cpus[i].props.has_die_id =3D true; ms->possible_cpus->cpus[i].props.die_id =3D topo_ids.die_id; } + if (ms->smp.clusters > 1) { + ms->possible_cpus->cpus[i].props.has_cluster_id =3D true; + ms->possible_cpus->cpus[i].props.cluster_id =3D topo_ids.modul= e_id; + } ms->possible_cpus->cpus[i].props.has_core_id =3D true; ms->possible_cpus->cpus[i].props.core_id =3D topo_ids.core_id; ms->possible_cpus->cpus[i].props.has_thread_id =3D true; diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index c807d3811dd3..3cec97b377f2 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -50,6 +50,7 @@ typedef uint32_t apic_id_t; typedef struct X86CPUTopoIDs { unsigned pkg_id; unsigned die_id; + unsigned module_id; unsigned core_id; unsigned smt_id; } X86CPUTopoIDs; @@ -127,6 +128,7 @@ static inline apic_id_t x86_apicid_from_topo_ids(X86CPU= TopoInfo *topo_info, { return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) | (topo_ids->die_id << apicid_die_offset(topo_info)) | + (topo_ids->module_id << apicid_module_offset(topo_info)) | (topo_ids->core_id << apicid_core_offset(topo_info)) | topo_ids->smt_id; } @@ -140,12 +142,16 @@ static inline void x86_topo_ids_from_idx(X86CPUTopoIn= fo *topo_info, X86CPUTopoIDs *topo_ids) { unsigned nr_dies =3D topo_info->dies_per_pkg; - unsigned nr_cores =3D topo_info->cores_per_module * - topo_info->modules_per_die; + unsigned nr_modules =3D topo_info->modules_per_die; + unsigned nr_cores =3D topo_info->cores_per_module; unsigned nr_threads =3D topo_info->threads_per_core; =20 - topo_ids->pkg_id =3D cpu_index / (nr_dies * nr_cores * nr_threads); - topo_ids->die_id =3D cpu_index / (nr_cores * nr_threads) % nr_dies; + topo_ids->pkg_id =3D cpu_index / (nr_dies * nr_modules * + nr_cores * nr_threads); + topo_ids->die_id =3D cpu_index / (nr_modules * nr_cores * + nr_threads) % nr_dies; + topo_ids->module_id =3D cpu_index / (nr_cores * nr_threads) % + nr_modules; topo_ids->core_id =3D cpu_index / nr_threads % nr_cores; topo_ids->smt_id =3D cpu_index % nr_threads; } @@ -163,6 +169,9 @@ static inline void x86_topo_ids_from_apicid(apic_id_t a= picid, topo_ids->core_id =3D (apicid >> apicid_core_offset(topo_info)) & ~(0xFFFFFFFFUL << apicid_core_width(topo_info)); + topo_ids->module_id =3D + (apicid >> apicid_module_offset(topo_info)) & + ~(0xFFFFFFFFUL << apicid_module_width(topo_info)); topo_ids->die_id =3D (apicid >> apicid_die_offset(topo_info)) & ~(0xFFFFFFFFUL << apicid_die_width(topo_info)); --=20 2.34.1 From nobody Wed May 15 12:14:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1690886044; cv=none; d=zohomail.com; s=zohoarc; b=Jlp6veqVbJo+sI81yzSwJmn8Lh9GRh3/TW1TGS9FV/5x1vMoX6TYeH1pATaC1XQ46p9+AUkwRofVHopZBXyk/861DSyZlVqU9u+obeSs7OQmxXyGA3bqc68ZdFcZ/ChWD+D5tUNxp1ExU2S4lDfgsGOILrlzbb5mPK3mKpzRz7I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690886044; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu , Zhuocheng Ding Subject: [PATCH v3 10/17] i386/cpu: Introduce cluster-id to X86CPU Date: Tue, 1 Aug 2023 18:35:20 +0800 Message-Id: <20230801103527.397756-11-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1690886045091100001 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding We introduce cluster-id other than module-id to be consistent with CpuInstanceProperties.cluster-id, and this avoids the confusion of parameter names when hotplugging. Following the legacy smp check rules, also add the cluster_id validity into x86_cpu_pre_plug(). Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu Acked-by: Michael S. Tsirkin --- hw/i386/x86.c | 33 +++++++++++++++++++++++++-------- target/i386/cpu.c | 2 ++ target/i386/cpu.h | 1 + 3 files changed, 28 insertions(+), 8 deletions(-) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 0b460fd6074d..8154b86f95c7 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -328,6 +328,14 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, cpu->die_id =3D 0; } =20 + /* + * cluster-id was optional in QEMU 8.0 and older, so keep it optio= nal + * if there's only one cluster per die. + */ + if (cpu->cluster_id < 0 && ms->smp.clusters =3D=3D 1) { + cpu->cluster_id =3D 0; + } + if (cpu->socket_id < 0) { error_setg(errp, "CPU socket-id is not set"); return; @@ -344,6 +352,14 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, cpu->die_id, ms->smp.dies - 1); return; } + if (cpu->cluster_id < 0) { + error_setg(errp, "CPU cluster-id is not set"); + return; + } else if (cpu->cluster_id > ms->smp.clusters - 1) { + error_setg(errp, "Invalid CPU cluster-id: %u must be in range = 0:%u", + cpu->cluster_id, ms->smp.clusters - 1); + return; + } if (cpu->core_id < 0) { error_setg(errp, "CPU core-id is not set"); return; @@ -363,16 +379,9 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, =20 topo_ids.pkg_id =3D cpu->socket_id; topo_ids.die_id =3D cpu->die_id; + topo_ids.module_id =3D cpu->cluster_id; topo_ids.core_id =3D cpu->core_id; topo_ids.smt_id =3D cpu->thread_id; - - /* - * TODO: This is the temporary initialization for topo_ids.module_= id to - * avoid "maybe-uninitialized" compilation errors. Will remove when - * X86CPU supports cluster_id. - */ - topo_ids.module_id =3D 0; - cpu->apic_id =3D x86_apicid_from_topo_ids(&topo_info, &topo_ids); } =20 @@ -419,6 +428,14 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, } cpu->die_id =3D topo_ids.die_id; =20 + if (cpu->cluster_id !=3D -1 && cpu->cluster_id !=3D topo_ids.module_id= ) { + error_setg(errp, "property cluster-id: %u doesn't match set apic-i= d:" + " 0x%x (cluster-id: %u)", cpu->cluster_id, cpu->apic_id, + topo_ids.module_id); + return; + } + cpu->cluster_id =3D topo_ids.module_id; + if (cpu->core_id !=3D -1 && cpu->core_id !=3D topo_ids.core_id) { error_setg(errp, "property core-id: %u doesn't match set apic-id:" " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d6969813ee02..ffa282219078 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7806,12 +7806,14 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), + DEFINE_PROP_INT32("cluster-id", X86CPU, cluster_id, 0), DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), #else DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), + DEFINE_PROP_INT32("cluster-id", X86CPU, cluster_id, -1), DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), #endif diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 5e97d0b76574..d9577938ae04 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2034,6 +2034,7 @@ struct ArchCPU { int32_t node_id; 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Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu , Zhuocheng Ding , Yongwei Ma Subject: [PATCH v3 11/17] tests: Add test case of APIC ID for module level parsing Date: Tue, 1 Aug 2023 18:35:21 +0800 Message-Id: <20230801103527.397756-12-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1690886124083100001 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding After i386 supports module level, it's time to add the test for module level's parsing. Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Yanan Wang Acked-by: Michael S. Tsirkin --- tests/unit/test-x86-topo.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/tests/unit/test-x86-topo.c b/tests/unit/test-x86-topo.c index f21b8a5d95c2..55b731ccae55 100644 --- a/tests/unit/test-x86-topo.c +++ b/tests/unit/test-x86-topo.c @@ -37,6 +37,7 @@ static void test_topo_bits(void) topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 1}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 0); g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 0); + g_assert_cmpuint(apicid_module_width(&topo_info), =3D=3D, 0); g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 0); =20 topo_info =3D (X86CPUTopoInfo) {1, 1, 1, 1}; @@ -74,13 +75,22 @@ static void test_topo_bits(void) topo_info =3D (X86CPUTopoInfo) {1, 1, 33, 2}; g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 6); =20 - topo_info =3D (X86CPUTopoInfo) {1, 1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {1, 6, 30, 2}; + g_assert_cmpuint(apicid_module_width(&topo_info), =3D=3D, 3); + topo_info =3D (X86CPUTopoInfo) {1, 7, 30, 2}; + g_assert_cmpuint(apicid_module_width(&topo_info), =3D=3D, 3); + topo_info =3D (X86CPUTopoInfo) {1, 8, 30, 2}; + g_assert_cmpuint(apicid_module_width(&topo_info), =3D=3D, 3); + topo_info =3D (X86CPUTopoInfo) {1, 9, 30, 2}; + g_assert_cmpuint(apicid_module_width(&topo_info), =3D=3D, 4); + + topo_info =3D (X86CPUTopoInfo) {1, 6, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 0); - topo_info =3D (X86CPUTopoInfo) {2, 1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {2, 6, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 1); - topo_info =3D (X86CPUTopoInfo) {3, 1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {3, 6, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 2); - topo_info =3D (X86CPUTopoInfo) {4, 1, 30, 2}; + topo_info =3D (X86CPUTopoInfo) {4, 6, 30, 2}; g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 2); =20 /* build a weird topology and see if IDs are calculated correctly @@ -91,6 +101,7 @@ static void test_topo_bits(void) topo_info =3D (X86CPUTopoInfo) {1, 1, 6, 3}; g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); g_assert_cmpuint(apicid_core_offset(&topo_info), =3D=3D, 2); + g_assert_cmpuint(apicid_module_offset(&topo_info), =3D=3D, 5); g_assert_cmpuint(apicid_die_offset(&topo_info), =3D=3D, 5); g_assert_cmpuint(apicid_pkg_offset(&topo_info), =3D=3D, 5); =20 --=20 2.34.1 From nobody Wed May 15 12:14:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1690886039; cv=none; d=zohomail.com; s=zohoarc; b=W6YvKFgUTdzSjIPTxahK421Tsxu6W/sqnWqjdvl9cSGK46cnbQd5Sa/+HWP9fLuEeiC6rDsrooQc+ahVh7PY184ETliH+JfwVeSD9PBLK/8EFkc2zeBBfRaDawKLxd3bu9dMQvRlSKMQNrSOcZViSAZ8hAZHrsY4koJVQECdjtw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu , Zhuocheng Ding Subject: [PATCH v3 12/17] hw/i386/pc: Support smp.clusters for x86 PC machine Date: Tue, 1 Aug 2023 18:35:22 +0800 Message-Id: <20230801103527.397756-13-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1690886040536100007 Content-Type: text/plain; charset="utf-8" From: Zhuocheng Ding As module-level topology support is added to X86CPU, now we can enable the support for the cluster parameter on PC machines. With this support, we can define a 5-level x86 CPU topology with "-smp": -smp cpus=3D*,maxcpus=3D*,sockets=3D*,dies=3D*,clusters=3D*,cores=3D*,threa= ds=3D*. Additionally, add the 5-level topology example in description of "-smp". Signed-off-by: Zhuocheng Ding Signed-off-by: Zhao Liu Reviewed-by: Yanan Wang Acked-by: Michael S. Tsirkin --- hw/i386/pc.c | 1 + qemu-options.hx | 10 +++++----- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 3109d5e0e035..f2ec5720d233 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1885,6 +1885,7 @@ static void pc_machine_class_init(ObjectClass *oc, vo= id *data) mc->default_cpu_type =3D TARGET_DEFAULT_CPU_TYPE; mc->nvdimm_supported =3D true; mc->smp_props.dies_supported =3D true; + mc->smp_props.clusters_supported =3D true; mc->default_ram_id =3D "pc.ram"; pcmc->default_smbios_ep_type =3D SMBIOS_ENTRY_POINT_TYPE_64; =20 diff --git a/qemu-options.hx b/qemu-options.hx index 29b98c3d4c55..5fb73d996151 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -319,14 +319,14 @@ SRST -smp 8,sockets=3D2,cores=3D2,threads=3D2,maxcpus=3D8 =20 The following sub-option defines a CPU topology hierarchy (2 sockets - totally on the machine, 2 dies per socket, 2 cores per die, 2 threads - per core) for PC machines which support sockets/dies/cores/threads. - Some members of the option can be omitted but their values will be - automatically computed: + totally on the machine, 2 dies per socket, 2 clusters per die, 2 cores= per + cluster, 2 threads per core) for PC machines which support sockets/dies + /clusters/cores/threads. Some members of the option can be omitted but + their values will be automatically computed: =20 :: =20 - -smp 16,sockets=3D2,dies=3D2,cores=3D2,threads=3D2,maxcpus=3D16 + -smp 32,sockets=3D2,dies=3D2,clusters=3D2,cores=3D2,threads=3D2,ma= xcpus=3D32 =20 The following sub-option defines a CPU topology hierarchy (2 sockets totally on the machine, 2 clusters per socket, 2 cores per cluster, --=20 2.34.1 From nobody Wed May 15 12:14:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1690886096; cv=none; d=zohomail.com; s=zohoarc; b=cF4dUvz0f383b5T5Dp+Rjq3TeknYX+zO5dDSzwAXfVieNCS/eR6XJlHKZzO/tf8QGDUXan2Z43OGY+kDU8nw7CfAsWV7s02v4qRXgJvNRW2ScZgepXRrLvVZAfmOBSkU5JA6W1utdFocSt7PtSezrjCUliFBxwNvLrM62NnhTIk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690886096; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1ppxF0Gec4Gu4ul5ilFLfzGcrOjLjpXQjygjYfHCpzg=; b=ctBLL25kmaXMyk8ZpKO1cHZ/vc58BdOyycriW0ntOfHl3OiTCwOhRngQkBRehFSaOBCYw22LDwLOjxfBLxSGTHjqPn4NwsWnaCZ/vPZLMjRs1p2XHyldfb9Eb/Y8KzeOigT8e5l7IQJqsMI0Lo4kSUYR58bl3q7ZRcbJQ+LV1Mw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690886096676842.7797998376676; Tue, 1 Aug 2023 03:34:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qQmgw-00018H-1K; Tue, 01 Aug 2023 06:33:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qQmgu-00011H-U6 for qemu-devel@nongnu.org; Tue, 01 Aug 2023 06:33:24 -0400 Received: from [192.55.52.88] (helo=mgamail.intel.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qQmgs-00037T-V9 for qemu-devel@nongnu.org; Tue, 01 Aug 2023 06:33:24 -0400 Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Aug 2023 03:25:44 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.28]) by fmsmga007.fm.intel.com with ESMTP; 01 Aug 2023 03:25:41 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690886002; x=1722422002; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HuAvmW2urcxx14s1OEKyo1jnFcyKI/5duM5pEPSkVws=; b=VMDrWU6hx55BXgq0Z8wWM5D+CRL7nFVhgy+pClZuWWafBi1JnFIdCauF o5F5tepWpGdcCjAhOGs3PbkrAd5BnZiVpYQVZVMhnsFQ1FxVWOjFCSUVp hntDBmG9ZEn2Xv/LGhtgjRDo+ytmPR7ICWLiju1thxHLwdMD/ahfdAg5A ygeeqxv56erFieh2gIBCP6xujAqgprkbiTW2rkC1+jCZoynLGnHnHE/AA 1nsZwrlSHL3EF4d6VwzPGRjIx1RL/q+RoUBSn3h2iv0TZMIALbZ5XPqe1 aJLr7np216w1jhVn7oEY3RtRKu6grR76ZPBlQ6bWPt+pftIxmJxfa6cgC Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="400211244" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="400211244" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="731932164" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="731932164" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu Subject: [PATCH v3 13/17] i386: Add cache topology info in CPUCacheInfo Date: Tue, 1 Aug 2023 18:35:23 +0800 Message-Id: <20230801103527.397756-14-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1690886097703100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu Currently, by default, the cache topology is encoded as: 1. i/d cache is shared in one core. 2. L2 cache is shared in one core. 3. L3 cache is shared in one die. This default general setting has caused a misunderstanding, that is, the cache topology is completely equated with a specific cpu topology, such as the connection between L2 cache and core level, and the connection between L3 cache and die level. In fact, the settings of these topologies depend on the specific platform and are not static. For example, on Alder Lake-P, every four Atom cores share the same L2 cache. Thus, we should explicitly define the corresponding cache topology for different cache models to increase scalability. Except legacy_l2_cache_cpuid2 (its default topo level is CPU_TOPO_LEVEL_UNKNOW), explicitly set the corresponding topology level for all other cache models. In order to be compatible with the existing cache topology, set the CPU_TOPO_LEVEL_CORE level for the i/d cache, set the CPU_TOPO_LEVEL_CORE level for L2 cache, and set the CPU_TOPO_LEVEL_DIE level for L3 cache. The field for CPUID[4].EAX[bits 25:14] or CPUID[0x8000001D].EAX[bits 25:14] will be set based on CPUCacheInfo.share_level. Signed-off-by: Zhao Liu --- Changes since v1: * Add the prefix "CPU_TOPO_LEVEL_*" for CPU topology level names. (Yanan) * Rename the "INVALID" level to "CPU_TOPO_LEVEL_UNKNOW". (Yanan) --- target/i386/cpu.c | 19 +++++++++++++++++++ target/i386/cpu.h | 16 ++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ffa282219078..55aba4889628 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -436,6 +436,7 @@ static CPUCacheInfo legacy_l1d_cache =3D { .sets =3D 64, .partitions =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ @@ -450,6 +451,7 @@ static CPUCacheInfo legacy_l1d_cache_amd =3D { .partitions =3D 1, .lines_per_tag =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /* L1 instruction cache: */ @@ -463,6 +465,7 @@ static CPUCacheInfo legacy_l1i_cache =3D { .sets =3D 64, .partitions =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ @@ -477,6 +480,7 @@ static CPUCacheInfo legacy_l1i_cache_amd =3D { .partitions =3D 1, .lines_per_tag =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /* Level 2 unified cache: */ @@ -490,6 +494,7 @@ static CPUCacheInfo legacy_l2_cache =3D { .sets =3D 4096, .partitions =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ @@ -512,6 +517,7 @@ static CPUCacheInfo legacy_l2_cache_amd =3D { .associativity =3D 16, .sets =3D 512, .partitions =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }; =20 /* Level 3 unified cache: */ @@ -527,6 +533,7 @@ static CPUCacheInfo legacy_l3_cache =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D CPU_TOPO_LEVEL_DIE, }; =20 /* TLB definitions: */ @@ -1819,6 +1826,7 @@ static const CPUCaches epyc_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -1831,6 +1839,7 @@ static const CPUCaches epyc_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -1841,6 +1850,7 @@ static const CPUCaches epyc_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -1854,6 +1864,7 @@ static const CPUCaches epyc_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -1919,6 +1930,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -1931,6 +1943,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -1941,6 +1954,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -1954,6 +1968,7 @@ static const CPUCaches epyc_rome_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 @@ -2019,6 +2034,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l1i_cache =3D &(CPUCacheInfo) { .type =3D INSTRUCTION_CACHE, @@ -2031,6 +2047,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .lines_per_tag =3D 1, .self_init =3D 1, .no_invd_sharing =3D true, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l2_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2041,6 +2058,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .partitions =3D 1, .sets =3D 1024, .lines_per_tag =3D 1, + .share_level =3D CPU_TOPO_LEVEL_CORE, }, .l3_cache =3D &(CPUCacheInfo) { .type =3D UNIFIED_CACHE, @@ -2054,6 +2072,7 @@ static const CPUCaches epyc_milan_cache_info =3D { .self_init =3D true, .inclusive =3D true, .complex_indexing =3D true, + .share_level =3D CPU_TOPO_LEVEL_DIE, }, }; =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d9577938ae04..3f0cdc45607a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1530,6 +1530,15 @@ enum CacheType { UNIFIED_CACHE }; =20 +enum CPUTopoLevel { + CPU_TOPO_LEVEL_UNKNOW =3D 0, + CPU_TOPO_LEVEL_SMT, + CPU_TOPO_LEVEL_CORE, + CPU_TOPO_LEVEL_MODULE, + CPU_TOPO_LEVEL_DIE, + CPU_TOPO_LEVEL_PACKAGE, +}; + typedef struct CPUCacheInfo { enum CacheType type; uint8_t level; @@ -1571,6 +1580,13 @@ typedef struct CPUCacheInfo { * address bits. CPUID[4].EDX[bit 2]. */ bool complex_indexing; + + /* + * Cache Topology. The level that cache is shared in. + * Used to encode CPUID[4].EAX[bits 25:14] or + * CPUID[0x8000001D].EAX[bits 25:14]. + */ + enum CPUTopoLevel share_level; } CPUCacheInfo; =20 =20 --=20 2.34.1 From nobody Wed May 15 12:14:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1690886069; cv=none; d=zohomail.com; s=zohoarc; b=EOODvQ2enJDN+A0bENUkUq/RjC+CxLQbBnItHU2K5E7ED0kuStjqEaYdzEVHO5atcM5qTfCwbCWw6NW3ebTPM7mVhZzhe5R+ECQV/rM32rg05SFvD75ibtmGqpIdEKYwLE3VGOtl52wiA87HREPMjYxSiqvYAyWbIKKmlyWizRc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690886069; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KVhvYeI4Yjn9GCAsoF9nG/xDPd01o+mDiAQZgNBBHFs=; b=XLvbyzJ3mSMaGz8op81pcuzxJ87JUO6f97SkYlZyTK0hQx6rgMAW/7bJLrI831fTK+JaIt3hLs10BEuPwtRhcYq+Dg1Gyock7UNUmfIMoWgnCFMUIY/lmo2UKtyA1RjczqgxLMiACnvTKVjq7U5SSkC72OT7i03c0wjN2eRzs3E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690886069097907.2589668147918; Tue, 1 Aug 2023 03:34:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qQmh2-0001JO-7I; Tue, 01 Aug 2023 06:33:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qQmh1-0001EG-64 for qemu-devel@nongnu.org; Tue, 01 Aug 2023 06:33:31 -0400 Received: from [192.55.52.88] (helo=mgamail.intel.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qQmgy-0003BJ-TQ for qemu-devel@nongnu.org; Tue, 01 Aug 2023 06:33:30 -0400 Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Aug 2023 03:25:47 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.28]) by fmsmga007.fm.intel.com with ESMTP; 01 Aug 2023 03:25:44 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690886008; x=1722422008; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HVrlowRnwcfGp5YzaUluNe/0zhltFaolFF71vUKn9FY=; b=FgjdIPWGN5TidlXgkChFZR8NpVcn74+PCPZrZ1wX/yHupJDiYh/v5MbH T6NHpe2NRLPIwjwj/o+zYGi9rkHP95hDeXiWUyrdS+Ocis2U6hKxTeRUI W1RZ+vUHBWry/yaPp1EWPLL9UD3F//bp8uGOpt1lQrq5rd0w+jufbZDC1 UjO6rFFRFoHiiy2n8ezRpqnUqBBpvUV1O+TEuABd4GzieWYTlvL6niFD1 rhpFGUEPS6uHyCIqwyWaXgK3+ejiAqRIhVojKQhZaywTr+/DTTIcB8u/j 2m7cbCcIDu/WhzevuEo6I8qzlofpSAZPkU6j9IaNcN9aL0FZ8jNYfavce w==; X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="400211259" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="400211259" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="731932189" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="731932189" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu Subject: [PATCH v3 14/17] i386: Use CPUCacheInfo.share_level to encode CPUID[4] Date: Tue, 1 Aug 2023 18:35:24 +0800 Message-Id: <20230801103527.397756-15-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1690886069902100001 Content-Type: text/plain; charset="utf-8" From: Zhao Liu CPUID[4].EAX[bits 25:14] is used to represent the cache topology for intel CPUs. After cache models have topology information, we can use CPUCacheInfo.share_level to decide which topology level to be encoded into CPUID[4].EAX[bits 25:14]. And since maximum_processor_id (original "num_apic_ids") is parsed based on cpu topology levels, which are verified when parsing smp, it's no need to check this value by "assert(num_apic_ids > 0)" again, so remove this assert. Additionally, wrap the encoding of CPUID[4].EAX[bits 31:26] into a helper to make the code cleaner. Signed-off-by: Zhao Liu --- Changes since v1: * Use "enum CPUTopoLevel share_level" as the parameter in max_processor_ids_for_cache(). * Make cache_into_passthrough case also use max_processor_ids_for_cache() and max_core_ids_in_package() to encode CPUID[4]. (Yanan) * Rename the title of this patch (the original is "i386: Use CPUCacheInfo.share_level to encode CPUID[4].EAX[bits 25:14]"). --- target/i386/cpu.c | 70 +++++++++++++++++++++++++++++------------------ 1 file changed, 43 insertions(+), 27 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 55aba4889628..c9897c0fe91a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -234,22 +234,53 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *= cache) ((t) =3D=3D UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 0 /* Invalid value */) =20 +static uint32_t max_processor_ids_for_cache(X86CPUTopoInfo *topo_info, + enum CPUTopoLevel share_level) +{ + uint32_t num_ids =3D 0; + + switch (share_level) { + case CPU_TOPO_LEVEL_CORE: + num_ids =3D 1 << apicid_core_offset(topo_info); + break; + case CPU_TOPO_LEVEL_DIE: + num_ids =3D 1 << apicid_die_offset(topo_info); + break; + case CPU_TOPO_LEVEL_PACKAGE: + num_ids =3D 1 << apicid_pkg_offset(topo_info); + break; + default: + /* + * Currently there is no use case for SMT and MODULE, so use + * assert directly to facilitate debugging. + */ + g_assert_not_reached(); + } + + return num_ids - 1; +} + +static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) +{ + uint32_t num_cores =3D 1 << (apicid_pkg_offset(topo_info) - + apicid_core_offset(topo_info)); + return num_cores - 1; +} =20 /* Encode cache info for CPUID[4] */ static void encode_cache_cpuid4(CPUCacheInfo *cache, - int num_apic_ids, int num_cores, + X86CPUTopoInfo *topo_info, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 - assert(num_apic_ids > 0); *eax =3D CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | - ((num_cores - 1) << 26) | - ((num_apic_ids - 1) << 14); + (max_core_ids_in_package(topo_info) << 26) | + (max_processor_ids_for_cache(topo_info, cache->share_level) << = 14); =20 assert(cache->line_size > 0); assert(cache->partitions > 0); @@ -6116,56 +6147,41 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, int host_vcpus_per_cache =3D 1 + ((*eax & 0x3FFC000) >> 14= ); =20 if (cores_per_pkg > 1) { - int addressable_cores_offset =3D - apicid_pkg_offset(&topo_in= fo) - - apicid_core_offset(&topo_i= nfo); - *eax &=3D ~0xFC000000; - *eax |=3D (1 << addressable_cores_offset - 1) << 26; + *eax |=3D max_core_ids_in_package(&topo_info) << 26; } if (host_vcpus_per_cache > cpus_per_pkg) { - int pkg_offset =3D apicid_pkg_offset(&topo_info); - *eax &=3D ~0x3FFC000; - *eax |=3D (1 << pkg_offset - 1) << 14; + *eax |=3D + max_processor_ids_for_cache(&topo_info, + CPU_TOPO_LEVEL_PACKAGE) <<= 14; } } } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { *eax =3D *ebx =3D *ecx =3D *edx =3D 0; } else { *eax =3D 0; - int addressable_cores_offset =3D apicid_pkg_offset(&topo_info)= - - apicid_core_offset(&topo_info); - int core_offset, die_offset; =20 switch (count) { case 0: /* L1 dcache info */ - core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - (1 << core_offset), - (1 << addressable_cores_offset), + &topo_info, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ - core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - (1 << core_offset), - (1 << addressable_cores_offset), + &topo_info, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ - core_offset =3D apicid_core_offset(&topo_info); encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, - (1 << core_offset), - (1 << addressable_cores_offset), + &topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - die_offset =3D apicid_die_offset(&topo_info); if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - (1 << die_offset), - (1 << addressable_cores_offset), + &topo_info, eax, ebx, ecx, edx); break; } --=20 2.34.1 From nobody Wed May 15 12:14:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1690886069; cv=none; d=zohomail.com; s=zohoarc; b=OXrl2kFAnTG/C8P09iqCE7qpmBomNWvvUFaT/LtnQrz6J0yoH2BOeaQ/y7g9Y5sFr8xMvCQRYomWC/pvOW9TlpyZONP03XwGE9AJzS5hMio//KrfFyQbU3WLMcAt4mQWT/FXLyQT9s9cK6NI+Z0cKDJQGGtpNT6v05IvsFjLIBY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690886069; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dryRT18aHEQf9McDkIxzPpXLLekHAS3wdS6A9/GLG9M=; b=G7SYuiG26J4swbUsHxnbpebaFyZpZxzYlvlrNnZa/54M/Oa5JHoMGfjEKStT1YeL0lpjroRKx1Gh7D/0vU5C+1TvCXBS9SIGUfvlzRPMgvjskIEBh3UfabpZFSfIwGG05y0pW3kdtxnooEKn2Cdxu9HUKEwNdy0/EAdlMxD8bsk= ARC-Authentication-Results: i=1; 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d="scan'208";a="400211271" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="731932207" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="731932207" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu Subject: [PATCH v3 15/17] i386: Fix NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Date: Tue, 1 Aug 2023 18:35:25 +0800 Message-Id: <20230801103527.397756-16-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1690886071503100009 Content-Type: text/plain; charset="utf-8" From: Zhao Liu The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information for cpuid 0x8000001D") adds the cache topology for AMD CPU by encoding the number of sharing threads directly. From AMD's APM, NumSharingCache (CPUID[0x8000001D].EAX[bits 25:14]) means [1]: The number of logical processors sharing this cache is the value of this field incremented by 1. To determine which logical processors are sharing a cache, determine a Share Id for each processor as follows: ShareId =3D LocalApicId >> log2(NumSharingCache+1) Logical processors with the same ShareId then share a cache. If NumSharingCache+1 is not a power of two, round it up to the next power of two. From the description above, the caculation of this feild should be same as CPUID[4].EAX[bits 25:14] for intel cpus. So also use the offsets of APIC ID to calculate this field. Note: I don't have the AMD hardware available, hope folks can help me to test this, thanks! [1]: APM, vol.3, appendix.E.4.15 Function 8000_001Dh--Cache Topology Information Cc: Babu Moger Signed-off-by: Zhao Liu --- Changes since v1: * Rename "l3_threads" to "num_apic_ids" in encode_cache_cpuid8000001d(). (Yanan) * Add the description of the original commit and add Cc. --- target/i386/cpu.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c9897c0fe91a..f67b6be10b8d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -361,7 +361,7 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *ca= che, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - uint32_t l3_threads; + uint32_t num_apic_ids; assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 @@ -370,13 +370,11 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *= cache, =20 /* L3 is shared among multiple cores */ if (cache->level =3D=3D 3) { - l3_threads =3D topo_info->modules_per_die * - topo_info->cores_per_module * - topo_info->threads_per_core; - *eax |=3D (l3_threads - 1) << 14; + num_apic_ids =3D 1 << apicid_die_offset(topo_info); } else { - *eax |=3D ((topo_info->threads_per_core - 1) << 14); + num_apic_ids =3D 1 << apicid_core_offset(topo_info); } + *eax |=3D (num_apic_ids - 1) << 14; =20 assert(cache->line_size > 0); assert(cache->partitions > 0); --=20 2.34.1 From nobody Wed May 15 12:14:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1690886040; cv=none; d=zohomail.com; s=zohoarc; b=WJzL2hq1R7xnQ65w4lMr89j33DCnJkSyvmhYfttSkFh0trX60h+cLskYpomvY2YqwYXOP03jnTjkSqEUTUqUpaYWdObFLcDsp+6FfmKT+n5rT1zaoMOoAUFcPAwzTWssIHOY+poc8gtQOFhOyAkm/btSFp55Pyv64dazfUnhn5E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690886040; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vZGsURcrhnAd7b6gR9owkW/xMTvUNBW/kO9fC98eGL0=; b=ZyVT6ZZYPlSbxi+8jg8/UHiocwu2e3VsE6vIHrIL1RJVpy5DnRPjUbP8NaWF45V31rIueMEMOVcdlJGmD/pl2EXFo+2r/5ah6FA7WQjPm44uZDaW+GiLyqbhVgYK6DTigi5Xqc2cEt0HRVmHQ78gXj1CwvuL8nRy6iuIjlzQK58= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690886040071666.2236883467676; Tue, 1 Aug 2023 03:34:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qQmhF-0002Ur-TV; Tue, 01 Aug 2023 06:33:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qQmhD-0002RE-UW for qemu-devel@nongnu.org; Tue, 01 Aug 2023 06:33:43 -0400 Received: from [192.55.52.88] (helo=mgamail.intel.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qQmhC-0003BJ-AS for qemu-devel@nongnu.org; Tue, 01 Aug 2023 06:33:43 -0400 Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Aug 2023 03:25:54 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.28]) by fmsmga007.fm.intel.com with ESMTP; 01 Aug 2023 03:25:51 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690886022; x=1722422022; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pjp88zojrHyw0f2tKKbTL4UQoKNAMSLlpFhgua2H3kE=; b=XVHPUM1qcJzo5w1N+xFDeehnfWF1rPIklWc80wMDqxupcnKPw865gkCA gs4xfoNKcPFN/O4RhL3304trxeJBuxQX/0Nc6P7pejJs28E5MSMzKKKDK uHpElw/+k/4zXjcckyHMDnpa/7yUdl7zGuC+UpaEJptQmD3B0dvhXh+WT omAK/Nccwq9FzI5L/cJTXhTJ6qZfmH3j612e9Tpyj8HfwMFx00BmUbTKi Nzk34HIz+CCAh0QtsWBfqekHpdbga1rgQQhkQj5EXMV72zRBKyA2LhvB1 qdGTLnW6vEWANRihiayxoKqPEwV1rgPVAumppS6dNyi7VZ/A1IS92YayT Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="400211282" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="400211282" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="731932215" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="731932215" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu Subject: [PATCH v3 16/17] i386: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14] Date: Tue, 1 Aug 2023 18:35:26 +0800 Message-Id: <20230801103527.397756-17-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1690886040997100009 Content-Type: text/plain; charset="utf-8" From: Zhao Liu CPUID[0x8000001D].EAX[bits 25:14] is used to represent the cache topology for amd CPUs. After cache models have topology information, we can use CPUCacheInfo.share_level to decide which topology level to be encoded into CPUID[0x8000001D].EAX[bits 25:14]. Signed-off-by: Zhao Liu --- Changes since v1: * Use cache->share_level as the parameter in max_processor_ids_for_cache(). --- target/i386/cpu.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f67b6be10b8d..6eee0274ade4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -361,20 +361,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *= cache, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - uint32_t num_apic_ids; assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 *eax =3D CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); - - /* L3 is shared among multiple cores */ - if (cache->level =3D=3D 3) { - num_apic_ids =3D 1 << apicid_die_offset(topo_info); - } else { - num_apic_ids =3D 1 << apicid_core_offset(topo_info); - } - *eax |=3D (num_apic_ids - 1) << 14; + *eax |=3D max_processor_ids_for_cache(topo_info, cache->share_level) <= < 14; =20 assert(cache->line_size > 0); assert(cache->partitions > 0); --=20 2.34.1 From nobody Wed May 15 12:14:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1690886110; cv=none; d=zohomail.com; s=zohoarc; b=DoFlIyDuoeBn9FaChtRcBvVIQDje/b/U49g4HyHbrA87IANUjpBAo0k6SFO8FGcyAq8hk4eSeiz9DsXOixtNjMjjJ+o+5fUBbyU036tIBsuh2ZV+Vln2ntNBri/IL7ye/SdBk0MOpX3erm8dQf9tGrabQrCoBd8GVnPQ3bDOPw0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690886110; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=anbnAIpIHCaGt6ilf8agaqcDH/GamBhrBj7Clz/KfcU=; b=oI0QFf04Xsmo8EMWD8+uN81hs5plZRhlTlzLI167jX2faI6J62qWHDf9PlQMQI9jmAnQXpng2EzfcOqq+n7do/V7cQB/oEDXQOmv4CSGxWLCyCctMLq8Ci4l1xVygPd/MSDV75ZPjbuyiaNsQz5Zli92XHwDESueR2Tpq97r9+s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690886109864946.924802581851; Tue, 1 Aug 2023 03:35:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qQmhD-0002Or-7X; Tue, 01 Aug 2023 06:33:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qQmhB-0002HA-Jh for qemu-devel@nongnu.org; Tue, 01 Aug 2023 06:33:41 -0400 Received: from [192.55.52.88] (helo=mgamail.intel.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qQmh9-0003Cu-Vf for qemu-devel@nongnu.org; Tue, 01 Aug 2023 06:33:41 -0400 Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Aug 2023 03:25:57 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.28]) by fmsmga007.fm.intel.com with ESMTP; 01 Aug 2023 03:25:54 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690886020; x=1722422020; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XFNRA6qL99jXr5lXDxjIiHWNWpIj8xxG4L5OTXEsoag=; b=nlI0GacisCgnT9cSwDp+jhZq77tyV4lqw4Q9QSTyIl1Estnk7j467SQU hDynSeOwlpj6ZH7qEcIj9MVSemejh6ufXb80hKAyLrw3FNepLcOKX7Pmp LwfzM3mDSkhJyeKWTpRk3zqEJU4Gm9+aC5OLY7RyVFMzzaJa8bc6Uotf9 2tjHLDysf9dXsGN8VP2Wr0PY3iEhL+hqh90Qv8jFtL0ECWTQDQkoxVmAc 0qjBI0QZ51TsayWr/AdJAeM/N/IL4mhSbCYX7WX20zkAOUjw2f5b8v5K2 b+AKEeDs2Rr6CDUJgHOZg5+vvjdkDLZXXRSEvJ73n2xHjIYHuyq5UNTLB A==; X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="400211298" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="400211298" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10788"; a="731932224" X-IronPort-AV: E=Sophos;i="6.01,246,1684825200"; d="scan'208";a="731932224" From: Zhao Liu To: Eduardo Habkost , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , "Michael S . Tsirkin" , Richard Henderson , Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhenyu Wang , Xiaoyao Li , Babu Moger , Zhao Liu , Yongwei Ma Subject: [PATCH v3 17/17] i386: Add new property to control L2 cache topo in CPUID.04H Date: Tue, 1 Aug 2023 18:35:27 +0800 Message-Id: <20230801103527.397756-18-zhao1.liu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230801103527.397756-1-zhao1.liu@linux.intel.com> References: <20230801103527.397756-1-zhao1.liu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 192.55.52.88 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.88; envelope-from=zhao1.liu@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1690886112175100003 Content-Type: text/plain; charset="utf-8" From: Zhao Liu The property x-l2-cache-topo will be used to change the L2 cache topology in CPUID.04H. Now it allows user to set the L2 cache is shared in core level or cluster level. If user passes "-cpu x-l2-cache-topo=3D[core|cluster]" then older L2 cache topology will be overrided by the new topology setting. Here we expose to user "cluster" instead of "module", to be consistent with "cluster-id" naming. Since CPUID.04H is used by intel CPUs, this property is available on intel CPUs as for now. When necessary, it can be extended to CPUID.8000001DH for amd CPUs. Signed-off-by: Zhao Liu Tested-by: Yongwei Ma --- Changes since v1: * Rename MODULE branch to CPU_TOPO_LEVEL_MODULE to match the previous renaming changes. --- target/i386/cpu.c | 34 +++++++++++++++++++++++++++++++++- target/i386/cpu.h | 2 ++ 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6eee0274ade4..f4c48e19fa4e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -243,6 +243,9 @@ static uint32_t max_processor_ids_for_cache(X86CPUTopoI= nfo *topo_info, case CPU_TOPO_LEVEL_CORE: num_ids =3D 1 << apicid_core_offset(topo_info); break; + case CPU_TOPO_LEVEL_MODULE: + num_ids =3D 1 << apicid_module_offset(topo_info); + break; case CPU_TOPO_LEVEL_DIE: num_ids =3D 1 << apicid_die_offset(topo_info); break; @@ -251,7 +254,7 @@ static uint32_t max_processor_ids_for_cache(X86CPUTopoI= nfo *topo_info, break; default: /* - * Currently there is no use case for SMT and MODULE, so use + * Currently there is no use case for SMT, so use * assert directly to facilitate debugging. */ g_assert_not_reached(); @@ -7458,6 +7461,34 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) env->cache_info_amd.l3_cache =3D &legacy_l3_cache; } =20 + if (cpu->l2_cache_topo_level) { + /* + * FIXME: Currently only supports changing CPUID[4] (for intel), a= nd + * will support changing CPUID[0x8000001D] when necessary. + */ + if (!IS_INTEL_CPU(env)) { + error_setg(errp, "only intel cpus supports x-l2-cache-topo"); + return; + } + + if (!strcmp(cpu->l2_cache_topo_level, "core")) { + env->cache_info_cpuid4.l2_cache->share_level =3D CPU_TOPO_LEVE= L_CORE; + } else if (!strcmp(cpu->l2_cache_topo_level, "cluster")) { + /* + * We expose to users "cluster" instead of "module", to be + * consistent with "cluster-id" naming. + */ + env->cache_info_cpuid4.l2_cache->share_level =3D + CPU_TOPO_LEVEL_MOD= ULE; + } else { + error_setg(errp, + "x-l2-cache-topo doesn't support '%s', " + "and it only supports 'core' or 'cluster'", + cpu->l2_cache_topo_level); + return; + } + } + #ifndef CONFIG_USER_ONLY MachineState *ms =3D MACHINE(qdev_get_machine()); qemu_register_reset(x86_cpu_machine_reset_cb, cpu); @@ -7961,6 +7992,7 @@ static Property x86_cpu_properties[] =3D { false), DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, true), + DEFINE_PROP_STRING("x-l2-cache-topo", X86CPU, l2_cache_topo_level), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 3f0cdc45607a..24db2a0d9588 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2057,6 +2057,8 @@ struct ArchCPU { int32_t hv_max_vps; =20 bool xen_vapic; + + char *l2_cache_topo_level; }; =20 =20 --=20 2.34.1