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helo=lists.gnu.org; Received-SPF: pass client-ip=66.111.4.29; envelope-from=its@irrelevant.dk; helo=out5-smtp.messagingengine.com X-Spam_score_int: -37 X-Spam_score: -3.8 X-Spam_bar: --- X-Spam_report: (-3.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1690745465730100003 From: Klaus Jensen Use the stl/ldl pci dma api for writing/reading doorbells. This removes the explicit endian conversions. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: C=C3=A9dric Le Goater Tested-by: C=C3=A9dric Le Goater Reviewed-by: Thomas Huth Signed-off-by: Klaus Jensen --- hw/nvme/ctrl.c | 42 +++++++++++++----------------------------- 1 file changed, 13 insertions(+), 29 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index dadc2dc7da10..f2e5a2fa737b 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -1468,20 +1468,16 @@ static inline void nvme_blk_write(BlockBackend *blk= , int64_t offset, =20 static void nvme_update_cq_eventidx(const NvmeCQueue *cq) { - uint32_t v =3D cpu_to_le32(cq->head); - trace_pci_nvme_update_cq_eventidx(cq->cqid, cq->head); =20 - pci_dma_write(PCI_DEVICE(cq->ctrl), cq->ei_addr, &v, sizeof(v)); + stl_le_pci_dma(PCI_DEVICE(cq->ctrl), cq->ei_addr, cq->head, + MEMTXATTRS_UNSPECIFIED); } =20 static void nvme_update_cq_head(NvmeCQueue *cq) { - uint32_t v; - - pci_dma_read(PCI_DEVICE(cq->ctrl), cq->db_addr, &v, sizeof(v)); - - cq->head =3D le32_to_cpu(v); + ldl_le_pci_dma(PCI_DEVICE(cq->ctrl), cq->db_addr, &cq->head, + MEMTXATTRS_UNSPECIFIED); =20 trace_pci_nvme_update_cq_head(cq->cqid, cq->head); } @@ -6801,7 +6797,6 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const = NvmeRequest *req) PCIDevice *pci =3D PCI_DEVICE(n); uint64_t dbs_addr =3D le64_to_cpu(req->cmd.dptr.prp1); uint64_t eis_addr =3D le64_to_cpu(req->cmd.dptr.prp2); - uint32_t v; int i; =20 /* Address should be page aligned */ @@ -6819,8 +6814,6 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const = NvmeRequest *req) NvmeCQueue *cq =3D n->cq[i]; =20 if (sq) { - v =3D cpu_to_le32(sq->tail); - /* * CAP.DSTRD is 0, so offset of ith sq db_addr is (i<<3) * nvme_process_db() uses this hard-coded way to calculate @@ -6828,7 +6821,7 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const = NvmeRequest *req) */ sq->db_addr =3D dbs_addr + (i << 3); sq->ei_addr =3D eis_addr + (i << 3); - pci_dma_write(pci, sq->db_addr, &v, sizeof(sq->tail)); + stl_le_pci_dma(pci, sq->db_addr, sq->tail, MEMTXATTRS_UNSPECIF= IED); =20 if (n->params.ioeventfd && sq->sqid !=3D 0) { if (!nvme_init_sq_ioeventfd(sq)) { @@ -6838,12 +6831,10 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, cons= t NvmeRequest *req) } =20 if (cq) { - v =3D cpu_to_le32(cq->head); - /* CAP.DSTRD is 0, so offset of ith cq db_addr is (i<<3)+(1<<2= ) */ cq->db_addr =3D dbs_addr + (i << 3) + (1 << 2); cq->ei_addr =3D eis_addr + (i << 3) + (1 << 2); - pci_dma_write(pci, cq->db_addr, &v, sizeof(cq->head)); + stl_le_pci_dma(pci, cq->db_addr, cq->head, MEMTXATTRS_UNSPECIF= IED); =20 if (n->params.ioeventfd && cq->cqid !=3D 0) { if (!nvme_init_cq_ioeventfd(cq)) { @@ -6974,20 +6965,16 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeReq= uest *req) =20 static void nvme_update_sq_eventidx(const NvmeSQueue *sq) { - uint32_t v =3D cpu_to_le32(sq->tail); - trace_pci_nvme_update_sq_eventidx(sq->sqid, sq->tail); =20 - pci_dma_write(PCI_DEVICE(sq->ctrl), sq->ei_addr, &v, sizeof(v)); + stl_le_pci_dma(PCI_DEVICE(sq->ctrl), sq->ei_addr, sq->tail, + MEMTXATTRS_UNSPECIFIED); } =20 static void nvme_update_sq_tail(NvmeSQueue *sq) { - uint32_t v; - - pci_dma_read(PCI_DEVICE(sq->ctrl), sq->db_addr, &v, sizeof(v)); - - sq->tail =3D le32_to_cpu(v); + ldl_le_pci_dma(PCI_DEVICE(sq->ctrl), sq->db_addr, &sq->tail, + MEMTXATTRS_UNSPECIFIED); =20 trace_pci_nvme_update_sq_tail(sq->sqid, sq->tail); } @@ -7592,7 +7579,7 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr a= ddr, unsigned size) static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val) { PCIDevice *pci =3D PCI_DEVICE(n); - uint32_t qid, v; + uint32_t qid; =20 if (unlikely(addr & ((1 << 2) - 1))) { NVME_GUEST_ERR(pci_nvme_ub_db_wr_misaligned, @@ -7659,8 +7646,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) start_sqs =3D nvme_cq_full(cq) ? 1 : 0; cq->head =3D new_head; if (!qid && n->dbbuf_enabled) { - v =3D cpu_to_le32(cq->head); - pci_dma_write(pci, cq->db_addr, &v, sizeof(cq->head)); + stl_le_pci_dma(pci, cq->db_addr, cq->head, MEMTXATTRS_UNSPECIF= IED); } if (start_sqs) { NvmeSQueue *sq; @@ -7720,8 +7706,6 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) =20 sq->tail =3D new_tail; if (!qid && n->dbbuf_enabled) { - v =3D cpu_to_le32(sq->tail); - /* * The spec states "the host shall also update the controller's * corresponding doorbell property to match the value of that = entry @@ -7735,7 +7719,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) * including ones that run on Linux, are not updating Admin Qu= eues, * so we can't trust reading it for an appropriate sq tail. */ - pci_dma_write(pci, sq->db_addr, &v, sizeof(sq->tail)); + stl_le_pci_dma(pci, sq->db_addr, sq->tail, MEMTXATTRS_UNSPECIF= IED); } =20 qemu_bh_schedule(sq->bh); --=20 2.41.0