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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id u8-20020a17090341c800b001b882880550sm1230139ple.282.2023.07.27.03.24.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 03:24:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1690453489; x=1691058289; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=6yy/ilJ4eRlk81CPTCEAUhyUjpFl7zB/SF7tY6vWp9Q=; b=ZvMzixzW84dQvuWiL5JHfHBog7fZy0l4GaUZUye7vaTLYRPeY2eFe4sLVa5TNUe+mc L/BC4RtrT8v6VVLrHrAF0IkPS+FG1ADidjQLyu/I3wTEsvZLUVzr7KeUWLmBBwJKf0Ea B0eA4uYdsruEWYwYbwWXTydoTxS0jbuTPHVnEucyMu34W0jZgZgd55JDHDCS82dcfYM8 VhBXfA8eX4ipbZy/A77q2qOq7susFIBqDQLvVZP9CYiTp5noyOgmHQr/4dsvBZcLYjW3 fJEJmIg2ais5W/u1LSc8CI128PPGwHry48ts9TWSPe755WuBwH+pEPqXp1Q+vQtn4WnL TVKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690453489; x=1691058289; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=6yy/ilJ4eRlk81CPTCEAUhyUjpFl7zB/SF7tY6vWp9Q=; b=D7k+Euzb3xkIpR5Zz824ZmsMnN1hbK6AAh57V4uwpH0O7Eob4rWNCGxzla1yH+D0ur /71UyYhNOnCrqsy5Hk16LCEwVhMoTxPZ9rP+lXW86CGYyoIuXs6C96vNlMyTObyTVUsU TsC92O1kmzkBvwEr+Le/tGjdONOhGRgi6iT22ZNLPh7i69AY6/00Gp+laAgnx+8IOzXY /Y1ZqHTbH2aOydO+WBxH+oZ4U8Ru4nVpU1TjRFXNsUnDUSUpEUzhbDuV/i9OYDaP7lsC 27cCyRO30qutpVAlvtYdi4cjDxSbO8+L7IY1kR7z1S8MS92CRUr72IZpdvsHEwMEC8Ed uoeg== X-Gm-Message-State: ABy/qLZrt1dGw/UMcgY0iOGVBR2K8Zbz1P93e6h1NM+zpM8BMhnuIIof mfBfcsg7acWesdwZJMAAXm1lYl6ohIfLhb6lrmYi8S3B3vYtgntlUebtCJZqBHCzmgWHUZeE/u2 Nw5JExebvX4NSip+SXi2ttTiHZLEypq9Fx7wz9ZzkAtIHwozVURDh0j/y6lym54UHI8CfNcCghA sm11lg X-Google-Smtp-Source: APBJJlEItx4fGp2NhStoWwWHVczs+3bVjo6yZrBaH71XSwXLXYElZVB+DMliOQsc+NtoHfaYKBZH2A== X-Received: by 2002:a05:6808:138d:b0:3a4:3192:1627 with SMTP id c13-20020a056808138d00b003a431921627mr3005146oiw.42.1690453488502; Thu, 27 Jul 2023 03:24:48 -0700 (PDT) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: rkanwal@rivosinc.com, anup@brainfault.org, dbarboza@ventanamicro.com, ajones@ventanamicro.com, atishp@atishpatra.org, vincent.chen@sifive.com, greentime.hu@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei Subject: [PATCH v7 1/5] target/riscv: support the AIA device emulation with KVM enabled Date: Thu, 27 Jul 2023 10:24:33 +0000 Message-Id: <20230727102439.22554-2-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230727102439.22554-1-yongxuan.wang@sifive.com> References: <20230727102439.22554-1-yongxuan.wang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=yongxuan.wang@sifive.com; helo=mail-ot1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1690458173962100003 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In this patch, we create the APLIC and IMSIC FDT helper functions and remove M mode AIA devices when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- hw/riscv/virt.c | 290 +++++++++++++++++++++++------------------------- 1 file changed, 137 insertions(+), 153 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d90286dc46..f595380be1 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -516,79 +516,28 @@ static uint32_t imsic_num_bits(uint32_t count) return ret; } =20 -static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, - uint32_t *phandle, uint32_t *intc_phandles, - uint32_t *msi_m_phandle, uint32_t *msi_s_phan= dle) +static void create_fdt_one_imsic(RISCVVirtState *s, hwaddr base_addr, + uint32_t *intc_phandles, uint32_t msi_pha= ndle, + bool m_mode, uint32_t imsic_guest_bits) { int cpu, socket; char *imsic_name; MachineState *ms =3D MACHINE(s); int socket_count =3D riscv_socket_count(ms); - uint32_t imsic_max_hart_per_socket, imsic_guest_bits; + uint32_t imsic_max_hart_per_socket; uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; =20 - *msi_m_phandle =3D (*phandle)++; - *msi_s_phandle =3D (*phandle)++; imsic_cells =3D g_new0(uint32_t, ms->smp.cpus * 2); imsic_regs =3D g_new0(uint32_t, socket_count * 4); =20 - /* M-level IMSIC node */ for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { imsic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_EXT); + imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_= S_EXT); } - imsic_max_hart_per_socket =3D 0; - for (socket =3D 0; socket < socket_count; socket++) { - imsic_addr =3D memmap[VIRT_IMSIC_M].base + - socket * VIRT_IMSIC_GROUP_MAX_SIZE; - imsic_size =3D IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; - imsic_regs[socket * 4 + 0] =3D 0; - imsic_regs[socket * 4 + 1] =3D cpu_to_be32(imsic_addr); - imsic_regs[socket * 4 + 2] =3D 0; - imsic_regs[socket * 4 + 3] =3D cpu_to_be32(imsic_size); - if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { - imsic_max_hart_per_socket =3D s->soc[socket].num_harts; - } - } - imsic_name =3D g_strdup_printf("/soc/imsics@%lx", - (unsigned long)memmap[VIRT_IMSIC_M].base); - qemu_fdt_add_subnode(ms->fdt, imsic_name); - qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", - "riscv,imsics"); - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", - FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", - NULL, 0); - qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", - NULL, 0); - qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", - imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); - qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, - socket_count * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", - VIRT_IRQCHIP_NUM_MSIS); - if (socket_count > 1) { - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", - imsic_num_bits(imsic_max_hart_per_socket)); - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits= ", - imsic_num_bits(socket_count)); - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shif= t", - IMSIC_MMIO_GROUP_MIN_SHIFT); - } - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle); - - g_free(imsic_name); =20 - /* S-level IMSIC node */ - for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { - imsic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_S_EXT); - } - imsic_guest_bits =3D imsic_num_bits(s->aia_guests + 1); imsic_max_hart_per_socket =3D 0; for (socket =3D 0; socket < socket_count; socket++) { - imsic_addr =3D memmap[VIRT_IMSIC_S].base + - socket * VIRT_IMSIC_GROUP_MAX_SIZE; + imsic_addr =3D base_addr + socket * VIRT_IMSIC_GROUP_MAX_SIZE; imsic_size =3D IMSIC_HART_SIZE(imsic_guest_bits) * s->soc[socket].num_harts; imsic_regs[socket * 4 + 0] =3D 0; @@ -599,119 +548,151 @@ static void create_fdt_imsic(RISCVVirtState *s, con= st MemMapEntry *memmap, imsic_max_hart_per_socket =3D s->soc[socket].num_harts; } } - imsic_name =3D g_strdup_printf("/soc/imsics@%lx", - (unsigned long)memmap[VIRT_IMSIC_S].base); + + imsic_name =3D g_strdup_printf("/soc/imsics@%lx", (unsigned long)base_= addr); qemu_fdt_add_subnode(ms->fdt, imsic_name); - qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", - "riscv,imsics"); + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsi= cs"); qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", - FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", - NULL, 0); - qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", - NULL, 0); + FDT_IMSIC_INT_CELLS); + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", - imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, - socket_count * sizeof(uint32_t) * 4); + socket_count * sizeof(uint32_t) * 4); qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", - VIRT_IRQCHIP_NUM_MSIS); + VIRT_IRQCHIP_NUM_MSIS); + if (imsic_guest_bits) { qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits= ", - imsic_guest_bits); + imsic_guest_bits); } + if (socket_count > 1) { qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", - imsic_num_bits(imsic_max_hart_per_socket)); + imsic_num_bits(imsic_max_hart_per_socket)); qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits= ", - imsic_num_bits(socket_count)); + imsic_num_bits(socket_count)); qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shif= t", - IMSIC_MMIO_GROUP_MIN_SHIFT); + IMSIC_MMIO_GROUP_MIN_SHIFT); } - qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle); - g_free(imsic_name); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", msi_phandle); =20 + g_free(imsic_name); g_free(imsic_regs); g_free(imsic_cells); } =20 -static void create_fdt_socket_aplic(RISCVVirtState *s, - const MemMapEntry *memmap, int socket, - uint32_t msi_m_phandle, - uint32_t msi_s_phandle, - uint32_t *phandle, - uint32_t *intc_phandles, - uint32_t *aplic_phandles) +static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, + uint32_t *phandle, uint32_t *intc_phandles, + uint32_t *msi_m_phandle, uint32_t *msi_s_phan= dle) +{ + *msi_m_phandle =3D (*phandle)++; + *msi_s_phandle =3D (*phandle)++; + + if (!kvm_enabled()) { + /* M-level IMSIC node */ + create_fdt_one_imsic(s, memmap[VIRT_IMSIC_M].base, intc_phandles, + *msi_m_phandle, true, 0); + } + + /* S-level IMSIC node */ + create_fdt_one_imsic(s, memmap[VIRT_IMSIC_S].base, intc_phandles, + *msi_s_phandle, false, + imsic_num_bits(s->aia_guests + 1)); + +} + +static void create_fdt_one_aplic(RISCVVirtState *s, int socket, + unsigned long aplic_addr, uint32_t aplic_= size, + uint32_t msi_phandle, + uint32_t *intc_phandles, + uint32_t aplic_phandle, + uint32_t aplic_child_phandle, + bool m_mode) { int cpu; char *aplic_name; uint32_t *aplic_cells; - unsigned long aplic_addr; MachineState *ms =3D MACHINE(s); - uint32_t aplic_m_phandle, aplic_s_phandle; =20 - aplic_m_phandle =3D (*phandle)++; - aplic_s_phandle =3D (*phandle)++; aplic_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 2); =20 - /* M-level APLIC node */ for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { aplic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - aplic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_EXT); + aplic_cells[cpu * 2 + 1] =3D cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_= S_EXT); } - aplic_addr =3D memmap[VIRT_APLIC_M].base + - (memmap[VIRT_APLIC_M].size * socket); + aplic_name =3D g_strdup_printf("/soc/aplic@%lx", aplic_addr); qemu_fdt_add_subnode(ms->fdt, aplic_name); qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,apli= c"); qemu_fdt_setprop_cell(ms->fdt, aplic_name, - "#interrupt-cells", FDT_APLIC_INT_CELLS); + "#interrupt-cells", FDT_APLIC_INT_CELLS); qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); + if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC) { qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", - aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); + aplic_cells, + s->soc[socket].num_harts * sizeof(uint32_t) * 2); } else { - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", - msi_m_phandle); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phand= le); } + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", - 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); + 0x0, aplic_addr, 0x0, aplic_size); qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", - VIRT_IRQCHIP_NUM_SOURCES); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", - aplic_s_phandle); - qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", - aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); + VIRT_IRQCHIP_NUM_SOURCES); + + if (aplic_child_phandle) { + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", + aplic_child_phandle); + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", + aplic_child_phandle, 0x1, + VIRT_IRQCHIP_NUM_SOURCES); + } + riscv_socket_fdt_write_id(ms, aplic_name, socket); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_phandle); + g_free(aplic_name); + g_free(aplic_cells); +} =20 - /* S-level APLIC node */ - for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { - aplic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); - aplic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_S_EXT); +static void create_fdt_socket_aplic(RISCVVirtState *s, + const MemMapEntry *memmap, int socket, + uint32_t msi_m_phandle, + uint32_t msi_s_phandle, + uint32_t *phandle, + uint32_t *intc_phandles, + uint32_t *aplic_phandles) +{ + char *aplic_name; + unsigned long aplic_addr; + MachineState *ms =3D MACHINE(s); + uint32_t aplic_m_phandle, aplic_s_phandle; + + aplic_m_phandle =3D (*phandle)++; + aplic_s_phandle =3D (*phandle)++; + + if (!kvm_enabled()) { + /* M-level APLIC node */ + aplic_addr =3D memmap[VIRT_APLIC_M].base + + (memmap[VIRT_APLIC_M].size * socket); + create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].s= ize, + msi_m_phandle, intc_phandles, + aplic_m_phandle, aplic_s_phandle, + true); } + + /* S-level APLIC node */ aplic_addr =3D memmap[VIRT_APLIC_S].base + (memmap[VIRT_APLIC_S].size * socket); + create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, + msi_s_phandle, intc_phandles, + aplic_s_phandle, 0, + false); + aplic_name =3D g_strdup_printf("/soc/aplic@%lx", aplic_addr); - qemu_fdt_add_subnode(ms->fdt, aplic_name); - qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,apli= c"); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, - "#interrupt-cells", FDT_APLIC_INT_CELLS); - qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); - if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC) { - qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", - aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); - } else { - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", - msi_s_phandle); - } - qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", - 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", - VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(ms, aplic_name, socket); - qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle); =20 if (!socket) { platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, @@ -722,7 +703,6 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, =20 g_free(aplic_name); =20 - g_free(aplic_cells); aplic_phandles[socket] =3D aplic_s_phandle; } =20 @@ -1163,16 +1143,20 @@ static DeviceState *virt_create_aia(RISCVVirtAIATyp= e aia_type, int aia_guests, int i; hwaddr addr; uint32_t guest_bits; - DeviceState *aplic_m; - bool msimode =3D (aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) ? true : = false; + DeviceState *aplic_s =3D NULL; + DeviceState *aplic_m =3D NULL; + bool msimode =3D aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC; =20 if (msimode) { - /* Per-socket M-level IMSICs */ - addr =3D memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX= _SIZE; - for (i =3D 0; i < hart_count; i++) { - riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), - base_hartid + i, true, 1, - VIRT_IRQCHIP_NUM_MSIS); + if (!kvm_enabled()) { + /* Per-socket M-level IMSICs */ + addr =3D memmap[VIRT_IMSIC_M].base + + socket * VIRT_IMSIC_GROUP_MAX_SIZE; + for (i =3D 0; i < hart_count; i++) { + riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), + base_hartid + i, true, 1, + VIRT_IRQCHIP_NUM_MSIS); + } } =20 /* Per-socket S-level IMSICs */ @@ -1185,29 +1169,29 @@ static DeviceState *virt_create_aia(RISCVVirtAIATyp= e aia_type, int aia_guests, } } =20 - /* Per-socket M-level APLIC */ - aplic_m =3D riscv_aplic_create( - memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, - memmap[VIRT_APLIC_M].size, - (msimode) ? 0 : base_hartid, - (msimode) ? 0 : hart_count, - VIRT_IRQCHIP_NUM_SOURCES, - VIRT_IRQCHIP_NUM_PRIO_BITS, - msimode, true, NULL); - - if (aplic_m) { - /* Per-socket S-level APLIC */ - riscv_aplic_create( - memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, - memmap[VIRT_APLIC_S].size, - (msimode) ? 0 : base_hartid, - (msimode) ? 0 : hart_count, - VIRT_IRQCHIP_NUM_SOURCES, - VIRT_IRQCHIP_NUM_PRIO_BITS, - msimode, false, aplic_m); + if (!kvm_enabled()) { + /* Per-socket M-level APLIC */ + aplic_m =3D riscv_aplic_create(memmap[VIRT_APLIC_M].base + + socket * memmap[VIRT_APLIC_M].size, + memmap[VIRT_APLIC_M].size, + (msimode) ? 0 : base_hartid, + (msimode) ? 0 : hart_count, + VIRT_IRQCHIP_NUM_SOURCES, + VIRT_IRQCHIP_NUM_PRIO_BITS, + msimode, true, NULL); } =20 - return aplic_m; + /* Per-socket S-level APLIC */ + aplic_s =3D riscv_aplic_create(memmap[VIRT_APLIC_S].base + + socket * memmap[VIRT_APLIC_S].size, + memmap[VIRT_APLIC_S].size, + (msimode) ? 0 : base_hartid, + (msimode) ? 0 : hart_count, + VIRT_IRQCHIP_NUM_SOURCES, + VIRT_IRQCHIP_NUM_PRIO_BITS, + msimode, false, aplic_m); + + return kvm_enabled() ? aplic_s : aplic_m; } =20 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) --=20 2.17.1 From nobody Wed May 15 21:08:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1690457743; cv=none; d=zohomail.com; s=zohoarc; b=mv31q35OeM6o4WqLDEFxlwy2yQVD33Ya5NnbzhZu89zNpbzwYbjLdh1Vw10tag8b7qqmXXi7wmj4hP37mAWUhAp6gM8b5NhpUdmpbYaWiWuJS3QvQx6lFiwK3QQjksFH+rhHOPFHJW79AWG+mr/HG9Wyu7+ArfuoIjo2gCxamZI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690457743; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=GfEVzfDMM3KV/MRFcXCu/fGQgJk4J1J61XVMjT70iMs=; b=d3VQhuFKhhVBTtv5dcMTt4kq6kGNuEpDoKLMzBoTcWQBUwlr7bQwjm6L844B/NGSpCRad1sA9jYBEXzgYOeyDm7LQJh6p73jbBLM5S4B2T06dmWFNPYk0UMAg4YgvN8WfhUGCbl9oe0A1696SCZfbRAUUbEUh9oWvGdix36bUqQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690457743530391.05598055200335; Thu, 27 Jul 2023 04:35:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qOyBJ-0003Ph-MJ; Thu, 27 Jul 2023 06:25:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qOyAy-0003PN-Fo for qemu-devel@nongnu.org; Thu, 27 Jul 2023 06:24:56 -0400 Received: from mail-io1-xd2f.google.com ([2607:f8b0:4864:20::d2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qOyAw-0003tw-Oo for qemu-devel@nongnu.org; Thu, 27 Jul 2023 06:24:56 -0400 Received: by mail-io1-xd2f.google.com with SMTP id ca18e2360f4ac-7906614bc90so5389639f.3 for ; Thu, 27 Jul 2023 03:24:54 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id u8-20020a17090341c800b001b882880550sm1230139ple.282.2023.07.27.03.24.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 03:24:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1690453493; x=1691058293; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=GfEVzfDMM3KV/MRFcXCu/fGQgJk4J1J61XVMjT70iMs=; b=cHmrInueGEngMD7UYGmB+iSXoktK/awClLPYSSKF/pxXfwAGRn+ArthLC/yhmHpuJB LswL/BReQY7IL6c2/yJXWuk09AYNEeR2QJscAvtNifHzohRaMFnzh7JCCOs+E/qsZn5n TS7CmIir0KqXVnwtD7qWEC8ZpYvZMPqiD2NQ3Vn+58/3ZCWF2Spok7iS6cAIvZaQ3h8H yMZJIHYAKXPamwly2j9kdO7kitEsCGSBFTRscnmDvQltEnV0RpJAfcpbrmq5R22FK8Q+ slnlFFAe9ukcL6dPVpCUHcvwdNNeIatrHV5mkFebfpIzyIR6/kQjINlH/Qjb8WoywZcp WcCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690453493; x=1691058293; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=GfEVzfDMM3KV/MRFcXCu/fGQgJk4J1J61XVMjT70iMs=; b=Y6QQNQ+R06Ndcy/hsjp9w7MKeYDDaDKOMtxyasrJyTy5e2hr0XJ7/f2k+0vl6uk/7e Yh6bdQ+Pth6nTnnPEYNfosbWZyByV+BOJomiihN7vxfhu112eiYq6eRCtsDOT51dphqa 70yKEJCVBrEneWVbDQb6Pqa/i/Z1LQBq0JTz2dptMo1lRSShMFn9F807QN8VPxI+zeF6 Yv8MYJEQUym5oO3Lpw+PLF07rhWCv5visI38j8gcOl0p16DhrJPR6JYGCLJt85g0s3jP 8hWxvkeDoRuSue9F55e48KPb4F6aZ8zWzkmNtWdJYlFDnc/TXtgU76lVLQb6GRVUGndF f5EA== X-Gm-Message-State: ABy/qLbE4OGEuX2U5F+fbHj+XHqEPmZD2lK26Shg3PWC3N4Tzx511g+K ptO8PiPAV+XC2Su2AlHcTD9iBE812mLUK3zJPItle6W3IGTc1hFO0ArlJGGgxrID0j5juL6tXYS raeQW6vfaB8objqCHpruL5uBGlCTIHeXzPbPncgnaKNBFeuAfY272kMA+pafiU0T+nHgGjUgKnI R8vMqF X-Google-Smtp-Source: APBJJlGmpqtL4QEdAiDixYp4kNbQW1CQ9NkC8foOTmxv9KtWAPuVL9V2HinYgjq9XtD2a/1AO9/O7w== X-Received: by 2002:a05:6e02:1a6a:b0:345:fbdc:bb78 with SMTP id w10-20020a056e021a6a00b00345fbdcbb78mr5294262ilv.29.1690453493285; Thu, 27 Jul 2023 03:24:53 -0700 (PDT) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: rkanwal@rivosinc.com, anup@brainfault.org, dbarboza@ventanamicro.com, ajones@ventanamicro.com, atishp@atishpatra.org, vincent.chen@sifive.com, greentime.hu@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Paolo Bonzini , kvm@vger.kernel.org Subject: [PATCH v7 2/5] target/riscv: check the in-kernel irqchip support Date: Thu, 27 Jul 2023 10:24:34 +0000 Message-Id: <20230727102439.22554-3-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230727102439.22554-1-yongxuan.wang@sifive.com> References: <20230727102439.22554-1-yongxuan.wang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d2f; envelope-from=yongxuan.wang@sifive.com; helo=mail-io1-xd2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1690457744547100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We check the in-kernel irqchip support when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 9d8a8982f9..005e054604 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -914,7 +914,15 @@ int kvm_arch_init(MachineState *ms, KVMState *s) =20 int kvm_arch_irqchip_create(KVMState *s) { - return 0; + if (kvm_kernel_irqchip_split()) { + error_report("-machine kernel_irqchip=3Dsplit is not supported on = RISC-V."); + exit(1); + } + + /* + * We can create the VAIA using the newer device control API. + */ + return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); } =20 int kvm_arch_process_async_events(CPUState *cs) --=20 2.17.1 From nobody Wed May 15 21:08:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1690456978; cv=none; d=zohomail.com; s=zohoarc; b=cajxjfN362g92VxeIingEQPWoPGpD8a3xs0Lgim9LA9zQlviCmdZzLFaWk1qsyA92NAZAP1kCJxoI1bKdYJJCPkP4K3JFJjHrO5Nf45Bz4pZXysssmsTIrw6lCPB2ZKu8201BA0vKRjJGW7pon+VE38QGKl1xtIXg4t7l8ryuX4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690456978; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=p3orrnsVpmPvdMzKCfa6SEMJluYKUnGd5kHcMJ1WXrM=; b=WCgeVx1sU8Oq3i3opReG7PW8rdNRKi6cYPLSi6MAgbNsr0WAY97roRDIq2NjaNRUtj1F6YlG6R8dUEmd7C4XMINe++5PYkgY9emQvno5qEDonG84Q5tmg/YO2F+cpXjV641cB6C9jm7tBUTJ3dshSTop3cIypeVATl2MtJzwurQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690456978057757.6550674842784; Thu, 27 Jul 2023 04:22:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qOyBo-0003Yg-ND; Thu, 27 Jul 2023 06:25:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qOyB4-0003Sm-IZ for qemu-devel@nongnu.org; Thu, 27 Jul 2023 06:25:14 -0400 Received: from mail-oa1-x36.google.com ([2001:4860:4864:20::36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qOyB2-0003uh-33 for qemu-devel@nongnu.org; Thu, 27 Jul 2023 06:25:02 -0400 Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-1bb98474b8cso658287fac.3 for ; Thu, 27 Jul 2023 03:24:59 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id u8-20020a17090341c800b001b882880550sm1230139ple.282.2023.07.27.03.24.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 03:24:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1690453498; x=1691058298; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=p3orrnsVpmPvdMzKCfa6SEMJluYKUnGd5kHcMJ1WXrM=; b=EQwROzf+msMOSLAm/5y6gX+AoHCG3hjukm31H/UEcZy+cDv/K/IxAF6tC0Jn447kNi WvBd1mymEdZl3hnTaEhb2l4atMqypmRR8yiHCyZjCLbPrPo9Jw0LXn52JEQrA+zguasi GdYHOF1G4+1YIPhdjZ7V7WVFJSv8VHyU6LANOlTiaEv6As5tRWt4yGx2mvtMBQFzBo4p dh97hXGkD5nonIy5JzxV6EdCFziww/Iac2BYEV2t0zD69A+zO0gqo3cSsJU4HAlCTBtu Q5RYXU6N5n1lm0koGTMVD4EXUcs4QEWKhgH1pJ8hw6JHNFAAJqaalklgQC4pD4dSWRLC xypg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690453498; x=1691058298; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=p3orrnsVpmPvdMzKCfa6SEMJluYKUnGd5kHcMJ1WXrM=; b=ASH1m0n86Mpcm2v5oZsqoWiRgsLvKPFnULr7p5Hs5E+Hn7sJSfOwRQKYrIhi+wOMPo DNCvc904H9ufe+bbp0OUsdcPEzgVVMLA3PCuOoi77bnfRgWTLAAmPetiucfQjqUT22UM eunJpG486DQiuOtBudf4oonef4nmyWOq3kJtbfuZCRNcMiU/Zl+aEfnispja5ENleGn0 5MIV2F+HW7ycuwV0KKRh0dR+URl5zZclVUatYrs/ydqt9B74BXlDpFNil9WMTu1FP26q JKOAKXZ5IUWDY7bq537HpD7SwVDFk0vXLr5f26kc/fuY2wFdXPsklisDxZ0LsG7na67w e+yA== X-Gm-Message-State: ABy/qLaBxM5EqaC1J691oZCTCmFDVnwgXd+OKH7kFcEo92hoqbrgBHbl vcS0nXxv7Z+ygQUk8RL9UC+CH9MnSZ+qtcfJAVx+DVi21423dASi4UdkfXtLQSu35bzmk6lm2+1 QHMRrSMDOxiyuQwrWZWvodYzBBxfl4ss+4AhMumqjmybPH4pZh+XTrcrMcLIdDdGgZAXFCzmo/Q 23mbVS X-Google-Smtp-Source: APBJJlF5PC70kkRRGOeQzn5k2u7WI5QwJ/1xIiC62ubRFNQuRYWlJ6zWKXRkGOLaLKOb+aFzSgKBXA== X-Received: by 2002:a05:6870:a550:b0:1bb:c236:dff with SMTP id p16-20020a056870a55000b001bbc2360dffmr2697769oal.50.1690453497854; Thu, 27 Jul 2023 03:24:57 -0700 (PDT) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: rkanwal@rivosinc.com, anup@brainfault.org, dbarboza@ventanamicro.com, ajones@ventanamicro.com, atishp@atishpatra.org, vincent.chen@sifive.com, greentime.hu@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Paolo Bonzini , kvm@vger.kernel.org Subject: [PATCH v7 3/5] target/riscv: Create an KVM AIA irqchip Date: Thu, 27 Jul 2023 10:24:35 +0000 Message-Id: <20230727102439.22554-4-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230727102439.22554-1-yongxuan.wang@sifive.com> References: <20230727102439.22554-1-yongxuan.wang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=yongxuan.wang@sifive.com; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1690456980098100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We create a vAIA chip by using the KVM_DEV_TYPE_RISCV_AIA and then set up the chip with the KVM_DEV_RISCV_AIA_GRP_* APIs. We also extend KVM accelerator to specify the KVM AIA mode. The "riscv-aia" parameter is passed along with --accel in QEMU command-line. 1) "riscv-aia=3Demul": IMSIC is emulated by hypervisor 2) "riscv-aia=3Dhwaccel": use hardware guest IMSIC 3) "riscv-aia=3Dauto": use the hardware guest IMSICs whenever available otherwise we fallback to software emulation. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm.c | 186 +++++++++++++++++++++++++++++++++++++++ target/riscv/kvm_riscv.h | 4 + 2 files changed, 190 insertions(+) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 005e054604..0c17e2027a 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -36,6 +36,7 @@ #include "exec/address-spaces.h" #include "hw/boards.h" #include "hw/irq.h" +#include "hw/intc/riscv_imsic.h" #include "qemu/log.h" #include "hw/loader.h" #include "kvm_riscv.h" @@ -43,6 +44,7 @@ #include "chardev/char-fe.h" #include "migration/migration.h" #include "sysemu/runstate.h" +#include "hw/riscv/numa.h" =20 static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, uint64_t idx) @@ -1023,6 +1025,190 @@ bool kvm_arch_cpu_check_are_resettable(void) return true; } =20 +static int aia_mode; + +static const char *kvm_aia_mode_str(uint64_t mode) +{ + switch (mode) { + case KVM_DEV_RISCV_AIA_MODE_EMUL: + return "emul"; + case KVM_DEV_RISCV_AIA_MODE_HWACCEL: + return "hwaccel"; + case KVM_DEV_RISCV_AIA_MODE_AUTO: + default: + return "auto"; + }; +} + +static char *riscv_get_kvm_aia(Object *obj, Error **errp) +{ + return g_strdup(kvm_aia_mode_str(aia_mode)); +} + +static void riscv_set_kvm_aia(Object *obj, const char *val, Error **errp) +{ + if (!strcmp(val, "emul")) { + aia_mode =3D KVM_DEV_RISCV_AIA_MODE_EMUL; + } else if (!strcmp(val, "hwaccel")) { + aia_mode =3D KVM_DEV_RISCV_AIA_MODE_HWACCEL; + } else if (!strcmp(val, "auto")) { + aia_mode =3D KVM_DEV_RISCV_AIA_MODE_AUTO; + } else { + error_setg(errp, "Invalid KVM AIA mode"); + error_append_hint(errp, "Valid values are emul, hwaccel, and auto.= \n"); + } +} + void kvm_arch_accel_class_init(ObjectClass *oc) { + object_class_property_add_str(oc, "riscv-aia", riscv_get_kvm_aia, + riscv_set_kvm_aia); + object_class_property_set_description(oc, "riscv-aia", + "Set KVM AIA mode. Valid values = are " + "emul, hwaccel, and auto. Defaul= t " + "is auto."); + object_property_set_default_str(object_class_property_find(oc, "riscv-= aia"), + "auto"); +} + +void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, + uint64_t aia_irq_num, uint64_t aia_msi_num, + uint64_t aplic_base, uint64_t imsic_base, + uint64_t guest_num) +{ + int ret, i; + int aia_fd =3D -1; + uint64_t default_aia_mode; + uint64_t socket_count =3D riscv_socket_count(machine); + uint64_t max_hart_per_socket =3D 0; + uint64_t socket, base_hart, hart_count, socket_imsic_base, imsic_addr; + uint64_t socket_bits, hart_bits, guest_bits; + + aia_fd =3D kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); + + if (aia_fd < 0) { + error_report("Unable to create in-kernel irqchip"); + exit(1); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_MODE, + &default_aia_mode, false, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to get current KVM AIA mode"); + exit(1); + } + qemu_log("KVM AIA: default mode is %s\n", + kvm_aia_mode_str(default_aia_mode)); + + if (default_aia_mode !=3D aia_mode) { + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_MODE, + &aia_mode, true, NULL); + if (ret < 0) + warn_report("KVM AIA: failed to set KVM AIA mode"); + else + qemu_log("KVM AIA: set current mode to %s\n", + kvm_aia_mode_str(aia_mode)); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_SRCS, + &aia_irq_num, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set number of input irq lines"); + exit(1); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_IDS, + &aia_msi_num, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set number of msi"); + exit(1); + } + + socket_bits =3D find_last_bit(&socket_count, BITS_PER_LONG) + 1; + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS, + &socket_bits, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set group_bits"); + exit(1); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT, + &group_shift, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set group_shift"); + exit(1); + } + + guest_bits =3D guest_num =3D=3D 0 ? 0 : + find_last_bit(&guest_num, BITS_PER_LONG) + 1; + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS, + &guest_bits, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set guest_bits"); + exit(1); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, + KVM_DEV_RISCV_AIA_ADDR_APLIC, + &aplic_base, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set the base address of APLIC"); + exit(1); + } + + for (socket =3D 0; socket < socket_count; socket++) { + socket_imsic_base =3D imsic_base + socket * (1U << group_shift); + hart_count =3D riscv_socket_hart_count(machine, socket); + base_hart =3D riscv_socket_first_hartid(machine, socket); + + if (max_hart_per_socket < hart_count) { + max_hart_per_socket =3D hart_count; + } + + for (i =3D 0; i < hart_count; i++) { + imsic_addr =3D socket_imsic_base + i * IMSIC_HART_SIZE(guest_b= its); + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, + KVM_DEV_RISCV_AIA_ADDR_IMSIC(i + base_= hart), + &imsic_addr, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set the IMSIC address for= hart %d", i); + exit(1); + } + } + } + + hart_bits =3D find_last_bit(&max_hart_per_socket, BITS_PER_LONG) + 1; + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, + &hart_bits, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set hart_bits"); + exit(1); + } + + if (kvm_has_gsi_routing()) { + for (uint64_t idx =3D 0; idx < aia_irq_num + 1; ++idx) { + /* KVM AIA only has one APLIC instance */ + kvm_irqchip_add_irq_route(kvm_state, idx, 0, idx); + } + kvm_gsi_routing_allowed =3D true; + kvm_irqchip_commit_routes(kvm_state); + } + + ret =3D kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, + KVM_DEV_RISCV_AIA_CTRL_INIT, + NULL, true, NULL); + if (ret < 0) { + error_report("KVM AIA: initialized fail"); + exit(1); + } + + kvm_msi_via_irqfd_allowed =3D kvm_irqfds_enabled(); } diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index e3ba935808..7d4b7c60e2 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -22,5 +22,9 @@ void kvm_riscv_init_user_properties(Object *cpu_obj); void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); +void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, + uint64_t aia_irq_num, uint64_t aia_msi_num, + uint64_t aplic_base, uint64_t imsic_base, + uint64_t guest_num); =20 #endif --=20 2.17.1 From nobody Wed May 15 21:08:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1690457438; cv=none; d=zohomail.com; s=zohoarc; b=NcMcqvdBUTK8oUZ/75Pt0Ppzn3Ybga6E0vY3f1Q+MSFGBM69lSiOGgsmLEgbWjSbXeHyPsoUrgulu5LXJRSRALZYIz3Cn8Hsj4xW0TpFgN4geEDbye+0qxLfKrYJbKHWWBfVTKmF/fuetGiDW8htIJmPoVebvlPwRU8ncHZdls0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690457438; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=OULN+wwisoBSnT3VMk9Y7HLLhh5KeELP9Ck02I8dOSM=; b=dAQ3f6jey1oyMm0Pqcns/WimQFZh+muKdxVs08iKoUoYHUcHBpw9Uy4SeJ7LNFOU+OfQ6mwaTp8dxwHXS1Ku0OPEn0SnUEtEKMwJEXh66mu+/5e6g6t3f5GSgiEtgTS1E7gGRDZi6E3OD9rZinYFG5qH5NO3lsZDukh1lruSSi0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690457438046608.5121991878301; Thu, 27 Jul 2023 04:30:38 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qOyC9-0003iU-1A; Thu, 27 Jul 2023 06:26:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qOyBP-0003Wu-79 for qemu-devel@nongnu.org; Thu, 27 Jul 2023 06:25:23 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qOyBD-00049T-BZ for qemu-devel@nongnu.org; Thu, 27 Jul 2023 06:25:15 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1bbc06f830aso4981225ad.0 for ; Thu, 27 Jul 2023 03:25:06 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id u8-20020a17090341c800b001b882880550sm1230139ple.282.2023.07.27.03.25.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 03:25:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1690453505; x=1691058305; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=OULN+wwisoBSnT3VMk9Y7HLLhh5KeELP9Ck02I8dOSM=; b=SkFM1Jhyqd5M80e+Hjce9UMwsCrdxraYXDT6NJnpvnnz1pf5JFUVdSWdvzN8BvQYwB k91nGrBhz2QzgVqfKxewEDSlwB91NrRLdUMFmuSQPRKkQLKbGHLM2pU0uZjC5TVvrOaM 9JuCg28UuEtQCvKkE/HmuIelNoN2qAdhfSQRKUxSv8KJlJtx7XGFyDaZxZHZSBpry0DE b26eCWl7u26IfOwzxKGOwYGGbS27TvsLeWZEP/GI3vWyp2/L5z4vCluGZxc+VhKhCst9 UflMBkGy8/6F0mF1d7suHEPza816s922eVSi4tUNrsJbJCzw6VvLtJVitnV6dh5kwQ6g aQbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690453505; x=1691058305; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=OULN+wwisoBSnT3VMk9Y7HLLhh5KeELP9Ck02I8dOSM=; b=FPYnlmrqhlaxxaDrIn0cn4YKpFlsdjLhrQguzwj7ut8NcCGsGKVnCT+V10sd7Nfd9Y VtzRPa1PgL8tr3CFOoyBJ18GXa6uDQaFpZTP2QJaebntntp7SQDMWw6ZqwJNLOfQ8aqz N26C96gDr4epZnhBf50YWp6rSQNxeebP8NWrNaY61lyEBC+mmZSql+WcIv7jvVeBdJ+T SkqSgcuTmylMwkEzQScgqp1lGtM9Vq64BC9hYfH69xn92sE1PTNrvlnETQ2aP24AyzJV sUzdsHypJmM53cZoc6bziUWpw+1DfTcNVMuxIht9/pU8HL4U67h3EF3vijb3Sy7gvR73 vs1Q== X-Gm-Message-State: ABy/qLYrfBS4gCxoboWOg2qyS1D1FkYrB6re80+YW8aBUAG0+c3Ei6x9 vxWHvB9HlowOvJcR9EdHDylRMphklDXkmtw3Pd5bs9do7Z65R8AHNHNBQA7UQBFuXdlat2GLRSx I5QOcDt4GI3GaI8fQ8N8UJJvnkRC1TFtlRUm4RkcROPaHBfHXrOHpZDPGaj6GpQF4bM0lcEz+Dr uD6O5I X-Google-Smtp-Source: APBJJlG2ZP7qwtNxQoeQJnvSWf3xpKzie1j1g+qVGFlELlVRwE77NiAW2P/zjn+f7Rk/e4CDl0wRcw== X-Received: by 2002:a17:902:64c8:b0:1b6:6b03:10e7 with SMTP id y8-20020a17090264c800b001b66b0310e7mr2648932pli.5.1690453505162; Thu, 27 Jul 2023 03:25:05 -0700 (PDT) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: rkanwal@rivosinc.com, anup@brainfault.org, dbarboza@ventanamicro.com, ajones@ventanamicro.com, atishp@atishpatra.org, vincent.chen@sifive.com, greentime.hu@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Alistair Francis , Ivan Klokov , Palmer Dabbelt Subject: [PATCH v7 4/5] target/riscv: update APLIC and IMSIC to support KVM AIA Date: Thu, 27 Jul 2023 10:24:36 +0000 Message-Id: <20230727102439.22554-5-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230727102439.22554-1-yongxuan.wang@sifive.com> References: <20230727102439.22554-1-yongxuan.wang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=yongxuan.wang@sifive.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1690457438577100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" KVM AIA can't emulate APLIC only. When "aia=3Daplic" parameter is passed, APLIC devices is emulated by QEMU. For "aia=3Daplic-imsic", remove the mmio operations of APLIC when using KVM AIA and send wired interrupt signal via KVM_IRQ_LINE API. After KVM AIA enabled, MSI messages are delivered by KVM_SIGNAL_MSI API when the IMSICs receive mmio write requests. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- hw/intc/riscv_aplic.c | 56 ++++++++++++++++++++++++++++++------------- hw/intc/riscv_imsic.c | 25 +++++++++++++++---- 2 files changed, 61 insertions(+), 20 deletions(-) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index 4bdc6a5d1a..592c3ce768 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -31,6 +31,7 @@ #include "hw/irq.h" #include "target/riscv/cpu.h" #include "sysemu/sysemu.h" +#include "sysemu/kvm.h" #include "migration/vmstate.h" =20 #define APLIC_MAX_IDC (1UL << 14) @@ -148,6 +149,15 @@ =20 #define APLIC_IDC_CLAIMI 0x1c =20 +/* + * KVM AIA only supports APLIC MSI, fallback to QEMU emulation if we want = to use + * APLIC Wired. + */ +static bool is_kvm_aia(bool msimode) +{ + return kvm_irqchip_in_kernel() && msimode; +} + static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic, uint32_t word) { @@ -471,6 +481,11 @@ static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState= *aplic, uint32_t idc) return topi; } =20 +static void riscv_kvm_aplic_request(void *opaque, int irq, int level) +{ + kvm_set_irq(kvm_state, irq, !!level); +} + static void riscv_aplic_request(void *opaque, int irq, int level) { bool update =3D false; @@ -801,29 +816,35 @@ static void riscv_aplic_realize(DeviceState *dev, Err= or **errp) uint32_t i; RISCVAPLICState *aplic =3D RISCV_APLIC(dev); =20 - aplic->bitfield_words =3D (aplic->num_irqs + 31) >> 5; - aplic->sourcecfg =3D g_new0(uint32_t, aplic->num_irqs); - aplic->state =3D g_new0(uint32_t, aplic->num_irqs); - aplic->target =3D g_new0(uint32_t, aplic->num_irqs); - if (!aplic->msimode) { - for (i =3D 0; i < aplic->num_irqs; i++) { - aplic->target[i] =3D 1; + if (!is_kvm_aia(aplic->msimode)) { + aplic->bitfield_words =3D (aplic->num_irqs + 31) >> 5; + aplic->sourcecfg =3D g_new0(uint32_t, aplic->num_irqs); + aplic->state =3D g_new0(uint32_t, aplic->num_irqs); + aplic->target =3D g_new0(uint32_t, aplic->num_irqs); + if (!aplic->msimode) { + for (i =3D 0; i < aplic->num_irqs; i++) { + aplic->target[i] =3D 1; + } } - } - aplic->idelivery =3D g_new0(uint32_t, aplic->num_harts); - aplic->iforce =3D g_new0(uint32_t, aplic->num_harts); - aplic->ithreshold =3D g_new0(uint32_t, aplic->num_harts); + aplic->idelivery =3D g_new0(uint32_t, aplic->num_harts); + aplic->iforce =3D g_new0(uint32_t, aplic->num_harts); + aplic->ithreshold =3D g_new0(uint32_t, aplic->num_harts); =20 - memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, apl= ic, - TYPE_RISCV_APLIC, aplic->aperture_size); - sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio); + memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, + aplic, TYPE_RISCV_APLIC, aplic->aperture_siz= e); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio); + } =20 /* * Only root APLICs have hardware IRQ lines. All non-root APLICs * have IRQ lines delegated by their parent APLIC. */ if (!aplic->parent) { - qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs); + if (is_kvm_aia(aplic->msimode)) { + qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irq= s); + } else { + qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs); + } } =20 /* Create output IRQ lines for non-MSI mode */ @@ -958,7 +979,10 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr si= ze, qdev_prop_set_bit(dev, "mmode", mmode); =20 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + + if (!is_kvm_aia(msimode)) { + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + } =20 if (parent) { riscv_aplic_add_child(parent, dev); diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index fea3385b51..760dbddcf7 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -32,6 +32,7 @@ #include "target/riscv/cpu.h" #include "target/riscv/cpu_bits.h" #include "sysemu/sysemu.h" +#include "sysemu/kvm.h" #include "migration/vmstate.h" =20 #define IMSIC_MMIO_PAGE_LE 0x00 @@ -283,6 +284,20 @@ static void riscv_imsic_write(void *opaque, hwaddr add= r, uint64_t value, goto err; } =20 +#if defined(CONFIG_KVM) + if (kvm_irqchip_in_kernel()) { + struct kvm_msi msi; + + msi.address_lo =3D extract64(imsic->mmio.addr + addr, 0, 32); + msi.address_hi =3D extract64(imsic->mmio.addr + addr, 32, 32); + msi.data =3D le32_to_cpu(value); + + kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi); + + return; + } +#endif + /* Writes only supported for MSI little-endian registers */ page =3D addr >> IMSIC_MMIO_PAGE_SHIFT; if ((addr & (IMSIC_MMIO_PAGE_SZ - 1)) =3D=3D IMSIC_MMIO_PAGE_LE) { @@ -320,10 +335,12 @@ static void riscv_imsic_realize(DeviceState *dev, Err= or **errp) CPUState *cpu =3D cpu_by_arch_id(imsic->hartid); CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; =20 - imsic->num_eistate =3D imsic->num_pages * imsic->num_irqs; - imsic->eidelivery =3D g_new0(uint32_t, imsic->num_pages); - imsic->eithreshold =3D g_new0(uint32_t, imsic->num_pages); - imsic->eistate =3D g_new0(uint32_t, imsic->num_eistate); + if (!kvm_irqchip_in_kernel()) { + imsic->num_eistate =3D imsic->num_pages * imsic->num_irqs; + imsic->eidelivery =3D g_new0(uint32_t, imsic->num_pages); + imsic->eithreshold =3D g_new0(uint32_t, imsic->num_pages); + imsic->eistate =3D g_new0(uint32_t, imsic->num_eistate); + } =20 memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops, imsic, TYPE_RISCV_IMSIC, --=20 2.17.1 From nobody Wed May 15 21:08:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1690454395; cv=none; d=zohomail.com; s=zohoarc; b=njGbil8JUXnr5BATXyE1aRcEw3CTAcn40hvr4j3AW4H8WBLORSSgHxx3vWJwVWaIrlRbjZbdOu47IDcPujtMf/3RiEOR7HiPXkHEQ2PkOTULxgb7UX9DGwlTY9InCEZKhgZhqByZ55kg7ID9HZc3I1iXTqg+qPtPWIvLsrEWjRs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690454395; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=H7Zt4zM7mdn4Ype868SA62zfOIkFcLwtmRVr8Dp/bb8=; b=TEHGx/vw0Cp/XCr/pTO5REOytnLp2Meep9La7zKvTd+GRxAK4q96j+hxr0XT/IkL5JvVnXPnHxFVjHOmEWsJwBFkHw+Y6xebfd7PZ2dacY+9Ig7e1X9OwZL6qSbrrtC+UBsoUPV+34fZY9OG3oJaHRvbShXpudss4Cfvo81FB5k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1690454395156497.3934634241584; Thu, 27 Jul 2023 03:39:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qOyCB-0003j4-3m; Thu, 27 Jul 2023 06:26:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qOyBQ-0003XJ-8j for qemu-devel@nongnu.org; Thu, 27 Jul 2023 06:25:36 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qOyBF-0004Bj-7E for qemu-devel@nongnu.org; Thu, 27 Jul 2023 06:25:19 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1bbc64f9a91so6252435ad.0 for ; Thu, 27 Jul 2023 03:25:11 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id u8-20020a17090341c800b001b882880550sm1230139ple.282.2023.07.27.03.25.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 03:25:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1690453510; x=1691058310; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=H7Zt4zM7mdn4Ype868SA62zfOIkFcLwtmRVr8Dp/bb8=; b=d9tzBPwHMDWBaO1swiv2Dw3LW7KVWDxxKgrMljO2n2C2ch9bvwjIxo7+wacgc/cECj Wa3qPcm1hmYSsevakmq3CWtP7xz2R6J8RdOPwnG3j3CO2Ax6qcPQ3Oqah8vvEfO3sSuB 0++tlOepW/H4ToxI5Kpwm15vjWw4ZFT7wcwLUBNF2mt0avt0VBXZfF9O7+e7rvdLLB5A dk+zUCVyOCc+8BvTu9c3AlePyo/9tNCTJagQcVGfhr/YLCy1NddId0k+lfENaB7rRKsj GXinsOu/PC89pdPt01jegja28o9fACrkazgahXzIXXED22YOdFn2ds/le0bImTLEXlZ8 X5ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690453510; x=1691058310; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=H7Zt4zM7mdn4Ype868SA62zfOIkFcLwtmRVr8Dp/bb8=; b=EFfSK0h6SVwl8YjTTBSNB837hM9jk3mOPwH4RWYu46jLTU/pR+BMbbsE3LVVyorbiz J1fx7UkqRuPopXyIoEew9cBMrDj9oUQqS+Gk0Vhl73RnwnDBiNlLs+avV7cZoK+LiaMc KzRNCx45xFD4Fk7Os3yWmbUZNIu0X/Lj8M/URgPUdMgN8yhdECOTlkn1F3bED6uSnRs3 NNWqx+dGTjPlNe9HMt3qtnsmcdtofRZSDq8Er6lm5DBv+NwTpNiaC6phC3Ea9pOsltb2 g62MX4xVM2XSAEeElByD4SiOW1QYNWVZGal4ISlNSj2QzN9nJstASzDSxPahjQNtQa/o CUfQ== X-Gm-Message-State: ABy/qLYukEW8OjGxkHmp6wT1TntWv4dc/2zx+bldEeBxfwJJ4u4cx55j bFloywKTVKqre/w1j8n8MIzokk4GI+rLWh3oHR1z89D/toKzFU3/C7ndM9rIdYVU45y9QQyD6jR wyENv5ip2ml+C5P1KS5+SMoeV2+oXdrlnRc32zEKlRpYfLzxkr2td1Fd56l0/y3zA8oca9qfPcK 2WocK5 X-Google-Smtp-Source: APBJJlGAOCc+wbYfEp9OyBp1n97lYyv0gEYX3EEXprsSRTX1yK8rvEb1Kyy5OvsMLmx74uGh/YPsIA== X-Received: by 2002:a17:902:db09:b0:1b8:8dbd:e1a0 with SMTP id m9-20020a170902db0900b001b88dbde1a0mr5968320plx.13.1690453509815; Thu, 27 Jul 2023 03:25:09 -0700 (PDT) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: rkanwal@rivosinc.com, anup@brainfault.org, dbarboza@ventanamicro.com, ajones@ventanamicro.com, atishp@atishpatra.org, vincent.chen@sifive.com, greentime.hu@sifive.com, frank.chang@sifive.com, jim.shu@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei Subject: [PATCH v7 5/5] target/riscv: select KVM AIA in riscv virt machine Date: Thu, 27 Jul 2023 10:24:37 +0000 Message-Id: <20230727102439.22554-6-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230727102439.22554-1-yongxuan.wang@sifive.com> References: <20230727102439.22554-1-yongxuan.wang@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=yongxuan.wang@sifive.com; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1690454397140100002 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Select KVM AIA when the host kernel has in-kernel AIA chip support. Since KVM AIA only has one APLIC instance, we map the QEMU APLIC devices to KVM APLIC. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- hw/riscv/virt.c | 94 +++++++++++++++++++++++++++++++++---------------- 1 file changed, 63 insertions(+), 31 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f595380be1..4af73ac1bb 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -35,6 +35,7 @@ #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" +#include "kvm_riscv.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/riscv_aplic.h" #include "hw/intc/riscv_imsic.h" @@ -75,6 +76,12 @@ #error "Can't accomodate all IMSIC groups in address space" #endif =20 +/* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU= . */ +static bool virt_use_kvm_aia(RISCVVirtState *s) +{ + return kvm_irqchip_in_kernel() && s->aia_type =3D=3D VIRT_AIA_TYPE_APL= IC_IMSIC; +} + static const MemMapEntry virt_memmap[] =3D { [VIRT_DEBUG] =3D { 0x0, 0x100 }, [VIRT_MROM] =3D { 0x1000, 0xf000 }, @@ -609,16 +616,16 @@ static void create_fdt_one_aplic(RISCVVirtState *s, i= nt socket, uint32_t *intc_phandles, uint32_t aplic_phandle, uint32_t aplic_child_phandle, - bool m_mode) + bool m_mode, int num_harts) { int cpu; char *aplic_name; uint32_t *aplic_cells; MachineState *ms =3D MACHINE(s); =20 - aplic_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 2); + aplic_cells =3D g_new0(uint32_t, num_harts * 2); =20 - for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { + for (cpu =3D 0; cpu < num_harts; cpu++) { aplic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); aplic_cells[cpu * 2 + 1] =3D cpu_to_be32(m_mode ? IRQ_M_EXT : IRQ_= S_EXT); } @@ -632,8 +639,7 @@ static void create_fdt_one_aplic(RISCVVirtState *s, int= socket, =20 if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC) { qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", - aplic_cells, - s->soc[socket].num_harts * sizeof(uint32_t) * 2); + aplic_cells, num_harts * sizeof(uint32_t) * 2); } else { qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_phand= le); } @@ -664,7 +670,8 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, uint32_t msi_s_phandle, uint32_t *phandle, uint32_t *intc_phandles, - uint32_t *aplic_phandles) + uint32_t *aplic_phandles, + int num_harts) { char *aplic_name; unsigned long aplic_addr; @@ -681,7 +688,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_M].s= ize, msi_m_phandle, intc_phandles, aplic_m_phandle, aplic_s_phandle, - true); + true, num_harts); } =20 /* S-level APLIC node */ @@ -690,7 +697,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, create_fdt_one_aplic(s, socket, aplic_addr, memmap[VIRT_APLIC_S].size, msi_s_phandle, intc_phandles, aplic_s_phandle, 0, - false); + false, num_harts); =20 aplic_name =3D g_strdup_printf("/soc/aplic@%lx", aplic_addr); =20 @@ -774,34 +781,51 @@ static void create_fdt_sockets(RISCVVirtState *s, con= st MemMapEntry *memmap, *msi_pcie_phandle =3D msi_s_phandle; } =20 - phandle_pos =3D ms->smp.cpus; - for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { - phandle_pos -=3D s->soc[socket].num_harts; - - if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { - create_fdt_socket_plic(s, memmap, socket, phandle, - &intc_phandles[phandle_pos], xplic_phandles); - } else { - create_fdt_socket_aplic(s, memmap, socket, - msi_m_phandle, msi_s_phandle, phandle, - &intc_phandles[phandle_pos], xplic_phandles); + /* KVM AIA only has one APLIC instance */ + if (virt_use_kvm_aia(s)) { + create_fdt_socket_aplic(s, memmap, 0, + msi_m_phandle, msi_s_phandle, phandle, + &intc_phandles[0], xplic_phandles, + ms->smp.cpus); + } else { + phandle_pos =3D ms->smp.cpus; + for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { + phandle_pos -=3D s->soc[socket].num_harts; + + if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { + create_fdt_socket_plic(s, memmap, socket, phandle, + &intc_phandles[phandle_pos], + xplic_phandles); + } else { + create_fdt_socket_aplic(s, memmap, socket, + msi_m_phandle, msi_s_phandle, phan= dle, + &intc_phandles[phandle_pos], + xplic_phandles, + s->soc[socket].num_harts); + } } } =20 g_free(intc_phandles); =20 - for (socket =3D 0; socket < socket_count; socket++) { - if (socket =3D=3D 0) { - *irq_mmio_phandle =3D xplic_phandles[socket]; - *irq_virtio_phandle =3D xplic_phandles[socket]; - *irq_pcie_phandle =3D xplic_phandles[socket]; - } - if (socket =3D=3D 1) { - *irq_virtio_phandle =3D xplic_phandles[socket]; - *irq_pcie_phandle =3D xplic_phandles[socket]; - } - if (socket =3D=3D 2) { - *irq_pcie_phandle =3D xplic_phandles[socket]; + if (virt_use_kvm_aia(s)) { + *irq_mmio_phandle =3D xplic_phandles[0]; + *irq_virtio_phandle =3D xplic_phandles[0]; + *irq_pcie_phandle =3D xplic_phandles[0]; + } else { + for (socket =3D 0; socket < socket_count; socket++) { + if (socket =3D=3D 0) { + *irq_mmio_phandle =3D xplic_phandles[socket]; + *irq_virtio_phandle =3D xplic_phandles[socket]; + *irq_pcie_phandle =3D xplic_phandles[socket]; + } + if (socket =3D=3D 1) { + *irq_virtio_phandle =3D xplic_phandles[socket]; + *irq_pcie_phandle =3D xplic_phandles[socket]; + } + if (socket =3D=3D 2) { + *irq_pcie_phandle =3D xplic_phandles[socket]; + } } } =20 @@ -1432,6 +1456,14 @@ static void virt_machine_init(MachineState *machine) } } =20 + if (virt_use_kvm_aia(s)) { + kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, + VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MS= IS, + memmap[VIRT_APLIC_S].base, + memmap[VIRT_IMSIC_S].base, + s->aia_guests); + } + if (riscv_is_32bit(&s->soc[0])) { #if HOST_LONG_BITS =3D=3D 64 /* limit RAM size in a 32-bit system */ --=20 2.17.1