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charset="utf-8" Add cpuid bit definition for the SUCCOR feature. This cpuid bit is required= to be exposed to guests to allow them to handle machine check exceptions on AMD hosts. Reported-by: William Roche Signed-off-by: John Allen --- v2: - Add "succor" feature word. - Add case to kvm_arch_get_supported_cpuid for the SUCCOR feature. --- target/i386/cpu.c | 18 +++++++++++++++++- target/i386/cpu.h | 4 ++++ target/i386/kvm/kvm.c | 2 ++ 3 files changed, 23 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 06009b80e8..9708785255 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -872,6 +872,22 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { }, .tcg_features =3D TCG_7_1_EAX_FEATURES, }, + [FEAT_8000_0007_EBX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + NULL, "succor", NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .cpuid =3D { .eax =3D 0x80000007, .reg =3D R_EBX, }, + .tcg_features =3D 0, + .unmigratable_flags =3D 0, + }, [FEAT_8000_0007_EDX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -5874,7 +5890,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; case 0x80000007: *eax =3D 0; - *ebx =3D 0; + *ebx =3D env->features[FEAT_8000_0007_EBX]; *ecx =3D 0; *edx =3D env->features[FEAT_8000_0007_EDX]; break; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 3edaad7688..fccb9b5a97 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -555,6 +555,7 @@ typedef enum FeatureWord { FEAT_7_1_EAX, /* CPUID[EAX=3D7,ECX=3D1].EAX */ FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */ FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */ + FEAT_8000_0007_EBX, /* CPUID[8000_0007].EBX */ FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */ FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */ FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */ @@ -856,6 +857,9 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; /* Packets which contain IP payload have LIP values */ #define CPUID_14_0_ECX_LIP (1U << 31) =20 +/* RAS Features */ +#define CPUID_8000_0007_EBX_SUCCOR (1U << 1) + /* CLZERO instruction */ #define CPUID_8000_0008_EBX_CLZERO (1U << 0) /* Always save/restore FP error pointers */ diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index f25837f63f..4b62138459 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -417,6 +417,8 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint= 32_t function, */ cpuid_1_edx =3D kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); 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charset="utf-8" For the most part, AMD hosts can use the same MCE injection code as Intel b= ut, there are instances where the qemu implementation is Intel specific. First,= MCE deliviery works differently on AMD and does not support broadcast. Second, kvm_mce_inject generates MCEs that include a number of Intel specific status bits. Modify kvm_mce_inject to properly generate MCEs on AMD platforms. Reported-by: William Roche Signed-off-by: John Allen --- target/i386/helper.c | 4 ++++ target/i386/kvm/kvm.c | 17 +++++++++++------ 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/target/i386/helper.c b/target/i386/helper.c index 533b29cb91..a6523858e0 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -76,6 +76,10 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env) int family =3D 0; int model =3D 0; =20 + if (IS_AMD_CPU(env)) { + return 0; + } + cpu_x86_version(env, &family, &model); if ((family =3D=3D 6 && model >=3D 14) || family > 6) { return 1; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 4b62138459..87a50c8aaf 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -532,16 +532,21 @@ static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr,= int code) CPUState *cs =3D CPU(cpu); CPUX86State *env =3D &cpu->env; uint64_t status =3D MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | - MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; + MCI_STATUS_MISCV | MCI_STATUS_ADDRV; uint64_t mcg_status =3D MCG_STATUS_MCIP; int flags =3D 0; =20 - if (code =3D=3D BUS_MCEERR_AR) { - status |=3D MCI_STATUS_AR | 0x134; - mcg_status |=3D MCG_STATUS_EIPV; + if (!IS_AMD_CPU(env)) { + status |=3D MCI_STATUS_S; + if (code =3D=3D BUS_MCEERR_AR) { + status |=3D MCI_STATUS_AR | 0x134; + mcg_status |=3D MCG_STATUS_EIPV; + } else { + status |=3D 0xc0; + mcg_status |=3D MCG_STATUS_RIPV; + } } else { - status |=3D 0xc0; - mcg_status |=3D MCG_STATUS_RIPV; + mcg_status |=3D MCG_STATUS_EIPV | MCG_STATUS_RIPV; } =20 flags =3D cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : = 0; --=20 2.39.3