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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=npiggin@gmail.com; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1690399082510100001 Content-Type: text/plain; charset="utf-8" The ASDR register was introduced in ISA v3.0. It has not been implemented for HPT. With HPT, ASDR is the format of the slbmte RS operand (containing VSID), which matches the ppc_slb_t field. Fixes: 3367c62f522b ("target/ppc: Support for POWER9 native hash") Signed-off-by: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/mmu-hash64.c | 27 ++++++++++++++++----------- 1 file changed, 16 insertions(+), 11 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 900f906990..a0c90df3ce 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -770,7 +770,8 @@ static bool ppc_hash64_use_vrma(CPUPPCState *env) } } =20 -static void ppc_hash64_set_isi(CPUState *cs, int mmu_idx, uint64_t error_c= ode) +static void ppc_hash64_set_isi(CPUState *cs, int mmu_idx, uint64_t slb_vsi= d, + uint64_t error_code) { CPUPPCState *env =3D &POWERPC_CPU(cs)->env; bool vpm; @@ -782,13 +783,15 @@ static void ppc_hash64_set_isi(CPUState *cs, int mmu_= idx, uint64_t error_code) } if (vpm && !mmuidx_hv(mmu_idx)) { cs->exception_index =3D POWERPC_EXCP_HISI; + env->spr[SPR_ASDR] =3D slb_vsid; } else { cs->exception_index =3D POWERPC_EXCP_ISI; } env->error_code =3D error_code; } =20 -static void ppc_hash64_set_dsi(CPUState *cs, int mmu_idx, uint64_t dar, ui= nt64_t dsisr) +static void ppc_hash64_set_dsi(CPUState *cs, int mmu_idx, uint64_t slb_vsi= d, + uint64_t dar, uint64_t dsisr) { CPUPPCState *env =3D &POWERPC_CPU(cs)->env; bool vpm; @@ -802,6 +805,7 @@ static void ppc_hash64_set_dsi(CPUState *cs, int mmu_id= x, uint64_t dar, uint64_t cs->exception_index =3D POWERPC_EXCP_HDSI; env->spr[SPR_HDAR] =3D dar; env->spr[SPR_HDSISR] =3D dsisr; + env->spr[SPR_ASDR] =3D slb_vsid; } else { cs->exception_index =3D POWERPC_EXCP_DSI; env->spr[SPR_DAR] =3D dar; @@ -963,13 +967,13 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, M= MUAccessType access_type, } switch (access_type) { case MMU_INST_FETCH: - ppc_hash64_set_isi(cs, mmu_idx, SRR1_PROTFAULT); + ppc_hash64_set_isi(cs, mmu_idx, 0, SRR1_PROTFAULT); break; case MMU_DATA_LOAD: - ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_PROTFAULT= ); + ppc_hash64_set_dsi(cs, mmu_idx, 0, eaddr, DSISR_PROTFA= ULT); break; case MMU_DATA_STORE: - ppc_hash64_set_dsi(cs, mmu_idx, eaddr, + ppc_hash64_set_dsi(cs, mmu_idx, 0, eaddr, DSISR_PROTFAULT | DSISR_ISSTORE); break; default: @@ -1022,7 +1026,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, M= MUAccessType access_type, /* 3. Check for segment level no-execute violation */ if (access_type =3D=3D MMU_INST_FETCH && (slb->vsid & SLB_VSID_N)) { if (guest_visible) { - ppc_hash64_set_isi(cs, mmu_idx, SRR1_NOEXEC_GUARD); + ppc_hash64_set_isi(cs, mmu_idx, slb->vsid, SRR1_NOEXEC_GUARD); } return false; } @@ -1035,13 +1039,14 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr,= MMUAccessType access_type, } switch (access_type) { case MMU_INST_FETCH: - ppc_hash64_set_isi(cs, mmu_idx, SRR1_NOPTE); + ppc_hash64_set_isi(cs, mmu_idx, slb->vsid, SRR1_NOPTE); break; case MMU_DATA_LOAD: - ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_NOPTE); + ppc_hash64_set_dsi(cs, mmu_idx, slb->vsid, eaddr, DSISR_NOPTE); break; case MMU_DATA_STORE: - ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_NOPTE | DSISR_ISS= TORE); + ppc_hash64_set_dsi(cs, mmu_idx, slb->vsid, eaddr, + DSISR_NOPTE | DSISR_ISSTORE); break; default: g_assert_not_reached(); @@ -1075,7 +1080,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, M= MUAccessType access_type, if (PAGE_EXEC & ~amr_prot) { srr1 |=3D SRR1_IAMR; /* Access violates virt pg class key = prot */ } - ppc_hash64_set_isi(cs, mmu_idx, srr1); + ppc_hash64_set_isi(cs, mmu_idx, slb->vsid, srr1); } else { int dsisr =3D 0; if (need_prot & ~pp_prot) { @@ -1087,7 +1092,7 @@ bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, M= MUAccessType access_type, if (need_prot & ~amr_prot) { dsisr |=3D DSISR_AMR; } - ppc_hash64_set_dsi(cs, mmu_idx, eaddr, dsisr); + ppc_hash64_set_dsi(cs, mmu_idx, slb->vsid, eaddr, dsisr); } return false; } --=20 2.40.1 From nobody Sun May 19 15:58:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1690399028; cv=none; d=zohomail.com; s=zohoarc; b=PHu1hAIh1WlRQvWcIpc/txuZ+6SdKmF2Mvw9yo9qUkRl+KLbcvBk+uvTsxOS6uuW8pq90H3cuOFofhH2NFT1AVNtxfOvnpo9linqRTotFE7IGc5tdWtHOu5jOEvyCVfX8nTuuHlFDFG+vDnPJH1W7MXZZPEJR11XhYz2hYRGyZ0= ARC-Message-Signature: i=1; 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Wed, 26 Jul 2023 11:22:49 -0700 (PDT) From: Nicholas Piggin To: Daniel Henrique Barboza Cc: Nicholas Piggin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson , Greg Kurz , Harsh Prateek Bora , qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/6] target/ppc: Fix VRMA page size for ISA v3.0 Date: Thu, 27 Jul 2023 04:22:26 +1000 Message-Id: <20230726182230.433945-3-npiggin@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230726182230.433945-1-npiggin@gmail.com> References: <20230726182230.433945-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=npiggin@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1690399029858100003 Content-Type: text/plain; charset="utf-8" Until v2.07s, the VRMA page size (L||LP) was encoded in LPCR[VRMASD]. In v3.0 that moved to the partition table PS field. The powernv machine can now run KVM HPT guests on POWER9/10 CPUs with this fix and the patch to add ASDR. Fixes: 3367c62f522b ("target/ppc: Support for POWER9 native hash") Signed-off-by: Nicholas Piggin --- target/ppc/mmu-hash64.c | 41 +++++++++++++++++++++++++++++++++++------ 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index a0c90df3ce..7f8bbbbdb0 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -874,12 +874,41 @@ static target_ulong rmls_limit(PowerPCCPU *cpu) return rma_sizes[rmls]; } =20 -static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb) +/* Return the LLP in SLB_VSID format */ +static uint64_t get_vrma_llp(PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; - target_ulong lpcr =3D env->spr[SPR_LPCR]; - uint32_t vrmasd =3D (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; - target_ulong vsid =3D SLB_VSID_VRMA | ((vrmasd << 4) & SLB_VSID_LLP_MA= SK); + uint64_t llp; + + if (env->mmu_model =3D=3D POWERPC_MMU_3_00) { + ppc_v3_pate_t pate; + uint64_t ps; + + /* + * ISA v3.0 removes the LPCR[VRMASD] field and puts the VRMA base + * page size (L||LP equivalent) in the PS field in the HPT partiti= on + * table entry. + */ + if (!ppc64_v3_get_pate(cpu, cpu->env.spr[SPR_LPIDR], &pate)) { + error_report("Bad VRMA with no partition table entry"); + return 0; + } + ps =3D pate.dw0 >> (63 - 58); + llp =3D ((ps & 0x4) << (63 - 55 - 2)) | ((ps & 0x3) << (63 - 59)); + + } else { + uint64_t lpcr =3D env->spr[SPR_LPCR]; + target_ulong vrmasd =3D (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; + + llp =3D (vrmasd << 4) & SLB_VSID_LLP_MASK; + } + + return llp; +} + +static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb) +{ + target_ulong vsid =3D SLB_VSID_VRMA | get_vrma_llp(cpu); int i; =20 for (i =3D 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { @@ -897,8 +926,8 @@ static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *= slb) } } =20 - error_report("Bad page size encoding in LPCR[VRMASD]; LPCR=3D0x" - TARGET_FMT_lx, lpcr); + error_report("Bad VRMA page size encoding 0x" TARGET_FMT_lx, + get_vrma_llp(cpu)); =20 return -1; } --=20 2.40.1 From nobody Sun May 19 15:58:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1690399530920100001 Content-Type: text/plain; charset="utf-8" HDEC is defined to not wake from PM state. There is a check in the HDEC timer to avoid setting the interrupt if we are in a PM state, but no check on PM entry to lower HDEC if it already fired. This can cause a HDECR wake up and QEMU abort with unsupported exception in Power Save mode. Fixes: 4b236b621bf ("ppc: Initial HDEC support") Signed-off-by: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/excp_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 003805b202..9aa8e46566 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -2685,6 +2685,12 @@ void helper_pminsn(CPUPPCState *env, uint32_t insn) env->resume_as_sreset =3D (insn !=3D PPC_PM_STOP) || (env->spr[SPR_PSSCR] & PSSCR_EC); =20 + /* HDECR is not to wake from PM state, it may have already fired */ + if (env->resume_as_sreset) { + PowerPCCPU *cpu =3D env_archcpu(env); + ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0); + } + ppc_maybe_interrupt(env); } #endif /* defined(TARGET_PPC64) */ --=20 2.40.1 From nobody Sun May 19 15:58:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=npiggin@gmail.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1690399007689100003 Content-Type: text/plain; charset="utf-8" The decrementer register contains a relative time in timebase units. When writing to DECR this is converted and stored as an absolute value in nanosecond units, reading DECR converts back to relative timebase. The tb<->ns conversion of the relative part can cause rounding such that a value writen to the decrementer can read back a different, with time held constant. This is a particular problem for a deterministic icount and record-replay trace. Fix this by storing the absolute value in timebase units rather than nanoseconds. The math before: store: decr_next =3D now_ns + decr * ns_per_sec / tb_per_sec load: decr =3D (decr_next - now_ns) * tb_per_sec / ns_per_sec load(store): decr =3D decr * ns_per_sec / tb_per_sec * tb_per_sec / ns_per_sec After: store: decr_next =3D now_ns * tb_per_sec / ns_per_sec + decr load: decr =3D decr_next - now_ns * tb_per_sec / ns_per_sec load(store): decr =3D decr Fixes: 9fddaa0c0cab ("PowerPC merge: real time TB and decrementer - faster = and simpler exception handling (Jocelyn Mayer)") Signed-off-by: Nicholas Piggin --- hw/ppc/ppc.c | 41 ++++++++++++++++++++++++----------------- 1 file changed, 24 insertions(+), 17 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 0e0a3d93c3..fa60f76dd4 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -686,16 +686,17 @@ bool ppc_decr_clear_on_delivery(CPUPPCState *env) static inline int64_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next) { ppc_tb_t *tb_env =3D env->tb_env; - int64_t decr, diff; + uint64_t now, n; + int64_t decr; =20 - diff =3D next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - if (diff >=3D 0) { - decr =3D muldiv64(diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND); - } else if (tb_env->flags & PPC_TIMER_BOOKE) { + now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + n =3D muldiv64(now, tb_env->decr_freq, NANOSECONDS_PER_SECOND); + if (next > n && tb_env->flags & PPC_TIMER_BOOKE) { decr =3D 0; - } else { - decr =3D -muldiv64(-diff, tb_env->decr_freq, NANOSECONDS_PER_SECON= D); + } else { + decr =3D next - n; } + trace_ppc_decr_load(decr); =20 return decr; @@ -834,11 +835,11 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uin= t64_t *nextp, =20 /* Calculate the next timer event */ now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - next =3D now + muldiv64(value, NANOSECONDS_PER_SECOND, tb_env->decr_fr= eq); - *nextp =3D next; + next =3D muldiv64(now, tb_env->decr_freq, NANOSECONDS_PER_SECOND) + va= lue; + *nextp =3D next; /* nextp is in timebase units */ =20 /* Adjust timer */ - timer_mod(timer, next); + timer_mod(timer, muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->decr_f= req)); } =20 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, target_ulong decr, @@ -1153,14 +1154,20 @@ static void start_stop_pit (CPUPPCState *env, ppc_t= b_t *tb_env, int is_excp) } else { trace_ppc4xx_pit_start(ppc40x_timer->pit_reload); now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - next =3D now + muldiv64(ppc40x_timer->pit_reload, - NANOSECONDS_PER_SECOND, tb_env->decr_freq); - if (is_excp) - next +=3D tb_env->decr_next - now; - if (next =3D=3D now) - next++; + + if (is_excp) { + tb_env->decr_next +=3D ppc40x_timer->pit_reload; + } else { + tb_env->decr_next =3D muldiv64(now, tb_env->decr_freq, + NANOSECONDS_PER_SECOND) + + ppc40x_timer->pit_reload; + } + next =3D muldiv64(tb_env->decr_next, NANOSECONDS_PER_SECOND, + tb_env->decr_freq); + if (next <=3D now) { + next =3D now + 1; + } timer_mod(tb_env->decr_timer, next); - tb_env->decr_next =3D next; } } =20 --=20 2.40.1 From nobody Sun May 19 15:58:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=npiggin@gmail.com; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1690398706223100001 Content-Type: text/plain; charset="utf-8" When writing a value to the decrementer that raises an exception, the irq is raised, but the value is not stored so the store doesn't appear to have changed the register when it is read again. Always store the write value to the register. Fixes: e81a982aa53 ("PPC: Clean up DECR implementation") Signed-off-by: Nicholas Piggin --- hw/ppc/ppc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index fa60f76dd4..cd1993e9c1 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -812,6 +812,11 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint= 64_t *nextp, return; } =20 + /* Calculate the next timer event */ + now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + next =3D muldiv64(now, tb_env->decr_freq, NANOSECONDS_PER_SECOND) + va= lue; + *nextp =3D next; /* nextp is in timebase units */ + /* * Going from 1 -> 0 or 0 -> -1 is the event to generate a DEC interru= pt. * @@ -833,11 +838,6 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint= 64_t *nextp, (*lower_excp)(cpu); } =20 - /* Calculate the next timer event */ - now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - next =3D muldiv64(now, tb_env->decr_freq, NANOSECONDS_PER_SECOND) + va= lue; - *nextp =3D next; /* nextp is in timebase units */ - /* Adjust timer */ timer_mod(timer, muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->decr_f= req)); } --=20 2.40.1 From nobody Sun May 19 15:58:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1690399543; cv=none; d=zohomail.com; s=zohoarc; b=brUOiWda2uT/iZvi43WLsfyNKFkbbF4IJzLBZyday9b6f8vhs/xQ1Si4wfisDJ/cGTONaPAPBGn3etXYTSQsRiiEQ4z/tAbDxmttJ1OZ12Pr4yVSdC+wBe3+0wpOsfRSdX8NzG/klD6y9Pnq8CG7exBDgMNbtIjeuK8If54MakM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1690399543; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jnOO8sOKFvquVVGd7wwV21JSwUZNyJsumnSJEzq/sZM=; b=DWHWt4QtDQXfl6exE0l9u+RSm9x07gTXu7+NkPmBXGjuccpTvvUUo3tlTXqWfiVG9KCdOMXOPYHjqego+JN4KW7nZ++X4c8TfLnobC2xcbnI3dDLc36Wht1+p2Cdf6+KhvTdJy11GWUWkRR77NcRSpb6uauX+LhzhPBeQ9BgTzI= ARC-Authentication-Results: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=npiggin@gmail.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1690399545029100001 Content-Type: text/plain; charset="utf-8" TCG does not maintain the DEC reigster in the SPR array, so it does get migrated. TCG also needs to re-start the decrementer timer on the destination machine. Load and store the decrementer into the SPR when migrating. This works for the level-triggered (book3s) decrementer, and should be compatible with existing KVM machines that do keep the DEC value there. This fixes lost decrementer interrupt on migration that can cause hangs, as well as other problems including record-replay bugs. Signed-off-by: Nicholas Piggin --- target/ppc/machine.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 134b16c625..ebb37e07d0 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -209,6 +209,14 @@ static int cpu_pre_save(void *opaque) /* Used to retain migration compatibility for pre 6.0 for 601 machines= . */ env->hflags_compat_nmsr =3D 0; =20 + if (tcg_enabled()) { + /* + * TCG does not maintain the DECR spr (unlike KVM) so have to save + * it here. + */ + env->spr[SPR_DECR] =3D cpu_ppc_load_decr(env); + } + return 0; } =20 @@ -314,6 +322,12 @@ static int cpu_post_load(void *opaque, int version_id) post_load_update_msr(env); =20 if (tcg_enabled()) { + /* + * TCG needs to re-start the decrementer timer and/or raise the + * interrupt. This works for level-triggered decrementer. Edge + * triggered types (including HDEC) would need to carry more state. + */ + cpu_ppc_store_decr(env, env->spr[SPR_DECR]); pmu_mmcr01_updated(env); } =20 --=20 2.40.1