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Wed, 26 Jul 2023 04:17:33 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7C2626182F; Wed, 26 Jul 2023 08:17:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AF351C433C8; Wed, 26 Jul 2023 08:17:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1690359441; bh=y8XDVLlLUG9TcUvhyT8tlZ6bs1bvY7y2wzACPFZTjCA=; h=From:To:Cc:Subject:Date:From; b=FYubeef0yufLZmV4Aun+6MC00fq/P1oBr8U5DWMoDUDMUpVlcWV88Za+RaUiSyvRg M4yzzprraY3M9tSyt+FA6gXxte9WKN5SoJFfTPPTII+lL40L5SeE+CYlN96jW99Fh5 aqRFA8eNJ2miaBWdRAEB0lM2g2HaEs/memfBZQdRPPoE8nCaRMa3Y/4Cg/ZjMFPpaR h17it3xnBEa4B2IY6BtAzW9syKv6dVxDPpYU7UV3D8NYc/VSf5ljGUboVsDtf+YXp7 fD7eEdhM4mN27JiMw0xqW2tHyQS3wpFUudbLjx9eA9cZw1eBQ/QQQ5OFicJ03AjGll jDuRbGrtSs5kw== From: Ard Biesheuvel To: qemu-devel@nongnu.org Cc: Ard Biesheuvel , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [RFC PATCH] target/i386: Truncate ESP when exiting from long mode Date: Wed, 26 Jul 2023 10:17:10 +0200 Message-Id: <20230726081710.1051126-1-ardb@kernel.org> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Developer-Signature: v=1; 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charset="utf-8" While working on some EFI boot changes for Linux/x86, I noticed that TCG deviates from bare metal when it comes to how it handles the value of the stack pointer register RSP when dropping out of long mode. On bare metal, RSP is truncated to 32 bits, even if the code that runs in 32-bit protected mode never uses the stack at all (and uses a long jump rather than long return to switch back to long mode). This means 64-bit code cannot rely on RSP surviving any excursions into 32-bit protected mode (with paging disabled). Let's align TCG with this behavior, so that code that relies on RSP retaining its value does not inadvertently work while bare metal does not. Observed on Intel Ice Lake cores. Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Link: https://lore.kernel.org/all/20230711091453.2543622-11-ardb@kernel.org/ Signed-off-by: Ard Biesheuvel Acked-by: Richard Henderson --- I used this patch locally to reproduce an issue that was reported on Ice Lake but didn't trigger in my QEMU testing. Hints welcome on where the architectural behavior is specified, and in particular, whether or not other 64-bit GPRs can be relied upon to preserve their full 64-bit length values. target/i386/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/helper.c b/target/i386/helper.c index 89aa696c6d53d68c..a338da23a87746ed 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -149,6 +149,7 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_= cr0) env->efer &=3D ~MSR_EFER_LMA; env->hflags &=3D ~(HF_LMA_MASK | HF_CS64_MASK); env->eip &=3D 0xffffffff; + env->regs[R_ESP] &=3D 0xffffffff; } #endif env->cr[0] =3D new_cr0 | CR0_ET_MASK; --=20 2.39.2