[v1] riscv-to-apply queue

[PULL 0/5] riscv-to-apply queue

Alistair Francis posted 5 patches 9 months, 2 weeks ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20230719044538.2013401-1-alistair.francis@wdc.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Weiwei Li <liweiwei@iscas.ac.cn>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

There is a newer version of this series

docs/system/target-riscv.rst | 24 ++++++++++++++++--------
disas/riscv.h                |  2 ++
disas/riscv.c                | 19 ++++++++++++++++---
hw/riscv/numa.c              |  4 ++--
target/riscv/cpu.c           |  3 ++-
target/riscv/vector_helper.c |  4 ++--
6 files changed, 40 insertions(+), 16 deletions(-)

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[PULL 0/5] riscv-to-apply queue

Posted by Alistair Francis 9 months, 2 weeks ago

The following changes since commit 361d5397355276e3007825cc17217c1e4d4320f7:

  Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-07-17 15:49:27 +0100)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230719-1

for you to fetch changes up to 32be32509987fbe42cf5c2fd3cea3c2ad6eae179:

  target/riscv: Fix LMUL check to use VLEN (2023-07-19 14:37:26 +1000)

----------------------------------------------------------------
Fourth RISC-V PR for 8.1

* Fix LMUL check to use VLEN
* Fix typo field in NUMA error_report
* check priv_ver before auto-enable zca/zcd/zcf
* Fix disas output of upper immediates
* tidy CPU firmware section

----------------------------------------------------------------
Christoph Müllner (1):
      riscv/disas: Fix disas output of upper immediates

Daniel Henrique Barboza (2):
      docs/system/target-riscv.rst: tidy CPU firmware section
      target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf

Rob Bradford (1):
      target/riscv: Fix LMUL check to use VLEN

Zhao Liu (1):
      hw/riscv: Fix typo field in error_report

 docs/system/target-riscv.rst | 24 ++++++++++++++++--------
 disas/riscv.h                |  2 ++
 disas/riscv.c                | 19 ++++++++++++++++---
 hw/riscv/numa.c              |  4 ++--
 target/riscv/cpu.c           |  3 ++-
 target/riscv/vector_helper.c |  4 ++--
 6 files changed, 40 insertions(+), 16 deletions(-)

Re: [PULL 0/5] riscv-to-apply queue

Posted by Peter Maydell 9 months, 2 weeks ago

On Wed, 19 Jul 2023 at 05:46, Alistair Francis <alistair23@gmail.com> wrote:
>
> The following changes since commit 361d5397355276e3007825cc17217c1e4d4320f7:
>
>   Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into staging (2023-07-17 15:49:27 +0100)
>
> are available in the Git repository at:
>
>   https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230719-1
>
> for you to fetch changes up to 32be32509987fbe42cf5c2fd3cea3c2ad6eae179:
>
>   target/riscv: Fix LMUL check to use VLEN (2023-07-19 14:37:26 +1000)
>
> ----------------------------------------------------------------
> Fourth RISC-V PR for 8.1
>
> * Fix LMUL check to use VLEN
> * Fix typo field in NUMA error_report
> * check priv_ver before auto-enable zca/zcd/zcf
> * Fix disas output of upper immediates
> * tidy CPU firmware section
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/8.1
for any user-visible changes.

-- PMM