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Mon, 03 Jul 2023 11:31:54 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Beraldo Leal , Wainer dos Santos Moschetta , Alistair Francis , Daniel Henrique Barboza , kvm@vger.kernel.org, qemu-riscv@nongnu.org, Bin Meng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Liu Zhiwei Subject: [PATCH v2 01/16] target/riscv: Remove unuseful KVM stubs Date: Mon, 3 Jul 2023 20:31:30 +0200 Message-Id: <20230703183145.24779-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230703183145.24779-1-philmd@linaro.org> References: <20230703183145.24779-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688409274857100001 Since we always check whether KVM is enabled before calling kvm_riscv_reset_vcpu() and kvm_riscv_set_irq(), their call is elided by the compiler when KVM is not available. Therefore the stubs are not even linked. Remove them. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Tested-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/kvm-stub.c | 30 ------------------------------ target/riscv/kvm.c | 4 +--- target/riscv/meson.build | 2 +- 3 files changed, 2 insertions(+), 34 deletions(-) delete mode 100644 target/riscv/kvm-stub.c diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c deleted file mode 100644 index 4e8fc31a21..0000000000 --- a/target/riscv/kvm-stub.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * QEMU KVM RISC-V specific function stubs - * - * Copyright (c) 2020 Huawei Technologies Co., Ltd - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or - * more details. - * - * You should have received a copy of the GNU General Public License along= with - * this program. If not, see . - */ -#include "qemu/osdep.h" -#include "cpu.h" -#include "kvm_riscv.h" - -void kvm_riscv_reset_vcpu(RISCVCPU *cpu) -{ - abort(); -} - -void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) -{ - abort(); -} diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 0f932a5b96..52884bbe15 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -503,9 +503,7 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu) { CPURISCVState *env =3D &cpu->env; =20 - if (!kvm_enabled()) { - return; - } + assert(kvm_enabled()); env->pc =3D cpu->env.kernel_addr; env->gpr[10] =3D kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ env->gpr[11] =3D cpu->env.fdt_addr; /* a1 */ diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 7f56c5f88d..e3ab3df4e5 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -22,7 +22,7 @@ riscv_ss.add(files( 'crypto_helper.c', 'zce_helper.c' )) -riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files(= 'kvm-stub.c')) +riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 riscv_system_ss =3D ss.source_set() riscv_system_ss.add(files( --=20 2.38.1 From nobody Tue May 14 09:30:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 03 Jul 2023 11:32:00 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Beraldo Leal , Wainer dos Santos Moschetta , Alistair Francis , Daniel Henrique Barboza , kvm@vger.kernel.org, qemu-riscv@nongnu.org, Bin Meng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Liu Zhiwei Subject: [PATCH v2 02/16] target/riscv: Remove unused 'instmap.h' header in translate.c Date: Mon, 3 Jul 2023 20:31:31 +0200 Message-Id: <20230703183145.24779-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230703183145.24779-1-philmd@linaro.org> References: <20230703183145.24779-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688409160652100004 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- target/riscv/translate.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 621dd99241..e3a6697cd8 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -30,7 +30,6 @@ #include "exec/log.h" #include "semihosting/semihost.h" =20 -#include "instmap.h" #include "internals.h" =20 #define HELPER_H "helper.h" --=20 2.38.1 From nobody Tue May 14 09:30:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 03 Jul 2023 11:32:07 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Beraldo Leal , Wainer dos Santos Moschetta , Alistair Francis , Daniel Henrique Barboza , kvm@vger.kernel.org, qemu-riscv@nongnu.org, Bin Meng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Liu Zhiwei Subject: [PATCH v2 03/16] target/riscv: Restrict sysemu specific header to user emulation Date: Mon, 3 Jul 2023 20:31:32 +0200 Message-Id: <20230703183145.24779-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230703183145.24779-1-philmd@linaro.org> References: <20230703183145.24779-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688409291454100003 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- target/riscv/cpu.c | 8 +++++--- target/riscv/cpu_helper.c | 2 ++ target/riscv/csr.c | 2 ++ 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fd647534cf..174003348f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -23,9 +23,13 @@ #include "qemu/log.h" #include "cpu.h" #include "cpu_vendorid.h" +#ifndef CONFIG_USER_ONLY #include "pmu.h" -#include "internals.h" #include "time_helper.h" +#include "sysemu/kvm.h" +#include "kvm_riscv.h" +#endif +#include "internals.h" #include "exec/exec-all.h" #include "qapi/error.h" #include "qapi/visitor.h" @@ -33,8 +37,6 @@ #include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "fpu/softfloat-helpers.h" -#include "sysemu/kvm.h" -#include "kvm_riscv.h" #include "tcg/tcg.h" =20 /* RISC-V CPU definitions */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9f611d89bb..e8b7f70be3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -28,7 +28,9 @@ #include "tcg/tcg-op.h" #include "trace.h" #include "semihosting/common-semi.h" +#ifndef CONFIG_USER_ONLY #include "sysemu/cpu-timers.h" +#endif #include "cpu_bits.h" #include "debug.h" #include "tcg/oversized-guest.h" diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ea7585329e..e5737dcf58 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -21,8 +21,10 @@ #include "qemu/log.h" #include "qemu/timer.h" #include "cpu.h" +#ifndef CONFIG_USER_ONLY #include "pmu.h" #include "time_helper.h" +#endif #include "qemu/main-loop.h" #include "exec/exec-all.h" #include "exec/tb-flush.h" --=20 2.38.1 From nobody Tue May 14 09:30:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 03 Jul 2023 11:32:13 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Beraldo Leal , Wainer dos Santos Moschetta , Alistair Francis , Daniel Henrique Barboza , kvm@vger.kernel.org, qemu-riscv@nongnu.org, Bin Meng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Liu Zhiwei Subject: [PATCH v2 04/16] target/riscv: Restrict 'rv128' machine to TCG accelerator Date: Mon, 3 Jul 2023 20:31:33 +0200 Message-Id: <20230703183145.24779-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230703183145.24779-1-philmd@linaro.org> References: <20230703183145.24779-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688409357635100002 We only build for 32/64-bit hosts, so TCG is required for 128-bit targets. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- target/riscv/cpu.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 174003348f..78ab61c274 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -498,6 +498,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) #endif } =20 +#ifdef CONFIG_TCG static void rv128_base_cpu_init(Object *obj) { if (qemu_tcg_mttcg_enabled()) { @@ -516,7 +517,10 @@ static void rv128_base_cpu_init(Object *obj) set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif } -#else +#endif + +#else /* !TARGET_RISCV64 */ + static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -598,7 +602,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) cpu->cfg.ext_icsr =3D true; cpu->cfg.pmp =3D true; } -#endif +#endif /* !TARGET_RISCV64 */ =20 #if defined(CONFIG_KVM) static void riscv_host_cpu_init(Object *obj) @@ -2033,8 +2037,10 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), +#ifdef CONFIG_TCG DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), -#endif +#endif /* CONFIG_TCG */ +#endif /* TARGET_RISCV64 */ }; =20 DEFINE_TYPES(riscv_cpu_type_infos) --=20 2.38.1 From nobody Tue May 14 09:30:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1688409192; cv=none; d=zohomail.com; s=zohoarc; b=iUjJE55cynpjQibi/z5zSyapSQc+tN0o2aZinj2WJkZdNH9fj8y25Cq+SqTtfl0AkXoi4FcWFwfZGWwSr6s6I6DuIzO70KjGG0ZMkaXj1/+Z529lWyivqFHGXvC7SMecHqtUmX9Gj1vSI4xjO8n7kqvN9/4Ga6padItiujcX3Wo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1688409192; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4bG6Uf/f+7A9KUtA1/pgxRjW23AnhFwtnrhoueQYVoE=; b=k2TBHbudRWsCpwHXohTXCU4QdwJ4e/eLoiQ4TCBW7KReMt4VPzBv72W9zrkuAn7nJPOX7jxYXWMGM6qMSiW44R6Db7BONziODEVmLVRPsLXlELZnv8nGt9P6kaBfaj4eGIxzY4cdfqX4ZzB+rm2csjWB2yT74vmV3CMVL03x3iE= ARC-Authentication-Results: i=1; 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Mon, 03 Jul 2023 11:32:20 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Beraldo Leal , Wainer dos Santos Moschetta , Alistair Francis , Daniel Henrique Barboza , kvm@vger.kernel.org, qemu-riscv@nongnu.org, Bin Meng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Liu Zhiwei Subject: [PATCH v2 05/16] target/riscv: Move sysemu-specific files to target/riscv/sysemu/ Date: Mon, 3 Jul 2023 20:31:34 +0200 Message-Id: <20230703183145.24779-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230703183145.24779-1-philmd@linaro.org> References: <20230703183145.24779-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12c; envelope-from=philmd@linaro.org; helo=mail-lf1-x12c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688409194364100005 Move sysemu-specific files to the a new 'sysemu' sub-directory, adapt meson rules. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/{ =3D> sysemu}/instmap.h | 0 target/riscv/{ =3D> sysemu}/kvm_riscv.h | 0 target/riscv/{ =3D> sysemu}/pmp.h | 0 target/riscv/{ =3D> sysemu}/pmu.h | 0 target/riscv/{ =3D> sysemu}/time_helper.h | 0 hw/riscv/virt.c | 2 +- target/riscv/cpu.c | 6 ++--- target/riscv/cpu_helper.c | 4 +-- target/riscv/csr.c | 4 +-- target/riscv/{ =3D> sysemu}/arch_dump.c | 0 target/riscv/sysemu/kvm-stub.c | 30 ++++++++++++++++++++++ target/riscv/{ =3D> sysemu}/kvm.c | 0 target/riscv/{ =3D> sysemu}/machine.c | 0 target/riscv/{ =3D> sysemu}/monitor.c | 0 target/riscv/{ =3D> sysemu}/pmp.c | 0 target/riscv/{ =3D> sysemu}/pmu.c | 0 target/riscv/{ =3D> sysemu}/riscv-qmp-cmds.c | 0 target/riscv/{ =3D> sysemu}/time_helper.c | 0 target/riscv/meson.build | 13 +++------- target/riscv/sysemu/meson.build | 11 ++++++++ 21 files changed, 54 insertions(+), 18 deletions(-) rename target/riscv/{ =3D> sysemu}/instmap.h (100%) rename target/riscv/{ =3D> sysemu}/kvm_riscv.h (100%) rename target/riscv/{ =3D> sysemu}/pmp.h (100%) rename target/riscv/{ =3D> sysemu}/pmu.h (100%) rename target/riscv/{ =3D> sysemu}/time_helper.h (100%) rename target/riscv/{ =3D> sysemu}/arch_dump.c (100%) create mode 100644 target/riscv/sysemu/kvm-stub.c rename target/riscv/{ =3D> sysemu}/kvm.c (100%) rename target/riscv/{ =3D> sysemu}/machine.c (100%) rename target/riscv/{ =3D> sysemu}/monitor.c (100%) rename target/riscv/{ =3D> sysemu}/pmp.c (100%) rename target/riscv/{ =3D> sysemu}/pmu.c (100%) rename target/riscv/{ =3D> sysemu}/riscv-qmp-cmds.c (100%) rename target/riscv/{ =3D> sysemu}/time_helper.c (100%) create mode 100644 target/riscv/sysemu/meson.build diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3081603464..00a4842d84 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -88,7 +88,7 @@ typedef enum { #define MAX_RISCV_PMPS (16) =20 #if !defined(CONFIG_USER_ONLY) -#include "pmp.h" +#include "sysemu/pmp.h" #include "debug.h" #endif =20 diff --git a/target/riscv/instmap.h b/target/riscv/sysemu/instmap.h similarity index 100% rename from target/riscv/instmap.h rename to target/riscv/sysemu/instmap.h diff --git a/target/riscv/kvm_riscv.h b/target/riscv/sysemu/kvm_riscv.h similarity index 100% rename from target/riscv/kvm_riscv.h rename to target/riscv/sysemu/kvm_riscv.h diff --git a/target/riscv/pmp.h b/target/riscv/sysemu/pmp.h similarity index 100% rename from target/riscv/pmp.h rename to target/riscv/sysemu/pmp.h diff --git a/target/riscv/pmu.h b/target/riscv/sysemu/pmu.h similarity index 100% rename from target/riscv/pmu.h rename to target/riscv/sysemu/pmu.h diff --git a/target/riscv/time_helper.h b/target/riscv/sysemu/time_helper.h similarity index 100% rename from target/riscv/time_helper.h rename to target/riscv/sysemu/time_helper.h diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 8ff4b5fd71..8f6b63ad07 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -30,7 +30,7 @@ #include "hw/char/serial.h" #include "target/riscv/cpu.h" #include "hw/core/sysbus-fdt.h" -#include "target/riscv/pmu.h" +#include "target/riscv/sysemu/pmu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 78ab61c274..cd01af3595 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -24,10 +24,10 @@ #include "cpu.h" #include "cpu_vendorid.h" #ifndef CONFIG_USER_ONLY -#include "pmu.h" -#include "time_helper.h" +#include "sysemu/pmu.h" +#include "sysemu/time_helper.h" #include "sysemu/kvm.h" -#include "kvm_riscv.h" +#include "sysemu/kvm_riscv.h" #endif #include "internals.h" #include "exec/exec-all.h" diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e8b7f70be3..0adde26321 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -22,9 +22,9 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "internals.h" -#include "pmu.h" +#include "sysemu/pmu.h" #include "exec/exec-all.h" -#include "instmap.h" +#include "sysemu/instmap.h" #include "tcg/tcg-op.h" #include "trace.h" #include "semihosting/common-semi.h" diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e5737dcf58..29151429ee 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -22,8 +22,8 @@ #include "qemu/timer.h" #include "cpu.h" #ifndef CONFIG_USER_ONLY -#include "pmu.h" -#include "time_helper.h" +#include "sysemu/pmu.h" +#include "sysemu/time_helper.h" #endif #include "qemu/main-loop.h" #include "exec/exec-all.h" diff --git a/target/riscv/arch_dump.c b/target/riscv/sysemu/arch_dump.c similarity index 100% rename from target/riscv/arch_dump.c rename to target/riscv/sysemu/arch_dump.c diff --git a/target/riscv/sysemu/kvm-stub.c b/target/riscv/sysemu/kvm-stub.c new file mode 100644 index 0000000000..4e8fc31a21 --- /dev/null +++ b/target/riscv/sysemu/kvm-stub.c @@ -0,0 +1,30 @@ +/* + * QEMU KVM RISC-V specific function stubs + * + * Copyright (c) 2020 Huawei Technologies Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "kvm_riscv.h" + +void kvm_riscv_reset_vcpu(RISCVCPU *cpu) +{ + abort(); +} + +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) +{ + abort(); +} diff --git a/target/riscv/kvm.c b/target/riscv/sysemu/kvm.c similarity index 100% rename from target/riscv/kvm.c rename to target/riscv/sysemu/kvm.c diff --git a/target/riscv/machine.c b/target/riscv/sysemu/machine.c similarity index 100% rename from target/riscv/machine.c rename to target/riscv/sysemu/machine.c diff --git a/target/riscv/monitor.c b/target/riscv/sysemu/monitor.c similarity index 100% rename from target/riscv/monitor.c rename to target/riscv/sysemu/monitor.c diff --git a/target/riscv/pmp.c b/target/riscv/sysemu/pmp.c similarity index 100% rename from target/riscv/pmp.c rename to target/riscv/sysemu/pmp.c diff --git a/target/riscv/pmu.c b/target/riscv/sysemu/pmu.c similarity index 100% rename from target/riscv/pmu.c rename to target/riscv/sysemu/pmu.c diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/sysemu/riscv-qmp-= cmds.c similarity index 100% rename from target/riscv/riscv-qmp-cmds.c rename to target/riscv/sysemu/riscv-qmp-cmds.c diff --git a/target/riscv/time_helper.c b/target/riscv/sysemu/time_helper.c similarity index 100% rename from target/riscv/time_helper.c rename to target/riscv/sysemu/time_helper.c diff --git a/target/riscv/meson.build b/target/riscv/meson.build index e3ab3df4e5..8967dfaded 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -7,6 +7,8 @@ gen =3D [ ] =20 riscv_ss =3D ss.source_set() +riscv_system_ss =3D ss.source_set() + riscv_ss.add(gen) riscv_ss.add(files( 'cpu.c', @@ -22,19 +24,12 @@ riscv_ss.add(files( 'crypto_helper.c', 'zce_helper.c' )) -riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) =20 -riscv_system_ss =3D ss.source_set() riscv_system_ss.add(files( - 'arch_dump.c', - 'pmp.c', 'debug.c', - 'monitor.c', - 'machine.c', - 'pmu.c', - 'time_helper.c', - 'riscv-qmp-cmds.c', )) =20 +subdir('sysemu') + target_arch +=3D {'riscv': riscv_ss} target_softmmu_arch +=3D {'riscv': riscv_system_ss} diff --git a/target/riscv/sysemu/meson.build b/target/riscv/sysemu/meson.bu= ild new file mode 100644 index 0000000000..64de0256a5 --- /dev/null +++ b/target/riscv/sysemu/meson.build @@ -0,0 +1,11 @@ +riscv_system_ss.add(files( + 'arch_dump.c', + 'machine.c', + 'monitor.c', + 'pmp.c', + 'pmu.c', + 'riscv-qmp-cmds.c', + 'time_helper.c', +)) + +riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) --=20 2.38.1 From nobody Tue May 14 09:30:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 03 Jul 2023 11:32:27 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Beraldo Leal , Wainer dos Santos Moschetta , Alistair Francis , Daniel Henrique Barboza , kvm@vger.kernel.org, qemu-riscv@nongnu.org, Bin Meng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Liu Zhiwei Subject: [PATCH v2 06/16] target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu Date: Mon, 3 Jul 2023 20:31:35 +0200 Message-Id: <20230703183145.24779-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230703183145.24779-1-philmd@linaro.org> References: <20230703183145.24779-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688409204798100003 riscv_cpu_do_interrupt() is not reachable on user emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.h | 5 +++-- target/riscv/cpu_helper.c | 7 ++----- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 00a4842d84..e6a8087022 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -411,7 +411,6 @@ extern const char * const riscv_int_regnamesh[]; extern const char * const riscv_fpr_regnames[]; =20 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); -void riscv_cpu_do_interrupt(CPUState *cpu); int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, DumpState *s); int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, @@ -444,6 +443,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, E= rror **errp); #define cpu_mmu_index riscv_cpu_mmu_index =20 #ifndef CONFIG_USER_ONLY +void riscv_cpu_do_interrupt(CPUState *cpu); void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, @@ -467,7 +467,8 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, = uint32_t priv, void *rmw_fn_arg); =20 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bi= t); -#endif +#endif /* !CONFIG_USER_ONLY */ + void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); =20 void riscv_translate_init(void); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0adde26321..597c47bc56 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1579,7 +1579,6 @@ static target_ulong riscv_transformed_insn(CPURISCVSt= ate *env, =20 return xinsn; } -#endif /* !CONFIG_USER_ONLY */ =20 /* * Handle Traps @@ -1589,8 +1588,6 @@ static target_ulong riscv_transformed_insn(CPURISCVSt= ate *env, */ void riscv_cpu_do_interrupt(CPUState *cs) { -#if !defined(CONFIG_USER_ONLY) - RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; bool write_gva =3D false; @@ -1783,6 +1780,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) =20 env->two_stage_lookup =3D false; env->two_stage_indirect_lookup =3D false; -#endif - cs->exception_index =3D RISCV_EXCP_NONE; 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Mon, 03 Jul 2023 11:32:34 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Beraldo Leal , Wainer dos Santos Moschetta , Alistair Francis , Daniel Henrique Barboza , kvm@vger.kernel.org, qemu-riscv@nongnu.org, Bin Meng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Liu Zhiwei Subject: [PATCH v2 07/16] target/riscv: Move TCG-specific files to target/riscv/tcg/ Date: Mon, 3 Jul 2023 20:31:36 +0200 Message-Id: <20230703183145.24779-8-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230703183145.24779-1-philmd@linaro.org> References: <20230703183145.24779-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688409385709100001 Move TCG-specific files to the a new 'tcg' sub-directory. Add stubs for riscv_cpu_[get/set]_fflags and riscv_raise_exception(). Adapt meson rules. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/{ =3D> tcg}/XVentanaCondOps.decode | 0 target/riscv/{ =3D> tcg}/insn16.decode | 0 target/riscv/{ =3D> tcg}/insn32.decode | 0 target/riscv/{ =3D> tcg}/xthead.decode | 0 target/riscv/{ =3D> tcg}/bitmanip_helper.c | 0 target/riscv/{ =3D> tcg}/crypto_helper.c | 0 target/riscv/{ =3D> tcg}/fpu_helper.c | 0 target/riscv/{ =3D> tcg}/m128_helper.c | 0 target/riscv/{ =3D> tcg}/op_helper.c | 0 target/riscv/tcg/tcg-stub.c | 25 +++++++++++++++++++ target/riscv/{ =3D> tcg}/translate.c | 0 target/riscv/{ =3D> tcg}/vector_helper.c | 0 target/riscv/{ =3D> tcg}/zce_helper.c | 0 target/riscv/meson.build | 18 +------------ target/riscv/tcg/meson.build | 19 ++++++++++++++ 15 files changed, 45 insertions(+), 17 deletions(-) rename target/riscv/{ =3D> tcg}/XVentanaCondOps.decode (100%) rename target/riscv/{ =3D> tcg}/insn16.decode (100%) rename target/riscv/{ =3D> tcg}/insn32.decode (100%) rename target/riscv/{ =3D> tcg}/xthead.decode (100%) rename target/riscv/{ =3D> tcg}/bitmanip_helper.c (100%) rename target/riscv/{ =3D> tcg}/crypto_helper.c (100%) rename target/riscv/{ =3D> tcg}/fpu_helper.c (100%) rename target/riscv/{ =3D> tcg}/m128_helper.c (100%) rename target/riscv/{ =3D> tcg}/op_helper.c (100%) create mode 100644 target/riscv/tcg/tcg-stub.c rename target/riscv/{ =3D> tcg}/translate.c (100%) rename target/riscv/{ =3D> tcg}/vector_helper.c (100%) rename target/riscv/{ =3D> tcg}/zce_helper.c (100%) create mode 100644 target/riscv/tcg/meson.build diff --git a/target/riscv/XVentanaCondOps.decode b/target/riscv/tcg/XVentan= aCondOps.decode similarity index 100% rename from target/riscv/XVentanaCondOps.decode rename to target/riscv/tcg/XVentanaCondOps.decode diff --git a/target/riscv/insn16.decode b/target/riscv/tcg/insn16.decode similarity index 100% rename from target/riscv/insn16.decode rename to target/riscv/tcg/insn16.decode diff --git a/target/riscv/insn32.decode b/target/riscv/tcg/insn32.decode similarity index 100% rename from target/riscv/insn32.decode rename to target/riscv/tcg/insn32.decode diff --git a/target/riscv/xthead.decode b/target/riscv/tcg/xthead.decode similarity index 100% rename from target/riscv/xthead.decode rename to target/riscv/tcg/xthead.decode diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/tcg/bitmanip_hel= per.c similarity index 100% rename from target/riscv/bitmanip_helper.c rename to target/riscv/tcg/bitmanip_helper.c diff --git a/target/riscv/crypto_helper.c b/target/riscv/tcg/crypto_helper.c similarity index 100% rename from target/riscv/crypto_helper.c rename to target/riscv/tcg/crypto_helper.c diff --git a/target/riscv/fpu_helper.c b/target/riscv/tcg/fpu_helper.c similarity index 100% rename from target/riscv/fpu_helper.c rename to target/riscv/tcg/fpu_helper.c diff --git a/target/riscv/m128_helper.c b/target/riscv/tcg/m128_helper.c similarity index 100% rename from target/riscv/m128_helper.c rename to target/riscv/tcg/m128_helper.c diff --git a/target/riscv/op_helper.c b/target/riscv/tcg/op_helper.c similarity index 100% rename from target/riscv/op_helper.c rename to target/riscv/tcg/op_helper.c diff --git a/target/riscv/tcg/tcg-stub.c b/target/riscv/tcg/tcg-stub.c new file mode 100644 index 0000000000..dfe42ae2ac --- /dev/null +++ b/target/riscv/tcg/tcg-stub.c @@ -0,0 +1,25 @@ +/* + * QEMU RISC-V TCG stubs + * + * Copyright (c) 2023 Linaro + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" + +target_ulong riscv_cpu_get_fflags(CPURISCVState *env) +{ + g_assert_not_reached(); +} + +void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong) +{ + g_assert_not_reached(); +} + +G_NORETURN void riscv_raise_exception(CPURISCVState *env, + uint32_t exception, uintptr_t pc) +{ + g_assert_not_reached(); +} diff --git a/target/riscv/translate.c b/target/riscv/tcg/translate.c similarity index 100% rename from target/riscv/translate.c rename to target/riscv/tcg/translate.c diff --git a/target/riscv/vector_helper.c b/target/riscv/tcg/vector_helper.c similarity index 100% rename from target/riscv/vector_helper.c rename to target/riscv/tcg/vector_helper.c diff --git a/target/riscv/zce_helper.c b/target/riscv/tcg/zce_helper.c similarity index 100% rename from target/riscv/zce_helper.c rename to target/riscv/tcg/zce_helper.c diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 8967dfaded..8ef47f43f9 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -1,34 +1,18 @@ -# FIXME extra_args should accept files() -gen =3D [ - decodetree.process('insn16.decode', extra_args: ['--static-decode=3Ddeco= de_insn16', '--insnwidth=3D16']), - decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), - decodetree.process('xthead.decode', extra_args: '--static-decode=3Ddecod= e_xthead'), - decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decod= e=3Ddecode_XVentanaCodeOps'), -] - riscv_ss =3D ss.source_set() riscv_system_ss =3D ss.source_set() =20 -riscv_ss.add(gen) riscv_ss.add(files( 'cpu.c', 'cpu_helper.c', 'csr.c', - 'fpu_helper.c', 'gdbstub.c', - 'op_helper.c', - 'vector_helper.c', - 'bitmanip_helper.c', - 'translate.c', - 'm128_helper.c', - 'crypto_helper.c', - 'zce_helper.c' )) =20 riscv_system_ss.add(files( 'debug.c', )) =20 +subdir('tcg') subdir('sysemu') =20 target_arch +=3D {'riscv': riscv_ss} diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build new file mode 100644 index 0000000000..65670493b1 --- /dev/null +++ b/target/riscv/tcg/meson.build @@ -0,0 +1,19 @@ +# FIXME extra_args should accept files() +gen =3D [ + decodetree.process('insn16.decode', extra_args: ['--static-decode=3Ddeco= de_insn16', '--insnwidth=3D16']), + decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddecod= e_insn32'), + decodetree.process('xthead.decode', extra_args: '--static-decode=3Ddecod= e_xthead'), + decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decod= e=3Ddecode_XVentanaCodeOps'), +] +riscv_ss.add(when: 'CONFIG_TCG', if_true: gen) + +riscv_ss.add(when: 'CONFIG_TCG', if_true: files( + 'fpu_helper.c', + 'op_helper.c', + 'vector_helper.c', + 'bitmanip_helper.c', + 'translate.c', + 'm128_helper.c', + 'crypto_helper.c', + 'zce_helper.c', +), if_false: files('tcg-stub.c')) --=20 2.38.1 From nobody Tue May 14 09:30:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 03 Jul 2023 11:32:40 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Beraldo Leal , Wainer dos Santos Moschetta , Alistair Francis , Daniel Henrique Barboza , kvm@vger.kernel.org, qemu-riscv@nongnu.org, Bin Meng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Liu Zhiwei Subject: [PATCH v2 08/16] target/riscv: Move TCG-specific cpu_get_tb_cpu_state() to tcg/cpu.c Date: Mon, 3 Jul 2023 20:31:37 +0200 Message-Id: <20230703183145.24779-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230703183145.24779-1-philmd@linaro.org> References: <20230703183145.24779-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688409297417100001 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Alistair Francis --- target/riscv/cpu_helper.c | 84 ------------------------------- target/riscv/tcg/cpu.c | 98 ++++++++++++++++++++++++++++++++++++ target/riscv/tcg/meson.build | 1 + 3 files changed, 99 insertions(+), 84 deletions(-) create mode 100644 target/riscv/tcg/cpu.c diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 597c47bc56..6f8778c6d3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -64,90 +64,6 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) #endif } =20 -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - CPUState *cs =3D env_cpu(env); - RISCVCPU *cpu =3D RISCV_CPU(cs); - RISCVExtStatus fs, vs; - uint32_t flags =3D 0; - - *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; - *cs_base =3D 0; - - if (cpu->cfg.ext_zve32f) { - /* - * If env->vl equals to VLMAX, we can use generic vector operation - * expanders (GVEC) to accerlate the vector operations. - * However, as LMUL could be a fractional number. The maximum - * vector size can be operated might be less than 8 bytes, - * which is not supported by GVEC. So we set vl_eq_vlmax flag to t= rue - * only when maxsz >=3D 8 bytes. - */ - uint32_t vlmax =3D vext_get_vlmax(cpu, env->vtype); - uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); - uint32_t maxsz =3D vlmax << sew; - bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) && - (maxsz >=3D 8); - flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); - flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, sew); - flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, - FIELD_EX64(env->vtype, VTYPE, VLMUL)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); - flags =3D FIELD_DP32(flags, TB_FLAGS, VTA, - FIELD_EX64(env->vtype, VTYPE, VTA)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, - FIELD_EX64(env->vtype, VTYPE, VMA)); - flags =3D FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart = =3D=3D 0); - } else { - flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); - } - -#ifdef CONFIG_USER_ONLY - fs =3D EXT_STATUS_DIRTY; - vs =3D EXT_STATUS_DIRTY; -#else - flags =3D FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); - - flags |=3D cpu_mmu_index(env, 0); - fs =3D get_field(env->mstatus, MSTATUS_FS); - vs =3D get_field(env->mstatus, MSTATUS_VS); - - if (env->virt_enabled) { - flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); - /* - * Merge DISABLED and !DIRTY states using MIN. - * We will set both fields when dirtying. - */ - fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); - vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); - } - - /* With Zfinx, floating point is enabled/disabled by Smstateen. */ - if (!riscv_has_ext(env, RVF)) { - fs =3D (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) =3D=3D RISCV_EXC= P_NONE) - ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; - } - - if (cpu->cfg.debug && !icount_enabled()) { - flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); - } -#endif - - flags =3D FIELD_DP32(flags, TB_FLAGS, FS, fs); - flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); - flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); - flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); - if (env->cur_pmmask !=3D 0) { - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); - } - if (env->cur_pmbase !=3D 0) { - flags =3D FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); - } - - *pflags =3D flags; -} - void riscv_cpu_update_mask(CPURISCVState *env) { target_ulong mask =3D 0, base =3D 0; diff --git a/target/riscv/tcg/cpu.c b/target/riscv/tcg/cpu.c new file mode 100644 index 0000000000..2ae6919b80 --- /dev/null +++ b/target/riscv/tcg/cpu.c @@ -0,0 +1,98 @@ +/* + * RISC-V CPU helpers (TCG specific) + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2017-2018 SiFive, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#ifndef CONFIG_USER_ONLY +#include "sysemu/cpu-timers.h" +#endif + +void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + RISCVExtStatus fs, vs; + uint32_t flags =3D 0; + + *pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc; + *cs_base =3D 0; + + if (cpu->cfg.ext_zve32f) { + /* + * If env->vl equals to VLMAX, we can use generic vector operation + * expanders (GVEC) to accerlate the vector operations. + * However, as LMUL could be a fractional number. The maximum + * vector size can be operated might be less than 8 bytes, + * which is not supported by GVEC. So we set vl_eq_vlmax flag to t= rue + * only when maxsz >=3D 8 bytes. + */ + uint32_t vlmax =3D vext_get_vlmax(cpu, env->vtype); + uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t maxsz =3D vlmax << sew; + bool vl_eq_vlmax =3D (env->vstart =3D=3D 0) && (vlmax =3D=3D env->= vl) && + (maxsz >=3D 8); + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, env->vill); + flags =3D FIELD_DP32(flags, TB_FLAGS, SEW, sew); + flags =3D FIELD_DP32(flags, TB_FLAGS, LMUL, + FIELD_EX64(env->vtype, VTYPE, VLMUL)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); + flags =3D FIELD_DP32(flags, TB_FLAGS, VTA, + FIELD_EX64(env->vtype, VTYPE, VTA)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, + FIELD_EX64(env->vtype, VTYPE, VMA)); + flags =3D FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart = =3D=3D 0); + } else { + flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); + } + +#ifdef CONFIG_USER_ONLY + fs =3D EXT_STATUS_DIRTY; + vs =3D EXT_STATUS_DIRTY; +#else + flags =3D FIELD_DP32(flags, TB_FLAGS, PRIV, env->priv); + + flags |=3D cpu_mmu_index(env, 0); + fs =3D get_field(env->mstatus, MSTATUS_FS); + vs =3D get_field(env->mstatus, MSTATUS_VS); + + if (env->virt_enabled) { + flags =3D FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1); + /* + * Merge DISABLED and !DIRTY states using MIN. + * We will set both fields when dirtying. + */ + fs =3D MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS)); + vs =3D MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); + } + + /* With Zfinx, floating point is enabled/disabled by Smstateen. */ + if (!riscv_has_ext(env, RVF)) { + fs =3D (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) =3D=3D RISCV_EXC= P_NONE) + ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; + } + + if (cpu->cfg.debug && !icount_enabled()) { + flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); + } +#endif + + flags =3D FIELD_DP32(flags, TB_FLAGS, FS, fs); + flags =3D FIELD_DP32(flags, TB_FLAGS, VS, vs); + flags =3D FIELD_DP32(flags, TB_FLAGS, XL, env->xl); + flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); + if (env->cur_pmmask !=3D 0) { + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); + } + if (env->cur_pmbase !=3D 0) { + flags =3D FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); + } + + *pflags =3D flags; +} diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build index 65670493b1..a615aafd9a 100644 --- a/target/riscv/tcg/meson.build +++ b/target/riscv/tcg/meson.build @@ -8,6 +8,7 @@ gen =3D [ riscv_ss.add(when: 'CONFIG_TCG', if_true: gen) =20 riscv_ss.add(when: 'CONFIG_TCG', if_true: files( + 'cpu.c', 'fpu_helper.c', 'op_helper.c', 'vector_helper.c', --=20 2.38.1 From nobody Tue May 14 09:30:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 03 Jul 2023 11:32:46 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Beraldo Leal , Wainer dos Santos Moschetta , Alistair Francis , Daniel Henrique Barboza , kvm@vger.kernel.org, qemu-riscv@nongnu.org, Bin Meng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Liu Zhiwei Subject: [PATCH v2 09/16] target/riscv: Expose some 'trigger' prototypes from debug.c Date: Mon, 3 Jul 2023 20:31:38 +0200 Message-Id: <20230703183145.24779-10-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230703183145.24779-1-philmd@linaro.org> References: <20230703183145.24779-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688409178708100001 We want to extract TCG-specific code from debug.c, but some functions call get_trigger_type() / do_trigger_action(). Expose these prototypes in "debug.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/debug.h | 4 ++++ target/riscv/debug.c | 5 ++--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index c471748d5a..65cd45b8f3 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -147,4 +147,8 @@ void riscv_trigger_init(CPURISCVState *env); =20 bool riscv_itrigger_enabled(CPURISCVState *env); void riscv_itrigger_update_priv(CPURISCVState *env); + +target_ulong get_trigger_type(CPURISCVState *env, target_ulong trigger_ind= ex); +void do_trigger_action(CPURISCVState *env, target_ulong trigger_index); + #endif /* RISCV_DEBUG_H */ diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 75ee1c4971..5676f2c57e 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -88,8 +88,7 @@ static inline target_ulong extract_trigger_type(CPURISCVS= tate *env, } } =20 -static inline target_ulong get_trigger_type(CPURISCVState *env, - target_ulong trigger_index) +target_ulong get_trigger_type(CPURISCVState *env, target_ulong trigger_ind= ex) { return extract_trigger_type(env, env->tdata1[trigger_index]); } @@ -217,7 +216,7 @@ static inline void warn_always_zero_bit(target_ulong va= l, target_ulong mask, } } =20 -static void do_trigger_action(CPURISCVState *env, target_ulong trigger_ind= ex) +void do_trigger_action(CPURISCVState *env, target_ulong trigger_index) { trigger_action_t action =3D get_trigger_action(env, trigger_index); =20 --=20 2.38.1 From nobody Tue May 14 09:30:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1688409316; cv=none; d=zohomail.com; s=zohoarc; b=Ghmmui4hjZduiQg6g3Oc1fLuVIDu6YBcbc9hOuNHC4YkVg8ZkUkKsxTJ9mcMkMsmGPa+ptSWnm9jkZqN7+w0wTyqUfcEwn6agwPYBV/o3eqz1LvX77aXWdY/w87xMtqVkMkmg36yiGy0keS66DRBRFLkCpfZKDTOvYkTHpC/Lt0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Mon, 03 Jul 2023 11:32:53 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Beraldo Leal , Wainer dos Santos Moschetta , Alistair Francis , Daniel Henrique Barboza , kvm@vger.kernel.org, qemu-riscv@nongnu.org, Bin Meng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Liu Zhiwei Subject: [PATCH v2 10/16] target/riscv: Extract TCG-specific code from debug.c Date: Mon, 3 Jul 2023 20:31:39 +0200 Message-Id: <20230703183145.24779-11-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230703183145.24779-1-philmd@linaro.org> References: <20230703183145.24779-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688409317353100003 Extract TCG-specific code from debug.c to tcg/sysemu/debug.c, restrict the prototypes to TCG, adapt meson rules. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/debug.h | 2 + target/riscv/debug.c | 148 ------------------------- target/riscv/tcg/sysemu/debug.c | 165 ++++++++++++++++++++++++++++ target/riscv/tcg/meson.build | 2 + target/riscv/tcg/sysemu/meson.build | 3 + 5 files changed, 172 insertions(+), 148 deletions(-) create mode 100644 target/riscv/tcg/sysemu/debug.c create mode 100644 target/riscv/tcg/sysemu/meson.build diff --git a/target/riscv/debug.h b/target/riscv/debug.h index 65cd45b8f3..0b3bdd5be1 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -139,9 +139,11 @@ void tdata_csr_write(CPURISCVState *env, int tdata_ind= ex, target_ulong val); =20 target_ulong tinfo_csr_read(CPURISCVState *env); =20 +#ifdef CONFIG_TCG void riscv_cpu_debug_excp_handler(CPUState *cs); bool riscv_cpu_debug_check_breakpoint(CPUState *cs); bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); +#endif =20 void riscv_trigger_init(CPURISCVState *env); =20 diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 5676f2c57e..45a2605d8a 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -754,154 +754,6 @@ target_ulong tinfo_csr_read(CPURISCVState *env) BIT(TRIGGER_TYPE_AD_MATCH6); } =20 -void riscv_cpu_debug_excp_handler(CPUState *cs) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - - if (cs->watchpoint_hit) { - if (cs->watchpoint_hit->flags & BP_CPU) { - do_trigger_action(env, DBG_ACTION_BP); - } - } else { - if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) { - do_trigger_action(env, DBG_ACTION_BP); - } - } -} - -bool riscv_cpu_debug_check_breakpoint(CPUState *cs) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - CPUBreakpoint *bp; - target_ulong ctrl; - target_ulong pc; - int trigger_type; - int i; - - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { - trigger_type =3D get_trigger_type(env, i); - - switch (trigger_type) { - case TRIGGER_TYPE_AD_MATCH: - /* type 2 trigger cannot be fired in VU/VS mode */ - if (env->virt_enabled) { - return false; - } - - ctrl =3D env->tdata1[i]; - pc =3D env->tdata2[i]; - - if ((ctrl & TYPE2_EXEC) && (bp->pc =3D=3D pc)) { - /* check U/S/M bit against current privilege level */ - if ((ctrl >> 3) & BIT(env->priv)) { - return true; - } - } - break; - case TRIGGER_TYPE_AD_MATCH6: - ctrl =3D env->tdata1[i]; - pc =3D env->tdata2[i]; - - if ((ctrl & TYPE6_EXEC) && (bp->pc =3D=3D pc)) { - if (env->virt_enabled) { - /* check VU/VS bit against current privilege level= */ - if ((ctrl >> 23) & BIT(env->priv)) { - return true; - } - } else { - /* check U/S/M bit against current privilege level= */ - if ((ctrl >> 3) & BIT(env->priv)) { - return true; - } - } - } - break; - default: - /* other trigger types are not supported or irrelevant */ - break; - } - } - } - - return false; -} - -bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - target_ulong ctrl; - target_ulong addr; - int trigger_type; - int flags; - int i; - - for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { - trigger_type =3D get_trigger_type(env, i); - - switch (trigger_type) { - case TRIGGER_TYPE_AD_MATCH: - /* type 2 trigger cannot be fired in VU/VS mode */ - if (env->virt_enabled) { - return false; - } - - ctrl =3D env->tdata1[i]; - addr =3D env->tdata2[i]; - flags =3D 0; - - if (ctrl & TYPE2_LOAD) { - flags |=3D BP_MEM_READ; - } - if (ctrl & TYPE2_STORE) { - flags |=3D BP_MEM_WRITE; - } - - if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { - /* check U/S/M bit against current privilege level */ - if ((ctrl >> 3) & BIT(env->priv)) { - return true; - } - } - break; - case TRIGGER_TYPE_AD_MATCH6: - ctrl =3D env->tdata1[i]; - addr =3D env->tdata2[i]; - flags =3D 0; - - if (ctrl & TYPE6_LOAD) { - flags |=3D BP_MEM_READ; - } - if (ctrl & TYPE6_STORE) { - flags |=3D BP_MEM_WRITE; - } - - if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { - if (env->virt_enabled) { - /* check VU/VS bit against current privilege level */ - if ((ctrl >> 23) & BIT(env->priv)) { - return true; - } - } else { - /* check U/S/M bit against current privilege level */ - if ((ctrl >> 3) & BIT(env->priv)) { - return true; - } - } - } - break; - default: - /* other trigger types are not supported */ - break; - } - } - - return false; -} - void riscv_trigger_init(CPURISCVState *env) { target_ulong tdata1 =3D build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0); diff --git a/target/riscv/tcg/sysemu/debug.c b/target/riscv/tcg/sysemu/debu= g.c new file mode 100644 index 0000000000..cdd6744b3a --- /dev/null +++ b/target/riscv/tcg/sysemu/debug.c @@ -0,0 +1,165 @@ +/* + * QEMU RISC-V Native Debug Support (TCG specific) + * + * Copyright (c) 2022 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This provides the native debug support via the Trigger Module, as defin= ed + * in the RISC-V Debug Specification: + * https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable= .pdf + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" + +void riscv_cpu_debug_excp_handler(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + do_trigger_action(env, DBG_ACTION_BP); + } + } else { + if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) { + do_trigger_action(env, DBG_ACTION_BP); + } + } +} + +bool riscv_cpu_debug_check_breakpoint(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + CPUBreakpoint *bp; + target_ulong ctrl; + target_ulong pc; + int trigger_type; + int i; + + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { + trigger_type =3D get_trigger_type(env, i); + + switch (trigger_type) { + case TRIGGER_TYPE_AD_MATCH: + /* type 2 trigger cannot be fired in VU/VS mode */ + if (env->virt_enabled) { + return false; + } + + ctrl =3D env->tdata1[i]; + pc =3D env->tdata2[i]; + + if ((ctrl & TYPE2_EXEC) && (bp->pc =3D=3D pc)) { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + break; + case TRIGGER_TYPE_AD_MATCH6: + ctrl =3D env->tdata1[i]; + pc =3D env->tdata2[i]; + + if ((ctrl & TYPE6_EXEC) && (bp->pc =3D=3D pc)) { + if (env->virt_enabled) { + /* check VU/VS bit against current privilege level= */ + if ((ctrl >> 23) & BIT(env->priv)) { + return true; + } + } else { + /* check U/S/M bit against current privilege level= */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + } + break; + default: + /* other trigger types are not supported or irrelevant */ + break; + } + } + } + + return false; +} + +bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + target_ulong ctrl; + target_ulong addr; + int trigger_type; + int flags; + int i; + + for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { + trigger_type =3D get_trigger_type(env, i); + + switch (trigger_type) { + case TRIGGER_TYPE_AD_MATCH: + /* type 2 trigger cannot be fired in VU/VS mode */ + if (env->virt_enabled) { + return false; + } + + ctrl =3D env->tdata1[i]; + addr =3D env->tdata2[i]; + flags =3D 0; + + if (ctrl & TYPE2_LOAD) { + flags |=3D BP_MEM_READ; + } + if (ctrl & TYPE2_STORE) { + flags |=3D BP_MEM_WRITE; + } + + if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + break; + case TRIGGER_TYPE_AD_MATCH6: + ctrl =3D env->tdata1[i]; + addr =3D env->tdata2[i]; + flags =3D 0; + + if (ctrl & TYPE6_LOAD) { + flags |=3D BP_MEM_READ; + } + if (ctrl & TYPE6_STORE) { + flags |=3D BP_MEM_WRITE; + } + + if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { + if (env->virt_enabled) { + /* check VU/VS bit against current privilege level */ + if ((ctrl >> 23) & BIT(env->priv)) { + return true; + } + } else { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + } + break; + default: + /* other trigger types are not supported */ + break; + } + } + + return false; +} diff --git a/target/riscv/tcg/meson.build b/target/riscv/tcg/meson.build index a615aafd9a..933d340799 100644 --- a/target/riscv/tcg/meson.build +++ b/target/riscv/tcg/meson.build @@ -18,3 +18,5 @@ riscv_ss.add(when: 'CONFIG_TCG', if_true: files( 'crypto_helper.c', 'zce_helper.c', ), if_false: files('tcg-stub.c')) + +subdir('sysemu') diff --git a/target/riscv/tcg/sysemu/meson.build b/target/riscv/tcg/sysemu/= meson.build new file mode 100644 index 0000000000..e8e61e5784 --- /dev/null +++ b/target/riscv/tcg/sysemu/meson.build @@ -0,0 +1,3 @@ +riscv_system_ss.add(when: 'CONFIG_TCG', if_true: files( + 'debug.c', +)) --=20 2.38.1 From nobody Tue May 14 09:30:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 03 Jul 2023 11:32:59 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Beraldo Leal , Wainer dos Santos Moschetta , Alistair Francis , Daniel Henrique Barboza , kvm@vger.kernel.org, qemu-riscv@nongnu.org, Bin Meng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Liu Zhiwei Subject: [PATCH v2 11/16] target/riscv: Move sysemu-specific debug files to target/riscv/sysemu/ Date: Mon, 3 Jul 2023 20:31:40 +0200 Message-Id: <20230703183145.24779-12-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230703183145.24779-1-philmd@linaro.org> References: <20230703183145.24779-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688409194129100003 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.h | 2 +- target/riscv/{ =3D> sysemu}/debug.h | 0 target/riscv/cpu_helper.c | 2 +- target/riscv/{ =3D> sysemu}/debug.c | 0 target/riscv/meson.build | 4 ---- target/riscv/sysemu/meson.build | 1 + 6 files changed, 3 insertions(+), 6 deletions(-) rename target/riscv/{ =3D> sysemu}/debug.h (100%) rename target/riscv/{ =3D> sysemu}/debug.c (100%) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e6a8087022..f9754013a8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -89,7 +89,7 @@ typedef enum { =20 #if !defined(CONFIG_USER_ONLY) #include "sysemu/pmp.h" -#include "debug.h" +#include "sysemu/debug.h" #endif =20 #define RV_VLEN_MAX 1024 diff --git a/target/riscv/debug.h b/target/riscv/sysemu/debug.h similarity index 100% rename from target/riscv/debug.h rename to target/riscv/sysemu/debug.h diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6f8778c6d3..6c773000a5 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -32,7 +32,7 @@ #include "sysemu/cpu-timers.h" #endif #include "cpu_bits.h" -#include "debug.h" +#include "sysemu/debug.h" #include "tcg/oversized-guest.h" =20 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) diff --git a/target/riscv/debug.c b/target/riscv/sysemu/debug.c similarity index 100% rename from target/riscv/debug.c rename to target/riscv/sysemu/debug.c diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 8ef47f43f9..49cdcde679 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -8,10 +8,6 @@ riscv_ss.add(files( 'gdbstub.c', )) =20 -riscv_system_ss.add(files( - 'debug.c', -)) - subdir('tcg') subdir('sysemu') =20 diff --git a/target/riscv/sysemu/meson.build b/target/riscv/sysemu/meson.bu= ild index 64de0256a5..e902ba2dad 100644 --- a/target/riscv/sysemu/meson.build +++ b/target/riscv/sysemu/meson.build @@ -1,5 +1,6 @@ riscv_system_ss.add(files( 'arch_dump.c', + 'debug.c', 'machine.c', 'monitor.c', 'pmp.c', --=20 2.38.1 From nobody Tue May 14 09:30:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 03 Jul 2023 11:33:05 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Beraldo Leal , Wainer dos Santos Moschetta , Alistair Francis , Daniel Henrique Barboza , kvm@vger.kernel.org, qemu-riscv@nongnu.org, Bin Meng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Liu Zhiwei Subject: [PATCH v2 12/16] target/riscv: Expose riscv_cpu_pending_to_irq() from cpu_helper.c Date: Mon, 3 Jul 2023 20:31:41 +0200 Message-Id: <20230703183145.24779-13-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230703183145.24779-1-philmd@linaro.org> References: <20230703183145.24779-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688409341633100003 We want to extract TCG/sysemu-specific code from cpu_helper.c, but some functions call riscv_cpu_pending_to_irq(). Expose the prototype in "internals.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/internals.h | 4 ++++ target/riscv/cpu_helper.c | 6 +++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index b5f823c7ec..b6881b4815 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -72,6 +72,10 @@ target_ulong fclass_d(uint64_t frs1); =20 #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_riscv_cpu; + +int riscv_cpu_pending_to_irq(CPURISCVState *env, + int extirq, unsigned int extirq_def_prio, + uint64_t pending, uint8_t *iprio); #endif =20 enum { diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 6c773000a5..e73cf56e5c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -256,9 +256,9 @@ uint8_t riscv_cpu_default_priority(int irq) return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; }; =20 -static int riscv_cpu_pending_to_irq(CPURISCVState *env, - int extirq, unsigned int extirq_def_pr= io, - uint64_t pending, uint8_t *iprio) +int riscv_cpu_pending_to_irq(CPURISCVState *env, + int extirq, unsigned int extirq_def_prio, + uint64_t pending, uint8_t *iprio) { int irq, best_irq =3D RISCV_EXCP_NONE; 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Mon, 03 Jul 2023 11:33:12 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Beraldo Leal , Wainer dos Santos Moschetta , Alistair Francis , Daniel Henrique Barboza , kvm@vger.kernel.org, qemu-riscv@nongnu.org, Bin Meng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Liu Zhiwei Subject: [RFC PATCH v2 13/16] target/riscv: Move TCG/sysemu-specific code to tcg/sysemu/cpu_helper.c Date: Mon, 3 Jul 2023 20:31:42 +0200 Message-Id: <20230703183145.24779-14-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230703183145.24779-1-philmd@linaro.org> References: <20230703183145.24779-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688409238937100002 Move TCG/sysemu-specific code and restrict the corresponding prototypes to TCG, adapting meson rules. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- RFC due to riscv_cpu_get_phys_page_debug() --- target/riscv/cpu.h | 15 +- target/riscv/cpu_helper.c | 745 -------------------------- target/riscv/tcg/sysemu/cpu_helper.c | 765 +++++++++++++++++++++++++++ target/riscv/tcg/tcg-stub.c | 6 + target/riscv/tcg/sysemu/meson.build | 1 + 5 files changed, 781 insertions(+), 751 deletions(-) create mode 100644 target/riscv/tcg/sysemu/cpu_helper.c diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f9754013a8..42bd7efe4c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -429,12 +429,6 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_u= long geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); -G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t reta= ddr); -bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); @@ -444,11 +438,20 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp); =20 #ifndef CONFIG_USER_ONLY void riscv_cpu_do_interrupt(CPUState *cpu); +#ifdef CONFIG_TCG +bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retad= dr); +G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t reta= ddr); +#endif /* CONFIG_TCG */ + hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e73cf56e5c..f1d0cd1e64 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -331,69 +331,6 @@ int riscv_cpu_vsirq_pending(CPURISCVState *env) irqs >> 1, env->hviprio); } =20 -static int riscv_cpu_local_irq_pending(CPURISCVState *env) -{ - int virq; - uint64_t irqs, pending, mie, hsie, vsie; - - /* Determine interrupt enable state of all privilege modes */ - if (env->virt_enabled) { - mie =3D 1; - hsie =3D 1; - vsie =3D (env->priv < PRV_S) || - (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_= SIE)); - } else { - mie =3D (env->priv < PRV_M) || - (env->priv =3D=3D PRV_M && get_field(env->mstatus, MSTATUS_M= IE)); - hsie =3D (env->priv < PRV_S) || - (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_= SIE)); - vsie =3D 0; - } - - /* Determine all pending interrupts */ - pending =3D riscv_cpu_all_pending(env); - - /* Check M-mode interrupts */ - irqs =3D pending & ~env->mideleg & -mie; - if (irqs) { - return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, - irqs, env->miprio); - } - - /* Check HS-mode interrupts */ - irqs =3D pending & env->mideleg & ~env->hideleg & -hsie; - if (irqs) { - return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, - irqs, env->siprio); - } - - /* Check VS-mode interrupts */ - irqs =3D pending & env->mideleg & env->hideleg & -vsie; - if (irqs) { - virq =3D riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, - irqs >> 1, env->hviprio); - return (virq <=3D 0) ? virq : virq + 1; - } - - /* Indicate no pending interrupt */ - return RISCV_EXCP_NONE; -} - -bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - if (interrupt_request & CPU_INTERRUPT_HARD) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - int interruptno =3D riscv_cpu_local_irq_pending(env); - if (interruptno >=3D 0) { - cs->exception_index =3D RISCV_EXCP_INT_FLAG | interruptno; - riscv_cpu_do_interrupt(cs); - return true; - } - } - return false; -} - /* Return true is floating point support is currently enabled */ bool riscv_cpu_fp_enabled(CPURISCVState *env) { @@ -609,688 +546,6 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ul= ong newpriv) env->load_res =3D -1; } =20 -/* - * get_physical_address_pmp - check PMP permission for this physical addre= ss - * - * Match the PMP region and check permission for this physical address and= it's - * TLB page. Returns 0 if the permission checking was successful - * - * @env: CPURISCVState - * @prot: The returned protection attributes - * @addr: The physical address to be checked permission - * @access_type: The type of MMU access - * @mode: Indicates current privilege level. - */ -static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr = addr, - int size, MMUAccessType access_type, - int mode) -{ - pmp_priv_t pmp_priv; - bool pmp_has_privs; - - if (!riscv_cpu_cfg(env)->pmp) { - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return TRANSLATE_SUCCESS; - } - - pmp_has_privs =3D pmp_hart_has_privs(env, addr, size, 1 << access_type, - &pmp_priv, mode); - if (!pmp_has_privs) { - *prot =3D 0; - return TRANSLATE_PMP_FAIL; - } - - *prot =3D pmp_priv_to_page_prot(pmp_priv); - - return TRANSLATE_SUCCESS; -} - -/* - * get_physical_address - get the physical address for this virtual address - * - * Do a page table walk to obtain the physical address corresponding to a - * virtual address. Returns 0 if the translation was successful - * - * Adapted from Spike's mmu_t::translate and mmu_t::walk - * - * @env: CPURISCVState - * @physical: This will be set to the calculated physical address - * @prot: The returned protection attributes - * @addr: The virtual address or guest physical address to be translated - * @fault_pte_addr: If not NULL, this will be set to fault pte address - * when a error occurs on pte address translation. - * This will already be shifted to match htval. - * @access_type: The type of MMU access - * @mmu_idx: Indicates current privilege level - * @first_stage: Are we in first stage translation? - * Second stage is used for hypervisor guest translation - * @two_stage: Are we going to perform two stage translation - * @is_debug: Is this access from a debugger or the monitor? - */ -static int get_physical_address(CPURISCVState *env, hwaddr *physical, - int *ret_prot, vaddr addr, - target_ulong *fault_pte_addr, - int access_type, int mmu_idx, - bool first_stage, bool two_stage, - bool is_debug) -{ - /* - * NOTE: the env->pc value visible here will not be - * correct, but the value visible to the exception handler - * (riscv_cpu_do_interrupt) is correct - */ - MemTxResult res; - MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; - int mode =3D mmuidx_priv(mmu_idx); - bool use_background =3D false; - hwaddr ppn; - int napot_bits =3D 0; - target_ulong napot_mask; - - /* - * Check if we should use the background registers for the two - * stage translation. We don't need to check if we actually need - * two stage translation as that happened before this function - * was called. Background registers will be used if the guest has - * forced a two stage translation to be on (in HS or M mode). - */ - if (!env->virt_enabled && two_stage) { - use_background =3D true; - } - - if (mode =3D=3D PRV_M || !riscv_cpu_cfg(env)->mmu) { - *physical =3D addr; - *ret_prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return TRANSLATE_SUCCESS; - } - - *ret_prot =3D 0; - - hwaddr base; - int levels, ptidxbits, ptesize, vm, widened; - - if (first_stage =3D=3D true) { - if (use_background) { - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - base =3D (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSH= IFT; - vm =3D get_field(env->vsatp, SATP32_MODE); - } else { - base =3D (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSH= IFT; - vm =3D get_field(env->vsatp, SATP64_MODE); - } - } else { - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - base =3D (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHI= FT; - vm =3D get_field(env->satp, SATP32_MODE); - } else { - base =3D (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHI= FT; - vm =3D get_field(env->satp, SATP64_MODE); - } - } - widened =3D 0; - } else { - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - base =3D (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; - vm =3D get_field(env->hgatp, SATP32_MODE); - } else { - base =3D (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; - vm =3D get_field(env->hgatp, SATP64_MODE); - } - widened =3D 2; - } - - switch (vm) { - case VM_1_10_SV32: - levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; - case VM_1_10_SV39: - levels =3D 3; ptidxbits =3D 9; ptesize =3D 8; break; - case VM_1_10_SV48: - levels =3D 4; ptidxbits =3D 9; ptesize =3D 8; break; - case VM_1_10_SV57: - levels =3D 5; ptidxbits =3D 9; ptesize =3D 8; break; - case VM_1_10_MBARE: - *physical =3D addr; - *ret_prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return TRANSLATE_SUCCESS; - default: - g_assert_not_reached(); - } - - CPUState *cs =3D env_cpu(env); - int va_bits =3D PGSHIFT + levels * ptidxbits + widened; - - if (first_stage =3D=3D true) { - target_ulong mask, masked_msbs; - - if (TARGET_LONG_BITS > (va_bits - 1)) { - mask =3D (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; - } else { - mask =3D 0; - } - masked_msbs =3D (addr >> (va_bits - 1)) & mask; - - if (masked_msbs !=3D 0 && masked_msbs !=3D mask) { - return TRANSLATE_FAIL; - } - } else { - if (vm !=3D VM_1_10_SV32 && addr >> va_bits !=3D 0) { - return TRANSLATE_FAIL; - } - } - - bool pbmte =3D env->menvcfg & MENVCFG_PBMTE; - bool hade =3D env->menvcfg & MENVCFG_HADE; - - if (first_stage && two_stage && env->virt_enabled) { - pbmte =3D pbmte && (env->henvcfg & HENVCFG_PBMTE); - hade =3D hade && (env->henvcfg & HENVCFG_HADE); - } - - int ptshift =3D (levels - 1) * ptidxbits; - target_ulong pte; - hwaddr pte_addr; - int i; - -#if !TCG_OVERSIZED_GUEST -restart: -#endif - for (i =3D 0; i < levels; i++, ptshift -=3D ptidxbits) { - target_ulong idx; - if (i =3D=3D 0) { - idx =3D (addr >> (PGSHIFT + ptshift)) & - ((1 << (ptidxbits + widened)) - 1); - } else { - idx =3D (addr >> (PGSHIFT + ptshift)) & - ((1 << ptidxbits) - 1); - } - - /* check that physical address of PTE is legal */ - - if (two_stage && first_stage) { - int vbase_prot; - hwaddr vbase; - - /* Do the second stage translation on the base PTE address. */ - int vbase_ret =3D get_physical_address(env, &vbase, &vbase_pro= t, - base, NULL, MMU_DATA_LOAD, - MMUIdx_U, false, true, - is_debug); - - if (vbase_ret !=3D TRANSLATE_SUCCESS) { - if (fault_pte_addr) { - *fault_pte_addr =3D (base + idx * ptesize) >> 2; - } - return TRANSLATE_G_STAGE_FAIL; - } - - pte_addr =3D vbase + idx * ptesize; - } else { - pte_addr =3D base + idx * ptesize; - } - - int pmp_prot; - int pmp_ret =3D get_physical_address_pmp(env, &pmp_prot, pte_addr, - sizeof(target_ulong), - MMU_DATA_LOAD, PRV_S); - if (pmp_ret !=3D TRANSLATE_SUCCESS) { - return TRANSLATE_PMP_FAIL; - } - - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - pte =3D address_space_ldl(cs->as, pte_addr, attrs, &res); - } else { - pte =3D address_space_ldq(cs->as, pte_addr, attrs, &res); - } - - if (res !=3D MEMTX_OK) { - return TRANSLATE_FAIL; - } - - if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { - ppn =3D pte >> PTE_PPN_SHIFT; - } else { - if (pte & PTE_RESERVED) { - return TRANSLATE_FAIL; - } - - if (!pbmte && (pte & PTE_PBMT)) { - return TRANSLATE_FAIL; - } - - if (!riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { - return TRANSLATE_FAIL; - } - - ppn =3D (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; - } - - if (!(pte & PTE_V)) { - /* Invalid PTE */ - return TRANSLATE_FAIL; - } - if (pte & (PTE_R | PTE_W | PTE_X)) { - goto leaf; - } - - /* Inner PTE, continue walking */ - if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { - return TRANSLATE_FAIL; - } - base =3D ppn << PGSHIFT; - } - - /* No leaf pte at any translation level. */ - return TRANSLATE_FAIL; - - leaf: - if (ppn & ((1ULL << ptshift) - 1)) { - /* Misaligned PPN */ - return TRANSLATE_FAIL; - } - if (!pbmte && (pte & PTE_PBMT)) { - /* Reserved without Svpbmt. */ - return TRANSLATE_FAIL; - } - - /* Check for reserved combinations of RWX flags. */ - switch (pte & (PTE_R | PTE_W | PTE_X)) { - case PTE_W: - case PTE_W | PTE_X: - return TRANSLATE_FAIL; - } - - int prot =3D 0; - if (pte & PTE_R) { - prot |=3D PAGE_READ; - } - if (pte & PTE_W) { - prot |=3D PAGE_WRITE; - } - if (pte & PTE_X) { - bool mxr; - - if (first_stage =3D=3D true) { - mxr =3D get_field(env->mstatus, MSTATUS_MXR); - } else { - mxr =3D get_field(env->vsstatus, MSTATUS_MXR); - } - if (mxr) { - prot |=3D PAGE_READ; - } - prot |=3D PAGE_EXEC; - } - - if (pte & PTE_U) { - if (mode !=3D PRV_U) { - if (!mmuidx_sum(mmu_idx)) { - return TRANSLATE_FAIL; - } - /* SUM allows only read+write, not execute. */ - prot &=3D PAGE_READ | PAGE_WRITE; - } - } else if (mode !=3D PRV_S) { - /* Supervisor PTE flags when not S mode */ - return TRANSLATE_FAIL; - } - - if (!((prot >> access_type) & 1)) { - /* Access check failed */ - return TRANSLATE_FAIL; - } - - /* If necessary, set accessed and dirty bits. */ - target_ulong updated_pte =3D pte | PTE_A | - (access_type =3D=3D MMU_DATA_STORE ? PTE_D : 0); - - /* Page table updates need to be atomic with MTTCG enabled */ - if (updated_pte !=3D pte && !is_debug) { - if (!hade) { - return TRANSLATE_FAIL; - } - - /* - * - if accessed or dirty bits need updating, and the PTE is - * in RAM, then we do so atomically with a compare and swap. - * - if the PTE is in IO space or ROM, then it can't be updated - * and we return TRANSLATE_FAIL. - * - if the PTE changed by the time we went to update it, then - * it is no longer valid and we must re-walk the page table. - */ - MemoryRegion *mr; - hwaddr l =3D sizeof(target_ulong), addr1; - mr =3D address_space_translate(cs->as, pte_addr, &addr1, &l, - false, MEMTXATTRS_UNSPECIFIED); - if (memory_region_is_ram(mr)) { - target_ulong *pte_pa =3D qemu_map_ram_ptr(mr->ram_block, addr1= ); -#if TCG_OVERSIZED_GUEST - /* - * MTTCG is not enabled on oversized TCG guests so - * page table updates do not need to be atomic - */ - *pte_pa =3D pte =3D updated_pte; -#else - target_ulong old_pte =3D qatomic_cmpxchg(pte_pa, pte, updated_= pte); - if (old_pte !=3D pte) { - goto restart; - } - pte =3D updated_pte; -#endif - } else { - /* - * Misconfigured PTE in ROM (AD bits are not preset) or - * PTE is in IO space and can't be updated atomically. - */ - return TRANSLATE_FAIL; - } - } - - /* For superpage mappings, make a fake leaf PTE for the TLB's benefit.= */ - target_ulong vpn =3D addr >> PGSHIFT; - - if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { - napot_bits =3D ctzl(ppn) + 1; - if ((i !=3D (levels - 1)) || (napot_bits !=3D 4)) { - return TRANSLATE_FAIL; - } - } - - napot_mask =3D (1 << napot_bits) - 1; - *physical =3D (((ppn & ~napot_mask) | (vpn & napot_mask) | - (vpn & (((target_ulong)1 << ptshift) - 1)) - ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); - - /* - * Remove write permission unless this is a store, or the page is - * already dirty, so that we TLB miss on later writes to update - * the dirty bit. - */ - if (access_type !=3D MMU_DATA_STORE && !(pte & PTE_D)) { - prot &=3D ~PAGE_WRITE; - } - *ret_prot =3D prot; - - return TRANSLATE_SUCCESS; -} - -static void raise_mmu_exception(CPURISCVState *env, target_ulong address, - MMUAccessType access_type, bool pmp_violat= ion, - bool first_stage, bool two_stage, - bool two_stage_indirect) -{ - CPUState *cs =3D env_cpu(env); - int page_fault_exceptions, vm; - uint64_t stap_mode; - - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - stap_mode =3D SATP32_MODE; - } else { - stap_mode =3D SATP64_MODE; - } - - if (first_stage) { - vm =3D get_field(env->satp, stap_mode); - } else { - vm =3D get_field(env->hgatp, stap_mode); - } - - page_fault_exceptions =3D vm !=3D VM_1_10_MBARE && !pmp_violation; - - switch (access_type) { - case MMU_INST_FETCH: - if (env->virt_enabled && !first_stage) { - cs->exception_index =3D RISCV_EXCP_INST_GUEST_PAGE_FAULT; - } else { - cs->exception_index =3D page_fault_exceptions ? - RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; - } - break; - case MMU_DATA_LOAD: - if (two_stage && !first_stage) { - cs->exception_index =3D RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; - } else { - cs->exception_index =3D page_fault_exceptions ? - RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; - } - break; - case MMU_DATA_STORE: - if (two_stage && !first_stage) { - cs->exception_index =3D RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAUL= T; - } else { - cs->exception_index =3D page_fault_exceptions ? - RISCV_EXCP_STORE_PAGE_FAULT : - RISCV_EXCP_STORE_AMO_ACCESS_FAULT; - } - break; - default: - g_assert_not_reached(); - } - env->badaddr =3D address; - env->two_stage_lookup =3D two_stage; - env->two_stage_indirect_lookup =3D two_stage_indirect; -} - -hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - hwaddr phys_addr; - int prot; - int mmu_idx =3D cpu_mmu_index(&cpu->env, false); - - if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_id= x, - true, env->virt_enabled, true)) { - return -1; - } - - if (env->virt_enabled) { - if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, - 0, mmu_idx, false, true, true)) { - return -1; - } - } - - return phys_addr & TARGET_PAGE_MASK; -} - -void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t retad= dr) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - - if (access_type =3D=3D MMU_DATA_STORE) { - cs->exception_index =3D RISCV_EXCP_STORE_AMO_ACCESS_FAULT; - } else if (access_type =3D=3D MMU_DATA_LOAD) { - cs->exception_index =3D RISCV_EXCP_LOAD_ACCESS_FAULT; - } else { - cs->exception_index =3D RISCV_EXCP_INST_ACCESS_FAULT; - } - - env->badaddr =3D addr; - env->two_stage_lookup =3D mmuidx_2stage(mmu_idx); - env->two_stage_indirect_lookup =3D false; - cpu_loop_exit_restore(cs, retaddr); -} - -void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - switch (access_type) { - case MMU_INST_FETCH: - cs->exception_index =3D RISCV_EXCP_INST_ADDR_MIS; - break; - case MMU_DATA_LOAD: - cs->exception_index =3D RISCV_EXCP_LOAD_ADDR_MIS; - break; - case MMU_DATA_STORE: - cs->exception_index =3D RISCV_EXCP_STORE_AMO_ADDR_MIS; - break; - default: - g_assert_not_reached(); - } - env->badaddr =3D addr; - env->two_stage_lookup =3D mmuidx_2stage(mmu_idx); - env->two_stage_indirect_lookup =3D false; - cpu_loop_exit_restore(cs, retaddr); -} - - -static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) -{ - enum riscv_pmu_event_idx pmu_event_type; - - switch (access_type) { - case MMU_INST_FETCH: - pmu_event_type =3D RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; - break; - case MMU_DATA_LOAD: - pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; - break; - case MMU_DATA_STORE: - pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; - break; - default: - return; - } - - riscv_pmu_incr_ctr(cpu, pmu_event_type); -} - -bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - vaddr im_address; - hwaddr pa =3D 0; - int prot, prot2, prot_pmp; - bool pmp_violation =3D false; - bool first_stage_error =3D true; - bool two_stage_lookup =3D mmuidx_2stage(mmu_idx); - bool two_stage_indirect_error =3D false; - int ret =3D TRANSLATE_FAIL; - int mode =3D mmu_idx; - /* default TLB page size */ - target_ulong tlb_size =3D TARGET_PAGE_SIZE; - - env->guest_phys_fault_addr =3D 0; - - qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", - __func__, address, access_type, mmu_idx); - - pmu_tlb_fill_incr_ctr(cpu, access_type); - if (two_stage_lookup) { - /* Two stage lookup */ - ret =3D get_physical_address(env, &pa, &prot, address, - &env->guest_phys_fault_addr, access_typ= e, - mmu_idx, true, true, false); - - /* - * A G-stage exception may be triggered during two state lookup. - * And the env->guest_phys_fault_addr has already been set in - * get_physical_address(). - */ - if (ret =3D=3D TRANSLATE_G_STAGE_FAIL) { - first_stage_error =3D false; - two_stage_indirect_error =3D true; - } - - qemu_log_mask(CPU_LOG_MMU, - "%s 1st-stage address=3D%" VADDR_PRIx " ret %d physi= cal " - HWADDR_FMT_plx " prot %d\n", - __func__, address, ret, pa, prot); - - if (ret =3D=3D TRANSLATE_SUCCESS) { - /* Second stage lookup */ - im_address =3D pa; - - ret =3D get_physical_address(env, &pa, &prot2, im_address, NUL= L, - access_type, MMUIdx_U, false, true, - false); - - qemu_log_mask(CPU_LOG_MMU, - "%s 2nd-stage address=3D%" VADDR_PRIx - " ret %d physical " - HWADDR_FMT_plx " prot %d\n", - __func__, im_address, ret, pa, prot2); - - prot &=3D prot2; - - if (ret =3D=3D TRANSLATE_SUCCESS) { - ret =3D get_physical_address_pmp(env, &prot_pmp, pa, - size, access_type, mode); - tlb_size =3D pmp_get_tlb_size(env, pa); - - qemu_log_mask(CPU_LOG_MMU, - "%s PMP address=3D" HWADDR_FMT_plx " ret %d = prot" - " %d tlb_size " TARGET_FMT_lu "\n", - __func__, pa, ret, prot_pmp, tlb_size); - - prot &=3D prot_pmp; - } - - if (ret !=3D TRANSLATE_SUCCESS) { - /* - * Guest physical address translation failed, this is a HS - * level exception - */ - first_stage_error =3D false; - env->guest_phys_fault_addr =3D (im_address | - (address & - (TARGET_PAGE_SIZE - 1))) >>= 2; - } - } - } else { - /* Single stage lookup */ - ret =3D get_physical_address(env, &pa, &prot, address, NULL, - access_type, mmu_idx, true, false, fals= e); - - qemu_log_mask(CPU_LOG_MMU, - "%s address=3D%" VADDR_PRIx " ret %d physical " - HWADDR_FMT_plx " prot %d\n", - __func__, address, ret, pa, prot); - - if (ret =3D=3D TRANSLATE_SUCCESS) { - ret =3D get_physical_address_pmp(env, &prot_pmp, pa, - size, access_type, mode); - tlb_size =3D pmp_get_tlb_size(env, pa); - - qemu_log_mask(CPU_LOG_MMU, - "%s PMP address=3D" HWADDR_FMT_plx " ret %d prot" - " %d tlb_size " TARGET_FMT_lu "\n", - __func__, pa, ret, prot_pmp, tlb_size); - - prot &=3D prot_pmp; - } - } - - if (ret =3D=3D TRANSLATE_PMP_FAIL) { - pmp_violation =3D true; - } - - if (ret =3D=3D TRANSLATE_SUCCESS) { - tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), - prot, mmu_idx, tlb_size); - return true; - } else if (probe) { - return false; - } else { - raise_mmu_exception(env, address, access_type, pmp_violation, - first_stage_error, two_stage_lookup, - two_stage_indirect_error); - cpu_loop_exit_restore(cs, retaddr); - } - - return true; -} - static target_ulong riscv_transformed_insn(CPURISCVState *env, target_ulong insn, target_ulong taddr) diff --git a/target/riscv/tcg/sysemu/cpu_helper.c b/target/riscv/tcg/sysemu= /cpu_helper.c new file mode 100644 index 0000000000..544f489872 --- /dev/null +++ b/target/riscv/tcg/sysemu/cpu_helper.c @@ -0,0 +1,765 @@ +/* + * RISC-V CPU system helpers (TCG specific) + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2017-2018 SiFive, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/main-loop.h" +#include "exec/exec-all.h" +#include "cpu.h" +#include "internals.h" +#include "sysemu/cpu-timers.h" +#include "sysemu/pmu.h" +#include "sysemu/instmap.h" +#include "semihosting/common-semi.h" +#include "trace.h" + + +static int riscv_cpu_local_irq_pending(CPURISCVState *env) +{ + int virq; + uint64_t irqs, pending, mie, hsie, vsie; + + /* Determine interrupt enable state of all privilege modes */ + if (env->virt_enabled) { + mie =3D 1; + hsie =3D 1; + vsie =3D (env->priv < PRV_S) || + (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_= SIE)); + } else { + mie =3D (env->priv < PRV_M) || + (env->priv =3D=3D PRV_M && get_field(env->mstatus, MSTATUS_M= IE)); + hsie =3D (env->priv < PRV_S) || + (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_= SIE)); + vsie =3D 0; + } + + /* Determine all pending interrupts */ + pending =3D riscv_cpu_all_pending(env); + + /* Check M-mode interrupts */ + irqs =3D pending & ~env->mideleg & -mie; + if (irqs) { + return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, + irqs, env->miprio); + } + + /* Check HS-mode interrupts */ + irqs =3D pending & env->mideleg & ~env->hideleg & -hsie; + if (irqs) { + return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, + irqs, env->siprio); + } + + /* Check VS-mode interrupts */ + irqs =3D pending & env->mideleg & env->hideleg & -vsie; + if (irqs) { + virq =3D riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, + irqs >> 1, env->hviprio); + return (virq <=3D 0) ? virq : virq + 1; + } + + /* Indicate no pending interrupt */ + return RISCV_EXCP_NONE; +} + +bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + int interruptno =3D riscv_cpu_local_irq_pending(env); + if (interruptno >=3D 0) { + cs->exception_index =3D RISCV_EXCP_INT_FLAG | interruptno; + riscv_cpu_do_interrupt(cs); + return true; + } + } + return false; +} + +/* + * get_physical_address_pmp - check PMP permission for this physical addre= ss + * + * Match the PMP region and check permission for this physical address and= it's + * TLB page. Returns 0 if the permission checking was successful + * + * @env: CPURISCVState + * @prot: The returned protection attributes + * @addr: The physical address to be checked permission + * @access_type: The type of MMU access + * @mode: Indicates current privilege level. + */ +static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr = addr, + int size, MMUAccessType access_type, + int mode) +{ + pmp_priv_t pmp_priv; + bool pmp_has_privs; + + if (!riscv_cpu_cfg(env)->pmp) { + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return TRANSLATE_SUCCESS; + } + + pmp_has_privs =3D pmp_hart_has_privs(env, addr, size, 1 << access_type, + &pmp_priv, mode); + if (!pmp_has_privs) { + *prot =3D 0; + return TRANSLATE_PMP_FAIL; + } + + *prot =3D pmp_priv_to_page_prot(pmp_priv); + + return TRANSLATE_SUCCESS; +} + +/* + * get_physical_address - get the physical address for this virtual address + * + * Do a page table walk to obtain the physical address corresponding to a + * virtual address. Returns 0 if the translation was successful + * + * Adapted from Spike's mmu_t::translate and mmu_t::walk + * + * @env: CPURISCVState + * @physical: This will be set to the calculated physical address + * @prot: The returned protection attributes + * @addr: The virtual address or guest physical address to be translated + * @fault_pte_addr: If not NULL, this will be set to fault pte address + * when a error occurs on pte address translation. + * This will already be shifted to match htval. + * @access_type: The type of MMU access + * @mmu_idx: Indicates current privilege level + * @first_stage: Are we in first stage translation? + * Second stage is used for hypervisor guest translation + * @two_stage: Are we going to perform two stage translation + * @is_debug: Is this access from a debugger or the monitor? + */ +static int get_physical_address(CPURISCVState *env, hwaddr *physical, + int *ret_prot, vaddr addr, + target_ulong *fault_pte_addr, + int access_type, int mmu_idx, + bool first_stage, bool two_stage, + bool is_debug) +{ + /* + * NOTE: the env->pc value visible here will not be + * correct, but the value visible to the exception handler + * (riscv_cpu_do_interrupt) is correct + */ + MemTxResult res; + MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; + int mode =3D mmuidx_priv(mmu_idx); + bool use_background =3D false; + hwaddr ppn; + int napot_bits =3D 0; + target_ulong napot_mask; + + /* + * Check if we should use the background registers for the two + * stage translation. We don't need to check if we actually need + * two stage translation as that happened before this function + * was called. Background registers will be used if the guest has + * forced a two stage translation to be on (in HS or M mode). + */ + if (!env->virt_enabled && two_stage) { + use_background =3D true; + } + + if (mode =3D=3D PRV_M || !riscv_cpu_cfg(env)->mmu) { + *physical =3D addr; + *ret_prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return TRANSLATE_SUCCESS; + } + + *ret_prot =3D 0; + + hwaddr base; + int levels, ptidxbits, ptesize, vm, widened; + + if (first_stage =3D=3D true) { + if (use_background) { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + base =3D (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSH= IFT; + vm =3D get_field(env->vsatp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSH= IFT; + vm =3D get_field(env->vsatp, SATP64_MODE); + } + } else { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + base =3D (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHI= FT; + vm =3D get_field(env->satp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHI= FT; + vm =3D get_field(env->satp, SATP64_MODE); + } + } + widened =3D 0; + } else { + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + base =3D (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT; + vm =3D get_field(env->hgatp, SATP32_MODE); + } else { + base =3D (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT; + vm =3D get_field(env->hgatp, SATP64_MODE); + } + widened =3D 2; + } + + switch (vm) { + case VM_1_10_SV32: + levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; + case VM_1_10_SV39: + levels =3D 3; ptidxbits =3D 9; ptesize =3D 8; break; + case VM_1_10_SV48: + levels =3D 4; ptidxbits =3D 9; ptesize =3D 8; break; + case VM_1_10_SV57: + levels =3D 5; ptidxbits =3D 9; ptesize =3D 8; break; + case VM_1_10_MBARE: + *physical =3D addr; + *ret_prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return TRANSLATE_SUCCESS; + default: + g_assert_not_reached(); + } + + CPUState *cs =3D env_cpu(env); + int va_bits =3D PGSHIFT + levels * ptidxbits + widened; + + if (first_stage =3D=3D true) { + target_ulong mask, masked_msbs; + + if (TARGET_LONG_BITS > (va_bits - 1)) { + mask =3D (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; + } else { + mask =3D 0; + } + masked_msbs =3D (addr >> (va_bits - 1)) & mask; + + if (masked_msbs !=3D 0 && masked_msbs !=3D mask) { + return TRANSLATE_FAIL; + } + } else { + if (vm !=3D VM_1_10_SV32 && addr >> va_bits !=3D 0) { + return TRANSLATE_FAIL; + } + } + + bool pbmte =3D env->menvcfg & MENVCFG_PBMTE; + bool hade =3D env->menvcfg & MENVCFG_HADE; + + if (first_stage && two_stage && env->virt_enabled) { + pbmte =3D pbmte && (env->henvcfg & HENVCFG_PBMTE); + hade =3D hade && (env->henvcfg & HENVCFG_HADE); + } + + int ptshift =3D (levels - 1) * ptidxbits; + target_ulong pte; + hwaddr pte_addr; + int i; + +#if !TCG_OVERSIZED_GUEST +restart: +#endif + for (i =3D 0; i < levels; i++, ptshift -=3D ptidxbits) { + target_ulong idx; + if (i =3D=3D 0) { + idx =3D (addr >> (PGSHIFT + ptshift)) & + ((1 << (ptidxbits + widened)) - 1); + } else { + idx =3D (addr >> (PGSHIFT + ptshift)) & + ((1 << ptidxbits) - 1); + } + + /* check that physical address of PTE is legal */ + + if (two_stage && first_stage) { + int vbase_prot; + hwaddr vbase; + + /* Do the second stage translation on the base PTE address. */ + int vbase_ret =3D get_physical_address(env, &vbase, &vbase_pro= t, + base, NULL, MMU_DATA_LOAD, + MMUIdx_U, false, true, + is_debug); + + if (vbase_ret !=3D TRANSLATE_SUCCESS) { + if (fault_pte_addr) { + *fault_pte_addr =3D (base + idx * ptesize) >> 2; + } + return TRANSLATE_G_STAGE_FAIL; + } + + pte_addr =3D vbase + idx * ptesize; + } else { + pte_addr =3D base + idx * ptesize; + } + + int pmp_prot; + int pmp_ret =3D get_physical_address_pmp(env, &pmp_prot, pte_addr, + sizeof(target_ulong), + MMU_DATA_LOAD, PRV_S); + if (pmp_ret !=3D TRANSLATE_SUCCESS) { + return TRANSLATE_PMP_FAIL; + } + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + pte =3D address_space_ldl(cs->as, pte_addr, attrs, &res); + } else { + pte =3D address_space_ldq(cs->as, pte_addr, attrs, &res); + } + + if (res !=3D MEMTX_OK) { + return TRANSLATE_FAIL; + } + + if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { + ppn =3D pte >> PTE_PPN_SHIFT; + } else { + if (pte & PTE_RESERVED) { + return TRANSLATE_FAIL; + } + + if (!pbmte && (pte & PTE_PBMT)) { + return TRANSLATE_FAIL; + } + + if (!riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { + return TRANSLATE_FAIL; + } + + ppn =3D (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; + } + + if (!(pte & PTE_V)) { + /* Invalid PTE */ + return TRANSLATE_FAIL; + } + if (pte & (PTE_R | PTE_W | PTE_X)) { + goto leaf; + } + + /* Inner PTE, continue walking */ + if (pte & (PTE_D | PTE_A | PTE_U | PTE_ATTR)) { + return TRANSLATE_FAIL; + } + base =3D ppn << PGSHIFT; + } + + /* No leaf pte at any translation level. */ + return TRANSLATE_FAIL; + + leaf: + if (ppn & ((1ULL << ptshift) - 1)) { + /* Misaligned PPN */ + return TRANSLATE_FAIL; + } + if (!pbmte && (pte & PTE_PBMT)) { + /* Reserved without Svpbmt. */ + return TRANSLATE_FAIL; + } + + /* Check for reserved combinations of RWX flags. */ + switch (pte & (PTE_R | PTE_W | PTE_X)) { + case PTE_W: + case PTE_W | PTE_X: + return TRANSLATE_FAIL; + } + + int prot =3D 0; + if (pte & PTE_R) { + prot |=3D PAGE_READ; + } + if (pte & PTE_W) { + prot |=3D PAGE_WRITE; + } + if (pte & PTE_X) { + bool mxr; + + if (first_stage =3D=3D true) { + mxr =3D get_field(env->mstatus, MSTATUS_MXR); + } else { + mxr =3D get_field(env->vsstatus, MSTATUS_MXR); + } + if (mxr) { + prot |=3D PAGE_READ; + } + prot |=3D PAGE_EXEC; + } + + if (pte & PTE_U) { + if (mode !=3D PRV_U) { + if (!mmuidx_sum(mmu_idx)) { + return TRANSLATE_FAIL; + } + /* SUM allows only read+write, not execute. */ + prot &=3D PAGE_READ | PAGE_WRITE; + } + } else if (mode !=3D PRV_S) { + /* Supervisor PTE flags when not S mode */ + return TRANSLATE_FAIL; + } + + if (!((prot >> access_type) & 1)) { + /* Access check failed */ + return TRANSLATE_FAIL; + } + + /* If necessary, set accessed and dirty bits. */ + target_ulong updated_pte =3D pte | PTE_A | + (access_type =3D=3D MMU_DATA_STORE ? PTE_D : 0); + + /* Page table updates need to be atomic with MTTCG enabled */ + if (updated_pte !=3D pte && !is_debug) { + if (!hade) { + return TRANSLATE_FAIL; + } + + /* + * - if accessed or dirty bits need updating, and the PTE is + * in RAM, then we do so atomically with a compare and swap. + * - if the PTE is in IO space or ROM, then it can't be updated + * and we return TRANSLATE_FAIL. + * - if the PTE changed by the time we went to update it, then + * it is no longer valid and we must re-walk the page table. + */ + MemoryRegion *mr; + hwaddr l =3D sizeof(target_ulong), addr1; + mr =3D address_space_translate(cs->as, pte_addr, &addr1, &l, + false, MEMTXATTRS_UNSPECIFIED); + if (memory_region_is_ram(mr)) { + target_ulong *pte_pa =3D qemu_map_ram_ptr(mr->ram_block, addr1= ); +#if TCG_OVERSIZED_GUEST + /* + * MTTCG is not enabled on oversized TCG guests so + * page table updates do not need to be atomic + */ + *pte_pa =3D pte =3D updated_pte; +#else + target_ulong old_pte =3D qatomic_cmpxchg(pte_pa, pte, updated_= pte); + if (old_pte !=3D pte) { + goto restart; + } + pte =3D updated_pte; +#endif + } else { + /* + * Misconfigured PTE in ROM (AD bits are not preset) or + * PTE is in IO space and can't be updated atomically. + */ + return TRANSLATE_FAIL; + } + } + + /* For superpage mappings, make a fake leaf PTE for the TLB's benefit.= */ + target_ulong vpn =3D addr >> PGSHIFT; + + if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { + napot_bits =3D ctzl(ppn) + 1; + if ((i !=3D (levels - 1)) || (napot_bits !=3D 4)) { + return TRANSLATE_FAIL; + } + } + + napot_mask =3D (1 << napot_bits) - 1; + *physical =3D (((ppn & ~napot_mask) | (vpn & napot_mask) | + (vpn & (((target_ulong)1 << ptshift) - 1)) + ) << PGSHIFT) | (addr & ~TARGET_PAGE_MASK); + + /* + * Remove write permission unless this is a store, or the page is + * already dirty, so that we TLB miss on later writes to update + * the dirty bit. + */ + if (access_type !=3D MMU_DATA_STORE && !(pte & PTE_D)) { + prot &=3D ~PAGE_WRITE; + } + *ret_prot =3D prot; + + return TRANSLATE_SUCCESS; +} + +static void raise_mmu_exception(CPURISCVState *env, target_ulong address, + MMUAccessType access_type, bool pmp_violat= ion, + bool first_stage, bool two_stage, + bool two_stage_indirect) +{ + CPUState *cs =3D env_cpu(env); + int page_fault_exceptions, vm; + uint64_t stap_mode; + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + stap_mode =3D SATP32_MODE; + } else { + stap_mode =3D SATP64_MODE; + } + + if (first_stage) { + vm =3D get_field(env->satp, stap_mode); + } else { + vm =3D get_field(env->hgatp, stap_mode); + } + + page_fault_exceptions =3D vm !=3D VM_1_10_MBARE && !pmp_violation; + + switch (access_type) { + case MMU_INST_FETCH: + if (env->virt_enabled && !first_stage) { + cs->exception_index =3D RISCV_EXCP_INST_GUEST_PAGE_FAULT; + } else { + cs->exception_index =3D page_fault_exceptions ? + RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; + } + break; + case MMU_DATA_LOAD: + if (two_stage && !first_stage) { + cs->exception_index =3D RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; + } else { + cs->exception_index =3D page_fault_exceptions ? + RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; + } + break; + case MMU_DATA_STORE: + if (two_stage && !first_stage) { + cs->exception_index =3D RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAUL= T; + } else { + cs->exception_index =3D page_fault_exceptions ? + RISCV_EXCP_STORE_PAGE_FAULT : + RISCV_EXCP_STORE_AMO_ACCESS_FAULT; + } + break; + default: + g_assert_not_reached(); + } + env->badaddr =3D address; + env->two_stage_lookup =3D two_stage; + env->two_stage_indirect_lookup =3D two_stage_indirect; +} + +hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + hwaddr phys_addr; + int prot; + int mmu_idx =3D cpu_mmu_index(&cpu->env, false); + + if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_id= x, + true, env->virt_enabled, true)) { + return -1; + } + + if (env->virt_enabled) { + if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL, + 0, mmu_idx, false, true, true)) { + return -1; + } + } + + return phys_addr & TARGET_PAGE_MASK; +} + +void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retad= dr) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + + if (access_type =3D=3D MMU_DATA_STORE) { + cs->exception_index =3D RISCV_EXCP_STORE_AMO_ACCESS_FAULT; + } else if (access_type =3D=3D MMU_DATA_LOAD) { + cs->exception_index =3D RISCV_EXCP_LOAD_ACCESS_FAULT; + } else { + cs->exception_index =3D RISCV_EXCP_INST_ACCESS_FAULT; + } + + env->badaddr =3D addr; + env->two_stage_lookup =3D mmuidx_2stage(mmu_idx); + env->two_stage_indirect_lookup =3D false; + cpu_loop_exit_restore(cs, retaddr); +} + +void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + switch (access_type) { + case MMU_INST_FETCH: + cs->exception_index =3D RISCV_EXCP_INST_ADDR_MIS; + break; + case MMU_DATA_LOAD: + cs->exception_index =3D RISCV_EXCP_LOAD_ADDR_MIS; + break; + case MMU_DATA_STORE: + cs->exception_index =3D RISCV_EXCP_STORE_AMO_ADDR_MIS; + break; + default: + g_assert_not_reached(); + } + env->badaddr =3D addr; + env->two_stage_lookup =3D mmuidx_2stage(mmu_idx); + env->two_stage_indirect_lookup =3D false; + cpu_loop_exit_restore(cs, retaddr); +} + +static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) +{ + enum riscv_pmu_event_idx pmu_event_type; + + switch (access_type) { + case MMU_INST_FETCH: + pmu_event_type =3D RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; + break; + case MMU_DATA_LOAD: + pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; + break; + case MMU_DATA_STORE: + pmu_event_type =3D RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; + break; + default: + return; + } + + riscv_pmu_incr_ctr(cpu, pmu_event_type); +} + +bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + vaddr im_address; + hwaddr pa =3D 0; + int prot, prot2, prot_pmp; + bool pmp_violation =3D false; + bool first_stage_error =3D true; + bool two_stage_lookup =3D mmuidx_2stage(mmu_idx); + bool two_stage_indirect_error =3D false; + int ret =3D TRANSLATE_FAIL; + int mode =3D mmu_idx; + /* default TLB page size */ + target_ulong tlb_size =3D TARGET_PAGE_SIZE; + + env->guest_phys_fault_addr =3D 0; + + qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", + __func__, address, access_type, mmu_idx); + + pmu_tlb_fill_incr_ctr(cpu, access_type); + if (two_stage_lookup) { + /* Two stage lookup */ + ret =3D get_physical_address(env, &pa, &prot, address, + &env->guest_phys_fault_addr, access_typ= e, + mmu_idx, true, true, false); + + /* + * A G-stage exception may be triggered during two state lookup. + * And the env->guest_phys_fault_addr has already been set in + * get_physical_address(). + */ + if (ret =3D=3D TRANSLATE_G_STAGE_FAIL) { + first_stage_error =3D false; + two_stage_indirect_error =3D true; + } + + qemu_log_mask(CPU_LOG_MMU, + "%s 1st-stage address=3D%" VADDR_PRIx " ret %d physi= cal " + HWADDR_FMT_plx " prot %d\n", + __func__, address, ret, pa, prot); + + if (ret =3D=3D TRANSLATE_SUCCESS) { + /* Second stage lookup */ + im_address =3D pa; + + ret =3D get_physical_address(env, &pa, &prot2, im_address, NUL= L, + access_type, MMUIdx_U, false, true, + false); + + qemu_log_mask(CPU_LOG_MMU, + "%s 2nd-stage address=3D%" VADDR_PRIx + " ret %d physical " + HWADDR_FMT_plx " prot %d\n", + __func__, im_address, ret, pa, prot2); + + prot &=3D prot2; + + if (ret =3D=3D TRANSLATE_SUCCESS) { + ret =3D get_physical_address_pmp(env, &prot_pmp, pa, + size, access_type, mode); + tlb_size =3D pmp_get_tlb_size(env, pa); + + qemu_log_mask(CPU_LOG_MMU, + "%s PMP address=3D" HWADDR_FMT_plx " ret %d = prot" + " %d tlb_size " TARGET_FMT_lu "\n", + __func__, pa, ret, prot_pmp, tlb_size); + + prot &=3D prot_pmp; + } + + if (ret !=3D TRANSLATE_SUCCESS) { + /* + * Guest physical address translation failed, this is a HS + * level exception + */ + first_stage_error =3D false; + env->guest_phys_fault_addr =3D (im_address | + (address & + (TARGET_PAGE_SIZE - 1))) >>= 2; + } + } + } else { + /* Single stage lookup */ + ret =3D get_physical_address(env, &pa, &prot, address, NULL, + access_type, mmu_idx, true, false, fals= e); + + qemu_log_mask(CPU_LOG_MMU, + "%s address=3D%" VADDR_PRIx " ret %d physical " + HWADDR_FMT_plx " prot %d\n", + __func__, address, ret, pa, prot); + + if (ret =3D=3D TRANSLATE_SUCCESS) { + ret =3D get_physical_address_pmp(env, &prot_pmp, pa, + size, access_type, mode); + tlb_size =3D pmp_get_tlb_size(env, pa); + + qemu_log_mask(CPU_LOG_MMU, + "%s PMP address=3D" HWADDR_FMT_plx " ret %d prot" + " %d tlb_size " TARGET_FMT_lu "\n", + __func__, pa, ret, prot_pmp, tlb_size); + + prot &=3D prot_pmp; + } + } + + if (ret =3D=3D TRANSLATE_PMP_FAIL) { + pmp_violation =3D true; + } + + if (ret =3D=3D TRANSLATE_SUCCESS) { + tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), + prot, mmu_idx, tlb_size); + return true; + } else if (probe) { + return false; + } else { + raise_mmu_exception(env, address, access_type, pmp_violation, + first_stage_error, two_stage_lookup, + two_stage_indirect_error); + cpu_loop_exit_restore(cs, retaddr); + } + + return true; +} diff --git a/target/riscv/tcg/tcg-stub.c b/target/riscv/tcg/tcg-stub.c index dfe42ae2ac..e329d25355 100644 --- a/target/riscv/tcg/tcg-stub.c +++ b/target/riscv/tcg/tcg-stub.c @@ -23,3 +23,9 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env, { g_assert_not_reached(); } + +hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + /* XXX too many TCG code in the real riscv_cpu_get_phys_page_debug() */ + return -1; +} diff --git a/target/riscv/tcg/sysemu/meson.build b/target/riscv/tcg/sysemu/= meson.build index e8e61e5784..a549e497ce 100644 --- a/target/riscv/tcg/sysemu/meson.build +++ b/target/riscv/tcg/sysemu/meson.build @@ -1,3 +1,4 @@ riscv_system_ss.add(when: 'CONFIG_TCG', if_true: files( + 'cpu_helper.c', 'debug.c', )) --=20 2.38.1 From nobody Tue May 14 09:30:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 03 Jul 2023 11:33:21 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Beraldo Leal , Wainer dos Santos Moschetta , Alistair Francis , Daniel Henrique Barboza , kvm@vger.kernel.org, qemu-riscv@nongnu.org, Bin Meng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Liu Zhiwei Subject: [PATCH v2 14/16] target/riscv: Move sysemu-specific code to sysemu/cpu_helper.c Date: Mon, 3 Jul 2023 20:31:43 +0200 Message-Id: <20230703183145.24779-15-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230703183145.24779-1-philmd@linaro.org> References: <20230703183145.24779-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688409368020100003 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu_helper.c | 858 +----------------------------- target/riscv/sysemu/cpu_helper.c | 863 +++++++++++++++++++++++++++++++ target/riscv/sysemu/meson.build | 1 + 3 files changed, 865 insertions(+), 857 deletions(-) create mode 100644 target/riscv/sysemu/cpu_helper.c diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f1d0cd1e64..900e3c2b5c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -18,22 +18,12 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/log.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "internals.h" -#include "sysemu/pmu.h" -#include "exec/exec-all.h" -#include "sysemu/instmap.h" -#include "tcg/tcg-op.h" -#include "trace.h" -#include "semihosting/common-semi.h" #ifndef CONFIG_USER_ONLY #include "sysemu/cpu-timers.h" #endif -#include "cpu_bits.h" -#include "sysemu/debug.h" -#include "tcg/oversized-guest.h" + =20 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { @@ -108,849 +98,3 @@ void riscv_cpu_update_mask(CPURISCVState *env) env->cur_pmbase =3D base; } } - -#ifndef CONFIG_USER_ONLY - -/* - * The HS-mode is allowed to configure priority only for the - * following VS-mode local interrupts: - * - * 0 (Reserved interrupt, reads as zero) - * 1 Supervisor software interrupt - * 4 (Reserved interrupt, reads as zero) - * 5 Supervisor timer interrupt - * 8 (Reserved interrupt, reads as zero) - * 13 (Reserved interrupt) - * 14 " - * 15 " - * 16 " - * 17 " - * 18 " - * 19 " - * 20 " - * 21 " - * 22 " - * 23 " - */ - -static const int hviprio_index2irq[] =3D { - 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; -static const int hviprio_index2rdzero[] =3D { - 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; - -int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) -{ - if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <=3D index) { - return -EINVAL; - } - - if (out_irq) { - *out_irq =3D hviprio_index2irq[index]; - } - - if (out_rdzero) { - *out_rdzero =3D hviprio_index2rdzero[index]; - } - - return 0; -} - -/* - * Default priorities of local interrupts are defined in the - * RISC-V Advanced Interrupt Architecture specification. - * - * ---------------------------------------------------------------- - * Default | - * Priority | Major Interrupt Numbers - * ---------------------------------------------------------------- - * Highest | 47, 23, 46, 45, 22, 44, - * | 43, 21, 42, 41, 20, 40 - * | - * | 11 (0b), 3 (03), 7 (07) - * | 9 (09), 1 (01), 5 (05) - * | 12 (0c) - * | 10 (0a), 2 (02), 6 (06) - * | - * | 39, 19, 38, 37, 18, 36, - * Lowest | 35, 17, 34, 33, 16, 32 - * ---------------------------------------------------------------- - */ -static const uint8_t default_iprio[64] =3D { - /* Custom interrupts 48 to 63 */ - [63] =3D IPRIO_MMAXIPRIO, - [62] =3D IPRIO_MMAXIPRIO, - [61] =3D IPRIO_MMAXIPRIO, - [60] =3D IPRIO_MMAXIPRIO, - [59] =3D IPRIO_MMAXIPRIO, - [58] =3D IPRIO_MMAXIPRIO, - [57] =3D IPRIO_MMAXIPRIO, - [56] =3D IPRIO_MMAXIPRIO, - [55] =3D IPRIO_MMAXIPRIO, - [54] =3D IPRIO_MMAXIPRIO, - [53] =3D IPRIO_MMAXIPRIO, - [52] =3D IPRIO_MMAXIPRIO, - [51] =3D IPRIO_MMAXIPRIO, - [50] =3D IPRIO_MMAXIPRIO, - [49] =3D IPRIO_MMAXIPRIO, - [48] =3D IPRIO_MMAXIPRIO, - - /* Custom interrupts 24 to 31 */ - [31] =3D IPRIO_MMAXIPRIO, - [30] =3D IPRIO_MMAXIPRIO, - [29] =3D IPRIO_MMAXIPRIO, - [28] =3D IPRIO_MMAXIPRIO, - [27] =3D IPRIO_MMAXIPRIO, - [26] =3D IPRIO_MMAXIPRIO, - [25] =3D IPRIO_MMAXIPRIO, - [24] =3D IPRIO_MMAXIPRIO, - - [47] =3D IPRIO_DEFAULT_UPPER, - [23] =3D IPRIO_DEFAULT_UPPER + 1, - [46] =3D IPRIO_DEFAULT_UPPER + 2, - [45] =3D IPRIO_DEFAULT_UPPER + 3, - [22] =3D IPRIO_DEFAULT_UPPER + 4, - [44] =3D IPRIO_DEFAULT_UPPER + 5, - - [43] =3D IPRIO_DEFAULT_UPPER + 6, - [21] =3D IPRIO_DEFAULT_UPPER + 7, - [42] =3D IPRIO_DEFAULT_UPPER + 8, - [41] =3D IPRIO_DEFAULT_UPPER + 9, - [20] =3D IPRIO_DEFAULT_UPPER + 10, - [40] =3D IPRIO_DEFAULT_UPPER + 11, - - [11] =3D IPRIO_DEFAULT_M, - [3] =3D IPRIO_DEFAULT_M + 1, - [7] =3D IPRIO_DEFAULT_M + 2, - - [9] =3D IPRIO_DEFAULT_S, - [1] =3D IPRIO_DEFAULT_S + 1, - [5] =3D IPRIO_DEFAULT_S + 2, - - [12] =3D IPRIO_DEFAULT_SGEXT, - - [10] =3D IPRIO_DEFAULT_VS, - [2] =3D IPRIO_DEFAULT_VS + 1, - [6] =3D IPRIO_DEFAULT_VS + 2, - - [39] =3D IPRIO_DEFAULT_LOWER, - [19] =3D IPRIO_DEFAULT_LOWER + 1, - [38] =3D IPRIO_DEFAULT_LOWER + 2, - [37] =3D IPRIO_DEFAULT_LOWER + 3, - [18] =3D IPRIO_DEFAULT_LOWER + 4, - [36] =3D IPRIO_DEFAULT_LOWER + 5, - - [35] =3D IPRIO_DEFAULT_LOWER + 6, - [17] =3D IPRIO_DEFAULT_LOWER + 7, - [34] =3D IPRIO_DEFAULT_LOWER + 8, - [33] =3D IPRIO_DEFAULT_LOWER + 9, - [16] =3D IPRIO_DEFAULT_LOWER + 10, - [32] =3D IPRIO_DEFAULT_LOWER + 11, -}; - -uint8_t riscv_cpu_default_priority(int irq) -{ - if (irq < 0 || irq > 63) { - return IPRIO_MMAXIPRIO; - } - - return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; -}; - -int riscv_cpu_pending_to_irq(CPURISCVState *env, - int extirq, unsigned int extirq_def_prio, - uint64_t pending, uint8_t *iprio) -{ - int irq, best_irq =3D RISCV_EXCP_NONE; - unsigned int prio, best_prio =3D UINT_MAX; - - if (!pending) { - return RISCV_EXCP_NONE; - } - - irq =3D ctz64(pending); - if (!((extirq =3D=3D IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : - riscv_cpu_cfg(env)->ext_ssaia)) { - return irq; - } - - pending =3D pending >> irq; - while (pending) { - prio =3D iprio[irq]; - if (!prio) { - if (irq =3D=3D extirq) { - prio =3D extirq_def_prio; - } else { - prio =3D (riscv_cpu_default_priority(irq) < extirq_def_pri= o) ? - 1 : IPRIO_MMAXIPRIO; - } - } - if ((pending & 0x1) && (prio <=3D best_prio)) { - best_irq =3D irq; - best_prio =3D prio; - } - irq++; - pending =3D pending >> 1; - } - - return best_irq; -} - -uint64_t riscv_cpu_all_pending(CPURISCVState *env) -{ - uint32_t gein =3D get_field(env->hstatus, HSTATUS_VGEIN); - uint64_t vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; - uint64_t vstip =3D (env->vstime_irq) ? MIP_VSTIP : 0; - - return (env->mip | vsgein | vstip) & env->mie; -} - -int riscv_cpu_mirq_pending(CPURISCVState *env) -{ - uint64_t irqs =3D riscv_cpu_all_pending(env) & ~env->mideleg & - ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); - - return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, - irqs, env->miprio); -} - -int riscv_cpu_sirq_pending(CPURISCVState *env) -{ - uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & - ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); - - return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, - irqs, env->siprio); -} - -int riscv_cpu_vsirq_pending(CPURISCVState *env) -{ - uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); - - return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, - irqs >> 1, env->hviprio); -} - -/* Return true is floating point support is currently enabled */ -bool riscv_cpu_fp_enabled(CPURISCVState *env) -{ - if (env->mstatus & MSTATUS_FS) { - if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { - return false; - } - return true; - } - - return false; -} - -/* Return true is vector support is currently enabled */ -bool riscv_cpu_vector_enabled(CPURISCVState *env) -{ - if (env->mstatus & MSTATUS_VS) { - if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { - return false; - } - return true; - } - - return false; -} - -void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) -{ - uint64_t mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | - MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | - MSTATUS64_UXL | MSTATUS_VS; - - if (riscv_has_ext(env, RVF)) { - mstatus_mask |=3D MSTATUS_FS; - } - bool current_virt =3D env->virt_enabled; - - g_assert(riscv_has_ext(env, RVH)); - - if (current_virt) { - /* Current V=3D1 and we are about to change to V=3D0 */ - env->vsstatus =3D env->mstatus & mstatus_mask; - env->mstatus &=3D ~mstatus_mask; - env->mstatus |=3D env->mstatus_hs; - - env->vstvec =3D env->stvec; - env->stvec =3D env->stvec_hs; - - env->vsscratch =3D env->sscratch; - env->sscratch =3D env->sscratch_hs; - - env->vsepc =3D env->sepc; - env->sepc =3D env->sepc_hs; - - env->vscause =3D env->scause; - env->scause =3D env->scause_hs; - - env->vstval =3D env->stval; - env->stval =3D env->stval_hs; - - env->vsatp =3D env->satp; - env->satp =3D env->satp_hs; - } else { - /* Current V=3D0 and we are about to change to V=3D1 */ - env->mstatus_hs =3D env->mstatus & mstatus_mask; - env->mstatus &=3D ~mstatus_mask; - env->mstatus |=3D env->vsstatus; - - env->stvec_hs =3D env->stvec; - env->stvec =3D env->vstvec; - - env->sscratch_hs =3D env->sscratch; - env->sscratch =3D env->vsscratch; - - env->sepc_hs =3D env->sepc; - env->sepc =3D env->vsepc; - - env->scause_hs =3D env->scause; - env->scause =3D env->vscause; - - env->stval_hs =3D env->stval; - env->stval =3D env->vstval; - - env->satp_hs =3D env->satp; - env->satp =3D env->vsatp; - } -} - -target_ulong riscv_cpu_get_geilen(CPURISCVState *env) -{ - if (!riscv_has_ext(env, RVH)) { - return 0; - } - - return env->geilen; -} - -void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) -{ - if (!riscv_has_ext(env, RVH)) { - return; - } - - if (geilen > (TARGET_LONG_BITS - 1)) { - return; - } - - env->geilen =3D geilen; -} - -/* This function can only be called to set virt when RVH is enabled */ -void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) -{ - /* Flush the TLB on all virt mode changes. */ - if (env->virt_enabled !=3D enable) { - tlb_flush(env_cpu(env)); - } - - env->virt_enabled =3D enable; - - if (enable) { - /* - * The guest external interrupts from an interrupt controller are - * delivered only when the Guest/VM is running (i.e. V=3D1). This = means - * any guest external interrupt which is triggered while the Guest= /VM - * is not running (i.e. V=3D0) will be missed on QEMU resulting in= guest - * with sluggish response to serial console input and other I/O ev= ents. - * - * To solve this, we check and inject interrupt after setting V=3D= 1. - */ - riscv_cpu_update_mip(env, 0, 0); - } -} - -int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) -{ - CPURISCVState *env =3D &cpu->env; - if (env->miclaim & interrupts) { - return -1; - } else { - env->miclaim |=3D interrupts; - return 0; - } -} - -uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - uint64_t gein, vsgein =3D 0, vstip =3D 0, old =3D env->mip; - - if (env->virt_enabled) { - gein =3D get_field(env->hstatus, HSTATUS_VGEIN); - vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; - } - - vstip =3D env->vstime_irq ? MIP_VSTIP : 0; - - QEMU_IOTHREAD_LOCK_GUARD(); - - env->mip =3D (env->mip & ~mask) | (value & mask); - - if (env->mip | vsgein | vstip) { - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } - - return old; -} - -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), - void *arg) -{ - env->rdtime_fn =3D fn; - env->rdtime_fn_arg =3D arg; -} - -void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, - int (*rmw_fn)(void *arg, - target_ulong reg, - target_ulong *val, - target_ulong new_val, - target_ulong write_mask), - void *rmw_fn_arg) -{ - if (priv <=3D PRV_M) { - env->aia_ireg_rmw_fn[priv] =3D rmw_fn; - env->aia_ireg_rmw_fn_arg[priv] =3D rmw_fn_arg; - } -} - -void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) -{ - g_assert(newpriv <=3D PRV_M && newpriv !=3D PRV_RESERVED); - - if (icount_enabled() && newpriv !=3D env->priv) { - riscv_itrigger_update_priv(env); - } - /* tlb_flush is unnecessary as mode is contained in mmu_idx */ - env->priv =3D newpriv; - env->xl =3D cpu_recompute_xl(env); - riscv_cpu_update_mask(env); - - /* - * Clear the load reservation - otherwise a reservation placed in one - * context/process can be used by another, resulting in an SC succeedi= ng - * incorrectly. Version 2.2 of the ISA specification explicitly requir= es - * this behaviour, while later revisions say that the kernel "should" = use - * an SC instruction to force the yielding of a load reservation on a - * preemptive context switch. As a result, do both. - */ - env->load_res =3D -1; -} - -static target_ulong riscv_transformed_insn(CPURISCVState *env, - target_ulong insn, - target_ulong taddr) -{ - target_ulong xinsn =3D 0; - target_ulong access_rs1 =3D 0, access_imm =3D 0, access_size =3D 0; - - /* - * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to - * be uncompressed. The Quadrant 1 of RVC instruction space need - * not be transformed because these instructions won't generate - * any load/store trap. - */ - - if ((insn & 0x3) !=3D 0x3) { - /* Transform 16bit instruction into 32bit instruction */ - switch (GET_C_OP(insn)) { - case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ - switch (GET_C_FUNC(insn)) { - case OPC_RISC_C_FUNC_FLD_LQ: - if (riscv_cpu_xlen(env) !=3D 128) { /* C.FLD (RV32/64) */ - xinsn =3D OPC_RISC_FLD; - xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); - access_rs1 =3D GET_C_RS1S(insn); - access_imm =3D GET_C_LD_IMM(insn); - access_size =3D 8; - } - break; - case OPC_RISC_C_FUNC_LW: /* C.LW */ - xinsn =3D OPC_RISC_LW; - xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); - access_rs1 =3D GET_C_RS1S(insn); - access_imm =3D GET_C_LW_IMM(insn); - access_size =3D 4; - break; - case OPC_RISC_C_FUNC_FLW_LD: - if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FLW (RV32) */ - xinsn =3D OPC_RISC_FLW; - xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); - access_rs1 =3D GET_C_RS1S(insn); - access_imm =3D GET_C_LW_IMM(insn); - access_size =3D 4; - } else { /* C.LD (RV64/RV128) */ - xinsn =3D OPC_RISC_LD; - xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); - access_rs1 =3D GET_C_RS1S(insn); - access_imm =3D GET_C_LD_IMM(insn); - access_size =3D 8; - } - break; - case OPC_RISC_C_FUNC_FSD_SQ: - if (riscv_cpu_xlen(env) !=3D 128) { /* C.FSD (RV32/64) */ - xinsn =3D OPC_RISC_FSD; - xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); - access_rs1 =3D GET_C_RS1S(insn); - access_imm =3D GET_C_SD_IMM(insn); - access_size =3D 8; - } - break; - case OPC_RISC_C_FUNC_SW: /* C.SW */ - xinsn =3D OPC_RISC_SW; - xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); - access_rs1 =3D GET_C_RS1S(insn); - access_imm =3D GET_C_SW_IMM(insn); - access_size =3D 4; - break; - case OPC_RISC_C_FUNC_FSW_SD: - if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FSW (RV32) */ - xinsn =3D OPC_RISC_FSW; - xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); - access_rs1 =3D GET_C_RS1S(insn); - access_imm =3D GET_C_SW_IMM(insn); - access_size =3D 4; - } else { /* C.SD (RV64/RV128) */ - xinsn =3D OPC_RISC_SD; - xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); - access_rs1 =3D GET_C_RS1S(insn); - access_imm =3D GET_C_SD_IMM(insn); - access_size =3D 8; - } - break; - default: - break; - } - break; - case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ - switch (GET_C_FUNC(insn)) { - case OPC_RISC_C_FUNC_FLDSP_LQSP: - if (riscv_cpu_xlen(env) !=3D 128) { /* C.FLDSP (RV32/64) */ - xinsn =3D OPC_RISC_FLD; - xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); - access_rs1 =3D 2; - access_imm =3D GET_C_LDSP_IMM(insn); - access_size =3D 8; - } - break; - case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ - xinsn =3D OPC_RISC_LW; - xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); - access_rs1 =3D 2; - access_imm =3D GET_C_LWSP_IMM(insn); - access_size =3D 4; - break; - case OPC_RISC_C_FUNC_FLWSP_LDSP: - if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FLWSP (RV32) */ - xinsn =3D OPC_RISC_FLW; - xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); - access_rs1 =3D 2; - access_imm =3D GET_C_LWSP_IMM(insn); - access_size =3D 4; - } else { /* C.LDSP (RV64/RV128) */ - xinsn =3D OPC_RISC_LD; - xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); - access_rs1 =3D 2; - access_imm =3D GET_C_LDSP_IMM(insn); - access_size =3D 8; - } - break; - case OPC_RISC_C_FUNC_FSDSP_SQSP: - if (riscv_cpu_xlen(env) !=3D 128) { /* C.FSDSP (RV32/64) */ - xinsn =3D OPC_RISC_FSD; - xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); - access_rs1 =3D 2; - access_imm =3D GET_C_SDSP_IMM(insn); - access_size =3D 8; - } - break; - case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ - xinsn =3D OPC_RISC_SW; - xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); - access_rs1 =3D 2; - access_imm =3D GET_C_SWSP_IMM(insn); - access_size =3D 4; - break; - case 7: - if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FSWSP (RV32) */ - xinsn =3D OPC_RISC_FSW; - xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); - access_rs1 =3D 2; - access_imm =3D GET_C_SWSP_IMM(insn); - access_size =3D 4; - } else { /* C.SDSP (RV64/RV128) */ - xinsn =3D OPC_RISC_SD; - xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); - access_rs1 =3D 2; - access_imm =3D GET_C_SDSP_IMM(insn); - access_size =3D 8; - } - break; - default: - break; - } - break; - default: - break; - } - - /* - * Clear Bit1 of transformed instruction to indicate that - * original insruction was a 16bit instruction - */ - xinsn &=3D ~((target_ulong)0x2); - } else { - /* Transform 32bit (or wider) instructions */ - switch (MASK_OP_MAJOR(insn)) { - case OPC_RISC_ATOMIC: - xinsn =3D insn; - access_rs1 =3D GET_RS1(insn); - access_size =3D 1 << GET_FUNCT3(insn); - break; - case OPC_RISC_LOAD: - case OPC_RISC_FP_LOAD: - xinsn =3D SET_I_IMM(insn, 0); - access_rs1 =3D GET_RS1(insn); - access_imm =3D GET_IMM(insn); - access_size =3D 1 << GET_FUNCT3(insn); - break; - case OPC_RISC_STORE: - case OPC_RISC_FP_STORE: - xinsn =3D SET_S_IMM(insn, 0); - access_rs1 =3D GET_RS1(insn); - access_imm =3D GET_STORE_IMM(insn); - access_size =3D 1 << GET_FUNCT3(insn); - break; - case OPC_RISC_SYSTEM: - if (MASK_OP_SYSTEM(insn) =3D=3D OPC_RISC_HLVHSV) { - xinsn =3D insn; - access_rs1 =3D GET_RS1(insn); - access_size =3D 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); - access_size =3D 1 << access_size; - } - break; - default: - break; - } - } - - if (access_size) { - xinsn =3D SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_i= mm)) & - (access_size - 1)); - } - - return xinsn; -} - -/* - * Handle Traps - * - * Adapted from Spike's processor_t::take_trap. - * - */ -void riscv_cpu_do_interrupt(CPUState *cs) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - bool write_gva =3D false; - uint64_t s; - - /* - * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide - * so we mask off the MSB and separate into trap type and cause. - */ - bool async =3D !!(cs->exception_index & RISCV_EXCP_INT_FLAG); - target_ulong cause =3D cs->exception_index & RISCV_EXCP_INT_MASK; - uint64_t deleg =3D async ? env->mideleg : env->medeleg; - target_ulong tval =3D 0; - target_ulong tinst =3D 0; - target_ulong htval =3D 0; - target_ulong mtval2 =3D 0; - - if (cause =3D=3D RISCV_EXCP_SEMIHOST) { - do_common_semihosting(cs); - env->pc +=3D 4; - return; - } - - if (!async) { - /* set tval to badaddr for traps with address information */ - switch (cause) { - case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: - case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: - case RISCV_EXCP_LOAD_ADDR_MIS: - case RISCV_EXCP_STORE_AMO_ADDR_MIS: - case RISCV_EXCP_LOAD_ACCESS_FAULT: - case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: - case RISCV_EXCP_LOAD_PAGE_FAULT: - case RISCV_EXCP_STORE_PAGE_FAULT: - write_gva =3D env->two_stage_lookup; - tval =3D env->badaddr; - if (env->two_stage_indirect_lookup) { - /* - * special pseudoinstruction for G-stage fault taken while - * doing VS-stage page table walk. - */ - tinst =3D (riscv_cpu_xlen(env) =3D=3D 32) ? 0x00002000 : 0= x00003000; - } else { - /* - * The "Addr. Offset" field in transformed instruction is - * non-zero only for misaligned access. - */ - tinst =3D riscv_transformed_insn(env, env->bins, tval); - } - break; - case RISCV_EXCP_INST_GUEST_PAGE_FAULT: - case RISCV_EXCP_INST_ADDR_MIS: - case RISCV_EXCP_INST_ACCESS_FAULT: - case RISCV_EXCP_INST_PAGE_FAULT: - write_gva =3D env->two_stage_lookup; - tval =3D env->badaddr; - if (env->two_stage_indirect_lookup) { - /* - * special pseudoinstruction for G-stage fault taken while - * doing VS-stage page table walk. - */ - tinst =3D (riscv_cpu_xlen(env) =3D=3D 32) ? 0x00002000 : 0= x00003000; - } - break; - case RISCV_EXCP_ILLEGAL_INST: - case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: - tval =3D env->bins; - break; - case RISCV_EXCP_BREAKPOINT: - if (cs->watchpoint_hit) { - tval =3D cs->watchpoint_hit->hitaddr; - cs->watchpoint_hit =3D NULL; - } - break; - default: - break; - } - /* ecall is dispatched as one cause so translate based on mode */ - if (cause =3D=3D RISCV_EXCP_U_ECALL) { - assert(env->priv <=3D 3); - - if (env->priv =3D=3D PRV_M) { - cause =3D RISCV_EXCP_M_ECALL; - } else if (env->priv =3D=3D PRV_S && env->virt_enabled) { - cause =3D RISCV_EXCP_VS_ECALL; - } else if (env->priv =3D=3D PRV_S && !env->virt_enabled) { - cause =3D RISCV_EXCP_S_ECALL; - } else if (env->priv =3D=3D PRV_U) { - cause =3D RISCV_EXCP_U_ECALL; - } - } - } - - trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, - riscv_cpu_get_trap_name(cause, async)); - - qemu_log_mask(CPU_LOG_INT, - "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_l= x", " - "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=3D%= s\n", - __func__, env->mhartid, async, cause, env->pc, tval, - riscv_cpu_get_trap_name(cause, async)); - - if (env->priv <=3D PRV_S && - cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { - /* handle the trap in S-mode */ - if (riscv_has_ext(env, RVH)) { - uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; - - if (env->virt_enabled && ((hdeleg >> cause) & 1)) { - /* Trap to VS mode */ - /* - * See if we need to adjust cause. Yes if its VS mode inte= rrupt - * no if hypervisor has delegated one of hs mode's interru= pt - */ - if (cause =3D=3D IRQ_VS_TIMER || cause =3D=3D IRQ_VS_SOFT = || - cause =3D=3D IRQ_VS_EXT) { - cause =3D cause - 1; - } - write_gva =3D false; - } else if (env->virt_enabled) { - /* Trap into HS mode, from virt */ - riscv_cpu_swap_hypervisor_regs(env); - env->hstatus =3D set_field(env->hstatus, HSTATUS_SPVP, - env->priv); - env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, true= ); - - htval =3D env->guest_phys_fault_addr; - - riscv_cpu_set_virt_enabled(env, 0); - } else { - /* Trap into HS mode */ - env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, fals= e); - htval =3D env->guest_phys_fault_addr; - } - env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, write_gv= a); - } - - s =3D env->mstatus; - s =3D set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); - s =3D set_field(s, MSTATUS_SPP, env->priv); - s =3D set_field(s, MSTATUS_SIE, 0); - env->mstatus =3D s; - env->scause =3D cause | ((target_ulong)async << (TARGET_LONG_BITS = - 1)); - env->sepc =3D env->pc; - env->stval =3D tval; - env->htval =3D htval; - env->htinst =3D tinst; - env->pc =3D (env->stvec >> 2 << 2) + - ((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0); - riscv_cpu_set_mode(env, PRV_S); - } else { - /* handle the trap in M-mode */ - if (riscv_has_ext(env, RVH)) { - if (env->virt_enabled) { - riscv_cpu_swap_hypervisor_regs(env); - } - env->mstatus =3D set_field(env->mstatus, MSTATUS_MPV, - env->virt_enabled); - if (env->virt_enabled && tval) { - env->mstatus =3D set_field(env->mstatus, MSTATUS_GVA, 1); - } - - mtval2 =3D env->guest_phys_fault_addr; - - /* Trapping to M mode, virt is disabled */ - riscv_cpu_set_virt_enabled(env, 0); - } - - s =3D env->mstatus; - s =3D set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); - s =3D set_field(s, MSTATUS_MPP, env->priv); - s =3D set_field(s, MSTATUS_MIE, 0); - env->mstatus =3D s; - env->mcause =3D cause | ~(((target_ulong)-1) >> async); - env->mepc =3D env->pc; - env->mtval =3D tval; - env->mtval2 =3D mtval2; - env->mtinst =3D tinst; - env->pc =3D (env->mtvec >> 2 << 2) + - ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); - riscv_cpu_set_mode(env, PRV_M); - } - - /* - * NOTE: it is not necessary to yield load reservations here. It is on= ly - * necessary for an SC from "another hart" to cause a load reservation - * to be yielded. Refer to the memory consistency model section of the - * RISC-V ISA Specification. - */ - - env->two_stage_lookup =3D false; - env->two_stage_indirect_lookup =3D false; -} - -#endif /* !CONFIG_USER_ONLY */ diff --git a/target/riscv/sysemu/cpu_helper.c b/target/riscv/sysemu/cpu_hel= per.c new file mode 100644 index 0000000000..05a6b834fa --- /dev/null +++ b/target/riscv/sysemu/cpu_helper.c @@ -0,0 +1,863 @@ +/* + * RISC-V CPU system helpers for QEMU. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2017-2018 SiFive, Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/main-loop.h" +#include "exec/exec-all.h" +#include "cpu.h" +#include "internals.h" +#include "sysemu/cpu-timers.h" +#include "sysemu/pmu.h" +#include "sysemu/instmap.h" +#include "semihosting/common-semi.h" +#include "trace.h" + + +/* + * The HS-mode is allowed to configure priority only for the + * following VS-mode local interrupts: + * + * 0 (Reserved interrupt, reads as zero) + * 1 Supervisor software interrupt + * 4 (Reserved interrupt, reads as zero) + * 5 Supervisor timer interrupt + * 8 (Reserved interrupt, reads as zero) + * 13 (Reserved interrupt) + * 14 " + * 15 " + * 16 " + * 17 " + * 18 " + * 19 " + * 20 " + * 21 " + * 22 " + * 23 " + */ + +static const int hviprio_index2irq[] =3D { + 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; +static const int hviprio_index2rdzero[] =3D { + 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; + +int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero) +{ + if (index < 0 || ARRAY_SIZE(hviprio_index2irq) <=3D index) { + return -EINVAL; + } + + if (out_irq) { + *out_irq =3D hviprio_index2irq[index]; + } + + if (out_rdzero) { + *out_rdzero =3D hviprio_index2rdzero[index]; + } + + return 0; +} + +/* + * Default priorities of local interrupts are defined in the + * RISC-V Advanced Interrupt Architecture specification. + * + * ---------------------------------------------------------------- + * Default | + * Priority | Major Interrupt Numbers + * ---------------------------------------------------------------- + * Highest | 47, 23, 46, 45, 22, 44, + * | 43, 21, 42, 41, 20, 40 + * | + * | 11 (0b), 3 (03), 7 (07) + * | 9 (09), 1 (01), 5 (05) + * | 12 (0c) + * | 10 (0a), 2 (02), 6 (06) + * | + * | 39, 19, 38, 37, 18, 36, + * Lowest | 35, 17, 34, 33, 16, 32 + * ---------------------------------------------------------------- + */ +static const uint8_t default_iprio[64] =3D { + /* Custom interrupts 48 to 63 */ + [63] =3D IPRIO_MMAXIPRIO, + [62] =3D IPRIO_MMAXIPRIO, + [61] =3D IPRIO_MMAXIPRIO, + [60] =3D IPRIO_MMAXIPRIO, + [59] =3D IPRIO_MMAXIPRIO, + [58] =3D IPRIO_MMAXIPRIO, + [57] =3D IPRIO_MMAXIPRIO, + [56] =3D IPRIO_MMAXIPRIO, + [55] =3D IPRIO_MMAXIPRIO, + [54] =3D IPRIO_MMAXIPRIO, + [53] =3D IPRIO_MMAXIPRIO, + [52] =3D IPRIO_MMAXIPRIO, + [51] =3D IPRIO_MMAXIPRIO, + [50] =3D IPRIO_MMAXIPRIO, + [49] =3D IPRIO_MMAXIPRIO, + [48] =3D IPRIO_MMAXIPRIO, + + /* Custom interrupts 24 to 31 */ + [31] =3D IPRIO_MMAXIPRIO, + [30] =3D IPRIO_MMAXIPRIO, + [29] =3D IPRIO_MMAXIPRIO, + [28] =3D IPRIO_MMAXIPRIO, + [27] =3D IPRIO_MMAXIPRIO, + [26] =3D IPRIO_MMAXIPRIO, + [25] =3D IPRIO_MMAXIPRIO, + [24] =3D IPRIO_MMAXIPRIO, + + [47] =3D IPRIO_DEFAULT_UPPER, + [23] =3D IPRIO_DEFAULT_UPPER + 1, + [46] =3D IPRIO_DEFAULT_UPPER + 2, + [45] =3D IPRIO_DEFAULT_UPPER + 3, + [22] =3D IPRIO_DEFAULT_UPPER + 4, + [44] =3D IPRIO_DEFAULT_UPPER + 5, + + [43] =3D IPRIO_DEFAULT_UPPER + 6, + [21] =3D IPRIO_DEFAULT_UPPER + 7, + [42] =3D IPRIO_DEFAULT_UPPER + 8, + [41] =3D IPRIO_DEFAULT_UPPER + 9, + [20] =3D IPRIO_DEFAULT_UPPER + 10, + [40] =3D IPRIO_DEFAULT_UPPER + 11, + + [11] =3D IPRIO_DEFAULT_M, + [3] =3D IPRIO_DEFAULT_M + 1, + [7] =3D IPRIO_DEFAULT_M + 2, + + [9] =3D IPRIO_DEFAULT_S, + [1] =3D IPRIO_DEFAULT_S + 1, + [5] =3D IPRIO_DEFAULT_S + 2, + + [12] =3D IPRIO_DEFAULT_SGEXT, + + [10] =3D IPRIO_DEFAULT_VS, + [2] =3D IPRIO_DEFAULT_VS + 1, + [6] =3D IPRIO_DEFAULT_VS + 2, + + [39] =3D IPRIO_DEFAULT_LOWER, + [19] =3D IPRIO_DEFAULT_LOWER + 1, + [38] =3D IPRIO_DEFAULT_LOWER + 2, + [37] =3D IPRIO_DEFAULT_LOWER + 3, + [18] =3D IPRIO_DEFAULT_LOWER + 4, + [36] =3D IPRIO_DEFAULT_LOWER + 5, + + [35] =3D IPRIO_DEFAULT_LOWER + 6, + [17] =3D IPRIO_DEFAULT_LOWER + 7, + [34] =3D IPRIO_DEFAULT_LOWER + 8, + [33] =3D IPRIO_DEFAULT_LOWER + 9, + [16] =3D IPRIO_DEFAULT_LOWER + 10, + [32] =3D IPRIO_DEFAULT_LOWER + 11, +}; + +uint8_t riscv_cpu_default_priority(int irq) +{ + if (irq < 0 || irq > 63) { + return IPRIO_MMAXIPRIO; + } + + return default_iprio[irq] ? default_iprio[irq] : IPRIO_MMAXIPRIO; +}; + +int riscv_cpu_pending_to_irq(CPURISCVState *env, + int extirq, unsigned int extirq_def_prio, + uint64_t pending, uint8_t *iprio) +{ + int irq, best_irq =3D RISCV_EXCP_NONE; + unsigned int prio, best_prio =3D UINT_MAX; + + if (!pending) { + return RISCV_EXCP_NONE; + } + + irq =3D ctz64(pending); + if (!((extirq =3D=3D IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : + riscv_cpu_cfg(env)->ext_ssaia)) { + return irq; + } + + pending =3D pending >> irq; + while (pending) { + prio =3D iprio[irq]; + if (!prio) { + if (irq =3D=3D extirq) { + prio =3D extirq_def_prio; + } else { + prio =3D (riscv_cpu_default_priority(irq) < extirq_def_pri= o) ? + 1 : IPRIO_MMAXIPRIO; + } + } + if ((pending & 0x1) && (prio <=3D best_prio)) { + best_irq =3D irq; + best_prio =3D prio; + } + irq++; + pending =3D pending >> 1; + } + + return best_irq; +} + +uint64_t riscv_cpu_all_pending(CPURISCVState *env) +{ + uint32_t gein =3D get_field(env->hstatus, HSTATUS_VGEIN); + uint64_t vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; + uint64_t vstip =3D (env->vstime_irq) ? MIP_VSTIP : 0; + + return (env->mip | vsgein | vstip) & env->mie; +} + +int riscv_cpu_mirq_pending(CPURISCVState *env) +{ + uint64_t irqs =3D riscv_cpu_all_pending(env) & ~env->mideleg & + ~(MIP_SGEIP | MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); + + return riscv_cpu_pending_to_irq(env, IRQ_M_EXT, IPRIO_DEFAULT_M, + irqs, env->miprio); +} + +int riscv_cpu_sirq_pending(CPURISCVState *env) +{ + uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & + ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); + + return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, + irqs, env->siprio); +} + +int riscv_cpu_vsirq_pending(CPURISCVState *env) +{ + uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & + (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); + + return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, + irqs >> 1, env->hviprio); +} + +/* Return true is floating point support is currently enabled */ +bool riscv_cpu_fp_enabled(CPURISCVState *env) +{ + if (env->mstatus & MSTATUS_FS) { + if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_FS)) { + return false; + } + return true; + } + + return false; +} + +/* Return true is vector support is currently enabled */ +bool riscv_cpu_vector_enabled(CPURISCVState *env) +{ + if (env->mstatus & MSTATUS_VS) { + if (env->virt_enabled && !(env->mstatus_hs & MSTATUS_VS)) { + return false; + } + return true; + } + + return false; +} + +void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) +{ + uint64_t mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | + MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | + MSTATUS64_UXL | MSTATUS_VS; + + if (riscv_has_ext(env, RVF)) { + mstatus_mask |=3D MSTATUS_FS; + } + bool current_virt =3D env->virt_enabled; + + g_assert(riscv_has_ext(env, RVH)); + + if (current_virt) { + /* Current V=3D1 and we are about to change to V=3D0 */ + env->vsstatus =3D env->mstatus & mstatus_mask; + env->mstatus &=3D ~mstatus_mask; + env->mstatus |=3D env->mstatus_hs; + + env->vstvec =3D env->stvec; + env->stvec =3D env->stvec_hs; + + env->vsscratch =3D env->sscratch; + env->sscratch =3D env->sscratch_hs; + + env->vsepc =3D env->sepc; + env->sepc =3D env->sepc_hs; + + env->vscause =3D env->scause; + env->scause =3D env->scause_hs; + + env->vstval =3D env->stval; + env->stval =3D env->stval_hs; + + env->vsatp =3D env->satp; + env->satp =3D env->satp_hs; + } else { + /* Current V=3D0 and we are about to change to V=3D1 */ + env->mstatus_hs =3D env->mstatus & mstatus_mask; + env->mstatus &=3D ~mstatus_mask; + env->mstatus |=3D env->vsstatus; + + env->stvec_hs =3D env->stvec; + env->stvec =3D env->vstvec; + + env->sscratch_hs =3D env->sscratch; + env->sscratch =3D env->vsscratch; + + env->sepc_hs =3D env->sepc; + env->sepc =3D env->vsepc; + + env->scause_hs =3D env->scause; + env->scause =3D env->vscause; + + env->stval_hs =3D env->stval; + env->stval =3D env->vstval; + + env->satp_hs =3D env->satp; + env->satp =3D env->vsatp; + } +} + +target_ulong riscv_cpu_get_geilen(CPURISCVState *env) +{ + if (!riscv_has_ext(env, RVH)) { + return 0; + } + + return env->geilen; +} + +void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen) +{ + if (!riscv_has_ext(env, RVH)) { + return; + } + + if (geilen > (TARGET_LONG_BITS - 1)) { + return; + } + + env->geilen =3D geilen; +} + +/* This function can only be called to set virt when RVH is enabled */ +void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) +{ + /* Flush the TLB on all virt mode changes. */ + if (env->virt_enabled !=3D enable) { + tlb_flush(env_cpu(env)); + } + + env->virt_enabled =3D enable; + + if (enable) { + /* + * The guest external interrupts from an interrupt controller are + * delivered only when the Guest/VM is running (i.e. V=3D1). This = means + * any guest external interrupt which is triggered while the Guest= /VM + * is not running (i.e. V=3D0) will be missed on QEMU resulting in= guest + * with sluggish response to serial console input and other I/O ev= ents. + * + * To solve this, we check and inject interrupt after setting V=3D= 1. + */ + riscv_cpu_update_mip(env, 0, 0); + } +} + +int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) +{ + CPURISCVState *env =3D &cpu->env; + if (env->miclaim & interrupts) { + return -1; + } else { + env->miclaim |=3D interrupts; + return 0; + } +} + +uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + uint64_t gein, vsgein =3D 0, vstip =3D 0, old =3D env->mip; + + if (env->virt_enabled) { + gein =3D get_field(env->hstatus, HSTATUS_VGEIN); + vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; + } + + vstip =3D env->vstime_irq ? MIP_VSTIP : 0; + + QEMU_IOTHREAD_LOCK_GUARD(); + + env->mip =3D (env->mip & ~mask) | (value & mask); + + if (env->mip | vsgein | vstip) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } + + return old; +} + +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), + void *arg) +{ + env->rdtime_fn =3D fn; + env->rdtime_fn_arg =3D arg; +} + +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, + int (*rmw_fn)(void *arg, + target_ulong reg, + target_ulong *val, + target_ulong new_val, + target_ulong write_mask), + void *rmw_fn_arg) +{ + if (priv <=3D PRV_M) { + env->aia_ireg_rmw_fn[priv] =3D rmw_fn; + env->aia_ireg_rmw_fn_arg[priv] =3D rmw_fn_arg; + } +} + +void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) +{ + g_assert(newpriv <=3D PRV_M && newpriv !=3D PRV_RESERVED); + + if (icount_enabled() && newpriv !=3D env->priv) { + riscv_itrigger_update_priv(env); + } + /* tlb_flush is unnecessary as mode is contained in mmu_idx */ + env->priv =3D newpriv; + env->xl =3D cpu_recompute_xl(env); + riscv_cpu_update_mask(env); + + /* + * Clear the load reservation - otherwise a reservation placed in one + * context/process can be used by another, resulting in an SC succeedi= ng + * incorrectly. Version 2.2 of the ISA specification explicitly requir= es + * this behaviour, while later revisions say that the kernel "should" = use + * an SC instruction to force the yielding of a load reservation on a + * preemptive context switch. As a result, do both. + */ + env->load_res =3D -1; +} + +static target_ulong riscv_transformed_insn(CPURISCVState *env, + target_ulong insn, + target_ulong taddr) +{ + target_ulong xinsn =3D 0; + target_ulong access_rs1 =3D 0, access_imm =3D 0, access_size =3D 0; + + /* + * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to + * be uncompressed. The Quadrant 1 of RVC instruction space need + * not be transformed because these instructions won't generate + * any load/store trap. + */ + + if ((insn & 0x3) !=3D 0x3) { + /* Transform 16bit instruction into 32bit instruction */ + switch (GET_C_OP(insn)) { + case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLD_LQ: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FLD (RV32/64) */ + xinsn =3D OPC_RISC_FLD; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_LD_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_LW: /* C.LW */ + xinsn =3D OPC_RISC_LW; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_LW_IMM(insn); + access_size =3D 4; + break; + case OPC_RISC_C_FUNC_FLW_LD: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FLW (RV32) */ + xinsn =3D OPC_RISC_FLW; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_LW_IMM(insn); + access_size =3D 4; + } else { /* C.LD (RV64/RV128) */ + xinsn =3D OPC_RISC_LD; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_LD_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_FSD_SQ: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FSD (RV32/64) */ + xinsn =3D OPC_RISC_FSD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_SD_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_SW: /* C.SW */ + xinsn =3D OPC_RISC_SW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_SW_IMM(insn); + access_size =3D 4; + break; + case OPC_RISC_C_FUNC_FSW_SD: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FSW (RV32) */ + xinsn =3D OPC_RISC_FSW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_SW_IMM(insn); + access_size =3D 4; + } else { /* C.SD (RV64/RV128) */ + xinsn =3D OPC_RISC_SD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + access_rs1 =3D GET_C_RS1S(insn); + access_imm =3D GET_C_SD_IMM(insn); + access_size =3D 8; + } + break; + default: + break; + } + break; + case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLDSP_LQSP: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FLDSP (RV32/64) */ + xinsn =3D OPC_RISC_FLD; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_LDSP_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ + xinsn =3D OPC_RISC_LW; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_LWSP_IMM(insn); + access_size =3D 4; + break; + case OPC_RISC_C_FUNC_FLWSP_LDSP: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FLWSP (RV32) */ + xinsn =3D OPC_RISC_FLW; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_LWSP_IMM(insn); + access_size =3D 4; + } else { /* C.LDSP (RV64/RV128) */ + xinsn =3D OPC_RISC_LD; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_LDSP_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_FSDSP_SQSP: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FSDSP (RV32/64) */ + xinsn =3D OPC_RISC_FSD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_SDSP_IMM(insn); + access_size =3D 8; + } + break; + case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ + xinsn =3D OPC_RISC_SW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_SWSP_IMM(insn); + access_size =3D 4; + break; + case 7: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FSWSP (RV32) */ + xinsn =3D OPC_RISC_FSW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_SWSP_IMM(insn); + access_size =3D 4; + } else { /* C.SDSP (RV64/RV128) */ + xinsn =3D OPC_RISC_SD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + access_rs1 =3D 2; + access_imm =3D GET_C_SDSP_IMM(insn); + access_size =3D 8; + } + break; + default: + break; + } + break; + default: + break; + } + + /* + * Clear Bit1 of transformed instruction to indicate that + * original insruction was a 16bit instruction + */ + xinsn &=3D ~((target_ulong)0x2); + } else { + /* Transform 32bit (or wider) instructions */ + switch (MASK_OP_MAJOR(insn)) { + case OPC_RISC_ATOMIC: + xinsn =3D insn; + access_rs1 =3D GET_RS1(insn); + access_size =3D 1 << GET_FUNCT3(insn); + break; + case OPC_RISC_LOAD: + case OPC_RISC_FP_LOAD: + xinsn =3D SET_I_IMM(insn, 0); + access_rs1 =3D GET_RS1(insn); + access_imm =3D GET_IMM(insn); + access_size =3D 1 << GET_FUNCT3(insn); + break; + case OPC_RISC_STORE: + case OPC_RISC_FP_STORE: + xinsn =3D SET_S_IMM(insn, 0); + access_rs1 =3D GET_RS1(insn); + access_imm =3D GET_STORE_IMM(insn); + access_size =3D 1 << GET_FUNCT3(insn); + break; + case OPC_RISC_SYSTEM: + if (MASK_OP_SYSTEM(insn) =3D=3D OPC_RISC_HLVHSV) { + xinsn =3D insn; + access_rs1 =3D GET_RS1(insn); + access_size =3D 1 << ((GET_FUNCT7(insn) >> 1) & 0x3); + access_size =3D 1 << access_size; + } + break; + default: + break; + } + } + + if (access_size) { + xinsn =3D SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_i= mm)) & + (access_size - 1)); + } + + return xinsn; +} + +/* + * Handle Traps + * + * Adapted from Spike's processor_t::take_trap. + * + */ +void riscv_cpu_do_interrupt(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + bool write_gva =3D false; + uint64_t s; + + /* + * cs->exception is 32-bits wide unlike mcause which is XLEN-bits wide + * so we mask off the MSB and separate into trap type and cause. + */ + bool async =3D !!(cs->exception_index & RISCV_EXCP_INT_FLAG); + target_ulong cause =3D cs->exception_index & RISCV_EXCP_INT_MASK; + uint64_t deleg =3D async ? env->mideleg : env->medeleg; + target_ulong tval =3D 0; + target_ulong tinst =3D 0; + target_ulong htval =3D 0; + target_ulong mtval2 =3D 0; + + if (cause =3D=3D RISCV_EXCP_SEMIHOST) { + do_common_semihosting(cs); + env->pc +=3D 4; + return; + } + + if (!async) { + /* set tval to badaddr for traps with address information */ + switch (cause) { + case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: + case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: + case RISCV_EXCP_LOAD_ADDR_MIS: + case RISCV_EXCP_STORE_AMO_ADDR_MIS: + case RISCV_EXCP_LOAD_ACCESS_FAULT: + case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: + case RISCV_EXCP_LOAD_PAGE_FAULT: + case RISCV_EXCP_STORE_PAGE_FAULT: + write_gva =3D env->two_stage_lookup; + tval =3D env->badaddr; + if (env->two_stage_indirect_lookup) { + /* + * special pseudoinstruction for G-stage fault taken while + * doing VS-stage page table walk. + */ + tinst =3D (riscv_cpu_xlen(env) =3D=3D 32) ? 0x00002000 : 0= x00003000; + } else { + /* + * The "Addr. Offset" field in transformed instruction is + * non-zero only for misaligned access. + */ + tinst =3D riscv_transformed_insn(env, env->bins, tval); + } + break; + case RISCV_EXCP_INST_GUEST_PAGE_FAULT: + case RISCV_EXCP_INST_ADDR_MIS: + case RISCV_EXCP_INST_ACCESS_FAULT: + case RISCV_EXCP_INST_PAGE_FAULT: + write_gva =3D env->two_stage_lookup; + tval =3D env->badaddr; + if (env->two_stage_indirect_lookup) { + /* + * special pseudoinstruction for G-stage fault taken while + * doing VS-stage page table walk. + */ + tinst =3D (riscv_cpu_xlen(env) =3D=3D 32) ? 0x00002000 : 0= x00003000; + } + break; + case RISCV_EXCP_ILLEGAL_INST: + case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: + tval =3D env->bins; + break; + case RISCV_EXCP_BREAKPOINT: + if (cs->watchpoint_hit) { + tval =3D cs->watchpoint_hit->hitaddr; + cs->watchpoint_hit =3D NULL; + } + break; + default: + break; + } + /* ecall is dispatched as one cause so translate based on mode */ + if (cause =3D=3D RISCV_EXCP_U_ECALL) { + assert(env->priv <=3D 3); + + if (env->priv =3D=3D PRV_M) { + cause =3D RISCV_EXCP_M_ECALL; + } else if (env->priv =3D=3D PRV_S && env->virt_enabled) { + cause =3D RISCV_EXCP_VS_ECALL; + } else if (env->priv =3D=3D PRV_S && !env->virt_enabled) { + cause =3D RISCV_EXCP_S_ECALL; + } else if (env->priv =3D=3D PRV_U) { + cause =3D RISCV_EXCP_U_ECALL; + } + } + } + + trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, + riscv_cpu_get_trap_name(cause, async)); + + qemu_log_mask(CPU_LOG_INT, + "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_l= x", " + "epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=3D%= s\n", + __func__, env->mhartid, async, cause, env->pc, tval, + riscv_cpu_get_trap_name(cause, async)); + + if (env->priv <=3D PRV_S && + cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { + /* handle the trap in S-mode */ + if (riscv_has_ext(env, RVH)) { + uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; + + if (env->virt_enabled && ((hdeleg >> cause) & 1)) { + /* Trap to VS mode */ + /* + * See if we need to adjust cause. Yes if its VS mode inte= rrupt + * no if hypervisor has delegated one of hs mode's interru= pt + */ + if (cause =3D=3D IRQ_VS_TIMER || cause =3D=3D IRQ_VS_SOFT = || + cause =3D=3D IRQ_VS_EXT) { + cause =3D cause - 1; + } + write_gva =3D false; + } else if (env->virt_enabled) { + /* Trap into HS mode, from virt */ + riscv_cpu_swap_hypervisor_regs(env); + env->hstatus =3D set_field(env->hstatus, HSTATUS_SPVP, + env->priv); + env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, true= ); + + htval =3D env->guest_phys_fault_addr; + + riscv_cpu_set_virt_enabled(env, 0); + } else { + /* Trap into HS mode */ + env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, fals= e); + htval =3D env->guest_phys_fault_addr; + } + env->hstatus =3D set_field(env->hstatus, HSTATUS_GVA, write_gv= a); + } + + s =3D env->mstatus; + s =3D set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); + s =3D set_field(s, MSTATUS_SPP, env->priv); + s =3D set_field(s, MSTATUS_SIE, 0); + env->mstatus =3D s; + env->scause =3D cause | ((target_ulong)async << (TARGET_LONG_BITS = - 1)); + env->sepc =3D env->pc; + env->stval =3D tval; + env->htval =3D htval; + env->htinst =3D tinst; + env->pc =3D (env->stvec >> 2 << 2) + + ((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0); + riscv_cpu_set_mode(env, PRV_S); + } else { + /* handle the trap in M-mode */ + if (riscv_has_ext(env, RVH)) { + if (env->virt_enabled) { + riscv_cpu_swap_hypervisor_regs(env); + } + env->mstatus =3D set_field(env->mstatus, MSTATUS_MPV, + env->virt_enabled); + if (env->virt_enabled && tval) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_GVA, 1); + } + + mtval2 =3D env->guest_phys_fault_addr; + + /* Trapping to M mode, virt is disabled */ + riscv_cpu_set_virt_enabled(env, 0); + } + + s =3D env->mstatus; + s =3D set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); + s =3D set_field(s, MSTATUS_MPP, env->priv); + s =3D set_field(s, MSTATUS_MIE, 0); + env->mstatus =3D s; + env->mcause =3D cause | ~(((target_ulong)-1) >> async); + env->mepc =3D env->pc; + env->mtval =3D tval; + env->mtval2 =3D mtval2; + env->mtinst =3D tinst; + env->pc =3D (env->mtvec >> 2 << 2) + + ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); + riscv_cpu_set_mode(env, PRV_M); + } + + /* + * NOTE: it is not necessary to yield load reservations here. It is on= ly + * necessary for an SC from "another hart" to cause a load reservation + * to be yielded. Refer to the memory consistency model section of the + * RISC-V ISA Specification. + */ + + env->two_stage_lookup =3D false; + env->two_stage_indirect_lookup =3D false; +} diff --git a/target/riscv/sysemu/meson.build b/target/riscv/sysemu/meson.bu= ild index e902ba2dad..3573fdbe1f 100644 --- a/target/riscv/sysemu/meson.build +++ b/target/riscv/sysemu/meson.build @@ -1,5 +1,6 @@ riscv_system_ss.add(files( 'arch_dump.c', + 'cpu_helper.c', 'debug.c', 'machine.c', 'monitor.c', --=20 2.38.1 From nobody Tue May 14 09:30:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1688409244; cv=none; d=zohomail.com; s=zohoarc; b=D7Zh2CmzeWCJf0zA74Ttq3AupUcYP+pGV/XwCKXLTqfMC6YqnYih6S0gr7hPj/+NzTrxga+Mv8yIY7E+4L7wAMKP1qThLYUJPH/9ovjcqRAtvFJgot3Dz0nbvjau/OIaznJAr2rAQlK1W7oaF0yisyTWfeLkocauGuBwk+nMkMU= ARC-Message-Signature: i=1; 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Mon, 03 Jul 2023 11:33:29 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Beraldo Leal , Wainer dos Santos Moschetta , Alistair Francis , Daniel Henrique Barboza , kvm@vger.kernel.org, qemu-riscv@nongnu.org, Bin Meng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Weiwei Li , Liu Zhiwei Subject: [PATCH v2 15/16] target/riscv: Restrict TCG-specific prototype declarations Date: Mon, 3 Jul 2023 20:31:44 +0200 Message-Id: <20230703183145.24779-16-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230703183145.24779-1-philmd@linaro.org> References: <20230703183145.24779-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688409246917100002 Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.h | 3 +++ target/riscv/cpu.c | 11 +++++++++++ 2 files changed, 14 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 42bd7efe4c..ab1968deb7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -474,7 +474,10 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, in= t index, uint64_t bit); =20 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); =20 +#ifdef CONFIG_TCG void riscv_translate_init(void); +#endif + G_NORETURN void riscv_raise_exception(CPURISCVState *env, uint32_t exception, uintptr_t pc); =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cd01af3595..31ca1a4ff9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -37,7 +37,9 @@ #include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "fpu/softfloat-helpers.h" +#ifdef CONFIG_TCG #include "tcg/tcg.h" +#endif =20 /* RISC-V CPU definitions */ =20 @@ -785,6 +787,7 @@ static vaddr riscv_cpu_get_pc(CPUState *cs) return env->pc; } =20 +#ifdef CONFIG_TCG static void riscv_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -802,6 +805,7 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, } } } +#endif =20 static bool riscv_cpu_has_work(CPUState *cs) { @@ -818,6 +822,7 @@ static bool riscv_cpu_has_work(CPUState *cs) #endif } =20 +#ifdef CONFIG_TCG static void riscv_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) @@ -840,6 +845,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, } env->bins =3D data[1]; } +#endif =20 static void riscv_cpu_reset_hold(Object *obj) { @@ -1871,6 +1877,8 @@ static const struct SysemuCPUOps riscv_sysemu_ops =3D= { }; #endif =20 +#ifdef CONFIG_TCG + #include "hw/core/tcg-cpu-ops.h" =20 static const struct TCGCPUOps riscv_tcg_ops =3D { @@ -1889,6 +1897,7 @@ static const struct TCGCPUOps riscv_tcg_ops =3D { .debug_check_watchpoint =3D riscv_cpu_debug_check_watchpoint, #endif /* !CONFIG_USER_ONLY */ }; +#endif /* CONFIG_TCG */ =20 static void riscv_cpu_class_init(ObjectClass *c, void *data) { @@ -1919,7 +1928,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; +#ifdef CONFIG_TCG cc->tcg_ops =3D &riscv_tcg_ops; +#endif /* CONFIG_TCG */ =20 device_class_set_props(dc, riscv_cpu_properties); } --=20 2.38.1 From nobody Tue May 14 09:30:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1688409391740100001 Add a new job to cross-build the riscv64 target without the TCG accelerator (IOW: only KVM accelerator enabled). Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- .gitlab-ci.d/crossbuilds.yml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index b6ec99ecd1..588ef4ebcb 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -129,6 +129,14 @@ cross-riscv64-user: variables: IMAGE: debian-riscv64-cross =20 +cross-riscv64-kvm-only: + extends: .cross_accel_build_job + needs: + job: riscv64-debian-cross-container + variables: + IMAGE: debian-riscv64-cross + EXTRA_CONFIGURE_OPTS: --disable-tcg --without-default-features + cross-s390x-system: extends: .cross_system_build_job needs: --=20 2.38.1