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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=npiggin@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1688385870357100001 Content-Type: text/plain; charset="utf-8" ppc currently silently accepts invalid real address access. Catch these and turn them into machine checks on POWER9/10 machines. Signed-off-by: Nicholas Piggin Reviewed-by: C=C3=A9dric Le Goater --- Since v1: - Only implement this for POWER9/10. Seems like previous IBM processors may not catch this, trying to get info. Since v2: - Split out from larger series since it is independent. target/ppc/cpu_init.c | 1 + target/ppc/excp_helper.c | 49 ++++++++++++++++++++++++++++++++++++++++ target/ppc/internal.h | 5 ++++ 3 files changed, 55 insertions(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 720aad9e05..6ac1765a8d 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7335,6 +7335,7 @@ static const struct TCGCPUOps ppc_tcg_ops =3D { .cpu_exec_enter =3D ppc_cpu_exec_enter, .cpu_exec_exit =3D ppc_cpu_exec_exit, .do_unaligned_access =3D ppc_cpu_do_unaligned_access, + .do_transaction_failed =3D ppc_cpu_do_transaction_failed, #endif /* !CONFIG_USER_ONLY */ }; #endif /* CONFIG_TCG */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 354392668e..e49e13a30d 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1428,7 +1428,9 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) /* machine check exceptions don't have ME set */ new_msr &=3D ~((target_ulong)1 << MSR_ME); =20 + msr |=3D env->error_code; break; + case POWERPC_EXCP_DSI: /* Data storage exception = */ trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]); break; @@ -3184,5 +3186,52 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr= vaddr, env->error_code =3D insn & 0x03FF0000; cpu_loop_exit(cs); } + +void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr vaddr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) +{ + CPUPPCState *env =3D cs->env_ptr; + + switch (env->excp_model) { +#if defined(TARGET_PPC64) + case POWERPC_EXCP_POWER9: + case POWERPC_EXCP_POWER10: + /* + * Machine check codes can be found in processor User Manual or + * Linux or skiboot source. + */ + if (access_type =3D=3D MMU_DATA_LOAD) { + env->spr[SPR_DAR] =3D vaddr; + env->spr[SPR_DSISR] =3D PPC_BIT(57); + env->error_code =3D PPC_BIT(42); + + } else if (access_type =3D=3D MMU_DATA_STORE) { + /* + * MCE for stores in POWER is asynchronous so hardware does + * not set DAR, but QEMU can do better. + */ + env->spr[SPR_DAR] =3D vaddr; + env->error_code =3D PPC_BIT(36) | PPC_BIT(43) | PPC_BIT(45); + env->error_code |=3D PPC_BIT(42); + + } else { /* Fetch */ + env->error_code =3D PPC_BIT(36) | PPC_BIT(44) | PPC_BIT(45); + } + break; +#endif + default: + /* + * TODO: Check behaviour for other CPUs, for now do nothing. + * Could add a basic MCE even if real hardware ignores. + */ + return; + } + + cs->exception_index =3D POWERPC_EXCP_MCHECK; + cpu_loop_exit_restore(cs, retaddr); +} #endif /* CONFIG_TCG */ #endif /* !CONFIG_USER_ONLY */ diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 901bae6d39..57acb3212c 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -296,6 +296,11 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, G_NORETURN void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int= mmu_idx, uintptr_t retaddr); +void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr= ); #endif =20 FIELD(GER_MSK, XMSK, 0, 4) --=20 2.40.1