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[125.228.20.175]) by smtp.gmail.com with ESMTPSA id y19-20020aa78553000000b0066f37665a63sm8231969pfn.73.2023.07.02.08.54.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 08:54:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1688313268; x=1690905268; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1riBvo1oXFtMRmpl8ENRZtm2YSjNOJkGaUz7dnmSvt8=; b=nlUaSpfgRUAs+TSnTLE3zY1mQrIEjF80xv386ocVBndswXlNeHz8bhmBDC1R74LcRb ToaV+Q+Sc4ET4L1pk+sFoY/ZPG/Ef0ZiiNJnRYqT1B9nPzR55d+J+xxOwf1e/1GODjEm llzl3LcDf4dpzuWmECq4+EKQMXq/uqMvZ5mwIPN2HW7RcuOYm87YA346qER+O37tki4l nqtjMnIisy4Hn5+T8QaApRru64UmanXrVp6bgm0EQJQ3Ya473B5Ss9whErRBadlZFeu4 /Drrw2ZXjdb7eDns9VGa13WBcR9k6bR84yW/4zG0rISNEItarg5VkKutCiZNLOezbLT2 a9ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688313268; x=1690905268; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1riBvo1oXFtMRmpl8ENRZtm2YSjNOJkGaUz7dnmSvt8=; b=IpwVChc509jv0Smh2WYzSpHxovap7ZnMbzZnXdb70+aBaDR7ltjWiboGiN/Pe7GZGm Kq3C/Vd4gBnshLaiW6Zvu3TbCx+lpKsNil3G6wSp5DUHh+Gjx9CgRyTeIkfidWQcNJaf S+vcX/NmxgHIaliqcv1lv8JTVDkPTx/o6jU6S9XZqxjiZxpGV21ciub4SKZyKuYdfU5r IzX/hY9QPmrE+G64MdxhBoxfvio6Hfu0pRQAIC/8Aopy30tvIpCnToqK+rC4o8VhbeGW f6Tv8dJ3jXxPW+ECIzgx5VDSdrTtO/R8afNgaZoTRr11QA6KKK8tJwa+zjt2erooUulc onFQ== X-Gm-Message-State: ABy/qLaioeIfsO79pIgSD6KnhMTuedM2sbZBjBvimg9N7crpK9OLwo1G Fjv7BzdBTcKeIfVE/vMxK6J6tDROnFQfBkQvKftgh1A1jPBUN3M9Qghv6EHWNAif7uhr+FCim27 SMklsifQrHGuMfApsRNO8xkAOvBSxAwKvbpz6XKl3Ooj8sqZDa30UiTvU6lxzw95d1g3o27cT9z VrmM8= X-Google-Smtp-Source: APBJJlGuNQgHy21FaTv9T2e4+2C78seBUVPV1Gx/OGwo8a9fBBKe9oeGgyJJbhGaAEDL6ZvsA6pArQ== X-Received: by 2002:a05:6a00:1a8f:b0:676:20f8:be41 with SMTP id e15-20020a056a001a8f00b0067620f8be41mr8232006pfv.16.1688313267568; Sun, 02 Jul 2023 08:54:27 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: dbarboza@ventanamicro.com, Kiran Ostrolenk , Weiwei Li , Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Liu Zhiwei Subject: [PATCH v7 01/15] target/riscv: Refactor some of the generic vector functionality Date: Sun, 2 Jul 2023 23:53:35 +0800 Message-Id: <20230702155354.2478495-2-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230702155354.2478495-1-max.chou@sifive.com> References: <20230702155354.2478495-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=max.chou@sifive.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1688313295345100003 Content-Type: text/plain; charset="utf-8" From: Kiran Ostrolenk Take some functions/macros out of `vector_helper` and put them in a new module called `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk Reviewed-by: Weiwei Li Signed-off-by: Max Chou --- target/riscv/meson.build | 1 + target/riscv/vector_helper.c | 201 +------------------------------- target/riscv/vector_internals.c | 81 +++++++++++++ target/riscv/vector_internals.h | 182 +++++++++++++++++++++++++++++ 4 files changed, 265 insertions(+), 200 deletions(-) create mode 100644 target/riscv/vector_internals.c create mode 100644 target/riscv/vector_internals.h diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 7f56c5f88d..c3801ee5e0 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -16,6 +16,7 @@ riscv_ss.add(files( 'gdbstub.c', 'op_helper.c', 'vector_helper.c', + 'vector_internals.c', 'bitmanip_helper.c', 'translate.c', 'm128_helper.c', diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 1e06e7447c..57be83400d 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -26,6 +26,7 @@ #include "fpu/softfloat.h" #include "tcg/tcg-gvec-desc.h" #include "internals.h" +#include "vector_internals.h" #include =20 target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, @@ -72,68 +73,6 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_u= long s1, return vl; } =20 -/* - * Note that vector data is stored in host-endian 64-bit chunks, - * so addressing units smaller than that needs a host-endian fixup. - */ -#if HOST_BIG_ENDIAN -#define H1(x) ((x) ^ 7) -#define H1_2(x) ((x) ^ 6) -#define H1_4(x) ((x) ^ 4) -#define H2(x) ((x) ^ 3) -#define H4(x) ((x) ^ 1) -#define H8(x) ((x)) -#else -#define H1(x) (x) -#define H1_2(x) (x) -#define H1_4(x) (x) -#define H2(x) (x) -#define H4(x) (x) -#define H8(x) (x) -#endif - -static inline uint32_t vext_nf(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, NF); -} - -static inline uint32_t vext_vm(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VM); -} - -/* - * Encode LMUL to lmul as following: - * LMUL vlmul lmul - * 1 000 0 - * 2 001 1 - * 4 010 2 - * 8 011 3 - * - 100 - - * 1/8 101 -3 - * 1/4 110 -2 - * 1/2 111 -1 - */ -static inline int32_t vext_lmul(uint32_t desc) -{ - return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); -} - -static inline uint32_t vext_vta(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VTA); -} - -static inline uint32_t vext_vma(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VMA); -} - -static inline uint32_t vext_vta_all_1s(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S); -} - /* * Get the maximum number of elements can be operated. * @@ -152,21 +91,6 @@ static inline uint32_t vext_max_elems(uint32_t desc, ui= nt32_t log2_esz) return scale < 0 ? vlenb >> -scale : vlenb << scale; } =20 -/* - * Get number of total elements, including prestart, body and tail element= s. - * Note that when LMUL < 1, the tail includes the elements past VLMAX that - * are held in the same vector register. - */ -static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t d= esc, - uint32_t esz) -{ - uint32_t vlenb =3D simd_maxsz(desc); - uint32_t sew =3D 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); - int8_t emul =3D ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 : - ctzl(esz) - ctzl(sew) + vext_lmul(desc); - return (vlenb << emul) / esz; -} - static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong ad= dr) { return (addr & ~env->cur_pmmask) | env->cur_pmbase; @@ -199,20 +123,6 @@ static void probe_pages(CPURISCVState *env, target_ulo= ng addr, } } =20 -/* set agnostic elements to 1s */ -static void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t c= nt, - uint32_t tot) -{ - if (is_agnostic =3D=3D 0) { - /* policy undisturbed */ - return; - } - if (tot - cnt =3D=3D 0) { - return; - } - memset(base + cnt, -1, tot - cnt); -} - static inline void vext_set_elem_mask(void *v0, int index, uint8_t value) { @@ -222,18 +132,6 @@ static inline void vext_set_elem_mask(void *v0, int in= dex, ((uint64_t *)v0)[idx] =3D deposit64(old, pos, 1, value); } =20 -/* - * Earlier designs (pre-0.9) had a varying number of bits - * per mask value (MLEN). In the 0.9 design, MLEN=3D1. - * (Section 4.5) - */ -static inline int vext_elem_mask(void *v0, int index) -{ - int idx =3D index / 64; - int pos =3D index % 64; - return (((uint64_t *)v0)[idx] >> pos) & 1; -} - /* elements operations for load and store */ typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr, uint32_t idx, void *vd, uintptr_t retaddr); @@ -728,18 +626,11 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) * Vector Integer Arithmetic Instructions */ =20 -/* expand macro args before macro */ -#define RVVCALL(macro, ...) macro(__VA_ARGS__) - /* (TD, T1, T2, TX1, TX2) */ #define OP_SSS_B int8_t, int8_t, int8_t, int8_t, int8_t #define OP_SSS_H int16_t, int16_t, int16_t, int16_t, int16_t #define OP_SSS_W int32_t, int32_t, int32_t, int32_t, int32_t #define OP_SSS_D int64_t, int64_t, int64_t, int64_t, int64_t -#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t -#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t -#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t -#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t #define OP_SUS_B int8_t, uint8_t, int8_t, uint8_t, int8_t #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t @@ -763,16 +654,6 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) #define NOP_UUU_H uint16_t, uint16_t, uint32_t, uint16_t, uint32_t #define NOP_UUU_W uint32_t, uint32_t, uint64_t, uint32_t, uint64_t =20 -/* operation of two vector elements */ -typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); - -#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ -static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ -{ \ - TX1 s1 =3D *((T1 *)vs1 + HS1(i)); \ - TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ - *((TD *)vd + HD(i)) =3D OP(s2, s1); \ -} #define DO_SUB(N, M) (N - M) #define DO_RSUB(N, M) (M - N) =20 @@ -785,40 +666,6 @@ RVVCALL(OPIVV2, vsub_vv_h, OP_SSS_H, H2, H2, H2, DO_SU= B) RVVCALL(OPIVV2, vsub_vv_w, OP_SSS_W, H4, H4, H4, DO_SUB) RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB) =20 -static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, - CPURISCVState *env, uint32_t desc, - opivv2_fn *fn, uint32_t esz) -{ - uint32_t vm =3D vext_vm(desc); - uint32_t vl =3D env->vl; - uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); - uint32_t vta =3D vext_vta(desc); - uint32_t vma =3D vext_vma(desc); - uint32_t i; - - for (i =3D env->vstart; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, i)) { - /* set masked-off elements to 1s */ - vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); - continue; - } - fn(vd, vs1, vs2, i); - } - env->vstart =3D 0; - /* set tail elements to 1s */ - vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); -} - -/* generate the helpers for OPIVV */ -#define GEN_VEXT_VV(NAME, ESZ) \ -void HELPER(NAME)(void *vd, void *v0, void *vs1, \ - void *vs2, CPURISCVState *env, \ - uint32_t desc) \ -{ \ - do_vext_vv(vd, v0, vs1, vs2, env, desc, \ - do_##NAME, ESZ); \ -} - GEN_VEXT_VV(vadd_vv_b, 1) GEN_VEXT_VV(vadd_vv_h, 2) GEN_VEXT_VV(vadd_vv_w, 4) @@ -828,18 +675,6 @@ GEN_VEXT_VV(vsub_vv_h, 2) GEN_VEXT_VV(vsub_vv_w, 4) GEN_VEXT_VV(vsub_vv_d, 8) =20 -typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); - -/* - * (T1)s1 gives the real operator type. - * (TX1)(T1)s1 expands the operator type of widen or narrow operations. - */ -#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ -static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ -{ \ - TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ - *((TD *)vd + HD(i)) =3D OP(s2, (TX1)(T1)s1); \ -} =20 RVVCALL(OPIVX2, vadd_vx_b, OP_SSS_B, H1, H1, DO_ADD) RVVCALL(OPIVX2, vadd_vx_h, OP_SSS_H, H2, H2, DO_ADD) @@ -854,40 +689,6 @@ RVVCALL(OPIVX2, vrsub_vx_h, OP_SSS_H, H2, H2, DO_RSUB) RVVCALL(OPIVX2, vrsub_vx_w, OP_SSS_W, H4, H4, DO_RSUB) RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB) =20 -static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, - CPURISCVState *env, uint32_t desc, - opivx2_fn fn, uint32_t esz) -{ - uint32_t vm =3D vext_vm(desc); - uint32_t vl =3D env->vl; - uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); - uint32_t vta =3D vext_vta(desc); - uint32_t vma =3D vext_vma(desc); - uint32_t i; - - for (i =3D env->vstart; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, i)) { - /* set masked-off elements to 1s */ - vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); - continue; - } - fn(vd, s1, vs2, i); - } - env->vstart =3D 0; - /* set tail elements to 1s */ - vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); -} - -/* generate the helpers for OPIVX */ -#define GEN_VEXT_VX(NAME, ESZ) \ -void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ - void *vs2, CPURISCVState *env, \ - uint32_t desc) \ -{ \ - do_vext_vx(vd, v0, s1, vs2, env, desc, \ - do_##NAME, ESZ); \ -} - GEN_VEXT_VX(vadd_vx_b, 1) GEN_VEXT_VX(vadd_vx_h, 2) GEN_VEXT_VX(vadd_vx_w, 4) diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internal= s.c new file mode 100644 index 0000000000..9cf5c17cde --- /dev/null +++ b/target/riscv/vector_internals.c @@ -0,0 +1,81 @@ +/* + * RISC-V Vector Extension Internals + * + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "vector_internals.h" + +/* set agnostic elements to 1s */ +void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, + uint32_t tot) +{ + if (is_agnostic =3D=3D 0) { + /* policy undisturbed */ + return; + } + if (tot - cnt =3D=3D 0) { + return ; + } + memset(base + cnt, -1, tot - cnt); +} + +void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivv2_fn *fn, uint32_t esz) +{ + uint32_t vm =3D vext_vm(desc); + uint32_t vl =3D env->vl; + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); + uint32_t i; + + for (i =3D env->vstart; i < vl; i++) { + if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); + continue; + } + fn(vd, vs1, vs2, i); + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); +} + +void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivx2_fn fn, uint32_t esz) +{ + uint32_t vm =3D vext_vm(desc); + uint32_t vl =3D env->vl; + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t vma =3D vext_vma(desc); + uint32_t i; + + for (i =3D env->vstart; i < vl; i++) { + if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); + continue; + } + fn(vd, s1, vs2, i); + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); +} diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internal= s.h new file mode 100644 index 0000000000..749d138beb --- /dev/null +++ b/target/riscv/vector_internals.h @@ -0,0 +1,182 @@ +/* + * RISC-V Vector Extension Internals + * + * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef TARGET_RISCV_VECTOR_INTERNALS_H +#define TARGET_RISCV_VECTOR_INTERNALS_H + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "cpu.h" +#include "tcg/tcg-gvec-desc.h" +#include "internals.h" + +static inline uint32_t vext_nf(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, NF); +} + +/* + * Note that vector data is stored in host-endian 64-bit chunks, + * so addressing units smaller than that needs a host-endian fixup. + */ +#if HOST_BIG_ENDIAN +#define H1(x) ((x) ^ 7) +#define H1_2(x) ((x) ^ 6) +#define H1_4(x) ((x) ^ 4) +#define H2(x) ((x) ^ 3) +#define H4(x) ((x) ^ 1) +#define H8(x) ((x)) +#else +#define H1(x) (x) +#define H1_2(x) (x) +#define H1_4(x) (x) +#define H2(x) (x) +#define H4(x) (x) +#define H8(x) (x) +#endif + +/* + * Encode LMUL to lmul as following: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + */ +static inline int32_t vext_lmul(uint32_t desc) +{ + return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); +} + +static inline uint32_t vext_vm(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VM); +} + +static inline uint32_t vext_vma(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VMA); +} + +static inline uint32_t vext_vta(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VTA); +} + +static inline uint32_t vext_vta_all_1s(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S); +} + +/* + * Earlier designs (pre-0.9) had a varying number of bits + * per mask value (MLEN). In the 0.9 design, MLEN=3D1. + * (Section 4.5) + */ +static inline int vext_elem_mask(void *v0, int index) +{ + int idx =3D index / 64; + int pos =3D index % 64; + return (((uint64_t *)v0)[idx] >> pos) & 1; +} + +/* + * Get number of total elements, including prestart, body and tail element= s. + * Note that when LMUL < 1, the tail includes the elements past VLMAX that + * are held in the same vector register. + */ +static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t d= esc, + uint32_t esz) +{ + uint32_t vlenb =3D simd_maxsz(desc); + uint32_t sew =3D 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); + int8_t emul =3D ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 : + ctzl(esz) - ctzl(sew) + vext_lmul(desc); + return (vlenb << emul) / esz; +} + +/* set agnostic elements to 1s */ +void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, + uint32_t tot); + +/* expand macro args before macro */ +#define RVVCALL(macro, ...) macro(__VA_ARGS__) + +/* (TD, T1, T2, TX1, TX2) */ +#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t +#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t +#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t +#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t + +/* operation of two vector elements */ +typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); + +#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ +static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ +{ \ + TX1 s1 =3D *((T1 *)vs1 + HS1(i)); \ + TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) =3D OP(s2, s1); \ +} + +void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivv2_fn *fn, uint32_t esz); + +/* generate the helpers for OPIVV */ +#define GEN_VEXT_VV(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + do_vext_vv(vd, v0, vs1, vs2, env, desc, \ + do_##NAME, ESZ); \ +} + +typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); + +/* + * (T1)s1 gives the real operator type. + * (TX1)(T1)s1 expands the operator type of widen or narrow operations. + */ +#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ +{ \ + TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) =3D OP(s2, (TX1)(T1)s1); \ +} + +void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivx2_fn fn, uint32_t esz); + +/* generate the helpers for OPIVX */ +#define GEN_VEXT_VX(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + do_vext_vx(vd, v0, s1, vs2, env, desc, \ + do_##NAME, ESZ); \ +} + +#endif /* TARGET_RISCV_VECTOR_INTERNALS_H */ --=20 2.34.1 From nobody Sun May 19 01:15:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1688313337; cv=none; d=zohomail.com; s=zohoarc; b=SyBCUzS0vaz20Ex6Lec3Xi1Y2UxoiKdDl+SyZ+ffnGH3r0O6finIEBysUt4pBzyr2IroneJ76RSlqOPjJWvJdhKPOVirzYnF4XedCtC5m3tp+TPQfzHXo1kiMQONdSaEfNjVuEJqSJqrQ/B03TD2a5ir3pNpZX2jGmAQw6+VADs= ARC-Message-Signature: i=1; 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Signed-off-by: Kiran Ostrolenk Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 62 +++++++++++++------------ 1 file changed, 32 insertions(+), 30 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index c2f7527f53..4a8e62a8be 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1643,38 +1643,40 @@ GEN_OPIWX_WIDEN_TRANS(vwadd_wx) GEN_OPIWX_WIDEN_TRANS(vwsubu_wx) GEN_OPIWX_WIDEN_TRANS(vwsub_wx) =20 +static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t = vm, + gen_helper_gvec_4_ptr *fn, DisasContext *s) +{ + uint32_t data =3D 0; + TCGLabel *over =3D gen_new_label(); + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); + + data =3D FIELD_DP32(data, VDATA, VM, vm); + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); + tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1), + vreg_ofs(s, vs2), cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, fn); + mark_vs_dirty(s); + gen_set_label(over); + return true; +} + /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */ /* OPIVV without GVEC IR */ -#define GEN_OPIVV_TRANS(NAME, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (CHECK(s, a)) { \ - uint32_t data =3D 0; \ - static gen_helper_gvec_4_ptr * const fns[4] =3D { \ - gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ - }; \ - TCGLabel *over =3D gen_new_label(); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ - \ - data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ - data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ - data =3D \ - FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\ - data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs1), \ - vreg_ofs(s, a->rs2), cpu_env, \ - s->cfg_ptr->vlen / 8, \ - s->cfg_ptr->vlen / 8, data, \ - fns[s->sew]); \ - mark_vs_dirty(s); \ - gen_set_label(over); \ - return true; \ - } \ - return false; \ +#define GEN_OPIVV_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + static gen_helper_gvec_4_ptr * const fns[4] =3D { = \ + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ + }; \ + return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\ + } \ + return false; \ } =20 /* --=20 2.34.1 From nobody Sun May 19 01:15:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Nazar Kazakov Reviewed-by: Weiwei Li Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 31 +------------------------ 1 file changed, 1 insertion(+), 30 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 4a8e62a8be..7e194aae34 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -617,7 +617,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, ui= nt32_t data, TCGv_i32 desc; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -786,7 +785,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1= , uint32_t rs2, TCGv_i32 desc; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -893,7 +891,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1,= uint32_t vs2, TCGv_i32 desc; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -1034,7 +1031,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uin= t32_t data, TCGv_i32 desc; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -1191,7 +1187,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3F= n *gvec_fn, return false; } =20 - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { @@ -1241,7 +1236,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, uint32_t vm, uint32_t data =3D 0; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -1405,7 +1399,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, ui= nt32_t vs2, uint32_t vm, uint32_t data =3D 0; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -1492,7 +1485,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr = *a, if (checkfn(s, a)) { uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -1575,7 +1567,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr = *a, if (opiwv_widen_check(s, a)) { uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -1648,7 +1639,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, ui= nt32_t vs2, uint32_t vm, { uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, vm); @@ -1842,7 +1832,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_w, \ }; \ TCGLabel *over =3D gen_new_label(); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2054,7 +2043,6 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_= v *a) gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d, }; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), @@ -2078,7 +2066,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_= x *a) vext_check_ss(s, a->rd, 0, 1)) { TCGv s1; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 s1 =3D get_gpr(s, a->rs1, EXT_SIGN); @@ -2140,7 +2127,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_= i *a) gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, }; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 s1 =3D tcg_constant_i64(simm); @@ -2288,7 +2274,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm(s, RISCV_FRM_DYN); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2323,7 +2308,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, ui= nt32_t vs2, TCGv_i64 t1; =20 TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 dest =3D tcg_temp_new_ptr(); @@ -2408,7 +2392,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm(s, RISCV_FRM_DYN); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2483,7 +2466,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm(s, RISCV_FRM_DYN); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2601,7 +2583,6 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); gen_set_rm_chkfrm(s, rm); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -2713,7 +2694,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) gen_helper_vmv_v_x_d, }; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 t1 =3D tcg_temp_new_i64(); @@ -2792,7 +2772,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm_chkfrm(s, FRM); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2844,7 +2823,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm(s, RISCV_FRM_DYN); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2912,7 +2890,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm_chkfrm(s, FRM); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2962,7 +2939,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)= \ }; \ TCGLabel *over =3D gen_new_label(); \ gen_set_rm_chkfrm(s, FRM); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -3053,7 +3029,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) = \ uint32_t data =3D 0; \ gen_helper_gvec_4_ptr *fn =3D gen_helper_##NAME; \ TCGLabel *over =3D gen_new_label(); \ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ @@ -3224,7 +3199,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) require_vm(a->vm, a->rd)) { uint32_t data =3D 0; TCGLabel *over =3D gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); @@ -3411,7 +3385,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_= x *a) TCGv s1; TCGLabel *over =3D gen_new_label(); =20 - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 t1 =3D tcg_temp_new_i64(); @@ -3468,8 +3441,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_= s_f *a) TCGv_i64 t1; TCGLabel *over =3D gen_new_label(); =20 - /* if vl =3D=3D 0 or vstart >=3D vl, skip vector register write ba= ck */ - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); + /* if vstart >=3D vl, skip vector register write back */ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 /* NaN-box f[rs1] */ @@ -3720,7 +3692,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, u= int8_t seq) uint32_t data =3D 0; gen_helper_gvec_3_ptr *fn; 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[125.228.20.175]) by smtp.gmail.com with ESMTPSA id y19-20020aa78553000000b0066f37665a63sm8231969pfn.73.2023.07.02.08.54.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 08:54:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1688313285; x=1690905285; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OEJ9kwymeFlmuuKiMd/g4dpMPoDIXBBqm7ECdie05ks=; b=iYsROF1GOplbDCnMac+xg1NdRh8tr6aubb7OwSKs0XNFyqDlQceWBoizviFXWsinpx exaer0RBI4zKqLDLw8I1Yfn3EyRBTs4sape2vVWno56ugmgo3eLUtR8V/5gOYSeYbgKi v8GQqIE8zGl3E7J19nbpEgSYNRD8sdzTzxe7epEfDU38nD4g0sLaaPPQkhYf9JRGuUqu DEvlN3JdXev7zAt6Q9dzKCv5hSQzK7iJN2UKQPMMmPKaiHu9i0X2/3Mr5oDgn++He9UC +fGSA+06mk5gx/sZDjg5qtOkCX5TXgwgIrLe4r+NqGpi+taR5H3VWqvQdRcg89ARsgbi kZcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688313285; x=1690905285; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OEJ9kwymeFlmuuKiMd/g4dpMPoDIXBBqm7ECdie05ks=; b=GpITSd7zifeaswkwmIsk/OYykH4upC0t0PZKBFHIb9gHPuvq7v50qkL4Q9vAabtSjk 28uF41pMp+L9tuAdGPYkJlPAS9K5yLM2u2QkgoIhU9+KWMiG2GiwLZb21lCcsL5CFUuI v8c8/eccHuAN3qDtlqCxSyCEgyt84dBsCau2qdX6bM/rW2wanhJS0VQf1O9RuTFXAif8 pirrJhspq8RwSqVvOlo9mlYP0VoKHSXRSQsY+pgVKvXCIZUVJGDKjqE12tBdYCHHjear 1loCD6B6VFFpzj8uzeFcSoRytEsF9vUAlzRMUbweFu+y1MjONt5vWUJRyHp3hMi8wV9l p4UQ== X-Gm-Message-State: ABy/qLYt9rnHPHoayS56upIlTOthvGkKkF6VNQFzL/6Xq6ewB1D7EDZZ QD9jYCnE27dzd6Qd+ACrTK6Q151+lk9H7HSu23QAh1HQKUXQ0F+JN6Cy6j9TKqeRHL+ROtSk5oe VABXX/6vfkGprnNUlg3ArDiNdXMma2L3RIk5O+wBqbnO3IYqwbzmC/3GAg+90z8VITpMTbZAhzm OQd/Q= X-Google-Smtp-Source: APBJJlEjBmxT6IdRXOjoQEUqA9a9NEENLkRE+0ZIxbZPimzQ8saRldFSZUsD39WpsiFWt4x3fCpKiQ== X-Received: by 2002:aa7:982e:0:b0:67b:8602:aa1e with SMTP id q14-20020aa7982e000000b0067b8602aa1emr9977755pfl.28.1688313285016; Sun, 02 Jul 2023 08:54:45 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: dbarboza@ventanamicro.com, Lawrence Hunter , Nazar Kazakov , Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Kiran Ostrolenk Subject: [PATCH v7 04/15] target/riscv: Add Zvbc ISA extension support Date: Sun, 2 Jul 2023 23:53:38 +0800 Message-Id: <20230702155354.2478495-5-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230702155354.2478495-1-max.chou@sifive.com> References: <20230702155354.2478495-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=max.chou@sifive.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1688313340351100011 Content-Type: text/plain; charset="utf-8" From: Lawrence Hunter This commit adds support for the Zvbc vector-crypto extension, which consists of the following instructions: * vclmulh.[vx,vv] * vclmul.[vx,vv] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov Co-authored-by: Max Chou Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter Signed-off-by: Max Chou [max.chou@sifive.com: Exposed x-zvbc property] --- target/riscv/cpu.c | 9 ++++ target/riscv/cpu_cfg.h | 1 + target/riscv/helper.h | 6 +++ target/riscv/insn32.decode | 6 +++ target/riscv/insn_trans/trans_rvvk.c.inc | 62 ++++++++++++++++++++++++ target/riscv/meson.build | 3 +- target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 59 ++++++++++++++++++++++ 8 files changed, 146 insertions(+), 1 deletion(-) create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc create mode 100644 target/riscv/vcrypto_helper.c diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 881bddf393..174ae9fe1a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -111,6 +111,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), + ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc), ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), @@ -1184,6 +1185,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu= , Error **errp) return; } =20 + if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) { + error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensio= ns"); + return; + } + if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn =3D true; cpu->cfg.ext_zkr =3D true; @@ -1683,6 +1689,9 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), =20 + /* Vector cryptography extensions */ + DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), + DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index c4a627d335..b6e9bd2e99 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -83,6 +83,7 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; bool ext_zve64d; + bool ext_zvbc; bool ext_zmmul; bool ext_zvfh; bool ext_zvfhmin; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 98e97810fd..be0f0f1058 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1153,3 +1153,9 @@ DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl,= tl, tl) =20 /* Zce helper */ DEF_HELPER_FLAGS_2(cm_jalt, TCG_CALL_NO_WG, tl, env, i32) + +/* Vector crypto functions */ +DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 73d5d1b045..52cd92e262 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -908,3 +908,9 @@ sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_a= es # *** RV32 Zicond Standard Extension *** czero_eqz 0000111 ..... ..... 101 ..... 0110011 @r czero_nez 0000111 ..... ..... 111 ..... 0110011 @r + +# *** Zvbc vector crypto extension *** +vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm +vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm +vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm +vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc new file mode 100644 index 0000000000..552b08a2fd --- /dev/null +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -0,0 +1,62 @@ +/* + * RISC-V translation routines for the vector crypto extension. + * + * Copyright (C) 2023 SiFive, Inc. + * Written by Codethink Ltd and SiFive. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +/* + * Zvbc + */ + +#define GEN_VV_MASKED_TRANS(NAME, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, \ + gen_helper_##NAME, s); \ + } \ + return false; \ + } + +static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a) +{ + return opivv_check(s, a) && + s->cfg_ptr->ext_zvbc =3D=3D true && + s->sew =3D=3D MO_64; +} + +GEN_VV_MASKED_TRANS(vclmul_vv, vclmul_vv_check) +GEN_VV_MASKED_TRANS(vclmulh_vv, vclmul_vv_check) + +#define GEN_VX_MASKED_TRANS(NAME, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, \ + gen_helper_##NAME, s); \ + } \ + return false; \ + } + +static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a) +{ + return opivx_check(s, a) && + s->cfg_ptr->ext_zvbc =3D=3D true && + s->sew =3D=3D MO_64; +} + +GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check) +GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check) diff --git a/target/riscv/meson.build b/target/riscv/meson.build index c3801ee5e0..660078bda1 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -21,7 +21,8 @@ riscv_ss.add(files( 'translate.c', 'm128_helper.c', 'crypto_helper.c', - 'zce_helper.c' + 'zce_helper.c', + 'vcrypto_helper.c' )) riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files(= 'kvm-stub.c')) =20 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8a33da811e..b785f83cdc 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1106,6 +1106,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, t= arget_ulong pc) #include "insn_trans/trans_rvzicbo.c.inc" #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_rvk.c.inc" +#include "insn_trans/trans_rvvk.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "decode-xthead.c.inc" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c new file mode 100644 index 0000000000..8b7c63d499 --- /dev/null +++ b/target/riscv/vcrypto_helper.c @@ -0,0 +1,59 @@ +/* + * RISC-V Vector Crypto Extension Helpers for QEMU. + * + * Copyright (C) 2023 SiFive, Inc. + * Written by Codethink Ltd and SiFive. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/host-utils.h" +#include "qemu/bitops.h" +#include "cpu.h" +#include "exec/memop.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "internals.h" +#include "vector_internals.h" + +static uint64_t clmul64(uint64_t y, uint64_t x) +{ + uint64_t result =3D 0; + for (int j =3D 63; j >=3D 0; j--) { + if ((y >> j) & 1) { + result ^=3D (x << j); + } + } + return result; +} + +static uint64_t clmulh64(uint64_t y, uint64_t x) +{ + uint64_t result =3D 0; + for (int j =3D 63; j >=3D 1; j--) { + if ((y >> j) & 1) { + result ^=3D (x >> (64 - j)); + } + } + return result; +} + +RVVCALL(OPIVV2, vclmul_vv, OP_UUU_D, H8, H8, H8, clmul64) +GEN_VEXT_VV(vclmul_vv, 8) +RVVCALL(OPIVX2, vclmul_vx, OP_UUU_D, H8, H8, clmul64) +GEN_VEXT_VX(vclmul_vx, 8) +RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmulh64) +GEN_VEXT_VV(vclmulh_vv, 8) +RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64) +GEN_VEXT_VX(vclmulh_vx, 8) --=20 2.34.1 From nobody Sun May 19 01:15:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1688313340; cv=none; d=zohomail.com; s=zohoarc; b=ZUXgFhymmlIslWJuRFwiX85hiv0PR7pr9LO5TIMDjsJZW/6BquvCcKQMdyPRbrAl+UttieBQ1pVBK0ybakpTldU4dLYr/4XUa+vEmaPCLqTfTILY17DLIMnL1Y0Kzrn2gT+oqDvTF7RXL92Aek9FOBK2IzkPJdIfx4EWyzzossI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1688313340; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Q2Ovee+6qNzPOr0iR3dEIiS21VnlZ9hT+MEjpqH5QMg=; b=j0zhlk2PzWbMpZWfPzNZCEp0JFYUGz4u7+rOnJGqiEHOGmEuv2+YmLuTll4jdRm2TH16J8PXMWmgyuIQ4WzBMgj2hCFFUsMgkZFWm5qcwEfhAgT780Xyc4YpbGZ8ZFUnPhXvoHJWtvRnkfOVkZk9ZhZaj2xvLyuI4bBYY6WhT7s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1688313340104913.7467261615261; Sun, 2 Jul 2023 08:55:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qFzPx-0002aG-Qu; Sun, 02 Jul 2023 11:55:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFzPj-0002UC-J7 for qemu-devel@nongnu.org; Sun, 02 Jul 2023 11:55:06 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qFzPg-0008MC-G8 for qemu-devel@nongnu.org; Sun, 02 Jul 2023 11:55:03 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-666eef03ebdso1779835b3a.1 for ; Sun, 02 Jul 2023 08:54:50 -0700 (PDT) Received: from duncan.localdomain (125-228-20-175.hinet-ip.hinet.net. [125.228.20.175]) by smtp.gmail.com with ESMTPSA id y19-20020aa78553000000b0066f37665a63sm8231969pfn.73.2023.07.02.08.54.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 08:54:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1688313289; x=1690905289; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q2Ovee+6qNzPOr0iR3dEIiS21VnlZ9hT+MEjpqH5QMg=; b=X3zpVaj1LxzhS1EUMbiYZaWFECsl63qAGDKU/BaYXzHIaaa/16+7ocuVvokB0mvIi4 piW885I2Sgt6j3eOx/oq2MJErwxkxIb/KCLkrW3VqOMw4/pF/2geNrQVF5/CVjrNl67K bzDtgGn+UXAf9t2Jb8wgN9BgcOOZL/UlH6otlkGZvf6d9UFFy05FGxknnlq1gv2fqJyy tW985iS0+LnOYbM7JlaWgb0y6n4ux1BZNHNHj0UdjNHgFHl9w5YyBbWk8t7rG7YM/cVV 6fi7ZYtgDy5cIhYunkikpt1GnB8WzlaaQu9OaaP+iIWSYH9JgWIc48YD3Hma1m9O6yBo 9/fw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688313289; x=1690905289; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q2Ovee+6qNzPOr0iR3dEIiS21VnlZ9hT+MEjpqH5QMg=; b=PKZsFCOYdqjzntpFN82iupuI5/BzgiBXnUnIyAV/la53UkLmDc4mH7tJr/xElW+mcz X95dfntw9pcKtr8pjy4m9dyjPDKUbiZM+PxApOKj6Ri44ZYZctsE7gGe6u7CDuUboRUI z3SiWZYXJ9BDbimkKUy6nkJ5BOvrztIk7OY4dPjJCsCPPKKSsh+ti4xX8HRcKtzPN2/i DS+xZiQZRB0TdJY9FP2T7IT5R6gywUuveFhaL3mVnjoNK0HKvWprQbpPqZGkY6d2S35+ kz/sqlrDbAKBYQAuAja4FhAw3B7yha+PsHK6k87kSjvUyxpgnb1E3fhtnad2ZAfwE83s 0vjw== X-Gm-Message-State: ABy/qLaTbIz9uWUpb3fVMnT69a797YU1M/LkfG9Wj8wDNdEkmH/uEL98 lC8H2NunHIg9O7wlHxT/fRh14zLOiqusv4eGQrAJBzPtzSCjwz6cVRfNJ7ITqauNpolZWyMmxTz AWvrSsWn0th7QMWoQyuQwuiHJGVvGUOTzveDAqbnV80wvj/pjfkarkC+A0FQHcRmJrMVdjnWktU Tl1XE= X-Google-Smtp-Source: APBJJlFbOlvzbGl9KML6qpg+abd4FbEePh1Gqfj7VkOHD6X3PpvyT3swyzX/oqLGifAiz2eHOflF3A== X-Received: by 2002:a05:6a00:1501:b0:668:9bf9:fa70 with SMTP id q1-20020a056a00150100b006689bf9fa70mr7655739pfu.34.1688313289319; Sun, 02 Jul 2023 08:54:49 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: dbarboza@ventanamicro.com, Nazar Kazakov , Richard Henderson , Weiwei Li , Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Liu Zhiwei , Frank Chang Subject: [PATCH v7 05/15] target/riscv: Move vector translation checks Date: Sun, 2 Jul 2023 23:53:39 +0800 Message-Id: <20230702155354.2478495-6-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230702155354.2478495-1-max.chou@sifive.com> References: <20230702155354.2478495-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=max.chou@sifive.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1688313340831100015 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions and into the corresponding macros. This enables the functions to be reused in proceeding commits without check duplication. Signed-off-by: Nazar Kazakov Reviewed-by: Richard Henderson Reviewed-by: Weiwei Li Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 28 +++++++++++-------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 7e194aae34..5dfd524c7d 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1183,9 +1183,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3F= n *gvec_fn, gen_helper_gvec_4_ptr *fn) { TCGLabel *over =3D gen_new_label(); - if (!opivv_check(s, a)) { - return false; - } =20 tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); =20 @@ -1218,6 +1215,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ }; \ + if (!opivv_check(s, a)) { \ + return false; \ + } \ return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ } =20 @@ -1276,10 +1276,6 @@ static inline bool do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn, gen_helper_opivx *fn) { - if (!opivx_check(s, a)) { - return false; - } - if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { TCGv_i64 src1 =3D tcg_temp_new_i64(); =20 @@ -1301,6 +1297,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ }; \ + if (!opivx_check(s, a)) { \ + return false; \ + } \ return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ } =20 @@ -1432,10 +1431,6 @@ static inline bool do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn, gen_helper_opivx *fn, imm_mode_t imm_mode) { - if (!opivx_check(s, a)) { - return false; - } - if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s)); @@ -1453,6 +1448,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \ gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \ }; \ + if (!opivx_check(s, a)) { \ + return false; \ + } \ return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \ fns[s->sew], IMM_MODE); \ } @@ -1775,10 +1773,6 @@ static inline bool do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn, gen_helper_opivx *fn) { - if (!opivx_check(s, a)) { - return false; - } - if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) { TCGv_i32 src1 =3D tcg_temp_new_i32(); =20 @@ -1800,7 +1794,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a= ) \ gen_helper_##NAME##_b, gen_helper_##NAME##_h, \ gen_helper_##NAME##_w, gen_helper_##NAME##_d, \ }; \ - \ + if (!opivx_check(s, a)) { \ + return false; \ + } \ return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ } =20 --=20 2.34.1 From nobody Sun May 19 01:15:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[125.228.20.175]) by smtp.gmail.com with ESMTPSA id y19-20020aa78553000000b0066f37665a63sm8231969pfn.73.2023.07.02.08.54.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 08:54:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1688313295; x=1690905295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hg0EKwgvCCgR7W9/tfUNXThD0shU8nTw5ygSHtQqyWI=; b=RUDFxvT39zRokQg6IPJXLpBIRWps2KQkmNnORosmcLYSrQh3X1U5B1tAoKAyBJytSn X/NI3EJAUfXITIh35pFyy7sr+LuXeOzDyVJO4smPjBYee9wpDxqU2NiHxsyvZXfajG7l HA2LeFh/zlg6mWU4yQ3NOAw1iOKUasn4d9UMZprlFj5T/+fzB6f8FamMHO64V1s+VwGW gdDohAC2TFoZ01AGlNlrJ5eqh6v0Ju4bSTb/YsFIrpvFPAyllksdRKX7gx21b6lXF/HZ PFbvAYJe+YpYJmvyPaVDqBE8x63TYFPfQgyMOIMKm/Re61gHklvVOR2q+ajc3s951Ohc aqNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688313295; x=1690905295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hg0EKwgvCCgR7W9/tfUNXThD0shU8nTw5ygSHtQqyWI=; b=e2P5GTAut7FrL329VJVm7FS/VkB3B88MJoQQm0H0OXBIAVtevkEHs7/jYEO2wj787D wvyd01fk1z4O4vrHN6StEe6FPKQFwagg1Vor+rMSuzZxWyV1Coy22+bMyNdFUvetlNCn wpZy32F5DpcITMfkhbOqTVax4GUuYzatKqp5iz4mPtRqHMkZrKBz0v9t0Zxi9qKLoHaV tAyKBYMLP6eGf7jJPg0Ey6/xzgii226uNgIj4WOAdvi9TJUW9wmSiNOA7NjAErW+c6EN nyP+GEGRkMhrJyhqF46q7lO1I6K/lvCgvolv0xeL3OlUO/jXLQiaJpGFl8mUV9R/qOHD Z5iQ== X-Gm-Message-State: ABy/qLa/a3tGyxbiSWYGoM861wfW2E2AZbpOVrYAnzkI28xrG2lGns0W N5X9xOME5ynANNhJTdGrnVSucvw5lQm2E4Jln6oWUAdBNCQJyF5w7UkiRAkXkWuVWmU62EqeDEn KN8NuWUA7ylRCkJvCTbYFvBMmNvrXwz5slQ2uV1dauSQ7pYbaWjCOMGDCOAqj2jitS/3/3a4mJk 6H140= X-Google-Smtp-Source: APBJJlF/0C/EUemMyq7KDKZGcn0zfNVFY+/r2tbFZClsNihGLO3POSGqgEr2WA6bQdwzkVw2WVzQ3Q== X-Received: by 2002:a05:6a00:15c9:b0:674:8fe0:126f with SMTP id o9-20020a056a0015c900b006748fe0126fmr12171276pfu.27.1688313294689; Sun, 02 Jul 2023 08:54:54 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: dbarboza@ventanamicro.com, Dickon Hood , Richard Henderson , Weiwei Li , Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Liu Zhiwei , Frank Chang Subject: [PATCH v7 06/15] target/riscv: Refactor translation of vector-widening instruction Date: Sun, 2 Jul 2023 23:53:40 +0800 Message-Id: <20230702155354.2478495-7-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230702155354.2478495-1-max.chou@sifive.com> References: <20230702155354.2478495-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=max.chou@sifive.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1688313336461100002 Content-Type: text/plain; charset="utf-8" From: Dickon Hood Zvbb (implemented in later commit) has a widening instruction, which requires an extra check on the enabled extensions. Refactor GEN_OPIVX_WIDEN_TRANS() to take a check function to avoid reimplementing it. Signed-off-by: Dickon Hood Reviewed-by: Richard Henderson Reviewed-by: Weiwei Li Signed-off-by: Max Chou --- target/riscv/insn_trans/trans_rvv.c.inc | 52 +++++++++++-------------- 1 file changed, 23 insertions(+), 29 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 5dfd524c7d..a556250553 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1526,30 +1526,24 @@ static bool opivx_widen_check(DisasContext *s, arg_= rmrr *a) vext_check_ds(s, a->rd, a->rs2, a->vm); } =20 -static bool do_opivx_widen(DisasContext *s, arg_rmrr *a, - gen_helper_opivx *fn) -{ - if (opivx_widen_check(s, a)) { - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); - } - return false; -} - -#define GEN_OPIVX_WIDEN_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - static gen_helper_opivx * const fns[3] =3D { \ - gen_helper_##NAME##_b, \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w \ - }; \ - return do_opivx_widen(s, a, fns[s->sew]); \ +#define GEN_OPIVX_WIDEN_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + static gen_helper_opivx * const fns[3] =3D { = \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w \ + }; \ + return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s); \ + } \ + return false; \ } =20 -GEN_OPIVX_WIDEN_TRANS(vwaddu_vx) -GEN_OPIVX_WIDEN_TRANS(vwadd_vx) -GEN_OPIVX_WIDEN_TRANS(vwsubu_vx) -GEN_OPIVX_WIDEN_TRANS(vwsub_vx) +GEN_OPIVX_WIDEN_TRANS(vwaddu_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwadd_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwsubu_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwsub_vx, opivx_widen_check) =20 /* WIDEN OPIVV with WIDEN */ static bool opiwv_widen_check(DisasContext *s, arg_rmrr *a) @@ -1997,9 +1991,9 @@ GEN_OPIVX_TRANS(vrem_vx, opivx_check) GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check) GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check) GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check) -GEN_OPIVX_WIDEN_TRANS(vwmul_vx) -GEN_OPIVX_WIDEN_TRANS(vwmulu_vx) -GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx) +GEN_OPIVX_WIDEN_TRANS(vwmul_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmulu_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx, opivx_widen_check) =20 /* Vector Single-Width Integer Multiply-Add Instructions */ GEN_OPIVV_TRANS(vmacc_vv, opivv_check) @@ -2015,10 +2009,10 @@ GEN_OPIVX_TRANS(vnmsub_vx, opivx_check) GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check) GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check) GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check) -GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx) -GEN_OPIVX_WIDEN_TRANS(vwmacc_vx) -GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx) -GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx) +GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmacc_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx, opivx_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx, opivx_widen_check) =20 /* Vector Integer Merge and Move Instructions */ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) --=20 2.34.1 From nobody Sun May 19 01:15:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[125.228.20.175]) by smtp.gmail.com with ESMTPSA id y19-20020aa78553000000b0066f37665a63sm8231969pfn.73.2023.07.02.08.54.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 08:54:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1688313299; x=1690905299; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XkO25Rg1Lt6NXKDYaL4gODfG/1cPbL2sMM5/ee4/pn4=; b=Mtmyp0lpM3CH0/kNd+tmGiG4dr5rMCo5yB8z7xw1XXKbVG3REmq3aSku0WjJN7enwB lT3bHG9Zcqh6cBUn6658V2HlOy7s70Q0QSzuyltFQgcVfNrPNBTVkvj2ZRRG9RX2ELwd BIO0x9Okrv7tFrYYKJrnGbqlU4a6xeeRY9O0Xg/vu3bMpw4/XP859hm1kT+B/XW7LbsK BXFGKKIXYzz1v7Z1jsFeMJrewDckEGXM/eaaJK25HiQ+Rd9A7tSruJTeWDu2oAWn4WV6 GDxfCcRIe4xsJ9n0F3AXr7kv6+jAUhOtOOTsn//HIydlDNwl3q5t5kgVAgasFWDKA9XO wOJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688313299; x=1690905299; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XkO25Rg1Lt6NXKDYaL4gODfG/1cPbL2sMM5/ee4/pn4=; b=NZHCYMnAhdMcxD6LcLI4E78bZ1tnXTvVNZQNW5yGtCOm++YfHPKVOHdo0rKoqT1pLz eQWlRs+GTLZK1cSA1eqd4f4VqWIKC24mKBmKq99T18q143TUCFt8LOE9Sb59rsLtsYaJ Ad7jaZ9thp4dRApXKZNZtA8lc5+6Ay/TvVSduQRKXdLaksm2Fg3Wn0XYoC/NKjI9/rle K/JSFBJxc7vzhVQE4NiX6yZAl6Hl9Bm4LdaGrEszuxN/gpNI7qcBO7DFn5z5HcbPHEcE zInu6jVVsGeyNSGd104eZraYfsaXsS5ty8QG/sgAiv55BOl5vlgbO2Nirl9pnkn3mUcC 8oVg== X-Gm-Message-State: AC+VfDz3H20yHhe7j/J/fA7Ymr5aS/hL7MtviBYokfE/62lsYpfmKWlF oc/WpWIcqZxwiLvNiVJJib8UlUsYJ4TVYTwxdrJISca5s9n0TexCJbjxnpKB9euZ8VDOxaPGhFg 67N9AThJsRu2Id8PVY+XqM188W1nBHnlKpJwgYaZ7im694+tF4w6OKV0kdc5/JM1JseTrwTIh3X +2nnw= X-Google-Smtp-Source: ACHHUZ4FqKOoCIjTHb90BD5bSm+XbK4xg4QOD1PUcejSp/GgcnLy9WenRC/GEFwjXFfvYpv+VF5n/g== X-Received: by 2002:a05:6a20:1051:b0:12b:e7de:6382 with SMTP id gt17-20020a056a20105100b0012be7de6382mr8537676pzc.34.1688313299101; Sun, 02 Jul 2023 08:54:59 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: dbarboza@ventanamicro.com, Kiran Ostrolenk , Weiwei Li , Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Liu Zhiwei Subject: [PATCH v7 07/15] target/riscv: Refactor some of the generic vector functionality Date: Sun, 2 Jul 2023 23:53:41 +0800 Message-Id: <20230702155354.2478495-8-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230702155354.2478495-1-max.chou@sifive.com> References: <20230702155354.2478495-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=max.chou@sifive.com; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1688313387074100007 Content-Type: text/plain; charset="utf-8" From: Kiran Ostrolenk Move some macros out of `vector_helper` and into `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits). Signed-off-by: Kiran Ostrolenk Reviewed-by: Weiwei Li Signed-off-by: Max Chou --- target/riscv/vector_helper.c | 42 ------------------------------ target/riscv/vector_internals.h | 46 +++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+), 42 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 57be83400d..124ed22f95 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -635,9 +635,6 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t #define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t -#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t -#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t -#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t #define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t #define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t #define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t @@ -3426,11 +3423,6 @@ GEN_VEXT_VF(vfwnmsac_vf_h, 4) GEN_VEXT_VF(vfwnmsac_vf_w, 8) =20 /* Vector Floating-Point Square-Root Instruction */ -/* (TD, T2, TX2) */ -#define OP_UU_H uint16_t, uint16_t, uint16_t -#define OP_UU_W uint32_t, uint32_t, uint32_t -#define OP_UU_D uint64_t, uint64_t, uint64_t - #define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, void *vs2, int i, \ CPURISCVState *env) \ @@ -4127,40 +4119,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32) GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64) =20 /* Vector Floating-Point Classify Instruction */ -#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ -static void do_##NAME(void *vd, void *vs2, int i) \ -{ \ - TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ - *((TD *)vd + HD(i)) =3D OP(s2); \ -} - -#define GEN_VEXT_V(NAME, ESZ) \ -void HELPER(NAME)(void *vd, void *v0, void *vs2, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t vm =3D vext_vm(desc); \ - uint32_t vl =3D env->vl; \ - uint32_t total_elems =3D \ - vext_get_total_elems(env, desc, ESZ); \ - uint32_t vta =3D vext_vta(desc); \ - uint32_t vma =3D vext_vma(desc); \ - uint32_t i; \ - \ - for (i =3D env->vstart; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, i)) { \ - /* set masked-off elements to 1s */ \ - vext_set_elems_1s(vd, vma, i * ESZ, \ - (i + 1) * ESZ); \ - continue; \ - } \ - do_##NAME(vd, vs2, i); \ - } \ - env->vstart =3D 0; \ - /* set tail elements to 1s */ \ - vext_set_elems_1s(vd, vta, vl * ESZ, \ - total_elems * ESZ); \ -} - target_ulong fclass_h(uint64_t frs1) { float16 f =3D frs1; diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internal= s.h index 749d138beb..8133111e5f 100644 --- a/target/riscv/vector_internals.h +++ b/target/riscv/vector_internals.h @@ -121,12 +121,52 @@ void vext_set_elems_1s(void *base, uint32_t is_agnost= ic, uint32_t cnt, /* expand macro args before macro */ #define RVVCALL(macro, ...) macro(__VA_ARGS__) =20 +/* (TD, T2, TX2) */ +#define OP_UU_B uint8_t, uint8_t, uint8_t +#define OP_UU_H uint16_t, uint16_t, uint16_t +#define OP_UU_W uint32_t, uint32_t, uint32_t +#define OP_UU_D uint64_t, uint64_t, uint64_t + /* (TD, T1, T2, TX1, TX2) */ #define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t #define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t #define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t #define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t =20 +#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, void *vs2, int i) \ +{ \ + TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) =3D OP(s2); \ +} + +#define GEN_VEXT_V(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm =3D vext_vm(desc); \ + uint32_t vl =3D env->vl; \ + uint32_t total_elems =3D \ + vext_get_total_elems(env, desc, ESZ); \ + uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ + uint32_t i; \ + \ + for (i =3D env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * ESZ, \ + (i + 1) * ESZ); \ + continue; \ + } \ + do_##NAME(vd, vs2, i); \ + } \ + env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * ESZ, \ + total_elems * ESZ); \ +} + /* operation of two vector elements */ typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); =20 @@ -179,4 +219,10 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,= \ do_##NAME, ESZ); \ } =20 +/* Three of the widening shortening macros: */ +/* (TD, T1, T2, TX1, TX2) */ +#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t +#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t +#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t + #endif /* TARGET_RISCV_VECTOR_INTERNALS_H */ --=20 2.34.1 From nobody Sun May 19 01:15:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[125.228.20.175]) by smtp.gmail.com with ESMTPSA id y19-20020aa78553000000b0066f37665a63sm8231969pfn.73.2023.07.02.08.55.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 08:55:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1688313305; x=1690905305; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XZxb36BSx0BizWvRmUSfduL2BqUWs072sfauyeLdXQg=; b=XcxVNY9UTmXqKFHb2ibKuyiOXCLs3E1QhJJpfxiVH6U4Q4OsEho2DxE0aIlA9EENmN ojUY0yCnPPfUwkx86Ppug9U6vF7JsS8UycmUSQUiPboQG5VbEVl/ELmBZGtj92Zvd5Lz XOUk7yYFbxjMhoSgxggpGJE1sDooqkkMvbFDRsxve8k8XVRcB9NP2nYoZUVsZUTVVk3b Nw7NiECbT/DTtYUQ7gyxbTMT7uuTWSF5FwWfHoJ6KnvnMlmtSwPsmQ4QdTRfV/gYw5yX +O/1nUgRg8Go5Bsy24rsKPsoRPQoW5e+41GP4x3axK4ZQ/v+fOCfieD03UD9HJEAVcKS omUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688313305; x=1690905305; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XZxb36BSx0BizWvRmUSfduL2BqUWs072sfauyeLdXQg=; b=lJTscizXpzyCmwy/HE8Feeewa6SS7rHMgPSwg2AmXftTZ9D+qy9fERTXZpwnANgOZf 7PRMIFrrq+Er7972BTK2bBiRanvzrQ/C2/Mh0auPcPdkqnZjgT7nvCWBWg5MUpSNF4zh TdLrG/rvQrhd3837TO7wg0/K687FlR1S4LL0zyx9TYpVmcyWomSO2XQXphFMfrSGwWtW XGJAq+TYhAcFKcrdHCjzBuwflQCSTwgEPr2ON/31kB1emxwo6addvfCRYSxEJtvtjR4j 0TNpQ+kFtYXGGA56KeMNGKhd4JdgU3d/jn8RkF04IWeEL+6lRFqeYC8G2NwjDUGt2I6Y W6EQ== X-Gm-Message-State: ABy/qLaJEpEk1oSYZl6tA/+1WqiE+64tU+HKGQJByBfXN4/eUyvkdCmk wFBg037pf41HZSfve9hL2OW++89luH9YTA6PwLSVRCQ7Cxb6WB1TTJ7OC6VRlgLDkGP57YHsQGY LsF5KgEjIH4ya6dDR8RNeweHBgw+la5l9gXD97AxoUH9ADTiZ3KsXYbwsTIX9fWRSiOZUtNUo9m Es3l4= X-Google-Smtp-Source: APBJJlEaCBdY7XESwGujH5gXlVHdQlBfDMUu00smIjJ2xdlT2GiDlASy4xUwjcgf79sZEE5+m6YOXw== X-Received: by 2002:a05:6a00:39a2:b0:667:e17e:85b7 with SMTP id fi34-20020a056a0039a200b00667e17e85b7mr10022838pfb.1.1688313304389; Sun, 02 Jul 2023 08:55:04 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: dbarboza@ventanamicro.com, Dickon Hood , Nazar Kazakov , William Salmon , Kiran Ostrolenk , Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Lawrence Hunter Subject: [PATCH v7 08/15] target/riscv: Add Zvbb ISA extension support Date: Sun, 2 Jul 2023 23:53:42 +0800 Message-Id: <20230702155354.2478495-9-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230702155354.2478495-1-max.chou@sifive.com> References: <20230702155354.2478495-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=max.chou@sifive.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1688313342888100017 Content-Type: text/plain; charset="utf-8" From: Dickon Hood This commit adds support for the Zvbb vector-crypto extension, which consists of the following instructions: * vrol.[vv,vx] * vror.[vv,vx,vi] * vbrev8.v * vrev8.v * vandn.[vv,vx] * vbrev.v * vclz.v * vctz.v * vcpop.v * vwsll.[vv,vx,vi] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov Co-authored-by: William Salmon Co-authored-by: Kiran Ostrolenk [max.chou@sifive.com: Fix imm mode of vror.vi] Signed-off-by: Nazar Kazakov Signed-off-by: William Salmon Signed-off-by: Kiran Ostrolenk Signed-off-by: Dickon Hood Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza [max.chou@sifive.com: Exposed x-zvbb property] --- target/riscv/cpu.c | 12 ++ target/riscv/cpu_cfg.h | 1 + target/riscv/helper.h | 62 +++++++++ target/riscv/insn32.decode | 20 +++ target/riscv/insn_trans/trans_rvvk.c.inc | 164 +++++++++++++++++++++++ target/riscv/vcrypto_helper.c | 138 +++++++++++++++++++ 6 files changed, 397 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 174ae9fe1a..7e24eef3f1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -111,6 +111,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), + ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb), ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc), ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), @@ -1185,6 +1186,16 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu= , Error **errp) return; } =20 + /* + * In principle Zve*x would also suffice here, were they supported + * in qemu + */ + if (cpu->cfg.ext_zvbb && !cpu->cfg.ext_zve32f) { + error_setg(errp, + "Vector crypto extensions require V or Zve* extensions"= ); + return; + } + if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) { error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensio= ns"); return; @@ -1690,6 +1701,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), =20 /* Vector cryptography extensions */ + DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false), DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), =20 DEFINE_PROP_END_OF_LIST(), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index b6e9bd2e99..0d43281dd7 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -83,6 +83,7 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; bool ext_zve64d; + bool ext_zvbb; bool ext_zvbc; bool ext_zmmul; bool ext_zvfh; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index be0f0f1058..fbb0ceca81 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1159,3 +1159,65 @@ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, en= v, i32) DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vror_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vror_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vror_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vror_vv_d, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vror_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vror_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vror_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vror_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vrol_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrol_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrol_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrol_vv_d, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vrol_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_5(vrev8_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev_v_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(vclz_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vclz_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vclz_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vclz_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vctz_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vctz_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vctz_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vctz_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vcpop_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vcpop_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vcpop_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vcpop_v_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vwsll_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsll_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsll_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsll_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsll_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsll_vx_w, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vandn_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 52cd92e262..aa6d3185a2 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -37,6 +37,7 @@ %imm_u 12:s20 !function=3Dex_shift_12 %imm_bs 30:2 !function=3Dex_shift_3 %imm_rnum 20:4 +%imm_z6 26:1 15:5 =20 # Argument sets: &empty @@ -82,6 +83,7 @@ @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=3D1 %rs2 %rs1 = %rd @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=3D0 %rs2 %rs1 = %rd +@r2_zimm6 ..... . vm:1 ..... ..... ... ..... ....... &rmrr %rs2 rs1=3D%i= mm_z6 %rd @r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd @r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 @@ -914,3 +916,21 @@ vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_= vm vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm + +# *** Zvbb vector crypto extension *** +vrol_vv 010101 . ..... ..... 000 ..... 1010111 @r_vm +vrol_vx 010101 . ..... ..... 100 ..... 1010111 @r_vm +vror_vv 010100 . ..... ..... 000 ..... 1010111 @r_vm +vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm +vror_vi 01010. . ..... ..... 011 ..... 1010111 @r2_zimm6 +vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm +vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm +vandn_vv 000001 . ..... ..... 000 ..... 1010111 @r_vm +vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm +vbrev_v 010010 . ..... 01010 010 ..... 1010111 @r2_vm +vclz_v 010010 . ..... 01100 010 ..... 1010111 @r2_vm +vctz_v 010010 . ..... 01101 010 ..... 1010111 @r2_vm +vcpop_v 010010 . ..... 01110 010 ..... 1010111 @r2_vm +vwsll_vv 110101 . ..... ..... 000 ..... 1010111 @r_vm +vwsll_vx 110101 . ..... ..... 100 ..... 1010111 @r_vm +vwsll_vi 110101 . ..... ..... 011 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index 552b08a2fd..0e4b337613 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -60,3 +60,167 @@ static bool vclmul_vx_check(DisasContext *s, arg_rmrr *= a) =20 GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check) GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check) + +/* + * Zvbb + */ + +#define GEN_OPIVI_GVEC_TRANS_CHECK(NAME, IMM_MODE, OPIVX, SUF, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + static gen_helper_opivx *const fns[4] =3D { \ + gen_helper_##OPIVX##_b, \ + gen_helper_##OPIVX##_h, \ + gen_helper_##OPIVX##_w, \ + gen_helper_##OPIVX##_d, \ + }; \ + return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew], \ + IMM_MODE); \ + } \ + return false; \ + } + +#define GEN_OPIVV_GVEC_TRANS_CHECK(NAME, SUF, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + static gen_helper_gvec_4_ptr *const fns[4] =3D { = \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ + } \ + return false; \ + } + +#define GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(NAME, SUF, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + static gen_helper_opivx *const fns[4] =3D { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, \ + fns[s->sew]); \ + } \ + return false; \ + } + +static bool zvbb_vv_check(DisasContext *s, arg_rmrr *a) +{ + return opivv_check(s, a) && s->cfg_ptr->ext_zvbb =3D=3D true; +} + +static bool zvbb_vx_check(DisasContext *s, arg_rmrr *a) +{ + return opivx_check(s, a) && s->cfg_ptr->ext_zvbb =3D=3D true; +} + +/* vrol.v[vx] */ +GEN_OPIVV_GVEC_TRANS_CHECK(vrol_vv, rotlv, zvbb_vv_check) +GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vrol_vx, rotls, zvbb_vx_check) + +/* vror.v[vxi] */ +GEN_OPIVV_GVEC_TRANS_CHECK(vror_vv, rotrv, zvbb_vv_check) +GEN_OPIVX_GVEC_SHIFT_TRANS_CHECK(vror_vx, rotrs, zvbb_vx_check) +GEN_OPIVI_GVEC_TRANS_CHECK(vror_vi, IMM_TRUNC_SEW, vror_vx, rotri, zvbb_vx= _check) + +#define GEN_OPIVX_GVEC_TRANS_CHECK(NAME, SUF, CHECK) \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ + { \ + if (CHECK(s, a)) { \ + static gen_helper_opivx *const fns[4] =3D { = \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \ + } \ + return false; \ + } + +/* vandn.v[vx] */ +GEN_OPIVV_GVEC_TRANS_CHECK(vandn_vv, andc, zvbb_vv_check) +GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvbb_vx_check) + +#define GEN_OPIV_TRANS(NAME, CHECK) = \ + static bool trans_##NAME(DisasContext *s, arg_rmr *a) = \ + { = \ + if (CHECK(s, a)) { = \ + uint32_t data =3D 0; = \ + static gen_helper_gvec_3_ptr *const fns[4] =3D { = \ + gen_helper_##NAME##_b, = \ + gen_helper_##NAME##_h, = \ + gen_helper_##NAME##_w, = \ + gen_helper_##NAME##_d, = \ + }; = \ + TCGLabel *over =3D gen_new_label(); = \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); = \ + = \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); = \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); = \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s= ); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), = \ + vreg_ofs(s, a->rs2), cpu_env, = \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,= \ + data, fns[s->sew]); = \ + mark_vs_dirty(s); = \ + gen_set_label(over); = \ + return true; = \ + } = \ + return false; = \ + } + +static bool zvbb_opiv_check(DisasContext *s, arg_rmr *a) +{ + return s->cfg_ptr->ext_zvbb =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + vext_check_ss(s, a->rd, a->rs2, a->vm); +} + +GEN_OPIV_TRANS(vbrev8_v, zvbb_opiv_check) +GEN_OPIV_TRANS(vrev8_v, zvbb_opiv_check) +GEN_OPIV_TRANS(vbrev_v, zvbb_opiv_check) +GEN_OPIV_TRANS(vclz_v, zvbb_opiv_check) +GEN_OPIV_TRANS(vctz_v, zvbb_opiv_check) +GEN_OPIV_TRANS(vcpop_v, zvbb_opiv_check) + +static bool vwsll_vv_check(DisasContext *s, arg_rmrr *a) +{ + return s->cfg_ptr->ext_zvbb && opivv_widen_check(s, a); +} + +static bool vwsll_vx_check(DisasContext *s, arg_rmrr *a) +{ + return s->cfg_ptr->ext_zvbb && opivx_widen_check(s, a); +} + +/* OPIVI without GVEC IR */ +#define GEN_OPIVI_WIDEN_TRANS(NAME, IMM_MODE, OPIVX, CHECK) = \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) = \ + { = \ + if (CHECK(s, a)) { = \ + static gen_helper_opivx *const fns[3] =3D { = \ + gen_helper_##OPIVX##_b, = \ + gen_helper_##OPIVX##_h, = \ + gen_helper_##OPIVX##_w, = \ + }; = \ + return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], = s, \ + IMM_MODE); = \ + } = \ + return false; = \ + } + +GEN_OPIVV_WIDEN_TRANS(vwsll_vv, vwsll_vv_check) +GEN_OPIVX_WIDEN_TRANS(vwsll_vx, vwsll_vx_check) +GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 8b7c63d499..11239b59d6 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" #include "qemu/bitops.h" +#include "qemu/bswap.h" #include "cpu.h" #include "exec/memop.h" #include "exec/exec-all.h" @@ -57,3 +58,140 @@ RVVCALL(OPIVV2, vclmulh_vv, OP_UUU_D, H8, H8, H8, clmul= h64) GEN_VEXT_VV(vclmulh_vv, 8) RVVCALL(OPIVX2, vclmulh_vx, OP_UUU_D, H8, H8, clmulh64) GEN_VEXT_VX(vclmulh_vx, 8) + +RVVCALL(OPIVV2, vror_vv_b, OP_UUU_B, H1, H1, H1, ror8) +RVVCALL(OPIVV2, vror_vv_h, OP_UUU_H, H2, H2, H2, ror16) +RVVCALL(OPIVV2, vror_vv_w, OP_UUU_W, H4, H4, H4, ror32) +RVVCALL(OPIVV2, vror_vv_d, OP_UUU_D, H8, H8, H8, ror64) +GEN_VEXT_VV(vror_vv_b, 1) +GEN_VEXT_VV(vror_vv_h, 2) +GEN_VEXT_VV(vror_vv_w, 4) +GEN_VEXT_VV(vror_vv_d, 8) + +RVVCALL(OPIVX2, vror_vx_b, OP_UUU_B, H1, H1, ror8) +RVVCALL(OPIVX2, vror_vx_h, OP_UUU_H, H2, H2, ror16) +RVVCALL(OPIVX2, vror_vx_w, OP_UUU_W, H4, H4, ror32) +RVVCALL(OPIVX2, vror_vx_d, OP_UUU_D, H8, H8, ror64) +GEN_VEXT_VX(vror_vx_b, 1) +GEN_VEXT_VX(vror_vx_h, 2) +GEN_VEXT_VX(vror_vx_w, 4) +GEN_VEXT_VX(vror_vx_d, 8) + +RVVCALL(OPIVV2, vrol_vv_b, OP_UUU_B, H1, H1, H1, rol8) +RVVCALL(OPIVV2, vrol_vv_h, OP_UUU_H, H2, H2, H2, rol16) +RVVCALL(OPIVV2, vrol_vv_w, OP_UUU_W, H4, H4, H4, rol32) +RVVCALL(OPIVV2, vrol_vv_d, OP_UUU_D, H8, H8, H8, rol64) +GEN_VEXT_VV(vrol_vv_b, 1) +GEN_VEXT_VV(vrol_vv_h, 2) +GEN_VEXT_VV(vrol_vv_w, 4) +GEN_VEXT_VV(vrol_vv_d, 8) + +RVVCALL(OPIVX2, vrol_vx_b, OP_UUU_B, H1, H1, rol8) +RVVCALL(OPIVX2, vrol_vx_h, OP_UUU_H, H2, H2, rol16) +RVVCALL(OPIVX2, vrol_vx_w, OP_UUU_W, H4, H4, rol32) +RVVCALL(OPIVX2, vrol_vx_d, OP_UUU_D, H8, H8, rol64) +GEN_VEXT_VX(vrol_vx_b, 1) +GEN_VEXT_VX(vrol_vx_h, 2) +GEN_VEXT_VX(vrol_vx_w, 4) +GEN_VEXT_VX(vrol_vx_d, 8) + +static uint64_t brev8(uint64_t val) +{ + val =3D ((val & 0x5555555555555555ull) << 1) | + ((val & 0xAAAAAAAAAAAAAAAAull) >> 1); + val =3D ((val & 0x3333333333333333ull) << 2) | + ((val & 0xCCCCCCCCCCCCCCCCull) >> 2); + val =3D ((val & 0x0F0F0F0F0F0F0F0Full) << 4) | + ((val & 0xF0F0F0F0F0F0F0F0ull) >> 4); + + return val; +} + +RVVCALL(OPIVV1, vbrev8_v_b, OP_UU_B, H1, H1, brev8) +RVVCALL(OPIVV1, vbrev8_v_h, OP_UU_H, H2, H2, brev8) +RVVCALL(OPIVV1, vbrev8_v_w, OP_UU_W, H4, H4, brev8) +RVVCALL(OPIVV1, vbrev8_v_d, OP_UU_D, H8, H8, brev8) +GEN_VEXT_V(vbrev8_v_b, 1) +GEN_VEXT_V(vbrev8_v_h, 2) +GEN_VEXT_V(vbrev8_v_w, 4) +GEN_VEXT_V(vbrev8_v_d, 8) + +#define DO_IDENTITY(a) (a) +RVVCALL(OPIVV1, vrev8_v_b, OP_UU_B, H1, H1, DO_IDENTITY) +RVVCALL(OPIVV1, vrev8_v_h, OP_UU_H, H2, H2, bswap16) +RVVCALL(OPIVV1, vrev8_v_w, OP_UU_W, H4, H4, bswap32) +RVVCALL(OPIVV1, vrev8_v_d, OP_UU_D, H8, H8, bswap64) +GEN_VEXT_V(vrev8_v_b, 1) +GEN_VEXT_V(vrev8_v_h, 2) +GEN_VEXT_V(vrev8_v_w, 4) +GEN_VEXT_V(vrev8_v_d, 8) + +#define DO_ANDN(a, b) ((a) & ~(b)) +RVVCALL(OPIVV2, vandn_vv_b, OP_UUU_B, H1, H1, H1, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_h, OP_UUU_H, H2, H2, H2, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_w, OP_UUU_W, H4, H4, H4, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_d, OP_UUU_D, H8, H8, H8, DO_ANDN) +GEN_VEXT_VV(vandn_vv_b, 1) +GEN_VEXT_VV(vandn_vv_h, 2) +GEN_VEXT_VV(vandn_vv_w, 4) +GEN_VEXT_VV(vandn_vv_d, 8) + +RVVCALL(OPIVX2, vandn_vx_b, OP_UUU_B, H1, H1, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_h, OP_UUU_H, H2, H2, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_w, OP_UUU_W, H4, H4, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_d, OP_UUU_D, H8, H8, DO_ANDN) +GEN_VEXT_VX(vandn_vx_b, 1) +GEN_VEXT_VX(vandn_vx_h, 2) +GEN_VEXT_VX(vandn_vx_w, 4) +GEN_VEXT_VX(vandn_vx_d, 8) + +RVVCALL(OPIVV1, vbrev_v_b, OP_UU_B, H1, H1, revbit8) +RVVCALL(OPIVV1, vbrev_v_h, OP_UU_H, H2, H2, revbit16) +RVVCALL(OPIVV1, vbrev_v_w, OP_UU_W, H4, H4, revbit32) +RVVCALL(OPIVV1, vbrev_v_d, OP_UU_D, H8, H8, revbit64) +GEN_VEXT_V(vbrev_v_b, 1) +GEN_VEXT_V(vbrev_v_h, 2) +GEN_VEXT_V(vbrev_v_w, 4) +GEN_VEXT_V(vbrev_v_d, 8) + +RVVCALL(OPIVV1, vclz_v_b, OP_UU_B, H1, H1, clz8) +RVVCALL(OPIVV1, vclz_v_h, OP_UU_H, H2, H2, clz16) +RVVCALL(OPIVV1, vclz_v_w, OP_UU_W, H4, H4, clz32) +RVVCALL(OPIVV1, vclz_v_d, OP_UU_D, H8, H8, clz64) +GEN_VEXT_V(vclz_v_b, 1) +GEN_VEXT_V(vclz_v_h, 2) +GEN_VEXT_V(vclz_v_w, 4) +GEN_VEXT_V(vclz_v_d, 8) + +RVVCALL(OPIVV1, vctz_v_b, OP_UU_B, H1, H1, ctz8) +RVVCALL(OPIVV1, vctz_v_h, OP_UU_H, H2, H2, ctz16) +RVVCALL(OPIVV1, vctz_v_w, OP_UU_W, H4, H4, ctz32) +RVVCALL(OPIVV1, vctz_v_d, OP_UU_D, H8, H8, ctz64) +GEN_VEXT_V(vctz_v_b, 1) +GEN_VEXT_V(vctz_v_h, 2) +GEN_VEXT_V(vctz_v_w, 4) +GEN_VEXT_V(vctz_v_d, 8) + +RVVCALL(OPIVV1, vcpop_v_b, OP_UU_B, H1, H1, ctpop8) +RVVCALL(OPIVV1, vcpop_v_h, OP_UU_H, H2, H2, ctpop16) +RVVCALL(OPIVV1, vcpop_v_w, OP_UU_W, H4, H4, ctpop32) +RVVCALL(OPIVV1, vcpop_v_d, OP_UU_D, H8, H8, ctpop64) +GEN_VEXT_V(vcpop_v_b, 1) +GEN_VEXT_V(vcpop_v_h, 2) +GEN_VEXT_V(vcpop_v_w, 4) +GEN_VEXT_V(vcpop_v_d, 8) + +#define DO_SLL(N, M) (N << (M & (sizeof(N) * 8 - 1))) +RVVCALL(OPIVV2, vwsll_vv_b, WOP_UUU_B, H2, H1, H1, DO_SLL) +RVVCALL(OPIVV2, vwsll_vv_h, WOP_UUU_H, H4, H2, H2, DO_SLL) +RVVCALL(OPIVV2, vwsll_vv_w, WOP_UUU_W, H8, H4, H4, DO_SLL) +GEN_VEXT_VV(vwsll_vv_b, 2) +GEN_VEXT_VV(vwsll_vv_h, 4) +GEN_VEXT_VV(vwsll_vv_w, 8) + +RVVCALL(OPIVX2, vwsll_vx_b, WOP_UUU_B, H2, H1, DO_SLL) +RVVCALL(OPIVX2, vwsll_vx_h, WOP_UUU_H, H4, H2, DO_SLL) +RVVCALL(OPIVX2, vwsll_vx_w, WOP_UUU_W, H8, H4, DO_SLL) +GEN_VEXT_VX(vwsll_vx_b, 2) +GEN_VEXT_VX(vwsll_vx_h, 4) +GEN_VEXT_VX(vwsll_vx_w, 8) --=20 2.34.1 From nobody Sun May 19 01:15:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) 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Co-authored-by: Lawrence Hunter Co-authored-by: William Salmon [max.chou@sifive.com: Replaced vstart checking by TCG op] Signed-off-by: Lawrence Hunter Signed-off-by: William Salmon Signed-off-by: Nazar Kazakov Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza [max.chou@sifive.com: Imported aes-round.h and exposed x-zvkned property] [max.chou@sifive.com: Fixed endian issues and replaced the vstart & vl egs checking by helper function] --- target/riscv/cpu.c | 4 +- target/riscv/cpu_cfg.h | 1 + target/riscv/helper.h | 14 ++ target/riscv/insn32.decode | 14 ++ target/riscv/insn_trans/trans_rvvk.c.inc | 147 +++++++++++++++++ target/riscv/vcrypto_helper.c | 202 +++++++++++++++++++++++ 6 files changed, 381 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7e24eef3f1..9b754122ac 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -118,6 +118,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), + ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), @@ -1190,7 +1191,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) * In principle Zve*x would also suffice here, were they supported * in qemu */ - if (cpu->cfg.ext_zvbb && !cpu->cfg.ext_zve32f) { + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned) && !cpu->cfg.ext_zve32f= ) { error_setg(errp, "Vector crypto extensions require V or Zve* extensions"= ); return; @@ -1703,6 +1704,7 @@ static Property riscv_cpu_extensions[] =3D { /* Vector cryptography extensions */ DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false), DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), + DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), =20 DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 0d43281dd7..13dbc11e90 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -85,6 +85,7 @@ struct RISCVCPUConfig { bool ext_zve64d; bool ext_zvbb; bool ext_zvbc; + bool ext_zvkned; bool ext_zmmul; bool ext_zvfh; bool ext_zvfhmin; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index fbb0ceca81..24b434c8a2 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1221,3 +1221,17 @@ DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, en= v, i32) DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_2(egs_check, void, i32, env) + +DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesem_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesem_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) +DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32) +DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index aa6d3185a2..7e0295d493 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -75,6 +75,7 @@ @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd @r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd +@r2_vm_1 ...... . ..... ..... ... ..... ....... &rmr vm=3D1 %rs2 %rd @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd @@ -934,3 +935,16 @@ vcpop_v 010010 . ..... 01110 010 ..... 1010111 @r2= _vm vwsll_vv 110101 . ..... ..... 000 ..... 1010111 @r_vm vwsll_vx 110101 . ..... ..... 100 ..... 1010111 @r_vm vwsll_vi 110101 . ..... ..... 011 ..... 1010111 @r_vm + +# *** Zvkned vector crypto extension *** +vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1 +vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 +vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 +vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 +vaesem_vv 101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1 +vaesem_vs 101001 1 ..... 00010 010 ..... 1110111 @r2_vm_1 +vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 +vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 +vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 +vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index 0e4b337613..817353f4d3 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -224,3 +224,150 @@ static bool vwsll_vx_check(DisasContext *s, arg_rmrr = *a) GEN_OPIVV_WIDEN_TRANS(vwsll_vv, vwsll_vv_check) GEN_OPIVX_WIDEN_TRANS(vwsll_vx, vwsll_vx_check) GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check) + +/* + * Zvkned + */ + +#define ZVKNED_EGS 4 + +#define GEN_V_UNMASKED_TRANS(NAME, CHECK, EGS) = \ + static bool trans_##NAME(DisasContext *s, arg_##NAME *a) = \ + { = \ + if (CHECK(s, a)) { = \ + TCGv_ptr rd_v, rs2_v; = \ + TCGv_i32 desc, egs; = \ + uint32_t data =3D 0; = \ + TCGLabel *over =3D gen_new_label(); = \ + = \ + if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { = \ + /* save opcode for unwinding in case we throw an exception= */ \ + decode_save_opc(s); = \ + egs =3D tcg_constant_i32(EGS); = \ + gen_helper_egs_check(egs, cpu_env); = \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);= \ + } = \ + = \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); = \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); = \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s= ); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ + rd_v =3D tcg_temp_new_ptr(); = \ + rs2_v =3D tcg_temp_new_ptr(); = \ + desc =3D tcg_constant_i32( = \ + simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data= )); \ + tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); = \ + tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); = \ + gen_helper_##NAME(rd_v, rs2_v, cpu_env, desc); = \ + mark_vs_dirty(s); = \ + gen_set_label(over); = \ + return true; = \ + } = \ + return false; = \ + } + +static bool vaes_check_vv(DisasContext *s, arg_rmr *a) +{ + int egw_bytes =3D ZVKNED_EGS << s->sew; + return s->cfg_ptr->ext_zvkned =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + MAXSZ(s) >=3D egw_bytes && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul) && + s->sew =3D=3D MO_32; +} + +static bool vaes_check_overlap(DisasContext *s, int vd, int vs2) +{ + int8_t op_size =3D s->lmul <=3D 0 ? 1 : 1 << s->lmul; + return !is_overlapped(vd, op_size, vs2, 1); +} + +static bool vaes_check_vs(DisasContext *s, arg_rmr *a) +{ + int egw_bytes =3D ZVKNED_EGS << s->sew; + return vaes_check_overlap(s, a->rd, a->rs2) && + MAXSZ(s) >=3D egw_bytes && + s->cfg_ptr->ext_zvkned =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + require_align(a->rd, s->lmul) && + s->sew =3D=3D MO_32; +} + +GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv, ZVKNED_EGS) +GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs, ZVKNED_EGS) +GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv, ZVKNED_EGS) +GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs, ZVKNED_EGS) +GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv, ZVKNED_EGS) +GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs, ZVKNED_EGS) +GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs, ZVKNED_EGS) +GEN_V_UNMASKED_TRANS(vaesem_vv, vaes_check_vv, ZVKNED_EGS) +GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS) + +#define GEN_VI_UNMASKED_TRANS(NAME, CHECK, EGS) = \ + static bool trans_##NAME(DisasContext *s, arg_##NAME *a) = \ + { = \ + if (CHECK(s, a)) { = \ + TCGv_ptr rd_v, rs2_v; = \ + TCGv_i32 uimm_v, desc, egs; = \ + uint32_t data =3D 0; = \ + TCGLabel *over =3D gen_new_label(); = \ + = \ + if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { = \ + /* save opcode for unwinding in case we throw an exception= */ \ + decode_save_opc(s); = \ + egs =3D tcg_constant_i32(EGS); = \ + gen_helper_egs_check(egs, cpu_env); = \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);= \ + } = \ + = \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); = \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); = \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s= ); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ + = \ + rd_v =3D tcg_temp_new_ptr(); = \ + rs2_v =3D tcg_temp_new_ptr(); = \ + uimm_v =3D tcg_constant_i32(a->rs1); = \ + desc =3D tcg_constant_i32( = \ + simd_desc(s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, data= )); \ + tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); = \ + tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); = \ + gen_helper_##NAME(rd_v, rs2_v, uimm_v, cpu_env, desc); = \ + mark_vs_dirty(s); = \ + gen_set_label(over); = \ + return true; = \ + } = \ + return false; = \ + } + +static bool vaeskf1_check(DisasContext *s, arg_vaeskf1_vi *a) +{ + int egw_bytes =3D ZVKNED_EGS << s->sew; + return s->cfg_ptr->ext_zvkned =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + MAXSZ(s) >=3D egw_bytes && + s->sew =3D=3D MO_32 && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul); +} + +static bool vaeskf2_check(DisasContext *s, arg_vaeskf2_vi *a) +{ + int egw_bytes =3D ZVKNED_EGS << s->sew; + return s->cfg_ptr->ext_zvkned =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + MAXSZ(s) >=3D egw_bytes && + s->sew =3D=3D MO_32 && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul); +} + +GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check, ZVKNED_EGS) +GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 11239b59d6..73cd1f91d9 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -22,6 +22,8 @@ #include "qemu/bitops.h" #include "qemu/bswap.h" #include "cpu.h" +#include "crypto/aes.h" +#include "crypto/aes-round.h" #include "exec/memop.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -195,3 +197,203 @@ RVVCALL(OPIVX2, vwsll_vx_w, WOP_UUU_W, H8, H4, DO_SLL) GEN_VEXT_VX(vwsll_vx_b, 2) GEN_VEXT_VX(vwsll_vx_h, 4) GEN_VEXT_VX(vwsll_vx_w, 8) + +void HELPER(egs_check)(uint32_t egs, CPURISCVState *env) +{ + uint32_t vl =3D env->vl; + uint32_t vstart =3D env->vstart; + + if (vl % egs !=3D 0 || vstart % egs !=3D 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } +} + +static inline void xor_round_key(AESState *round_state, AESState *round_ke= y) +{ + round_state->v =3D round_state->v ^ round_key->v; +} + +#define GEN_ZVKNED_HELPER_VV(NAME, ...) \ + void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \ + uint32_t desc) \ + { \ + uint32_t vl =3D env->vl; = \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); = \ + uint32_t vta =3D vext_vta(desc); = \ + \ + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { = \ + AESState round_key; \ + round_key.d[0] =3D *((uint64_t *)vs2 + H8(i * 2 + 0)); = \ + round_key.d[1] =3D *((uint64_t *)vs2 + H8(i * 2 + 1)); = \ + AESState round_state; \ + round_state.d[0] =3D *((uint64_t *)vd + H8(i * 2 + 0)); = \ + round_state.d[1] =3D *((uint64_t *)vd + H8(i * 2 + 1)); = \ + __VA_ARGS__; \ + *((uint64_t *)vd + H8(i * 2 + 0)) =3D round_state.d[0]; = \ + *((uint64_t *)vd + H8(i * 2 + 1)) =3D round_state.d[1]; = \ + } \ + env->vstart =3D 0; = \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \ + } + +#define GEN_ZVKNED_HELPER_VS(NAME, ...) \ + void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \ + uint32_t desc) \ + { \ + uint32_t vl =3D env->vl; = \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); = \ + uint32_t vta =3D vext_vta(desc); = \ + \ + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { = \ + AESState round_key; \ + round_key.d[0] =3D *((uint64_t *)vs2 + H8(0)); = \ + round_key.d[1] =3D *((uint64_t *)vs2 + H8(1)); = \ + AESState round_state; \ + round_state.d[0] =3D *((uint64_t *)vd + H8(i * 2 + 0)); = \ + round_state.d[1] =3D *((uint64_t *)vd + H8(i * 2 + 1)); = \ + __VA_ARGS__; \ + *((uint64_t *)vd + H8(i * 2 + 0)) =3D round_state.d[0]; = \ + *((uint64_t *)vd + H8(i * 2 + 1)) =3D round_state.d[1]; = \ + } \ + env->vstart =3D 0; = \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \ + } + +GEN_ZVKNED_HELPER_VV(vaesef_vv, aesenc_SB_SR_AK(&round_state, + &round_state, + &round_key, + false);) +GEN_ZVKNED_HELPER_VS(vaesef_vs, aesenc_SB_SR_AK(&round_state, + &round_state, + &round_key, + false);) +GEN_ZVKNED_HELPER_VV(vaesdf_vv, aesdec_ISB_ISR_AK(&round_state, + &round_state, + &round_key, + false);) +GEN_ZVKNED_HELPER_VS(vaesdf_vs, aesdec_ISB_ISR_AK(&round_state, + &round_state, + &round_key, + false);) +GEN_ZVKNED_HELPER_VV(vaesem_vv, aesenc_SB_SR_MC_AK(&round_state, + &round_state, + &round_key, + false);) +GEN_ZVKNED_HELPER_VS(vaesem_vs, aesenc_SB_SR_MC_AK(&round_state, + &round_state, + &round_key, + false);) +GEN_ZVKNED_HELPER_VV(vaesdm_vv, aesdec_ISB_ISR_AK_IMC(&round_state, + &round_state, + &round_key, + false);) +GEN_ZVKNED_HELPER_VS(vaesdm_vs, aesdec_ISB_ISR_AK_IMC(&round_state, + &round_state, + &round_key, + false);) +GEN_ZVKNED_HELPER_VS(vaesz_vs, xor_round_key(&round_state, &round_key);) + +void HELPER(vaeskf1_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, + CPURISCVState *env, uint32_t desc) +{ + uint32_t *vd =3D vd_vptr; + uint32_t *vs2 =3D vs2_vptr; + uint32_t vl =3D env->vl; + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); + uint32_t vta =3D vext_vta(desc); + + uimm &=3D 0b1111; + if (uimm > 10 || uimm =3D=3D 0) { + uimm ^=3D 0b1000; + } + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + uint32_t rk[8]; + static const uint32_t rcon[] =3D { + 0x01000000, 0x02000000, 0x04000000, 0x08000000, 0x10000000, + 0x20000000, 0x40000000, 0x80000000, 0x1B000000, 0x36000000, + }; + + rk[0] =3D bswap32(vs2[i * 4 + H4(0)]); + rk[1] =3D bswap32(vs2[i * 4 + H4(1)]); + rk[2] =3D bswap32(vs2[i * 4 + H4(2)]); + rk[3] =3D bswap32(vs2[i * 4 + H4(3)]); + uint32_t tmp =3D rol32(rk[3], 8); + + rk[4] =3D rk[0] ^ (((uint32_t)AES_sbox[(tmp >> 24) & 0xff] << 24) | + ((uint32_t)AES_sbox[(tmp >> 16) & 0xff] << 16) | + ((uint32_t)AES_sbox[(tmp >> 8) & 0xff] << 8) | + ((uint32_t)AES_sbox[(tmp >> 0) & 0xff] << 0)) + ^ rcon[uimm - 1]; + rk[5] =3D rk[1] ^ rk[4]; + rk[6] =3D rk[2] ^ rk[5]; + rk[7] =3D rk[3] ^ rk[6]; + + vd[i * 4 + H4(0)] =3D bswap32(rk[4]); + vd[i * 4 + H4(1)] =3D bswap32(rk[5]); + vd[i * 4 + H4(2)] =3D bswap32(rk[6]); + vd[i * 4 + H4(3)] =3D bswap32(rk[7]); + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); +} + +void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, + CPURISCVState *env, uint32_t desc) +{ + uint32_t *vd =3D vd_vptr; + uint32_t *vs2 =3D vs2_vptr; + uint32_t vl =3D env->vl; + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); + uint32_t vta =3D vext_vta(desc); + + uimm &=3D 0b1111; + if (uimm > 14 || uimm < 2) { + uimm ^=3D 0b1000; + } + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + uint32_t rk[12]; + static const uint32_t rcon[] =3D { + 0x01000000, 0x02000000, 0x04000000, 0x08000000, 0x10000000, + 0x20000000, 0x40000000, 0x80000000, 0x1B000000, 0x36000000, + }; + + rk[0] =3D bswap32(vd[i * 4 + H4(0)]); + rk[1] =3D bswap32(vd[i * 4 + H4(1)]); + rk[2] =3D bswap32(vd[i * 4 + H4(2)]); + rk[3] =3D bswap32(vd[i * 4 + H4(3)]); + rk[4] =3D bswap32(vs2[i * 4 + H4(0)]); + rk[5] =3D bswap32(vs2[i * 4 + H4(1)]); + rk[6] =3D bswap32(vs2[i * 4 + H4(2)]); + rk[7] =3D bswap32(vs2[i * 4 + H4(3)]); + + if (uimm % 2 =3D=3D 0) { + uint32_t tmp =3D rol32(rk[7], 8); + rk[8] =3D rk[0] ^ (((uint32_t)AES_sbox[(tmp >> 24) & 0xff] << = 24) | + ((uint32_t)AES_sbox[(tmp >> 16) & 0xff] << 16= ) | + ((uint32_t)AES_sbox[(tmp >> 8) & 0xff] << 8) | + ((uint32_t)AES_sbox[(tmp >> 0) & 0xff] << 0)) + ^ rcon[(uimm - 1) / 2]; + } else { + rk[8] =3D rk[0] ^ (((uint32_t)AES_sbox[(rk[7] >> 24) & 0xff] <= < 24) | + ((uint32_t)AES_sbox[(rk[7] >> 16) & 0xff] << = 16) | + ((uint32_t)AES_sbox[(rk[7] >> 8) & 0xff] << 8= ) | + ((uint32_t)AES_sbox[(rk[7] >> 0) & 0xff] << 0= )); + } + rk[9] =3D rk[1] ^ rk[8]; + rk[10] =3D rk[2] ^ rk[9]; + rk[11] =3D rk[3] ^ rk[10]; + + vd[i * 4 + H4(0)] =3D bswap32(rk[8]); + vd[i * 4 + H4(1)] =3D bswap32(rk[9]); + vd[i * 4 + H4(2)] =3D bswap32(rk[10]); + vd[i * 4 + H4(3)] =3D bswap32(rk[11]); + } + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); +} --=20 2.34.1 From nobody Sun May 19 01:15:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1688313485; cv=none; d=zohomail.com; s=zohoarc; b=iKU1UNkP11iU8tTVckj51mnsfuRt26PphqX3si90tz5IoYBK8R5+8ZjG98f0d9L96PgNgFNQY+ocVHUQrJfxqUN4gb4ouCp3SQ83dFeeXQdds/5ZxChBxQTF1gQ1EKL12hXNDfTqdLubvxL0FKjOckFn5V50EosFC8q6Mk4llU0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1688313485; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PyMD7p7TJbZi4xxjOPLq0g5HXJbgJTY945/N9q5fuNY=; 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[125.228.20.175]) by smtp.gmail.com with ESMTPSA id y19-20020aa78553000000b0066f37665a63sm8231969pfn.73.2023.07.02.08.55.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 08:55:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1688313314; x=1690905314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PyMD7p7TJbZi4xxjOPLq0g5HXJbgJTY945/N9q5fuNY=; b=AeBVo35zbLjGJ+gRiD8MfGmCdcas8Ud3zaoGXm9HQwKGcBdlPD2e0GdfBZkDYfGZLp 77x4mEhzxZr2Sxm1XW9SNCWUViECOLMqNDxGpj1n/yjgWJdcdl44WQOgWM5nVc6l1Q16 xC4AdkAP9l3BPBi9JqKSECiTKPxwdQ7Yv/6V1AGXrKFA3pAE/OHWgvBZ7nTR/MUHrHu9 p/M7EwBRmA1CNEplCPZOrFqvS0AfKHORuK7EsIDPLNnX8Q8myngO+idrpB9kkd4dwtpQ mVpByQrYOY7fjgOcTDNwv1XuJwicyquDbm+kGScqGDge6i5QM+AWp2HFt6QKGbQY6hAl pWOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688313314; x=1690905314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PyMD7p7TJbZi4xxjOPLq0g5HXJbgJTY945/N9q5fuNY=; b=NINQF6GbxrzFIYaKUK5VXh5yblNkdnTrL/vH7AJGlFAmVuVp5Sj+IO9MQ9tNzvalwy Uzt8esvCcLYmFSUiRT5/dwcXvpxK0mPwdp0Sj7HDRDDZeuW0fcWE4pRW4Gw+H6rBwo7f /0NaXot++KCfhgEzYSxl5bPoUvQ3v2V5/OS8ChzTeksZFM7RlzI/OiH7m9HgAKgwdD9L /A1kyOQrKvBA+xQlD8cc9px8qsF4SU/SJs+Un/1OYcTIF43KlQn698EfsdCERFJKcpHC zU3FcOBUIcM/V18NReR4kIFPGuvDuW4d/nXVIa3c8MII7HdqeFTP1faAIUtiuDdNaBqu eW4g== X-Gm-Message-State: ABy/qLaCxuE7W7oNLoAoGtAb0OZKpl2DPjky+d9Bls96mpjKWWcPeVA+ 0VOqkeCsMvfEGc7CzBs9yo+2ZwGiic4LENMy+PiXRaHEKhW2HhamEJ1Yu4PCGXTBwH4NagGnw7w lzT+cwbqIFXtd+6LXPwKRd6aHtocVnNrCohWK8SDkEq/c0D7YNtjKeoaAw2LnWth3jR3R3ArX6J hzERU= X-Google-Smtp-Source: APBJJlFa7pYgw5rfULnFUuKK75a2BqicxihoNGd8Wx1LHdqNf+uh3eOdZmJ8eD0SX/AlN16pvishig== X-Received: by 2002:a05:6a20:a10b:b0:12e:641b:454a with SMTP id q11-20020a056a20a10b00b0012e641b454amr955537pzk.30.1688313314093; Sun, 02 Jul 2023 08:55:14 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: dbarboza@ventanamicro.com, Kiran Ostrolenk , Nazar Kazakov , Lawrence Hunter , Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei Subject: [PATCH v7 10/15] target/riscv: Add Zvknh ISA extension support Date: Sun, 2 Jul 2023 23:53:44 +0800 Message-Id: <20230702155354.2478495-11-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230702155354.2478495-1-max.chou@sifive.com> References: <20230702155354.2478495-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=max.chou@sifive.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1688313487348100003 Content-Type: text/plain; charset="utf-8" From: Kiran Ostrolenk This commit adds support for the Zvknh vector-crypto extension, which consists of the following instructions: * vsha2ms.vv * vsha2c[hl].vv Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Nazar Kazakov Co-authored-by: Lawrence Hunter [max.chou@sifive.com: Replaced vstart checking by TCG op] Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter Signed-off-by: Kiran Ostrolenk Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza [max.chou@sifive.com: Exposed x-zvknha & x-zvknhb properties] [max.chou@sifive.com: Replaced SEW selection to happened during translation] --- target/riscv/cpu.c | 13 +- target/riscv/cpu_cfg.h | 2 + target/riscv/helper.h | 6 + target/riscv/insn32.decode | 5 + target/riscv/insn_trans/trans_rvvk.c.inc | 129 ++++++++++++ target/riscv/vcrypto_helper.c | 238 +++++++++++++++++++++++ 6 files changed, 390 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9b754122ac..3ca5ac209a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -119,6 +119,8 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), + ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), + ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), @@ -1191,14 +1193,17 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cp= u, Error **errp) * In principle Zve*x would also suffice here, were they supported * in qemu */ - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned) && !cpu->cfg.ext_zve32f= ) { + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha) = && + !cpu->cfg.ext_zve32f) { error_setg(errp, "Vector crypto extensions require V or Zve* extensions"= ); return; } =20 - if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) { - error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensio= ns"); + if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64f= ) { + error_setg( + errp, + "Zvbc and Zvknhb extensions require V or Zve64{f,d} extensions= "); return; } =20 @@ -1705,6 +1710,8 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false), DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), + DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false), + DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false), =20 DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 13dbc11e90..7144bfd228 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -86,6 +86,8 @@ struct RISCVCPUConfig { bool ext_zvbb; bool ext_zvbc; bool ext_zvkned; + bool ext_zvknha; + bool ext_zvknhb; bool ext_zmmul; bool ext_zvfh; bool ext_zvfhmin; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 24b434c8a2..66929b88cb 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1235,3 +1235,9 @@ DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32) DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32) + +DEF_HELPER_5(vsha2ms_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsha2ch32_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsha2ch64_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsha2cl32_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsha2cl64_vv, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 7e0295d493..d2cfb2729c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -948,3 +948,8 @@ vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_= vm_1 vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1 vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** Zvknh vector crypto extension *** +vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index 817353f4d3..a35be11b95 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -371,3 +371,132 @@ static bool vaeskf2_check(DisasContext *s, arg_vaeskf= 2_vi *a) =20 GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check, ZVKNED_EGS) GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS) + +/* + * Zvknh + */ + +#define ZVKNH_EGS 4 + +#define GEN_VV_UNMASKED_TRANS(NAME, CHECK, EGS) = \ + static bool trans_##NAME(DisasContext *s, arg_rmrr *a) = \ + { = \ + if (CHECK(s, a)) { = \ + uint32_t data =3D 0; = \ + TCGLabel *over =3D gen_new_label(); = \ + TCGv_i32 egs; = \ + = \ + if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { = \ + /* save opcode for unwinding in case we throw an exception= */ \ + decode_save_opc(s); = \ + egs =3D tcg_constant_i32(EGS); = \ + gen_helper_egs_check(egs, cpu_env); = \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);= \ + } = \ + = \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); = \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); = \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); = \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s= ); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); = \ + = \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), = \ + vreg_ofs(s, a->rs2), cpu_env, = \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8,= \ + data, gen_helper_##NAME); = \ + = \ + mark_vs_dirty(s); = \ + gen_set_label(over); = \ + return true; = \ + } = \ + return false; = \ + } + +static bool vsha_check_sew(DisasContext *s) +{ + return (s->cfg_ptr->ext_zvknha =3D=3D true && s->sew =3D=3D MO_32) || + (s->cfg_ptr->ext_zvknhb =3D=3D true && + (s->sew =3D=3D MO_32 || s->sew =3D=3D MO_64)); +} + +static bool vsha_check(DisasContext *s, arg_rmrr *a) +{ + int egw_bytes =3D ZVKNH_EGS << s->sew; + int mult =3D 1 << MAX(s->lmul, 0); + return opivv_check(s, a) && + vsha_check_sew(s) && + MAXSZ(s) >=3D egw_bytes && + !is_overlapped(a->rd, mult, a->rs1, mult) && + !is_overlapped(a->rd, mult, a->rs2, mult) && + s->lmul >=3D 0; +} + +GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check, ZVKNH_EGS) + +static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a) +{ + if (vsha_check(s, a)) { + uint32_t data =3D 0; + TCGLabel *over =3D gen_new_label(); + TCGv_i32 egs; + + if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { + /* save opcode for unwinding in case we throw an exception */ + decode_save_opc(s); + egs =3D tcg_constant_i32(ZVKNH_EGS); + gen_helper_egs_check(egs, cpu_env); + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); + } + + data =3D FIELD_DP32(data, VDATA, VM, a->vm); + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); + + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), + vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, + s->sew =3D=3D MO_32 ? + gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv); + + mark_vs_dirty(s); + gen_set_label(over); + return true; + } + return false; +} + +static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a) +{ + if (vsha_check(s, a)) { + uint32_t data =3D 0; + TCGLabel *over =3D gen_new_label(); + TCGv_i32 egs; + + if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { + /* save opcode for unwinding in case we throw an exception */ + decode_save_opc(s); + egs =3D tcg_constant_i32(ZVKNH_EGS); + gen_helper_egs_check(egs, cpu_env); + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); + } + + data =3D FIELD_DP32(data, VDATA, VM, a->vm); + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); + + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), + vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8, + s->cfg_ptr->vlen / 8, data, + s->sew =3D=3D MO_32 ? + gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv); + + mark_vs_dirty(s); + gen_set_label(over); + return true; + } + return false; +} diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 73cd1f91d9..50f7e9e166 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -397,3 +397,241 @@ void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr= , uint32_t uimm, /* set tail elements to 1s */ vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); } + +static inline uint32_t sig0_sha256(uint32_t x) +{ + return ror32(x, 7) ^ ror32(x, 18) ^ (x >> 3); +} + +static inline uint32_t sig1_sha256(uint32_t x) +{ + return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10); +} + +static inline uint64_t sig0_sha512(uint64_t x) +{ + return ror64(x, 1) ^ ror64(x, 8) ^ (x >> 7); +} + +static inline uint64_t sig1_sha512(uint64_t x) +{ + return ror64(x, 19) ^ ror64(x, 61) ^ (x >> 6); +} + +static inline void vsha2ms_e32(uint32_t *vd, uint32_t *vs1, uint32_t *vs2) +{ + uint32_t res[4]; + res[0] =3D sig1_sha256(vs1[H4(2)]) + vs2[H4(1)] + sig0_sha256(vd[H4(1)= ]) + + vd[H4(0)]; + res[1] =3D sig1_sha256(vs1[H4(3)]) + vs2[H4(2)] + sig0_sha256(vd[H4(2)= ]) + + vd[H4(1)]; + res[2] =3D + sig1_sha256(res[0]) + vs2[H4(3)] + sig0_sha256(vd[H4(3)]) + vd[H4(= 2)]; + res[3] =3D + sig1_sha256(res[1]) + vs1[H4(0)] + sig0_sha256(vs2[H4(0)]) + vd[H4= (3)]; + vd[H4(3)] =3D res[3]; + vd[H4(2)] =3D res[2]; + vd[H4(1)] =3D res[1]; + vd[H4(0)] =3D res[0]; +} + +static inline void vsha2ms_e64(uint64_t *vd, uint64_t *vs1, uint64_t *vs2) +{ + uint64_t res[4]; + res[0] =3D sig1_sha512(vs1[2]) + vs2[1] + sig0_sha512(vd[1]) + vd[0]; + res[1] =3D sig1_sha512(vs1[3]) + vs2[2] + sig0_sha512(vd[2]) + vd[1]; + res[2] =3D sig1_sha512(res[0]) + vs2[3] + sig0_sha512(vd[3]) + vd[2]; + res[3] =3D sig1_sha512(res[1]) + vs1[0] + sig0_sha512(vs2[0]) + vd[3]; + vd[3] =3D res[3]; + vd[2] =3D res[2]; + vd[1] =3D res[1]; + vd[0] =3D res[0]; +} + +void HELPER(vsha2ms_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, + uint32_t desc) +{ + uint32_t sew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t esz =3D sew =3D=3D MO_32 ? 4 : 8; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + if (sew =3D=3D MO_32) { + vsha2ms_e32(((uint32_t *)vd) + i * 4, ((uint32_t *)vs1) + i * = 4, + ((uint32_t *)vs2) + i * 4); + } else { + /* If not 32 then SEW should be 64 */ + vsha2ms_e64(((uint64_t *)vd) + i * 4, ((uint64_t *)vs1) + i * = 4, + ((uint64_t *)vs2) + i * 4); + } + } + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} + +static inline uint64_t sum0_64(uint64_t x) +{ + return ror64(x, 28) ^ ror64(x, 34) ^ ror64(x, 39); +} + +static inline uint32_t sum0_32(uint32_t x) +{ + return ror32(x, 2) ^ ror32(x, 13) ^ ror32(x, 22); +} + +static inline uint64_t sum1_64(uint64_t x) +{ + return ror64(x, 14) ^ ror64(x, 18) ^ ror64(x, 41); +} + +static inline uint32_t sum1_32(uint32_t x) +{ + return ror32(x, 6) ^ ror32(x, 11) ^ ror32(x, 25); +} + +#define ch(x, y, z) ((x & y) ^ ((~x) & z)) + +#define maj(x, y, z) ((x & y) ^ (x & z) ^ (y & z)) + +static void vsha2c_64(uint64_t *vs2, uint64_t *vd, uint64_t *vs1) +{ + uint64_t a =3D vs2[3], b =3D vs2[2], e =3D vs2[1], f =3D vs2[0]; + uint64_t c =3D vd[3], d =3D vd[2], g =3D vd[1], h =3D vd[0]; + uint64_t W0 =3D vs1[0], W1 =3D vs1[1]; + uint64_t T1 =3D h + sum1_64(e) + ch(e, f, g) + W0; + uint64_t T2 =3D sum0_64(a) + maj(a, b, c); + + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + T1 =3D h + sum1_64(e) + ch(e, f, g) + W1; + T2 =3D sum0_64(a) + maj(a, b, c); + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + vd[0] =3D f; + vd[1] =3D e; + vd[2] =3D b; + vd[3] =3D a; +} + +static void vsha2c_32(uint32_t *vs2, uint32_t *vd, uint32_t *vs1) +{ + uint32_t a =3D vs2[H4(3)], b =3D vs2[H4(2)], e =3D vs2[H4(1)], f =3D v= s2[H4(0)]; + uint32_t c =3D vd[H4(3)], d =3D vd[H4(2)], g =3D vd[H4(1)], h =3D vd[H= 4(0)]; + uint32_t W0 =3D vs1[H4(0)], W1 =3D vs1[H4(1)]; + uint32_t T1 =3D h + sum1_32(e) + ch(e, f, g) + W0; + uint32_t T2 =3D sum0_32(a) + maj(a, b, c); + + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + T1 =3D h + sum1_32(e) + ch(e, f, g) + W1; + T2 =3D sum0_32(a) + maj(a, b, c); + h =3D g; + g =3D f; + f =3D e; + e =3D d + T1; + d =3D c; + c =3D b; + b =3D a; + a =3D T1 + T2; + + vd[H4(0)] =3D f; + vd[H4(1)] =3D e; + vd[H4(2)] =3D b; + vd[H4(3)] =3D a; +} + +void HELPER(vsha2ch32_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *e= nv, + uint32_t desc) +{ + const uint32_t esz =3D 4; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, + ((uint32_t *)vs1) + 4 * i + 2); + } + + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} + +void HELPER(vsha2ch64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *e= nv, + uint32_t desc) +{ + const uint32_t esz =3D 8; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, + ((uint64_t *)vs1) + 4 * i + 2); + } + + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} + +void HELPER(vsha2cl32_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *e= nv, + uint32_t desc) +{ + const uint32_t esz =3D 4; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, + (((uint32_t *)vs1) + 4 * i)); + } + + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} + +void HELPER(vsha2cl64_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *e= nv, + uint32_t desc) +{ + uint32_t esz =3D 8; + uint32_t total_elems; + uint32_t vta =3D vext_vta(desc); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, + (((uint64_t *)vs1) + 4 * i)); + } + + /* set tail elements to 1s */ + total_elems =3D vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} --=20 2.34.1 From nobody Sun May 19 01:15:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1688313346; 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Co-authored-by: Kiran Ostrolenk [max.chou@sifive.com: Replaced vstart checking by TCG op] Signed-off-by: Kiran Ostrolenk Signed-off-by: Lawrence Hunter Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza [max.chou@sifive.com: Exposed x-zvksh property] --- target/riscv/cpu.c | 6 +- target/riscv/cpu_cfg.h | 1 + target/riscv/helper.h | 3 + target/riscv/insn32.decode | 4 + target/riscv/insn_trans/trans_rvvk.c.inc | 31 ++++++ target/riscv/vcrypto_helper.c | 134 +++++++++++++++++++++++ 6 files changed, 177 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3ca5ac209a..08b8355f52 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -121,6 +121,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), + ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), @@ -1193,8 +1194,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) * In principle Zve*x would also suffice here, were they supported * in qemu */ - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha) = && - !cpu->cfg.ext_zve32f) { + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || + cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { error_setg(errp, "Vector crypto extensions require V or Zve* extensions"= ); return; @@ -1712,6 +1713,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false), DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false), + DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false), =20 DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 7144bfd228..27062b12a8 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -88,6 +88,7 @@ struct RISCVCPUConfig { bool ext_zvkned; bool ext_zvknha; bool ext_zvknhb; + bool ext_zvksh; bool ext_zmmul; bool ext_zvfh; bool ext_zvfhmin; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 66929b88cb..172c91c65c 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1241,3 +1241,6 @@ DEF_HELPER_5(vsha2ch32_vv, void, ptr, ptr, ptr, env, = i32) DEF_HELPER_5(vsha2ch64_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsha2cl32_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsha2cl64_vv, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index d2cfb2729c..5ca83e8462 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -953,3 +953,7 @@ vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_v= m_1 vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** Zvksh vector crypto extension *** +vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index a35be11b95..6469dd2f02 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -500,3 +500,34 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr= *a) } return false; } + +/* + * Zvksh + */ + +#define ZVKSH_EGS 8 + +static inline bool vsm3_check(DisasContext *s, arg_rmrr *a) +{ + int egw_bytes =3D ZVKSH_EGS << s->sew; + int mult =3D 1 << MAX(s->lmul, 0); + return s->cfg_ptr->ext_zvksh =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + !is_overlapped(a->rd, mult, a->rs2, mult) && + MAXSZ(s) >=3D egw_bytes && + s->sew =3D=3D MO_32; +} + +static inline bool vsm3me_check(DisasContext *s, arg_rmrr *a) +{ + return vsm3_check(s, a) && vext_check_sss(s, a->rd, a->rs1, a->rs2, a-= >vm); +} + +static inline bool vsm3c_check(DisasContext *s, arg_rmrr *a) +{ + return vsm3_check(s, a) && vext_check_ss(s, a->rd, a->rs2, a->vm); +} + +GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check, ZVKSH_EGS) +GEN_VI_UNMASKED_TRANS(vsm3c_vi, vsm3c_check, ZVKSH_EGS) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 50f7e9e166..ff7fb11928 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -635,3 +635,137 @@ void HELPER(vsha2cl64_vv)(void *vd, void *vs1, void *= vs2, CPURISCVState *env, vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); env->vstart =3D 0; } + +static inline uint32_t p1(uint32_t x) +{ + return x ^ rol32(x, 15) ^ rol32(x, 23); +} + +static inline uint32_t zvksh_w(uint32_t m16, uint32_t m9, uint32_t m3, + uint32_t m13, uint32_t m6) +{ + return p1(m16 ^ m9 ^ rol32(m3, 15)) ^ rol32(m13, 7) ^ m6; +} + +void HELPER(vsm3me_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr, + CPURISCVState *env, uint32_t desc) +{ + uint32_t esz =3D memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW)); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t *vd =3D vd_vptr; + uint32_t *vs1 =3D vs1_vptr; + uint32_t *vs2 =3D vs2_vptr; + + for (int i =3D env->vstart / 8; i < env->vl / 8; i++) { + uint32_t w[24]; + for (int j =3D 0; j < 8; j++) { + w[j] =3D bswap32(vs1[H4((i * 8) + j)]); + w[j + 8] =3D bswap32(vs2[H4((i * 8) + j)]); + } + for (int j =3D 0; j < 8; j++) { + w[j + 16] =3D + zvksh_w(w[j], w[j + 7], w[j + 13], w[j + 3], w[j + 10]); + } + for (int j =3D 0; j < 8; j++) { + vd[(i * 8) + j] =3D bswap32(w[H4(j + 16)]); + } + } + vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} + +static inline uint32_t ff1(uint32_t x, uint32_t y, uint32_t z) +{ + return x ^ y ^ z; +} + +static inline uint32_t ff2(uint32_t x, uint32_t y, uint32_t z) +{ + return (x & y) | (x & z) | (y & z); +} + +static inline uint32_t ff_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j) +{ + return (j <=3D 15) ? ff1(x, y, z) : ff2(x, y, z); +} + +static inline uint32_t gg1(uint32_t x, uint32_t y, uint32_t z) +{ + return x ^ y ^ z; +} + +static inline uint32_t gg2(uint32_t x, uint32_t y, uint32_t z) +{ + return (x & y) | (~x & z); +} + +static inline uint32_t gg_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j) +{ + return (j <=3D 15) ? gg1(x, y, z) : gg2(x, y, z); +} + +static inline uint32_t t_j(uint32_t j) +{ + return (j <=3D 15) ? 0x79cc4519 : 0x7a879d8a; +} + +static inline uint32_t p_0(uint32_t x) +{ + return x ^ rol32(x, 9) ^ rol32(x, 17); +} + +static void sm3c(uint32_t *vd, uint32_t *vs1, uint32_t *vs2, uint32_t uimm) +{ + uint32_t x0, x1; + uint32_t j; + uint32_t ss1, ss2, tt1, tt2; + x0 =3D vs2[0] ^ vs2[4]; + x1 =3D vs2[1] ^ vs2[5]; + j =3D 2 * uimm; + ss1 =3D rol32(rol32(vs1[0], 12) + vs1[4] + rol32(t_j(j), j % 32), 7); + ss2 =3D ss1 ^ rol32(vs1[0], 12); + tt1 =3D ff_j(vs1[0], vs1[1], vs1[2], j) + vs1[3] + ss2 + x0; + tt2 =3D gg_j(vs1[4], vs1[5], vs1[6], j) + vs1[7] + ss1 + vs2[0]; + vs1[3] =3D vs1[2]; + vd[3] =3D rol32(vs1[1], 9); + vs1[1] =3D vs1[0]; + vd[1] =3D tt1; + vs1[7] =3D vs1[6]; + vd[7] =3D rol32(vs1[5], 19); + vs1[5] =3D vs1[4]; + vd[5] =3D p_0(tt2); + j =3D 2 * uimm + 1; + ss1 =3D rol32(rol32(vd[1], 12) + vd[5] + rol32(t_j(j), j % 32), 7); + ss2 =3D ss1 ^ rol32(vd[1], 12); + tt1 =3D ff_j(vd[1], vs1[1], vd[3], j) + vs1[3] + ss2 + x1; + tt2 =3D gg_j(vd[5], vs1[5], vd[7], j) + vs1[7] + ss1 + vs2[1]; + vd[2] =3D rol32(vs1[1], 9); + vd[0] =3D tt1; + vd[6] =3D rol32(vs1[5], 19); + vd[4] =3D p_0(tt2); +} + +void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, + CPURISCVState *env, uint32_t desc) +{ + uint32_t esz =3D memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW)); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + uint32_t vta =3D vext_vta(desc); + uint32_t *vd =3D vd_vptr; + uint32_t *vs2 =3D vs2_vptr; + uint32_t v1[8], v2[8], v3[8]; + + for (int i =3D env->vstart / 8; i < env->vl / 8; i++) { + for (int k =3D 0; k < 8; k++) { + v2[k] =3D bswap32(vd[H4(i * 8 + k)]); + v3[k] =3D bswap32(vs2[H4(i * 8 + k)]); + } + sm3c(v1, v2, v3, uimm); + for (int k =3D 0; k < 8; k++) { + vd[i * 8 + k] =3D bswap32(v1[H4(k)]); + } + } + vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); + env->vstart =3D 0; +} --=20 2.34.1 From nobody Sun May 19 01:15:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1688313376; cv=none; d=zohomail.com; s=zohoarc; b=EtwbKHPwwIVpPImBso5xf55lElhirpIRIKrUofEYYba86PrgPUx0OsnnK5/SVUDr9Jyu+8qB/o82v/vkeFtdpGLdIqZUumknT5e5PKTO3eL0p2pNUbcAsHUdz7vI+G8i1/JFyudeg4CbnfR06O2DG/YOLYRVIT0dwbIna6MCJ9M= ARC-Message-Signature: i=1; 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[125.228.20.175]) by smtp.gmail.com with ESMTPSA id y19-20020aa78553000000b0066f37665a63sm8231969pfn.73.2023.07.02.08.55.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 08:55:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1688313324; x=1690905324; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V7s8FOaU/HDCwiQFY7lwWobbCWup7XZJdwKvN1YCrfs=; b=WZzYrrbNj5veoCTtgA8niE9wweSKRYRcMWNJTXbHdp3VwoHRYcTq3wd2u74Hkxx2A/ 1ZK1MIgaBeDVCGaVnniADCA2zkkoyAlyF4TvvEyCfgfF0KmsRm+dDnJ/7Yw8lua9AEw5 sMxcK1O++JAzdgqHPZ6qrD+iLRhGE/GdBR+uDKOijbsSyb6tUM9iyZk2GkNNNn4ORb8H 71mQoXvxPbc396DQ+eWR+wtsdNIBAVe05b7c3VUCiBS1u/JVWmFJcmxvEeqgi4dJ4Jur H7Hkb68rW0Xqtkmwjmj8wjzpm3wY3qs43Z5ZiTMneFpidxChZT5xgxrQhRucukdJNtbS 6KbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688313324; x=1690905324; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V7s8FOaU/HDCwiQFY7lwWobbCWup7XZJdwKvN1YCrfs=; b=OYOKO+J0fGlQ38MLmUQIUbyMSmpscFyeybp40vbcpokghd/hoDWZnbRf1anUefpmUz 6j2nI/Y/Mdluep6da2EF9TaLqsicJJ8AqB48uUEA6pUbPPapVyv5MuN4s2/PL+Sh39Pw U79SWbDpb2vLIfpJu0LXC300HrbEU4jDWHlcA1eD4GCHxjSP9PXXa2Oyx4mDJBR65jzw AKa8QLicCq+N0JYjjte6AKKGMwjeWGGmYL8fwMP+WntVyRdxUDyqZijIco/MPdjKsHuD 8tAijvVgxxSr41eXglJR2QEACjcdkWHbTVlwsxpn+rbOVQAyjQJjP2AdX1JH+hL+BAlZ ipUw== X-Gm-Message-State: AC+VfDw2vtT6xJQguyvcq33eEGsjDbQDhjyqP6OgfcAq7ul9Yt9C4d35 B3Bq9RAXYxAi2fmGBjCGeaJimvPp0uS/qEE3L0czLexBoEhlzrL8qNXQCzzs5HWB2k3dXCCbIsk zBBxmDshbkFLGxfbVXPJSUfolBDAxtQZX35vRACuwWjFVDG3l3v+No2R0iT4eQ24oqMC0PtZvEf IpfsI= X-Google-Smtp-Source: ACHHUZ4PuS/ygYoBgTisytwB+FlJA92FAe6yI05OUiGvkQVSgbDjOFf0pwB8kdb14OilHBf4Z6rtzA== X-Received: by 2002:a05:6a20:9184:b0:12c:f685:87e3 with SMTP id v4-20020a056a20918400b0012cf68587e3mr8209790pzd.21.1688313323824; Sun, 02 Jul 2023 08:55:23 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: dbarboza@ventanamicro.com, Nazar Kazakov , Lawrence Hunter , Max Chou , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Kiran Ostrolenk Subject: [PATCH v7 12/15] target/riscv: Add Zvkg ISA extension support Date: Sun, 2 Jul 2023 23:53:46 +0800 Message-Id: <20230702155354.2478495-13-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230702155354.2478495-1-max.chou@sifive.com> References: <20230702155354.2478495-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=max.chou@sifive.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1688313378497100003 Content-Type: text/plain; charset="utf-8" From: Nazar Kazakov This commit adds support for the Zvkg vector-crypto extension, which consists of the following instructions: * vgmul.vv * vghsh.vv Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Co-authored-by: Lawrence Hunter [max.chou@sifive.com: Replaced vstart checking by TCG op] Signed-off-by: Lawrence Hunter Signed-off-by: Nazar Kazakov Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza [max.chou@sifive.com: Exposed x-zvkg property] --- target/riscv/cpu.c | 6 +- target/riscv/cpu_cfg.h | 1 + target/riscv/helper.h | 3 + target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvvk.c.inc | 30 ++++++++++ target/riscv/vcrypto_helper.c | 72 ++++++++++++++++++++++++ 6 files changed, 114 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 08b8355f52..699ab5e9fa 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -118,6 +118,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), + ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), @@ -1194,8 +1195,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) * In principle Zve*x would also suffice here, were they supported * in qemu */ - if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || - cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32f) { + if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || + cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32= f) { error_setg(errp, "Vector crypto extensions require V or Zve* extensions"= ); return; @@ -1710,6 +1711,7 @@ static Property riscv_cpu_extensions[] =3D { /* Vector cryptography extensions */ DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false), DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), + DEFINE_PROP_BOOL("x-zvkg", RISCVCPU, cfg.ext_zvkg, false), DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false), DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 27062b12a8..960761c479 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -85,6 +85,7 @@ struct RISCVCPUConfig { bool ext_zve64d; bool ext_zvbb; bool ext_zvbc; + bool ext_zvkg; bool ext_zvkned; bool ext_zvknha; bool ext_zvknhb; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 172c91c65c..238343cb42 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1244,3 +1244,6 @@ DEF_HELPER_5(vsha2cl64_vv, void, ptr, ptr, ptr, env, = i32) =20 DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) + +DEF_HELPER_5(vghsh_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_4(vgmul_vv, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 5ca83e8462..b10497afd3 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -957,3 +957,7 @@ vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_v= m_1 # *** Zvksh vector crypto extension *** vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** Zvkg vector crypto extension *** +vghsh_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index 6469dd2f02..af7cd62e7d 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -531,3 +531,33 @@ static inline bool vsm3c_check(DisasContext *s, arg_rm= rr *a) =20 GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check, ZVKSH_EGS) GEN_VI_UNMASKED_TRANS(vsm3c_vi, vsm3c_check, ZVKSH_EGS) + +/* + * Zvkg + */ + +#define ZVKG_EGS 4 + +static bool vgmul_check(DisasContext *s, arg_rmr *a) +{ + int egw_bytes =3D ZVKG_EGS << s->sew; + return s->cfg_ptr->ext_zvkg =3D=3D true && + vext_check_isa_ill(s) && + require_rvv(s) && + MAXSZ(s) >=3D egw_bytes && + vext_check_ss(s, a->rd, a->rs2, a->vm) && + s->sew =3D=3D MO_32; +} + +GEN_V_UNMASKED_TRANS(vgmul_vv, vgmul_check, ZVKG_EGS) + +static bool vghsh_check(DisasContext *s, arg_rmrr *a) +{ + int egw_bytes =3D ZVKG_EGS << s->sew; + return s->cfg_ptr->ext_zvkg =3D=3D true && + opivv_check(s, a) && + MAXSZ(s) >=3D egw_bytes && + s->sew =3D=3D MO_32; +} + +GEN_VV_UNMASKED_TRANS(vghsh_vv, vghsh_check, ZVKG_EGS) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index ff7fb11928..f127fc0d3a 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -769,3 +769,75 @@ void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, u= int32_t uimm, vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); env->vstart =3D 0; } + +void HELPER(vghsh_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr, + CPURISCVState *env, uint32_t desc) +{ + uint64_t *vd =3D vd_vptr; + uint64_t *vs1 =3D vs1_vptr; + uint64_t *vs2 =3D vs2_vptr; + uint32_t vta =3D vext_vta(desc); + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + uint64_t Y[2] =3D {vd[i * 2 + 0], vd[i * 2 + 1]}; + uint64_t H[2] =3D {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])}; + uint64_t X[2] =3D {vs1[i * 2 + 0], vs1[i * 2 + 1]}; + uint64_t Z[2] =3D {0, 0}; + + uint64_t S[2] =3D {brev8(Y[0] ^ X[0]), brev8(Y[1] ^ X[1])}; + + for (uint j =3D 0; j < 128; j++) { + if ((S[j / 64] >> (j % 64)) & 1) { + Z[0] ^=3D H[0]; + Z[1] ^=3D H[1]; + } + bool reduce =3D ((H[1] >> 63) & 1); + H[1] =3D H[1] << 1 | H[0] >> 63; + H[0] =3D H[0] << 1; + if (reduce) { + H[0] ^=3D 0x87; + } + } + + vd[i * 2 + 0] =3D brev8(Z[0]); + vd[i * 2 + 1] =3D brev8(Z[1]); + } + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); + env->vstart =3D 0; +} + +void HELPER(vgmul_vv)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, + uint32_t desc) +{ + uint64_t *vd =3D vd_vptr; + uint64_t *vs2 =3D vs2_vptr; + uint32_t vta =3D vext_vta(desc); + uint32_t total_elems =3D vext_get_total_elems(env, desc, 4); + + for (uint32_t i =3D env->vstart / 4; i < env->vl / 4; i++) { + uint64_t Y[2] =3D {brev8(vd[i * 2 + 0]), brev8(vd[i * 2 + 1])}; + uint64_t H[2] =3D {brev8(vs2[i * 2 + 0]), brev8(vs2[i * 2 + 1])}; + uint64_t Z[2] =3D {0, 0}; + + for (uint j =3D 0; j < 128; j++) { + if ((Y[j / 64] >> (j % 64)) & 1) { + Z[0] ^=3D H[0]; + Z[1] ^=3D H[1]; + } + bool reduce =3D ((H[1] >> 63) & 1); + H[1] =3D H[1] << 1 | H[0] >> 63; + H[0] =3D H[0] << 1; + if (reduce) { + H[0] ^=3D 0x87; + } + } + + vd[i * 2 + 0] =3D brev8(Z[0]); + vd[i * 2 + 1] =3D brev8(Z[1]); + } + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); + env->vstart =3D 0; +} --=20 2.34.1 From nobody Sun May 19 01:15:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[125.228.20.175]) by smtp.gmail.com with ESMTPSA id y19-20020aa78553000000b0066f37665a63sm8231969pfn.73.2023.07.02.08.55.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 08:55:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1688313328; x=1690905328; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DEIqVctPEZTYbzcDe0Hbcq05xA1rg82RA8xn7gYRFBw=; b=QTxmpJw9M5cu3YaNlWJZaqkAzB8f1Oejcl1mWtsEMyniZr9egiGF5rgKaZMa0YNVEU Qx9I9HnwJo8s4oWo+PCFsPa05GRrrDZQmuH2BAf9nnR8mxf2zg0XDpH0xhWI+pabfKvS 76lYDHzFw4z1Oo4UMLRsp0X+ynzEShVn5M9sMHqlgaQB7sY+hIacSwhf03NbxD//OI8J JDjQH1x3Rn1FDEqt5mYFoIVai/1JbtENMDFzy/TYGuAnjsSknKqTeZHpMVPdN4IzR3qY n2BvgiFKOY3gsoyg5DTI++CgIk3xBYooL+bHs/Q+JOKN7XLU8GczIoxy2nS5fv34zsuS XIew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688313328; x=1690905328; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DEIqVctPEZTYbzcDe0Hbcq05xA1rg82RA8xn7gYRFBw=; b=FsrmpUfKc3iT/Axc8AWb7oKKOcxF+W0Ghvdng5+amPZ/YuW13aUeDWsu8fGg3JsgUu pVSs4jatilKRDt8nOJ16/dqcQuZe9rO3vImLrtkfsHkrPyc7UM83+/e57xK4FAp3sA9p Wue1tm0LxcrUA8rcdFmual1AYTPHuz5jEajh2Nvq9Rfl2yiEx9MVIyjpo04J1SnJ5pZK MjG7QdmccwknRASDbPhl5pxjuhYaAOYAVQ06ttNXXos7ea52vKvItJEfMMOym22A2UJC o/A85haYk1F8xGIfJX8JxHCPl2yr3CH2N4trsHEPcFnKJ437QIYDw4mmQ089kkUSU6Ao zuGg== X-Gm-Message-State: ABy/qLbK+bkRoFk3bev5AeyeOvy/pyLlrUYwrbpfazucEaQcdJq9Coqs Raa7vAg7di4BPBljCA3EDlQs0fHvxJbzYTAkkJBdWNgsP60F25VYed7QUXh7XIpj3bcTAQHBvzE 0GHk0I0s/IlPbK+PwzN18KbcQOIjA3z3BB9R0HKZj98YpHqDLSv2r6DkuopkIb1dzJb+e+JB2vl HSGEI= X-Google-Smtp-Source: APBJJlEzmw9aR7JGkhGtbn9ZCtEW7/DTDyKAh5CL8Fl0Tb/hnLteOPDxP8EDnuFPppD8mVJTNCFpcA== X-Received: by 2002:a05:6a00:2d0f:b0:682:93ce:4825 with SMTP id fa15-20020a056a002d0f00b0068293ce4825mr460345pfb.3.1688313327834; Sun, 02 Jul 2023 08:55:27 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: dbarboza@ventanamicro.com, Max Chou , Frank Chang , Richard Henderson , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Peter Maydell , qemu-arm@nongnu.org Subject: [PATCH v7 13/15] crypto: Create sm4_subword Date: Sun, 2 Jul 2023 23:53:47 +0800 Message-Id: <20230702155354.2478495-14-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230702155354.2478495-1-max.chou@sifive.com> References: <20230702155354.2478495-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=max.chou@sifive.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1688313475573100003 Content-Type: text/plain; charset="utf-8" Allows sharing of sm4_subword between different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang Reviewed-by: Richard Henderson Signed-off-by: Max Chou --- include/crypto/sm4.h | 8 ++++++++ target/arm/tcg/crypto_helper.c | 10 ++-------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h index 9bd3ebc62e..de8245d8a7 100644 --- a/include/crypto/sm4.h +++ b/include/crypto/sm4.h @@ -3,4 +3,12 @@ =20 extern const uint8_t sm4_sbox[256]; =20 +static inline uint32_t sm4_subword(uint32_t word) +{ + return sm4_sbox[word & 0xff] | + sm4_sbox[(word >> 8) & 0xff] << 8 | + sm4_sbox[(word >> 16) & 0xff] << 16 | + sm4_sbox[(word >> 24) & 0xff] << 24; +} + #endif diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index fdd70abbfd..7cadd61e12 100644 --- a/target/arm/tcg/crypto_helper.c +++ b/target/arm/tcg/crypto_helper.c @@ -614,10 +614,7 @@ static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn,= uint64_t *rm) CR_ST_WORD(d, (i + 3) % 4) ^ CR_ST_WORD(n, i); =20 - t =3D sm4_sbox[t & 0xff] | - sm4_sbox[(t >> 8) & 0xff] << 8 | - sm4_sbox[(t >> 16) & 0xff] << 16 | - sm4_sbox[(t >> 24) & 0xff] << 24; + t =3D sm4_subword(t); =20 CR_ST_WORD(d, i) ^=3D t ^ rol32(t, 2) ^ rol32(t, 10) ^ rol32(t, 18= ) ^ rol32(t, 24); @@ -651,10 +648,7 @@ static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *= rn, uint64_t *rm) CR_ST_WORD(d, (i + 3) % 4) ^ CR_ST_WORD(m, i); =20 - t =3D sm4_sbox[t & 0xff] | - sm4_sbox[(t >> 8) & 0xff] << 8 | - sm4_sbox[(t >> 16) & 0xff] << 16 | - sm4_sbox[(t >> 24) & 0xff] << 24; + t =3D sm4_subword(t); =20 CR_ST_WORD(d, i) ^=3D t ^ rol32(t, 13) ^ rol32(t, 23); } --=20 2.34.1 From nobody Sun May 19 01:15:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1688313385; cv=none; d=zohomail.com; s=zohoarc; b=ngQ8HXVt3jWYgHC/k4hjwHVBCx93rdlGgS/rGxabxxf1nsLPxFiQzEgYv5WuG8EyB1Gwiy8gY/YZu05nP8ehCssuJ09hW1sh3PvTT2OWCqkvlSmNTDFOuvYSSDTHR/XJlngNXkkjvy0cOKyk1ph9zRO4a5vhrgQUj7aoT57b5Pw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1688313385; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ue2dx04GA0MMTMF2nL8iZsmgnBaXiJ8OB2kvZbsFtIY=; b=GUl9fUFp0/oMumubYNoxNBq9kA31STvV10mryPE7DVAtpGG0aTJvBd2u+m+22g0vxSqzqR/NpfWPbvmvmj1ZVXV+c3ScWKQ0QolydQCJyMHZ9t5T87q+NavQHe7eim2hW8etfC6YJ68w84xPyEtEbALkqYximqYyuT2dzkx1t+Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1688313385914681.0760895425703; Sun, 2 Jul 2023 08:56:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qFzQe-0004sJ-53; Sun, 02 Jul 2023 11:56:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFzQF-000431-96 for qemu-devel@nongnu.org; Sun, 02 Jul 2023 11:55:35 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qFzQD-0000Id-IF for qemu-devel@nongnu.org; Sun, 02 Jul 2023 11:55:34 -0400 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-53fbf2c42bfso2671497a12.3 for ; Sun, 02 Jul 2023 08:55:32 -0700 (PDT) Received: from duncan.localdomain (125-228-20-175.hinet-ip.hinet.net. [125.228.20.175]) by smtp.gmail.com with ESMTPSA id y19-20020aa78553000000b0066f37665a63sm8231969pfn.73.2023.07.02.08.55.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 08:55:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1688313332; x=1690905332; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ue2dx04GA0MMTMF2nL8iZsmgnBaXiJ8OB2kvZbsFtIY=; b=KN3xH9UZQsBWqB4gAlh/vijbgpiZIO1tPy/i5BLomaA+jZT8pN8d7ownBz+95nU9Li V7QdsCP7jwKkytPvMIAZvCNf2ZqmbYPa0MsCTuYlccmTtdf5sXaaS5DvoiNkSbK1Zd90 gLX0Lt78x8BCW47KXD7qTKc+21483ed2cuCaDbNDp1vU5egN7MnQnZNcn//JsNVo6YI5 cf8KIKWSwGA0vRZidKlypSLAc2HaDoJKKq587hY4CB+5biWTCyFZEXlAWLPa1A6BjFx3 vu4/YpzEYXy2pj2a+MeY2r3Zqti8f7xEU2/8U5YYhKxDMZeaKZBaWXXu2rlvumDksz69 pzyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688313332; x=1690905332; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ue2dx04GA0MMTMF2nL8iZsmgnBaXiJ8OB2kvZbsFtIY=; b=CNARWE73lsL8UcVDqI74TSv3jPZo24ryRhdpWF+2mVIZIWPiFX8PUyQU4H6t0AhoFW 8M/JjKtypWTpUm6Ua3oue1DXWCDPSbeatTvmhgZ4r6xZmJEVLuDFXwSOswfPmaihoIGH hkyqTePlziUVcqcB4ircgV/xPDUSSBQ4L3w9FiYSZjPkZlzyLQPcDQ12DaF5M/E6L0SX Nb5KoO3ED5m1fBOl+j7fQjmP4DuOg/qBC7P4HTyLfTGlIIC2zUihpAaPIrWsncAEvgTt KCnR3fjnAhPM1GPdBsQpaaLRgQF5idfyDI9C16X4rxnsYWarW6q0kbZhG1poSAFoQwa1 HsOw== X-Gm-Message-State: AC+VfDycJ5tWAZBCXwvF+Ud4B224GzJDxjtEFz5quf1pG266mUL5Wk0T 2zXerA5BFu7ty6sm4nOw8OYf7xmVowps3YtQuDdCql0/RQS4RjlN3TX0ZSF03wcQfZIW3W6SJmC 7N/HUXvBGk7Fj4bJGTX3CcS+AImgegFHWi1Lf+/Fm7N4Di/PxRnVyki9declLmcMzMrxUexrSJ1 raVLc= X-Google-Smtp-Source: ACHHUZ4JSt57NbLfXAI7CVUzf3qa4Hh5I8M3PBsPsTjma3iFKO3BYQexLJHWDsXiqi0yu/6wykZEFA== X-Received: by 2002:a05:6a20:511:b0:12c:8871:26dd with SMTP id 17-20020a056a20051100b0012c887126ddmr8900488pzp.25.1688313331659; Sun, 02 Jul 2023 08:55:31 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: dbarboza@ventanamicro.com, Max Chou , Frank Chang , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Subject: [PATCH v7 14/15] crypto: Add SM4 constant parameter CK Date: Sun, 2 Jul 2023 23:53:48 +0800 Message-Id: <20230702155354.2478495-15-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230702155354.2478495-1-max.chou@sifive.com> References: <20230702155354.2478495-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=max.chou@sifive.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1688313386538100001 Content-Type: text/plain; charset="utf-8" Adds sm4_ck constant for use in sm4 cryptography across different targets. Signed-off-by: Max Chou Reviewed-by: Frank Chang Signed-off-by: Max Chou --- crypto/sm4.c | 10 ++++++++++ include/crypto/sm4.h | 1 + 2 files changed, 11 insertions(+) diff --git a/crypto/sm4.c b/crypto/sm4.c index 9f0cd452c7..2987306cf7 100644 --- a/crypto/sm4.c +++ b/crypto/sm4.c @@ -47,3 +47,13 @@ uint8_t const sm4_sbox[] =3D { 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48, }; =20 +uint32_t const sm4_ck[] =3D { + 0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269, + 0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9, + 0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249, + 0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9, + 0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229, + 0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299, + 0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209, + 0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279 +}; diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h index de8245d8a7..382b26d922 100644 --- a/include/crypto/sm4.h +++ b/include/crypto/sm4.h @@ -2,6 +2,7 @@ #define QEMU_SM4_H =20 extern const uint8_t sm4_sbox[256]; +extern const uint32_t sm4_ck[32]; =20 static inline uint32_t sm4_subword(uint32_t word) { --=20 2.34.1 From nobody Sun May 19 01:15:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1688313366; cv=none; d=zohomail.com; s=zohoarc; b=ijP+iCQWwieO4jFnVlTXtilNMowYx+gvTdjn3Nb2GKDf7JFpwzaH4AvCAl7cPJd0ghsIhtTx6qLMXCNwl2iX2oGWMPCbEk4F/GZBD/8ipQFnU5Sp6gwDf/Cu+bZEkWvjkjmFjLd1MHku4o++/RWiwMGR34j8E3MccnePd5AdeFA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1688313366; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aS0dXTLkW+u7nmcwpFCMg/zLai0IpZoABvi8bFk3m00=; b=P8MXeAyahx7GcVvvezdyzCGnIQTOyfDAuYk25WCZyysvRmBhhm8YK53HcLnEoOjNCZ6CRIC1BS/Nys1n6aTUyvmrpgvPrYzGzK/PbIxcQOaqJ9+XEUCvGJ03Wq+0Gn1OFWW3ygJx5VNr4cCWuhf/DKKnbKOJjfdQSqDU7GE4mog= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1688313366242947.9061312163736; Sun, 2 Jul 2023 08:56:06 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qFzQe-0004sk-4X; Sun, 02 Jul 2023 11:56:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qFzQM-0004hF-5T for qemu-devel@nongnu.org; Sun, 02 Jul 2023 11:55:47 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qFzQI-0000Jl-DI for qemu-devel@nongnu.org; Sun, 02 Jul 2023 11:55:40 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-666e6ecb52dso1847516b3a.2 for ; Sun, 02 Jul 2023 08:55:38 -0700 (PDT) Received: from duncan.localdomain (125-228-20-175.hinet-ip.hinet.net. [125.228.20.175]) by smtp.gmail.com with ESMTPSA id y19-20020aa78553000000b0066f37665a63sm8231969pfn.73.2023.07.02.08.55.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Jul 2023 08:55:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1688313337; x=1690905337; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aS0dXTLkW+u7nmcwpFCMg/zLai0IpZoABvi8bFk3m00=; b=TbGXtNCeOQ7OkaOmiPjfuC3JLz9tAPWoaQxv5WYuXkaoSsyIJXfI0k6UtJz65wjhbu mDzIR6b5XEQN+h46DNoDXwLHPlNjgSbkucpdFZGKnCZ/WZ6FAgpdireBifk8CNscwkW/ yihfdUDKEKIVsIR33x/Jaavbfx+A5PXrJuZHgQX2dxYE6uWqRc/uDjPhiz9L015Mghzl mL5d160xuMkNgTCc09MLsYCZZ/mIcF8eVaeqqIFxd5y21AMZl0yeDWQ9hQKu2r65U6eO t7OPPUoAWbVTBGln9gRjb8cA5Wg0zvQzSenRUm3biwKRf9DSiAvEabDa4rTr2qoB1aA0 hX/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688313337; x=1690905337; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aS0dXTLkW+u7nmcwpFCMg/zLai0IpZoABvi8bFk3m00=; b=dMsM/WfBCPQfcJxZpibuavgC4lFP8kAmdSLObP//2gF67gng2Fs5F7uIz2XwFHoag5 BQDuuxwJfRc0T8E+KMi+TfQAeUQWCggSiZK/VwUoZxwl+xcJk+8VsNkLOymK5cK+t9K0 xN7BUMhHJMWCs7HQHfr2EBssp3lt8B0f0LBqqHV/6MulrsAzpUZQ3lhHLETqfxYpS2b/ eHkFYZpFQfj1dCTY1knnj+02CzmbgBIaXogdIFRqhwd4u4/mxX5bk5FRfRRaYdzzBpn6 RHXRQjfR/P3HosaLIzZHDsnWoZ7oCuuOSMPiqABad0c/uRRdiWYqCT+oU6MBMkgF6NUY 7WYA== X-Gm-Message-State: ABy/qLZzqamCKuPTZ74IM/QW8EG8Wv5CZeTfyiVGYuiV0Snky0S2CZnH GCV7jjVpwJo5BsSKWulcqHdC0iCJX491rMhSgruXjDf26/htGvXJ+2E+HO5IRpumD2kzrbnDncg 9waSyGnDRhrcUn+sWgGYDWSE8buHY4QkNW+EPITKhmoJaRxpHbHkiVTSdkRgaSOVZGKq58XL++/ YUoOw= X-Google-Smtp-Source: APBJJlFhgH5kwKMjoKH2LQNOS8YVNkZTuoBqGZatSovQ7W3x6Dg2J/eTZ2w/pebuuXD9rPqdMN8Smw== X-Received: by 2002:a05:6a00:21d1:b0:647:4dee:62b7 with SMTP id t17-20020a056a0021d100b006474dee62b7mr8488769pfj.29.1688313336697; Sun, 02 Jul 2023 08:55:36 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: dbarboza@ventanamicro.com, Max Chou , Frank Chang , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Nazar Kazakov , Lawrence Hunter , Kiran Ostrolenk Subject: [PATCH v7 15/15] target/riscv: Add Zvksed ISA extension support Date: Sun, 2 Jul 2023 23:53:49 +0800 Message-Id: <20230702155354.2478495-16-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230702155354.2478495-1-max.chou@sifive.com> References: <20230702155354.2478495-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=max.chou@sifive.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1688313368378100003 Content-Type: text/plain; charset="utf-8" This commit adds support for the Zvksed vector-crypto extension, which consists of the following instructions: * vsm4k.vi * vsm4r.[vv,vs] Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`. Signed-off-by: Max Chou Reviewed-by: Frank Chang [lawrence.hunter@codethink.co.uk: Moved SM4 functions from crypto_helper.c to vcrypto_helper.c] [nazar.kazakov@codethink.co.uk: Added alignment checks, refactored code to use macros, and minor style changes] Signed-off-by: Max Chou --- target/riscv/cpu.c | 5 +- target/riscv/cpu_cfg.h | 1 + target/riscv/helper.h | 4 + target/riscv/insn32.decode | 5 + target/riscv/insn_trans/trans_rvvk.c.inc | 43 ++++++++ target/riscv/vcrypto_helper.c | 127 +++++++++++++++++++++++ 6 files changed, 184 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 699ab5e9fa..d4c2f77d44 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -122,6 +122,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), + ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed), ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), @@ -1196,7 +1197,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,= Error **errp) * in qemu */ if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkg || cpu->cfg.ext_zvkned || - cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32= f) { + cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || cpu->cfg.ext_zvksh)= && + !cpu->cfg.ext_zve32f) { error_setg(errp, "Vector crypto extensions require V or Zve* extensions"= ); return; @@ -1715,6 +1717,7 @@ static Property riscv_cpu_extensions[] =3D { DEFINE_PROP_BOOL("x-zvkned", RISCVCPU, cfg.ext_zvkned, false), DEFINE_PROP_BOOL("x-zvknha", RISCVCPU, cfg.ext_zvknha, false), DEFINE_PROP_BOOL("x-zvknhb", RISCVCPU, cfg.ext_zvknhb, false), + DEFINE_PROP_BOOL("x-zvksed", RISCVCPU, cfg.ext_zvksed, false), DEFINE_PROP_BOOL("x-zvksh", RISCVCPU, cfg.ext_zvksh, false), =20 DEFINE_PROP_END_OF_LIST(), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 960761c479..a4b60f8a51 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -89,6 +89,7 @@ struct RISCVCPUConfig { bool ext_zvkned; bool ext_zvknha; bool ext_zvknhb; + bool ext_zvksed; bool ext_zvksh; bool ext_zmmul; bool ext_zvfh; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 238343cb42..5b9dbc61a0 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1247,3 +1247,7 @@ DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) =20 DEF_HELPER_5(vghsh_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_4(vgmul_vv, void, ptr, ptr, env, i32) + +DEF_HELPER_5(vsm4k_vi, void, ptr, ptr, i32, env, i32) +DEF_HELPER_4(vsm4r_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b10497afd3..dab38e23e3 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -961,3 +961,8 @@ vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_v= m_1 # *** Zvkg vector crypto extension *** vghsh_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1 vgmul_vv 101000 1 ..... 10001 010 ..... 1110111 @r2_vm_1 + +# *** Zvksed vector crypto extension *** +vsm4k_vi 100001 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsm4r_vv 101000 1 ..... 10000 010 ..... 1110111 @r2_vm_1 +vsm4r_vs 101001 1 ..... 10000 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_t= rans/trans_rvvk.c.inc index af7cd62e7d..c00c70dfc6 100644 --- a/target/riscv/insn_trans/trans_rvvk.c.inc +++ b/target/riscv/insn_trans/trans_rvvk.c.inc @@ -561,3 +561,46 @@ static bool vghsh_check(DisasContext *s, arg_rmrr *a) } =20 GEN_VV_UNMASKED_TRANS(vghsh_vv, vghsh_check, ZVKG_EGS) + +/* + * Zvksed + */ + +#define ZVKSED_EGS 4 + +static bool zvksed_check(DisasContext *s) +{ + int egw_bytes =3D ZVKSED_EGS << s->sew; + return s->cfg_ptr->ext_zvksed =3D=3D true && + require_rvv(s) && + vext_check_isa_ill(s) && + MAXSZ(s) >=3D egw_bytes && + s->sew =3D=3D MO_32; +} + +static bool vsm4k_vi_check(DisasContext *s, arg_rmrr *a) +{ + return zvksed_check(s) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul); +} + +GEN_VI_UNMASKED_TRANS(vsm4k_vi, vsm4k_vi_check, ZVKSED_EGS) + +static bool vsm4r_vv_check(DisasContext *s, arg_rmr *a) +{ + return zvksed_check(s) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul); +} + +GEN_V_UNMASKED_TRANS(vsm4r_vv, vsm4r_vv_check, ZVKSED_EGS) + +static bool vsm4r_vs_check(DisasContext *s, arg_rmr *a) +{ + return zvksed_check(s) && + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) && + require_align(a->rd, s->lmul); +} + +GEN_V_UNMASKED_TRANS(vsm4r_vs, vsm4r_vs_check, ZVKSED_EGS) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index f127fc0d3a..5ce77e3934 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -24,6 +24,7 @@ #include "cpu.h" #include "crypto/aes.h" #include "crypto/aes-round.h" +#include "crypto/sm4.h" #include "exec/memop.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -841,3 +842,129 @@ void HELPER(vgmul_vv)(void *vd_vptr, void *vs2_vptr, = CPURISCVState *env, vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); env->vstart =3D 0; } + +void HELPER(vsm4k_vi)(void *vd, void *vs2, uint32_t uimm5, CPURISCVState *= env, + uint32_t desc) +{ + const uint32_t egs =3D 4; + uint32_t rnd =3D uimm5 & 0x7; + uint32_t group_start =3D env->vstart / egs; + uint32_t group_end =3D env->vl / egs; + uint32_t esz =3D sizeof(uint32_t); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + + for (uint32_t i =3D group_start; i < group_end; ++i) { + uint32_t vstart =3D i * egs; + uint32_t vend =3D (i + 1) * egs; + uint32_t rk[4] =3D {0}; + uint32_t tmp[8] =3D {0}; + + for (uint32_t j =3D vstart; j < vend; ++j) { + rk[j - vstart] =3D *((uint32_t *)vs2 + H4(j)); + } + + for (uint32_t j =3D 0; j < egs; ++j) { + tmp[j] =3D rk[j]; + } + + for (uint32_t j =3D 0; j < egs; ++j) { + uint32_t b, s; + b =3D tmp[j + 1] ^ tmp[j + 2] ^ tmp[j + 3] ^ sm4_ck[rnd * 4 + = j]; + + s =3D sm4_subword(b); + + tmp[j + 4] =3D tmp[j] ^ (s ^ rol32(s, 13) ^ rol32(s, 23)); + } + + for (uint32_t j =3D vstart; j < vend; ++j) { + *((uint32_t *)vd + H4(j)) =3D tmp[egs + (j - vstart)]; + } + } + + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz= ); +} + +static void do_sm4_round(uint32_t *rk, uint32_t *buf) +{ + const uint32_t egs =3D 4; + uint32_t s, b; + + for (uint32_t j =3D egs; j < egs * 2; ++j) { + b =3D buf[j - 3] ^ buf[j - 2] ^ buf[j - 1] ^ rk[j - 4]; + + s =3D sm4_subword(b); + + buf[j] =3D buf[j - 4] ^ (s ^ rol32(s, 2) ^ rol32(s, 10) ^ rol32(s,= 18) ^ + rol32(s, 24)); + } +} + +void HELPER(vsm4r_vv)(void *vd, void *vs2, CPURISCVState *env, uint32_t de= sc) +{ + const uint32_t egs =3D 4; + uint32_t group_start =3D env->vstart / egs; + uint32_t group_end =3D env->vl / egs; + uint32_t esz =3D sizeof(uint32_t); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + + for (uint32_t i =3D group_start; i < group_end; ++i) { + uint32_t vstart =3D i * egs; + uint32_t vend =3D (i + 1) * egs; + uint32_t rk[4] =3D {0}; + uint32_t tmp[8] =3D {0}; + + for (uint32_t j =3D vstart; j < vend; ++j) { + rk[j - vstart] =3D *((uint32_t *)vs2 + H4(j)); + } + + for (uint32_t j =3D vstart; j < vend; ++j) { + tmp[j - vstart] =3D *((uint32_t *)vd + H4(j)); + } + + do_sm4_round(rk, tmp); + + for (uint32_t j =3D vstart; j < vend; ++j) { + *((uint32_t *)vd + H4(j)) =3D tmp[egs + (j - vstart)]; + } + } + + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz= ); +} + +void HELPER(vsm4r_vs)(void *vd, void *vs2, CPURISCVState *env, uint32_t de= sc) +{ + const uint32_t egs =3D 4; + uint32_t group_start =3D env->vstart / egs; + uint32_t group_end =3D env->vl / egs; + uint32_t esz =3D sizeof(uint32_t); + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); + + for (uint32_t i =3D group_start; i < group_end; ++i) { + uint32_t vstart =3D i * egs; + uint32_t vend =3D (i + 1) * egs; + uint32_t rk[4] =3D {0}; + uint32_t tmp[8] =3D {0}; + + for (uint32_t j =3D 0; j < egs; ++j) { + rk[j] =3D *((uint32_t *)vs2 + H4(j)); + } + + for (uint32_t j =3D vstart; j < vend; ++j) { + tmp[j - vstart] =3D *((uint32_t *)vd + H4(j)); + } + + do_sm4_round(rk, tmp); + + for (uint32_t j =3D vstart; j < vend; ++j) { + *((uint32_t *)vd + H4(j)) =3D tmp[egs + (j - vstart)]; + } + } + + env->vstart =3D 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz= ); +} --=20 2.34.1