The ptw code is accessed by non-TCG code (specifically arm_pamax and
arm_cpu_get_phys_page_attrs_debug) but most of it is really only for
TCG emulation. Seeing as we already assert for a non TARGET_AARCH64
build lets extend the test rather than further messing with the ifdef
ladder.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

---
NB: I need this because I'm about to change the probe action is calls
and probes are very definitely TCG only operations through cputlb.c.
---
 target/arm/ptw.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 422bf7e3b1..8cac685aa6 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -628,7 +628,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
                              uint64_t new_val, S1Translate *ptw,
                              ARMMMUFaultInfo *fi)
 {
-#ifdef TARGET_AARCH64
+#if defined(TARGET_AARCH64) && defined(CONFIG_TCG)
     uint64_t cur_val;
     void *host = ptw->out_host;
 
@@ -708,7 +708,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
 
     return cur_val;
 #else
-    /* AArch32 does not have FEAT_HADFS. */
+    /* AArch32 and non TCG guests do not have FEAT_HADFS. */
     g_assert_not_reached();
 #endif
 }
-- 
2.39.2

On 6/30/23 13:07, Alex Bennée wrote:
> The ptw code is accessed by non-TCG code (specifically arm_pamax and
> arm_cpu_get_phys_page_attrs_debug) but most of it is really only for
> TCG emulation. Seeing as we already assert for a non TARGET_AARCH64
> build lets extend the test rather than further messing with the ifdef
> ladder.
> 
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> 
> ---
> NB: I need this because I'm about to change the probe action is calls
> and probes are very definitely TCG only operations through cputlb.c.
> ---
>   target/arm/ptw.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/arm/ptw.c b/target/arm/ptw.c
> index 422bf7e3b1..8cac685aa6 100644
> --- a/target/arm/ptw.c
> +++ b/target/arm/ptw.c
> @@ -628,7 +628,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
>                                uint64_t new_val, S1Translate *ptw,
>                                ARMMMUFaultInfo *fi)
>   {
> -#ifdef TARGET_AARCH64
> +#if defined(TARGET_AARCH64) && defined(CONFIG_TCG)
>       uint64_t cur_val;
>       void *host = ptw->out_host;
>   
> @@ -708,7 +708,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val,
>   
>       return cur_val;
>   #else
> -    /* AArch32 does not have FEAT_HADFS. */
> +    /* AArch32 and non TCG guests do not have FEAT_HADFS. */
Better as

   AArch32 does not have FEAT_HADFS; non-TCG guests only use debug-mode.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~