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Thu, 22 Jun 2023 16:25:30 +0000 Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay01.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 35MGPSlx000524 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 22 Jun 2023 16:25:28 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8B1742004D; Thu, 22 Jun 2023 16:25:28 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 373362004B; Thu, 22 Jun 2023 16:25:28 +0000 (GMT) Received: from borneo.ibmuc.com (unknown [9.171.58.93]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 22 Jun 2023 16:25:28 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=7jQ96OxTNuY3vC3vuXXoceXjQkQANMLmsBe6I/h4lMw=; b=Nl5f6DLVt89iu5g22Aw4Ch5/gnwsmF5Ao1BCqOCRwxPt1C+jlhubcs2RWmMEzl8CQLR+ n2cov+PaCZr1XceKQT/Gd8XTpr2gS1tZt6ktTA0c+TCB0ibDx7dGJNgyVqb0sQ/tSXTX BkeyvVPG1lORDn/4zsbbNEImvT6nHdS/EDitC840pr5wtosp9sfxdXXCzkG4b6aJvj/u OfQ4FmxEVbY/jrKNy/9vlbga03tPAjAjfG8EllsQxAaqjPg4XZKhSA8XdoEPFXy2FZSW BuHw0aQaE8JnrRUDYjSxZxHXHIZzsOGwuF4AYDj6dH9NPTOedjBK9hndKStYTPPZBwET dg== From: Frederic Barrat To: clg@kaod.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 1/2] pnv/xive2: Add a get_config() method on the presenter class Date: Thu, 22 Jun 2023 18:25:26 +0200 Message-ID: <20230622162527.1118350-2-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230622162527.1118350-1-fbarrat@linux.ibm.com> References: <20230622162527.1118350-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: CrxpJ9xngw6bOyVrCAA02tM5f8gZWsS5 X-Proofpoint-ORIG-GUID: rws7748ID-nj0H8b9w98UDkLQLYVbmzC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-22_11,2023-06-22_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 mlxlogscore=999 spamscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 phishscore=0 clxscore=1015 priorityscore=1501 adultscore=0 suspectscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306220136 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=fbarrat@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1687451224783100001 Content-Type: text/plain; charset="utf-8" The presenters for xive on P9 and P10 are mostly similar but the behavior can be tuned through a few CQ registers. This patch adds a "get_config" method, which will allow to access that config from the presenter in a later patch. For now, just define the config for the TIMA version. Signed-off-by: Frederic Barrat Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive.c | 11 +++++++++++ hw/intc/pnv_xive2.c | 12 ++++++++++++ hw/intc/spapr_xive.c | 16 ++++++++++++++++ hw/intc/xive.c | 7 +++++++ include/hw/ppc/xive.h | 3 +++ 5 files changed, 49 insertions(+) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 622f9d28b7..e536b3ec26 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -479,6 +479,16 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uin= t8_t format, return count; } =20 +static uint32_t pnv_xive_presenter_get_config(XivePresenter *xptr) +{ + uint32_t cfg =3D 0; + + /* TIMA GEN1 is all P9 knows */ + cfg |=3D XIVE_PRESENTER_GEN1_TIMA_OS; + + return cfg; +} + static uint8_t pnv_xive_get_block_id(XiveRouter *xrtr) { return pnv_xive_block_id(PNV_XIVE(xrtr)); @@ -1991,6 +2001,7 @@ static void pnv_xive_class_init(ObjectClass *klass, v= oid *data) =20 xnc->notify =3D pnv_xive_notify; xpc->match_nvt =3D pnv_xive_match_nvt; + xpc->get_config =3D pnv_xive_presenter_get_config; }; =20 static const TypeInfo pnv_xive_info =3D { diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index ec1edeb385..59534f6843 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -501,6 +501,17 @@ static int pnv_xive2_match_nvt(XivePresenter *xptr, ui= nt8_t format, return count; } =20 +static uint32_t pnv_xive2_presenter_get_config(XivePresenter *xptr) +{ + PnvXive2 *xive =3D PNV_XIVE2(xptr); + uint32_t cfg =3D 0; + + if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS) { + cfg |=3D XIVE_PRESENTER_GEN1_TIMA_OS; + } + return cfg; +} + static uint8_t pnv_xive2_get_block_id(Xive2Router *xrtr) { return pnv_xive2_block_id(PNV_XIVE2(xrtr)); @@ -1987,6 +1998,7 @@ static void pnv_xive2_class_init(ObjectClass *klass, = void *data) xnc->notify =3D pnv_xive2_notify; =20 xpc->match_nvt =3D pnv_xive2_match_nvt; + xpc->get_config =3D pnv_xive2_presenter_get_config; }; =20 static const TypeInfo pnv_xive2_info =3D { diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index dc641cc604..8bcab2846c 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -475,6 +475,21 @@ static int spapr_xive_match_nvt(XivePresenter *xptr, u= int8_t format, return count; } =20 +static uint32_t spapr_xive_presenter_get_config(XivePresenter *xptr) +{ + uint32_t cfg =3D 0; + + /* + * Let's claim GEN1 TIMA format. If running with KVM on P10, the + * correct answer is deep in the hardware and not accessible to + * us. But it shouldn't matter as it only affects the presenter + * as seen by a guest OS. + */ + cfg |=3D XIVE_PRESENTER_GEN1_TIMA_OS; + + return cfg; +} + static uint8_t spapr_xive_get_block_id(XiveRouter *xrtr) { return SPAPR_XIVE_BLOCK_ID; @@ -832,6 +847,7 @@ static void spapr_xive_class_init(ObjectClass *klass, v= oid *data) sicc->post_load =3D spapr_xive_post_load; =20 xpc->match_nvt =3D spapr_xive_match_nvt; + xpc->get_config =3D spapr_xive_presenter_get_config; xpc->in_kernel =3D spapr_xive_in_kernel_xptr; } =20 diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 5204c14b87..34a868b185 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -461,6 +461,13 @@ static void xive_tm_push_os_ctx(XivePresenter *xptr, X= iveTCTX *tctx, } } =20 +static __attribute__((unused)) uint32_t xive_presenter_get_config(XivePres= enter *xptr) +{ + XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr); + + return xpc->get_config(xptr); +} + /* * Define a mapping of "special" operations depending on the TIMA page * offset and the size of the operation. diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index f7eea4ca81..3dfb06e002 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -430,6 +430,8 @@ typedef struct XivePresenterClass XivePresenterClass; DECLARE_CLASS_CHECKERS(XivePresenterClass, XIVE_PRESENTER, TYPE_XIVE_PRESENTER) =20 +#define XIVE_PRESENTER_GEN1_TIMA_OS 0x1 + struct XivePresenterClass { InterfaceClass parent; int (*match_nvt)(XivePresenter *xptr, uint8_t format, @@ -437,6 +439,7 @@ struct XivePresenterClass { bool cam_ignore, uint8_t priority, uint32_t logic_serv, XiveTCTXMatch *match); bool (*in_kernel)(const XivePresenter *xptr); + uint32_t (*get_config)(XivePresenter *xptr); }; =20 int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, --=20 2.41.0 From nobody Sat May 18 14:25:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1687451225; cv=none; d=zohomail.com; s=zohoarc; b=CjY0K8NF3FBOabXnmMjU+hYo4RftTqeIv8gjjnKCvNU6MnSpt0QX+B59/6AVx+8NiiV42FTZFKtNXWrUexcstR3S6PwrmHCzhjt2HMiAZq6RnQwTVG9PIRhyB/LaVqd1miKLli8C5nE/F6Mq4+Oksn+q0+dDNXdUwIGxz7XP3pg= ARC-Message-Signature: i=1; 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Thu, 22 Jun 2023 16:25:28 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=U7MMtxFyDlFmucvR/ikgK8O86T+5qNS0usDaBvKh9oU=; b=UQMl0JvE6uf085XLYNdzUad0w2SWk492zvCBQj5HXRO8zwEDvguk3D/ub4eGwXtGGvjd 4YFLmouTON4Q4+VIgzeF9lYGRJtr1BfPyKrEGxsDNqqtW7/o6CmHp1OxmhzCUW6KO3jz PuxEgPGkAHJ1u4vZJvVk17bqAxG1wYs4RCjMaGEeZ/jDfeKnnjhSiCWLzBYqRjoZy5YN u4bWgxpTIDju2TYtLCiGJ3XemA5o+lgXZGsXdh/gIvvsoUJ/r9VOtw2WcYCTViK/ESl9 pdUlfu86bL1tmjAd8e7s7EV9ujdKzTDcnJenWN+j0xgQTKXwkqkpmvVBTOfrK5mQRkRo 7g== From: Frederic Barrat To: clg@kaod.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 2/2] pnv/xive2: Check TIMA special ops against a dedicated array for P10 Date: Thu, 22 Jun 2023 18:25:27 +0200 Message-ID: <20230622162527.1118350-3-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230622162527.1118350-1-fbarrat@linux.ibm.com> References: <20230622162527.1118350-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: lVz1kLImeYpQy1n1zpARiG0mIKQqM8wd X-Proofpoint-ORIG-GUID: bl2FMchXcqlaAnU_0sStuEcy3Df8_RRZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-22_11,2023-06-22_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxlogscore=999 spamscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306220136 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=fbarrat@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1687451226748100007 Content-Type: text/plain; charset="utf-8" Accessing the TIMA from some specific ring/offset combination can trigger a special operation, with or without side effects. It is implemented in qemu with an array of special operations to compare accesses against. Since the presenter on P10 is pretty similar to P9, we had the full array defined for P9 and we just had a special case for P10 to treat one access differently. With a recent change, 6f2cbd133d4 ("pnv/xive2: Handle TIMA access through all ports"), we now ignore some of the bits of the TIMA address, but that patch managed to botch the detection of the special case for P10. To clean that up, this patch introduces a full array of special ops to be used for P10. The code to detect a special access is common with P9, only the array of operations differs. The presenter can pick the correct array of special ops based on its configuration introduced in a previous patch. Fixes: Coverity CID 1512997, 1512998 Fixes: 6f2cbd133d4 ("pnv/xive2: Handle TIMA access through all ports") Signed-off-by: Frederic Barrat Reviewed-by: C=C3=A9dric Le Goater --- hw/intc/pnv_xive2.c | 32 ---------------------------- hw/intc/xive.c | 52 +++++++++++++++++++++++++++++++++++++-------- 2 files changed, 43 insertions(+), 41 deletions(-) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 59534f6843..ed438a20ed 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1656,17 +1656,6 @@ static const MemoryRegionOps pnv_xive2_ic_tm_indirec= t_ops =3D { /* * TIMA ops */ - -/* - * Special TIMA offsets to handle accesses in a POWER10 way. - * - * Only the CAM line updates done by the hypervisor should be handled - * specifically. - */ -#define HV_PAGE_OFFSET (XIVE_TM_HV_PAGE << TM_SHIFT) -#define HV_PUSH_OS_CTX_OFFSET (HV_PAGE_OFFSET | (TM_QW1_OS + TM_WORD2)) -#define HV_PULL_OS_CTX_OFFSET (HV_PAGE_OFFSET | TM_SPC_PULL_OS_CTX) - static void pnv_xive2_tm_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { @@ -1674,18 +1663,7 @@ static void pnv_xive2_tm_write(void *opaque, hwaddr = offset, PnvXive2 *xive =3D pnv_xive2_tm_get_xive(cpu); XiveTCTX *tctx =3D XIVE_TCTX(pnv_cpu_state(cpu)->intc); XivePresenter *xptr =3D XIVE_PRESENTER(xive); - bool gen1_tima_os =3D - xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; - - offset &=3D TM_ADDRESS_MASK; =20 - /* TODO: should we switch the TM ops table instead ? */ - if (!gen1_tima_os && offset =3D=3D HV_PUSH_OS_CTX_OFFSET) { - xive2_tm_push_os_ctx(xptr, tctx, offset, value, size); - return; - } - - /* Other TM ops are the same as XIVE1 */ xive_tctx_tm_write(xptr, tctx, offset, value, size); } =20 @@ -1695,17 +1673,7 @@ static uint64_t pnv_xive2_tm_read(void *opaque, hwad= dr offset, unsigned size) PnvXive2 *xive =3D pnv_xive2_tm_get_xive(cpu); XiveTCTX *tctx =3D XIVE_TCTX(pnv_cpu_state(cpu)->intc); XivePresenter *xptr =3D XIVE_PRESENTER(xive); - bool gen1_tima_os =3D - xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; - - offset &=3D TM_ADDRESS_MASK; - - /* TODO: should we switch the TM ops table instead ? */ - if (!gen1_tima_os && offset =3D=3D HV_PULL_OS_CTX_OFFSET) { - return xive2_tm_pull_os_ctx(xptr, tctx, offset, size); - } =20 - /* Other TM ops are the same as XIVE1 */ return xive_tctx_tm_read(xptr, tctx, offset, size); } =20 diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 34a868b185..84c079b034 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -20,6 +20,7 @@ #include "monitor/monitor.h" #include "hw/irq.h" #include "hw/ppc/xive.h" +#include "hw/ppc/xive2.h" #include "hw/ppc/xive_regs.h" #include "trace.h" =20 @@ -461,7 +462,7 @@ static void xive_tm_push_os_ctx(XivePresenter *xptr, Xi= veTCTX *tctx, } } =20 -static __attribute__((unused)) uint32_t xive_presenter_get_config(XivePres= enter *xptr) +static uint32_t xive_presenter_get_config(XivePresenter *xptr) { XivePresenterClass *xpc =3D XIVE_PRESENTER_GET_CLASS(xptr); =20 @@ -504,14 +505,47 @@ static const XiveTmOp xive_tm_operations[] =3D { { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_c= tx }, }; =20 -static const XiveTmOp *xive_tm_find_op(hwaddr offset, unsigned size, bool = write) +static const XiveTmOp xive2_tm_operations[] =3D { + /* + * MMIOs below 2K : raw values and special operations without side + * effects + */ + { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL= }, + { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive2_tm_push_os_ctx, NUL= L }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, N= ULL }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push, NULL= }, + { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL, xive_tm_vt_poll= }, + + /* MMIOs above 2K : special operations with side effects */ + { XIVE_TM_OS_PAGE, TM_SPC_ACK_OS_REG, 2, NULL, xive_tm_ack_os_reg = }, + { XIVE_TM_OS_PAGE, TM_SPC_SET_OS_PENDING, 1, xive_tm_set_os_pending, N= ULL }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 4, NULL, xive2_tm_pull_os_ct= x }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_OS_CTX, 8, NULL, xive2_tm_pull_os_ct= x }, + { XIVE_TM_HV_PAGE, TM_SPC_ACK_HV_REG, 2, NULL, xive_tm_ack_hv_reg = }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 4, NULL, xive_tm_pull_pool_c= tx }, + { XIVE_TM_HV_PAGE, TM_SPC_PULL_POOL_CTX, 8, NULL, xive_tm_pull_pool_c= tx }, +}; + +static const XiveTmOp *xive_tm_find_op(XivePresenter *xptr, hwaddr offset, + unsigned size, bool write) { uint8_t page_offset =3D (offset >> TM_SHIFT) & 0x3; uint32_t op_offset =3D offset & TM_ADDRESS_MASK; - int i; + const XiveTmOp *tm_ops; + int i, tm_ops_count; + uint32_t cfg; + + cfg =3D xive_presenter_get_config(xptr); + if (cfg & XIVE_PRESENTER_GEN1_TIMA_OS) { + tm_ops =3D xive_tm_operations; + tm_ops_count =3D ARRAY_SIZE(xive_tm_operations); + } else { + tm_ops =3D xive2_tm_operations; + tm_ops_count =3D ARRAY_SIZE(xive2_tm_operations); + } =20 - for (i =3D 0; i < ARRAY_SIZE(xive_tm_operations); i++) { - const XiveTmOp *xto =3D &xive_tm_operations[i]; + for (i =3D 0; i < tm_ops_count; i++) { + const XiveTmOp *xto =3D &tm_ops[i]; =20 /* Accesses done from a more privileged TIMA page is allowed */ if (xto->page_offset >=3D page_offset && @@ -542,7 +576,7 @@ void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *= tctx, hwaddr offset, * First, check for special operations in the 2K region */ if (offset & TM_SPECIAL_OP) { - xto =3D xive_tm_find_op(offset, size, true); + xto =3D xive_tm_find_op(tctx->xptr, offset, size, true); if (!xto) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid write access at = TIMA " "@%"HWADDR_PRIx"\n", offset); @@ -555,7 +589,7 @@ void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *= tctx, hwaddr offset, /* * Then, for special operations in the region below 2K. */ - xto =3D xive_tm_find_op(offset, size, true); + xto =3D xive_tm_find_op(tctx->xptr, offset, size, true); if (xto) { xto->write_handler(xptr, tctx, offset, value, size); return; @@ -581,7 +615,7 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCT= X *tctx, hwaddr offset, * First, check for special operations in the 2K region */ if (offset & TM_SPECIAL_OP) { - xto =3D xive_tm_find_op(offset, size, false); + xto =3D xive_tm_find_op(tctx->xptr, offset, size, false); if (!xto) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid read access to T= IMA" "@%"HWADDR_PRIx"\n", offset); @@ -594,7 +628,7 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCT= X *tctx, hwaddr offset, /* * Then, for special operations in the region below 2K. */ - xto =3D xive_tm_find_op(offset, size, false); + xto =3D xive_tm_find_op(tctx->xptr, offset, size, false); if (xto) { ret =3D xto->read_handler(xptr, tctx, offset, size); goto out; --=20 2.41.0