From nobody Sun May 19 09:42:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185190; cv=none; d=zohomail.com; s=zohoarc; b=EHq6T9UUE2gAbvgJuACqK7ghaAzHS0bpb+0HlkXN3+enpZ0OWppFvhX8SgKLfVt1G+kuS96qV9HU28jjatcv88H73EFQcRbkgoEnuPyz0v1/PS+ARMjpM8ewUWZpXeRQcrVAyqLT3yR1WkEDrD1CBQU5x+JFi2B5O1Md6JpcL8I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185190; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QYoLjQUBzDtsQLiewQeHZyMx2G0pXSiMumiEHL4MRBM=; b=CKFI8pNOXLWXPNR42Nm6B6lpE6qNR+a4wOlsiaTFm4bIVoghoQA2Vm5vTPrjFrvj8gcfay/SK585zsTzz1DlIfMKR1ZaS2Z9Vnts9Ite/r8s0AHi3W+BbxdfA4lO32DmpazErBEcSEgfcoIiO0h5LVgq1nygOU5QwIbf3/+ALck= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687185190308430.4654974955545; Mon, 19 Jun 2023 07:33:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBFsf-0000YR-KY; Mon, 19 Jun 2023 10:29:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBFse-0000Xx-7Z for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:20 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBFsc-0002AH-54 for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:19 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3f90b8acefdso13061015e9.1 for ; Mon, 19 Jun 2023 07:29:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184956; x=1689776956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=QYoLjQUBzDtsQLiewQeHZyMx2G0pXSiMumiEHL4MRBM=; b=mJyHVSeDzjgtg4uCTejlEQhY7vrzr1rh51K82VWaS5ngwkSJ2eCoYW4/pdG74lVwZV bFcljNGsZ2v4quUPBNpTVX/qUHGfLOwaP+eDoSJOfLi6URq8UQHTGlunY81Tm0PZX7fx RK5lOLcaBrFOvJT2SXqUJgo68WTxOZgUH0njFIMrTh8XylR9uv9+6GBLao4889vyGNqg +Fj6rHhgnACRZA2VMZA015IpmeMAodTuV52+gM35fpFeUHnBxCf5fJVilbCKan2nt4Bh 7jbyMJlxMHmJLSSSCkH1QOyJ6i9k6MwLs6Ixf4Ebk7KeQia8NVHXjjB0WCTjHZZEtAkI t54Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184956; x=1689776956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QYoLjQUBzDtsQLiewQeHZyMx2G0pXSiMumiEHL4MRBM=; b=C3rUlpsKt0abGQPzHhbEDdp8K94+3L7BtO4LyzU/uTmu/UoG2WH3Lh9vGqNUn30rAP 6Xv85WtaHDQuaNCfXfOJPpdB1b6mFgL+9JHemCJDrPjs59qbSGblUN0nHLavwpCcWN3o uzHjz3zxVkcEHzuqetpVuGG9nylyeHNZyWqcMNTnnBKJ7Rsn1XYorIa0B/oUAtQfDJqa A9sB5w4EhEIrsQ+AGkng2kKVnjx7F8KssjbZuLgvP0ARCZ+9xsWSCtfNfttiiQrTCla+ u8XBwpGQmbCSHxHNM0W2donSf5qUuY3OC4hY+6dKr0JmczjBeFZJqM7aSIHBTKYLMKCb +NKg== X-Gm-Message-State: AC+VfDzRauTTrkkgpmGOxOc3nA0pT2Oih5T2f+gF1qDSU6V2JDOkDhG7 LwcV3RcO1TyeVaeWEBb9AoLkJvkp2RlAg0lN8Bo= X-Google-Smtp-Source: ACHHUZ7yk0dYqEmmnTnhq+ZC6tcP89CG5yXHxc2vr7ZgrmPWaxfxhxN0ZjAJJOGW56cYOy6yEtjEXA== X-Received: by 2002:a7b:c407:0:b0:3f7:e605:287c with SMTP id k7-20020a7bc407000000b003f7e605287cmr6359827wmi.40.1687184956636; Mon, 19 Jun 2023 07:29:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/33] target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics Date: Mon, 19 Jun 2023 15:28:42 +0100 Message-Id: <20230619142914.963184-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185190788100001 Content-Type: text/plain; charset="utf-8" The atomic memory operations are supposed to return the old memory data value in the destination register. This value is not sign-extended, even if the operation is the signed minimum or maximum. (In the pseudocode for the instructions the returned data value is passed to ZeroExtend() to create the value in the register.) We got this wrong because we were doing a 32-to-64 zero extend on the result for 8 and 16 bit data values, rather than the correct amount of zero extension. Fix the bug by using ext8u and ext16u for the MO_8 and MO_16 data sizes rather than ext32u. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-2-peter.maydell@linaro.org --- target/arm/tcg/translate-a64.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index aa93f37e216..246e3c15145 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3545,8 +3545,22 @@ static void disas_ldst_atomic(DisasContext *s, uint3= 2_t insn, */ fn(tcg_rt, clean_addr, tcg_rs, get_mem_index(s), mop); =20 - if ((mop & MO_SIGN) && size !=3D MO_64) { - tcg_gen_ext32u_i64(tcg_rt, tcg_rt); + if (mop & MO_SIGN) { + switch (size) { + case MO_8: + tcg_gen_ext8u_i64(tcg_rt, tcg_rt); + break; + case MO_16: + tcg_gen_ext16u_i64(tcg_rt, tcg_rt); + break; + case MO_32: + tcg_gen_ext32u_i64(tcg_rt, tcg_rt); + break; + case MO_64: + break; + default: + g_assert_not_reached(); + } } } =20 --=20 2.34.1 From nobody Sun May 19 09:42:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185384; cv=none; d=zohomail.com; s=zohoarc; b=mNFPLk4ro9yVdWkFMCyt9Ga0px+HSOYjghJvM9iniwJZTd2ztuoNZnhU+jjgOsL7xrLjREA7XHmWTnaSfiq28AHzM/TIOkMTchFNmCFhscrRQFkTL+rdZTt49yXjuK+GRtN9e7EJ3tJka3H3+/bxzRemd83jEV+NkTWU7PUmtM4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185384; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3mwJOChiCQUlVNSGMLtjTUS0WqEV7jHFVk5J5OdBzPw=; b=TpGyelB6SXdF2z/xKBPqW0YAhgCtFZ9nh3/qpTf+5yZsT/EozFiUbWxIWxYVwoe4UaaC7C0W6LSw+w7TJMtN/4RWti6kyTyoPQQCh9+sbHXir4DdlD2SGWiu+KF75ubiAPFlElz8cEJOFgTHMS+/7SReblv17t5lPprG5xKI6Hs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687185384853535.4764689042845; Mon, 19 Jun 2023 07:36:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBFsh-0000ZG-8E; Mon, 19 Jun 2023 10:29:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBFsf-0000YE-Aj for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:21 -0400 Received: from mail-lf1-x12a.google.com ([2a00:1450:4864:20::12a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBFsd-0002AP-2l for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:20 -0400 Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-4f122ff663eso4496103e87.2 for ; Mon, 19 Jun 2023 07:29:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184957; x=1689776957; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3mwJOChiCQUlVNSGMLtjTUS0WqEV7jHFVk5J5OdBzPw=; b=wyVZvXysiK8nU+VO8MMjtO2pB/vpgNMQbSYFkyeZot8GjsJ/SibcZ7LG2ezFXxInOd Wq/vV/AVvghSJGL3N9ke8BIusYIKxsHL+SPY/ZyD/eFwSDixxKVZ4kY8U+cYe6yUme9p oN8VdfeLtae/rRer/Mwxx3JATi79Evs2O/kQmW+1n3u8cQpLeIiEv2tJR7ocx37i0Sau 6f/Gthpdz98kO8pitpBsgD/aKDVwwQAXr3Q+AlDBCCp9dVSfUgwO2099cLPDvjWjs+jp sWobWV6HUMthsf+2OJxZVF5OtrpkVVf5XTrZ1nycaOObVgUrCB6ya/U6G15jZzY+WxBx 5nUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184957; x=1689776957; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3mwJOChiCQUlVNSGMLtjTUS0WqEV7jHFVk5J5OdBzPw=; b=QT8T5q5CHYbCmscc/UfGiFJs+5SH6WDkn4hLDcCBDq540c07hVqVkRvfLrKP0+Qv3H TfBciJs8+kVOq5d56ngCSxpGIOuUqOnM/iGo7rPhbv9jMT6cZqwj3bdO7TRxGiBwv6tv bgLrS3XNIVhFDz/gHFDpy3KZ1VAW6nc2XqUS6NMXqOtC98dg6cllC8pMT4fTAywEwaRy InMdjfVCKxSO4wPHtRGk4G1SOAdpB2DWFw5zouT3szMep3kLxEIPJxr+GhHXuUoQvI1/ RSTK9lji4guJ7pHqwfZ+BP8R0niIoRqBXDO7tZ+MrQFnELcu1PFx0yaWuqCgRaRCXkKl kNRQ== X-Gm-Message-State: AC+VfDzK+Rhnmih6wDk4nkv2YXQiLGePSEr9wchmQsaLEM8T+k+tD0/P /xM9/GO4IDWZz8PKIfSk48uRorPf6CfGniGCwWc= X-Google-Smtp-Source: ACHHUZ4xtYO4bynF2LGOFuA9Th1+oZP3RP7kjKRB8xRFsLXbDAs2fJvP5Rby97BPg1Q9/wzC+fAI5g== X-Received: by 2002:ac2:5f9b:0:b0:4ed:d2cf:857b with SMTP id r27-20020ac25f9b000000b004edd2cf857bmr5373226lfe.5.1687184957097; Mon, 19 Jun 2023 07:29:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/33] target/arm: Return correct result for LDG when ATA=0 Date: Mon, 19 Jun 2023 15:28:43 +0100 Message-Id: <20230619142914.963184-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185386442100005 Content-Type: text/plain; charset="utf-8" The LDG instruction loads the tag from a memory address (identified by [Xn + offset]), and then merges that tag into the destination register Xt. We implemented this correctly for the case when allocation tags are enabled, but didn't get it right when ATA=3D0: instead of merging the tag bits into Xt, we merged them into the memory address [Xn + offset] and then set Xt to that. Merge the tag bits into the old Xt value, as they should be. Cc: qemu-stable@nongnu.org Fixes: c15294c1e36a7dd9b25 ("target/arm: Implement LDG, STG, ST2G instructi= ons") Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 246e3c15145..4ec857bcd8d 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4201,9 +4201,13 @@ static void disas_ldst_tag(DisasContext *s, uint32_t= insn) if (s->ata) { gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); } else { + /* + * Tag access disabled: we must check for aborts on the load + * load from [rn+offset], and then insert a 0 tag into rt. + */ clean_addr =3D clean_data_tbi(s, addr); gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8); - gen_address_with_allocation_tag0(tcg_rt, addr); + gen_address_with_allocation_tag0(tcg_rt, tcg_rt); } } else { tcg_rt =3D cpu_reg_sp(s, rt); --=20 2.34.1 From nobody Sun May 19 09:42:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185270; cv=none; d=zohomail.com; s=zohoarc; b=dJtcEJV2WnULHkcpXZzPrYeyUQNn/RYa1huD2RH6FmXzxjsnRiiGlQEl55y2rZHWBtamde0o1bKlCBFsKpyyKca15FkSRWNPZg97eQBU61OGDGrB/hYSScUKC8MJsrIVWmOi408ah3w8TkS3DDHrVtPxk+7cOJY5QmrjhVIWuMg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185270; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DRiCDQf6VnX7QrB2jN0QiTtMgaauc3TNsMR5cTED1OI=; b=MOnxYcz2CT2OE5s/eselJH6cZpVRvoZjJY6B2jurbYohW2qUdhqpj8M3cl1AtI8fyYidzzGmA8Net7r7e/FC+slv0BeIaHoB/O2Mk1M9lwWoZJ3kaWWtXv7qAbItaN7y+v+MtI0Gq5z6FxD0FnysDd93jAcn+mVVMh4bftQf2S0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168718527036487.80890206781305; Mon, 19 Jun 2023 07:34:30 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBFsj-0000aR-8Y; Mon, 19 Jun 2023 10:29:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBFsf-0000YD-9U for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:21 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBFsc-0002AS-QC for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:20 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-3f904dcc1e2so24313685e9.3 for ; Mon, 19 Jun 2023 07:29:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184957; x=1689776957; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=DRiCDQf6VnX7QrB2jN0QiTtMgaauc3TNsMR5cTED1OI=; b=GjLpGB49fbi9nTLLGboX6JYyxI+R1FsiCeFsNuYDBsv4VAQPS4bdAK5ACDEc8QDS1R XPGRqzliiQjLdulb1FItwrKqHDDBFa5g5TxfmfU4BjpWq9Wn2/jt566tt1cjtm4QjNM6 1jeh5FK6sCz/v32CFZ51IyZpwfsKZfVRdqCSBM+nKL86v/D78tdo9Puf/ZvTJyOgNU/k j9oIpfByncDAwWAp+PZig9gJXYF9FWj0dTyag45rEbPWY6+N5OHt4vPJ5mQsTNW0qhgt LExwCiU9QZa3VnNlRsGZfNONC1IF9xuS03NL6mBnkhuG/bvjPEL+RyMKFZED5Wg/lQjB iK4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184957; x=1689776957; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DRiCDQf6VnX7QrB2jN0QiTtMgaauc3TNsMR5cTED1OI=; b=Ofw6vidfk+m+r3KM4oQ5HJmKpakAPr3BN+L68HNW1YpB8ABqN+H9niag0+cIHpwfqY Qtr68QXPk9cyuQiNTtQLBj3HNfaGYClU7wvF9Zsbw5DoRkYD1X0w8cByHIbwDAvcZ/Ie Mr96h4m2NjPkou1GY6WdYzAG4VbL7hCAhXmZ32CLed7a0dsBx5rFoCRygvTnGFcKPkRl AaKZiWY8EW2jH4/2KmuZQF9gh5JvOrrMX7gWb4hg3XF3BPyhxiBN3BZxUvOLSNwYnvmi WL4yd3SHivBWRCLi6B0n1GSLXwp2vgFV+9HL3JA5cMh2oWh0KJnaCCd0/7DM9SoiUpdF mgrg== X-Gm-Message-State: AC+VfDxavdLUoi9ZOB4bDovYE9NsYCtONyRgThBIE1lJzUqGk8mYhjNa M5YchPYdu0ZpII3F6CKQoUfA6OupjF8THaoofgo= X-Google-Smtp-Source: ACHHUZ4zSKMX+8WRIILnPvXWfHodD9J/Z9OngsBpOvgufZJEhV1FXKbaJSRAwQmkw52B89d3Ahz7FQ== X-Received: by 2002:a05:600c:a38a:b0:3f8:11ec:7c0a with SMTP id hn10-20020a05600ca38a00b003f811ec7c0amr7517338wmb.23.1687184957598; Mon, 19 Jun 2023 07:29:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/33] target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode Date: Mon, 19 Jun 2023 15:28:44 +0100 Message-Id: <20230619142914.963184-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185271582100003 In disas_ldst_reg_imm9() we missed one place where a call to a gen_mte_check* function should now be passed the memop we have created rather than just being passed the size. Fix this. Fixes: 0a9091424d ("target/arm: Pass memop to gen_mte_check1*") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/tcg/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 4ec857bcd8d..d271449431a 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3226,7 +3226,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, =20 clean_addr =3D gen_mte_check1_mmuidx(s, dirty_addr, is_store, writeback || rn !=3D 31, - size, is_unpriv, memidx); + memop, is_unpriv, memidx); =20 if (is_vector) { if (is_store) { --=20 2.34.1 From nobody Sun May 19 09:42:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185048; cv=none; d=zohomail.com; s=zohoarc; b=eD41vWyizMwhzekFBgReq7R7gaNODZEPUpyBC6y6vsh4D2SGa0spuSpRSq1TxkKWyO/gfeCWOQSDEaCyzOrYZ5TyAN57J6eRoVWVE9qmFIdwL9FPSMTm0qw6mn+F3jI6a2q6/bg2Bra2EOGoRzNcXLgbtBy4fSuZUaAo5m45UoA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185048; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=p5AHeXSNq8A09A3osIiOP7MyhShnndOyCGPqtuAITLU=; b=bMF/rXXNWQF4+D/uGKqU38I2RA5PXRzVnnL1D911PuNIJNNlaRI6gMKx7olpdk9KuD0LZeHwq8XJzFaAW5njdcilotHXOhNDmsEVVMd9i4ctYI8ZhnBq1D105Q6TVBwbM25lT6HJfdSnTnU6eF3Bxgqqx7Tlg4WYtoKLAj0ics8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687185048192822.3493492177387; Mon, 19 Jun 2023 07:30:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBFsk-0000bP-1X; Mon, 19 Jun 2023 10:29:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBFsf-0000YS-KG for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:21 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBFsd-0002Aa-Cr for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:21 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-3f9b258f3a2so8619475e9.0 for ; Mon, 19 Jun 2023 07:29:19 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184958; x=1689776958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=p5AHeXSNq8A09A3osIiOP7MyhShnndOyCGPqtuAITLU=; b=ZkeWNEPpCXLOmNzBtXBwP3Q4u14mRPGc6gRwLMi1GEYpfx49XarB2qh8NXa0lEi54J uIcoqSEdmbjHMTqh3DEcBCL2J/wMbjVTdsGLnVZEhkCjtsUS6lpy/VsBUDdXLn4Lslcw tY0sDEmlBxrs0NaTVvEdCMUvXFvcEB7/0Mpi1nMdVYvhcsP7uTvsWuh7/tcy5cygQVug 5luA87Xy2eRmwl4zANbcrHKB3LEs+m8cpp+XoZa8zN2Dc6D+moOvsacozYIbGDCmEl9c scRU3kcJIGBEV2C8vRLIc9cC29h/SNajLV1vyiTp4UZM3bjdeEWhcStULRPyMZP7LA2L e9lQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184958; x=1689776958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p5AHeXSNq8A09A3osIiOP7MyhShnndOyCGPqtuAITLU=; b=PsuZ0BJXrLm90phzYwDkbqfAbQeYD3zgrZU/rovFKxqHGZYmCMiNhyt7anZ3VUpzSc +lX1UKBZZgHeE5kXTuFYHG/yVR0YD98+NtKFSb3MmJR87EcMUo/4SGnGH9E5K2PfW/+a aAP9tUH3AO/XZoGsKwN8Fe7ShrSnaUFkYfXjjY72fMvE2fB0quqUvHecsd+L5dXAImev +VGYw74GVnRjH/wIPab1JyVyCxzdm2MvQG8qqs5lGdAXWcFAsRBA6BH/eCnB0jdtCIcs thyyyvq0W9BwruZlecLGjC39VAJ5TgS5eEJtw+/qiyo7TotDnEwWbafeKFsWub5mEkz5 4rzg== X-Gm-Message-State: AC+VfDxywSAkFAiYTIuZqs/hndoyqjATtzg83AObPNE6mnf+H0CTfOaZ iUWzsaCr1ds+9GypCeu3Z8g98PpZLtZrmvRIQfs= X-Google-Smtp-Source: ACHHUZ6K6pLKOOaaQWupSioekzbbnggtrgrln1xExPLhNTG05smQeqqhfZFBKHEsU8opfuQZ8DqPRA== X-Received: by 2002:a7b:c391:0:b0:3f9:b3f5:b8f with SMTP id s17-20020a7bc391000000b003f9b3f50b8fmr900964wmj.34.1687184958061; Mon, 19 Jun 2023 07:29:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/33] target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores Date: Mon, 19 Jun 2023 15:28:45 +0100 Message-Id: <20230619142914.963184-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185048593100001 Content-Type: text/plain; charset="utf-8" In the recent refactoring we missed a few places which should be calling finalize_memop_asimd() for ASIMD loads and stores but instead are just calling finalize_memop(); fix these. For the disas_ldst_single_struct() and disas_ldst_multiple_struct() cases, this is not a behaviour change because there the size is never MO_128 and the two finalize functions do the same thing. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index d271449431a..1108f8287b8 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3309,6 +3309,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, if (!fp_access_check(s)) { return; } + memop =3D finalize_memop_asimd(s, size); } else { if (size =3D=3D 3 && opc =3D=3D 2) { /* PRFM - prefetch */ @@ -3321,6 +3322,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, is_store =3D (opc =3D=3D 0); is_signed =3D !is_store && extract32(opc, 1, 1); is_extended =3D (size < 3) && extract32(opc, 0, 1); + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); } =20 if (rn =3D=3D 31) { @@ -3333,7 +3335,6 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, =20 tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); =20 - memop =3D finalize_memop(s, size + is_signed * MO_SIGN); clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, true, memop); =20 if (is_vector) { @@ -3398,6 +3399,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, if (!fp_access_check(s)) { return; } + memop =3D finalize_memop_asimd(s, size); } else { if (size =3D=3D 3 && opc =3D=3D 2) { /* PRFM - prefetch */ @@ -3410,6 +3412,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, is_store =3D (opc =3D=3D 0); is_signed =3D !is_store && extract32(opc, 1, 1); is_extended =3D (size < 3) && extract32(opc, 0, 1); + memop =3D finalize_memop(s, size + is_signed * MO_SIGN); } =20 if (rn =3D=3D 31) { @@ -3419,7 +3422,6 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, offset =3D imm12 << size; tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); =20 - memop =3D finalize_memop(s, size + is_signed * MO_SIGN); clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, rn !=3D 31, mem= op); =20 if (is_vector) { @@ -3861,7 +3863,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) * promote consecutive little-endian elements below. */ clean_addr =3D gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != =3D 31, - total, finalize_memop(s, size)); + total, finalize_memop_asimd(s, size)); =20 /* * Consecutive little-endian elements from a single register @@ -4019,7 +4021,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) total =3D selem << scale; tcg_rn =3D cpu_reg_sp(s, rn); =20 - mop =3D finalize_memop(s, scale); + mop =3D finalize_memop_asimd(s, scale); =20 clean_addr =3D gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != =3D 31, total, mop); --=20 2.34.1 From nobody Sun May 19 09:42:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184958; x=1689776958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=tdjaSXSdLsKu4MO87YZyRq3fS44rsN7i4e3GLBzxGpI=; b=BbaTywIG7X23zzkODNkT4yCMbhcsJckN7ouLToei7akrCC1o/aEk6lq3kl3tBxR4Ah 3rN6QRm/vpa1/U9q11tCc1CdQGssHGCRIRZpXsxLF1e+N06wZQ1YPDKdca+5gEeqRcZ6 rocIrS/w/TKpCePhUD45b4WqHFsqd/CLyaFw5AHe81R5Bp6xf6gsuwZOK5fU0zDLXsMU AsBz4fcrL07BXDU0az7Eo5a3wKBRYoibOqbAC79v5zlf2PObZx6NgTagrbQ+HshN7sjS hhA9S0hIgKC4eBJKntHmcW/xavRflzF1/AkfYJR5sa21F1rj6MvZIqZ8XtSk6bkEQwL9 mkUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184958; x=1689776958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tdjaSXSdLsKu4MO87YZyRq3fS44rsN7i4e3GLBzxGpI=; b=RSnYtV2qtiiTcrYDc2rdks/8yG58jV40o53Lj9lIGjAgunJDSPRaukBE8PDkXyuyE3 JPwM1tfeoUV53t/P/PIqOG6wPHTAhyAJNX+q0S+TEdyWxOcCRrALFp+HDHCsRDvOOu9p JFHQ3IJJ4E5WPWL61MNEHI14EXqeZM/UhcSTHb6SIPkVE8RJ5Xj7pWoyl83XmkGvvJ4G 1q3g3f7Mf8E3sx38W9H5gV00+NMu2lnLDjoaWKfi5G1ss2TIEpiVwAU8/eLMeyG+Z6UW S4flbI/y8xiu4AK7rSdrR+vMrv3It5TBat4/jFdkAhSugJNb+VSMRD4O3Zdu0uwL2USj plgw== X-Gm-Message-State: AC+VfDz2DBhe8hjWHSp+Nf86sHnLgE6WdqL8uJZvYIwDG9/fuZgZLlGL +fJ3VI4lwt1pew8SY+NwZmJ/aSqimbC1UCuaucg= X-Google-Smtp-Source: ACHHUZ5Nv5xWahWnrg/N7VWLUKcL+kOUmTfnxu1pR6un3wmC6CZHgwYY1/+F76qISki5UG7l0sMQ8A== X-Received: by 2002:a05:600c:21ca:b0:3f4:2c21:b52c with SMTP id x10-20020a05600c21ca00b003f42c21b52cmr7977997wmj.39.1687184958581; Mon, 19 Jun 2023 07:29:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/33] target/arm: Convert hint instruction space to decodetree Date: Mon, 19 Jun 2023 15:28:46 +0100 Message-Id: <20230619142914.963184-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185090729100007 Content-Type: text/plain; charset="utf-8" Convert the various instructions in the hint instruction space to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-3-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 31 ++++ target/arm/tcg/translate-a64.c | 277 ++++++++++++++++++--------------- 2 files changed, 185 insertions(+), 123 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 12a310d0a31..1efd436e175 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -150,3 +150,34 @@ ERETA 1101011 0100 11111 00001 m:1 11111 111= 11 &reta # ERETAA, ERETAB # the processor is in halting debug state (which we don't implement). # The pattern is listed here as documentation. # DRPS 1101011 0101 11111 000000 11111 00000 + +# Hint instruction group +{ + [ + YIELD 1101 0101 0000 0011 0010 0000 001 11111 + WFE 1101 0101 0000 0011 0010 0000 010 11111 + WFI 1101 0101 0000 0011 0010 0000 011 11111 + # We implement WFE to never block, so our SEV/SEVL are NOPs + # SEV 1101 0101 0000 0011 0010 0000 100 11111 + # SEVL 1101 0101 0000 0011 0010 0000 101 11111 + # Our DGL is a NOP because we don't merge memory accesses anyway. + # DGL 1101 0101 0000 0011 0010 0000 110 11111 + XPACLRI 1101 0101 0000 0011 0010 0000 111 11111 + PACIA1716 1101 0101 0000 0011 0010 0001 000 11111 + PACIB1716 1101 0101 0000 0011 0010 0001 010 11111 + AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 + AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 + ESB 1101 0101 0000 0011 0010 0010 000 11111 + PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 + PACIASP 1101 0101 0000 0011 0010 0011 001 11111 + PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 + PACIBSP 1101 0101 0000 0011 0010 0011 011 11111 + AUTIAZ 1101 0101 0000 0011 0010 0011 100 11111 + AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 + AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 + AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 + ] + # The canonical NOP has CRm =3D=3D op2 =3D=3D 0, but all of the space + # that isn't specifically allocated to an instruction must NOP + NOP 1101 0101 0000 0011 0010 ---- --- 11111 +} diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1108f8287b8..eb8addac1b3 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1649,133 +1649,167 @@ static bool trans_ERETA(DisasContext *s, arg_reta= *a) return true; } =20 -/* HINT instruction group, including various allocated HINTs */ -static void handle_hint(DisasContext *s, uint32_t insn, - unsigned int op1, unsigned int op2, unsigned int c= rm) +static bool trans_NOP(DisasContext *s, arg_NOP *a) { - unsigned int selector =3D crm << 3 | op2; + return true; +} =20 - if (op1 !=3D 3) { - unallocated_encoding(s); - return; +static bool trans_YIELD(DisasContext *s, arg_YIELD *a) +{ + /* + * When running in MTTCG we don't generate jumps to the yield and + * WFE helpers as it won't affect the scheduling of other vCPUs. + * If we wanted to more completely model WFE/SEV so we don't busy + * spin unnecessarily we would need to do something more involved. + */ + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + s->base.is_jmp =3D DISAS_YIELD; } + return true; +} =20 - switch (selector) { - case 0b00000: /* NOP */ - break; - case 0b00011: /* WFI */ - s->base.is_jmp =3D DISAS_WFI; - break; - case 0b00001: /* YIELD */ - /* When running in MTTCG we don't generate jumps to the yield and - * WFE helpers as it won't affect the scheduling of other vCPUs. - * If we wanted to more completely model WFE/SEV so we don't busy - * spin unnecessarily we would need to do something more involved. +static bool trans_WFI(DisasContext *s, arg_WFI *a) +{ + s->base.is_jmp =3D DISAS_WFI; + return true; +} + +static bool trans_WFE(DisasContext *s, arg_WFI *a) +{ + /* + * When running in MTTCG we don't generate jumps to the yield and + * WFE helpers as it won't affect the scheduling of other vCPUs. + * If we wanted to more completely model WFE/SEV so we don't busy + * spin unnecessarily we would need to do something more involved. + */ + if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { + s->base.is_jmp =3D DISAS_WFE; + } + return true; +} + +static bool trans_XPACLRI(DisasContext *s, arg_XPACLRI *a) +{ + if (s->pauth_active) { + gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); + } + return true; +} + +static bool trans_PACIA1716(DisasContext *s, arg_PACIA1716 *a) +{ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + return true; +} + +static bool trans_PACIB1716(DisasContext *s, arg_PACIB1716 *a) +{ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + return true; +} + +static bool trans_AUTIA1716(DisasContext *s, arg_AUTIA1716 *a) +{ + if (s->pauth_active) { + gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + return true; +} + +static bool trans_AUTIB1716(DisasContext *s, arg_AUTIB1716 *a) +{ + if (s->pauth_active) { + gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); + } + return true; +} + +static bool trans_ESB(DisasContext *s, arg_ESB *a) +{ + /* Without RAS, we must implement this as NOP. */ + if (dc_isar_feature(aa64_ras, s)) { + /* + * QEMU does not have a source of physical SErrors, + * so we are only concerned with virtual SErrors. + * The pseudocode in the ARM for this case is + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then + * AArch64.vESBOperation(); + * Most of the condition can be evaluated at translation time. + * Test for EL2 present, and defer test for SEL2 to runtime. */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - s->base.is_jmp =3D DISAS_YIELD; + if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { + gen_helper_vesb(cpu_env); } - break; - case 0b00010: /* WFE */ - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - s->base.is_jmp =3D DISAS_WFE; - } - break; - case 0b00100: /* SEV */ - case 0b00101: /* SEVL */ - case 0b00110: /* DGH */ - /* we treat all as NOP at least for now */ - break; - case 0b00111: /* XPACLRI */ - if (s->pauth_active) { - gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]); - } - break; - case 0b01000: /* PACIA1716 */ - if (s->pauth_active) { - gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); - } - break; - case 0b01010: /* PACIB1716 */ - if (s->pauth_active) { - gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); - } - break; - case 0b01100: /* AUTIA1716 */ - if (s->pauth_active) { - gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); - } - break; - case 0b01110: /* AUTIB1716 */ - if (s->pauth_active) { - gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); - } - break; - case 0b10000: /* ESB */ - /* Without RAS, we must implement this as NOP. */ - if (dc_isar_feature(aa64_ras, s)) { - /* - * QEMU does not have a source of physical SErrors, - * so we are only concerned with virtual SErrors. - * The pseudocode in the ARM for this case is - * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then - * AArch64.vESBOperation(); - * Most of the condition can be evaluated at translation time. - * Test for EL2 present, and defer test for SEL2 to runtime. - */ - if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)= ) { - gen_helper_vesb(cpu_env); - } - } - break; - case 0b11000: /* PACIAZ */ - if (s->pauth_active) { - gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], - tcg_constant_i64(0)); - } - break; - case 0b11001: /* PACIASP */ - if (s->pauth_active) { - gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); - } - break; - case 0b11010: /* PACIBZ */ - if (s->pauth_active) { - gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], - tcg_constant_i64(0)); - } - break; - case 0b11011: /* PACIBSP */ - if (s->pauth_active) { - gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); - } - break; - case 0b11100: /* AUTIAZ */ - if (s->pauth_active) { - gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], - tcg_constant_i64(0)); - } - break; - case 0b11101: /* AUTIASP */ - if (s->pauth_active) { - gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); - } - break; - case 0b11110: /* AUTIBZ */ - if (s->pauth_active) { - gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], - tcg_constant_i64(0)); - } - break; - case 0b11111: /* AUTIBSP */ - if (s->pauth_active) { - gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); - } - break; - default: - /* default specified as NOP equivalent */ - break; } + return true; +} + +static bool trans_PACIAZ(DisasContext *s, arg_PACIAZ *a) +{ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0= )); + } + return true; +} + +static bool trans_PACIASP(DisasContext *s, arg_PACIASP *a) +{ + if (s->pauth_active) { + gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + return true; +} + +static bool trans_PACIBZ(DisasContext *s, arg_PACIBZ *a) +{ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0= )); + } + return true; +} + +static bool trans_PACIBSP(DisasContext *s, arg_PACIBSP *a) +{ + if (s->pauth_active) { + gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + return true; +} + +static bool trans_AUTIAZ(DisasContext *s, arg_AUTIAZ *a) +{ + if (s->pauth_active) { + gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0= )); + } + return true; +} + +static bool trans_AUTIASP(DisasContext *s, arg_AUTIASP *a) +{ + if (s->pauth_active) { + gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + return true; +} + +static bool trans_AUTIBZ(DisasContext *s, arg_AUTIBZ *a) +{ + if (s->pauth_active) { + gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], tcg_constant_i64(0= )); + } + return true; +} + +static bool trans_AUTIBSP(DisasContext *s, arg_AUTIBSP *a) +{ + if (s->pauth_active) { + gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]); + } + return true; } =20 static void gen_clrex(DisasContext *s, uint32_t insn) @@ -2302,9 +2336,6 @@ static void disas_system(DisasContext *s, uint32_t in= sn) return; } switch (crn) { - case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */ - handle_hint(s, insn, op1, op2, crm); - break; case 3: /* CLREX, DSB, DMB, ISB */ handle_sync(s, insn, op1, op2, crm); break; --=20 2.34.1 From nobody Sun May 19 09:42:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185388; cv=none; d=zohomail.com; s=zohoarc; b=MPAzis1XAK9d6X3d9MYTNyUtqD+Eo2r4+eXZF7gP5w0x9+w+jjt9kIU2jVpg1YF8E5RhsYtgMf16/jQ0ELW1HaUhwpRreGz1x+Asf8w0OJmKmzkl56LueojL2LDyKlIjEgF/sEFIq7uWp+lKvvacfKTHh3NTJdfKz2I0ZMkhAb0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185388; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bu9xu6sgDL960caTpLR2VLDgZoGVO/M9+l0fW87QI0Y=; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184959; x=1689776959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=bu9xu6sgDL960caTpLR2VLDgZoGVO/M9+l0fW87QI0Y=; b=vJzuyE/j6PvhSdUc4dxjwMoZqQg5Ug7OBFChZhp8wBbCL61cH5DAtrp2cz3J7qHk3s 02mmatn2fNmoo1da4u87cVH4aV1pinu/4SqR+ayQuANnPifrfx4ikBlZo5nYUH+l+Pqk 7L88kbpoSj5M6Lh00rO7Ap+S4FxucdAUe4lQDtD4ZpHunw0FvfzpnaLmoCdHhpQZmbTi 8IQtTQjPQ92IKy0EqCKpI3ab8yDrAADzqcZWsXx+axlsRNy5n4ovdGdnKov6aPamQWZO QtNBU9aAOaTgJGOcVBvy/ZKACXiUO16z54LXE0iAkigpexQrJgsCWoSY53Iym/eKxkBM EMXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184959; x=1689776959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bu9xu6sgDL960caTpLR2VLDgZoGVO/M9+l0fW87QI0Y=; b=UhvbzQQJYJ1IpZazhgJbCA8f/HTB4uzcq1SbsRXpqgeHyJeNHoFZiiXkGLSH/8TqiG MUD9aiiRo3Z9CooQEYOsZAR3CmiXezXT+sBOt0+syw/2iXehV1nIj4UGpA/+2PR8FELR /ficPRzwm6P9XwYxgeL/0LGKBNHJmCdjrrOyLmBoBtgzFwB9Oei0dfekSU7m3LlTXLfO HDngFtYqWOQqKs0Qowcke6MYLpAl+EfhuzZfgDyOmA8tsUtayzenX+HTicChbcUZoaxL jbvG1HbWympwBUmGrcB4gVfhk+77TdSN4KhFPJb7k7VbFo9OIc44Sfvr3KfOIzV07wKL ornA== X-Gm-Message-State: AC+VfDwk9Qa2t/uufQ/Vu38omhXPC2Zdtlk7c3jhkMQeeL+2+C4416QS JEBqNEA+Rj4cQ97iOtF3BVMNqtN3ZusHjb3TC78= X-Google-Smtp-Source: ACHHUZ6N93mCXCndo1ax5X/sWZur8bmB77Am9LbnVrq1DjrJ8yzw31kX1/Y/YHcy4AljpYjlHY323Q== X-Received: by 2002:a1c:770a:0:b0:3f9:c04:e76c with SMTP id t10-20020a1c770a000000b003f90c04e76cmr3541339wmi.28.1687184958987; Mon, 19 Jun 2023 07:29:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/33] target/arm: Convert barrier insns to decodetree Date: Mon, 19 Jun 2023 15:28:47 +0100 Message-Id: <20230619142914.963184-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185390114100015 Convert the insns in the "Barriers" instruction class to decodetree: CLREX, DSB, DMB, ISB and SB. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-4-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/tcg/a64.decode | 7 +++ target/arm/tcg/translate-a64.c | 92 ++++++++++++++-------------------- 2 files changed, 46 insertions(+), 53 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 1efd436e175..b3608d38dc9 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -181,3 +181,10 @@ ERETA 1101011 0100 11111 00001 m:1 11111 111= 11 &reta # ERETAA, ERETAB # that isn't specifically allocated to an instruction must NOP NOP 1101 0101 0000 0011 0010 ---- --- 11111 } + +# Barriers + +CLREX 1101 0101 0000 0011 0011 ---- 010 11111 +DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 +ISB 1101 0101 0000 0011 0011 ---- 110 11111 +SB 1101 0101 0000 0011 0011 0000 111 11111 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index eb8addac1b3..088dfd8b1fd 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1812,67 +1812,56 @@ static bool trans_AUTIBSP(DisasContext *s, arg_AUTI= BSP *a) return true; } =20 -static void gen_clrex(DisasContext *s, uint32_t insn) +static bool trans_CLREX(DisasContext *s, arg_CLREX *a) { tcg_gen_movi_i64(cpu_exclusive_addr, -1); + return true; } =20 -/* CLREX, DSB, DMB, ISB */ -static void handle_sync(DisasContext *s, uint32_t insn, - unsigned int op1, unsigned int op2, unsigned int c= rm) +static bool trans_DSB_DMB(DisasContext *s, arg_DSB_DMB *a) { + /* We handle DSB and DMB the same way */ TCGBar bar; =20 - if (op1 !=3D 3) { - unallocated_encoding(s); - return; + switch (a->types) { + case 1: /* MBReqTypes_Reads */ + bar =3D TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST; + break; + case 2: /* MBReqTypes_Writes */ + bar =3D TCG_BAR_SC | TCG_MO_ST_ST; + break; + default: /* MBReqTypes_All */ + bar =3D TCG_BAR_SC | TCG_MO_ALL; + break; } + tcg_gen_mb(bar); + return true; +} =20 - switch (op2) { - case 2: /* CLREX */ - gen_clrex(s, insn); - return; - case 4: /* DSB */ - case 5: /* DMB */ - switch (crm & 3) { - case 1: /* MBReqTypes_Reads */ - bar =3D TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST; - break; - case 2: /* MBReqTypes_Writes */ - bar =3D TCG_BAR_SC | TCG_MO_ST_ST; - break; - default: /* MBReqTypes_All */ - bar =3D TCG_BAR_SC | TCG_MO_ALL; - break; - } - tcg_gen_mb(bar); - return; - case 6: /* ISB */ - /* We need to break the TB after this insn to execute - * a self-modified code correctly and also to take - * any pending interrupts immediately. - */ - reset_btype(s); - gen_goto_tb(s, 0, 4); - return; +static bool trans_ISB(DisasContext *s, arg_ISB *a) +{ + /* + * We need to break the TB after this insn to execute + * self-modifying code correctly and also to take + * any pending interrupts immediately. + */ + reset_btype(s); + gen_goto_tb(s, 0, 4); + return true; +} =20 - case 7: /* SB */ - if (crm !=3D 0 || !dc_isar_feature(aa64_sb, s)) { - goto do_unallocated; - } - /* - * TODO: There is no speculation barrier opcode for TCG; - * MB and end the TB instead. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, 4); - return; - - default: - do_unallocated: - unallocated_encoding(s); - return; +static bool trans_SB(DisasContext *s, arg_SB *a) +{ + if (!dc_isar_feature(aa64_sb, s)) { + return false; } + /* + * TODO: There is no speculation barrier opcode for TCG; + * MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, 4); + return true; } =20 static void gen_xaflag(void) @@ -2336,9 +2325,6 @@ static void disas_system(DisasContext *s, uint32_t in= sn) return; } switch (crn) { - case 3: /* CLREX, DSB, DMB, ISB */ - handle_sync(s, insn, op1, op2, crm); - break; case 4: /* MSR (immediate) */ handle_msr_i(s, insn, op1, op2, crm); break; --=20 2.34.1 From nobody Sun May 19 09:42:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185056; cv=none; d=zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184959; x=1689776959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=EhniXz311o/2DcPgdcKAEpSrZXehm+PpvIlCx/ZyH40=; b=M05wa6NuqfLZtUxI2Eq4C+jES/JGo4SSb0VTNy36Nz4VlcySUN0XORWuat/KyK0gCF iBFH9WlfftHTEVCjLlbCgyVn34RYw9ccPFw7ifa5zPJAdxdrRFkcgxJSw+eFo2iTSMsA X8ym3ZjFs9F+L4Kb1cnqDUxnA+LF0Jt/xDR+SHxy+82NMJ3h5OQXBYjoPpnCX8x0RMnt YFutFtRRfv2tqnFSxAGJ0t+37BhZ3ZnAKopbAgh742wtxZEZCzsVPCvHfO5wVeug7SUX NDBIIfNf6st0tNQdBIYoNijwWFps3ak+cWwIf9XmgGTlG3e/LcNthHFbYlTZ1NjYYTw0 QiVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184959; x=1689776959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EhniXz311o/2DcPgdcKAEpSrZXehm+PpvIlCx/ZyH40=; b=ANCq86zsPvlx5VzSv9/VVIsKLO4hzse1pg/17Lq0tbSdEUeez/Huia8uXO3DUexD/7 8Qoy5YDugfZhM7uDiR3/hGz2l8cLa3fj+1qAEWot8wuwBj7kfgowC14W7cX+1x2UoAG+ OZSXuL9f2Fj7KA1zbMWwDcydVpaV1Rikoa8dzMpKtBqgpHXcbyR4qlX80TuIAtSKBCSj 2AZ5AeXezqeK4kcwgq86GhTX5SkK/XatbOggArWeLaVCnZM1T5xAnlb/xhPaWozCv5l3 AsqUoqdI1LOnhnpIj0FLPn7LSbqKVHLViguO6qamSRaB3tp0CG8uWlGG40OqP7f2DV6C vJAA== X-Gm-Message-State: AC+VfDzZQBlWhdU5OSsvSybzKcTYyid80HJeIe4M0DQDJyhoKQb+ftnj 3KADO3wGOmB9VWLKclmBFBIjN9hxqBHgbl0TbLM= X-Google-Smtp-Source: ACHHUZ50M0GHqy+mCLcse1lQD5WR9zm1bMkAuE+l56frfmGNXvT7oylRkQTOce1kVAc+rchNBHaUoQ== X-Received: by 2002:a1c:4b11:0:b0:3f7:e78e:8a41 with SMTP id y17-20020a1c4b11000000b003f7e78e8a41mr14072873wma.18.1687184959425; Mon, 19 Jun 2023 07:29:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/33] target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree Date: Mon, 19 Jun 2023 15:28:48 +0100 Message-Id: <20230619142914.963184-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185057687100003 Content-Type: text/plain; charset="utf-8" Convert the CFINV, XAFLAG and AXFLAG insns to decodetree. The old decoder handles these in handle_msr_i(), but the architecture defines them as separate instructions from MSR (immediate). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-5-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 6 ++++ target/arm/tcg/translate-a64.c | 53 +++++++++++++++++----------------- 2 files changed, 32 insertions(+), 27 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index b3608d38dc9..fd23fc3e0ff 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -188,3 +188,9 @@ CLREX 1101 0101 0000 0011 0011 ---- 010 11111 DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111 ISB 1101 0101 0000 0011 0011 ---- 110 11111 SB 1101 0101 0000 0011 0011 0000 111 11111 + +# PSTATE + +CFINV 1101 0101 0000 0 000 0100 0000 000 11111 +XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 +AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 088dfd8b1fd..c1b02b96183 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1864,9 +1864,24 @@ static bool trans_SB(DisasContext *s, arg_SB *a) return true; } =20 -static void gen_xaflag(void) +static bool trans_CFINV(DisasContext *s, arg_CFINV *a) { - TCGv_i32 z =3D tcg_temp_new_i32(); + if (!dc_isar_feature(aa64_condm_4, s)) { + return false; + } + tcg_gen_xori_i32(cpu_CF, cpu_CF, 1); + return true; +} + +static bool trans_XAFLAG(DisasContext *s, arg_XAFLAG *a) +{ + TCGv_i32 z; + + if (!dc_isar_feature(aa64_condm_5, s)) { + return false; + } + + z =3D tcg_temp_new_i32(); =20 tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0); =20 @@ -1890,10 +1905,16 @@ static void gen_xaflag(void) =20 /* C | Z */ tcg_gen_or_i32(cpu_CF, cpu_CF, z); + + return true; } =20 -static void gen_axflag(void) +static bool trans_AXFLAG(DisasContext *s, arg_AXFLAG *a) { + if (!dc_isar_feature(aa64_condm_5, s)) { + return false; + } + tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */ tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */ =20 @@ -1902,6 +1923,8 @@ static void gen_axflag(void) =20 tcg_gen_movi_i32(cpu_NF, 0); tcg_gen_movi_i32(cpu_VF, 0); + + return true; } =20 /* MSR (immediate) - move immediate to processor state field */ @@ -1914,30 +1937,6 @@ static void handle_msr_i(DisasContext *s, uint32_t i= nsn, s->base.is_jmp =3D DISAS_TOO_MANY; =20 switch (op) { - case 0x00: /* CFINV */ - if (crm !=3D 0 || !dc_isar_feature(aa64_condm_4, s)) { - goto do_unallocated; - } - tcg_gen_xori_i32(cpu_CF, cpu_CF, 1); - s->base.is_jmp =3D DISAS_NEXT; - break; - - case 0x01: /* XAFlag */ - if (crm !=3D 0 || !dc_isar_feature(aa64_condm_5, s)) { - goto do_unallocated; - } - gen_xaflag(); - s->base.is_jmp =3D DISAS_NEXT; - break; - - case 0x02: /* AXFlag */ - if (crm !=3D 0 || !dc_isar_feature(aa64_condm_5, s)) { - goto do_unallocated; - } - gen_axflag(); - s->base.is_jmp =3D DISAS_NEXT; - break; - case 0x03: /* UAO */ if (!dc_isar_feature(aa64_uao, s) || s->current_el =3D=3D 0) { goto do_unallocated; --=20 2.34.1 From nobody Sun May 19 09:42:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185041; cv=none; d=zohomail.com; s=zohoarc; b=gS37to2MfksnTdHJ/ozgOd8fiEU/vH8H25c+67ACFQGqVIVjw9RevmYZNTcUOrKMqob3moHCXyxfEvHJwfEn8JqEajM698t0G16u2Fd1IVqozl4YuffHWfs8LIuZOjgB2qu3Hw5UiB2oaiSaeWjDr27z7EIue8HiJe4gRjAF5rY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185041; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gOvf60YN74xnTNfixpVWMsKoOKc9WSdyaA7UMG2RTxA=; b=F9UHuYUJKF69ygLWbRrd040z4Fj9tOPWb3vflTfJEQgWHueRD1PpKi2oJj5N13mhmYTF6vDgklZ0gJ1wlo71PVzEKE8WFCoQkcsiF2gOf6mmE7vzyyRA2OsmF3l/NtNBkol9uWpyYOERGu+VUasCcxX5l+jd/DjolxGfdopZW7U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687185041386528.1314095810019; Mon, 19 Jun 2023 07:30:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBFss-0000e9-MV; Mon, 19 Jun 2023 10:29:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBFsh-0000Zf-RX for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:23 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBFsf-0002BO-NI for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:23 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-3f90b8acefeso15540665e9.0 for ; Mon, 19 Jun 2023 07:29:21 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184960; x=1689776960; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=gOvf60YN74xnTNfixpVWMsKoOKc9WSdyaA7UMG2RTxA=; b=xv9Eiv/myW9IUryTAgiBc+HclQ0xq+GHKtMIpSvu4BMxblovgA+a5Caz3w63zWI7ys LJN1Bj4wKAUj59vEx6BFPdOrUFJFwViI6vQiqkHyby/ieFPXHuxvcViDnRRVX3TB1WS4 y7mVeuNAxVQNJexRN+HDLuM+ztECKLVdH2G6EsuNjtDUToHh3dpnhwAVgeIlDoautklC rpl9/bRr3I4pDcAzCrRbH/qsGOY9ZfbZAeYH6R9e5KDd98MS7Pauj1JjDtlxLESQhrkZ 0pIrZfu01FobuuTzEtwt6YMGFeNO0r2yoqN0Xl1pnxRXjHM1Ojfrh5aSLFYFt17SIF3C 7sug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184960; x=1689776960; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gOvf60YN74xnTNfixpVWMsKoOKc9WSdyaA7UMG2RTxA=; b=gRgjML9qoXsnSkodJH8/ZRqoMoVYrOP8AzqoH16HTIUfI7jylSiSa7Y68Q6UPfJ0Bf t0nK95GmkekNRbRDsLp+3QISFCcYiHOTxVBCm2lRG45MfobI2lDPZbA4ZK+qpMY9VKSn kTZTo0LKP4tfAt1O5ZAmZxcGhbPy8CwE+cG/xuqx2iQvmpdYSkBcx6Jo3r5KfIvJ8cR8 Ptch4X5vNSYhKiD/9V4AJVZ5H1O4lN8hxk6o31jL4j0JDKsy+u2WOPsJxIskfmbGgCHj NQq8nDTV3SXfxoTDGi65OtfR3XdEEKZ4q1H1qe392B1oekZxIO+8uSTvwnprSH3K6re0 SLmw== X-Gm-Message-State: AC+VfDzNUlGVIjcvgcY0ji52TJVo3Vr1jII39IHZeCx7SgS2q2rhoqOC fzDq8laTWFuAY0pmdMLPVuEikIeMq2HhvISCr3E= X-Google-Smtp-Source: ACHHUZ7WZ/dgysny3z0GtkzLGIz6T8Nz4KhTq2L7E2k3t5VyJFEDEjgApDW+26ieUY02FF1JA3NUkQ== X-Received: by 2002:a05:600c:2245:b0:3f7:f584:579b with SMTP id a5-20020a05600c224500b003f7f584579bmr6978590wmm.9.1687184960003; Mon, 19 Jun 2023 07:29:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/33] target/arm: Convert MSR (immediate) to decodetree Date: Mon, 19 Jun 2023 15:28:49 +0100 Message-Id: <20230619142914.963184-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185042536100001 Content-Type: text/plain; charset="utf-8" Convert the MSR (immediate) insn to decodetree. Our implementation has basically no commonality between the different destinations, so we decode the destination register in a64.decode. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-6-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 13 ++ target/arm/tcg/translate-a64.c | 251 ++++++++++++++++----------------- 2 files changed, 136 insertions(+), 128 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index fd23fc3e0ff..4f94a08907b 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -194,3 +194,16 @@ SB 1101 0101 0000 0011 0011 0000 111 11111 CFINV 1101 0101 0000 0 000 0100 0000 000 11111 XAFLAG 1101 0101 0000 0 000 0100 0000 001 11111 AXFLAG 1101 0101 0000 0 000 0100 0000 010 11111 + +# These are architecturally all "MSR (immediate)"; we decode the destinati= on +# register too because there is no commonality in our implementation. +@msr_i .... .... .... . ... .... imm:4 ... ..... +MSR_i_UAO 1101 0101 0000 0 000 0100 .... 011 11111 @msr_i +MSR_i_PAN 1101 0101 0000 0 000 0100 .... 100 11111 @msr_i +MSR_i_SPSEL 1101 0101 0000 0 000 0100 .... 101 11111 @msr_i +MSR_i_SBSS 1101 0101 0000 0 011 0100 .... 001 11111 @msr_i +MSR_i_DIT 1101 0101 0000 0 011 0100 .... 010 11111 @msr_i +MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 11111 @msr_i +MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i +MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i +MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index c1b02b96183..8c57b48d81f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1927,124 +1927,130 @@ static bool trans_AXFLAG(DisasContext *s, arg_AXF= LAG *a) return true; } =20 -/* MSR (immediate) - move immediate to processor state field */ -static void handle_msr_i(DisasContext *s, uint32_t insn, - unsigned int op1, unsigned int op2, unsigned int = crm) +static bool trans_MSR_i_UAO(DisasContext *s, arg_i *a) { - int op =3D op1 << 3 | op2; - - /* End the TB by default, chaining is ok. */ - s->base.is_jmp =3D DISAS_TOO_MANY; - - switch (op) { - case 0x03: /* UAO */ - if (!dc_isar_feature(aa64_uao, s) || s->current_el =3D=3D 0) { - goto do_unallocated; - } - if (crm & 1) { - set_pstate_bits(PSTATE_UAO); - } else { - clear_pstate_bits(PSTATE_UAO); - } - gen_rebuild_hflags(s); - break; - - case 0x04: /* PAN */ - if (!dc_isar_feature(aa64_pan, s) || s->current_el =3D=3D 0) { - goto do_unallocated; - } - if (crm & 1) { - set_pstate_bits(PSTATE_PAN); - } else { - clear_pstate_bits(PSTATE_PAN); - } - gen_rebuild_hflags(s); - break; - - case 0x05: /* SPSel */ - if (s->current_el =3D=3D 0) { - goto do_unallocated; - } - gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(crm & PSTATE_SP)); - break; - - case 0x19: /* SSBS */ - if (!dc_isar_feature(aa64_ssbs, s)) { - goto do_unallocated; - } - if (crm & 1) { - set_pstate_bits(PSTATE_SSBS); - } else { - clear_pstate_bits(PSTATE_SSBS); - } - /* Don't need to rebuild hflags since SSBS is a nop */ - break; - - case 0x1a: /* DIT */ - if (!dc_isar_feature(aa64_dit, s)) { - goto do_unallocated; - } - if (crm & 1) { - set_pstate_bits(PSTATE_DIT); - } else { - clear_pstate_bits(PSTATE_DIT); - } - /* There's no need to rebuild hflags because DIT is a nop */ - break; - - case 0x1e: /* DAIFSet */ - gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(crm)); - break; - - case 0x1f: /* DAIFClear */ - gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(crm)); - /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. = */ - s->base.is_jmp =3D DISAS_UPDATE_EXIT; - break; - - case 0x1c: /* TCO */ - if (dc_isar_feature(aa64_mte, s)) { - /* Full MTE is enabled -- set the TCO bit as directed. */ - if (crm & 1) { - set_pstate_bits(PSTATE_TCO); - } else { - clear_pstate_bits(PSTATE_TCO); - } - gen_rebuild_hflags(s); - /* Many factors, including TCO, go into MTE_ACTIVE. */ - s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; - } else if (dc_isar_feature(aa64_mte_insn_reg, s)) { - /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. = */ - s->base.is_jmp =3D DISAS_NEXT; - } else { - goto do_unallocated; - } - break; - - case 0x1b: /* SVCR* */ - if (!dc_isar_feature(aa64_sme, s) || crm < 2 || crm > 7) { - goto do_unallocated; - } - if (sme_access_check(s)) { - int old =3D s->pstate_sm | (s->pstate_za << 1); - int new =3D (crm & 1) * 3; - int msk =3D (crm >> 1) & 3; - - if ((old ^ new) & msk) { - /* At least one bit changes. */ - gen_helper_set_svcr(cpu_env, tcg_constant_i32(new), - tcg_constant_i32(msk)); - } else { - s->base.is_jmp =3D DISAS_NEXT; - } - } - break; - - default: - do_unallocated: - unallocated_encoding(s); - return; + if (!dc_isar_feature(aa64_uao, s) || s->current_el =3D=3D 0) { + return false; } + if (a->imm & 1) { + set_pstate_bits(PSTATE_UAO); + } else { + clear_pstate_bits(PSTATE_UAO); + } + gen_rebuild_hflags(s); + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_PAN(DisasContext *s, arg_i *a) +{ + if (!dc_isar_feature(aa64_pan, s) || s->current_el =3D=3D 0) { + return false; + } + if (a->imm & 1) { + set_pstate_bits(PSTATE_PAN); + } else { + clear_pstate_bits(PSTATE_PAN); + } + gen_rebuild_hflags(s); + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_SPSEL(DisasContext *s, arg_i *a) +{ + if (s->current_el =3D=3D 0) { + return false; + } + gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(a->imm & PSTATE_SP)); + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_SBSS(DisasContext *s, arg_i *a) +{ + if (!dc_isar_feature(aa64_ssbs, s)) { + return false; + } + if (a->imm & 1) { + set_pstate_bits(PSTATE_SSBS); + } else { + clear_pstate_bits(PSTATE_SSBS); + } + /* Don't need to rebuild hflags since SSBS is a nop */ + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_DIT(DisasContext *s, arg_i *a) +{ + if (!dc_isar_feature(aa64_dit, s)) { + return false; + } + if (a->imm & 1) { + set_pstate_bits(PSTATE_DIT); + } else { + clear_pstate_bits(PSTATE_DIT); + } + /* There's no need to rebuild hflags because DIT is a nop */ + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_TCO(DisasContext *s, arg_i *a) +{ + if (dc_isar_feature(aa64_mte, s)) { + /* Full MTE is enabled -- set the TCO bit as directed. */ + if (a->imm & 1) { + set_pstate_bits(PSTATE_TCO); + } else { + clear_pstate_bits(PSTATE_TCO); + } + gen_rebuild_hflags(s); + /* Many factors, including TCO, go into MTE_ACTIVE. */ + s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; + return true; + } else if (dc_isar_feature(aa64_mte_insn_reg, s)) { + /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */ + return true; + } else { + /* Insn not present */ + return false; + } +} + +static bool trans_MSR_i_DAIFSET(DisasContext *s, arg_i *a) +{ + gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(a->imm)); + s->base.is_jmp =3D DISAS_TOO_MANY; + return true; +} + +static bool trans_MSR_i_DAIFCLEAR(DisasContext *s, arg_i *a) +{ + gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(a->imm)); + /* Exit the cpu loop to re-evaluate pending IRQs. */ + s->base.is_jmp =3D DISAS_UPDATE_EXIT; + return true; +} + +static bool trans_MSR_i_SVCR(DisasContext *s, arg_MSR_i_SVCR *a) +{ + if (!dc_isar_feature(aa64_sme, s) || a->mask =3D=3D 0) { + return false; + } + if (sme_access_check(s)) { + int old =3D s->pstate_sm | (s->pstate_za << 1); + int new =3D a->imm * 3; + + if ((old ^ new) & a->mask) { + /* At least one bit changes. */ + gen_helper_set_svcr(cpu_env, tcg_constant_i32(new), + tcg_constant_i32(a->mask)); + s->base.is_jmp =3D DISAS_TOO_MANY; + } + } + return true; } =20 static void gen_get_nzcv(TCGv_i64 tcg_rt) @@ -2319,18 +2325,7 @@ static void disas_system(DisasContext *s, uint32_t i= nsn) rt =3D extract32(insn, 0, 5); =20 if (op0 =3D=3D 0) { - if (l || rt !=3D 31) { - unallocated_encoding(s); - return; - } - switch (crn) { - case 4: /* MSR (immediate) */ - handle_msr_i(s, insn, op1, op2, crm); - break; - default: - unallocated_encoding(s); - break; - } + unallocated_encoding(s); return; } handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185088; cv=none; d=zohomail.com; s=zohoarc; b=Me2LEtXFZTOXJg/bv1XXmg6sDdNk/Au8iZJpf/HNxf4yQAlF6HJBjOfV3LsIhSccrWelt1YbcMdwoHmdcr1NH9RO6HvfWy3wd3GHf6onJrGTcAgpBhEX1DRyyPU2cQ/7omzxOaPExiY6cAzNkQVim9PobCREI8Wq1EhIYpHktzU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185088; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184960; x=1689776960; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7l+ZsA3tEJ7e9mj81PR383GnadYfBL0LIimUCD7qHwo=; b=jOrIJqJ5tvNmD4yrdsLz6lFIfcw/rdZASyequoaNAXChvdvm9h14cL4fhIl/w7LPbR bbm/R07jRHUA4l7hpsI1ZCL41jFS+KLUsSAM+K56sCfdbDXeY7FOF3S+PQOrQBK25JQF o4xWPzd/aojMKKqTxIt+zJX1c+GSaYaYcnoBxCowU7CwXUPLPnFU5P142N7VzlQab2RJ G3/l5UhFeFSKwAf5Q7QmAMT0J8AQeHCtg6UBGfjRpo392rbZCb1l6eu8giio2UvdMYlE mbAZZ54cZlk4nTcSpW+pnRdUxNWAINJnW++kZPKcdtY8FIH62JogBMP/tUEmK85ZJ3io BeDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184960; x=1689776960; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7l+ZsA3tEJ7e9mj81PR383GnadYfBL0LIimUCD7qHwo=; b=hGqnYasZhJ3PNhgPSrRe8g46DRsoioIlkymoMGeiKNcjHJ33Yrga36IwU/r0rn/roM A//FxaM9D0+gmMWzK/PIgyhkJEOYaoJ+V4b0tn4Aa7EUdCffqx2+eVyJb15muzjLV3Sh EyFSWmgojRXXid2ib7tUCEnCQCqgpez3Mmpwj16yr7/bCU2Q5vYfrapxQvpQoECcNr6h 3au/bfq4fErufuv6dSoVUXsQ7GsCmBbgy3Dd5n2b0cMiMLQRKqqeBLpkytaZqwcZ5CrX wwbYywBzsSda/kZ56Uj/s1brBCW1GDjJ7L2RT4bq5KI8bozGbYYK/L+7Zpw1M4V1LJDv XRgQ== X-Gm-Message-State: AC+VfDxigg1QexwF0wchagc8G3UPhHuii5xCO4VSs2gm6C3sr/wSWzuh Mj0ulhufTdvQ07ltNXOtDVgMCvauQQq1B9bJpx4= X-Google-Smtp-Source: ACHHUZ75mBCVtX2rwHmEBpFQw0oPWU2Fm16bsHZDzGFm9yZmx43UB3Z+lR6lqy3Iwe2bvDlEx5DxuA== X-Received: by 2002:a05:600c:2905:b0:3f9:b535:381b with SMTP id i5-20020a05600c290500b003f9b535381bmr377665wmd.35.1687184960432; Mon, 19 Jun 2023 07:29:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/33] target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree Date: Mon, 19 Jun 2023 15:28:50 +0100 Message-Id: <20230619142914.963184-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185088692100001 Convert MSR (reg), MRS, SYS, SYSL to decodetree. For QEMU these are all essentially the same instruction (system register access). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-7-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/tcg/a64.decode | 8 ++++++++ target/arm/tcg/translate-a64.c | 32 +++++--------------------------- 2 files changed, 13 insertions(+), 27 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 4f94a08907b..c49215cca8d 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -207,3 +207,11 @@ MSR_i_TCO 1101 0101 0000 0 011 0100 .... 100 111= 11 @msr_i MSR_i_DAIFSET 1101 0101 0000 0 011 0100 .... 110 11111 @msr_i MSR_i_DAIFCLEAR 1101 0101 0000 0 011 0100 .... 111 11111 @msr_i MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111 + +# MRS, MSR (register), SYS, SYSL. These are all essentially the +# same instruction as far as QEMU is concerned. +# NB: op0 is bits [20:19], but op0=3D0b00 is other insns, so we have +# to hand-decode it. +SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D1 +SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D2 +SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D3 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8c57b48d81f..74a389da4a7 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2122,7 +2122,7 @@ static void gen_sysreg_undef(DisasContext *s, bool is= read, * These are all essentially the same insn in 'read' and 'write' * versions, with varying op0 fields. */ -static void handle_sys(DisasContext *s, uint32_t insn, bool isread, +static void handle_sys(DisasContext *s, bool isread, unsigned int op0, unsigned int op1, unsigned int op= 2, unsigned int crn, unsigned int crm, unsigned int rt) { @@ -2307,28 +2307,10 @@ static void handle_sys(DisasContext *s, uint32_t in= sn, bool isread, } } =20 -/* System - * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0 - * +---------------------+---+-----+-----+-------+-------+-----+------+ - * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt | - * +---------------------+---+-----+-----+-------+-------+-----+------+ - */ -static void disas_system(DisasContext *s, uint32_t insn) +static bool trans_SYS(DisasContext *s, arg_SYS *a) { - unsigned int l, op0, op1, crn, crm, op2, rt; - l =3D extract32(insn, 21, 1); - op0 =3D extract32(insn, 19, 2); - op1 =3D extract32(insn, 16, 3); - crn =3D extract32(insn, 12, 4); - crm =3D extract32(insn, 8, 4); - op2 =3D extract32(insn, 5, 3); - rt =3D extract32(insn, 0, 5); - - if (op0 =3D=3D 0) { - unallocated_encoding(s); - return; - } - handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); + handle_sys(s, a->l, a->op0, a->op1, a->op2, a->crn, a->crm, a->rt); + return true; } =20 /* Exception generation @@ -2435,11 +2417,7 @@ static void disas_b_exc_sys(DisasContext *s, uint32_= t insn) switch (extract32(insn, 25, 7)) { case 0x6a: /* Exception generation / System */ if (insn & (1 << 24)) { - if (extract32(insn, 22, 2) =3D=3D 0) { - disas_system(s, insn); - } else { - unallocated_encoding(s); - } + unallocated_encoding(s); } else { disas_exc(s, insn); } --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185192; cv=none; d=zohomail.com; s=zohoarc; b=FcuxBp3dfb0g538SAhgoviB1t/CFZlI4/5aFQ+P+r7IHp2p7ixUw8yflx/+LI2xPyMKZ9BcI9ghAxqiLyzGhCiry3kqyMJKfR91IsNSToO8aQsN6lM5KLLrzfeY9bF1MfrOV6WMu5WZiNkCXgkDF9t+6RTLp4d02DLaFUQs3pm8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185192; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Hv0rchOEEfJPVEoDeEXmaUe1CECfSOxYqHxG0bO7LPk=; b=NC+oVCil5PwfxwTA6xABRH/b1Bl+fRZ8JpNP6B+H7kwuoVCYlWNQyQ3DT/uzZiA90BxrmZCIUTxtS+PBBeQ6jzGoi11y9vih0/n+JranVftqVcNWx+elrXkhv5VBewBTVAQa4FEIcbdeU68YVS/CGUErj3AwH1QdGQ3+idoxfpg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168718519280210.03012809706604; Mon, 19 Jun 2023 07:33:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBFsl-0000cY-JL; Mon, 19 Jun 2023 10:29:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBFsi-0000aD-Q0 for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:24 -0400 Received: from mail-lf1-x135.google.com ([2a00:1450:4864:20::135]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBFsg-0002C8-Jv for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:24 -0400 Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-4f867700f36so2395275e87.0 for ; Mon, 19 Jun 2023 07:29:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184961; x=1689776961; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Hv0rchOEEfJPVEoDeEXmaUe1CECfSOxYqHxG0bO7LPk=; b=yN8zbjoZ01J/E/bTph9yxu/8RGmfJw99jLqBMAPzKZ6YSINjZ0gzbZnsO0N3ptWqpD Tf8+UtoNz9P16zVSA/xvHPwGF1jqm7ZVTeBm1YU9kVrw2k1J4qvUauz66Bt0G+RR2K9b xxEaCY5oCfnyeF/1ku6TMIq2VVrPOpdfRT+v8bbhBMhw2QVgghFX5KsgX5pHxgcCqlJ9 9X5a3jXj63f8O3cojGbEGwheykPg08OXa7GCC9I1PLaxzpdL5KSvMzz53FN7LMB1bz/b kNjjvllVKYGZXMjOO6aN4Fu2IiLZgFTmFMi8f/LKV5XSwewmn5Ev/E8O8CGWuvnF/eqU /JaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184961; x=1689776961; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hv0rchOEEfJPVEoDeEXmaUe1CECfSOxYqHxG0bO7LPk=; b=jqkkuzhHaf5ChQ0Qjq79j4NFjz1unuIQSiw5zxolMTyAssbvtomQCWoI2CPWXO0ccT 3DY9+0xfCCFXWdzV8RlsW9oKQDo473dqYuiqmZFwoRiQOrlyKQfJ16Ghlb6nldpFIDVJ ZpnVJv7sj7g6R+PcHWGfK2ZhjYZnBNS/EiziOM/dOSIU6NetabRrTZwBRbNsdLw0waSY ZHvqZ0ASZ9JdepKNHYsvJmyr8O0X1EWJ7i+cXG8CWmB2fyyGRHWKgCWkch4ERwFLp9mQ X2HN0xYC7dsiEMxwkoGP5fdUrRpT8juAHfejLdjRjdFNGCSVsqWrmrrJ5GfCBeMpKVZQ KtJA== X-Gm-Message-State: AC+VfDwiOT40YmteGBKMRXrMqImR7BYwwPvpe7tcKoAppiCmjIX+OPJv Q0Bs5XPi3m9WHWGh0LUetKpsmrLdzeDBfDr7dlU= X-Google-Smtp-Source: ACHHUZ5j3f1v/s90ClXfwrZfFWOnhsgmnt5EvtdNpyqajDhjyUktr9h8T5m4Q5Ev3MbdSgXtuyyfZA== X-Received: by 2002:a19:f201:0:b0:4f7:42de:3a8f with SMTP id q1-20020a19f201000000b004f742de3a8fmr4899376lfh.56.1687184960929; Mon, 19 Jun 2023 07:29:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/33] target/arm: Convert exception generation instructions to decodetree Date: Mon, 19 Jun 2023 15:28:51 +0100 Message-Id: <20230619142914.963184-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185193952100014 Content-Type: text/plain; charset="utf-8" Convert the exception generation instructions SVC, HVC, SMC, BRK and HLT to decodetree. The old decoder decoded the halting-debug insnns DCPS1, DCPS2 and DCPS3 just in order to then make them UNDEF; as with DRPS, we don't bother to decode them, but document the patterns in a64.decode. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-8-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 15 +++ target/arm/tcg/translate-a64.c | 173 ++++++++++++--------------------- 2 files changed, 79 insertions(+), 109 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index c49215cca8d..eeaca08ae83 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -215,3 +215,18 @@ MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm= :1 011 11111 SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D1 SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D2 SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D3 + +# Exception generation + +@i16 .... .... ... imm:16 ... .. &i +SVC 1101 0100 000 ................ 000 01 @i16 +HVC 1101 0100 000 ................ 000 10 @i16 +SMC 1101 0100 000 ................ 000 11 @i16 +BRK 1101 0100 001 ................ 000 00 @i16 +HLT 1101 0100 010 ................ 000 00 @i16 +# These insns always UNDEF unless in halting debug state, which +# we don't implement. So we don't need to decode them. The patterns +# are listed here as documentation. +# DCPS1 1101 0100 101 ................ 000 01 @i16 +# DCPS2 1101 0100 101 ................ 000 10 @i16 +# DCPS3 1101 0100 101 ................ 000 11 @i16 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 74a389da4a7..a2a71b4062f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2313,119 +2313,77 @@ static bool trans_SYS(DisasContext *s, arg_SYS *a) return true; } =20 -/* Exception generation - * - * 31 24 23 21 20 5 4 2 1 0 - * +-----------------+-----+------------------------+-----+----+ - * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL | - * +-----------------------+------------------------+----------+ - */ -static void disas_exc(DisasContext *s, uint32_t insn) +static bool trans_SVC(DisasContext *s, arg_i *a) { - int opc =3D extract32(insn, 21, 3); - int op2_ll =3D extract32(insn, 0, 5); - int imm16 =3D extract32(insn, 5, 16); - uint32_t syndrome; - - switch (opc) { - case 0: - /* For SVC, HVC and SMC we advance the single-step state - * machine before taking the exception. This is architecturally - * mandated, to ensure that single-stepping a system call - * instruction works properly. - */ - switch (op2_ll) { - case 1: /* SVC= */ - syndrome =3D syn_aa64_svc(imm16); - if (s->fgt_svc) { - gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); - break; - } - gen_ss_advance(s); - gen_exception_insn(s, 4, EXCP_SWI, syndrome); - break; - case 2: /* HVC= */ - if (s->current_el =3D=3D 0) { - unallocated_encoding(s); - break; - } - /* The pre HVC helper handles cases when HVC gets trapped - * as an undefined insn by runtime configuration. - */ - gen_a64_update_pc(s, 0); - gen_helper_pre_hvc(cpu_env); - gen_ss_advance(s); - gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(imm16), 2); - break; - case 3: /* SMC= */ - if (s->current_el =3D=3D 0) { - unallocated_encoding(s); - break; - } - gen_a64_update_pc(s, 0); - gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm1= 6))); - gen_ss_advance(s); - gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(imm16), 3); - break; - default: - unallocated_encoding(s); - break; - } - break; - case 1: - if (op2_ll !=3D 0) { - unallocated_encoding(s); - break; - } - /* BRK */ - gen_exception_bkpt_insn(s, syn_aa64_bkpt(imm16)); - break; - case 2: - if (op2_ll !=3D 0) { - unallocated_encoding(s); - break; - } - /* HLT. This has two purposes. - * Architecturally, it is an external halting debug instruction. - * Since QEMU doesn't implement external debug, we treat this as - * it is required for halting debug disabled: it will UNDEF. - * Secondly, "HLT 0xf000" is the A64 semihosting syscall instructi= on. - */ - if (semihosting_enabled(s->current_el =3D=3D 0) && imm16 =3D=3D 0x= f000) { - gen_exception_internal_insn(s, EXCP_SEMIHOST); - } else { - unallocated_encoding(s); - } - break; - case 5: - if (op2_ll < 1 || op2_ll > 3) { - unallocated_encoding(s); - break; - } - /* DCPS1, DCPS2, DCPS3 */ - unallocated_encoding(s); - break; - default: - unallocated_encoding(s); - break; + /* + * For SVC, HVC and SMC we advance the single-step state + * machine before taking the exception. This is architecturally + * mandated, to ensure that single-stepping a system call + * instruction works properly. + */ + uint32_t syndrome =3D syn_aa64_svc(a->imm); + if (s->fgt_svc) { + gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); + return true; } + gen_ss_advance(s); + gen_exception_insn(s, 4, EXCP_SWI, syndrome); + return true; } =20 -/* Branches, exception generating and system instructions */ -static void disas_b_exc_sys(DisasContext *s, uint32_t insn) +static bool trans_HVC(DisasContext *s, arg_i *a) { - switch (extract32(insn, 25, 7)) { - case 0x6a: /* Exception generation / System */ - if (insn & (1 << 24)) { - unallocated_encoding(s); - } else { - disas_exc(s, insn); - } - break; - default: + if (s->current_el =3D=3D 0) { unallocated_encoding(s); - break; + return true; } + /* + * The pre HVC helper handles cases when HVC gets trapped + * as an undefined insn by runtime configuration. + */ + gen_a64_update_pc(s, 0); + gen_helper_pre_hvc(cpu_env); + /* Architecture requires ss advance before we do the actual work */ + gen_ss_advance(s); + gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), 2); + return true; +} + +static bool trans_SMC(DisasContext *s, arg_i *a) +{ + if (s->current_el =3D=3D 0) { + unallocated_encoding(s); + return true; + } + gen_a64_update_pc(s, 0); + gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(a->imm))); + /* Architecture requires ss advance before we do the actual work */ + gen_ss_advance(s); + gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(a->imm), 3); + return true; +} + +static bool trans_BRK(DisasContext *s, arg_i *a) +{ + gen_exception_bkpt_insn(s, syn_aa64_bkpt(a->imm)); + return true; +} + +static bool trans_HLT(DisasContext *s, arg_i *a) +{ + /* + * HLT. This has two purposes. + * Architecturally, it is an external halting debug instruction. + * Since QEMU doesn't implement external debug, we treat this as + * it is required for halting debug disabled: it will UNDEF. + * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction. + */ + if (semihosting_enabled(s->current_el =3D=3D 0) && a->imm =3D=3D 0xf00= 0) { + gen_exception_internal_insn(s, EXCP_SEMIHOST); + } else { + unallocated_encoding(s); + } + return true; } =20 /* @@ -14188,9 +14146,6 @@ static bool btype_destination_ok(uint32_t insn, boo= l bt, int btype) static void disas_a64_legacy(DisasContext *s, uint32_t insn) { switch (extract32(insn, 25, 4)) { - case 0xa: case 0xb: /* Branch, exception generation and system insns */ - disas_b_exc_sys(s, insn); - break; case 0x4: case 0x6: case 0xc: --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185027; cv=none; d=zohomail.com; s=zohoarc; b=EEOJqTWhH5cZj09xqqjFPxmfgPDQoyvmfdk0EsCNVY/Fkaox/UtA23mkiI2nsju4EvMj5migqHtF3gROzQLWOP/OUFnLHrRkOKWK3C3ou+bPsfMHlHtbejXY6omDy7VPTCSHT6NpVqyzcsoBZJua5fQi7aCbIMw6rLuqrpSA5Cc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185027; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SdGx08aoksaLp21YxsKPPHNcMRVUjRR75hXQYQOrgY4=; b=RyIdNQuiLoWdKAACjpJxFgoXXO6cZs+RB0SOvhg4T7yXFlYKQCy05KL3j/6Z57n82fr4hVXNiY2V0h39apYOmgmqeTiXtBFxVSaz3hj/wGNxMMdCwkHe2nhPQBDlMtIiN+YBUltH8uhVLaW7lLZBOfdhKg+NaWHnZOFTSROui30= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687185027375433.9894155603728; Mon, 19 Jun 2023 07:30:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBFsk-0000bU-Je; Mon, 19 Jun 2023 10:29:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBFsi-0000aC-Om for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:24 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBFsg-0002CN-OM for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:24 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-3f9b1a117caso7703345e9.0 for ; Mon, 19 Jun 2023 07:29:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184961; x=1689776961; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=SdGx08aoksaLp21YxsKPPHNcMRVUjRR75hXQYQOrgY4=; b=IAJRk+C6GWSGPogaUp/RbEq6dXH07m7t1SSErcVbtYlZFb0STpYbcufmNMCdvHPE61 ZpYicsezUW6YnS9YheybYNID+oKTbwlQxQ+8Zkx1wjwu7xwyoFKjL6adtSf7XD91EAYy ikPXVvRDU2VxLEftDkWLqfwi0xNUy3C/4IEAWEe4s810zNgXekwaVp/HkM9HzXXO8vOI JV1OBzCyPjQ6uwIYtZFuvedw7dUEblXtjQ0VSDyXiej9+QGBF43q9EGo2W8LSIKBOI3s bcQKzEipNxrhqyCOS4Bb+tIaXYt7YYuezs79xzTs77okvRsYchQQ10lSJ3OeaLqFE2tS rSZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184961; x=1689776961; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SdGx08aoksaLp21YxsKPPHNcMRVUjRR75hXQYQOrgY4=; b=ZNawbRvCVSVUUjxfKhoIOe53YpB8yzS6UO6V0RMxZ3h9454q37DB1RnVmt+IK9iWPU Ccc2wVpgJW9nkLlOJCl7dd1TRZFer+CMC5YSSA8AeO20hOEpZ9j5OiNXqhle2mJYPVv7 17WlDmiSh90B+0fyuvOf5TnKe9hUuK3yuQWk1oV1302nUTdREZN8fsASuUwvCFMGagVJ OAXr0vmjNnhCY3Aov/4DRJiB9kb92TPuO3EifuITqLt36ieUBz5GtY7FoFIQY2soR9HU 3+p+8jUz5tgAhH/oIf2qxH81kmbN5SJhgKZwhR+3Omm33xbIxkk3BQJvXbFhzLFylCZD stfw== X-Gm-Message-State: AC+VfDwdLjt5vy1mzz/FHkuSlL0ZvUw2CuKRAYB/TLCxES9dN34LNhkb ktw+dqe8OdN4fmj52RzjKtzxk7B8pJzQnjEAOy4= X-Google-Smtp-Source: ACHHUZ7ihJBdRvOMN0rSa+qGhG90A4MsF6Z7o38TCjbMHZ6FPOnis0F/GG7GO2E3PYOkQUm2qkjDDw== X-Received: by 2002:a1c:7405:0:b0:3f9:b05a:90b6 with SMTP id p5-20020a1c7405000000b003f9b05a90b6mr1882331wmc.36.1687184961429; Mon, 19 Jun 2023 07:29:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/33] target/arm: Convert load/store exclusive and ordered to decodetree Date: Mon, 19 Jun 2023 15:28:52 +0100 Message-Id: <20230619142914.963184-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185028664100003 Content-Type: text/plain; charset="utf-8" Convert the instructions in the load/store exclusive (STXR, STLXR, LDXR, LDAXR) and load/store ordered (STLR, STLLR, LDAR, LDLAR) to decodetree. Note that for STLR, STLLR, LDAR, LDLAR this fixes an under-decoding in the legacy decoder where we were not checking that the RES1 bits in the Rs and Rt2 fields were set. The new function ldst_iss_sf() is equivalent to the existing disas_ldst_compute_iss_sf(), but it takes the pre-decoded 'ext' field rather than taking an undecoded two-bit opc field and extracting 'ext' from it. Once all the loads and stores have been converted to decodetree disas_ldst_compute_iss_sf() will be unused and can be deleted. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-9-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 11 +++ target/arm/tcg/translate-a64.c | 154 ++++++++++++++++++++------------- 2 files changed, 103 insertions(+), 62 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index eeaca08ae83..c5894fc06d2 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -230,3 +230,14 @@ HLT 1101 0100 010 ................ 000 00 = @i16 # DCPS1 1101 0100 101 ................ 000 01 @i16 # DCPS2 1101 0100 101 ................ 000 10 @i16 # DCPS3 1101 0100 101 ................ 000 11 @i16 + +# Loads and stores + +&stxr rn rt rt2 rs sz lasr +&stlr rn rt sz lasr +@stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr +@stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr +STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR +LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR +STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR +LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index a2a71b4062f..1ba2d6a75e4 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2652,6 +2652,95 @@ static bool disas_ldst_compute_iss_sf(int size, bool= is_signed, int opc) return regsize =3D=3D 64; } =20 +static bool ldst_iss_sf(int size, bool sign, bool ext) +{ + + if (sign) { + /* + * Signed loads are 64 bit results if we are not going to + * do a zero-extend from 32 to 64 after the load. + * (For a store, sign and ext are always false.) + */ + return !ext; + } else { + /* Unsigned loads/stores work at the specified size */ + return size =3D=3D MO_64; + } +} + +static bool trans_STXR(DisasContext *s, arg_stxr *a) +{ + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + if (a->lasr) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + gen_store_exclusive(s, a->rs, a->rt, a->rt2, a->rn, a->sz, false); + return true; +} + +static bool trans_LDXR(DisasContext *s, arg_stxr *a) +{ + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + gen_load_exclusive(s, a->rt, a->rt2, a->rn, a->sz, false); + if (a->lasr) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } + return true; +} + +static bool trans_STLR(DisasContext *s, arg_stlr *a) +{ + TCGv_i64 clean_addr; + MemOp memop; + bool iss_sf =3D ldst_iss_sf(a->sz, false, false); + + /* + * StoreLORelease is the same as Store-Release for QEMU, but + * needs the feature-test. + */ + if (!a->lasr && !dc_isar_feature(aa64_lor, s)) { + return false; + } + /* Generate ISS for non-exclusive accesses including LASR. */ + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + memop =3D check_ordered_align(s, a->rn, 0, true, a->sz); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, a->rn), + true, a->rn !=3D 31, memop); + do_gpr_st(s, cpu_reg(s, a->rt), clean_addr, memop, true, a->rt, + iss_sf, a->lasr); + return true; +} + +static bool trans_LDAR(DisasContext *s, arg_stlr *a) +{ + TCGv_i64 clean_addr; + MemOp memop; + bool iss_sf =3D ldst_iss_sf(a->sz, false, false); + + /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ + if (!a->lasr && !dc_isar_feature(aa64_lor, s)) { + return false; + } + /* Generate ISS for non-exclusive accesses including LASR. */ + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + memop =3D check_ordered_align(s, a->rn, 0, false, a->sz); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, a->rn), + false, a->rn !=3D 31, memop); + do_gpr_ld(s, cpu_reg(s, a->rt), clean_addr, memop, false, true, + a->rt, iss_sf, a->lasr); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + return true; +} + /* Load/store exclusive * * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 @@ -2674,70 +2763,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_= t insn) int is_lasr =3D extract32(insn, 15, 1); int o2_L_o1_o0 =3D extract32(insn, 21, 3) * 2 | is_lasr; int size =3D extract32(insn, 30, 2); - TCGv_i64 clean_addr; - MemOp memop; =20 switch (o2_L_o1_o0) { - case 0x0: /* STXR */ - case 0x1: /* STLXR */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - if (is_lasr) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - gen_store_exclusive(s, rs, rt, rt2, rn, size, false); - return; - - case 0x4: /* LDXR */ - case 0x5: /* LDAXR */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - gen_load_exclusive(s, rt, rt2, rn, size, false); - if (is_lasr) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } - return; - - case 0x8: /* STLLR */ - if (!dc_isar_feature(aa64_lor, s)) { - break; - } - /* StoreLORelease is the same as Store-Release for QEMU. */ - /* fall through */ - case 0x9: /* STLR */ - /* Generate ISS for non-exclusive accesses including LASR. */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - memop =3D check_ordered_align(s, rn, 0, true, size); - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - true, rn !=3D 31, memop); - do_gpr_st(s, cpu_reg(s, rt), clean_addr, memop, true, rt, - disas_ldst_compute_iss_sf(size, false, 0), is_lasr); - return; - - case 0xc: /* LDLAR */ - if (!dc_isar_feature(aa64_lor, s)) { - break; - } - /* LoadLOAcquire is the same as Load-Acquire for QEMU. */ - /* fall through */ - case 0xd: /* LDAR */ - /* Generate ISS for non-exclusive accesses including LASR. */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - memop =3D check_ordered_align(s, rn, 0, false, size); - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), - false, rn !=3D 31, memop); - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, memop, false, true, - rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - return; - case 0x2: case 0x3: /* CASP / STXP */ if (size & 2) { /* STXP / STLXP */ if (rn =3D=3D 31) { @@ -2787,6 +2814,9 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) return; } break; + default: + /* Handled in decodetree */ + break; } unallocated_encoding(s); } --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185018; cv=none; d=zohomail.com; s=zohoarc; b=epnwPD0XB3TiCzNiDiL6rWrJLleaA4/eqsVWJmIgsZqmbu/vQuTJwaZuCyMkc8COtzv4xvgexC8MekwrDf9rQ04rcqwjNSg7DAYodSIsiUBgcuEKB+gnWr4Es+mA1vidu7uT7bgPrElBg808LWInX+r829EapuW3sNeTwzBFFwU= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184962; x=1689776962; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=6KI6vCKi2hK4kMqI/ACVjSnqVa1PBuwOd1A7QPwu8LI=; b=LZqizN8MxVRIs/7oLKNo6z9x/tnIHBaf1x4J1oLjNLHIb5hYH4l8OKZQZttgxbH+O+ ucEkJ8b1bxEByWxLj3YuIAjvI1hcycl5NmSwrNw9d3zYxl2/RyhK8r/RMBkownA0S1jc jW159SHKsv6T4uL3C1UcuvjolITsh5eaFTOS0GdPuv6JekO+atLT+7fqaZOGOj2QdY9d DGsMrnKLs4wWL2C8mVgbHLf8T5xkh1qFMkgN/3ms7h+/+O0vxi6zL4XIiJsOxHVNloRc /Vx959zAbA56H+qeSCcZsrwuIcs9MNbIgi3KmDMtaJh6rjZJKiZ4BGHrXU5Lhdr6ovQ/ DMUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184962; x=1689776962; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6KI6vCKi2hK4kMqI/ACVjSnqVa1PBuwOd1A7QPwu8LI=; b=dksOEQfll7u611MexoF9jbVgL2QInm/6XUwi/mS8p2KPom0tUDttku5bwRkWZwCjYr 87g+7zzqQUI926jrb5ZQGnN869u6M9qY9fm3Y+pk8ccNIQ9QvANtRrng9Shab06p0wnn IXc/g3YWK5EJpzhb1fUEVkA6WT1gy5BF2OMkkzy44DjfzPlsgN9EgfnpgJz73zDpZnvc IeriUEzXiez+Gs7uPFux5YLRaf6CZbUmEXEUu0xkgcM0+UIzONclR3yo7FNwSBm6eMUr Azm2fKzQtrwN04rRLXP3hWuT/f2B40UWcThydgM4DJEkSrK5wWqZj+B38Ke56uhSHxbK eFZg== X-Gm-Message-State: AC+VfDzC1iLMeQqdaipxhXL5uwBqenLbFKp0M+29VVLAkOcE+Z6LB+3l C2VWlTY4KHpQYjd7/Jtfj+6TNg9/TEKuNwTUQLc= X-Google-Smtp-Source: ACHHUZ43bHP+gzBvWjJjbWzq8A34vhVEN33CMlPTiFPQpUpwlychPcOUAVwvEv8cwQDL14+dhrRz8Q== X-Received: by 2002:a7b:ce14:0:b0:3f9:7a15:1716 with SMTP id m20-20020a7bce14000000b003f97a151716mr3627068wmc.5.1687184961821; Mon, 19 Jun 2023 07:29:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/33] target/arm: Convert LDXP, STXP, CASP, CAS to decodetree Date: Mon, 19 Jun 2023 15:28:53 +0100 Message-Id: <20230619142914.963184-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185020130100003 Content-Type: text/plain; charset="utf-8" Convert the load/store exclusive pair (LDXP, STXP, LDAXP, STLXP), compare-and-swap pair (CASP, CASPA, CASPAL, CASPL), and compare-and swap (CAS, CASA, CASAL, CASL) instructions to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-10-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 11 +++ target/arm/tcg/translate-a64.c | 121 ++++++++++++--------------------- 2 files changed, 53 insertions(+), 79 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index c5894fc06d2..6b1079b8bdf 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -237,7 +237,18 @@ HLT 1101 0100 010 ................ 000 00 = @i16 &stlr rn rt sz lasr @stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr @stlr sz:2 ...... ... ..... lasr:1 ..... rn:5 rt:5 &stlr +%imm1_30_p2 30:1 !function=3Dplus_2 +@stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=3D%imm1= _30_p2 STXR .. 001000 000 ..... . ..... ..... ..... @stxr # inc STLXR LDXR .. 001000 010 ..... . ..... ..... ..... @stxr # inc LDAXR STLR .. 001000 100 11111 . 11111 ..... ..... @stlr # inc STLLR LDAR .. 001000 110 11111 . 11111 ..... ..... @stlr # inc LDLAR + +STXP 1 . 001000 001 ..... . ..... ..... ..... @stxp # inc STLXP +LDXP 1 . 001000 011 ..... . ..... ..... ..... @stxp # inc LDAXP + +# CASP, CASPA, CASPAL, CASPL (we don't decode the bits that determine +# acquire/release semantics because QEMU's cmpxchg always has those) +CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=3D%imm1_30_p2 +# CAS, CASA, CASAL, CASL +CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1ba2d6a75e4..ff4338ee4df 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2741,84 +2741,50 @@ static bool trans_LDAR(DisasContext *s, arg_stlr *a) return true; } =20 -/* Load/store exclusive - * - * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 - * +-----+-------------+----+---+----+------+----+-------+------+------+ - * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt | - * +-----+-------------+----+---+----+------+----+-------+------+------+ - * - * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit - * L: 0 -> store, 1 -> load - * o2: 0 -> exclusive, 1 -> not - * o1: 0 -> single register, 1 -> register pair - * o0: 1 -> load-acquire/store-release, 0 -> not - */ -static void disas_ldst_excl(DisasContext *s, uint32_t insn) +static bool trans_STXP(DisasContext *s, arg_stxr *a) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int rt2 =3D extract32(insn, 10, 5); - int rs =3D extract32(insn, 16, 5); - int is_lasr =3D extract32(insn, 15, 1); - int o2_L_o1_o0 =3D extract32(insn, 21, 3) * 2 | is_lasr; - int size =3D extract32(insn, 30, 2); - - switch (o2_L_o1_o0) { - case 0x2: case 0x3: /* CASP / STXP */ - if (size & 2) { /* STXP / STLXP */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - if (is_lasr) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - gen_store_exclusive(s, rs, rt, rt2, rn, size, true); - return; - } - if (rt2 =3D=3D 31 - && ((rt | rs) & 1) =3D=3D 0 - && dc_isar_feature(aa64_atomics, s)) { - /* CASP / CASPL */ - gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); - return; - } - break; - - case 0x6: case 0x7: /* CASPA / LDXP */ - if (size & 2) { /* LDXP / LDAXP */ - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - gen_load_exclusive(s, rt, rt2, rn, size, true); - if (is_lasr) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } - return; - } - if (rt2 =3D=3D 31 - && ((rt | rs) & 1) =3D=3D 0 - && dc_isar_feature(aa64_atomics, s)) { - /* CASPA / CASPAL */ - gen_compare_and_swap_pair(s, rs, rt, rn, size | 2); - return; - } - break; - - case 0xa: /* CAS */ - case 0xb: /* CASL */ - case 0xe: /* CASA */ - case 0xf: /* CASAL */ - if (rt2 =3D=3D 31 && dc_isar_feature(aa64_atomics, s)) { - gen_compare_and_swap(s, rs, rt, rn, size); - return; - } - break; - default: - /* Handled in decodetree */ - break; + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); } - unallocated_encoding(s); + if (a->lasr) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + gen_store_exclusive(s, a->rs, a->rt, a->rt2, a->rn, a->sz, true); + return true; +} + +static bool trans_LDXP(DisasContext *s, arg_stxr *a) +{ + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + gen_load_exclusive(s, a->rt, a->rt2, a->rn, a->sz, true); + if (a->lasr) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } + return true; +} + +static bool trans_CASP(DisasContext *s, arg_CASP *a) +{ + if (!dc_isar_feature(aa64_atomics, s)) { + return false; + } + if (((a->rt | a->rs) & 1) !=3D 0) { + return false; + } + + gen_compare_and_swap_pair(s, a->rs, a->rt, a->rn, a->sz); + return true; +} + +static bool trans_CAS(DisasContext *s, arg_CAS *a) +{ + if (!dc_isar_feature(aa64_atomics, s)) { + return false; + } + gen_compare_and_swap(s, a->rs, a->rt, a->rn, a->sz); + return true; } =20 /* @@ -4247,9 +4213,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t = insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x08: /* Load/store exclusive */ - disas_ldst_excl(s, insn); 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184962; x=1689776962; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Zon/L+1E7pApwo5q3JdDpEUBgb4onUwkVEYPmbfuPTc=; b=g1I211GDebIA8HWP8V2OMIsLHexHYH7rK8JBCxNecvoYezhZSZUU6UZWPFm7DbdT52 DYAIvSG+OKplGf1oGpegxXB41qggdX07Rx+Q3PWOXsFS9YfHraSpwZcW6UgfGl4zSAAb uj0jBEko4u5ru3OwETMmTRgLY+T6NNObyB4qKuRlPosh8LphRUrMISEmU+80Oocsb972 6PnS9o06xEJLq9nuzkh7xpVQ7BVbRm0ZdhUwISWA0QW6GQJbvuJB87c3rfXaW8MDLWLt K4IXHToV3fMYC8t+O1fAwf/G+EsucZkc6lRm/AJUwmBXo+JpKMrUEjaDMUTKXyiwu6Nv jM2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184962; x=1689776962; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zon/L+1E7pApwo5q3JdDpEUBgb4onUwkVEYPmbfuPTc=; b=FfJ5xOLjoAhpm6FNdY7USEna9he84x5EfSuNoouJ+RRjw74Bl7UIZADFoKAbuDYKaH swvEWHDnkpEXwzQHQaDeJIhg1M6wW+Qp+3goM3xCf2ntw9HvqSr+MlOl75bEzZE77zkN iaICmhxFw4syA6T1+MdXSqRhe0RVYaQHJ5WjG//+btKfm9HRG9uS8uTPbafvZumKXTAP dcv5BGZ/qfsFONlOcloTvvDVrqfwB2W3/sAkyqwZ92hcXL2L3E9FKAXF9OvOwoWhHZNs glEK6ZUoZawNLNxgPdEShDuVl9hjSTm89n1pZchqv60KbjKY1W4JORQ4VgYK1LVw9suz 3aeA== X-Gm-Message-State: AC+VfDzByVm/3pJlZbZ7vaKp/nHh7xOX2mr4/1Y8Q/uj2k1btTL/An+2 vg7vZsSoQjk/Ms18b1edcweVb3DpycoUElrqNTw= X-Google-Smtp-Source: ACHHUZ7tS8xvLiJvWsXyREjmayst4X4sGNhPdXYKR/eEIMce/AYNohwyzji6Waz8c5LqeEfZae6iLA== X-Received: by 2002:adf:f304:0:b0:306:3e96:6c5f with SMTP id i4-20020adff304000000b003063e966c5fmr6368734wro.15.1687184962350; Mon, 19 Jun 2023 07:29:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/33] target/arm: Convert load reg (literal) group to decodetree Date: Mon, 19 Jun 2023 15:28:54 +0100 Message-Id: <20230619142914.963184-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185312432100003 Content-Type: text/plain; charset="utf-8" Convert the "Load register (literal)" instruction class to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-11-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 13 ++++++ target/arm/tcg/translate-a64.c | 76 ++++++++++------------------------ 2 files changed, 35 insertions(+), 54 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 6b1079b8bdf..c2c6ac0196d 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -252,3 +252,16 @@ LDXP 1 . 001000 011 ..... . ..... ..... ...= .. @stxp # inc LDAXP CASP 0 . 001000 0 - 1 rs:5 - 11111 rn:5 rt:5 sz=3D%imm1_30_p2 # CAS, CASA, CASAL, CASL CAS sz:2 001000 1 - 1 rs:5 - 11111 rn:5 rt:5 + +&ldlit rt imm sz sign +@ldlit .. ... . .. ................... rt:5 &ldlit imm=3D%imm19 + +LD_lit 00 011 0 00 ................... ..... @ldlit sz=3D2 sign= =3D0 +LD_lit 01 011 0 00 ................... ..... @ldlit sz=3D3 sign= =3D0 +LD_lit 10 011 0 00 ................... ..... @ldlit sz=3D2 sign= =3D1 +LD_lit_v 00 011 1 00 ................... ..... @ldlit sz=3D2 sign= =3D0 +LD_lit_v 01 011 1 00 ................... ..... @ldlit sz=3D3 sign= =3D0 +LD_lit_v 10 011 1 00 ................... ..... @ldlit sz=3D4 sign= =3D0 + +# PRFM +NOP 11 011 0 00 ------------------- ----- diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ff4338ee4df..d1df41f2e5e 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2787,62 +2787,33 @@ static bool trans_CAS(DisasContext *s, arg_CAS *a) return true; } =20 -/* - * Load register (literal) - * - * 31 30 29 27 26 25 24 23 5 4 0 - * +-----+-------+---+-----+-------------------+-------+ - * | opc | 0 1 1 | V | 0 0 | imm19 | Rt | - * +-----+-------+---+-----+-------------------+-------+ - * - * V: 1 -> vector (simd/fp) - * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit, - * 10-> 32 bit signed, 11 -> prefetch - * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated) - */ -static void disas_ld_lit(DisasContext *s, uint32_t insn) +static bool trans_LD_lit(DisasContext *s, arg_ldlit *a) { - int rt =3D extract32(insn, 0, 5); - int64_t imm =3D sextract32(insn, 5, 19) << 2; - bool is_vector =3D extract32(insn, 26, 1); - int opc =3D extract32(insn, 30, 2); - bool is_signed =3D false; - int size =3D 2; - TCGv_i64 tcg_rt, clean_addr; + bool iss_sf =3D ldst_iss_sf(a->sz, a->sign, false); + TCGv_i64 tcg_rt =3D cpu_reg(s, a->rt); + TCGv_i64 clean_addr =3D tcg_temp_new_i64(); + MemOp memop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); + + gen_pc_plus_diff(s, clean_addr, a->imm); + do_gpr_ld(s, tcg_rt, clean_addr, memop, + false, true, a->rt, iss_sf, false); + return true; +} + +static bool trans_LD_lit_v(DisasContext *s, arg_ldlit *a) +{ + /* Load register (literal), vector version */ + TCGv_i64 clean_addr; MemOp memop; =20 - if (is_vector) { - if (opc =3D=3D 3) { - unallocated_encoding(s); - return; - } - size =3D 2 + opc; - if (!fp_access_check(s)) { - return; - } - memop =3D finalize_memop_asimd(s, size); - } else { - if (opc =3D=3D 3) { - /* PRFM (literal) : prefetch */ - return; - } - size =3D 2 + extract32(opc, 0, 1); - is_signed =3D extract32(opc, 1, 1); - memop =3D finalize_memop(s, size + is_signed * MO_SIGN); + if (!fp_access_check(s)) { + return true; } - - tcg_rt =3D cpu_reg(s, rt); - + memop =3D finalize_memop_asimd(s, a->sz); clean_addr =3D tcg_temp_new_i64(); - gen_pc_plus_diff(s, clean_addr, imm); - - if (is_vector) { - do_fp_ld(s, rt, clean_addr, memop); - } else { - /* Only unsigned 32bit loads target 32bit registers. */ - bool iss_sf =3D opc !=3D 0; - do_gpr_ld(s, tcg_rt, clean_addr, memop, false, true, rt, iss_sf, f= alse); - } + gen_pc_plus_diff(s, clean_addr, a->imm); + do_fp_ld(s, a->rt, clean_addr, memop); + return true; } =20 /* @@ -4213,9 +4184,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t = insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x18: case 0x1c: /* Load register (literal) */ - disas_ld_lit(s, insn); - break; case 0x28: case 0x29: case 0x2c: case 0x2d: /* Load/store pair (all forms) */ disas_ldst_pair(s, insn); --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185215; cv=none; d=zohomail.com; s=zohoarc; b=mNoBQM/B9/NK70dUY2uhx76jG6yHlnONgBsjyecC/gXtU5vjrjVa6uj68GAVhkQBado0/vsjpKWrLADFyVPoV4H33zCyanj+YlJYQ4yyXOrrl2XtJVKtckb/ZZVPPMNuNNnGA7SlJstJ4NC6lJuWl4NgdsCNuHRKWoKTBZzfmeA= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184963; x=1689776963; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=zdWrcxAFWPcu8gfjJ8ZBg/XxlBs06EXCzgp0imYkLDs=; b=DW8gACuvqerhpco2+Jpb2vAim8cVMTJZF8WC31Gebkk6hNoNEBTvcGev93VBHDQ63M lEuvwkBsyuLA+9VueAfUtcROEv1DAgOf/JrSYPkWqAgS0UiaXdo1zvUW8lxgpDt4a7zD OHo4aawKjz74f+Jr+WGovtCQXdt6qJ0aMpvn90/g70gWXLXjpET9AuOee7wPj7oU35lL uECZXSQhJm7iciv1wvI2t7ygOK4ezwxmk0AOUVSaIZ797LYdQNCX/44CT4bQrXOSoIrL 8V5yhE1r2YVZmiTHLHE81rovZthoI1AzoAfY7FY+qfpMQTzlLEPctNfXElqotEGFrDME 38oA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184963; x=1689776963; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zdWrcxAFWPcu8gfjJ8ZBg/XxlBs06EXCzgp0imYkLDs=; b=Rd8tskSMqGVAN6AxskSh9B3OmbnHTQT0hyAOWymny+RrIQdJ92AHuUgtN5L0m3fdDl 1eFW0srk46rUj/1KRRnAKJYz0fdbZqpbUXO09/YKUFd49fRSm4iikKzvv4niGI1SFSaH IN4VXFTMA4itJhh3lPAnfAjseo4rk1AzCfysKrp6iD14Bz56XW80kDDY7d2snkeMpSBh V/gsr3+8fRZGUykO4Ys24Q4wHyEyxgYrgPTRw7YC88Bxo4QAjDKjds9q8HHSMNsBZkjv zWQwzbWVko4GYG+71YU8mwSGRRQqYZ6+4yEMK+Od5dnUGwz7wmgyCE5HuVxicR9hZb3V 7SXA== X-Gm-Message-State: AC+VfDxR7dFFtKM1G/l15BF/ucPksiCZYYaM3Ex7bdqE2Fa+sEa4vUhl fDS9Ab9s8FimuUKoYzXg8tgKR82rKXhvpax83rw= X-Google-Smtp-Source: ACHHUZ5oaIoH49MqoZOHSJPdluXmtcQ6A6BYWQyRJVldZvhpAoXL2YPSH34rK8tLO+5Ejy0DccYxzA== X-Received: by 2002:a1c:f70f:0:b0:3f7:2a1d:1b05 with SMTP id v15-20020a1cf70f000000b003f72a1d1b05mr10605041wmh.14.1687184962742; Mon, 19 Jun 2023 07:29:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/33] target/arm: Convert load/store-pair to decodetree Date: Mon, 19 Jun 2023 15:28:55 +0100 Message-Id: <20230619142914.963184-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185216130100001 Content-Type: text/plain; charset="utf-8" Convert the load/store register pair insns (LDP, STP, LDNP, STNP, LDPSW, STGP) to decodetree. Signed-off-by: Peter Maydell Message-id: 20230602155223.2040685-12-peter.maydell@linaro.org Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 61 +++++ target/arm/tcg/translate-a64.c | 422 ++++++++++++++++----------------- 2 files changed, 268 insertions(+), 215 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index c2c6ac0196d..f5787919931 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -265,3 +265,64 @@ LD_lit_v 10 011 1 00 ................... ..... = @ldlit sz=3D4 sign=3D0 =20 # PRFM NOP 11 011 0 00 ------------------- ----- + +&ldstpair rt2 rt rn imm sz sign w p +@ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair + +# STNP, LDNP: Signed offset, non-temporal hint. We don't emulate caches +# so we ignore hints about data access patterns, and handle these like +# plain signed offset. +STP 00 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +LDP 00 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +STP 10 101 0 000 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +LDP 10 101 0 000 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +STP_v 00 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +LDP_v 00 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +STP_v 01 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +LDP_v 01 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +STP_v 10 101 1 000 0 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D0 +LDP_v 10 101 1 000 1 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D0 + +# STP and LDP: post-indexed +STP 00 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D1 w=3D1 +LDP 00 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D1 w=3D1 +LDP 01 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D1 p=3D1 w=3D1 +STP 10 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 +LDP 10 101 0 001 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 +STP_v 00 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D1 w=3D1 +LDP_v 00 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D1 w=3D1 +STP_v 01 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 +LDP_v 01 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 +STP_v 10 101 1 001 0 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D1 w=3D1 +LDP_v 10 101 1 001 1 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D1 w=3D1 + +# STP and LDP: offset +STP 00 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +LDP 00 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +LDP 01 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D1 p=3D0 w=3D0 +STP 10 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +LDP 10 101 0 010 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +STP_v 00 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +LDP_v 00 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D0 +STP_v 01 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +LDP_v 01 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +STP_v 10 101 1 010 0 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D0 +LDP_v 10 101 1 010 1 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D0 + +# STP and LDP: pre-indexed +STP 00 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D1 +LDP 00 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D1 +LDP 01 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D1 p=3D0 w=3D1 +STP 10 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 +LDP 10 101 0 011 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 +STP_v 00 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D1 +LDP_v 00 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3D2 = sign=3D0 p=3D0 w=3D1 +STP_v 01 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 +LDP_v 01 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 +STP_v 10 101 1 011 0 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D1 +LDP_v 10 101 1 011 1 ....... ..... ..... ..... @ldstpair sz=3D4 = sign=3D0 p=3D0 w=3D1 + +# STGP: store tag and pair +STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 +STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 +STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index d1df41f2e5e..103e54d0c49 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2816,229 +2816,225 @@ static bool trans_LD_lit_v(DisasContext *s, arg_l= dlit *a) return true; } =20 -/* - * LDNP (Load Pair - non-temporal hint) - * LDP (Load Pair - non vector) - * LDPSW (Load Pair Signed Word - non vector) - * STNP (Store Pair - non-temporal hint) - * STP (Store Pair - non vector) - * LDNP (Load Pair of SIMD&FP - non-temporal hint) - * LDP (Load Pair of SIMD&FP) - * STNP (Store Pair of SIMD&FP - non-temporal hint) - * STP (Store Pair of SIMD&FP) - * - * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0 - * +-----+-------+---+---+-------+---+-----------------------------+ - * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt | - * +-----+-------+---+---+-------+---+-------+-------+------+------+ - * - * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit - * LDPSW/STGP 01 - * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit - * V: 0 -> GPR, 1 -> Vector - * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, - * 10 -> signed offset, 11 -> pre-index - * L: 0 -> Store 1 -> Load - * - * Rt, Rt2 =3D GPR or SIMD registers to be stored - * Rn =3D general purpose register containing address - * imm7 =3D signed offset (multiple of 4 or 8 depending on size) - */ -static void disas_ldst_pair(DisasContext *s, uint32_t insn) +static void op_addr_ldstpair_pre(DisasContext *s, arg_ldstpair *a, + TCGv_i64 *clean_addr, TCGv_i64 *dirty_add= r, + uint64_t offset, bool is_store, MemOp mop) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int rt2 =3D extract32(insn, 10, 5); - uint64_t offset =3D sextract64(insn, 15, 7); - int index =3D extract32(insn, 23, 2); - bool is_vector =3D extract32(insn, 26, 1); - bool is_load =3D extract32(insn, 22, 1); - int opc =3D extract32(insn, 30, 2); - bool is_signed =3D false; - bool postindex =3D false; - bool wback =3D false; - bool set_tag =3D false; - TCGv_i64 clean_addr, dirty_addr; - MemOp mop; - int size; - - if (opc =3D=3D 3) { - unallocated_encoding(s); - return; - } - - if (is_vector) { - size =3D 2 + opc; - } else if (opc =3D=3D 1 && !is_load) { - /* STGP */ - if (!dc_isar_feature(aa64_mte_insn_reg, s) || index =3D=3D 0) { - unallocated_encoding(s); - return; - } - size =3D 3; - set_tag =3D true; - } else { - size =3D 2 + extract32(opc, 1, 1); - is_signed =3D extract32(opc, 0, 1); - if (!is_load && is_signed) { - unallocated_encoding(s); - return; - } - } - - switch (index) { - case 1: /* post-index */ - postindex =3D true; - wback =3D true; - break; - case 0: - /* signed offset with "non-temporal" hint. Since we don't emulate - * caches we don't care about hints to the cache system about - * data access patterns, and handle this identically to plain - * signed offset. - */ - if (is_signed) { - /* There is no non-temporal-hint version of LDPSW */ - unallocated_encoding(s); - return; - } - postindex =3D false; - break; - case 2: /* signed offset, rn not updated */ - postindex =3D false; - break; - case 3: /* pre-index */ - postindex =3D false; - wback =3D true; - break; - } - - if (is_vector && !fp_access_check(s)) { - return; - } - - offset <<=3D (set_tag ? LOG2_TAG_GRANULE : size); - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); - if (!postindex) { + *dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); + if (!a->p) { + tcg_gen_addi_i64(*dirty_addr, *dirty_addr, offset); + } + + *clean_addr =3D gen_mte_checkN(s, *dirty_addr, is_store, + (a->w || a->rn !=3D 31), 2 << a->sz, mop); +} + +static void op_addr_ldstpair_post(DisasContext *s, arg_ldstpair *a, + TCGv_i64 dirty_addr, uint64_t offset) +{ + if (a->w) { + if (a->p) { + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + } + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr); + } +} + +static bool trans_STP(DisasContext *s, arg_ldstpair *a) +{ + uint64_t offset =3D a->imm << a->sz; + TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2; + MemOp mop =3D finalize_memop(s, a->sz); + + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, true, mop= ); + tcg_rt =3D cpu_reg(s, a->rt); + tcg_rt2 =3D cpu_reg(s, a->rt2); + /* + * We built mop above for the single logical access -- rebuild it + * now for the paired operation. + * + * With LSE2, non-sign-extending pairs are treated atomically if + * aligned, and if unaligned one of the pair will be completely + * within a 16-byte block and that element will be atomic. + * Otherwise each element is separately atomic. + * In all cases, issue one operation with the correct atomicity. + */ + mop =3D a->sz + 1; + if (s->align_mem) { + mop |=3D (a->sz =3D=3D 2 ? MO_ALIGN_4 : MO_ALIGN_8); + } + mop =3D finalize_memop_pair(s, mop); + if (a->sz =3D=3D 2) { + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat32_i64(tmp, tcg_rt, tcg_rt2); + } else { + tcg_gen_concat32_i64(tmp, tcg_rt2, tcg_rt); + } + tcg_gen_qemu_st_i64(tmp, clean_addr, get_mem_index(s), mop); + } else { + TCGv_i128 tmp =3D tcg_temp_new_i128(); + + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat_i64_i128(tmp, tcg_rt, tcg_rt2); + } else { + tcg_gen_concat_i64_i128(tmp, tcg_rt2, tcg_rt); + } + tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mop); + } + op_addr_ldstpair_post(s, a, dirty_addr, offset); + return true; +} + +static bool trans_LDP(DisasContext *s, arg_ldstpair *a) +{ + uint64_t offset =3D a->imm << a->sz; + TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2; + MemOp mop =3D finalize_memop(s, a->sz); + + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, false, mo= p); + tcg_rt =3D cpu_reg(s, a->rt); + tcg_rt2 =3D cpu_reg(s, a->rt2); + + /* + * We built mop above for the single logical access -- rebuild it + * now for the paired operation. + * + * With LSE2, non-sign-extending pairs are treated atomically if + * aligned, and if unaligned one of the pair will be completely + * within a 16-byte block and that element will be atomic. + * Otherwise each element is separately atomic. + * In all cases, issue one operation with the correct atomicity. + * + * This treats sign-extending loads like zero-extending loads, + * since that reuses the most code below. + */ + mop =3D a->sz + 1; + if (s->align_mem) { + mop |=3D (a->sz =3D=3D 2 ? MO_ALIGN_4 : MO_ALIGN_8); + } + mop =3D finalize_memop_pair(s, mop); + if (a->sz =3D=3D 2) { + int o2 =3D s->be_data =3D=3D MO_LE ? 32 : 0; + int o1 =3D o2 ^ 32; + + tcg_gen_qemu_ld_i64(tcg_rt, clean_addr, get_mem_index(s), mop); + if (a->sign) { + tcg_gen_sextract_i64(tcg_rt2, tcg_rt, o2, 32); + tcg_gen_sextract_i64(tcg_rt, tcg_rt, o1, 32); + } else { + tcg_gen_extract_i64(tcg_rt2, tcg_rt, o2, 32); + tcg_gen_extract_i64(tcg_rt, tcg_rt, o1, 32); + } + } else { + TCGv_i128 tmp =3D tcg_temp_new_i128(); + + tcg_gen_qemu_ld_i128(tmp, clean_addr, get_mem_index(s), mop); + if (s->be_data =3D=3D MO_LE) { + tcg_gen_extr_i128_i64(tcg_rt, tcg_rt2, tmp); + } else { + tcg_gen_extr_i128_i64(tcg_rt2, tcg_rt, tmp); + } + } + op_addr_ldstpair_post(s, a, dirty_addr, offset); + return true; +} + +static bool trans_STP_v(DisasContext *s, arg_ldstpair *a) +{ + uint64_t offset =3D a->imm << a->sz; + TCGv_i64 clean_addr, dirty_addr; + MemOp mop; + + if (!fp_access_check(s)) { + return true; + } + + /* LSE2 does not merge FP pairs; leave these as separate operations. */ + mop =3D finalize_memop_asimd(s, a->sz); + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, true, mop= ); + do_fp_st(s, a->rt, clean_addr, mop); + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << a->sz); + do_fp_st(s, a->rt2, clean_addr, mop); + op_addr_ldstpair_post(s, a, dirty_addr, offset); + return true; +} + +static bool trans_LDP_v(DisasContext *s, arg_ldstpair *a) +{ + uint64_t offset =3D a->imm << a->sz; + TCGv_i64 clean_addr, dirty_addr; + MemOp mop; + + if (!fp_access_check(s)) { + return true; + } + + /* LSE2 does not merge FP pairs; leave these as separate operations. */ + mop =3D finalize_memop_asimd(s, a->sz); + op_addr_ldstpair_pre(s, a, &clean_addr, &dirty_addr, offset, false, mo= p); + do_fp_ld(s, a->rt, clean_addr, mop); + tcg_gen_addi_i64(clean_addr, clean_addr, 1 << a->sz); + do_fp_ld(s, a->rt2, clean_addr, mop); + op_addr_ldstpair_post(s, a, dirty_addr, offset); + return true; +} + +static bool trans_STGP(DisasContext *s, arg_ldstpair *a) +{ + TCGv_i64 clean_addr, dirty_addr, tcg_rt, tcg_rt2; + uint64_t offset =3D a->imm << LOG2_TAG_GRANULE; + MemOp mop; + TCGv_i128 tmp; + + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { + return false; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); + if (!a->p) { tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } =20 - if (set_tag) { - if (!s->ata) { - /* - * TODO: We could rely on the stores below, at least for - * system mode, if we arrange to add MO_ALIGN_16. - */ - gen_helper_stg_stub(cpu_env, dirty_addr); - } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr); - } else { - gen_helper_stg(cpu_env, dirty_addr, dirty_addr); - } - } - - if (is_vector) { - mop =3D finalize_memop_asimd(s, size); - } else { - mop =3D finalize_memop(s, size); - } - clean_addr =3D gen_mte_checkN(s, dirty_addr, !is_load, - (wback || rn !=3D 31) && !set_tag, - 2 << size, mop); - - if (is_vector) { - /* LSE2 does not merge FP pairs; leave these as separate operation= s. */ - if (is_load) { - do_fp_ld(s, rt, clean_addr, mop); - } else { - do_fp_st(s, rt, clean_addr, mop); - } - tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size); - if (is_load) { - do_fp_ld(s, rt2, clean_addr, mop); - } else { - do_fp_st(s, rt2, clean_addr, mop); - } - } else { - TCGv_i64 tcg_rt =3D cpu_reg(s, rt); - TCGv_i64 tcg_rt2 =3D cpu_reg(s, rt2); - + if (!s->ata) { /* - * We built mop above for the single logical access -- rebuild it - * now for the paired operation. - * - * With LSE2, non-sign-extending pairs are treated atomically if - * aligned, and if unaligned one of the pair will be completely - * within a 16-byte block and that element will be atomic. - * Otherwise each element is separately atomic. - * In all cases, issue one operation with the correct atomicity. - * - * This treats sign-extending loads like zero-extending loads, - * since that reuses the most code below. + * TODO: We could rely on the stores below, at least for + * system mode, if we arrange to add MO_ALIGN_16. */ - mop =3D size + 1; - if (s->align_mem) { - mop |=3D (size =3D=3D 2 ? MO_ALIGN_4 : MO_ALIGN_8); - } - mop =3D finalize_memop_pair(s, mop); - - if (is_load) { - if (size =3D=3D 2) { - int o2 =3D s->be_data =3D=3D MO_LE ? 32 : 0; - int o1 =3D o2 ^ 32; - - tcg_gen_qemu_ld_i64(tcg_rt, clean_addr, get_mem_index(s), = mop); - if (is_signed) { - tcg_gen_sextract_i64(tcg_rt2, tcg_rt, o2, 32); - tcg_gen_sextract_i64(tcg_rt, tcg_rt, o1, 32); - } else { - tcg_gen_extract_i64(tcg_rt2, tcg_rt, o2, 32); - tcg_gen_extract_i64(tcg_rt, tcg_rt, o1, 32); - } - } else { - TCGv_i128 tmp =3D tcg_temp_new_i128(); - - tcg_gen_qemu_ld_i128(tmp, clean_addr, get_mem_index(s), mo= p); - if (s->be_data =3D=3D MO_LE) { - tcg_gen_extr_i128_i64(tcg_rt, tcg_rt2, tmp); - } else { - tcg_gen_extr_i128_i64(tcg_rt2, tcg_rt, tmp); - } - } - } else { - if (size =3D=3D 2) { - TCGv_i64 tmp =3D tcg_temp_new_i64(); - - if (s->be_data =3D=3D MO_LE) { - tcg_gen_concat32_i64(tmp, tcg_rt, tcg_rt2); - } else { - tcg_gen_concat32_i64(tmp, tcg_rt2, tcg_rt); - } - tcg_gen_qemu_st_i64(tmp, clean_addr, get_mem_index(s), mop= ); - } else { - TCGv_i128 tmp =3D tcg_temp_new_i128(); - - if (s->be_data =3D=3D MO_LE) { - tcg_gen_concat_i64_i128(tmp, tcg_rt, tcg_rt2); - } else { - tcg_gen_concat_i64_i128(tmp, tcg_rt2, tcg_rt); - } - tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mo= p); - } - } + gen_helper_stg_stub(cpu_env, dirty_addr); + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { + gen_helper_stg_parallel(cpu_env, dirty_addr, dirty_addr); + } else { + gen_helper_stg(cpu_env, dirty_addr, dirty_addr); } =20 - if (wback) { - if (postindex) { - tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); - } - tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); + mop =3D finalize_memop(s, a->sz); + clean_addr =3D gen_mte_checkN(s, dirty_addr, true, false, 2 << a->sz, = mop); + + tcg_rt =3D cpu_reg(s, a->rt); + tcg_rt2 =3D cpu_reg(s, a->rt2); + + assert(a->sz =3D=3D 3); + + tmp =3D tcg_temp_new_i128(); + if (s->be_data =3D=3D MO_LE) { + tcg_gen_concat_i64_i128(tmp, tcg_rt, tcg_rt2); + } else { + tcg_gen_concat_i64_i128(tmp, tcg_rt2, tcg_rt); } + tcg_gen_qemu_st_i128(tmp, clean_addr, get_mem_index(s), mop); + + op_addr_ldstpair_post(s, a, dirty_addr, offset); + return true; } =20 /* @@ -4184,10 +4180,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t= insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x28: case 0x29: - case 0x2c: case 0x2d: /* Load/store pair (all forms) */ - disas_ldst_pair(s, insn); - break; case 0x38: case 0x39: case 0x3c: case 0x3d: /* Load/store register (all forms) */ disas_ldst_reg(s, insn); --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185089; cv=none; d=zohomail.com; s=zohoarc; b=MRLw5AgoC5st3XkzfHa4hJEfcy3/hgp7L2WIcPHmKA9YCaDqhVP6BGMLQK0igK3q2OMJq3gFm4RpxVvg2WQopg42drWzRh/bMKkrsKZAn7BJlQi1rr/4meBRd+BCQgtmyF2JWMEHFLKNCB2YzJkaG9a1DuXBXzfJqT0ZVRug8rI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185089; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OBnS252vauoaeLoGy2Pd1180Qv2s4Y9APpSeQJOp5Ss=; b=MAJaICzvi/vkpcneLpHfIOm0DaDOTKrk7czQQUyduay8teDhsFaV/j9KC+JL8yA6QnxIublqJPAQ+Obp4jvF1JpEzhjdmZAyYMFmk1MxG/FN5BroeoYsUJTL+CnTzO+nJopB+J+oO7a5mm9wgMGoDLrGoFpiSc+pVdsIaxU8P5E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 168718508918698.29969238197714; Mon, 19 Jun 2023 07:31:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBFtQ-0001Rc-Ur; Mon, 19 Jun 2023 10:30:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBFsl-0000bs-84 for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:27 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBFsi-0002DL-Kn for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:26 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-3f9189228bcso11681045e9.3 for ; Mon, 19 Jun 2023 07:29:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184963; x=1689776963; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=OBnS252vauoaeLoGy2Pd1180Qv2s4Y9APpSeQJOp5Ss=; b=djTPCGVVL9+oUy5e2UYNBOYJTTyY93JAuVRAD7y6e1yGu2dvGEzdHVXYarbk90byqc o91WNpOf041OSE8qnawccwYUTo+U303LeJbepy7xGszgrRbt9YuyYS5F0S6ce3jN9lgE 61kJDqEO/hmaMzjtuNOnastsWWSmKf01/ZBAD71ST5wPA7OeeXMFZ4t1GGVrKYRTyv8f 1o9Gi2KqUBBIBQOvzhJt78JQfh/M3E4imFLZiXfjjYzHirl3uHcSoOTmP7D0xTSR/iTI 6/P9V1VI1jrqiCl8vDjIzy1Xo0D44+Slv9sKRbxFfmSFKMrPXbgzvXc5dmTly4b2N8q6 CHcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184963; x=1689776963; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OBnS252vauoaeLoGy2Pd1180Qv2s4Y9APpSeQJOp5Ss=; b=Udy/6DF789K7aJ5CsaoRqFZg/OfWEbZo9x8f+Vg12l9UH7jbX8BFOjXWse2w+qjy+v Ulod9qeYBRemOk7rBTvZ5pUn+rufmQ325iZ+bobj1vbNgyPkmE2SZhU2IpKYRPi6dJ/d J7TjemNGzYw2Oxk4L9hzLqM3F8WjSYcDtCRLO2HbT0hMc78VXJpPhpp3vuXdfeze5+5p 0J04i+USBbR6FzEnbUoqCsRnrKuh4PmthEfXY81zhqEIliUFr9rWxlQAfue+hI0E0FIG gOeADzGCX/obrOsdiduD+dzXJcOS6SXHcPBMowJcQ/HHijB6lKcPBtaPQCjlcK72stib YoKA== X-Gm-Message-State: AC+VfDyFPvXmzLdsWpyJh+LcYx7EX4YKPgF2G+SZUvD0XfmlqJxDyDk5 witP8U7N+N9VK0pyYdKfxD9A67OIhJ67LIh1Gic= X-Google-Smtp-Source: ACHHUZ6jDuhq/q8g50MuPTIzsX69w6aRh3BpmTWDylqCIaXs3F0MOKB8xFY6C/1Tywr+gRiR3tCbpg== X-Received: by 2002:a05:600c:2942:b0:3f7:5d:4a06 with SMTP id n2-20020a05600c294200b003f7005d4a06mr6826886wmd.1.1687184963147; Mon, 19 Jun 2023 07:29:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/33] target/arm: Convert ld/st reg+imm9 insns to decodetree Date: Mon, 19 Jun 2023 15:28:56 +0100 Message-Id: <20230619142914.963184-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185090143100005 Content-Type: text/plain; charset="utf-8" Convert the load and store instructions which use a 9-bit immediate offset to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-13-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 69 +++++++++++ target/arm/tcg/translate-a64.c | 206 ++++++++++++++------------------- 2 files changed, 153 insertions(+), 122 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index f5787919931..d55c09684a7 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -326,3 +326,72 @@ LDP_v 10 101 1 011 1 ....... ..... ..... ...= .. @ldstpair sz=3D4 sign=3D0 p STGP 01 101 0 001 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D1 w=3D1 STGP 01 101 0 010 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D0 STGP 01 101 0 011 0 ....... ..... ..... ..... @ldstpair sz=3D3 = sign=3D0 p=3D0 w=3D1 + +# Load/store register (unscaled immediate) +&ldst_imm rt rn imm sz sign w p unpriv ext +@ldst_imm .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=3D0 = p=3D0 w=3D0 +@ldst_imm_pre .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=3D0 = p=3D0 w=3D1 +@ldst_imm_post .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=3D0 = p=3D1 w=3D1 +@ldst_imm_user .. ... . .. .. . imm:s9 .. rn:5 rt:5 &ldst_imm unpriv=3D1 = p=3D0 w=3D0 + +STR_i sz:2 111 0 00 00 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 +LDR_i 00 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D1 sz=3D1 +LDR_i 10 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D1 sz=3D2 +LDR_i 11 111 0 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 sz=3D3 +LDR_i 00 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D0 sz=3D0 +LDR_i 01 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D0 sz=3D1 +LDR_i 10 111 0 00 10 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D0 sz=3D2 +LDR_i 00 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 11 0 ......... 00 ..... ..... @ldst_imm sign= =3D1 ext=3D1 sz=3D1 + +STR_i sz:2 111 0 00 00 0 ......... 01 ..... ..... @ldst_imm_post= sign=3D0 ext=3D0 +LDR_i 00 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D1 sz=3D1 +LDR_i 10 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D1 sz=3D2 +LDR_i 11 111 0 00 01 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D0 sz=3D3 +LDR_i 00 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D0 sz=3D0 +LDR_i 01 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D0 sz=3D1 +LDR_i 10 111 0 00 10 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D0 sz=3D2 +LDR_i 00 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 11 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D1 ext=3D1 sz=3D1 + +STR_i sz:2 111 0 00 00 0 ......... 10 ..... ..... @ldst_imm_user= sign=3D0 ext=3D0 +LDR_i 00 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D0 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D0 ext=3D1 sz=3D1 +LDR_i 10 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D0 ext=3D1 sz=3D2 +LDR_i 11 111 0 00 01 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D0 ext=3D0 sz=3D3 +LDR_i 00 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D0 sz=3D0 +LDR_i 01 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D0 sz=3D1 +LDR_i 10 111 0 00 10 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D0 sz=3D2 +LDR_i 00 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 11 0 ......... 10 ..... ..... @ldst_imm_user s= ign=3D1 ext=3D1 sz=3D1 + +STR_i sz:2 111 0 00 00 0 ......... 11 ..... ..... @ldst_imm_pre = sign=3D0 ext=3D0 +LDR_i 00 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D1 sz=3D1 +LDR_i 10 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D1 sz=3D2 +LDR_i 11 111 0 00 01 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D3 +LDR_i 00 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D0 sz=3D0 +LDR_i 01 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D0 sz=3D1 +LDR_i 10 111 0 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D0 sz=3D2 +LDR_i 00 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D1 sz=3D0 +LDR_i 01 111 0 00 11 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D1 ext=3D1 sz=3D1 + +# PRFM : prefetch memory: a no-op for QEMU +NOP 11 111 0 00 10 0 --------- 00 ----- ----- + +STR_v_i sz:2 111 1 00 00 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 +STR_v_i 00 111 1 00 10 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 sz=3D4 +LDR_v_i sz:2 111 1 00 01 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 +LDR_v_i 00 111 1 00 11 0 ......... 00 ..... ..... @ldst_imm sign= =3D0 ext=3D0 sz=3D4 + +STR_v_i sz:2 111 1 00 00 0 ......... 01 ..... ..... @ldst_imm_post= sign=3D0 ext=3D0 +STR_v_i 00 111 1 00 10 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D0 sz=3D4 +LDR_v_i sz:2 111 1 00 01 0 ......... 01 ..... ..... @ldst_imm_post= sign=3D0 ext=3D0 +LDR_v_i 00 111 1 00 11 0 ......... 01 ..... ..... @ldst_imm_post s= ign=3D0 ext=3D0 sz=3D4 + +STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... ..... @ldst_imm_pre = sign=3D0 ext=3D0 +STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D4 +LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre = sign=3D0 ext=3D0 +LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D4 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 103e54d0c49..a1ddb1a9cdd 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3037,134 +3037,101 @@ static bool trans_STGP(DisasContext *s, arg_ldstp= air *a) return true; } =20 -/* - * Load/store (immediate post-indexed) - * Load/store (immediate pre-indexed) - * Load/store (unscaled immediate) - * - * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0 - * +----+-------+---+-----+-----+---+--------+-----+------+------+ - * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt | - * +----+-------+---+-----+-----+---+--------+-----+------+------+ - * - * idx =3D 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeb= ack) - 10 -> unprivileged - * V =3D 0 -> non-vector - * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit - * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 - */ -static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, - int opc, - int size, - int rt, - bool is_vector) +static void op_addr_ldst_imm_pre(DisasContext *s, arg_ldst_imm *a, + TCGv_i64 *clean_addr, TCGv_i64 *dirty_add= r, + uint64_t offset, bool is_store, MemOp mop) { - int rn =3D extract32(insn, 5, 5); - int imm9 =3D sextract32(insn, 12, 9); - int idx =3D extract32(insn, 10, 2); - bool is_signed =3D false; - bool is_store =3D false; - bool is_extended =3D false; - bool is_unpriv =3D (idx =3D=3D 2); - bool iss_valid; - bool post_index; - bool writeback; int memidx; - MemOp memop; - TCGv_i64 clean_addr, dirty_addr; =20 - if (is_vector) { - size |=3D (opc & 2) << 1; - if (size > 4 || is_unpriv) { - unallocated_encoding(s); - return; - } - is_store =3D ((opc & 1) =3D=3D 0); - if (!fp_access_check(s)) { - return; - } - memop =3D finalize_memop_asimd(s, size); - } else { - if (size =3D=3D 3 && opc =3D=3D 2) { - /* PRFM - prefetch */ - if (idx !=3D 0) { - unallocated_encoding(s); - return; - } - return; - } - if (opc =3D=3D 3 && size > 1) { - unallocated_encoding(s); - return; - } - is_store =3D (opc =3D=3D 0); - is_signed =3D !is_store && extract32(opc, 1, 1); - is_extended =3D (size < 3) && extract32(opc, 0, 1); - memop =3D finalize_memop(s, size + is_signed * MO_SIGN); - } - - switch (idx) { - case 0: - case 2: - post_index =3D false; - writeback =3D false; - break; - case 1: - post_index =3D true; - writeback =3D true; - break; - case 3: - post_index =3D false; - writeback =3D true; - break; - default: - g_assert_not_reached(); - } - - iss_valid =3D !is_vector && !writeback; - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); - if (!post_index) { - tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); + *dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); + if (!a->p) { + tcg_gen_addi_i64(*dirty_addr, *dirty_addr, offset); } + memidx =3D a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); + *clean_addr =3D gen_mte_check1_mmuidx(s, *dirty_addr, is_store, + a->w || a->rn !=3D 31, + mop, a->unpriv, memidx); +} =20 - memidx =3D is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); - - clean_addr =3D gen_mte_check1_mmuidx(s, dirty_addr, is_store, - writeback || rn !=3D 31, - memop, is_unpriv, memidx); - - if (is_vector) { - if (is_store) { - do_fp_st(s, rt, clean_addr, memop); - } else { - do_fp_ld(s, rt, clean_addr, memop); - } - } else { - TCGv_i64 tcg_rt =3D cpu_reg(s, rt); - bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); - - if (is_store) { - do_gpr_st_memidx(s, tcg_rt, clean_addr, memop, memidx, - iss_valid, rt, iss_sf, false); - } else { - do_gpr_ld_memidx(s, tcg_rt, clean_addr, memop, - is_extended, memidx, - iss_valid, rt, iss_sf, false); +static void op_addr_ldst_imm_post(DisasContext *s, arg_ldst_imm *a, + TCGv_i64 dirty_addr, uint64_t offset) +{ + if (a->w) { + if (a->p) { + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr); } +} =20 - if (writeback) { - TCGv_i64 tcg_rn =3D cpu_reg_sp(s, rn); - if (post_index) { - tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); - } - tcg_gen_mov_i64(tcg_rn, dirty_addr); +static bool trans_STR_i(DisasContext *s, arg_ldst_imm *a) +{ + bool iss_sf, iss_valid =3D !a->w; + TCGv_i64 clean_addr, dirty_addr, tcg_rt; + int memidx =3D a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s= ); + MemOp mop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); + + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true, mop= ); + + tcg_rt =3D cpu_reg(s, a->rt); + iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); + + do_gpr_st_memidx(s, tcg_rt, clean_addr, mop, memidx, + iss_valid, a->rt, iss_sf, false); + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); + return true; +} + +static bool trans_LDR_i(DisasContext *s, arg_ldst_imm *a) +{ + bool iss_sf, iss_valid =3D !a->w; + TCGv_i64 clean_addr, dirty_addr, tcg_rt; + int memidx =3D a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s= ); + MemOp mop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); + + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false, mo= p); + + tcg_rt =3D cpu_reg(s, a->rt); + iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); + + do_gpr_ld_memidx(s, tcg_rt, clean_addr, mop, + a->ext, memidx, iss_valid, a->rt, iss_sf, false); + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); + return true; +} + +static bool trans_STR_v_i(DisasContext *s, arg_ldst_imm *a) +{ + TCGv_i64 clean_addr, dirty_addr; + MemOp mop; + + if (!fp_access_check(s)) { + return true; } + mop =3D finalize_memop_asimd(s, a->sz); + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true, mop= ); + do_fp_st(s, a->rt, clean_addr, mop); + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); + return true; +} + +static bool trans_LDR_v_i(DisasContext *s, arg_ldst_imm *a) +{ + TCGv_i64 clean_addr, dirty_addr; + MemOp mop; + + if (!fp_access_check(s)) { + return true; + } + mop =3D finalize_memop_asimd(s, a->sz); + op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false, mo= p); + do_fp_ld(s, a->rt, clean_addr, mop); + op_addr_ldst_imm_post(s, a, dirty_addr, a->imm); + return true; } =20 /* @@ -3637,12 +3604,7 @@ static void disas_ldst_reg(DisasContext *s, uint32_t= insn) switch (extract32(insn, 24, 2)) { case 0: if (extract32(insn, 21, 1) =3D=3D 0) { - /* Load/store register (unscaled immediate) - * Load/store immediate pre/post-indexed - * Load/store register unprivileged - */ - disas_ldst_reg_imm9(s, insn, opc, size, rt, is_vector); - return; + break; } switch (extract32(insn, 10, 2)) { case 0: --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185259; cv=none; d=zohomail.com; s=zohoarc; b=Eyyl32BWc/W98MxKYk5WJay/FfYPSBRNEXHVtUr09INJAfaGqJkAfGdgg+WXht8epP67sNj4YjU/Gpu1NraGzs/q44UeSmzTMuR8Ffx8y98zzMm2GoOtPpWa8UDiI7UTID9fM5PUmFb5HUCVU/MGJSzLwylYKPejp11UaD67wcw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185259; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=grRrhMxoKNz9VHeMIDBGTUawovkjPz3zJ6U9jbCL8Ps=; b=bPE9gSZ04CAdMsDjEFjc+6mlh1Byx4h6ejjZsd6pmTJK0kDtsAgXFU1rdKzynfAZUOaGzdzfFUHton0xlXr1rFOFJlM+qhFZDebDaHtAYBh/12tIzPfxpOo4OL02osER1wFI7SqVHEXeTEPVg0jV/q70vB8A3ka3zYbAktrFZM0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687185259695354.34852798811403; Mon, 19 Jun 2023 07:34:19 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBFtO-0001En-E5; Mon, 19 Jun 2023 10:30:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBFsl-0000bi-1C for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:27 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBFsi-0002DU-Vu for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:26 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3f9b258f3a2so8620755e9.0 for ; Mon, 19 Jun 2023 07:29:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184963; x=1689776963; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=grRrhMxoKNz9VHeMIDBGTUawovkjPz3zJ6U9jbCL8Ps=; b=L9z/Lr4/nKaNQS6DUjUehMP1i96lbcwsiaINO7Z6UiiOxh2qSSlnNXkuTDkFU3Ex4N ohVlYSi9BQ7Qg6dxhUOWCtEw2cDyn3X+hGFBRka4zGww8u28b1mTbXxfpmZLh1zeCUIy fP4LHBzRs9iXEWMpvuI47Y23KfnCKDFfTeC1fdKq2Da7tTGhWr8gjICu3JoeAMzuXu3x r6EqHgVLIX30K+dVtXs49htiG2TjRDhge9WzzhTPlK/42e5hZk2RSRAT3hnUL0qGZ8s5 dcDn1Rk6dsW2m8t8eDV4/SqFJ7ORyDvlCuK6GCPg9eXqXZdgqBJqQ6N6hvkqpd/s5h0+ itiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184963; x=1689776963; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=grRrhMxoKNz9VHeMIDBGTUawovkjPz3zJ6U9jbCL8Ps=; b=TW/fPscCpl0huR9mHgY4aiJmQL5v2l2QoeMzTx3dul+sZXTBnJs5izFTvnMjiZaJ0E /lsb3pqE3xxkV5tpAHL6j2u8BKwx0SNmoQZ8H5sFGp0PR7VTViBBqPR45t4gngbPPJJV 0kntKNhgkZdPavymN1ZsiOVVsDvoqV3rf7XVqb3Bi+bvkqL/OLKuWoHZed+8uEZSOiwa BOEJCJlgSBFbMW6OnnIgiG4DMHK86/czmYFEZ3dEJpDPlImQXVPaEdC7oqbe+xzbXcW6 8CdtUrQW2uM9rJn+KUrl+xnV5hqX6PnTScCLjn2nb/4uc+0TCLf74JHKKcORMCnXrIDo O5Ng== X-Gm-Message-State: AC+VfDwhLYuAJ8Yr+xtnDHjsxHfZ+AQoUNT1ghI2SJcngZiL5uT3N0gu 2TRqYwfFEyRUfSzCT436qvd+fXslTtZfnpqDw7w= X-Google-Smtp-Source: ACHHUZ6MIw47EsEyFiyWlnlKa5FVb/QBClQRwA0Y6CBrgIDJfHtvhs3nIPqFOjobm99qbmeRJx5RYg== X-Received: by 2002:a7b:c34d:0:b0:3f7:b1df:26d with SMTP id l13-20020a7bc34d000000b003f7b1df026dmr11376578wmj.38.1687184963564; Mon, 19 Jun 2023 07:29:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/33] target/arm: Convert LDR/STR with 12-bit immediate to decodetree Date: Mon, 19 Jun 2023 15:28:57 +0100 Message-Id: <20230619142914.963184-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185261545100005 Content-Type: text/plain; charset="utf-8" Convert the LDR and STR instructions which use a 12-bit immediate offset to decodetree. We can reuse the existing LDR and STR trans functions for these. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-14-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 25 ++++++++ target/arm/tcg/translate-a64.c | 104 +++++---------------------------- 2 files changed, 41 insertions(+), 88 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index d55c09684a7..d6b31c10838 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -395,3 +395,28 @@ STR_v_i sz:2 111 1 00 00 0 ......... 11 ..... = ..... @ldst_imm_pre sign=3D0 STR_v_i 00 111 1 00 10 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D4 LDR_v_i sz:2 111 1 00 01 0 ......... 11 ..... ..... @ldst_imm_pre = sign=3D0 ext=3D0 LDR_v_i 00 111 1 00 11 0 ......... 11 ..... ..... @ldst_imm_pre si= gn=3D0 ext=3D0 sz=3D4 + +# Load/store with an unsigned 12 bit immediate, which is scaled by the +# element size. The function gets the sz:imm and returns the scaled immedi= ate. +%uimm_scaled 10:12 sz:3 !function=3Duimm_scaled + +@ldst_uimm .. ... . .. .. ............ rn:5 rt:5 &ldst_imm unpriv=3D0= p=3D0 w=3D0 imm=3D%uimm_scaled + +STR_i sz:2 111 0 01 00 ............ ..... ..... @ldst_uimm sign= =3D0 ext=3D0 +LDR_i 00 111 0 01 01 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D1 sz=3D0 +LDR_i 01 111 0 01 01 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D1 sz=3D1 +LDR_i 10 111 0 01 01 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D1 sz=3D2 +LDR_i 11 111 0 01 01 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D0 sz=3D3 +LDR_i 00 111 0 01 10 ............ ..... ..... @ldst_uimm sign=3D= 1 ext=3D0 sz=3D0 +LDR_i 01 111 0 01 10 ............ ..... ..... @ldst_uimm sign=3D= 1 ext=3D0 sz=3D1 +LDR_i 10 111 0 01 10 ............ ..... ..... @ldst_uimm sign=3D= 1 ext=3D0 sz=3D2 +LDR_i 00 111 0 01 11 ............ ..... ..... @ldst_uimm sign=3D= 1 ext=3D1 sz=3D0 +LDR_i 01 111 0 01 11 ............ ..... ..... @ldst_uimm sign=3D= 1 ext=3D1 sz=3D1 + +# PRFM +NOP 11 111 0 01 10 ------------ ----- ----- + +STR_v_i sz:2 111 1 01 00 ............ ..... ..... @ldst_uimm sign= =3D0 ext=3D0 +STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D0 sz=3D4 +LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign= =3D0 ext=3D0 +LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D0 sz=3D4 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index a1ddb1a9cdd..82da83d9733 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -46,6 +46,22 @@ enum a64_shift_type { A64_SHIFT_TYPE_ROR =3D 3 }; =20 +/* + * Helpers for extracting complex instruction fields + */ + +/* + * For load/store with an unsigned 12 bit immediate scaled by the element + * size. The input has the immediate field in bits [14:3] and the element + * size in [2:0]. + */ +static int uimm_scaled(DisasContext *s, int x) +{ + unsigned imm =3D x >> 3; + unsigned scale =3D extract32(x, 0, 3); + return imm << scale; +} + /* * Include the generated decoders. */ @@ -3234,91 +3250,6 @@ static void disas_ldst_reg_roffset(DisasContext *s, = uint32_t insn, } } =20 -/* - * Load/store (unsigned immediate) - * - * 31 30 29 27 26 25 24 23 22 21 10 9 5 - * +----+-------+---+-----+-----+------------+-------+------+ - * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt | - * +----+-------+---+-----+-----+------------+-------+------+ - * - * For non-vector: - * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit - * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 - * For vector: - * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated - * opc<0>: 0 -> store, 1 -> load - * Rn: base address register (inc SP) - * Rt: target register - */ -static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, - int opc, - int size, - int rt, - bool is_vector) -{ - int rn =3D extract32(insn, 5, 5); - unsigned int imm12 =3D extract32(insn, 10, 12); - unsigned int offset; - TCGv_i64 clean_addr, dirty_addr; - bool is_store; - bool is_signed =3D false; - bool is_extended =3D false; - MemOp memop; - - if (is_vector) { - size |=3D (opc & 2) << 1; - if (size > 4) { - unallocated_encoding(s); - return; - } - is_store =3D !extract32(opc, 0, 1); - if (!fp_access_check(s)) { - return; - } - memop =3D finalize_memop_asimd(s, size); - } else { - if (size =3D=3D 3 && opc =3D=3D 2) { - /* PRFM - prefetch */ - return; - } - if (opc =3D=3D 3 && size > 1) { - unallocated_encoding(s); - return; - } - is_store =3D (opc =3D=3D 0); - is_signed =3D !is_store && extract32(opc, 1, 1); - is_extended =3D (size < 3) && extract32(opc, 0, 1); - memop =3D finalize_memop(s, size + is_signed * MO_SIGN); - } - - if (rn =3D=3D 31) { - gen_check_sp_alignment(s); - } - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); - offset =3D imm12 << size; - tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); - - clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, rn !=3D 31, mem= op); - - if (is_vector) { - if (is_store) { - do_fp_st(s, rt, clean_addr, memop); - } else { - do_fp_ld(s, rt, clean_addr, memop); - } - } else { - TCGv_i64 tcg_rt =3D cpu_reg(s, rt); - bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); - if (is_store) { - do_gpr_st(s, tcg_rt, clean_addr, memop, true, rt, iss_sf, fals= e); - } else { - do_gpr_ld(s, tcg_rt, clean_addr, memop, - is_extended, true, rt, iss_sf, false); - } - } -} - /* Atomic memory operations * * 31 30 27 26 24 22 21 16 15 12 10 5 0 @@ -3618,9 +3549,6 @@ static void disas_ldst_reg(DisasContext *s, uint32_t = insn) return; } break; - case 1: - disas_ldst_reg_unsigned_imm(s, insn, opc, size, rt, is_vector); - return; } unallocated_encoding(s); } --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184964; x=1689776964; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=2H1PoVsZkBVF3PXsxyEPbgjiOcccDMExHKaHncVAW8U=; b=sO8SGO7J+kL/DIN1Amv+89jnCm5GOnSgmMSy6B5GEl/CpRSViUaGovAOeCpmdZ1uM+ K6KnsNd/H0YXBd2PWW4xaakJwaNy+pGmoayrqFRzfV6na2JCfLlqZTacy4ZXoryW28xF Yr+Km+5NK8aEJi+UrX7vTvyRFhByIY/Jt8MmmMy9k6vUISHMYWLOfCMWd5r1IFn0O7P+ kmYDeOGKm5xe7U5hay4BNousQjYS9SKRw92wpeCo/B/1FRACI13dw0p1NQamYez3luAm uCIHXxYUHuqTMy1VvkMCuWn1+gYLqzE73GY0lymNrOvdNfEtxXuYK0i6t1d1ID87/Vla UO2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184964; x=1689776964; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2H1PoVsZkBVF3PXsxyEPbgjiOcccDMExHKaHncVAW8U=; b=RRvjotM4Lekx/Au7o1eG9FYYrlghnEJYQ/CeUBxm3Xwqq2JUHnxY6LET+3/a/H2Hk6 461ypemFFJwuUgPnHb6ZkO12s2GC6W6O7XkWhPV2ZBo2NaNjRXYxN6Dkaq6DqVWh2jmf Q4KUEES/nAvcKt/Q5fUlL50SUzNaWoBQCjPDvHbmtxR5ZTadJWJTHZb2FODlswjj3iTj lBoJVaZTFepiVBiY48He/+JlUJ52t5AET0GXxEcXQRQjWwKSakvnESRpyKhJ4uNEB9Co QzykNfUX1wKUZK1BFhoxx0rWGxL5cCFXiXtU35omA9/c29drr1tRPrJriz+15JpqFkiQ +9Vw== X-Gm-Message-State: AC+VfDxXqjhROsNJS9d1HBd/P22w3uFJyqBm5KAErmIRB97+knHXNlor 5AK2pDqijblpfr1UfddYME8F2bw7+r0M7quzAOs= X-Google-Smtp-Source: ACHHUZ7lGP6iS53U92rHKy9JO1PmVcImb1QZaaAkAT27wf5VUNdllTwacF1xt2xhtUCt6ChN+a0IMg== X-Received: by 2002:a7b:c84f:0:b0:3f8:fed0:1c5c with SMTP id c15-20020a7bc84f000000b003f8fed01c5cmr5496970wml.8.1687184963958; Mon, 19 Jun 2023 07:29:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/33] target/arm: Convert LDR/STR reg+reg to decodetree Date: Mon, 19 Jun 2023 15:28:58 +0100 Message-Id: <20230619142914.963184-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185223540100001 Content-Type: text/plain; charset="utf-8" Convert the LDR and STR instructions which take a register plus register offset to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-15-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 22 +++++ target/arm/tcg/translate-a64.c | 173 +++++++++++++++------------------ 2 files changed, 103 insertions(+), 92 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index d6b31c10838..5c086d6af6d 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -420,3 +420,25 @@ STR_v_i sz:2 111 1 01 00 ............ ..... ..= ... @ldst_uimm sign=3D0 ext=3D STR_v_i 00 111 1 01 10 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D0 sz=3D4 LDR_v_i sz:2 111 1 01 01 ............ ..... ..... @ldst_uimm sign= =3D0 ext=3D0 LDR_v_i 00 111 1 01 11 ............ ..... ..... @ldst_uimm sign=3D= 0 ext=3D0 sz=3D4 + +# Load/store with register offset +&ldst rm rn rt sign ext sz opt s +@ldst .. ... . .. .. . rm:5 opt:3 s:1 .. rn:5 rt:5 &ldst +STR sz:2 111 0 00 00 1 ..... ... . 10 ..... ..... @ldst sign= =3D0 ext=3D0 +LDR 00 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D1 sz=3D0 +LDR 01 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D1 sz=3D1 +LDR 10 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D1 sz=3D2 +LDR 11 111 0 00 01 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D0 sz=3D3 +LDR 00 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=3D1= ext=3D0 sz=3D0 +LDR 01 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=3D1= ext=3D0 sz=3D1 +LDR 10 111 0 00 10 1 ..... ... . 10 ..... ..... @ldst sign=3D1= ext=3D0 sz=3D2 +LDR 00 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=3D1= ext=3D1 sz=3D0 +LDR 01 111 0 00 11 1 ..... ... . 10 ..... ..... @ldst sign=3D1= ext=3D1 sz=3D1 + +# PRFM +NOP 11 111 0 00 10 1 ----- -1- - 10 ----- ----- + +STR_v sz:2 111 1 00 00 1 ..... ... . 10 ..... ..... @ldst sign= =3D0 ext=3D0 +STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D0 sz=3D4 +LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign= =3D0 ext=3D0 +LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D0 sz=3D4 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 82da83d9733..2d5e920c7bb 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3150,104 +3150,95 @@ static bool trans_LDR_v_i(DisasContext *s, arg_lds= t_imm *a) return true; } =20 -/* - * Load/store (register offset) - * - * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0 - * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ - * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt | - * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ - * - * For non-vector: - * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit - * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 - * For vector: - * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated - * opc<0>: 0 -> store, 1 -> load - * V: 1 -> vector/simd - * opt: extend encoding (see DecodeRegExtend) - * S: if S=3D1 then scale (essentially index by sizeof(size)) - * Rt: register to transfer into/out of - * Rn: address register or SP for base - * Rm: offset register or ZR for offset - */ -static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, - int opc, - int size, - int rt, - bool is_vector) +static void op_addr_ldst_pre(DisasContext *s, arg_ldst *a, + TCGv_i64 *clean_addr, TCGv_i64 *dirty_addr, + bool is_store, MemOp memop) { - int rn =3D extract32(insn, 5, 5); - int shift =3D extract32(insn, 12, 1); - int rm =3D extract32(insn, 16, 5); - int opt =3D extract32(insn, 13, 3); - bool is_signed =3D false; - bool is_store =3D false; - bool is_extended =3D false; - TCGv_i64 tcg_rm, clean_addr, dirty_addr; - MemOp memop; + TCGv_i64 tcg_rm; =20 - if (extract32(opt, 1, 1) =3D=3D 0) { - unallocated_encoding(s); - return; - } - - if (is_vector) { - size |=3D (opc & 2) << 1; - if (size > 4) { - unallocated_encoding(s); - return; - } - is_store =3D !extract32(opc, 0, 1); - if (!fp_access_check(s)) { - return; - } - memop =3D finalize_memop_asimd(s, size); - } else { - if (size =3D=3D 3 && opc =3D=3D 2) { - /* PRFM - prefetch */ - return; - } - if (opc =3D=3D 3 && size > 1) { - unallocated_encoding(s); - return; - } - is_store =3D (opc =3D=3D 0); - is_signed =3D !is_store && extract32(opc, 1, 1); - is_extended =3D (size < 3) && extract32(opc, 0, 1); - memop =3D finalize_memop(s, size + is_signed * MO_SIGN); - } - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); + *dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); =20 - tcg_rm =3D read_cpu_reg(s, rm, 1); - ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); + tcg_rm =3D read_cpu_reg(s, a->rm, 1); + ext_and_shift_reg(tcg_rm, tcg_rm, a->opt, a->s ? a->sz : 0); =20 - tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); + tcg_gen_add_i64(*dirty_addr, *dirty_addr, tcg_rm); + *clean_addr =3D gen_mte_check1(s, *dirty_addr, is_store, true, memop); +} =20 - clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, true, memop); +static bool trans_LDR(DisasContext *s, arg_ldst *a) +{ + TCGv_i64 clean_addr, dirty_addr, tcg_rt; + bool iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); + MemOp memop; =20 - if (is_vector) { - if (is_store) { - do_fp_st(s, rt, clean_addr, memop); - } else { - do_fp_ld(s, rt, clean_addr, memop); - } - } else { - TCGv_i64 tcg_rt =3D cpu_reg(s, rt); - bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); - - if (is_store) { - do_gpr_st(s, tcg_rt, clean_addr, memop, - true, rt, iss_sf, false); - } else { - do_gpr_ld(s, tcg_rt, clean_addr, memop, - is_extended, true, rt, iss_sf, false); - } + if (extract32(a->opt, 1, 1) =3D=3D 0) { + return false; } + + memop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); + op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, false, memop); + tcg_rt =3D cpu_reg(s, a->rt); + do_gpr_ld(s, tcg_rt, clean_addr, memop, + a->ext, true, a->rt, iss_sf, false); + return true; +} + +static bool trans_STR(DisasContext *s, arg_ldst *a) +{ + TCGv_i64 clean_addr, dirty_addr, tcg_rt; + bool iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); + MemOp memop; + + if (extract32(a->opt, 1, 1) =3D=3D 0) { + return false; + } + + memop =3D finalize_memop(s, a->sz); + op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, true, memop); + tcg_rt =3D cpu_reg(s, a->rt); + do_gpr_st(s, tcg_rt, clean_addr, memop, true, a->rt, iss_sf, false); + return true; +} + +static bool trans_LDR_v(DisasContext *s, arg_ldst *a) +{ + TCGv_i64 clean_addr, dirty_addr; + MemOp memop; + + if (extract32(a->opt, 1, 1) =3D=3D 0) { + return false; + } + + if (!fp_access_check(s)) { + return true; + } + + memop =3D finalize_memop_asimd(s, a->sz); + op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, false, memop); + do_fp_ld(s, a->rt, clean_addr, memop); + return true; +} + +static bool trans_STR_v(DisasContext *s, arg_ldst *a) +{ + TCGv_i64 clean_addr, dirty_addr; + MemOp memop; + + if (extract32(a->opt, 1, 1) =3D=3D 0) { + return false; + } + + if (!fp_access_check(s)) { + return true; + } + + memop =3D finalize_memop_asimd(s, a->sz); + op_addr_ldst_pre(s, a, &clean_addr, &dirty_addr, true, memop); + do_fp_st(s, a->rt, clean_addr, memop); + return true; } =20 /* Atomic memory operations @@ -3528,7 +3519,6 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, ui= nt32_t insn) static void disas_ldst_reg(DisasContext *s, uint32_t insn) { int rt =3D extract32(insn, 0, 5); - int opc =3D extract32(insn, 22, 2); bool is_vector =3D extract32(insn, 26, 1); int size =3D extract32(insn, 30, 2); =20 @@ -3542,8 +3532,7 @@ static void disas_ldst_reg(DisasContext *s, uint32_t = insn) disas_ldst_atomic(s, insn, size, rt, is_vector); return; case 2: - disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector); - return; + break; default: disas_ldst_pac(s, insn, size, rt, is_vector); return; --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185267; cv=none; d=zohomail.com; s=zohoarc; b=YgF7mehxaEVvaR4ebvMG8sRLYuJAEVwf9H5dQsh5J+Tf4GUb2bHj6Igcp39fw2zSzE1q5Pp6igtEzX6zt36xKOWjfDu4BKH5Yb/r5f6/i/J//8XdIYv+4ZnFzVhRYXDc1cM61uuihTeAUq31hVjqMx3U6i6TgadaATqQbmCmPug= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185267; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184964; x=1689776964; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=GWDPHwbryLWLThkqGYPBgX9bWZ5mDhC9sezGwxPcAlQ=; b=XKumKUw282wpVtjdBX8yek+frrlnzqkJM7dcFDwj88/KqRlHDItdzVvKQQB4WcAGDv VcVTrCkNzIVgE3JsPfeFBaZA/w1HZtJnLh4AG5G8Jsya6Nqz/n5HlqpjIKERvIQ2+I3X HU/PEMZuQar2CB6sFPcZDeYI73PFLDfYBP6RYY2/ejhoI3mcfdp8ZGM5btowRxzRgV2f afBK0ysicjthC0nbKIqlCBskTPZlaLBvZbjjEXGsrgRMgqqaygF2kTDV/ZWmjS7WLdF5 Ik9YR2wR32Ht6QawVCWjXP4vVxtVU9M8WMSkfKmHC2tA/8dt5eKPapw5fRMaEJrMilHI R0cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184964; x=1689776964; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GWDPHwbryLWLThkqGYPBgX9bWZ5mDhC9sezGwxPcAlQ=; b=hfhR5tqQJ4DPimXehyCsAOYEDCUb3uUllGgjpMam0ze4VyqnCDzgjRlaFL+TgAeM8i tMMrAuEmZ8R9RruNyaIh9PG5bV39eB1eVm30BnxpHyX7MmOBbiADEPAtVd7jlqlPtEcd dIVZxwl4K1fqngF8stgOMPriX3C3OF5votDLvtw7UTB5a458/mbPGQbGayfoDxg6vL1L hSLk3ucBahLy/0B466tc/IsIRgje2c1hvjXK742Ls5kGQHa9a47u8pF6owRRaWOzyqqE FfASFnfIxeI3G+m8DJV0lVNF6/lN8s6/zDBnmCbb0XG+J+khul03Cc11vYUtE45hnA6D oriQ== X-Gm-Message-State: AC+VfDwt/HV5mU6+vfhGTyQgbnBJVa3Wx//4Y3tjTv6UNCc/e178LxDK d8dSpg4krM3cKgQxfVUOMPnpptthFNEGp3t4DVc= X-Google-Smtp-Source: ACHHUZ7miIBrxYVck+Arp5oASn1LNM0JZ2R0ftJOh8+bDOPqdP7n4F6HprF6G30gHVaksIRn7VIIKA== X-Received: by 2002:a7b:c8c9:0:b0:3f9:82f:bad5 with SMTP id f9-20020a7bc8c9000000b003f9082fbad5mr4190522wml.35.1687184964341; Mon, 19 Jun 2023 07:29:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/33] target/arm: Convert atomic memory ops to decodetree Date: Mon, 19 Jun 2023 15:28:59 +0100 Message-Id: <20230619142914.963184-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185267826100001 Content-Type: text/plain; charset="utf-8" Convert the insns in the atomic memory operations group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-16-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 15 ++++ target/arm/tcg/translate-a64.c | 153 ++++++++++++--------------------- 2 files changed, 70 insertions(+), 98 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 5c086d6af6d..799c5ecb77a 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -442,3 +442,18 @@ STR_v sz:2 111 1 00 00 1 ..... ... . 10 ....= . ..... @ldst sign=3D0 ext=3D0 STR_v 00 111 1 00 10 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D0 sz=3D4 LDR_v sz:2 111 1 00 01 1 ..... ... . 10 ..... ..... @ldst sign= =3D0 ext=3D0 LDR_v 00 111 1 00 11 1 ..... ... . 10 ..... ..... @ldst sign=3D0= ext=3D0 sz=3D4 + +# Atomic memory operations +&atomic rs rn rt a r sz +@atomic sz:2 ... . .. a:1 r:1 . rs:5 . ... .. rn:5 rt:5 &atomic +LDADD .. 111 0 00 . . 1 ..... 0000 00 ..... ..... @atomic +LDCLR .. 111 0 00 . . 1 ..... 0001 00 ..... ..... @atomic +LDEOR .. 111 0 00 . . 1 ..... 0010 00 ..... ..... @atomic +LDSET .. 111 0 00 . . 1 ..... 0011 00 ..... ..... @atomic +LDSMAX .. 111 0 00 . . 1 ..... 0100 00 ..... ..... @atomic +LDSMIN .. 111 0 00 . . 1 ..... 0101 00 ..... ..... @atomic +LDUMAX .. 111 0 00 . . 1 ..... 0110 00 ..... ..... @atomic +LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... ..... @atomic +SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic + +LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 2d5e920c7bb..6dc8151c407 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3241,113 +3241,32 @@ static bool trans_STR_v(DisasContext *s, arg_ldst = *a) return true; } =20 -/* Atomic memory operations - * - * 31 30 27 26 24 22 21 16 15 12 10 5 0 - * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+ - * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt | - * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+ - * - * Rt: the result register - * Rn: base address or SP - * Rs: the source register for the operation - * V: vector flag (always 0 as of v8.3) - * A: acquire flag - * R: release flag - */ -static void disas_ldst_atomic(DisasContext *s, uint32_t insn, - int size, int rt, bool is_vector) + +static bool do_atomic_ld(DisasContext *s, arg_atomic *a, AtomicThreeOpFn *= fn, + int sign, bool invert) { - int rs =3D extract32(insn, 16, 5); - int rn =3D extract32(insn, 5, 5); - int o3_opc =3D extract32(insn, 12, 4); - bool r =3D extract32(insn, 22, 1); - bool a =3D extract32(insn, 23, 1); - TCGv_i64 tcg_rs, tcg_rt, clean_addr; - AtomicThreeOpFn *fn =3D NULL; - MemOp mop =3D size; + MemOp mop =3D a->sz | sign; + TCGv_i64 clean_addr, tcg_rs, tcg_rt; =20 - if (is_vector || !dc_isar_feature(aa64_atomics, s)) { - unallocated_encoding(s); - return; - } - switch (o3_opc) { - case 000: /* LDADD */ - fn =3D tcg_gen_atomic_fetch_add_i64; - break; - case 001: /* LDCLR */ - fn =3D tcg_gen_atomic_fetch_and_i64; - break; - case 002: /* LDEOR */ - fn =3D tcg_gen_atomic_fetch_xor_i64; - break; - case 003: /* LDSET */ - fn =3D tcg_gen_atomic_fetch_or_i64; - break; - case 004: /* LDSMAX */ - fn =3D tcg_gen_atomic_fetch_smax_i64; - mop |=3D MO_SIGN; - break; - case 005: /* LDSMIN */ - fn =3D tcg_gen_atomic_fetch_smin_i64; - mop |=3D MO_SIGN; - break; - case 006: /* LDUMAX */ - fn =3D tcg_gen_atomic_fetch_umax_i64; - break; - case 007: /* LDUMIN */ - fn =3D tcg_gen_atomic_fetch_umin_i64; - break; - case 010: /* SWP */ - fn =3D tcg_gen_atomic_xchg_i64; - break; - case 014: /* LDAPR, LDAPRH, LDAPRB */ - if (!dc_isar_feature(aa64_rcpc_8_3, s) || - rs !=3D 31 || a !=3D 1 || r !=3D 0) { - unallocated_encoding(s); - return; - } - break; - default: - unallocated_encoding(s); - return; - } - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } - - mop =3D check_atomic_align(s, rn, mop); - clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31,= mop); - - if (o3_opc =3D=3D 014) { - /* - * LDAPR* are a special case because they are a simple load, not a - * fetch-and-do-something op. - * The architectural consistency requirements here are weaker than - * full load-acquire (we only need "load-acquire processor consist= ent"), - * but we choose to implement them as full LDAQ. - */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop, false, - true, rt, disas_ldst_compute_iss_sf(size, false, 0), tru= e); - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - return; - } - - tcg_rs =3D read_cpu_reg(s, rs, true); - tcg_rt =3D cpu_reg(s, rt); - - if (o3_opc =3D=3D 1) { /* LDCLR */ + mop =3D check_atomic_align(s, a->rn, mop); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, a->rn), false, + a->rn !=3D 31, mop); + tcg_rs =3D read_cpu_reg(s, a->rs, true); + tcg_rt =3D cpu_reg(s, a->rt); + if (invert) { tcg_gen_not_i64(tcg_rs, tcg_rs); } - - /* The tcg atomic primitives are all full barriers. Therefore we + /* + * The tcg atomic primitives are all full barriers. Therefore we * can ignore the Acquire and Release bits of this instruction. */ fn(tcg_rt, clean_addr, tcg_rs, get_mem_index(s), mop); =20 if (mop & MO_SIGN) { - switch (size) { + switch (a->sz) { case MO_8: tcg_gen_ext8u_i64(tcg_rt, tcg_rt); break; @@ -3363,6 +3282,46 @@ static void disas_ldst_atomic(DisasContext *s, uint3= 2_t insn, g_assert_not_reached(); } } + return true; +} + +TRANS_FEAT(LDADD, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_add_= i64, 0, false) +TRANS_FEAT(LDCLR, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_and_= i64, 0, true) +TRANS_FEAT(LDEOR, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_xor_= i64, 0, false) +TRANS_FEAT(LDSET, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_or_i= 64, 0, false) +TRANS_FEAT(LDSMAX, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_sma= x_i64, MO_SIGN, false) +TRANS_FEAT(LDSMIN, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_smi= n_i64, MO_SIGN, false) +TRANS_FEAT(LDUMAX, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_uma= x_i64, 0, false) +TRANS_FEAT(LDUMIN, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_fetch_umi= n_i64, 0, false) +TRANS_FEAT(SWP, aa64_atomics, do_atomic_ld, a, tcg_gen_atomic_xchg_i64, 0,= false) + +static bool trans_LDAPR(DisasContext *s, arg_LDAPR *a) +{ + bool iss_sf =3D ldst_iss_sf(a->sz, false, false); + TCGv_i64 clean_addr; + MemOp mop; + + if (!dc_isar_feature(aa64_atomics, s) || + !dc_isar_feature(aa64_rcpc_8_3, s)) { + return false; + } + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + mop =3D check_atomic_align(s, a->rn, a->sz); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, a->rn), false, + a->rn !=3D 31, mop); + /* + * LDAPR* are a special case because they are a simple load, not a + * fetch-and-do-something op. + * The architectural consistency requirements here are weaker than + * full load-acquire (we only need "load-acquire processor consistent"= ), + * but we choose to implement them as full LDAQ. + */ + do_gpr_ld(s, cpu_reg(s, a->rt), clean_addr, mop, false, + true, a->rt, iss_sf, true); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + return true; } =20 /* @@ -3529,8 +3488,6 @@ static void disas_ldst_reg(DisasContext *s, uint32_t = insn) } switch (extract32(insn, 10, 2)) { case 0: - disas_ldst_atomic(s, insn, size, rt, is_vector); - return; case 2: break; default: --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185018; cv=none; d=zohomail.com; s=zohoarc; b=gKXW0USY7AIgi5syy1oDWQYo8z02zole4eB+iPmw5s5CG4sMO8VAlbLeKGEefePfyVmw/Jwet18pjJLIGOwVRimg9TFhoPgy2NVW1rCt0as8VujTTH6EVd0u4or0qHluDB2D2bS3ZYgDdxkMP3j2XsV83YNcq0pEXB0rDtsNa10= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185018; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wZtVgFV8GkDyXO4vsdUA6xljaLuLuyspVB+wnGanNt0=; b=NMfvruvfSlRQV8Rd61quyrJkvPZ6uEoG2LLN8kqjzmgmvJ8SiIk9TYTs09QD1MGnFeOEycdTMe2PnMoNMU6TcbGQtgmH0G8788UA1mLmkwlx5fz/NS0DVhK2bD3N0QHVq0IhhoICWJJRbCnGNh1St168We+e2ofJHbr9tfRnz80= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687185018930182.48101607781234; Mon, 19 Jun 2023 07:30:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBFtM-0000x3-T8; Mon, 19 Jun 2023 10:30:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBFsm-0000dN-Fp for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:28 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBFsj-0002EE-V7 for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:28 -0400 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-3f9b23dc270so9119485e9.0 for ; Mon, 19 Jun 2023 07:29:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184964; x=1689776964; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wZtVgFV8GkDyXO4vsdUA6xljaLuLuyspVB+wnGanNt0=; b=n/L6FsN+ZHSU9rnRM8ff7hdiQkWfAKj88SEo3GaadMf+ckOHTAmc83lrZIgVb7Rml9 6EiEm7IqPYGrSHGv1+QJh3WyBwn3hu1JGadrTXkyDodo3N4/wSIPnxLkNK3ehufEtVYD keeKPjcFyEcWRogKpRtAi/WPA8NfGgSwYjcVuWG2GLcFtQWwLwAwZY4zFN2PWNEsx7ws F6Cx63m7FHFM2se3Gba9i5gV8SiJxXElZs99iZwxOjciao/REUn5awOdTyMzHgo8joTw sS/mB6PmAIwYS7rk9dR6sCaUdtPJOUbZ69XDA/dzFJ2KT+sOmsU4cEurN6iU4PrH4QWr cTgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184964; x=1689776964; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wZtVgFV8GkDyXO4vsdUA6xljaLuLuyspVB+wnGanNt0=; b=AySdWtwxWqwdBWmfeQsjw4XPsA4KBj8Sdwa6aYYvKjq4pZApIHxqwNLtWaMYx91DGz yX/Q42qW432vtbIzKM9AHCNg47r95BSjGrS9a4+n4GQQxkJpliizELGJ+puRiJDxvwUH D5KlN5+fAQQ75sVEcUwCYE56iBAdpH2AAji3JEYqc1EfXFvEayQFP1XD+GpH4XO8sV0R rFLARoxz8XP5z3Zjl7mOqZgHT3SS09m8z01t5XYNu4SYg5LNQ81zXimgTX3xKUs5+/4u Or1vGx1cdv/VeMUeRk0yUWjE4UxCp5P6ac1fy1EbxDz2U/xi0dNJkxOnEkYnuq68/quh c7qA== X-Gm-Message-State: AC+VfDwywyX+2O97S9FIstiAB/vaS9+Ln2ufAwCFtp5osxXgCYPxfmuy LHpB8F6igi2IQE0+GCghyWNehOnt9yPRDkzybyE= X-Google-Smtp-Source: ACHHUZ6b1AMWFFT4LEt9OB6TlYnb48odo2nCazGXr7H2+f7ioRcq22V6FRU+IIKmc0+VhbeikZb99g== X-Received: by 2002:a7b:c38f:0:b0:3f8:ff4e:8ba3 with SMTP id s15-20020a7bc38f000000b003f8ff4e8ba3mr6719190wmj.38.1687184964723; Mon, 19 Jun 2023 07:29:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/33] target/arm: Convert load (pointer auth) insns to decodetree Date: Mon, 19 Jun 2023 15:29:00 +0100 Message-Id: <20230619142914.963184-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185019379100001 Convert the instructions in the load/store register (pointer authentication) group ot decodetree: LDRAA, LDRAB. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-17-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 7 +++ target/arm/tcg/translate-a64.c | 83 +++++++--------------------------- 2 files changed, 23 insertions(+), 67 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 799c5ecb77a..b80a17111e7 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -457,3 +457,10 @@ LDUMIN .. 111 0 00 . . 1 ..... 0111 00 ..... = ..... @atomic SWP .. 111 0 00 . . 1 ..... 1000 00 ..... ..... @atomic =20 LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 + +# Load/store register (pointer authentication) + +# LDRA immediate is 10 bits signed and scaled, but the bits aren't all con= tiguous +%ldra_imm 22:s1 12:9 !function=3Dtimes_2 + +LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=3D%ldra_= imm diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 6dc8151c407..2bffb14e84e 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3324,43 +3324,23 @@ static bool trans_LDAPR(DisasContext *s, arg_LDAPR = *a) return true; } =20 -/* - * PAC memory operations - * - * 31 30 27 26 24 22 21 12 11 10 5 0 - * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ - * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt | - * +------+-------+---+-----+-----+---+--------+---+---+----+-----+ - * - * Rt: the result register - * Rn: base address or SP - * V: vector flag (always 0 as of v8.3) - * M: clear for key DA, set for key DB - * W: pre-indexing flag - * S: sign for imm9. - */ -static void disas_ldst_pac(DisasContext *s, uint32_t insn, - int size, int rt, bool is_vector) +static bool trans_LDRA(DisasContext *s, arg_LDRA *a) { - int rn =3D extract32(insn, 5, 5); - bool is_wback =3D extract32(insn, 11, 1); - bool use_key_a =3D !extract32(insn, 23, 1); - int offset; TCGv_i64 clean_addr, dirty_addr, tcg_rt; MemOp memop; =20 - if (size !=3D 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) { - unallocated_encoding(s); - return; + /* Load with pointer authentication */ + if (!dc_isar_feature(aa64_pauth, s)) { + return false; } =20 - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); + dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); =20 if (s->pauth_active) { - if (use_key_a) { + if (!a->m) { gen_helper_autda(dirty_addr, cpu_env, dirty_addr, tcg_constant_i64(0)); } else { @@ -3369,25 +3349,23 @@ static void disas_ldst_pac(DisasContext *s, uint32_= t insn, } } =20 - /* Form the 10-bit signed, scaled offset. */ - offset =3D (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9); - offset =3D sextract32(offset << size, 0, 10 + size); - tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + tcg_gen_addi_i64(dirty_addr, dirty_addr, a->imm); =20 - memop =3D finalize_memop(s, size); + memop =3D finalize_memop(s, MO_64); =20 /* Note that "clean" and "dirty" here refer to TBI not PAC. */ clean_addr =3D gen_mte_check1(s, dirty_addr, false, - is_wback || rn !=3D 31, memop); + a->w || a->rn !=3D 31, memop); =20 - tcg_rt =3D cpu_reg(s, rt); + tcg_rt =3D cpu_reg(s, a->rt); do_gpr_ld(s, tcg_rt, clean_addr, memop, - /* extend */ false, /* iss_valid */ !is_wback, - /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false); + /* extend */ false, /* iss_valid */ !a->w, + /* iss_srt */ a->rt, /* iss_sf */ true, /* iss_ar */ false); =20 - if (is_wback) { - tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); + if (a->w) { + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), dirty_addr); } + return true; } =20 /* @@ -3474,31 +3452,6 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, u= int32_t insn) } } =20 -/* Load/store register (all forms) */ -static void disas_ldst_reg(DisasContext *s, uint32_t insn) -{ - int rt =3D extract32(insn, 0, 5); - bool is_vector =3D extract32(insn, 26, 1); - int size =3D extract32(insn, 30, 2); - - switch (extract32(insn, 24, 2)) { - case 0: - if (extract32(insn, 21, 1) =3D=3D 0) { - break; - } - switch (extract32(insn, 10, 2)) { - case 0: - case 2: - break; - default: - disas_ldst_pac(s, insn, size, rt, is_vector); - return; - } - break; - } - unallocated_encoding(s); -} - /* AdvSIMD load/store multiple structures * * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 @@ -4016,10 +3969,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t= insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x38: case 0x39: - case 0x3c: case 0x3d: /* Load/store register (all forms) */ - disas_ldst_reg(s, insn); - break; case 0x0c: /* AdvSIMD load/store multiple structures */ disas_ldst_multiple_struct(s, insn); break; --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185238; cv=none; d=zohomail.com; s=zohoarc; b=d7LKOZtyn/ba1AU2VNupDb0DrYxoMXXXX6+XyMnUk2muXx/yDn/1T3gPOkB6JgnuzULqXmQGZpa7Ujdphh85jb6ZWUMbR3bAzdiMdsjYhtyS4CB5HTDI/8mzWVN2EDqlzrYYMBG2Y88HxQJX1fuKkQpksGXtmw9O9IORJlvMczY= ARC-Message-Signature: i=1; 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Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-18-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 10 +++ target/arm/tcg/translate-a64.c | 132 ++++++++++++--------------------- 2 files changed, 56 insertions(+), 86 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index b80a17111e7..db4f44c4f40 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -464,3 +464,13 @@ LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5= rt:5 %ldra_imm 22:s1 12:9 !function=3Dtimes_2 =20 LDRA 11 111 0 00 m:1 . 1 ......... w:1 1 rn:5 rt:5 imm=3D%ldra_= imm + +&ldapr_stlr_i rn rt imm sz sign ext +@ldapr_stlr_i .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i +STLR_i sz:2 011001 00 0 ......... 00 ..... ..... @ldapr_stlr_i si= gn=3D0 ext=3D0 +LDAPR_i sz:2 011001 01 0 ......... 00 ..... ..... @ldapr_stlr_i si= gn=3D0 ext=3D0 +LDAPR_i 00 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D0 sz=3D0 +LDAPR_i 01 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D0 sz=3D1 +LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D0 sz=3D2 +LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D1 sz=3D0 +LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D1 sz=3D1 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 2bffb14e84e..c0d38c48798 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2652,22 +2652,12 @@ static void gen_compare_and_swap_pair(DisasContext = *s, int rs, int rt, } } =20 -/* Update the Sixty-Four bit (SF) registersize. This logic is derived +/* + * Compute the ISS.SF bit for syndrome information if an exception + * is taken on a load or store. This indicates whether the instruction + * is accessing a 32-bit or 64-bit register. This logic is derived * from the ARMv8 specs for LDR (Shared decode for all encodings). */ -static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc) -{ - int opc0 =3D extract32(opc, 0, 1); - int regsize; - - if (is_signed) { - regsize =3D opc0 ? 32 : 64; - } else { - regsize =3D size =3D=3D 3 ? 64 : 32; - } - return regsize =3D=3D 64; -} - static bool ldst_iss_sf(int size, bool sign, bool ext) { =20 @@ -3368,88 +3358,60 @@ static bool trans_LDRA(DisasContext *s, arg_LDRA *a) return true; } =20 -/* - * LDAPR/STLR (unscaled immediate) - * - * 31 30 24 22 21 12 10 5 0 - * +------+-------------+-----+---+--------+-----+----+-----+ - * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt | - * +------+-------------+-----+---+--------+-----+----+-----+ - * - * Rt: source or destination register - * Rn: base register - * imm9: unscaled immediate offset - * opc: 00: STLUR*, 01/10/11: various LDAPUR* - * size: size of load/store - */ -static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) +static bool trans_LDAPR_i(DisasContext *s, arg_ldapr_stlr_i *a) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int offset =3D sextract32(insn, 12, 9); - int opc =3D extract32(insn, 22, 2); - int size =3D extract32(insn, 30, 2); TCGv_i64 clean_addr, dirty_addr; - bool is_store =3D false; - bool extend =3D false; - bool iss_sf; - MemOp mop =3D size; + MemOp mop =3D a->sz | (a->sign ? MO_SIGN : 0); + bool iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); =20 if (!dc_isar_feature(aa64_rcpc_8_4, s)) { - unallocated_encoding(s); - return; + return false; } =20 - switch (opc) { - case 0: /* STLURB */ - is_store =3D true; - break; - case 1: /* LDAPUR* */ - break; - case 2: /* LDAPURS* 64-bit variant */ - if (size =3D=3D 3) { - unallocated_encoding(s); - return; - } - mop |=3D MO_SIGN; - break; - case 3: /* LDAPURS* 32-bit variant */ - if (size > 1) { - unallocated_encoding(s); - return; - } - mop |=3D MO_SIGN; - extend =3D true; /* zero-extend 32->64 after signed load */ - break; - default: - g_assert_not_reached(); - } - - iss_sf =3D disas_ldst_compute_iss_sf(size, (mop & MO_SIGN) !=3D 0, opc= ); - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 - mop =3D check_ordered_align(s, rn, offset, is_store, mop); - - dirty_addr =3D read_cpu_reg_sp(s, rn, 1); - tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + mop =3D check_ordered_align(s, a->rn, a->imm, false, mop); + dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); + tcg_gen_addi_i64(dirty_addr, dirty_addr, a->imm); clean_addr =3D clean_data_tbi(s, dirty_addr); =20 - if (is_store) { - /* Store-Release semantics */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - do_gpr_st(s, cpu_reg(s, rt), clean_addr, mop, true, rt, iss_sf, tr= ue); - } else { - /* - * Load-AcquirePC semantics; we implement as the slightly more - * restrictive Load-Acquire. - */ - do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop, - extend, true, rt, iss_sf, true); - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + /* + * Load-AcquirePC semantics; we implement as the slightly more + * restrictive Load-Acquire. + */ + do_gpr_ld(s, cpu_reg(s, a->rt), clean_addr, mop, a->ext, true, + a->rt, iss_sf, true); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + return true; +} + +static bool trans_STLR_i(DisasContext *s, arg_ldapr_stlr_i *a) +{ + TCGv_i64 clean_addr, dirty_addr; + MemOp mop =3D a->sz; + bool iss_sf =3D ldst_iss_sf(a->sz, a->sign, a->ext); + + if (!dc_isar_feature(aa64_rcpc_8_4, s)) { + return false; } + + /* TODO: ARMv8.4-LSE SCTLR.nAA */ + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + mop =3D check_ordered_align(s, a->rn, a->imm, true, mop); + dirty_addr =3D read_cpu_reg_sp(s, a->rn, 1); + tcg_gen_addi_i64(dirty_addr, dirty_addr, a->imm); + clean_addr =3D clean_data_tbi(s, dirty_addr); + + /* Store-Release semantics */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + do_gpr_st(s, cpu_reg(s, a->rt), clean_addr, mop, true, a->rt, iss_sf, = true); + return true; } =20 /* AdvSIMD load/store multiple structures @@ -3978,8 +3940,6 @@ static void disas_ldst(DisasContext *s, uint32_t insn) case 0x19: if (extract32(insn, 21, 1) !=3D 0) { disas_ldst_tag(s, insn); - } else if (extract32(insn, 10, 2) =3D=3D 0) { - disas_ldst_ldapr_stlr(s, insn); } else { unallocated_encoding(s); } --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184965; x=1689776965; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ecFzLygpAx1acENNT2vpDRF7LirFVwYSwEwJOiBRXNw=; b=dw0Y9OkdwRM6niVfLFQQN+pPcgH7yplnpRCyI0FtZRsi07ClNjpvlNwgeHw7CBqJ83 ixkky6w8rrvZBUDBqTledNeLAc4iSH00yNm5nj7XwvcBcrctBkOQ76AYv0u8pelE+8nK X4xhj/RQ5IzAFvBhyBrCx1jLVVz8ea1PhduAD8bBmxOaK7LBZFD5yycUNS4eGhrlXzjX l7mQvse3ZHx2J3dYpPVGqaaRBTmatjaKJgY5b4z0wAmjTDT9V2C60h203GyKTd6woC71 S+KRdJPYN5FuEJJduRhEEsCIOSsagi5TyYiJDl8Y/aHMokU4zaRvT4hcegLCagYp4RRQ QEEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184966; x=1689776966; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ecFzLygpAx1acENNT2vpDRF7LirFVwYSwEwJOiBRXNw=; b=Ds7q97SUrtehi2QvBIGXIJ7y4wYCf9+BkyZXUq82xcAughiJKNpk5zFzfKpj+7+Bfx 7CAuTjE0azQcQ1W2fJ333Yeh5xflCb7MfC1MSHuUMbUGN9mVKazGDcZVTvm6nm+H3/qT o8c+E9qX4NkjDOoAjZwVKViT4tJStOWaNPBIokU5YZVBqPoeVnJC1nL/XcjfR6RvYgRA w4Q2/gsFTYlYbesH2RMyIzTFcivvhFTk3zd637olagwPhn0rMsrR6f73RQvZ+WzMimTt 9qbdHC2XSLcALf13+gvaEMzmFfEqab689Nz9Jzf5kysV3xv6wAB0T0Mc4EpwoHRWXfl7 CAVg== X-Gm-Message-State: AC+VfDxMizBVTnYQAeUjyyNpbRKNVGPrV1s6ogeUhiN7is6kKtKZKs8F UHcF8dXNZ36erI7t62a8twZlKhOPmQSGL1ZNtCE= X-Google-Smtp-Source: ACHHUZ69RSulJoZptmSnesqUeq/Z9cn2Fm5GQV/XdmQxVOMsUimjoUw1a4kjunSq3NIOwv9n+VTtWA== X-Received: by 2002:a19:3851:0:b0:4f5:a181:97bf with SMTP id d17-20020a193851000000b004f5a18197bfmr4751203lfj.58.1687184965704; Mon, 19 Jun 2023 07:29:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/33] target/arm: Convert load/store (multiple structures) to decodetree Date: Mon, 19 Jun 2023 15:29:02 +0100 Message-Id: <20230619142914.963184-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185092160100015 Content-Type: text/plain; charset="utf-8" Convert the instructions in the ASIMD load/store multiple structures instruction classes to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-19-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 20 +++ target/arm/tcg/translate-a64.c | 222 ++++++++++++++++----------------- 2 files changed, 131 insertions(+), 111 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index db4f44c4f40..69bdfa2e73b 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -474,3 +474,23 @@ LDAPR_i 01 011001 10 0 ......... 00 ..... ....= . @ldapr_stlr_i sign=3D1 ext LDAPR_i 10 011001 10 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D0 sz=3D2 LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D1 sz=3D0 LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D1 sz=3D1 + +# Load/store multiple structures +# The 4-bit opcode in [15:12] encodes repeat count and structure elements +&ldst_mult rm rn rt sz q p rpt selem +@ldst_mult . q:1 ...... p:1 . . rm:5 .... sz:2 rn:5 rt:5 &ldst_mult +ST_mult 0 . 001100 . 0 0 ..... 0000 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D4 +ST_mult 0 . 001100 . 0 0 ..... 0010 .. ..... ..... @ldst_mult rpt= =3D4 selem=3D1 +ST_mult 0 . 001100 . 0 0 ..... 0100 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D3 +ST_mult 0 . 001100 . 0 0 ..... 0110 .. ..... ..... @ldst_mult rpt= =3D3 selem=3D1 +ST_mult 0 . 001100 . 0 0 ..... 0111 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D1 +ST_mult 0 . 001100 . 0 0 ..... 1000 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D2 +ST_mult 0 . 001100 . 0 0 ..... 1010 .. ..... ..... @ldst_mult rpt= =3D2 selem=3D1 + +LD_mult 0 . 001100 . 1 0 ..... 0000 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D4 +LD_mult 0 . 001100 . 1 0 ..... 0010 .. ..... ..... @ldst_mult rpt= =3D4 selem=3D1 +LD_mult 0 . 001100 . 1 0 ..... 0100 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D3 +LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... ..... @ldst_mult rpt= =3D3 selem=3D1 +LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D1 +LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D2 +LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt= =3D2 selem=3D1 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index c0d38c48798..f2d9ceeed04 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3414,99 +3414,28 @@ static bool trans_STLR_i(DisasContext *s, arg_ldapr= _stlr_i *a) return true; } =20 -/* AdvSIMD load/store multiple structures - * - * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 - * +---+---+---------------+---+-------------+--------+------+------+-----= -+ - * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt = | - * +---+---+---------------+---+-------------+--------+------+------+-----= -+ - * - * AdvSIMD load/store multiple structures (post-indexed) - * - * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0 - * +---+---+---------------+---+---+---------+--------+------+------+-----= -+ - * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt = | - * +---+---+---------------+---+---+---------+--------+------+------+-----= -+ - * - * Rt: first (or only) SIMD&FP register to be transferred - * Rn: base address or SP - * Rm (post-index only): post-index register (when !31) or size dependent = #imm - */ -static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) +static bool trans_LD_mult(DisasContext *s, arg_ldst_mult *a) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int rm =3D extract32(insn, 16, 5); - int size =3D extract32(insn, 10, 2); - int opcode =3D extract32(insn, 12, 4); - bool is_store =3D !extract32(insn, 22, 1); - bool is_postidx =3D extract32(insn, 23, 1); - bool is_q =3D extract32(insn, 30, 1); TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; MemOp endian, align, mop; =20 int total; /* total bytes */ int elements; /* elements per vector */ - int rpt; /* num iterations */ - int selem; /* structure elements */ int r; + int size =3D a->sz; =20 - if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) { - unallocated_encoding(s); - return; + if (!a->p && a->rm !=3D 0) { + /* For non-postindexed accesses the Rm field must be 0 */ + return false; } - - if (!is_postidx && rm !=3D 0) { - unallocated_encoding(s); - return; + if (size =3D=3D 3 && !a->q && a->selem !=3D 1) { + return false; } - - /* From the shared decode logic */ - switch (opcode) { - case 0x0: - rpt =3D 1; - selem =3D 4; - break; - case 0x2: - rpt =3D 4; - selem =3D 1; - break; - case 0x4: - rpt =3D 1; - selem =3D 3; - break; - case 0x6: - rpt =3D 3; - selem =3D 1; - break; - case 0x7: - rpt =3D 1; - selem =3D 1; - break; - case 0x8: - rpt =3D 1; - selem =3D 2; - break; - case 0xa: - rpt =3D 2; - selem =3D 1; - break; - default: - unallocated_encoding(s); - return; - } - - if (size =3D=3D 3 && !is_q && selem !=3D 1) { - /* reserved */ - unallocated_encoding(s); - return; - } - if (!fp_access_check(s)) { - return; + return true; } =20 - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 @@ -3516,22 +3445,22 @@ static void disas_ldst_multiple_struct(DisasContext= *s, uint32_t insn) endian =3D MO_LE; } =20 - total =3D rpt * selem * (is_q ? 16 : 8); - tcg_rn =3D cpu_reg_sp(s, rn); + total =3D a->rpt * a->selem * (a->q ? 16 : 8); + tcg_rn =3D cpu_reg_sp(s, a->rn); =20 /* * Issue the MTE check vs the logical repeat count, before we * promote consecutive little-endian elements below. */ - clean_addr =3D gen_mte_checkN(s, tcg_rn, is_store, is_postidx || rn != =3D 31, - total, finalize_memop_asimd(s, size)); + clean_addr =3D gen_mte_checkN(s, tcg_rn, false, a->p || a->rn !=3D 31,= total, + finalize_memop_asimd(s, size)); =20 /* * Consecutive little-endian elements from a single register * can be promoted to a larger little-endian operation. */ align =3D MO_ALIGN; - if (selem =3D=3D 1 && endian =3D=3D MO_LE) { + if (a->selem =3D=3D 1 && endian =3D=3D MO_LE) { align =3D pow2_align(size); size =3D 3; } @@ -3540,45 +3469,119 @@ static void disas_ldst_multiple_struct(DisasContex= t *s, uint32_t insn) } mop =3D endian | size | align; =20 - elements =3D (is_q ? 16 : 8) >> size; + elements =3D (a->q ? 16 : 8) >> size; tcg_ebytes =3D tcg_constant_i64(1 << size); - for (r =3D 0; r < rpt; r++) { + for (r =3D 0; r < a->rpt; r++) { int e; for (e =3D 0; e < elements; e++) { int xs; - for (xs =3D 0; xs < selem; xs++) { - int tt =3D (rt + r + xs) % 32; - if (is_store) { - do_vec_st(s, tt, e, clean_addr, mop); - } else { - do_vec_ld(s, tt, e, clean_addr, mop); - } + for (xs =3D 0; xs < a->selem; xs++) { + int tt =3D (a->rt + r + xs) % 32; + do_vec_ld(s, tt, e, clean_addr, mop); tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); } } } =20 - if (!is_store) { - /* For non-quad operations, setting a slice of the low - * 64 bits of the register clears the high 64 bits (in - * the ARM ARM pseudocode this is implicit in the fact - * that 'rval' is a 64 bit wide variable). - * For quad operations, we might still need to zero the - * high bits of SVE. - */ - for (r =3D 0; r < rpt * selem; r++) { - int tt =3D (rt + r) % 32; - clear_vec_high(s, is_q, tt); + /* + * For non-quad operations, setting a slice of the low 64 bits of + * the register clears the high 64 bits (in the ARM ARM pseudocode + * this is implicit in the fact that 'rval' is a 64 bit wide + * variable). For quad operations, we might still need to zero + * the high bits of SVE. + */ + for (r =3D 0; r < a->rpt * a->selem; r++) { + int tt =3D (a->rt + r) % 32; + clear_vec_high(s, a->q, tt); + } + + if (a->p) { + if (a->rm =3D=3D 31) { + tcg_gen_addi_i64(tcg_rn, tcg_rn, total); + } else { + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); + } + } + return true; +} + +static bool trans_ST_mult(DisasContext *s, arg_ldst_mult *a) +{ + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; + MemOp endian, align, mop; + + int total; /* total bytes */ + int elements; /* elements per vector */ + int r; + int size =3D a->sz; + + if (!a->p && a->rm !=3D 0) { + /* For non-postindexed accesses the Rm field must be 0 */ + return false; + } + if (size =3D=3D 3 && !a->q && a->selem !=3D 1) { + return false; + } + if (!fp_access_check(s)) { + return true; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + /* For our purposes, bytes are always little-endian. */ + endian =3D s->be_data; + if (size =3D=3D 0) { + endian =3D MO_LE; + } + + total =3D a->rpt * a->selem * (a->q ? 16 : 8); + tcg_rn =3D cpu_reg_sp(s, a->rn); + + /* + * Issue the MTE check vs the logical repeat count, before we + * promote consecutive little-endian elements below. + */ + clean_addr =3D gen_mte_checkN(s, tcg_rn, true, a->p || a->rn !=3D 31, = total, + finalize_memop_asimd(s, size)); + + /* + * Consecutive little-endian elements from a single register + * can be promoted to a larger little-endian operation. + */ + align =3D MO_ALIGN; + if (a->selem =3D=3D 1 && endian =3D=3D MO_LE) { + align =3D pow2_align(size); + size =3D 3; + } + if (!s->align_mem) { + align =3D 0; + } + mop =3D endian | size | align; + + elements =3D (a->q ? 16 : 8) >> size; + tcg_ebytes =3D tcg_constant_i64(1 << size); + for (r =3D 0; r < a->rpt; r++) { + int e; + for (e =3D 0; e < elements; e++) { + int xs; + for (xs =3D 0; xs < a->selem; xs++) { + int tt =3D (a->rt + r + xs) % 32; + do_vec_st(s, tt, e, clean_addr, mop); + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); + } } } =20 - if (is_postidx) { - if (rm =3D=3D 31) { + if (a->p) { + if (a->rm =3D=3D 31) { tcg_gen_addi_i64(tcg_rn, tcg_rn, total); } else { - tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); } } + return true; } =20 /* AdvSIMD load/store single structure @@ -3931,9 +3934,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t = insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x0c: /* AdvSIMD load/store multiple structures */ - disas_ldst_multiple_struct(s, insn); - break; case 0x0d: /* AdvSIMD load/store single structure */ disas_ldst_single_struct(s, insn); break; --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185057; cv=none; d=zohomail.com; s=zohoarc; b=Bjk9sK+Zi7p4k0AEyttYFHuL/gjX3bBTl7jds744Yl85c4PnOf7XfWynXT/P0nDU5uVewBxZCbQ4YzS3QLFI9DWzQFCDQopxUZCY2WxASUQRFKHo6AYVJR+vq4/EbMzfwAinJsQ7Q6pT9yJmMYItKbHbJjuKCV6sBZlXvVMHt8E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185057; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PtPIKJjcfFQdrBAt/+UBZeTWmTkL2YszBATqTZTTZWY=; b=OLzeGHIr+9hTg2wdcMrwJbSaVXidvMzbqiQ3mAyNGF28rUCp/QU/uRP2RN6+kPFd/ygp0dylokatr1vQm9Za7AaEeIjKZ+H9IpA5vkEIINhL2N7BfUYfGXTNjPpYyhs605neKJyjSZIPdDd8YgP80+vmzJ97QOKWygXKrIAZSaA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687185057121987.6680629355726; Mon, 19 Jun 2023 07:30:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBFtS-0001ad-KE; Mon, 19 Jun 2023 10:30:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBFsp-0000eC-KO for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:31 -0400 Received: from mail-lf1-x134.google.com ([2a00:1450:4864:20::134]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBFsm-0002FU-EM for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:30 -0400 Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-4f004cc54f4so4649864e87.3 for ; Mon, 19 Jun 2023 07:29:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184966; x=1689776966; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=PtPIKJjcfFQdrBAt/+UBZeTWmTkL2YszBATqTZTTZWY=; b=MLwu3vJagLhfLEsKomdcV+6vXVhODkt/kXrnEftDrWH9VNXppDluPvEo0wI7Vt7tJ/ DW5rng25Gno6n8YRRjK+Wo83o0Gtk2vsijNNeZ7TQzcl1cp8QmNuj4AFBw+v2nAhEEkM XQn2wMxF1xwDDG95h9ij4D2tpFFRz1rtw/o6QO4nSaR1bBn9WuyM6cF8SZ2J4J/PfE8I kleN0y3VT39RO6dwOdIWa6l4fVZrQ0rvU0BJcbJbjFoVXx9gu7n739Sbr2IKvPMhrBNy B3pFoxYKRQAx4ucLDlB46t6ggdyqGjsIMBMo0x91h+gRqkQH3t3JJ28pHXOv4rBOq8KD MsXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184966; x=1689776966; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PtPIKJjcfFQdrBAt/+UBZeTWmTkL2YszBATqTZTTZWY=; b=LF8domKu/96UBuda/UMvdsVs1E1QvLQHxVFD7rVROfK/8pQyfpbap/GldhOZJzJYml VS/E0J0Kjpw9ENRM4rp7Z3NGEUvAA5+u9ANXwVQwF+jkyQDlRmjCFiDbYcMLm4/SeWXb HXJsTmuaefvYlGHzZdD1u9engE53YM31SHMOKiA8OXVNI7QmDKpoZ96ebhUJ7a3qzVBk 9Ny1+0eaMrUFF+ucw54CiQHCKm7NyyqADvVwnpkVWCiMlAdZfYCZNFWx6RMy4dwxn+o9 b3EYCdDZwU0Ae9Fbxgw8NCynSdCcXQS0AuOf8YKke3QcifoY5gWotT6UTlcMpH8i+2Ex WeqA== X-Gm-Message-State: AC+VfDy/B/3XmULovu3HuyGBPfsle9OMzuvAVntYbjMvOTcUFcIBQW+9 SANYUdzAYn0QH6PWwlqzbsg25ctUec/1sXtqvM4= X-Google-Smtp-Source: ACHHUZ6d2OEKr3VAvhXZ6hmkhvsdheEpYPGveAseBZ3fh7sgCUh7WRRSH/WB54zqVKqk3BVR3kmC/Q== X-Received: by 2002:a05:6512:2e7:b0:4f8:71ca:bb15 with SMTP id m7-20020a05651202e700b004f871cabb15mr1686654lfq.48.1687184966294; Mon, 19 Jun 2023 07:29:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/33] target/arm: Convert load/store single structure to decodetree Date: Mon, 19 Jun 2023 15:29:03 +0100 Message-Id: <20230619142914.963184-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::134; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x134.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185057788100004 Content-Type: text/plain; charset="utf-8" Convert the ASIMD load/store single structure insns to decodetree. Signed-off-by: Peter Maydell Message-id: 20230602155223.2040685-20-peter.maydell@linaro.org Reviewed-by: Richard Henderson --- target/arm/tcg/a64.decode | 34 +++++ target/arm/tcg/translate-a64.c | 219 +++++++++++++++------------------ 2 files changed, 136 insertions(+), 117 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 69bdfa2e73b..4ffdc91865f 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -494,3 +494,37 @@ LD_mult 0 . 001100 . 1 0 ..... 0110 .. ..... .= .... @ldst_mult rpt=3D3 sele LD_mult 0 . 001100 . 1 0 ..... 0111 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D1 LD_mult 0 . 001100 . 1 0 ..... 1000 .. ..... ..... @ldst_mult rpt= =3D1 selem=3D2 LD_mult 0 . 001100 . 1 0 ..... 1010 .. ..... ..... @ldst_mult rpt= =3D2 selem=3D1 + +# Load/store single structure +&ldst_single rm rn rt p selem index scale + +%ldst_single_selem 13:1 21:1 !function=3Dplus_1 + +%ldst_single_index_b 30:1 10:3 +%ldst_single_index_h 30:1 11:2 +%ldst_single_index_s 30:1 12:1 + +@ldst_single_b .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ + &ldst_single scale=3D0 selem=3D%ldst_single_selem \ + index=3D%ldst_single_index_b +@ldst_single_h .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ + &ldst_single scale=3D1 selem=3D%ldst_single_selem \ + index=3D%ldst_single_index_h +@ldst_single_s .. ...... p:1 .. rm:5 ...... rn:5 rt:5 \ + &ldst_single scale=3D2 selem=3D%ldst_single_selem \ + index=3D%ldst_single_index_s +@ldst_single_d . index:1 ...... p:1 .. rm:5 ...... rn:5 rt:5 \ + &ldst_single scale=3D3 selem=3D%ldst_single_selem + +ST_single 0 . 001101 . 0 . ..... 00 . ... ..... ..... @ldst_sing= le_b +ST_single 0 . 001101 . 0 . ..... 01 . ..0 ..... ..... @ldst_sing= le_h +ST_single 0 . 001101 . 0 . ..... 10 . .00 ..... ..... @ldst_sing= le_s +ST_single 0 . 001101 . 0 . ..... 10 . 001 ..... ..... @ldst_sing= le_d + +LD_single 0 . 001101 . 1 . ..... 00 . ... ..... ..... @ldst_sing= le_b +LD_single 0 . 001101 . 1 . ..... 01 . ..0 ..... ..... @ldst_sing= le_h +LD_single 0 . 001101 . 1 . ..... 10 . .00 ..... ..... @ldst_sing= le_s +LD_single 0 . 001101 . 1 . ..... 10 . 001 ..... ..... @ldst_sing= le_d + +# Replicating load case +LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem= =3D%ldst_single_selem diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index f2d9ceeed04..f9a76141eb6 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3584,141 +3584,129 @@ static bool trans_ST_mult(DisasContext *s, arg_ld= st_mult *a) return true; } =20 -/* AdvSIMD load/store single structure - * - * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 = 0 - * +---+---+---------------+-----+-----------+-----+---+------+------+----= --+ - * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt= | - * +---+---+---------------+-----+-----------+-----+---+------+------+----= --+ - * - * AdvSIMD load/store single structure (post-indexed) - * - * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 = 0 - * +---+---+---------------+-----+-----------+-----+---+------+------+----= --+ - * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt= | - * +---+---+---------------+-----+-----------+-----+---+------+------+----= --+ - * - * Rt: first (or only) SIMD&FP register to be transferred - * Rn: base address or SP - * Rm (post-index only): post-index register (when !31) or size dependent = #imm - * index =3D encoded in Q:S:size dependent on size - * - * lane_size =3D encoded in R, opc - * transfer width =3D encoded in opc, S, size - */ -static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) +static bool trans_ST_single(DisasContext *s, arg_ldst_single *a) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - int rm =3D extract32(insn, 16, 5); - int size =3D extract32(insn, 10, 2); - int S =3D extract32(insn, 12, 1); - int opc =3D extract32(insn, 13, 3); - int R =3D extract32(insn, 21, 1); - int is_load =3D extract32(insn, 22, 1); - int is_postidx =3D extract32(insn, 23, 1); - int is_q =3D extract32(insn, 30, 1); - - int scale =3D extract32(opc, 1, 2); - int selem =3D (extract32(opc, 0, 1) << 1 | R) + 1; - bool replicate =3D false; - int index =3D is_q << 3 | S << 2 | size; - int xs, total; + int xs, total, rt; TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; MemOp mop; =20 - if (extract32(insn, 31, 1)) { - unallocated_encoding(s); - return; + if (!a->p && a->rm !=3D 0) { + return false; } - if (!is_postidx && rm !=3D 0) { - unallocated_encoding(s); - return; - } - - switch (scale) { - case 3: - if (!is_load || S) { - unallocated_encoding(s); - return; - } - scale =3D size; - replicate =3D true; - break; - case 0: - break; - case 1: - if (extract32(size, 0, 1)) { - unallocated_encoding(s); - return; - } - index >>=3D 1; - break; - case 2: - if (extract32(size, 1, 1)) { - unallocated_encoding(s); - return; - } - if (!extract32(size, 0, 1)) { - index >>=3D 2; - } else { - if (S) { - unallocated_encoding(s); - return; - } - index >>=3D 3; - scale =3D 3; - } - break; - default: - g_assert_not_reached(); - } - if (!fp_access_check(s)) { - return; + return true; } =20 - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 - total =3D selem << scale; - tcg_rn =3D cpu_reg_sp(s, rn); + total =3D a->selem << a->scale; + tcg_rn =3D cpu_reg_sp(s, a->rn); =20 - mop =3D finalize_memop_asimd(s, scale); - - clean_addr =3D gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != =3D 31, + mop =3D finalize_memop_asimd(s, a->scale); + clean_addr =3D gen_mte_checkN(s, tcg_rn, true, a->p || a->rn !=3D 31, total, mop); =20 - tcg_ebytes =3D tcg_constant_i64(1 << scale); - for (xs =3D 0; xs < selem; xs++) { - if (replicate) { - /* Load and replicate to all elements */ - TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); - - tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), mop= ); - tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt), - (is_q + 1) * 8, vec_full_reg_size(s), - tcg_tmp); - } else { - /* Load/store one element per register */ - if (is_load) { - do_vec_ld(s, rt, index, clean_addr, mop); - } else { - do_vec_st(s, rt, index, clean_addr, mop); - } - } + tcg_ebytes =3D tcg_constant_i64(1 << a->scale); + for (xs =3D 0, rt =3D a->rt; xs < a->selem; xs++, rt =3D (rt + 1) % 32= ) { + do_vec_st(s, rt, a->index, clean_addr, mop); tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); - rt =3D (rt + 1) % 32; } =20 - if (is_postidx) { - if (rm =3D=3D 31) { + if (a->p) { + if (a->rm =3D=3D 31) { tcg_gen_addi_i64(tcg_rn, tcg_rn, total); } else { - tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); } } + return true; +} + +static bool trans_LD_single(DisasContext *s, arg_ldst_single *a) +{ + int xs, total, rt; + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; + MemOp mop; + + if (!a->p && a->rm !=3D 0) { + return false; + } + if (!fp_access_check(s)) { + return true; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + total =3D a->selem << a->scale; + tcg_rn =3D cpu_reg_sp(s, a->rn); + + mop =3D finalize_memop_asimd(s, a->scale); + clean_addr =3D gen_mte_checkN(s, tcg_rn, false, a->p || a->rn !=3D 31, + total, mop); + + tcg_ebytes =3D tcg_constant_i64(1 << a->scale); + for (xs =3D 0, rt =3D a->rt; xs < a->selem; xs++, rt =3D (rt + 1) % 32= ) { + do_vec_ld(s, rt, a->index, clean_addr, mop); + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); + } + + if (a->p) { + if (a->rm =3D=3D 31) { + tcg_gen_addi_i64(tcg_rn, tcg_rn, total); + } else { + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); + } + } + return true; +} + +static bool trans_LD_single_repl(DisasContext *s, arg_LD_single_repl *a) +{ + int xs, total, rt; + TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; + MemOp mop; + + if (!a->p && a->rm !=3D 0) { + return false; + } + if (!fp_access_check(s)) { + return true; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + total =3D a->selem << a->scale; + tcg_rn =3D cpu_reg_sp(s, a->rn); + + mop =3D finalize_memop_asimd(s, a->scale); + clean_addr =3D gen_mte_checkN(s, tcg_rn, false, a->p || a->rn !=3D 31, + total, mop); + + tcg_ebytes =3D tcg_constant_i64(1 << a->scale); + for (xs =3D 0, rt =3D a->rt; xs < a->selem; xs++, rt =3D (rt + 1) % 32= ) { + /* Load and replicate to all elements */ + TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); + + tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), mop); + tcg_gen_gvec_dup_i64(a->scale, vec_full_reg_offset(s, rt), + (a->q + 1) * 8, vec_full_reg_size(s), tcg_tmp= ); + tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); + } + + if (a->p) { + if (a->rm =3D=3D 31) { + tcg_gen_addi_i64(tcg_rn, tcg_rn, total); + } else { + tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, a->rm)); + } + } + return true; } =20 /* @@ -3934,9 +3922,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t = insn) static void disas_ldst(DisasContext *s, uint32_t insn) { switch (extract32(insn, 24, 6)) { - case 0x0d: /* AdvSIMD load/store single structure */ - disas_ldst_single_struct(s, insn); - break; case 0x19: if (extract32(insn, 21, 1) !=3D 0) { disas_ldst_tag(s, insn); --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185262; cv=none; d=zohomail.com; s=zohoarc; b=XtAA3uy1U7leWOVMohYMvRNeKGiOJdgBB6vidf7fguSwaXw17lxFsEWwWbvGQLDmL5NHZKliRn+0QPwHxizOCJxeiqesh9AvurZh8+q+69qlqmmQA7UWNgv1j3kR+Uw625Eqb00y3L3OjZNKjGJz9n++xYdIJ+X4ASSdVPjKlho= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185262; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=s7f4L7r373uq6rq/Tk+eAX0siIZ8RlL33Pszb/2D3F0=; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184967; x=1689776967; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=s7f4L7r373uq6rq/Tk+eAX0siIZ8RlL33Pszb/2D3F0=; b=uhoYP+diqotCqbkKNcdQzXyOyafgrXSjmJUDj67068ripCVDU0BpvFaD8KUaIiyScP hrVSsnxhOrnkEltsWGAVJWqWysZ7L7mXnXG+yBmWfDAyIMHoIAtX+gnKjtXoPuskmWGO X/06dmfSUfBVbc7gabfVjE2Db2RTKjvQzxwrZCb/+mPAN3xGH33u/drrnmeqB2RZKiaw tP9853oYvhzelUojimxBxEXrea8Ye8wVZ4iCiWFDjv00oefKAbfFBEkhWGVxGyubx/KT GBnta9MZq7QQszpzEZpfqQ/AlEbdJiTc7G6ZYJlFAXi8P7jxQqpV0iiEaQtQXwkdTk5y tFXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184967; x=1689776967; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=s7f4L7r373uq6rq/Tk+eAX0siIZ8RlL33Pszb/2D3F0=; b=e/5AFA9evJpShAlmGxiLSNfU0TNMYW4b4SdnOT/rk3zaUXn1vz8NAoKkx7aZMMfD4C 9dSS652KS4mjo8W7buXTtDHpSt/gUwq+LOPyDoHooApekSuAMcAZeXa7iRDh34CPh5i9 jl/vtptIZxoz3hHyBxzV07kBsYmtDprdVGxeM7Wo/n4ojN5j2tR4joVeHQDRYcGqtcOf puKR28PFB4UEgsQAYw5O0jkydt9F0oKDzB643j6X1LjQ6QCYBHJ1HdXWYJunzravzlOi bmPwVlfR1Z5rOK85lVjhnDOEAE+wtuR89qxKggyR7LuoF7zlugztXJ9vGvcBmPJZxw4T 4E4w== X-Gm-Message-State: AC+VfDymx6Ny8lH20ydN4lJIfEkoTZFO3yvAMpwmjs1w9wbIziCY7YhQ 0OnFDgySFB70dcJv+YaWsk8OYNPP9OPkp/Ve9uo= X-Google-Smtp-Source: ACHHUZ4sHn0J0g2HPhvFaQVWgiXITzKoqWoG3mtT9YzL2zVe3lonpx0QCXCw8ymR6WSqj3Yll1dGug== X-Received: by 2002:a05:600c:b44:b0:3f9:6d10:eb0e with SMTP id k4-20020a05600c0b4400b003f96d10eb0emr2570444wmr.40.1687184966769; Mon, 19 Jun 2023 07:29:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/33] target/arm: Convert load/store tags insns to decodetree Date: Mon, 19 Jun 2023 15:29:04 +0100 Message-Id: <20230619142914.963184-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185263573100009 Content-Type: text/plain; charset="utf-8" Convert the instructions in the load/store memory tags instruction group to decodetree. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230602155223.2040685-21-peter.maydell@linaro.org --- target/arm/tcg/a64.decode | 25 +++ target/arm/tcg/translate-a64.c | 360 ++++++++++++++++----------------- 2 files changed, 199 insertions(+), 186 deletions(-) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 4ffdc91865f..ef64a3f9cba 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -528,3 +528,28 @@ LD_single 0 . 001101 . 1 . ..... 10 . 001 ...= .. ..... @ldst_single_d =20 # Replicating load case LD_single_repl 0 q:1 001101 p:1 1 . rm:5 11 . 0 scale:2 rn:5 rt:5 selem= =3D%ldst_single_selem + +%tag_offset 12:s9 !function=3Dscale_by_log2_tag_granule +&ldst_tag rn rt imm p w +@ldst_tag ........ .. . ......... .. rn:5 rt:5 &ldst_tag imm=3D%tag_= offset +@ldst_tag_mult ........ .. . 000000000 .. rn:5 rt:5 &ldst_tag imm=3D0 + +STZGM 11011001 00 1 ......... 00 ..... ..... @ldst_tag_mult p=3D= 0 w=3D0 +STG 11011001 00 1 ......... 01 ..... ..... @ldst_tag p=3D1 w= =3D1 +STG 11011001 00 1 ......... 10 ..... ..... @ldst_tag p=3D0 w= =3D0 +STG 11011001 00 1 ......... 11 ..... ..... @ldst_tag p=3D0 w= =3D1 + +LDG 11011001 01 1 ......... 00 ..... ..... @ldst_tag p=3D0 w= =3D0 +STZG 11011001 01 1 ......... 01 ..... ..... @ldst_tag p=3D1 w= =3D1 +STZG 11011001 01 1 ......... 10 ..... ..... @ldst_tag p=3D0 w= =3D0 +STZG 11011001 01 1 ......... 11 ..... ..... @ldst_tag p=3D0 w= =3D1 + +STGM 11011001 10 1 ......... 00 ..... ..... @ldst_tag_mult p=3D= 0 w=3D0 +ST2G 11011001 10 1 ......... 01 ..... ..... @ldst_tag p=3D1 w= =3D1 +ST2G 11011001 10 1 ......... 10 ..... ..... @ldst_tag p=3D0 w= =3D0 +ST2G 11011001 10 1 ......... 11 ..... ..... @ldst_tag p=3D0 w= =3D1 + +LDGM 11011001 11 1 ......... 00 ..... ..... @ldst_tag_mult p=3D= 0 w=3D0 +STZ2G 11011001 11 1 ......... 01 ..... ..... @ldst_tag p=3D1 w= =3D1 +STZ2G 11011001 11 1 ......... 10 ..... ..... @ldst_tag p=3D0 w= =3D0 +STZ2G 11011001 11 1 ......... 11 ..... ..... @ldst_tag p=3D0 w= =3D1 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index f9a76141eb6..3baab6aa602 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -62,6 +62,12 @@ static int uimm_scaled(DisasContext *s, int x) return imm << scale; } =20 +/* For load/store memory tags: scale offset by LOG2_TAG_GRANULE */ +static int scale_by_log2_tag_granule(DisasContext *s, int x) +{ + return x << LOG2_TAG_GRANULE; +} + /* * Include the generated decoders. */ @@ -3709,185 +3715,184 @@ static bool trans_LD_single_repl(DisasContext *s,= arg_LD_single_repl *a) return true; } =20 -/* - * Load/Store memory tags - * - * 31 30 29 24 22 21 12 10 5 0 - * +-----+-------------+-----+---+------+-----+------+------+ - * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt | - * +-----+-------------+-----+---+------+-----+------+------+ - */ -static void disas_ldst_tag(DisasContext *s, uint32_t insn) +static bool trans_STZGM(DisasContext *s, arg_ldst_tag *a) { - int rt =3D extract32(insn, 0, 5); - int rn =3D extract32(insn, 5, 5); - uint64_t offset =3D sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; - int op2 =3D extract32(insn, 10, 2); - int op1 =3D extract32(insn, 22, 2); - bool is_load =3D false, is_pair =3D false, is_zero =3D false, is_mult = =3D false; - int index =3D 0; TCGv_i64 addr, clean_addr, tcg_rt; + int size =3D 4 << s->dcz_blocksize; =20 - /* We checked insn bits [29:24,21] in the caller. */ - if (extract32(insn, 30, 2) !=3D 3) { - goto do_unallocated; + if (!dc_isar_feature(aa64_mte, s)) { + return false; + } + if (s->current_el =3D=3D 0) { + return false; } =20 - /* - * @index is a tri-state variable which has 3 states: - * < 0 : post-index, writeback - * =3D 0 : signed offset - * > 0 : pre-index, writeback - */ - switch (op1) { - case 0: - if (op2 !=3D 0) { - /* STG */ - index =3D op2 - 2; - } else { - /* STZGM */ - if (s->current_el =3D=3D 0 || offset !=3D 0) { - goto do_unallocated; - } - is_mult =3D is_zero =3D true; - } - break; - case 1: - if (op2 !=3D 0) { - /* STZG */ - is_zero =3D true; - index =3D op2 - 2; - } else { - /* LDG */ - is_load =3D true; - } - break; - case 2: - if (op2 !=3D 0) { - /* ST2G */ - is_pair =3D true; - index =3D op2 - 2; - } else { - /* STGM */ - if (s->current_el =3D=3D 0 || offset !=3D 0) { - goto do_unallocated; - } - is_mult =3D true; - } - break; - case 3: - if (op2 !=3D 0) { - /* STZ2G */ - is_pair =3D is_zero =3D true; - index =3D op2 - 2; - } else { - /* LDGM */ - if (s->current_el =3D=3D 0 || offset !=3D 0) { - goto do_unallocated; - } - is_mult =3D is_load =3D true; - } - break; - - default: - do_unallocated: - unallocated_encoding(s); - return; - } - - if (is_mult - ? !dc_isar_feature(aa64_mte, s) - : !dc_isar_feature(aa64_mte_insn_reg, s)) { - goto do_unallocated; - } - - if (rn =3D=3D 31) { + if (a->rn =3D=3D 31) { gen_check_sp_alignment(s); } =20 - addr =3D read_cpu_reg_sp(s, rn, true); - if (index >=3D 0) { + addr =3D read_cpu_reg_sp(s, a->rn, true); + tcg_gen_addi_i64(addr, addr, a->imm); + tcg_rt =3D cpu_reg(s, a->rt); + + if (s->ata) { + gen_helper_stzgm_tags(cpu_env, addr, tcg_rt); + } + /* + * The non-tags portion of STZGM is mostly like DC_ZVA, + * except the alignment happens before the access. + */ + clean_addr =3D clean_data_tbi(s, addr); + tcg_gen_andi_i64(clean_addr, clean_addr, -size); + gen_helper_dc_zva(cpu_env, clean_addr); + return true; +} + +static bool trans_STGM(DisasContext *s, arg_ldst_tag *a) +{ + TCGv_i64 addr, clean_addr, tcg_rt; + + if (!dc_isar_feature(aa64_mte, s)) { + return false; + } + if (s->current_el =3D=3D 0) { + return false; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + addr =3D read_cpu_reg_sp(s, a->rn, true); + tcg_gen_addi_i64(addr, addr, a->imm); + tcg_rt =3D cpu_reg(s, a->rt); + + if (s->ata) { + gen_helper_stgm(cpu_env, addr, tcg_rt); + } else { + MMUAccessType acc =3D MMU_DATA_STORE; + int size =3D 4 << GMID_EL1_BS; + + clean_addr =3D clean_data_tbi(s, addr); + tcg_gen_andi_i64(clean_addr, clean_addr, -size); + gen_probe_access(s, clean_addr, acc, size); + } + return true; +} + +static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a) +{ + TCGv_i64 addr, clean_addr, tcg_rt; + + if (!dc_isar_feature(aa64_mte, s)) { + return false; + } + if (s->current_el =3D=3D 0) { + return false; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + addr =3D read_cpu_reg_sp(s, a->rn, true); + tcg_gen_addi_i64(addr, addr, a->imm); + tcg_rt =3D cpu_reg(s, a->rt); + + if (s->ata) { + gen_helper_ldgm(tcg_rt, cpu_env, addr); + } else { + MMUAccessType acc =3D MMU_DATA_LOAD; + int size =3D 4 << GMID_EL1_BS; + + clean_addr =3D clean_data_tbi(s, addr); + tcg_gen_andi_i64(clean_addr, clean_addr, -size); + gen_probe_access(s, clean_addr, acc, size); + /* The result tags are zeros. */ + tcg_gen_movi_i64(tcg_rt, 0); + } + return true; +} + +static bool trans_LDG(DisasContext *s, arg_ldst_tag *a) +{ + TCGv_i64 addr, clean_addr, tcg_rt; + + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { + return false; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + addr =3D read_cpu_reg_sp(s, a->rn, true); + if (!a->p) { /* pre-index or signed offset */ - tcg_gen_addi_i64(addr, addr, offset); + tcg_gen_addi_i64(addr, addr, a->imm); } =20 - if (is_mult) { - tcg_rt =3D cpu_reg(s, rt); + tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); + tcg_rt =3D cpu_reg(s, a->rt); + if (s->ata) { + gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); + } else { + /* + * Tag access disabled: we must check for aborts on the load + * load from [rn+offset], and then insert a 0 tag into rt. + */ + clean_addr =3D clean_data_tbi(s, addr); + gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8); + gen_address_with_allocation_tag0(tcg_rt, tcg_rt); + } =20 - if (is_zero) { - int size =3D 4 << s->dcz_blocksize; - - if (s->ata) { - gen_helper_stzgm_tags(cpu_env, addr, tcg_rt); - } - /* - * The non-tags portion of STZGM is mostly like DC_ZVA, - * except the alignment happens before the access. - */ - clean_addr =3D clean_data_tbi(s, addr); - tcg_gen_andi_i64(clean_addr, clean_addr, -size); - gen_helper_dc_zva(cpu_env, clean_addr); - } else if (s->ata) { - if (is_load) { - gen_helper_ldgm(tcg_rt, cpu_env, addr); - } else { - gen_helper_stgm(cpu_env, addr, tcg_rt); - } - } else { - MMUAccessType acc =3D is_load ? MMU_DATA_LOAD : MMU_DATA_STORE; - int size =3D 4 << GMID_EL1_BS; - - clean_addr =3D clean_data_tbi(s, addr); - tcg_gen_andi_i64(clean_addr, clean_addr, -size); - gen_probe_access(s, clean_addr, acc, size); - - if (is_load) { - /* The result tags are zeros. */ - tcg_gen_movi_i64(tcg_rt, 0); - } + if (a->w) { + /* pre-index or post-index */ + if (a->p) { + /* post-index */ + tcg_gen_addi_i64(addr, addr, a->imm); } - return; + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), addr); + } + return true; +} + +static bool do_STG(DisasContext *s, arg_ldst_tag *a, bool is_zero, bool is= _pair) +{ + TCGv_i64 addr, tcg_rt; + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); } =20 - if (is_load) { - tcg_gen_andi_i64(addr, addr, -TAG_GRANULE); - tcg_rt =3D cpu_reg(s, rt); - if (s->ata) { - gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt); + addr =3D read_cpu_reg_sp(s, a->rn, true); + if (!a->p) { + /* pre-index or signed offset */ + tcg_gen_addi_i64(addr, addr, a->imm); + } + tcg_rt =3D cpu_reg_sp(s, a->rt); + if (!s->ata) { + /* + * For STG and ST2G, we need to check alignment and probe memory. + * TODO: For STZG and STZ2G, we could rely on the stores below, + * at least for system mode; user-only won't enforce alignment. + */ + if (is_pair) { + gen_helper_st2g_stub(cpu_env, addr); } else { - /* - * Tag access disabled: we must check for aborts on the load - * load from [rn+offset], and then insert a 0 tag into rt. - */ - clean_addr =3D clean_data_tbi(s, addr); - gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8); - gen_address_with_allocation_tag0(tcg_rt, tcg_rt); + gen_helper_stg_stub(cpu_env, addr); + } + } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { + if (is_pair) { + gen_helper_st2g_parallel(cpu_env, addr, tcg_rt); + } else { + gen_helper_stg_parallel(cpu_env, addr, tcg_rt); } } else { - tcg_rt =3D cpu_reg_sp(s, rt); - if (!s->ata) { - /* - * For STG and ST2G, we need to check alignment and probe memo= ry. - * TODO: For STZG and STZ2G, we could rely on the stores below, - * at least for system mode; user-only won't enforce alignment. - */ - if (is_pair) { - gen_helper_st2g_stub(cpu_env, addr); - } else { - gen_helper_stg_stub(cpu_env, addr); - } - } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - if (is_pair) { - gen_helper_st2g_parallel(cpu_env, addr, tcg_rt); - } else { - gen_helper_stg_parallel(cpu_env, addr, tcg_rt); - } + if (is_pair) { + gen_helper_st2g(cpu_env, addr, tcg_rt); } else { - if (is_pair) { - gen_helper_st2g(cpu_env, addr, tcg_rt); - } else { - gen_helper_stg(cpu_env, addr, tcg_rt); - } + gen_helper_stg(cpu_env, addr, tcg_rt); } } =20 @@ -3908,32 +3913,21 @@ static void disas_ldst_tag(DisasContext *s, uint32_= t insn) } } =20 - if (index !=3D 0) { + if (a->w) { /* pre-index or post-index */ - if (index < 0) { + if (a->p) { /* post-index */ - tcg_gen_addi_i64(addr, addr, offset); + tcg_gen_addi_i64(addr, addr, a->imm); } - tcg_gen_mov_i64(cpu_reg_sp(s, rn), addr); + tcg_gen_mov_i64(cpu_reg_sp(s, a->rn), addr); } + return true; } =20 -/* Loads and stores */ -static void disas_ldst(DisasContext *s, uint32_t insn) -{ - switch (extract32(insn, 24, 6)) { - case 0x19: - if (extract32(insn, 21, 1) !=3D 0) { - disas_ldst_tag(s, insn); - } else { - unallocated_encoding(s); - } - break; - default: - unallocated_encoding(s); - break; - } -} +TRANS_FEAT(STG, aa64_mte_insn_reg, do_STG, a, false, false) +TRANS_FEAT(STZG, aa64_mte_insn_reg, do_STG, a, true, false) +TRANS_FEAT(ST2G, aa64_mte_insn_reg, do_STG, a, false, true) +TRANS_FEAT(STZ2G, aa64_mte_insn_reg, do_STG, a, true, true) =20 typedef void ArithTwoOp(TCGv_i64, TCGv_i64, TCGv_i64); =20 @@ -13829,12 +13823,6 @@ static bool btype_destination_ok(uint32_t insn, bo= ol bt, int btype) static void disas_a64_legacy(DisasContext *s, uint32_t insn) { switch (extract32(insn, 25, 4)) { - case 0x4: - case 0x6: - case 0xc: - case 0xe: /* Loads and stores */ - disas_ldst(s, insn); - break; case 0x5: case 0xd: /* Data processing - register */ disas_data_proc_reg(s, insn); --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184967; x=1689776967; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=JqZ8k1zAHq1ZWAnTPJViyRqU+IGDsCc34HFn4gFwiZ4=; b=gSbpZbTP0baG6wqKoeRF5IHGfGm4MCDu6iYXP9C5t69C4/t60m9gS3ehGueDBnMX0x 1zHEQBAvbwAqxgawAvqs8hZKlxWl7Cv9JBAhlCuwFK4kOr5P1tsKxaeRnDGPvmfJsBi7 vNLL+cILPaW8kSxRODLtWkriAjVESjBwGE0uqAMH3Cg0O8rC15kEUKpRNq5QB4dySj/4 DiU3bWzTr/nAEDHW0Zb00MN8r4zIPXM2j4vzEMvvyra0UhmYC6kgha6pw9BkCUHeBt7T Z8hEAVnQ66phAy80UtF4idDzySQvNjBswFtIk6NZAubwFSR1Ml+Z4BX9e5p2IY530/+M E9ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184967; x=1689776967; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JqZ8k1zAHq1ZWAnTPJViyRqU+IGDsCc34HFn4gFwiZ4=; b=ANZn+LQvUFtwMw+n8BGEgVFOy029R1VkevgGjd5BdLkL1kIgMn2KdfKtGUlPne5wfs 5ECt/BoNVlTAzWS8phDJSzFBpphZ8fUlY7DhTLGIPdOblfQTD0PwgRimwEZx78nBBVKH RhtCqnRDOdj8vx2Gw2oSmfTOijiGoy+apDqxdYfrnYW2O36w/+yoAnWjWioCe6jOULOi gq5A5g+6qj2PuZncxLYa9vqSZlhJ0Hvk7+bpR/T3orC1BvUgM5YQ3KMtMO0zurFvbJdQ 19OgFGu8Dv2iMlePsrmM01MlSgVcOnyYulfXdvScm8pJ4OnXMcDNxqnn/dJPVo/82ayH ejyw== X-Gm-Message-State: AC+VfDwJUHLdIFfsg7z7Ru1s9pcD1z3UhqdFrqW1Wa4Nl48BEswOvlvR z6oXfLh+9uxE4qSwkh4g9WhX+oRgvjcP273JoiQ= X-Google-Smtp-Source: ACHHUZ70lhxB9h7f6mamtvVOmyylqolOwFGhVX4Pe1DDJc3Xq6PGZoNgX7kU51IE44uQfc3H/dx9dA== X-Received: by 2002:a19:e057:0:b0:4f8:7551:7485 with SMTP id g23-20020a19e057000000b004f875517485mr945522lfj.5.1687184967203; Mon, 19 Jun 2023 07:29:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/33] hw/intc/allwinner-a10-pic: Handle IRQ levels other than 0 or 1 Date: Mon, 19 Jun 2023 15:29:05 +0100 Message-Id: <20230619142914.963184-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185387293100009 In commit 2c5fa0778c3b430 we fixed an endianness bug in the Allwinner A10 PIC model; however in the process we introduced a regression. This is because the old code was robust against the incoming 'level' argument being something other than 0 or 1, whereas the new code was not. In particular, the allwinner-sdhost code treats its IRQ line as 0-vs-non-0 rather than 0-vs-1, so when the SD controller set its IRQ line for any reason other than transmit the interrupt controller would ignore it. The observed effect was a guest timeout when rebooting the guest kernel. Handle level values other than 0 or 1, to restore the old behaviour. Fixes: 2c5fa0778c3b430 ("hw/intc/allwinner-a10-pic: Don't use set_bit()/cle= ar_bit()") Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Guenter Roeck Message-id: 20230606104609.3692557-2-peter.maydell@linaro.org --- hw/intc/allwinner-a10-pic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c index 4875e68ba6a..d0bf8d545ba 100644 --- a/hw/intc/allwinner-a10-pic.c +++ b/hw/intc/allwinner-a10-pic.c @@ -51,7 +51,7 @@ static void aw_a10_pic_set_irq(void *opaque, int irq, int= level) AwA10PICState *s =3D opaque; uint32_t *pending_reg =3D &s->irq_pending[irq / 32]; =20 - *pending_reg =3D deposit32(*pending_reg, irq % 32, 1, level); + *pending_reg =3D deposit32(*pending_reg, irq % 32, 1, !!level); aw_a10_pic_update(s); } =20 --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185191; cv=none; d=zohomail.com; s=zohoarc; b=Kpu/zAAu8wTkKFYOtJX/tGDkHtGbb4ZXgCCJsDzUNEEWS1pfxuP65lVq0EIdK474qc+Wl0Bqvz1ha3Y0HdcPavBDl8YuH/ie4ehX/USKPhILtwGwFmhqPdngEXaiLq+7RHrf/03g0BaWg/xDZjcvKIjgAgzclDdPUsy/FcFuqWI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185191; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7NGVfS5DtDEvRzAeh2tIxqusOp/nBTZ4y0VaCfreOUI=; b=Yb7oclxQ4tWRhVhN3Ysx1gl3LC0t9SeHml6K2BWGiN7fB0BSuM995bLZS1KIRCO3r3RkZoxk5ZE17cImY9UjHCcfs6gjdNECtVo2FQpMxxMLttPplMZ/4mB/MTCOtbrOFm+hKn6tdmD2E38fUHJjvABZuKE5bweUh/XhOX80Fzg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687185191708545.3778142000713; Mon, 19 Jun 2023 07:33:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBFtT-0001dJ-8c; Mon, 19 Jun 2023 10:30:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBFsp-0000eE-KJ for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:31 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBFsn-0002Fw-3T for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:31 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-3f8fe9dc27aso22162115e9.3 for ; Mon, 19 Jun 2023 07:29:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184968; x=1689776968; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=7NGVfS5DtDEvRzAeh2tIxqusOp/nBTZ4y0VaCfreOUI=; b=TCecmzQ4uI3qKX4AN5uhqRdKZG+kTZf30LuPRxPDu0EUVIHu8xrBCIzDfZSOcSmu8A dif7ri655s3d/7jRapMFbFZNTazLVW3GgNvPy2mfUfLBx5u/s78QWwQGDG28fthjymOl XvjuQ0vmvu2RBg3WkUAGTszn7FHLKnYKqOJdX8d2anUxvLfJnzuox5rbTExjq0OpikIi 7fBUVIm8vU6HxUsms+UP9xKSrnCRIuRzz0CU1CF6bXWMBul2DJmouX/eXuGuTmaJHIoL ImxKH0PUlLA5fWXWKahH5vkY8GUfI/0SoUZEe8/wicf7zGpTJv8Z3LnNA3y8e+CDkF0d 6Ljw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184968; x=1689776968; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7NGVfS5DtDEvRzAeh2tIxqusOp/nBTZ4y0VaCfreOUI=; b=SdQWA011HnIykvJdt24paOogfOQAd2Tue5jV3pebJlsXQL2tltT4uCyJRTexQT1Ykb dgENguSgI4t2UB8o2xtBJXaAZGk5BIaDwFesdFFHZ+g+JeH9NP8XlHu2LmGHCQmHZUO3 nzZg7663ysDCjQ1FdXXZNLJSfRUZOB/fJxzYzrJB07hQ1vzSD62ldsH1OsYyEcHZzGjx zyKLgm9teiycoMppXl/Ip4NcRII8dECabmHp1FmsXDkP4PMt8L98ju2WOkaSHL1lxpV5 wZwhNAPzBKgkgSIpclNRxnH6z0tmxYpfeBTFCBeX00AGCtdXGnLhrMl+JPCGMNk5MCWi y9FQ== X-Gm-Message-State: AC+VfDwRae3Ope1d5mdDw/2O09Jt/Tn6ypc3+sHXkhZ52d3FhuZNQswD gvxD7WK26YuO4VMkfdUhtd+/tZOoIM5EGO7R5ec= X-Google-Smtp-Source: ACHHUZ5lcOOztqfqkWW1+Te0Lxs2aZbO7/4c0EEbuh4VXtDfQNbZe9cIo/UKQ8HqcIs5kKaMWzJ5Hg== X-Received: by 2002:a5d:6844:0:b0:30f:c22f:e901 with SMTP id o4-20020a5d6844000000b0030fc22fe901mr5526912wrw.26.1687184967734; Mon, 19 Jun 2023 07:29:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/33] hw/sd/allwinner-sdhost: Don't send non-boolean IRQ line levels Date: Mon, 19 Jun 2023 15:29:06 +0100 Message-Id: <20230619142914.963184-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185193198100011 QEMU allows qemu_irq lines to transfer arbitrary integers. However the convention is that for a simple IRQ line the values transferred are always 0 and 1. The A10 SD controller device instead assumes a 0-vs-non-0 convention, which happens to work with the interrupt controller it is wired up to. Coerce the value to boolean to follow our usual convention. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Guenter Roeck Message-id: 20230606104609.3692557-3-peter.maydell@linaro.org --- hw/sd/allwinner-sdhost.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c index 286e0095098..1a576d62ae2 100644 --- a/hw/sd/allwinner-sdhost.c +++ b/hw/sd/allwinner-sdhost.c @@ -193,7 +193,7 @@ static void allwinner_sdhost_update_irq(AwSdHostState *= s) } =20 trace_allwinner_sdhost_update_irq(irq); - qemu_set_irq(s->irq, irq); + qemu_set_irq(s->irq, !!irq); } =20 static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s, --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185208; cv=none; d=zohomail.com; s=zohoarc; b=XJ+BCgTDQCxHYhzzkyQHGF717+AfzYILyCUlLaacmnerz3wwiOTooA/PP/aQ0ANQVRKGadhXIOOJjD82p9dEExD19rOYTgDp8x7A/OUwXWoeVDwgy6hKYogeRC38q70AGPXrk6MqJPCILx+nuu9IpJ5i7gh2xpYFgo6GdRK+soE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185208; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=y/asvDbpuEPmw7wglRXtLAabLlYBYvk+Qg+LSrFniF4=; b=ls9Nz4ls8bqM4KuDqUeqlhcmgxqEu/spdxwZHbDqiTQSJDa/FeDplxS/JCdw49A/gcPgoIQ7eWKBxGcGq1zsCu8JyL9GmZtEuD9xZRCrtZr8R/sIhIop1UmFdY9pJjPycE/AuKQuXFFpixzU23OvtS2Ov5YQTOGvpSkyT1Z8R3E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687185208468655.6779880363989; Mon, 19 Jun 2023 07:33:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBFtU-0001iB-DF; Mon, 19 Jun 2023 10:30:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBFss-0000ed-Ld for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:36 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBFsn-0002GH-L2 for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:32 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-3f906d8fca3so19973225e9.1 for ; Mon, 19 Jun 2023 07:29:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184968; x=1689776968; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=y/asvDbpuEPmw7wglRXtLAabLlYBYvk+Qg+LSrFniF4=; b=MTdNamwBkWtM0q8JofFLOkkEltIJOiuQSp86tZ2ehokJrFV8OVWBuPEJV04VPiY0+z F28fWWjKuG28o8esZWvxiQZ6IpYaTjNTy07XbZQVNZDAgzYR05vrdNOEQk9oEf3rveu3 HWxT7B7qR9/80iQpHWAdYaX432Hjd0dbxKMwV7vsrgDUMrRhnyxgMnxY2MwajvL309hm oyZmwfCBP+xKq6TNgXulLom9E8GZwZ3wdGRiEaDi7CaQ3Qs8HC7X5+JXj+0Iy+kL68Uq 4Dj/fbG56OxPkjJ9ktkcqcZ4iJMvW3Nh0lwrrabPvoTyaDEHq1pdUwVgizOIKMfh20bW 7kyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184968; x=1689776968; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y/asvDbpuEPmw7wglRXtLAabLlYBYvk+Qg+LSrFniF4=; b=lMPm1pd5DnOso78YllYbgrG0toSICClgymTP4sloKmdzzlW77ou7HBe83t/Kd1TwMd Li6SmcU8qkUyfrygkY0ZExhgFhTZU+corGtw/enpylkMjvtbL7w/Jj8FFLqmJnJjldqU +mpvWi95yT4oeMzyYjhOjUvVtsz24apM1fNi0u934DuP2R/RsGMd7KxsFCn5lVZWy9nB nKi7Ak3d+jBp7pIAlhfKPiERrtnkBEbYBbhMDbQbBzxd86/s2E3vBKyNXsOTHe66kvFe vs8s3yIPx6eXMjgYkzL2KY6OIzsOjNVRZFKg68dEwLF0RhfhDIm1wU0SvpUm/PhrSKUk 8s8w== X-Gm-Message-State: AC+VfDyR3xe3dS6rLbGHKwKiziv/k/mf6EtmWO1A/WetDbwkF3Q7LBPt zTHbN8MTbM62IaS8WZePqmNzLo7bIFtXutuzh5k= X-Google-Smtp-Source: ACHHUZ5gAI5DKCTD+cxDIuou4d/eGWAXkhp1hwGBJgNWrauawfmwBrhxM5fgMXSHu2OA0Bhs+psaoA== X-Received: by 2002:a05:600c:22c2:b0:3f9:b19c:aab4 with SMTP id 2-20020a05600c22c200b003f9b19caab4mr1646678wmg.6.1687184968171; Mon, 19 Jun 2023 07:29:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/33] hw/timer/nrf51_timer: Don't lose time when timer is queried in tight loop Date: Mon, 19 Jun 2023 15:29:07 +0100 Message-Id: <20230619142914.963184-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185209228100003 Content-Type: text/plain; charset="utf-8" The nrf51_timer has a free-running counter which we implement using the pattern of using two fields (update_counter_ns, counter) to track the last point at which we calculated the counter value, and the counter value at that time. Then we can find the current counter value by converting the difference in wall-clock time between then and now to a tick count that we need to add to the counter value. Unfortunately the nrf51_timer's implementation of this has a bug which means it loses time every time update_counter() is called. After updating s->counter it always sets s->update_counter_ns to 'now', even though the actual point when s->counter hit the new value will be some point in the past (half a tick, say). In the worst case (guest code in a tight loop reading the counter, icount mode) the counter is continually queried less than a tick after it was last read, so s->counter never advances but s->update_counter_ns does, and the guest never makes forward progress. The fix for this is to only advance update_counter_ns to the timestamp of the last tick, not all the way to 'now'. (This is the pattern used in hw/misc/mps2-fpgaio.c's counter.) Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Joel Stanley Message-id: 20230606134917.3782215-1-peter.maydell@linaro.org --- hw/timer/nrf51_timer.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c index 42be79c7363..50c6772383e 100644 --- a/hw/timer/nrf51_timer.c +++ b/hw/timer/nrf51_timer.c @@ -45,7 +45,12 @@ static uint32_t update_counter(NRF51TimerState *s, int64= _t now) uint32_t ticks =3D ns_to_ticks(s, now - s->update_counter_ns); =20 s->counter =3D (s->counter + ticks) % BIT(bitwidths[s->bitmode]); - s->update_counter_ns =3D now; + /* + * Only advance the sync time to the timestamp of the last tick, + * not all the way to 'now', so we don't lose time if we do + * multiple resyncs in a single tick. + */ + s->update_counter_ns +=3D ticks_to_ns(s, ticks); return ticks; } =20 --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185191; cv=none; d=zohomail.com; s=zohoarc; b=IQnPuS109MInHJh3j+UwQJtqXeN+MRFTMe4Mw8+AwHEYk89a4drA0ntEXrR0eHjtB7abDcEur3vd9hLajXwa6QvbvRSfW4Jn6RbqKUWEdbUodMkk7IsQZZlapkc82+lvBzwyGUBegsucvWa+CEfsZy76uaVPMeMbis/nU/P6De4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185191; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FyPzDa94K3AZr/hbkz0BKSLwEV+wo2bmArnAzAqZpzg=; b=P1ECoQdT8SRYLVEyCcVc59vpfn93hqJJjExQo0eaWnjn+MoXQa5R/lBEkR2X7YciW4bVJExwq95ckc+l9NtrPmrMUCOScz0ZuXTPsDeQ6c83XpuYc4cg16EVS6ajqA1IqJ6wxcGN92sP5T5RAVyYfRqsQAwioX6U1hVTVHN9Kd4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687185191979278.2144305307494; Mon, 19 Jun 2023 07:33:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBFtU-0001ib-Ia; Mon, 19 Jun 2023 10:30:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBFsq-0000eb-TC for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:34 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBFsp-0002GY-Ay for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:32 -0400 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3f9b258f3a2so8621705e9.0 for ; Mon, 19 Jun 2023 07:29:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185192779100007 Content-Type: text/plain; charset="utf-8" From: Marcin Juszkiewicz Signed-off-by: Marcin Juszkiewicz Reviewed-by: Thomas Huth Message-id: 20230607092112.655098-1-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 2159de3ce65..7de17d1e8c3 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -268,6 +268,7 @@ config SBSA_REF select PL061 # GPIO select USB_EHCI_SYSBUS select WDT_SBSA + select BOCHS_DISPLAY =20 config SABRELITE bool --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184969; x=1689776969; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=MmGNmH8MdwxGE6tW13V4FAIDv1rJBSbOYavkF0+ToBY=; b=xwGgUekKwmHsgQwM+wLcF4p3ZuRMqDeLXnHUq/qhBEy0LLE7JBb6ZIVKMDFiWGlZYt 3jP1wDjiyfexzrmYC+RrLh9yDptfwAcAGYqQ15OkSdKnE463IDlGh2SpBzEZWtUhLleY 8iKe+3vC6u+veiHvYr278fmkoEJwLF16x5rULGLck5kWw1V+smElk35x3I/TILh1+gAK n1Q/BE+J1Avl76eaEeTAFbwROIG52AvFHxAid3JhTMKFz8VMWKm1+qpUSinYFh+Nykol h3pIpoT6cwD2pECRKvt98F8S/MXQ/FaSP9bVs0xKXr49htxMemi7/dEt8cL2JF7ft47k Q0yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184969; x=1689776969; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MmGNmH8MdwxGE6tW13V4FAIDv1rJBSbOYavkF0+ToBY=; b=KmwLCnsNfe8tQlnvlbdXi0+0VboJcQPl/V5cVeANF9XoOnOyLNTyJkrBDN991s7tHB 0ayv877RgOvB0SbZO8rMLe8a4Vi5277/ArrYSxYgKuB8AUUqALZfGXsPbBuiEYZL75L1 KRuZpm2tOtoyoxYEHmZ8ec8xevnH6Pk/oEYEDnkGXs6UwpYjUXkd612ctrstV0EDU8pI BMZAgjAEllZJhGsx2g5cckX5ysjhZ4U4fd3ZzO2XtwAqh2UtwkE7QCtAXEXR6fbiZiRe g9+SH1kuuEFYRw21hW7YWwBYDU0NT7fu30sriAyH82Szyc3MPCio21xnfm/xEUwMNnD1 g/8g== X-Gm-Message-State: AC+VfDxLMHmzk3NiCHBerD1h2aZmqkOdbLvUVtomtmuqYZw19WTM3LAi B4BCG8pO8kwCMEsfzuT+TmhSxRl5BGPKfywgILM= X-Google-Smtp-Source: ACHHUZ6ZP+lsSzDGEEBPzEwwuz3tLwkDv127ahGD9L7SfeFda5dUzdaSONaYPj3vozPC08DsaXmIkw== X-Received: by 2002:a1c:7514:0:b0:3f8:fe2a:25c2 with SMTP id o20-20020a1c7514000000b003f8fe2a25c2mr5644661wmc.38.1687184968944; Mon, 19 Jun 2023 07:29:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/33] imx_serial: set wake bit when we receive a data byte Date: Mon, 19 Jun 2023 15:29:09 +0100 Message-Id: <20230619142914.963184-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185281692100001 From: Martin Kaiser The Linux kernel added a flood check for RX data recently in commit 496a4471b7c3 ("serial: imx: work-around for hardware RX flood"). This check uses the wake bit in the UART status register 2. The wake bit indicates that the receiver detected a start bit on the RX line. If the kernel sees a number of RX interrupts without the wake bit being set, it treats this as spurious data and resets the UART port. imx_serial does never set the wake bit and triggers the kernel's flood check. This patch adds support for the wake bit. wake is set when we receive a new character (it's not set for break events). It seems that wake is cleared by the kernel driver, the hardware does not have to clear it automatically after data was read. The wake bit can be configured as an interrupt source. Support this mechanism as well. Co-developed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Martin Kaiser Signed-off-by: Peter Maydell --- include/hw/char/imx_serial.h | 1 + hw/char/imx_serial.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h index 91c9894ad55..b823f945195 100644 --- a/include/hw/char/imx_serial.h +++ b/include/hw/char/imx_serial.h @@ -71,6 +71,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL) =20 #define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */ #define UCR4_TCEN BIT(3) /* TX complete interrupt enable */ +#define UCR4_WKEN BIT(7) /* WAKE interrupt enable */ =20 #define UTS1_TXEMPTY (1<<6) #define UTS1_RXEMPTY (1<<5) diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index ee1375e26d7..1b75a895881 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -80,7 +80,7 @@ static void imx_update(IMXSerialState *s) * TCEN and TXDC are both bit 3 * RDR and DREN are both bit 0 */ - mask |=3D s->ucr4 & (UCR4_TCEN | UCR4_DREN); + mask |=3D s->ucr4 & (UCR4_WKEN | UCR4_TCEN | UCR4_DREN); =20 usr2 =3D s->usr2 & mask; =20 @@ -321,6 +321,9 @@ static void imx_put_data(void *opaque, uint32_t value) =20 static void imx_receive(void *opaque, const uint8_t *buf, int size) { + IMXSerialState *s =3D (IMXSerialState *)opaque; + + s->usr2 |=3D USR2_WAKE; imx_put_data(opaque, *buf); } =20 --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185328; cv=none; d=zohomail.com; s=zohoarc; b=WhHevJOGJ0/Efx/FVyCDE+hKjKlsPXxHEO9fMcjst5E6X3e8dPt18lOEvpYz0HEbo0lgsGa1HHYm6HgQBjQGv2sAnf5BQ1glmgO3sY8qPg6KtjAsxb5Ppcm+6Oy/tgNGohCWsGhq1qz592gQlPJvDmVjXi472uPhRdCzOr7ZQsQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185328; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NI6UwYNEBMwFDagdkUVm7AUEy/k4n7TnuACIpknFIYg=; b=hhuQ3fyZ3loZufEYV8Cenj9jir/cPQ2QJy2U9OgamDncbSreTNCZicX7/BCgoaGIjpRvtBTtlGupM0RLJUZVdXMIxJEPUurs9rt//o53OaRBgOmTkmn6k/6tKniFDofp8mh+Zi+TxxsFx7i5Wfo0X2Ic2avjVb5ZYmWcot+brzQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687185328559439.5994947471893; Mon, 19 Jun 2023 07:35:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBFtd-00024v-2b; Mon, 19 Jun 2023 10:30:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBFss-0000ee-LJ for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:36 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBFsp-0002Gs-BP for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:33 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f90b8acefeso15542395e9.0 for ; Mon, 19 Jun 2023 07:29:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184969; x=1689776969; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=NI6UwYNEBMwFDagdkUVm7AUEy/k4n7TnuACIpknFIYg=; b=sp70xA4RWw5A6piT8JSXreZF6x7BoillK9qDflhBejeIebW+SWvMNpk1uCwxfNbZam 1j8Gi4ctBF1PF2wJYpRQx4hXekKWxz+7Q2WiqDPbaddzcW7sHP3/IgLn4nq0H4/Cu91M DjxwHsoRVTkL0hOEwHnhU2l7S4YVmyrRHC7JYgwj4jDBZ9xYgwbaOMJwRgQ4/t4pOYOb Ukl1q6YBqzs5j8l+FjHlfTSFw7R8iXXTQ06piVwWTqLI9X4f5LEUj6662tbNicaHb8YL ePk3/F039k12wNj4iNCcBNU++SLtF7O4QQsNlKx4Jvfv9EGsh+469TA7rZ4f5YppMw/S DCOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184969; x=1689776969; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NI6UwYNEBMwFDagdkUVm7AUEy/k4n7TnuACIpknFIYg=; b=chl4X45QE+p2aq5Gtg6EnRyFr9aVybYIOKRsaVtpEmFfup5cd4s5ae2LFPLlbWWH1W nQ4LuwbM4EH1/BEQlNKYafuRuscx9nv8Nbi/fGNNvGD/hkjOPnfivzZItH417vgQJQOR ViSSgD2DaOAwZuGo0yelGxGHjLnN2VjlC6jnTi3uFlABkFimApsfNGfGqIhC20UY36Qp IbcC1c9r7wn8MrGq00rf0aKkWbIWKdHeKfHpInSue7YQvwMdp5Ud9qGOD+e/rBH2xiG0 zwXNEUS//KlBGfQ5rjmPvBj6etkDsurcWtrmTAtFN1FTAXJKd3iShoMF3HE3xrVedTsz 8Vpg== X-Gm-Message-State: AC+VfDztpar/aH3M+WGSQ4LAW9R5YAzegNIUh0C6T4KduG0BQ+y5kNHD 2XFvb/boP763zcWbINM5+3g0Yz5qsjq0E81h4rM= X-Google-Smtp-Source: ACHHUZ4uR6zDvnEjZDitR8995SosALGXNHWSCkmh+SCftWScnYjSsHeywI9AmpeqT3fmwYexJO6mcA== X-Received: by 2002:a1c:7904:0:b0:3f9:5db4:e8d8 with SMTP id l4-20020a1c7904000000b003f95db4e8d8mr2706758wme.18.1687184969307; Mon, 19 Jun 2023 07:29:29 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/33] docs: sbsa: document board to firmware interface Date: Mon, 19 Jun 2023 15:29:10 +0100 Message-Id: <20230619142914.963184-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185330725100001 Content-Type: text/plain; charset="utf-8" From: Marcin Juszkiewicz We plan to add more hardware information into DeviceTree to limit amount of hardcoded values in firmware. Signed-off-by: Marcin Juszkiewicz Message-id: 20230531171834.236569-1-marcin.juszkiewicz@linaro.org [PMM: fix format nits, add text about platform version fields from a comment in the C source file] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/sbsa.rst | 38 +++++++++++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 7 deletions(-) diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst index 016776aed82..f571fe645e7 100644 --- a/docs/system/arm/sbsa.rst +++ b/docs/system/arm/sbsa.rst @@ -6,12 +6,7 @@ any real hardware the ``sbsa-ref`` board intends to look l= ike real hardware. The `Server Base System Architecture `_ defines a minimum base line of hardware support and importantly how the firmware -reports that to any operating system. It is a static system that -reports a very minimal DT to the firmware for non-discoverable -information about components affected by the qemu command line (i.e. -cpus and memory). As a result it must have a firmware specifically -built to expect a certain hardware layout (as you would in a real -machine). +reports that to any operating system. =20 It is intended to be a machine for developing firmware and testing standards compliance with operating systems. @@ -19,7 +14,7 @@ standards compliance with operating systems. Supported devices """"""""""""""""" =20 -The sbsa-ref board supports: +The ``sbsa-ref`` board supports: =20 - A configurable number of AArch64 CPUs - GIC version 3 @@ -30,3 +25,32 @@ The sbsa-ref board supports: - Bochs display adapter on PCIe bus - A generic SBSA watchdog device =20 + +Board to firmware interface +""""""""""""""""""""""""""" + +``sbsa-ref`` is a static system that reports a very minimal devicetree to = the +firmware for non-discoverable information about system components. This +includes both internal hardware and parts affected by the qemu command line +(i.e. CPUs and memory). As a result it must have a firmware specifically b= uilt +to expect a certain hardware layout (as you would in a real machine). + +DeviceTree information +'''''''''''''''''''''' + +The devicetree provided by the board model to the firmware is not intended +to be a complete compliant DT. It currently reports: + + - CPUs + - memory + - platform version + - GIC addresses + +The platform version is only for informing platform firmware about +what kind of ``sbsa-ref`` board it is running on. It is neither +a QEMU versioned machine type nor a reflection of the level of the +SBSA/SystemReady SR support provided. + +The ``machine-version-major`` value is updated when changes breaking +fw compatibility are introduced. The ``machine-version-minor`` value +is updated when features are added that don't break fw compatibility. --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185231; cv=none; d=zohomail.com; s=zohoarc; b=HLOtG3gqk7sUkPT1WagPvs2DxNoE/ytPPY1yatWqSyR0flhscb52ERrI3Q7LUNinKiZ2UArwx8Y4WbCorU5FGdknx7vaw4zsf4gYdyGOoUkD/RAo1IMTnxWCqkNA1ow1Ac9uFEFq3i88JwJqatEHyeusa2TtcOxx4/8jejGxM2I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1687185231; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gANnIjR15MvbtEtqZKvq2YpAxv3DVsdAP26xm73zIX0=; b=dZc9U+kGCfrPCM/wpJlhFTCcAWRYVShtKdkWYPy6KrJZt/T9fFkk4UBVfXz/ZP6VLi4MmvXoHmyUL8omuTmn7TLEJ3WnTuQSM2115pYehdbcvrTB4TCQXEi0OrfYB8lN/0qi7AQj+VdMhGVOvJYUoVAh9xOX7Fh9JDoO2KLX3C8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1687185231260761.9057308525772; Mon, 19 Jun 2023 07:33:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBFte-0002Bf-EL; Mon, 19 Jun 2023 10:30:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBFss-0000eg-Lz for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:36 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBFsp-0002H5-Bb for qemu-devel@nongnu.org; Mon, 19 Jun 2023 10:29:33 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-3f9b37cd548so6532685e9.1 for ; Mon, 19 Jun 2023 07:29:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Subject: [PULL 30/33] hw/arm/raspi: Import Linux raspi definitions as 'raspberrypi-fw-defs.h' Date: Mon, 19 Jun 2023 15:29:11 +0100 Message-Id: <20230619142914.963184-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185231486100001 From: Sergey Kambalin Signed-off-by: Sergey Kambalin Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Richard Henderson Message-id: 20230612223456.33824-2-philmd@linaro.org Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com> [PMD: Split from bigger patch: 1/4] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- include/hw/misc/raspberrypi-fw-defs.h | 163 ++++++++++++++++++++++++++ 1 file changed, 163 insertions(+) create mode 100644 include/hw/misc/raspberrypi-fw-defs.h diff --git a/include/hw/misc/raspberrypi-fw-defs.h b/include/hw/misc/raspbe= rrypi-fw-defs.h new file mode 100644 index 00000000000..4551fe7450d --- /dev/null +++ b/include/hw/misc/raspberrypi-fw-defs.h @@ -0,0 +1,163 @@ +/* + * Raspberry Pi firmware definitions + * + * Copyright (C) 2022 Auriga LLC, based on Linux kernel + * `include/soc/bcm2835/raspberrypi-firmware.h` (Copyright =C2=A9 2015 B= roadcom) + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef INCLUDE_HW_MISC_RASPBERRYPI_FW_DEFS_H_ +#define INCLUDE_HW_MISC_RASPBERRYPI_FW_DEFS_H_ + +#include "qemu/osdep.h" + +enum rpi_firmware_property_tag { + RPI_FWREQ_PROPERTY_END =3D 0, + RPI_FWREQ_GET_FIRMWARE_REVISION =3D 0x00000001, + RPI_FWREQ_GET_FIRMWARE_VARIANT =3D 0x00000002, + RPI_FWREQ_GET_FIRMWARE_HASH =3D 0x00000003, + + RPI_FWREQ_SET_CURSOR_INFO =3D 0x00008010, + RPI_FWREQ_SET_CURSOR_STATE =3D 0x00008011, + + RPI_FWREQ_GET_BOARD_MODEL =3D 0x00010001, + RPI_FWREQ_GET_BOARD_REVISION =3D 0x00010002, + RPI_FWREQ_GET_BOARD_MAC_ADDRESS =3D 0x00010003, + RPI_FWREQ_GET_BOARD_SERIAL =3D 0x00010004, + RPI_FWREQ_GET_ARM_MEMORY =3D 0x00010005, + RPI_FWREQ_GET_VC_MEMORY =3D 0x00010006, + RPI_FWREQ_GET_CLOCKS =3D 0x00010007, + RPI_FWREQ_GET_POWER_STATE =3D 0x00020001, + RPI_FWREQ_GET_TIMING =3D 0x00020002, + RPI_FWREQ_SET_POWER_STATE =3D 0x00028001, + RPI_FWREQ_GET_CLOCK_STATE =3D 0x00030001, + RPI_FWREQ_GET_CLOCK_RATE =3D 0x00030002, + RPI_FWREQ_GET_VOLTAGE =3D 0x00030003, + RPI_FWREQ_GET_MAX_CLOCK_RATE =3D 0x00030004, + RPI_FWREQ_GET_MAX_VOLTAGE =3D 0x00030005, + RPI_FWREQ_GET_TEMPERATURE =3D 0x00030006, + RPI_FWREQ_GET_MIN_CLOCK_RATE =3D 0x00030007, + RPI_FWREQ_GET_MIN_VOLTAGE =3D 0x00030008, + RPI_FWREQ_GET_TURBO =3D 0x00030009, + RPI_FWREQ_GET_MAX_TEMPERATURE =3D 0x0003000a, + RPI_FWREQ_GET_STC =3D 0x0003000b, + RPI_FWREQ_ALLOCATE_MEMORY =3D 0x0003000c, + RPI_FWREQ_LOCK_MEMORY =3D 0x0003000d, + RPI_FWREQ_UNLOCK_MEMORY =3D 0x0003000e, + RPI_FWREQ_RELEASE_MEMORY =3D 0x0003000f, + RPI_FWREQ_EXECUTE_CODE =3D 0x00030010, + RPI_FWREQ_EXECUTE_QPU =3D 0x00030011, + RPI_FWREQ_SET_ENABLE_QPU =3D 0x00030012, + RPI_FWREQ_GET_DISPMANX_RESOURCE_MEM_HANDLE =3D 0x00030014, + RPI_FWREQ_GET_EDID_BLOCK =3D 0x00030020, + RPI_FWREQ_GET_CUSTOMER_OTP =3D 0x00030021, + RPI_FWREQ_GET_EDID_BLOCK_DISPLAY =3D 0x00030023, + RPI_FWREQ_GET_DOMAIN_STATE =3D 0x00030030, + RPI_FWREQ_GET_THROTTLED =3D 0x00030046, + RPI_FWREQ_GET_CLOCK_MEASURED =3D 0x00030047, + RPI_FWREQ_NOTIFY_REBOOT =3D 0x00030048, + RPI_FWREQ_SET_CLOCK_STATE =3D 0x00038001, + RPI_FWREQ_SET_CLOCK_RATE =3D 0x00038002, + RPI_FWREQ_SET_VOLTAGE =3D 0x00038003, + RPI_FWREQ_SET_MAX_CLOCK_RATE =3D 0x00038004, + RPI_FWREQ_SET_MIN_CLOCK_RATE =3D 0x00038007, + RPI_FWREQ_SET_TURBO =3D 0x00038009, + RPI_FWREQ_SET_CUSTOMER_OTP =3D 0x00038021, + RPI_FWREQ_SET_DOMAIN_STATE =3D 0x00038030, + RPI_FWREQ_GET_GPIO_STATE =3D 0x00030041, + RPI_FWREQ_SET_GPIO_STATE =3D 0x00038041, + RPI_FWREQ_SET_SDHOST_CLOCK =3D 0x00038042, + RPI_FWREQ_GET_GPIO_CONFIG =3D 0x00030043, + RPI_FWREQ_SET_GPIO_CONFIG =3D 0x00038043, + RPI_FWREQ_GET_PERIPH_REG =3D 0x00030045, + RPI_FWREQ_SET_PERIPH_REG =3D 0x00038045, + RPI_FWREQ_GET_POE_HAT_VAL =3D 0x00030049, + RPI_FWREQ_SET_POE_HAT_VAL =3D 0x00038049, + RPI_FWREQ_SET_POE_HAT_VAL_OLD =3D 0x00030050, + RPI_FWREQ_NOTIFY_XHCI_RESET =3D 0x00030058, + RPI_FWREQ_GET_REBOOT_FLAGS =3D 0x00030064, + RPI_FWREQ_SET_REBOOT_FLAGS =3D 0x00038064, + RPI_FWREQ_NOTIFY_DISPLAY_DONE =3D 0x00030066, + + /* Dispmanx TAGS */ + RPI_FWREQ_FRAMEBUFFER_ALLOCATE =3D 0x00040001, + RPI_FWREQ_FRAMEBUFFER_BLANK =3D 0x00040002, + RPI_FWREQ_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT =3D 0x00040003, + RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_WIDTH_HEIGHT =3D 0x00040004, + RPI_FWREQ_FRAMEBUFFER_GET_DEPTH =3D 0x00040005, + RPI_FWREQ_FRAMEBUFFER_GET_PIXEL_ORDER =3D 0x00040006, + RPI_FWREQ_FRAMEBUFFER_GET_ALPHA_MODE =3D 0x00040007, + RPI_FWREQ_FRAMEBUFFER_GET_PITCH =3D 0x00040008, + RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_OFFSET =3D 0x00040009, + RPI_FWREQ_FRAMEBUFFER_GET_OVERSCAN =3D 0x0004000a, + RPI_FWREQ_FRAMEBUFFER_GET_PALETTE =3D 0x0004000b, + RPI_FWREQ_FRAMEBUFFER_GET_LAYER =3D 0x0004000c, + RPI_FWREQ_FRAMEBUFFER_GET_TRANSFORM =3D 0x0004000d, + RPI_FWREQ_FRAMEBUFFER_GET_VSYNC =3D 0x0004000e, + RPI_FWREQ_FRAMEBUFFER_GET_TOUCHBUF =3D 0x0004000f, + RPI_FWREQ_FRAMEBUFFER_GET_GPIOVIRTBUF =3D 0x00040010, + RPI_FWREQ_FRAMEBUFFER_RELEASE =3D 0x00048001, + RPI_FWREQ_FRAMEBUFFER_GET_DISPLAY_ID =3D 0x00040016, + RPI_FWREQ_FRAMEBUFFER_SET_DISPLAY_NUM =3D 0x00048013, + RPI_FWREQ_FRAMEBUFFER_GET_NUM_DISPLAYS =3D 0x00040013, + RPI_FWREQ_FRAMEBUFFER_GET_DISPLAY_SETTINGS =3D 0x00040014, + RPI_FWREQ_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT =3D 0x00044003, + RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT =3D 0x00044004, + RPI_FWREQ_FRAMEBUFFER_TEST_DEPTH =3D 0x00044005, + RPI_FWREQ_FRAMEBUFFER_TEST_PIXEL_ORDER =3D 0x00044006, + RPI_FWREQ_FRAMEBUFFER_TEST_ALPHA_MODE =3D 0x00044007, + RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_OFFSET =3D 0x00044009, + RPI_FWREQ_FRAMEBUFFER_TEST_OVERSCAN =3D 0x0004400a, + RPI_FWREQ_FRAMEBUFFER_TEST_PALETTE =3D 0x0004400b, + RPI_FWREQ_FRAMEBUFFER_TEST_LAYER =3D 0x0004400c, + RPI_FWREQ_FRAMEBUFFER_TEST_TRANSFORM =3D 0x0004400d, + RPI_FWREQ_FRAMEBUFFER_TEST_VSYNC =3D 0x0004400e, + RPI_FWREQ_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT =3D 0x00048003, + RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT =3D 0x00048004, + RPI_FWREQ_FRAMEBUFFER_SET_DEPTH =3D 0x00048005, + RPI_FWREQ_FRAMEBUFFER_SET_PIXEL_ORDER =3D 0x00048006, + RPI_FWREQ_FRAMEBUFFER_SET_ALPHA_MODE =3D 0x00048007, + RPI_FWREQ_FRAMEBUFFER_SET_PITCH =3D 0x00048008, + RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_OFFSET =3D 0x00048009, + RPI_FWREQ_FRAMEBUFFER_SET_OVERSCAN =3D 0x0004800a, + RPI_FWREQ_FRAMEBUFFER_SET_PALETTE =3D 0x0004800b, + + RPI_FWREQ_FRAMEBUFFER_SET_TOUCHBUF =3D 0x0004801f, + RPI_FWREQ_FRAMEBUFFER_SET_GPIOVIRTBUF =3D 0x00048020, + RPI_FWREQ_FRAMEBUFFER_SET_VSYNC =3D 0x0004800e, + RPI_FWREQ_FRAMEBUFFER_SET_LAYER =3D 0x0004800c, + RPI_FWREQ_FRAMEBUFFER_SET_TRANSFORM =3D 0x0004800d, + RPI_FWREQ_FRAMEBUFFER_SET_BACKLIGHT =3D 0x0004800f, + + RPI_FWREQ_VCHIQ_INIT =3D 0x00048010, + + RPI_FWREQ_SET_PLANE =3D 0x00048015, + RPI_FWREQ_GET_DISPLAY_TIMING =3D 0x00040017, + RPI_FWREQ_SET_TIMING =3D 0x00048017, + RPI_FWREQ_GET_DISPLAY_CFG =3D 0x00040018, + RPI_FWREQ_SET_DISPLAY_POWER =3D 0x00048019, + RPI_FWREQ_GET_COMMAND_LINE =3D 0x00050001, + RPI_FWREQ_GET_DMA_CHANNELS =3D 0x00060001, +}; + +enum rpi_firmware_clk_id { + RPI_FIRMWARE_EMMC_CLK_ID =3D 1, + RPI_FIRMWARE_UART_CLK_ID, + RPI_FIRMWARE_ARM_CLK_ID, + RPI_FIRMWARE_CORE_CLK_ID, + RPI_FIRMWARE_V3D_CLK_ID, + RPI_FIRMWARE_H264_CLK_ID, + RPI_FIRMWARE_ISP_CLK_ID, + RPI_FIRMWARE_SDRAM_CLK_ID, + RPI_FIRMWARE_PIXEL_CLK_ID, + RPI_FIRMWARE_PWM_CLK_ID, + RPI_FIRMWARE_HEVC_CLK_ID, + RPI_FIRMWARE_EMMC2_CLK_ID, + RPI_FIRMWARE_M2MC_CLK_ID, + RPI_FIRMWARE_PIXEL_BVB_CLK_ID, + RPI_FIRMWARE_VEC_CLK_ID, + RPI_FIRMWARE_NUM_CLK_ID, +}; + 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184970; x=1689776970; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=RNT/r2o8ygcfuLmS3aOhU+fclJP7M52chyu0mF6eDgY=; b=HPv8A8OgmM1z/xDa5nsDS0Sp+5+gmJs3Czqcjf46B32Xs1t/5syKag7sPoGxQ4tMQl jjKUkATyhd5LAXdTNAA0ZXf9DP+C5uf37NOOg3qxagnL9u6BIMj6RRVhIg5xo3Uc7DJw VMTUbse+i44CQ2YPx6B5+Aau6JJeBHiiI/DZtur44GaOhLXt+iJbirPsxxbhH9ntbgfa ul+pZAOCyoqYJhw+hLUD8WDNCaIF6J9QiAV2rJIz13RICfRAzUYCkCwngFtcEErgYK1Q pzis7buIygr9PGnivHyNXpPvrOxUvgb07nNdga58u1HDdS4Yw/4GoK1ppYFV4YFHkeUK sIhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184970; x=1689776970; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RNT/r2o8ygcfuLmS3aOhU+fclJP7M52chyu0mF6eDgY=; b=B/8Gv64o/Nz3QXyr2ia+dKjEvzSBooT5XRlkHESLZTydGnn29R/+7thsDwoMZIhavD XVmO8VEKCkHncw8vbadnw3b1Q+rE/roMdx63dAXaXY+2UuD1q8RQd0Ata/q0BjVNr3YQ fhrWyHzImOkaGcLLrEMa2euur4wmIIwKQhvGRwNtGam+JbFsfugFRvI6r+vVU+IPWLmr TKRItXjoOVUCuVmm3pqH3FYBNphWorz+lT6MnxoLQ2Bsd2+QuoTo5A+1cVZ6TxbN7nj1 5/V2hsow+lmlr18k/73bdzwjFwSlbSETzaEVoBiz5102oGlS23Nh2iuCKGPhm8X0U/tF T7Bg== X-Gm-Message-State: AC+VfDy2weX3gElIO+E7rk8SnpcxPmpmn6dHcekEhIVzqUxbh4wdfB2J nybCF91t7KJfQ6dB0ITD+vfCfeOTbsMBnRpqeQQ= X-Google-Smtp-Source: ACHHUZ4wYXfLXVpnCefctX74xuiL9AFtdtw6LQy1TIYtFsAtbna42kK1PXbL0FKR2Qd+QwmkmlMubQ== X-Received: by 2002:a7b:c7ca:0:b0:3f9:b2db:88eb with SMTP id z10-20020a7bc7ca000000b003f9b2db88ebmr1143812wmk.28.1687184970343; Mon, 19 Jun 2023 07:29:30 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/33] hw/misc/bcm2835_property: Use 'raspberrypi-fw-defs.h' definitions Date: Mon, 19 Jun 2023 15:29:12 +0100 Message-Id: <20230619142914.963184-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619142914.963184-1-peter.maydell@linaro.org> References: <20230619142914.963184-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185046487100003 From: Sergey Kambalin Replace magic property values by a proper definition, removing redundant comments. Signed-off-by: Sergey Kambalin Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20230612223456.33824-3-philmd@linaro.org Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com> [PMD: Split from bigger patch: 2/4] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- hw/misc/bcm2835_property.c | 101 +++++++++++++++++++------------------ 1 file changed, 51 insertions(+), 50 deletions(-) diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c index 251b3d865d7..7d398a6f750 100644 --- a/hw/misc/bcm2835_property.c +++ b/hw/misc/bcm2835_property.c @@ -12,6 +12,7 @@ #include "migration/vmstate.h" #include "hw/irq.h" #include "hw/misc/bcm2835_mbox_defs.h" +#include "hw/misc/raspberrypi-fw-defs.h" #include "sysemu/dma.h" #include "qemu/log.h" #include "qemu/module.h" @@ -51,48 +52,48 @@ static void bcm2835_property_mbox_push(BCM2835PropertyS= tate *s, uint32_t value) /* @(value + 8) : Request/response indicator */ resplen =3D 0; switch (tag) { - case 0x00000000: /* End tag */ + case RPI_FWREQ_PROPERTY_END: break; - case 0x00000001: /* Get firmware revision */ + case RPI_FWREQ_GET_FIRMWARE_REVISION: stl_le_phys(&s->dma_as, value + 12, 346337); resplen =3D 4; break; - case 0x00010001: /* Get board model */ + case RPI_FWREQ_GET_BOARD_MODEL: qemu_log_mask(LOG_UNIMP, "bcm2835_property: 0x%08x get board model NYI\n", tag); resplen =3D 4; break; - case 0x00010002: /* Get board revision */ + case RPI_FWREQ_GET_BOARD_REVISION: stl_le_phys(&s->dma_as, value + 12, s->board_rev); resplen =3D 4; break; - case 0x00010003: /* Get board MAC address */ + case RPI_FWREQ_GET_BOARD_MAC_ADDRESS: resplen =3D sizeof(s->macaddr.a); dma_memory_write(&s->dma_as, value + 12, s->macaddr.a, resplen, MEMTXATTRS_UNSPECIFIED); break; - case 0x00010004: /* Get board serial */ + case RPI_FWREQ_GET_BOARD_SERIAL: qemu_log_mask(LOG_UNIMP, "bcm2835_property: 0x%08x get board serial NYI\n= ", tag); resplen =3D 8; break; - case 0x00010005: /* Get ARM memory */ + case RPI_FWREQ_GET_ARM_MEMORY: /* base */ stl_le_phys(&s->dma_as, value + 12, 0); /* size */ stl_le_phys(&s->dma_as, value + 16, s->fbdev->vcram_base); resplen =3D 8; break; - case 0x00010006: /* Get VC memory */ + case RPI_FWREQ_GET_VC_MEMORY: /* base */ stl_le_phys(&s->dma_as, value + 12, s->fbdev->vcram_base); /* size */ stl_le_phys(&s->dma_as, value + 16, s->fbdev->vcram_size); resplen =3D 8; break; - case 0x00028001: /* Set power state */ + case RPI_FWREQ_SET_POWER_STATE: /* Assume that whatever device they asked for exists, * and we'll just claim we set it to the desired state */ @@ -103,26 +104,26 @@ static void bcm2835_property_mbox_push(BCM2835Propert= yState *s, uint32_t value) =20 /* Clocks */ =20 - case 0x00030001: /* Get clock state */ + case RPI_FWREQ_GET_CLOCK_STATE: stl_le_phys(&s->dma_as, value + 16, 0x1); resplen =3D 8; break; =20 - case 0x00038001: /* Set clock state */ + case RPI_FWREQ_SET_CLOCK_STATE: qemu_log_mask(LOG_UNIMP, "bcm2835_property: 0x%08x set clock state NYI\n", tag); resplen =3D 8; break; =20 - case 0x00030002: /* Get clock rate */ - case 0x00030004: /* Get max clock rate */ - case 0x00030007: /* Get min clock rate */ + case RPI_FWREQ_GET_CLOCK_RATE: + case RPI_FWREQ_GET_MAX_CLOCK_RATE: + case RPI_FWREQ_GET_MIN_CLOCK_RATE: switch (ldl_le_phys(&s->dma_as, value + 12)) { - case 1: /* EMMC */ + case RPI_FIRMWARE_EMMC_CLK_ID: stl_le_phys(&s->dma_as, value + 16, 50000000); break; - case 2: /* UART */ + case RPI_FIRMWARE_UART_CLK_ID: stl_le_phys(&s->dma_as, value + 16, 3000000); break; default: @@ -132,9 +133,9 @@ static void bcm2835_property_mbox_push(BCM2835PropertyS= tate *s, uint32_t value) resplen =3D 8; break; =20 - case 0x00038002: /* Set clock rate */ - case 0x00038004: /* Set max clock rate */ - case 0x00038007: /* Set min clock rate */ + case RPI_FWREQ_SET_CLOCK_RATE: + case RPI_FWREQ_SET_MAX_CLOCK_RATE: + case RPI_FWREQ_SET_MIN_CLOCK_RATE: qemu_log_mask(LOG_UNIMP, "bcm2835_property: 0x%08x set clock rate NYI\n", tag); @@ -143,121 +144,121 @@ static void bcm2835_property_mbox_push(BCM2835Prope= rtyState *s, uint32_t value) =20 /* Temperature */ =20 - case 0x00030006: /* Get temperature */ + case RPI_FWREQ_GET_TEMPERATURE: stl_le_phys(&s->dma_as, value + 16, 25000); resplen =3D 8; break; =20 - case 0x0003000A: /* Get max temperature */ + case RPI_FWREQ_GET_MAX_TEMPERATURE: stl_le_phys(&s->dma_as, value + 16, 99000); resplen =3D 8; break; =20 /* Frame buffer */ =20 - case 0x00040001: /* Allocate buffer */ + case RPI_FWREQ_FRAMEBUFFER_ALLOCATE: stl_le_phys(&s->dma_as, value + 12, fbconfig.base); stl_le_phys(&s->dma_as, value + 16, bcm2835_fb_get_size(&fbconfig)); resplen =3D 8; break; - case 0x00048001: /* Release buffer */ + case RPI_FWREQ_FRAMEBUFFER_RELEASE: resplen =3D 0; break; - case 0x00040002: /* Blank screen */ + case RPI_FWREQ_FRAMEBUFFER_BLANK: resplen =3D 4; break; - case 0x00044003: /* Test physical display width/height */ - case 0x00044004: /* Test virtual display width/height */ + case RPI_FWREQ_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT: + case RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT: resplen =3D 8; break; - case 0x00048003: /* Set physical display width/height */ + case RPI_FWREQ_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT: fbconfig.xres =3D ldl_le_phys(&s->dma_as, value + 12); fbconfig.yres =3D ldl_le_phys(&s->dma_as, value + 16); bcm2835_fb_validate_config(&fbconfig); fbconfig_updated =3D true; /* fall through */ - case 0x00040003: /* Get physical display width/height */ + case RPI_FWREQ_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT: stl_le_phys(&s->dma_as, value + 12, fbconfig.xres); stl_le_phys(&s->dma_as, value + 16, fbconfig.yres); resplen =3D 8; break; - case 0x00048004: /* Set virtual display width/height */ + case RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT: fbconfig.xres_virtual =3D ldl_le_phys(&s->dma_as, value + 12); fbconfig.yres_virtual =3D ldl_le_phys(&s->dma_as, value + 16); bcm2835_fb_validate_config(&fbconfig); fbconfig_updated =3D true; /* fall through */ - case 0x00040004: /* Get virtual display width/height */ + case RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_WIDTH_HEIGHT: stl_le_phys(&s->dma_as, value + 12, fbconfig.xres_virtual); stl_le_phys(&s->dma_as, value + 16, fbconfig.yres_virtual); resplen =3D 8; break; - case 0x00044005: /* Test depth */ + case RPI_FWREQ_FRAMEBUFFER_TEST_DEPTH: resplen =3D 4; break; - case 0x00048005: /* Set depth */ + case RPI_FWREQ_FRAMEBUFFER_SET_DEPTH: fbconfig.bpp =3D ldl_le_phys(&s->dma_as, value + 12); bcm2835_fb_validate_config(&fbconfig); fbconfig_updated =3D true; /* fall through */ - case 0x00040005: /* Get depth */ + case RPI_FWREQ_FRAMEBUFFER_GET_DEPTH: stl_le_phys(&s->dma_as, value + 12, fbconfig.bpp); resplen =3D 4; break; - case 0x00044006: /* Test pixel order */ + case RPI_FWREQ_FRAMEBUFFER_TEST_PIXEL_ORDER: resplen =3D 4; break; - case 0x00048006: /* Set pixel order */ + case RPI_FWREQ_FRAMEBUFFER_SET_PIXEL_ORDER: fbconfig.pixo =3D ldl_le_phys(&s->dma_as, value + 12); bcm2835_fb_validate_config(&fbconfig); fbconfig_updated =3D true; /* fall through */ - case 0x00040006: /* Get pixel order */ + case RPI_FWREQ_FRAMEBUFFER_GET_PIXEL_ORDER: stl_le_phys(&s->dma_as, value + 12, fbconfig.pixo); resplen =3D 4; break; - case 0x00044007: /* Test pixel alpha */ + case RPI_FWREQ_FRAMEBUFFER_TEST_ALPHA_MODE: resplen =3D 4; break; - case 0x00048007: /* Set alpha */ + case RPI_FWREQ_FRAMEBUFFER_SET_ALPHA_MODE: fbconfig.alpha =3D ldl_le_phys(&s->dma_as, value + 12); bcm2835_fb_validate_config(&fbconfig); fbconfig_updated =3D true; /* fall through */ - case 0x00040007: /* Get alpha */ + case RPI_FWREQ_FRAMEBUFFER_GET_ALPHA_MODE: stl_le_phys(&s->dma_as, value + 12, fbconfig.alpha); resplen =3D 4; break; - case 0x00040008: /* Get pitch */ + case RPI_FWREQ_FRAMEBUFFER_GET_PITCH: stl_le_phys(&s->dma_as, value + 12, bcm2835_fb_get_pitch(&fbconfig)); resplen =3D 4; break; - case 0x00044009: /* Test virtual offset */ + case RPI_FWREQ_FRAMEBUFFER_TEST_VIRTUAL_OFFSET: resplen =3D 8; break; - case 0x00048009: /* Set virtual offset */ + case RPI_FWREQ_FRAMEBUFFER_SET_VIRTUAL_OFFSET: fbconfig.xoffset =3D ldl_le_phys(&s->dma_as, value + 12); fbconfig.yoffset =3D ldl_le_phys(&s->dma_as, value + 16); bcm2835_fb_validate_config(&fbconfig); fbconfig_updated =3D true; /* fall through */ - case 0x00040009: /* Get virtual offset */ + case RPI_FWREQ_FRAMEBUFFER_GET_VIRTUAL_OFFSET: stl_le_phys(&s->dma_as, value + 12, fbconfig.xoffset); stl_le_phys(&s->dma_as, value + 16, fbconfig.yoffset); resplen =3D 8; break; - case 0x0004000a: /* Get/Test/Set overscan */ - case 0x0004400a: - case 0x0004800a: + case RPI_FWREQ_FRAMEBUFFER_GET_OVERSCAN: + case RPI_FWREQ_FRAMEBUFFER_TEST_OVERSCAN: + case RPI_FWREQ_FRAMEBUFFER_SET_OVERSCAN: stl_le_phys(&s->dma_as, value + 12, 0); stl_le_phys(&s->dma_as, value + 16, 0); stl_le_phys(&s->dma_as, value + 20, 0); stl_le_phys(&s->dma_as, value + 24, 0); resplen =3D 16; break; - case 0x0004800b: /* Set palette */ + case RPI_FWREQ_FRAMEBUFFER_SET_PALETTE: offset =3D ldl_le_phys(&s->dma_as, value + 12); length =3D ldl_le_phys(&s->dma_as, value + 16); n =3D 0; @@ -270,18 +271,18 @@ static void bcm2835_property_mbox_push(BCM2835Propert= yState *s, uint32_t value) stl_le_phys(&s->dma_as, value + 12, 0); resplen =3D 4; break; - case 0x00040013: /* Get number of displays */ + case RPI_FWREQ_FRAMEBUFFER_GET_NUM_DISPLAYS: stl_le_phys(&s->dma_as, value + 12, 1); resplen =3D 4; break; =20 - case 0x00060001: /* Get DMA channels */ + case RPI_FWREQ_GET_DMA_CHANNELS: /* channels 2-5 */ stl_le_phys(&s->dma_as, value + 12, 0x003C); resplen =3D 4; break; =20 - case 0x00050001: /* Get command line */ + case RPI_FWREQ_GET_COMMAND_LINE: /* * We follow the firmware behaviour: no NUL terminator is * written to the buffer, and if the buffer is too short --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185262156100007 From: Sergey Kambalin Signed-off-by: Sergey Kambalin Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20230612223456.33824-4-philmd@linaro.org Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com> [PMD: Split from bigger patch: 4/4] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- include/hw/arm/raspi_platform.h | 5 +++++ hw/misc/bcm2835_property.c | 8 +++++--- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platfor= m.h index 4a56dd4b890..83f2588fc52 100644 --- a/include/hw/arm/raspi_platform.h +++ b/include/hw/arm/raspi_platform.h @@ -170,4 +170,9 @@ #define INTERRUPT_ILLEGAL_TYPE0 6 #define INTERRUPT_ILLEGAL_TYPE1 7 =20 +/* Clock rates */ +#define RPI_FIRMWARE_EMMC_CLK_RATE 50000000 +#define RPI_FIRMWARE_UART_CLK_RATE 3000000 +#define RPI_FIRMWARE_DEFAULT_CLK_RATE 700000000 + #endif diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c index 7d398a6f750..2e4fe969bf8 100644 --- a/hw/misc/bcm2835_property.c +++ b/hw/misc/bcm2835_property.c @@ -17,6 +17,7 @@ #include "qemu/log.h" #include "qemu/module.h" #include "trace.h" +#include "hw/arm/raspi_platform.h" =20 /* https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface= */ =20 @@ -121,13 +122,14 @@ static void bcm2835_property_mbox_push(BCM2835Propert= yState *s, uint32_t value) case RPI_FWREQ_GET_MIN_CLOCK_RATE: switch (ldl_le_phys(&s->dma_as, value + 12)) { case RPI_FIRMWARE_EMMC_CLK_ID: - stl_le_phys(&s->dma_as, value + 16, 50000000); + stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_EMMC_CLK_= RATE); break; case RPI_FIRMWARE_UART_CLK_ID: - stl_le_phys(&s->dma_as, value + 16, 3000000); + stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_UART_CLK_= RATE); break; default: - stl_le_phys(&s->dma_as, value + 16, 700000000); + stl_le_phys(&s->dma_as, value + 16, + RPI_FIRMWARE_DEFAULT_CLK_RATE); break; } resplen =3D 8; --=20 2.34.1 From nobody Sun May 19 09:42:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1687185064; cv=none; d=zohomail.com; s=zohoarc; b=PAltgO7IwBDCY6MqkIy9z2rFRtvx6F3Z393P9vo37apUB2nPGcQuq7JhL3sjpuBIrsWvrioOlmFOAt1qsB3PChu1DRtnNIE5+rbcFwZ+lz+ZPM+fRjNCrfbAZeU3c1Wde88e5nKxUO14BI0dEeD3Zd6hWkbXJxjuSnt4EJEQUtY= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a2-20020a05600c224200b003f9b53959a4sm429012wmm.43.2023.06.19.07.29.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jun 2023 07:29:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687184971; x=1689776971; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=79CNzgIoquxBlIAhz4j7SvzU/NO7uQSo19o8spaDBRU=; b=CBCWSwNnbt0tH1Kyaq6X+YOkD1h3/UodamiTf83kSyEWcrW/60eipoPzIZadQa1wxp hj9U4GUJDgQkLR8cOzukYg7lhnSl3i5xS0BlhypHmyUdwRztKnpARpf9aSrVBFuvWOR0 WJEFQ59t1mnuHY2RSNliU679z99FUaJx+O/GWngO98XvKf/DW3nT8pU/oWXqMbYSzuTj pgZa6LOuAdJvtzsfWsoHIFyMRNJ2qgs4WvQZ/eal8Nnp5kxlogKKoWgCBk7K2S8OAedP 43ml4XmO6ZBR0qnwGDRnP/Kc9VDVoK1e+t26SLMy+yPfvk2g/R+Z9hbC++MYcuXu+88n XmtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687184971; x=1689776971; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687185066620100003 From: Sergey Kambalin Signed-off-by: Sergey Kambalin Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230612223456.33824-5-philmd@linaro.org Message-Id: <20230531155258.8361-1-sergey.kambalin@auriga.com> [PMD: Split from bigger patch: 3/4] Signed-off-by: Philippe Mathieu-Daud=C3=A9 [PMM: added a comment about RPI_FIRMWARE_CORE_CLK_RATE really being SoC-specific] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/raspi_platform.h | 5 +++++ hw/misc/bcm2835_property.c | 3 +++ 2 files changed, 8 insertions(+) diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platfor= m.h index 83f2588fc52..ede98e63c33 100644 --- a/include/hw/arm/raspi_platform.h +++ b/include/hw/arm/raspi_platform.h @@ -173,6 +173,11 @@ /* Clock rates */ #define RPI_FIRMWARE_EMMC_CLK_RATE 50000000 #define RPI_FIRMWARE_UART_CLK_RATE 3000000 +/* + * TODO: this is really SoC-specific; we might want to + * set it per-SoC if it turns out any guests care. + */ +#define RPI_FIRMWARE_CORE_CLK_RATE 350000000 #define RPI_FIRMWARE_DEFAULT_CLK_RATE 700000000 =20 #endif diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c index 2e4fe969bf8..4ed9faa54a1 100644 --- a/hw/misc/bcm2835_property.c +++ b/hw/misc/bcm2835_property.c @@ -127,6 +127,9 @@ static void bcm2835_property_mbox_push(BCM2835PropertyS= tate *s, uint32_t value) case RPI_FIRMWARE_UART_CLK_ID: stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_UART_CLK_= RATE); break; + case RPI_FIRMWARE_CORE_CLK_ID: + stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_CORE_CLK_= RATE); + break; default: stl_le_phys(&s->dma_as, value + 16, RPI_FIRMWARE_DEFAULT_CLK_RATE); --=20 2.34.1