From nobody Sun May 19 10:57:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686909766765997.527273548133; Fri, 16 Jun 2023 03:02:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qA6HT-0007H4-8R; Fri, 16 Jun 2023 06:02:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qA6HR-0007GV-Dp for qemu-devel@nongnu.org; Fri, 16 Jun 2023 06:02:09 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qA6HN-0000d1-0Q for qemu-devel@nongnu.org; Fri, 16 Jun 2023 06:02:09 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8Cx_eoYM4xkQO8FAA--.12833S3; Fri, 16 Jun 2023 18:02:00 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxFOQWM4xkSygdAA--.17116S3; Fri, 16 Jun 2023 18:02:00 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, Tianrui Zhao Subject: [PULL 1/5] hw/loongarch/virt: Add cpu arch_id support Date: Fri, 16 Jun 2023 18:01:54 +0800 Message-Id: <20230616100158.1845239-2-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230616100158.1845239-1-gaosong@loongson.cn> References: <20230616100158.1845239-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8DxFOQWM4xkSygdAA--.17116S3 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686909767486100003 Content-Type: text/plain; charset="utf-8" From: Tianrui Zhao With acpi madt table, there is cpu physical coreid, which may be different with logical id in qemu. This patch adds cpu arch_id support, and fill madt table with arch_id. For the present cpu arch_id is still equal to logical id. Reviewed-by: Song Gao Signed-off-by: Tianrui Zhao Signed-off-by: Song Gao Message-Id: <20230613120552.2471420-2-zhaotianrui@loongson.cn> --- hw/loongarch/acpi-build.c | 20 ++++++++++++++------ hw/loongarch/virt.c | 34 ++++++++++++++++++++++++++++++++-- 2 files changed, 46 insertions(+), 8 deletions(-) diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c index 8e3ce07367..232344e1c7 100644 --- a/hw/loongarch/acpi-build.c +++ b/hw/loongarch/acpi-build.c @@ -107,7 +107,9 @@ static void build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *= lams) { MachineState *ms =3D MACHINE(lams); - int i; + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + const CPUArchIdList *arch_ids =3D mc->possible_cpu_arch_ids(ms); + int i, arch_id; AcpiTable table =3D { .sig =3D "APIC", .rev =3D 1, .oem_id =3D lams->o= em_id, .oem_table_id =3D lams->oem_table_id }; =20 @@ -117,13 +119,15 @@ build_madt(GArray *table_data, BIOSLinker *linker, Lo= ongArchMachineState *lams) build_append_int_noprefix(table_data, 0, 4); build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); /* Flag= s */ =20 - for (i =3D 0; i < ms->smp.cpus; i++) { + for (i =3D 0; i < arch_ids->len; i++) { /* Processor Core Interrupt Controller Structure */ + arch_id =3D arch_ids->cpus[i].arch_id; + build_append_int_noprefix(table_data, 17, 1); /* Type */ build_append_int_noprefix(table_data, 15, 1); /* Length */ build_append_int_noprefix(table_data, 1, 1); /* Version */ build_append_int_noprefix(table_data, i + 1, 4); /* ACPI Processor= ID */ - build_append_int_noprefix(table_data, i, 4); /* Core ID */ + build_append_int_noprefix(table_data, arch_id, 4); /* Core ID */ build_append_int_noprefix(table_data, 1, 4); /* Flags */ } =20 @@ -159,9 +163,11 @@ build_madt(GArray *table_data, BIOSLinker *linker, Loo= ngArchMachineState *lams) static void build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) { - uint64_t i; + int i, arch_id; LoongArchMachineState *lams =3D LOONGARCH_MACHINE(machine); MachineState *ms =3D MACHINE(lams); + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + const CPUArchIdList *arch_ids =3D mc->possible_cpu_arch_ids(ms); AcpiTable table =3D { .sig =3D "SRAT", .rev =3D 1, .oem_id =3D lams->o= em_id, .oem_table_id =3D lams->oem_table_id }; =20 @@ -169,13 +175,15 @@ build_srat(GArray *table_data, BIOSLinker *linker, Ma= chineState *machine) build_append_int_noprefix(table_data, 1, 4); /* Reserved */ build_append_int_noprefix(table_data, 0, 8); /* Reserved */ =20 - for (i =3D 0; i < ms->smp.cpus; ++i) { + for (i =3D 0; i < arch_ids->len; ++i) { + arch_id =3D arch_ids->cpus[i].arch_id; + /* Processor Local APIC/SAPIC Affinity Structure */ build_append_int_noprefix(table_data, 0, 1); /* Type */ build_append_int_noprefix(table_data, 16, 1); /* Length */ /* Proximity Domain [7:0] */ build_append_int_noprefix(table_data, 0, 1); - build_append_int_noprefix(table_data, i, 1); /* APIC ID */ + build_append_int_noprefix(table_data, arch_id, 1); /* APIC ID */ /* Flags, Table 5-36 */ build_append_int_noprefix(table_data, 1, 4); build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index ceddec1b23..ced5a862f8 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -771,6 +771,9 @@ static void loongarch_init(MachineState *machine) LoongArchMachineState *lams =3D LOONGARCH_MACHINE(machine); int i; hwaddr fdt_base; + const CPUArchIdList *possible_cpus; + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + CPUState *cpu; =20 if (!cpu_model) { cpu_model =3D LOONGARCH_CPU_TYPE_NAME("la464"); @@ -787,8 +790,12 @@ static void loongarch_init(MachineState *machine) } create_fdt(lams); /* Init CPUs */ - for (i =3D 0; i < machine->smp.cpus; i++) { - cpu_create(machine->cpu_type); + + possible_cpus =3D mc->possible_cpu_arch_ids(machine); + for (i =3D 0; i < possible_cpus->len; i++) { + cpu =3D cpu_create(machine->cpu_type); + cpu->cpu_index =3D i; + machine->possible_cpus->cpus[i].cpu =3D OBJECT(cpu); } fdt_add_cpu_nodes(lams); /* Add memory region */ @@ -1022,6 +1029,28 @@ static HotplugHandler *virt_machine_get_hotplug_hand= ler(MachineState *machine, return NULL; } =20 +static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) +{ + int n; + unsigned int max_cpus =3D ms->smp.max_cpus; + + if (ms->possible_cpus) { + assert(ms->possible_cpus->len =3D=3D max_cpus); + return ms->possible_cpus; + } + + ms->possible_cpus =3D g_malloc0(sizeof(CPUArchIdList) + + sizeof(CPUArchId) * max_cpus); + ms->possible_cpus->len =3D max_cpus; + for (n =3D 0; n < ms->possible_cpus->len; n++) { + ms->possible_cpus->cpus[n].type =3D ms->cpu_type; + ms->possible_cpus->cpus[n].arch_id =3D n; + ms->possible_cpus->cpus[n].props.has_core_id =3D true; + ms->possible_cpus->cpus[n].props.core_id =3D n % ms->smp.cores; + } + return ms->possible_cpus; +} + static void loongarch_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -1038,6 +1067,7 @@ static void loongarch_class_init(ObjectClass *oc, voi= d *data) mc->block_default_type =3D IF_VIRTIO; mc->default_boot_order =3D "c"; mc->no_cdrom =3D 1; + mc->possible_cpu_arch_ids =3D virt_possible_cpu_arch_ids; mc->get_hotplug_handler =3D virt_machine_get_hotplug_handler; mc->default_nic =3D "virtio-net-pci"; hc->plug =3D loongarch_machine_device_plug_cb; --=20 2.39.1 From nobody Sun May 19 10:57:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686909766766518.8484668437178; Fri, 16 Jun 2023 03:02:46 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qA6HU-0007Hd-0l; Fri, 16 Jun 2023 06:02:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qA6HR-0007GQ-6m for qemu-devel@nongnu.org; Fri, 16 Jun 2023 06:02:09 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qA6HN-0000dU-7O for qemu-devel@nongnu.org; Fri, 16 Jun 2023 06:02:08 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8DxTusZM4xkQu8FAA--.12586S3; Fri, 16 Jun 2023 18:02:01 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxFOQWM4xkSygdAA--.17116S4; Fri, 16 Jun 2023 18:02:00 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, Tianrui Zhao Subject: [PULL 2/5] hw/intc: Set physical cpuid route for LoongArch ipi device Date: Fri, 16 Jun 2023 18:01:55 +0800 Message-Id: <20230616100158.1845239-3-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230616100158.1845239-1-gaosong@loongson.cn> References: <20230616100158.1845239-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8DxFOQWM4xkSygdAA--.17116S4 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686909767469100001 Content-Type: text/plain; charset="utf-8" From: Tianrui Zhao LoongArch ipi device uses physical cpuid to route to different vcpus rather logical cpuid, and the physical cpuid is the same with cpuid in acpi dsdt and srat table. Reviewed-by: Song Gao Signed-off-by: Tianrui Zhao Signed-off-by: Song Gao Message-Id: <20230613120552.2471420-3-zhaotianrui@loongson.cn> --- hw/intc/loongarch_ipi.c | 44 ++++++++++++++++++++++++++++++++++------- hw/loongarch/virt.c | 1 + target/loongarch/cpu.h | 2 ++ 3 files changed, 40 insertions(+), 7 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 3e45381652..67858b521c 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -17,6 +17,8 @@ #include "target/loongarch/internals.h" #include "trace.h" =20 +static void loongarch_ipi_writel(void *, hwaddr, uint64_t, unsigned); + static uint64_t loongarch_ipi_readl(void *opaque, hwaddr addr, unsigned si= ze) { IPICore *s =3D opaque; @@ -75,13 +77,42 @@ static void send_ipi_data(CPULoongArchState *env, uint6= 4_t val, hwaddr addr) data, MEMTXATTRS_UNSPECIFIED, NULL); } =20 +static int archid_cmp(const void *a, const void *b) +{ + CPUArchId *archid_a =3D (CPUArchId *)a; + CPUArchId *archid_b =3D (CPUArchId *)b; + + return archid_a->arch_id - archid_b->arch_id; +} + +static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id) +{ + CPUArchId apic_id, *found_cpu; + + apic_id.arch_id =3D id; + found_cpu =3D bsearch(&apic_id, ms->possible_cpus->cpus, + ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), + archid_cmp); + + return found_cpu; +} + +static CPUState *ipi_getcpu(int arch_id) +{ + MachineState *machine =3D MACHINE(qdev_get_machine()); + CPUArchId *archid; + + archid =3D find_cpu_by_archid(machine, arch_id); + return CPU(archid->cpu); +} + static void ipi_send(uint64_t val) { uint32_t cpuid; uint8_t vector; - CPULoongArchState *env; CPUState *cs; LoongArchCPU *cpu; + LoongArchIPI *s; =20 cpuid =3D extract32(val, 16, 10); if (cpuid >=3D LOONGARCH_MAX_CPUS) { @@ -92,11 +123,10 @@ static void ipi_send(uint64_t val) /* IPI status vector */ vector =3D extract8(val, 0, 5); =20 - cs =3D qemu_get_cpu(cpuid); + cs =3D ipi_getcpu(cpuid); cpu =3D LOONGARCH_CPU(cs); - env =3D &cpu->env; - address_space_stl(&env->address_space_iocsr, 0x1008, - BIT(vector), MEMTXATTRS_UNSPECIFIED, NULL); + s =3D LOONGARCH_IPI(cpu->env.ipistate); + loongarch_ipi_writel(&s->ipi_core, CORE_SET_OFF, BIT(vector), 4); } =20 static void mail_send(uint64_t val) @@ -114,7 +144,7 @@ static void mail_send(uint64_t val) } =20 addr =3D 0x1020 + (val & 0x1c); - cs =3D qemu_get_cpu(cpuid); + cs =3D ipi_getcpu(cpuid); cpu =3D LOONGARCH_CPU(cs); env =3D &cpu->env; send_ipi_data(env, val, addr); @@ -135,7 +165,7 @@ static void any_send(uint64_t val) } =20 addr =3D val & 0xffff; - cs =3D qemu_get_cpu(cpuid); + cs =3D ipi_getcpu(cpuid); cpu =3D LOONGARCH_CPU(cs); env =3D &cpu->env; send_ipi_data(env, val, addr); diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index ced5a862f8..17bc37bccd 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -617,6 +617,7 @@ static void loongarch_irq_init(LoongArchMachineState *l= ams) memory_region_add_subregion(&env->system_iocsr, APIC_BASE, sysbus_mmio_get_region(SYS_BUS_DEVICE(exti= oi), cpu)); + env->ipistate =3D ipi; } =20 /* diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 1f37e36b7c..b23f38c3d5 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -351,6 +351,8 @@ typedef struct CPUArchState { MemoryRegion iocsr_mem; bool load_elf; uint64_t elf_address; + /* Store ipistate to access from this struct */ + DeviceState *ipistate; #endif } CPULoongArchState; =20 --=20 2.39.1 From nobody Sun May 19 10:57:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686909821415157.65321193011573; Fri, 16 Jun 2023 03:03:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qA6HT-0007HO-QR; Fri, 16 Jun 2023 06:02:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qA6HP-0007Fz-Uc for qemu-devel@nongnu.org; Fri, 16 Jun 2023 06:02:07 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qA6HM-0000dZ-Se for qemu-devel@nongnu.org; Fri, 16 Jun 2023 06:02:07 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8BxZ+kZM4xkRO8FAA--.10715S3; Fri, 16 Jun 2023 18:02:01 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxFOQWM4xkSygdAA--.17116S5; Fri, 16 Jun 2023 18:02:00 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, Tianrui Zhao Subject: [PULL 3/5] hw/loongarch: Add numa support Date: Fri, 16 Jun 2023 18:01:56 +0800 Message-Id: <20230616100158.1845239-4-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230616100158.1845239-1-gaosong@loongson.cn> References: <20230616100158.1845239-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8DxFOQWM4xkSygdAA--.17116S5 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686909823017100006 Content-Type: text/plain; charset="utf-8" From: Tianrui Zhao 1. Implement some functions for LoongArch numa support; 2. Implement fdt_add_memory_node() for fdt; 3. build_srat() fills node_id and adds build numa memory. Reviewed-by: Song Gao Signed-off-by: Tianrui Zhao Signed-off-by: Song Gao Message-Id: <20230613122613.2471743-1-zhaotianrui@loongson.cn> --- hw/loongarch/Kconfig | 1 + hw/loongarch/acpi-build.c | 60 +++++++++++++++++----- hw/loongarch/virt.c | 102 +++++++++++++++++++++++++++++++++----- 3 files changed, 139 insertions(+), 24 deletions(-) diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig index eb112af990..1e7c5b43c5 100644 --- a/hw/loongarch/Kconfig +++ b/hw/loongarch/Kconfig @@ -21,3 +21,4 @@ config LOONGARCH_VIRT select FW_CFG_DMA select DIMM select PFLASH_CFI01 + select ACPI_HMAT diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c index 232344e1c7..f526f3abba 100644 --- a/hw/loongarch/acpi-build.c +++ b/hw/loongarch/acpi-build.c @@ -34,6 +34,7 @@ #include "sysemu/tpm.h" #include "hw/platform-bus.h" #include "hw/acpi/aml-build.h" +#include "hw/acpi/hmat.h" =20 #define ACPI_BUILD_ALIGN_SIZE 0x1000 #define ACPI_BUILD_TABLE_SIZE 0x20000 @@ -163,11 +164,12 @@ build_madt(GArray *table_data, BIOSLinker *linker, Lo= ongArchMachineState *lams) static void build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) { - int i, arch_id; + int i, arch_id, node_id; + uint64_t mem_len, mem_base; + int nb_numa_nodes =3D machine->numa_state->num_nodes; LoongArchMachineState *lams =3D LOONGARCH_MACHINE(machine); - MachineState *ms =3D MACHINE(lams); - MachineClass *mc =3D MACHINE_GET_CLASS(ms); - const CPUArchIdList *arch_ids =3D mc->possible_cpu_arch_ids(ms); + MachineClass *mc =3D MACHINE_GET_CLASS(lams); + const CPUArchIdList *arch_ids =3D mc->possible_cpu_arch_ids(machine); AcpiTable table =3D { .sig =3D "SRAT", .rev =3D 1, .oem_id =3D lams->o= em_id, .oem_table_id =3D lams->oem_table_id }; =20 @@ -177,12 +179,13 @@ build_srat(GArray *table_data, BIOSLinker *linker, Ma= chineState *machine) =20 for (i =3D 0; i < arch_ids->len; ++i) { arch_id =3D arch_ids->cpus[i].arch_id; + node_id =3D arch_ids->cpus[i].props.node_id; =20 /* Processor Local APIC/SAPIC Affinity Structure */ build_append_int_noprefix(table_data, 0, 1); /* Type */ build_append_int_noprefix(table_data, 16, 1); /* Length */ /* Proximity Domain [7:0] */ - build_append_int_noprefix(table_data, 0, 1); + build_append_int_noprefix(table_data, node_id, 1); build_append_int_noprefix(table_data, arch_id, 1); /* APIC ID */ /* Flags, Table 5-36 */ build_append_int_noprefix(table_data, 1, 4); @@ -192,16 +195,36 @@ build_srat(GArray *table_data, BIOSLinker *linker, Ma= chineState *machine) build_append_int_noprefix(table_data, 0, 4); /* Reserved */ } =20 + /* Node0 */ build_srat_memory(table_data, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0, MEM_AFFINITY_ENABLED); + mem_base =3D VIRT_HIGHMEM_BASE; + if (!nb_numa_nodes) { + mem_len =3D machine->ram_size - VIRT_LOWMEM_SIZE; + } else { + mem_len =3D machine->numa_state->nodes[0].node_mem - VIRT_LOWMEM_S= IZE; + } + if (mem_len) + build_srat_memory(table_data, mem_base, mem_len, 0, MEM_AFFINITY_E= NABLED); + + /* Node1 - Nodemax */ + if (nb_numa_nodes) { + mem_base +=3D mem_len; + for (i =3D 1; i < nb_numa_nodes; ++i) { + if (machine->numa_state->nodes[i].node_mem > 0) { + build_srat_memory(table_data, mem_base, + machine->numa_state->nodes[i].node_mem, = i, + MEM_AFFINITY_ENABLED); + mem_base +=3D machine->numa_state->nodes[i].node_mem; + } + } + } =20 - build_srat_memory(table_data, VIRT_HIGHMEM_BASE, machine->ram_size - V= IRT_LOWMEM_SIZE, - 0, MEM_AFFINITY_ENABLED); - - if (ms->device_memory) { - build_srat_memory(table_data, ms->device_memory->base, - memory_region_size(&ms->device_memory->mr), - 0, MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENAB= LED); + if (machine->device_memory) { + build_srat_memory(table_data, machine->device_memory->base, + memory_region_size(&machine->device_memory->mr), + nb_numa_nodes - 1, + MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED= ); } =20 acpi_table_end(linker, &table); @@ -417,6 +440,19 @@ static void acpi_build(AcpiBuildTables *tables, Machin= eState *machine) acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, machine); =20 + if (machine->numa_state->num_nodes) { + if (machine->numa_state->have_numa_distance) { + acpi_add_table(table_offsets, tables_blob); + build_slit(tables_blob, tables->linker, machine, lams->oem_id, + lams->oem_table_id); + } + if (machine->numa_state->hmat_enabled) { + acpi_add_table(table_offsets, tables_blob); + build_hmat(tables_blob, tables->linker, machine->numa_state, + lams->oem_id, lams->oem_table_id); + } + } + acpi_add_table(table_offsets, tables_blob); { AcpiMcfgInfo mcfg =3D { diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 17bc37bccd..1d5c764408 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -164,11 +164,16 @@ static void fdt_add_cpu_nodes(const LoongArchMachineS= tate *lams) for (num =3D smp_cpus - 1; num >=3D 0; num--) { char *nodename =3D g_strdup_printf("/cpus/cpu@%d", num); LoongArchCPU *cpu =3D LOONGARCH_CPU(qemu_get_cpu(num)); + CPUState *cs =3D CPU(cpu); =20 qemu_fdt_add_subnode(ms->fdt, nodename); qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", cpu->dtb_compatible); + if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { + qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", + ms->possible_cpus->cpus[cs->cpu_index].props.node_id); + } qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", qemu_fdt_alloc_phandle(ms->fdt)); @@ -280,6 +285,22 @@ static void fdt_add_irqchip_node(LoongArchMachineState= *lams) g_free(nodename); } =20 +static void fdt_add_memory_node(MachineState *ms, + uint64_t base, uint64_t size, int node_id) +{ + char *nodename =3D g_strdup_printf("/memory@%" PRIx64, base); + + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 2, base, 2, size); + qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); + + if (ms->numa_state && ms->numa_state->num_nodes) { + qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); + } + + g_free(nodename); +} + #define PM_BASE 0x10080000 #define PM_SIZE 0x100 #define PM_CTRL 0x10 @@ -767,14 +788,17 @@ static void loongarch_init(MachineState *machine) const char *cpu_model =3D machine->cpu_type; ram_addr_t offset =3D 0; ram_addr_t ram_size =3D machine->ram_size; - uint64_t highram_size =3D 0; + uint64_t highram_size =3D 0, phyAddr =3D 0; MemoryRegion *address_space_mem =3D get_system_memory(); LoongArchMachineState *lams =3D LOONGARCH_MACHINE(machine); + int nb_numa_nodes =3D machine->numa_state->num_nodes; + NodeInfo *numa_info =3D machine->numa_state->nodes; int i; hwaddr fdt_base; const CPUArchIdList *possible_cpus; MachineClass *mc =3D MACHINE_GET_CLASS(machine); CPUState *cpu; + char *ramName =3D NULL; =20 if (!cpu_model) { cpu_model =3D LOONGARCH_CPU_TYPE_NAME("la464"); @@ -799,17 +823,43 @@ static void loongarch_init(MachineState *machine) machine->possible_cpus->cpus[i].cpu =3D OBJECT(cpu); } fdt_add_cpu_nodes(lams); - /* Add memory region */ - memory_region_init_alias(&lams->lowmem, NULL, "loongarch.lowram", - machine->ram, 0, 256 * MiB); - memory_region_add_subregion(address_space_mem, offset, &lams->lowmem); - offset +=3D 256 * MiB; - memmap_add_entry(0, 256 * MiB, 1); - highram_size =3D ram_size - 256 * MiB; - memory_region_init_alias(&lams->highmem, NULL, "loongarch.highmem", - machine->ram, offset, highram_size); - memory_region_add_subregion(address_space_mem, 0x90000000, &lams->high= mem); - memmap_add_entry(0x90000000, highram_size, 1); + + /* Node0 memory */ + memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1); + fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0); + memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram", + machine->ram, offset, VIRT_LOWMEM_SIZE); + memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem); + + offset +=3D VIRT_LOWMEM_SIZE; + if (nb_numa_nodes > 0) { + assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE); + highram_size =3D numa_info[0].node_mem - VIRT_LOWMEM_SIZE; + } else { + highram_size =3D ram_size - VIRT_LOWMEM_SIZE; + } + phyAddr =3D VIRT_HIGHMEM_BASE; + memmap_add_entry(phyAddr, highram_size, 1); + fdt_add_memory_node(machine, phyAddr, highram_size, 0); + memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highra= m", + machine->ram, offset, highram_size); + memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem= ); + + /* Node1 - Nodemax memory */ + offset +=3D highram_size; + phyAddr +=3D highram_size; + + for (i =3D 1; i < nb_numa_nodes; i++) { + MemoryRegion *nodemem =3D g_new(MemoryRegion, 1); + ramName =3D g_strdup_printf("loongarch.node%d.ram", i); + memory_region_init_alias(nodemem, NULL, ramName, machine->ram, + offset, numa_info[i].node_mem); + memory_region_add_subregion(address_space_mem, phyAddr, nodemem); + memmap_add_entry(phyAddr, numa_info[i].node_mem, 1); + fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i); + offset +=3D numa_info[i].node_mem; + phyAddr +=3D numa_info[i].node_mem; + } =20 /* initialize device memory address space */ if (machine->ram_size < machine->maxram_size) { @@ -1052,6 +1102,29 @@ static const CPUArchIdList *virt_possible_cpu_arch_i= ds(MachineState *ms) return ms->possible_cpus; } =20 +static CpuInstanceProperties +virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + const CPUArchIdList *possible_cpus =3D mc->possible_cpu_arch_ids(ms); + + assert(cpu_index < possible_cpus->len); + return possible_cpus->cpus[cpu_index].props; +} + +static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int id= x) +{ + int64_t nidx =3D 0; + + if (ms->numa_state->num_nodes) { + nidx =3D idx / (ms->smp.cpus / ms->numa_state->num_nodes); + if (ms->numa_state->num_nodes <=3D nidx) { + nidx =3D ms->numa_state->num_nodes - 1; + } + } + return nidx; +} + static void loongarch_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -1069,6 +1142,11 @@ static void loongarch_class_init(ObjectClass *oc, vo= id *data) mc->default_boot_order =3D "c"; mc->no_cdrom =3D 1; mc->possible_cpu_arch_ids =3D virt_possible_cpu_arch_ids; + mc->cpu_index_to_instance_props =3D virt_cpu_index_to_props; + mc->get_default_cpu_node_id =3D virt_get_default_cpu_node_id; + mc->numa_mem_supported =3D true; + mc->auto_enable_numa_with_memhp =3D true; + mc->auto_enable_numa_with_memdev =3D true; mc->get_hotplug_handler =3D virt_machine_get_hotplug_handler; mc->default_nic =3D "virtio-net-pci"; hc->plug =3D loongarch_machine_device_plug_cb; --=20 2.39.1 From nobody Sun May 19 10:57:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686909804331795.2291170233731; Fri, 16 Jun 2023 03:03:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qA6HT-0007H2-4y; Fri, 16 Jun 2023 06:02:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qA6HP-0007Fx-OO for qemu-devel@nongnu.org; Fri, 16 Jun 2023 06:02:07 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qA6HM-0000dY-V3 for qemu-devel@nongnu.org; Fri, 16 Jun 2023 06:02:07 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8CxvOoZM4xkR+8FAA--.12650S3; Fri, 16 Jun 2023 18:02:01 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxFOQWM4xkSygdAA--.17116S6; Fri, 16 Jun 2023 18:02:01 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, Tianrui Zhao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 4/5] hw/loongarch: Supplement cpu topology arguments Date: Fri, 16 Jun 2023 18:01:57 +0800 Message-Id: <20230616100158.1845239-5-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230616100158.1845239-1-gaosong@loongson.cn> References: <20230616100158.1845239-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8DxFOQWM4xkSygdAA--.17116S6 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686909804872100001 From: Tianrui Zhao Supplement LoongArch cpu topology arguments, including support socket and threads per core. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Song Gao Signed-off-by: Tianrui Zhao Signed-off-by: Song Gao Message-Id: <20230613123251.2471878-1-zhaotianrui@loongson.cn> --- hw/loongarch/acpi-build.c | 4 ++++ hw/loongarch/virt.c | 9 ++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c index f526f3abba..0b62c3a2f7 100644 --- a/hw/loongarch/acpi-build.c +++ b/hw/loongarch/acpi-build.c @@ -437,6 +437,10 @@ static void acpi_build(AcpiBuildTables *tables, Machin= eState *machine) acpi_add_table(table_offsets, tables_blob); build_madt(tables_blob, tables->linker, lams); =20 + acpi_add_table(table_offsets, tables_blob); + build_pptt(tables_blob, tables->linker, machine, + lams->oem_id, lams->oem_table_id); + acpi_add_table(table_offsets, tables_blob); build_srat(tables_blob, tables->linker, machine); =20 diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 1d5c764408..ca8824b6ef 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -1096,8 +1096,15 @@ static const CPUArchIdList *virt_possible_cpu_arch_i= ds(MachineState *ms) for (n =3D 0; n < ms->possible_cpus->len; n++) { ms->possible_cpus->cpus[n].type =3D ms->cpu_type; ms->possible_cpus->cpus[n].arch_id =3D n; + + ms->possible_cpus->cpus[n].props.has_socket_id =3D true; + ms->possible_cpus->cpus[n].props.socket_id =3D + n / (ms->smp.cores * ms->smp.threads); ms->possible_cpus->cpus[n].props.has_core_id =3D true; - ms->possible_cpus->cpus[n].props.core_id =3D n % ms->smp.cores; + ms->possible_cpus->cpus[n].props.core_id =3D + n / ms->smp.threads % ms->smp.cores; + ms->possible_cpus->cpus[n].props.has_thread_id =3D true; + ms->possible_cpus->cpus[n].props.thread_id =3D n % ms->smp.threads; } return ms->possible_cpus; } --=20 2.39.1 From nobody Sun May 19 10:57:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686909774759499.77018881660774; Fri, 16 Jun 2023 03:02:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qA6HU-0007I9-Ea; Fri, 16 Jun 2023 06:02:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qA6HR-0007GG-0b for qemu-devel@nongnu.org; Fri, 16 Jun 2023 06:02:09 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qA6HM-0000du-VG for qemu-devel@nongnu.org; Fri, 16 Jun 2023 06:02:08 -0400 Received: from loongson.cn (unknown [10.2.5.185]) by gateway (Coremail) with SMTP id _____8AxW+oaM4xkSu8FAA--.12706S3; Fri, 16 Jun 2023 18:02:02 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.185]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxFOQWM4xkSygdAA--.17116S7; Fri, 16 Jun 2023 18:02:01 +0800 (CST) From: Song Gao To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, Jiajie Chen Subject: [PULL 5/5] target/loongarch: Fix CSR.DMW0-3.VSEG check Date: Fri, 16 Jun 2023 18:01:58 +0800 Message-Id: <20230616100158.1845239-6-gaosong@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230616100158.1845239-1-gaosong@loongson.cn> References: <20230616100158.1845239-1-gaosong@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8DxFOQWM4xkSygdAA--.17116S7 X-CM-SenderInfo: 5jdr20tqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686909776533100003 Content-Type: text/plain; charset="utf-8" From: Jiajie Chen The previous code checks whether the highest 16 bits of virtual address equal to that of CSR.DMW0-3. This is incorrect according to the spec, and is corrected to compare only the highest four bits instead. Signed-off-by: Jiajie Chen Reviewed-by: Song Gao Message-Id: <20230614065556.2397513-1-c@jia.je> Signed-off-by: Song Gao --- target/loongarch/tlb_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c index cce1db1e0a..6e00190547 100644 --- a/target/loongarch/tlb_helper.c +++ b/target/loongarch/tlb_helper.c @@ -185,10 +185,10 @@ static int get_physical_address(CPULoongArchState *en= v, hwaddr *physical, } =20 plv =3D kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT); - base_v =3D address >> TARGET_VIRT_ADDR_SPACE_BITS; + base_v =3D address >> R_CSR_DMW_VSEG_SHIFT; /* Check direct map window */ for (int i =3D 0; i < 4; i++) { - base_c =3D env->CSR_DMW[i] >> TARGET_VIRT_ADDR_SPACE_BITS; + base_c =3D FIELD_EX64(env->CSR_DMW[i], CSR_DMW, VSEG); if ((plv & env->CSR_DMW[i]) && (base_c =3D=3D base_v)) { *physical =3D dmw_va2pa(address); *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; --=20 2.39.1