From nobody Sun May 19 09:08:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686850664188654.4775181364402; Thu, 15 Jun 2023 10:37:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9qt4-0000cX-3z; Thu, 15 Jun 2023 13:35:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9qsu-0000Zr-Re; Thu, 15 Jun 2023 13:35:48 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3] helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9qsp-0007gQ-JS; Thu, 15 Jun 2023 13:35:48 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4QhqFP44Z3z4x0G; Fri, 16 Jun 2023 03:35:37 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4QhqFM4TqKz4x0B; Fri, 16 Jun 2023 03:35:35 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson , Ninad Palsule , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 1/6] hw/arm/aspeed: Add VPD data for Rainier machine Date: Thu, 15 Jun 2023 19:35:20 +0200 Message-Id: <20230615173525.428831-2-clg@kaod.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230615173525.428831-1-clg@kaod.org> References: <20230615173525.428831-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=xCJj=CD=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -39 X-Spam_score: -4.0 X-Spam_bar: ---- X-Spam_report: (-4.0 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686850665796100003 From: Ninad Palsule The current modeling of Rainier machine creates zero filled VPDs(EEPROMs). This makes some services and applications unhappy and causing them to fail. Hence this drop adds some fabricated data for system and BMC FRU so that vpd services are happy and active. Tested: - The system-vpd.service is active. - VPD service related to bmc is active. Signed-off-by: Ninad Palsule Reviewed-by: C=C3=A9dric Le Goater [ clg: commit title cleanup ] Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_eeprom.h | 5 +++++ hw/arm/aspeed.c | 6 ++++-- hw/arm/aspeed_eeprom.c | 45 +++++++++++++++++++++++++++++++++++++++++- 3 files changed, 53 insertions(+), 3 deletions(-) diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h index 86db6f0479b7..bbf9e54365b8 100644 --- a/hw/arm/aspeed_eeprom.h +++ b/hw/arm/aspeed_eeprom.h @@ -22,4 +22,9 @@ extern const size_t fby35_bmc_fruid_len; extern const uint8_t yosemitev2_bmc_fruid[]; extern const size_t yosemitev2_bmc_fruid_len; =20 +extern const uint8_t rainier_bb_fruid[]; +extern const size_t rainier_bb_fruid_len; +extern const uint8_t rainier_bmc_fruid[]; +extern const size_t rainier_bmc_fruid_len; + #endif diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 0b29028fe115..bfc2070bd2ed 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -788,8 +788,10 @@ static void rainier_bmc_i2c_init(AspeedMachineState *b= mc) 0x48); i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, 0x4a); - at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB); - at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB); + at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, + 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len= ); + at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, + 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_l= en); create_pca9552(soc, 8, 0x60); create_pca9552(soc, 8, 0x61); /* Bus 8: ucd90320@11 */ diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c index dc33a88a5466..ace5266cec91 100644 --- a/hw/arm/aspeed_eeprom.c +++ b/hw/arm/aspeed_eeprom.c @@ -119,9 +119,52 @@ const uint8_t yosemitev2_bmc_fruid[] =3D { 0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45, }; =20 +const uint8_t rainier_bb_fruid[] =3D { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, + 0x28, 0x00, 0x52, 0x54, 0x04, 0x56, 0x48, 0x44, 0x52, 0x56, 0x44, 0x02, + 0x01, 0x00, 0x50, 0x54, 0x0e, 0x56, 0x54, 0x4f, 0x43, 0x00, 0x00, 0x37, + 0x00, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x46, 0x08, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x00, 0x52, 0x54, + 0x04, 0x56, 0x54, 0x4f, 0x43, 0x50, 0x54, 0x38, 0x56, 0x49, 0x4e, 0x49, + 0x00, 0x00, 0x81, 0x00, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x56, 0x53, + 0x59, 0x53, 0x00, 0x00, 0xbb, 0x00, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x56, 0x43, 0x45, 0x4e, 0x00, 0x00, 0xe2, 0x00, 0x27, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x56, 0x53, 0x42, 0x50, 0x00, 0x00, 0x09, 0x01, 0x19, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x50, 0x46, 0x01, 0x00, 0x00, 0x00, 0x36, 0x00, + 0x52, 0x54, 0x04, 0x56, 0x49, 0x4e, 0x49, 0x44, 0x52, 0x04, 0x44, 0x45, + 0x53, 0x43, 0x48, 0x57, 0x02, 0x30, 0x31, 0x43, 0x43, 0x04, 0x33, 0x34, + 0x35, 0x36, 0x46, 0x4e, 0x04, 0x46, 0x52, 0x34, 0x39, 0x53, 0x4e, 0x04, + 0x53, 0x52, 0x31, 0x32, 0x50, 0x4e, 0x04, 0x50, 0x52, 0x39, 0x39, 0x50, + 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x00, 0x52, 0x54, + 0x04, 0x56, 0x53, 0x59, 0x53, 0x53, 0x45, 0x07, 0x49, 0x42, 0x4d, 0x53, + 0x59, 0x53, 0x31, 0x54, 0x4d, 0x08, 0x32, 0x32, 0x32, 0x32, 0x2d, 0x32, + 0x32, 0x32, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, + 0x00, 0x52, 0x54, 0x04, 0x56, 0x43, 0x45, 0x4e, 0x53, 0x45, 0x07, 0x31, + 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x46, 0x43, 0x08, 0x31, 0x31, 0x31, + 0x31, 0x2d, 0x31, 0x31, 0x31, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x15, 0x00, 0x52, 0x54, 0x04, 0x56, 0x53, 0x42, 0x50, 0x49, + 0x4d, 0x04, 0x50, 0x00, 0x10, 0x01, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, + 0x00, 0x00, +}; + +/* Rainier BMC FRU */ +const uint8_t rainier_bmc_fruid[] =3D { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, + 0x28, 0x00, 0x52, 0x54, 0x04, 0x56, 0x48, 0x44, 0x52, 0x56, 0x44, 0x02, + 0x01, 0x00, 0x50, 0x54, 0x0e, 0x56, 0x54, 0x4f, 0x43, 0x00, 0x00, 0x37, + 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x46, 0x08, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x52, 0x54, + 0x04, 0x56, 0x54, 0x4f, 0x43, 0x50, 0x54, 0x0e, 0x56, 0x49, 0x4e, 0x49, + 0x00, 0x00, 0x57, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x46, + 0x01, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x52, 0x54, 0x04, 0x56, 0x49, 0x4e, + 0x49, 0x44, 0x52, 0x04, 0x44, 0x45, 0x53, 0x43, 0x48, 0x57, 0x02, 0x30, + 0x31, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + const size_t tiogapass_bmc_fruid_len =3D sizeof(tiogapass_bmc_fruid); const size_t fby35_nic_fruid_len =3D sizeof(fby35_nic_fruid); const size_t fby35_bb_fruid_len =3D sizeof(fby35_bb_fruid); const size_t fby35_bmc_fruid_len =3D sizeof(fby35_bmc_fruid); - const size_t yosemitev2_bmc_fruid_len =3D sizeof(yosemitev2_bmc_fruid); +const size_t rainier_bb_fruid_len =3D sizeof(rainier_bb_fruid); +const size_t rainier_bmc_fruid_len =3D sizeof(rainier_bmc_fruid); --=20 2.40.1 From nobody Sun May 19 09:08:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686850737716216.7636719564008; Thu, 15 Jun 2023 10:38:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9qt7-0000et-DS; Thu, 15 Jun 2023 13:36:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9qt1-0000bn-Eo; Thu, 15 Jun 2023 13:35:55 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9qsw-0007h9-La; Thu, 15 Jun 2023 13:35:53 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4QhqFX1TqSz4x0K; Fri, 16 Jun 2023 03:35:44 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4QhqFQ0pTXz4x08; Fri, 16 Jun 2023 03:35:37 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Steven Lee , Joel Stanley , qemu-stable@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Thomas Huth , Francisco Iglesias Subject: [PULL 2/6] aspeed/hace: Initialize g_autofree pointer Date: Thu, 15 Jun 2023 19:35:21 +0200 Message-Id: <20230615173525.428831-3-clg@kaod.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230615173525.428831-1-clg@kaod.org> References: <20230615173525.428831-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=xCJj=CD=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686850740581100006 As mentioned in docs/devel/style.rst "Automatic memory deallocation": * Variables declared with g_auto* MUST always be initialized, otherwise the cleanup function will use uninitialized stack memory This avoids QEMU to coredump when running the "hash test" command under Zephyr. Cc: Steven Lee Cc: Joel Stanley Cc: qemu-stable@nongnu.org Fixes: c5475b3f9a ("hw: Model ASPEED's Hash and Crypto Engine") Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Thomas Huth Reviewed-by: Francisco Iglesias Message-Id: <20230421131547.2177449-1-clg@kaod.org> Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Signed-off-by: C=C3=A9dric Le Goater --- hw/misc/aspeed_hace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 12a761f1f55d..b07506ec04ef 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -189,7 +189,7 @@ static void do_hash_operation(AspeedHACEState *s, int a= lgo, bool sg_mode, bool acc_mode) { struct iovec iov[ASPEED_HACE_MAX_SG]; - g_autofree uint8_t *digest_buf; + g_autofree uint8_t *digest_buf =3D NULL; size_t digest_len =3D 0; int niov =3D 0; int i; --=20 2.40.1 From nobody Sun May 19 09:08:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686850738056989.1034691047158; Thu, 15 Jun 2023 10:38:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9qt6-0000dd-2V; Thu, 15 Jun 2023 13:36:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9qt1-0000bo-FN; Thu, 15 Jun 2023 13:35:55 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9qsx-0007ha-OV; Thu, 15 Jun 2023 13:35:54 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4QhqFb1SHlz4x1R; Fri, 16 Jun 2023 03:35:47 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4QhqFX5LZQz4x0H; Fri, 16 Jun 2023 03:35:44 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Francisco Iglesias , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Joel Stanley Subject: [PULL 3/6] aspeed: Introduce a boot_rom region at the machine level Date: Thu, 15 Jun 2023 19:35:22 +0200 Message-Id: <20230615173525.428831-4-clg@kaod.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230615173525.428831-1-clg@kaod.org> References: <20230615173525.428831-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=xCJj=CD=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686850740083100003 This should also avoid Coverity to report a memory leak warning when the QEMU process exits. See CID 1508061. Reviewed-by: Francisco Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index bfc2070bd2ed..76a1e7303de1 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -40,6 +40,7 @@ struct AspeedMachineState { /* Public */ =20 AspeedSoCState soc; + MemoryRegion boot_rom; bool mmio_exec; char *fmc_model; char *spi_model; @@ -275,15 +276,15 @@ static void write_boot_rom(BlockBackend *blk, hwaddr = addr, size_t rom_size, * Create a ROM and copy the flash contents at the expected address * (0x0). Boots faster than execute-in-place. */ -static void aspeed_install_boot_rom(AspeedSoCState *soc, BlockBackend *blk, +static void aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend = *blk, uint64_t rom_size) { - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); + AspeedSoCState *soc =3D &bmc->soc; =20 - memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", rom_size, + memory_region_init_rom(&bmc->boot_rom, NULL, "aspeed.boot_rom", rom_si= ze, &error_abort); memory_region_add_subregion_overlap(&soc->spi_boot_container, 0, - boot_rom, 1); + &bmc->boot_rom, 1); write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size, &error_abort); } =20 @@ -431,8 +432,7 @@ static void aspeed_machine_init(MachineState *machine) =20 if (mtd0) { uint64_t rom_size =3D memory_region_size(&bmc->soc.spi_boot); - aspeed_install_boot_rom(&bmc->soc, blk_by_legacy_dinfo(mtd0), - rom_size); + aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(mtd0), rom_si= ze); } } =20 --=20 2.40.1 From nobody Sun May 19 09:08:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686850707821749.3408380961572; Thu, 15 Jun 2023 10:38:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9qt6-0000ei-Ng; Thu, 15 Jun 2023 13:36:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9qt4-0000cw-6F; Thu, 15 Jun 2023 13:35:58 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9qt1-0007jb-Ge; Thu, 15 Jun 2023 13:35:57 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4QhqFf4PTVz4x0L; Fri, 16 Jun 2023 03:35:50 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4QhqFb5Jysz4x08; Fri, 16 Jun 2023 03:35:47 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Delevoryas , Joel Stanley Subject: [PULL 4/6] aspeed: Use the boot_rom region of the fby35 machine Date: Thu, 15 Jun 2023 19:35:23 +0200 Message-Id: <20230615173525.428831-5-clg@kaod.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230615173525.428831-1-clg@kaod.org> References: <20230615173525.428831-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=xCJj=CD=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686850709488100001 This change completes commits 5aa281d757 ("aspeed: Introduce a spi_boot region under the SoC") and 8b744a6a47 ("aspeed: Add a boot_rom overlap region in the SoC spi_boot container") which introduced a spi_boot container at the SoC level to map the boot rom region as an overlap. It also fixes a Coverity report (CID 1508061) for a memory leak warning when the QEMU process exits by using an bmc_boot_rom MemoryRegion available at the machine level. Cc: Peter Delevoryas Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/fby35.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c index f4600c290b62..f2ff6c1abfd9 100644 --- a/hw/arm/fby35.c +++ b/hw/arm/fby35.c @@ -70,8 +70,6 @@ static void fby35_bmc_write_boot_rom(DriveInfo *dinfo, Me= moryRegion *mr, =20 static void fby35_bmc_init(Fby35State *s) { - DriveInfo *drive0 =3D drive_get(IF_MTD, 0, 0); - object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3"); =20 memory_region_init(&s->bmc_memory, OBJECT(&s->bmc), "bmc-memory", @@ -95,18 +93,21 @@ static void fby35_bmc_init(Fby35State *s) aspeed_board_init_flashes(&s->bmc.fmc, "n25q00", 2, 0); =20 /* Install first FMC flash content as a boot rom. */ - if (drive0) { - AspeedSMCFlash *fl =3D &s->bmc.fmc.flashes[0]; - MemoryRegion *boot_rom =3D g_new(MemoryRegion, 1); - uint64_t size =3D memory_region_size(&fl->mmio); - - if (!s->mmio_exec) { - memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", - size, &error_abort); - memory_region_add_subregion(&s->bmc_memory, FBY35_BMC_FIRMWARE= _ADDR, - boot_rom); - fby35_bmc_write_boot_rom(drive0, boot_rom, FBY35_BMC_FIRMWARE_= ADDR, - size, &error_abort); + if (!s->mmio_exec) { + DriveInfo *mtd0 =3D drive_get(IF_MTD, 0, 0); + + if (mtd0) { + AspeedSoCState *bmc =3D &s->bmc; + uint64_t rom_size =3D memory_region_size(&bmc->spi_boot); + + memory_region_init_rom(&s->bmc_boot_rom, NULL, "aspeed.boot_ro= m", + rom_size, &error_abort); + memory_region_add_subregion_overlap(&bmc->spi_boot_container, = 0, + &s->bmc_boot_rom, 1); + + fby35_bmc_write_boot_rom(mtd0, &s->bmc_boot_rom, + FBY35_BMC_FIRMWARE_ADDR, + rom_size, &error_abort); } } } --=20 2.40.1 From nobody Sun May 19 09:08:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686850613981385.9344482128098; Thu, 15 Jun 2023 10:36:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9qt8-0000gC-W2; Thu, 15 Jun 2023 13:36:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9qt6-0000e6-6u; Thu, 15 Jun 2023 13:36:00 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9qt2-0007k2-O6; Thu, 15 Jun 2023 13:35:59 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4QhqFj4ZFlz4x0G; Fri, 16 Jun 2023 03:35:53 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4QhqFg1B2Mz4x0H; Fri, 16 Jun 2023 03:35:50 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Abhishek Singh Dagur , Joel Stanley Subject: [PULL 5/6] aspeed: Introduce a "bmc-console" machine option Date: Thu, 15 Jun 2023 19:35:24 +0200 Message-Id: <20230615173525.428831-6-clg@kaod.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230615173525.428831-1-clg@kaod.org> References: <20230615173525.428831-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=xCJj=CD=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686850616056100003 Most of the Aspeed machines use the UART5 device for the boot console, and QEMU connects the first serial Chardev to this SoC device for this purpose. See routine connect_serial_hds_to_uarts(). Nevertheless, some machines use another boot console, such as the fuji, and commit 5d63d0c76c ("hw/arm/aspeed: Allow machine to set UART default") introduced a SoC class attribute 'uart_default' and property to be able to change the boot console device. It was later changed by commit d2b3eaefb4 ("aspeed: Refactor UART init for multi-SoC machines"). The "bmc-console" machine option goes a step further and lets the user defi= ne the UART device from the QEMU command line without introducing a new machine definition. For instance, to use device UART3 (mapped on /dev/ttyS2 under Linux) instead of the default UART5, one would use : -M ast2500-evb,bmc-console=3Duart3 Cc: Abhishek Singh Dagur Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Signed-off-by: C=C3=A9dric Le Goater --- docs/system/arm/aspeed.rst | 11 +++++++++++ hw/arm/aspeed.c | 40 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 49 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index d4e293e7f986..80538422a1a4 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -122,6 +122,11 @@ Options specific to Aspeed machines are : =20 * ``spi-model`` to change the SPI Flash model. =20 + * ``bmc-console`` to change the default console device. Most of the + machines use the ``UART5`` device for a boot console, which is + mapped on ``/dev/ttyS4`` under Linux, but it is not always the + case. + For instance, to start the ``ast2500-evb`` machine with a different FMC chip and a bigger (64M) SPI chip, use : =20 @@ -129,6 +134,12 @@ FMC chip and a bigger (64M) SPI chip, use : =20 -M ast2500-evb,fmc-model=3Dmx25l25635e,spi-model=3Dmx66u51235f =20 +To change the boot console and use device ``UART3`` (``/dev/ttyS2`` +under Linux), use : + +.. code-block:: bash + + -M ast2500-evb,bmc-console=3Duart3 =20 Aspeed minibmc family boards (``ast1030-evb``) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 76a1e7303de1..6880998484cd 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -42,6 +42,7 @@ struct AspeedMachineState { AspeedSoCState soc; MemoryRegion boot_rom; bool mmio_exec; + uint32_t uart_chosen; char *fmc_model; char *spi_model; }; @@ -333,10 +334,11 @@ static void connect_serial_hds_to_uarts(AspeedMachine= State *bmc) AspeedMachineClass *amc =3D ASPEED_MACHINE_GET_CLASS(bmc); AspeedSoCState *s =3D &bmc->soc; AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + int uart_chosen =3D bmc->uart_chosen ? bmc->uart_chosen : amc->uart_de= fault; =20 - aspeed_soc_uart_set_chr(s, amc->uart_default, serial_hd(0)); + aspeed_soc_uart_set_chr(s, uart_chosen, serial_hd(0)); for (int i =3D 1, uart =3D ASPEED_DEV_UART1; i < sc->uarts_num; i++, u= art++) { - if (uart =3D=3D amc->uart_default) { + if (uart =3D=3D uart_chosen) { continue; } aspeed_soc_uart_set_chr(s, uart, serial_hd(i)); @@ -1078,6 +1080,35 @@ static void aspeed_set_spi_model(Object *obj, const = char *value, Error **errp) bmc->spi_model =3D g_strdup(value); } =20 +static char *aspeed_get_bmc_console(Object *obj, Error **errp) +{ + AspeedMachineState *bmc =3D ASPEED_MACHINE(obj); + AspeedMachineClass *amc =3D ASPEED_MACHINE_GET_CLASS(bmc); + int uart_chosen =3D bmc->uart_chosen ? bmc->uart_chosen : amc->uart_de= fault; + + return g_strdup_printf("uart%d", uart_chosen - ASPEED_DEV_UART1 + 1); +} + +static void aspeed_set_bmc_console(Object *obj, const char *value, Error *= *errp) +{ + AspeedMachineState *bmc =3D ASPEED_MACHINE(obj); + AspeedMachineClass *amc =3D ASPEED_MACHINE_GET_CLASS(bmc); + AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(object_class_by_name(amc->soc_= name)); + int val; + + if (sscanf(value, "uart%u", &val) !=3D 1) { + error_setg(errp, "Bad value for \"uart\" property"); + return; + } + + /* The number of UART depends on the SoC */ + if (val < 1 || val > sc->uarts_num) { + error_setg(errp, "\"uart\" should be in range [1 - %d]", sc->uarts= _num); + return; + } + bmc->uart_chosen =3D ASPEED_DEV_UART1 + val - 1; +} + static void aspeed_machine_class_props_init(ObjectClass *oc) { object_class_property_add_bool(oc, "execute-in-place", @@ -1086,6 +1117,11 @@ static void aspeed_machine_class_props_init(ObjectCl= ass *oc) object_class_property_set_description(oc, "execute-in-place", "boot directly from CE0 flash device"); =20 + object_class_property_add_str(oc, "bmc-console", aspeed_get_bmc_consol= e, + aspeed_set_bmc_console); + object_class_property_set_description(oc, "bmc-console", + "Change the default UART to \"uartX\""); + object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model, aspeed_set_fmc_model); object_class_property_set_description(oc, "fmc-model", --=20 2.40.1 From nobody Sun May 19 09:08:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686850614298123.4889513053314; Thu, 15 Jun 2023 10:36:54 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9qt9-0000gS-78; Thu, 15 Jun 2023 13:36:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9qt7-0000fL-PS; Thu, 15 Jun 2023 13:36:01 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3] helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9qt5-0007kh-B3; Thu, 15 Jun 2023 13:36:01 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4QhqFm2dcTz4x0H; Fri, 16 Jun 2023 03:35:56 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4QhqFk1KJ0z4x08; Fri, 16 Jun 2023 03:35:53 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Joel Stanley , Peter Maydell Subject: [PULL 6/6] target/arm: Allow users to set the number of VFP registers Date: Thu, 15 Jun 2023 19:35:25 +0200 Message-Id: <20230615173525.428831-7-clg@kaod.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230615173525.428831-1-clg@kaod.org> References: <20230615173525.428831-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=xCJj=CD=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -39 X-Spam_score: -4.0 X-Spam_bar: ---- X-Spam_report: (-4.0 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686850616287100005 Cortex A7 CPUs with an FPU implementing VFPv4 without NEON support have 16 64-bit FPU registers and not 32 registers. Let users set the number of VFP registers with a CPU property. The primary use case of this property is for the Cortex A7 of the Aspeed AST2600 SoC. Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Reviewed-by: Peter Maydell Signed-off-by: C=C3=A9dric Le Goater --- target/arm/cpu.h | 2 ++ hw/arm/aspeed_ast2600.c | 2 ++ target/arm/cpu.c | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 36 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 36c608f0e6e1..af0119addfb6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -924,6 +924,8 @@ struct ArchCPU { bool has_pmu; /* CPU has VFP */ bool has_vfp; + /* CPU has 32 VFP registers */ + bool has_vfp_d32; /* CPU has Neon */ bool has_neon; /* CPU has M-profile DSP extension */ diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 1bf12461481c..a8b3a8065a11 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -316,6 +316,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) &error_abort); object_property_set_bool(OBJECT(&s->cpu[i]), "neon", false, &error_abort); + object_property_set_bool(OBJECT(&s->cpu[i]), "vfp-d32", false, + &error_abort); object_property_set_link(OBJECT(&s->cpu[i]), "memory", OBJECT(s->memory), &error_abort); =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4d5bb57f0797..353fc4856739 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1277,6 +1277,9 @@ static Property arm_cpu_cfgend_property =3D static Property arm_cpu_has_vfp_property =3D DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true); =20 +static Property arm_cpu_has_vfp_d32_property =3D + DEFINE_PROP_BOOL("vfp-d32", ARMCPU, has_vfp_d32, true); + static Property arm_cpu_has_neon_property =3D DEFINE_PROP_BOOL("neon", ARMCPU, has_neon, true); =20 @@ -1408,6 +1411,22 @@ void arm_cpu_post_init(Object *obj) } } =20 + if (cpu->has_vfp && cpu_isar_feature(aa32_simd_r32, cpu)) { + cpu->has_vfp_d32 =3D true; + if (!kvm_enabled()) { + /* + * The permitted values of the SIMDReg bits [3:0] on + * Armv8-A are either 0b0000 and 0b0010. On such CPUs, + * make sure that has_vfp_d32 can not be set to false. + */ + if (!(arm_feature(&cpu->env, ARM_FEATURE_V8) && + !arm_feature(&cpu->env, ARM_FEATURE_M))) { + qdev_property_add_static(DEVICE(obj), + &arm_cpu_has_vfp_d32_property); + } + } + } + if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { cpu->has_neon =3D true; if (!kvm_enabled()) { @@ -1674,6 +1693,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) return; } =20 + if (cpu->has_vfp_d32 !=3D cpu->has_neon) { + error_setg(errp, "ARM CPUs must have both VFP-D32 and Neon or neit= her"); + return; + } + + if (!cpu->has_vfp_d32) { + uint32_t u; + + u =3D cpu->isar.mvfr0; + u =3D FIELD_DP32(u, MVFR0, SIMDREG, 1); /* 16 registers */ + cpu->isar.mvfr0 =3D u; + } + if (!cpu->has_vfp) { uint64_t t; uint32_t u; --=20 2.40.1