From nobody Sun May 19 07:12:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1686839124602483.34989567332093; Thu, 15 Jun 2023 07:25:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q9ntm-0003BV-BU; Thu, 15 Jun 2023 10:24:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9nti-0003Aw-4g; Thu, 15 Jun 2023 10:24:26 -0400 Received: from viti.kaiser.cx ([2a01:238:43fe:e600:cd0c:bd4a:7a3:8e9f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q9ntg-00086e-JY; Thu, 15 Jun 2023 10:24:25 -0400 Received: from [94.118.66.68] (helo=martin-debian-2.paytec.ch) by viti.kaiser.cx with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1q9ntX-0001T5-QI; Thu, 15 Jun 2023 16:24:16 +0200 From: Martin Kaiser To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Martin Kaiser Subject: [PATCH v3] imx_serial: set wake bit when we receive a data byte Date: Thu, 15 Jun 2023 15:22:56 +0100 Message-Id: <20230615142256.1142849-1-martin@kaiser.cx> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230608154129.133169-1-martin@kaiser.cx> References: <20230608154129.133169-1-martin@kaiser.cx> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2a01:238:43fe:e600:cd0c:bd4a:7a3:8e9f; envelope-from=postmaster@kaiser.cx; helo=viti.kaiser.cx X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1686839126747100001 The Linux kernel added a flood check for RX data recently in commit 496a4471b7c3 ("serial: imx: work-around for hardware RX flood"). This check uses the wake bit in the UART status register 2. The wake bit indicates that the receiver detected a start bit on the RX line. If the kernel sees a number of RX interrupts without the wake bit being set, it treats this as spurious data and resets the UART port. imx_serial does never set the wake bit and triggers the kernel's flood check. This patch adds support for the wake bit. wake is set when we receive a new character (it's not set for break events). It seems that wake is cleared by the kernel driver, the hardware does not have to clear it automatically after data was read. The wake bit can be configured as an interrupt source. Support this mechanism as well. Co-developed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Martin Kaiser --- v3: - fix some spelling mistakes in the commit message - add Philippe's Reviewed-by v2: - support interrupts from wake - clean up the commit message hw/char/imx_serial.c | 5 ++++- include/hw/char/imx_serial.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index ee1375e26d..1b75a89588 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -80,7 +80,7 @@ static void imx_update(IMXSerialState *s) * TCEN and TXDC are both bit 3 * RDR and DREN are both bit 0 */ - mask |=3D s->ucr4 & (UCR4_TCEN | UCR4_DREN); + mask |=3D s->ucr4 & (UCR4_WKEN | UCR4_TCEN | UCR4_DREN); =20 usr2 =3D s->usr2 & mask; =20 @@ -321,6 +321,9 @@ static void imx_put_data(void *opaque, uint32_t value) =20 static void imx_receive(void *opaque, const uint8_t *buf, int size) { + IMXSerialState *s =3D (IMXSerialState *)opaque; + + s->usr2 |=3D USR2_WAKE; imx_put_data(opaque, *buf); } =20 diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h index 91c9894ad5..b823f94519 100644 --- a/include/hw/char/imx_serial.h +++ b/include/hw/char/imx_serial.h @@ -71,6 +71,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL) =20 #define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */ #define UCR4_TCEN BIT(3) /* TX complete interrupt enable */ +#define UCR4_WKEN BIT(7) /* WAKE interrupt enable */ =20 #define UTS1_TXEMPTY (1<<6) #define UTS1_RXEMPTY (1<<5) --=20 2.30.2